[edk2-devel] Side effects of enabling PML5 in EFI

[Pedro Falcato]

Hi all,

(+CC people vaguely related to the EFI spec, the PML5 implementation
and kernel EFI boot code)

As a result of the latest 5-level paging patches, I've been looking
into how tiano supports PML5.
This raised a question: Doesn't enabling PML5 in-firmware break
compatibility with non-PML5-aware bootloaders and kernels?

>From an architectural point of view:
- PML5 is enabled in CR4.LA57, but may only be toggled when not in
IA32e mode (so, only in 32-bit)
- Trying to mindlessly write to CR4 will #GP, and loading a 4-level
page tables will crash with probable page faults or #GPs

>From an EFI spec point of view:
- Whereas other architectures (arm64 for instance) specify the MMU
state in detail, the x64 bits do not specify anything beyond "Paging
enabled" (see 2.3.4). Which pre-PML5, was obviously well defined.
- When under boot services, this is likely not a problem as page
tables are owned by boot services. Unless they touch them as defined
in "2.3.4.3. Enabling Paging or Alternate Translations in an
Application", which may run into problems.

>From an OS kernel/bootloader point of view:
- A PML5 aware kernel/bootloader will likely correctly identify the
PML5 capability and enable LA57, load 5-level page tables. As such,
this scenario always works.
- A non-PML5-aware one may incorrectly overwrite LA57 (and #GP), or
just load a 4-level paging structure into CR3, and thus disastrously
crash.

So, how is any of this supposed to work?

-- 
Pedro


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