[edk2-devel] [PATCH v6 3/5] MdePkg: Implement RISC-V Cache Management Operations

[Laszlo Ersek]

On 10/21/23 19:33, Dhaval Sharma wrote:
> Implement Cache Management Operations (CMO) defined by
> RISC-V spec https://github.com/riscv/riscv-CMOs.
> 
> Notes:
> 1. CMO only supports block based Operations. Meaning cache
>    flush/invd/clean Operations are not available for the entire
>    range. In that case we fallback on fence.i instructions.
> 2. Operations are implemented using Opcodes to make them compiler
>    independent. binutils 2.39+ compilers support CMO instructions.
> 
> Test:
> 1. Ensured correct instructions are refelecting in asm
> 2. Not able to verify actual instruction in HW as Qemu ignores
>    any actual cache operations.
> 
> Cc: Michael D Kinney <michael.d.kinney at intel.com>
> Cc: Liming Gao <gaoliming at byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu at intel.com>
> Cc: Sunil V L <sunilvl at ventanamicro.com>
> Cc: Daniel Schaefer <git at danielschaefer.me>
> Cc: Laszlo Ersek <lersek at redhat.com>
> 
> Signed-off-by: Dhaval Sharma <dhaval at rivosinc.com>
> ---
> 
> Notes:
>     V1:
>     - Implement Cache management instructions in Baselib
> 
>  MdePkg/Library/BaseLib/BaseLib.inf                                |  2 +-
>  MdePkg/Include/Library/BaseLib.h                                  | 33 ++++++++++++++++++++
>  MdePkg/Include/RiscV64/RiscVasm.inc                               | 19 +++++++++++
>  MdePkg/Library/BaseLib/RiscV64/{FlushCache.S => RiscVCacheMgmt.S} | 17 ++++++++++
>  4 files changed, 70 insertions(+), 1 deletion(-)
> 
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
> index 03c7b02e828b..53389389448c 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -400,7 +400,7 @@ [Sources.RISCV64]
>    RiscV64/RiscVCpuBreakpoint.S      | GCC
>    RiscV64/RiscVCpuPause.S           | GCC
>    RiscV64/RiscVInterrupt.S          | GCC
> -  RiscV64/FlushCache.S              | GCC
> +  RiscV64/RiscVCacheMgmt.S          | GCC
>    RiscV64/CpuScratch.S              | GCC
>    RiscV64/ReadTimer.S               | GCC
>    RiscV64/RiscVMmu.S                | GCC
> diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
> index d4b56a9601da..60d60602b876 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -226,6 +226,39 @@ RiscVInvalidateDataCacheAsmFence (
>    VOID
>    );
>  
> +/**
> +  RISC-V flush cache block. Atomically perform a clean operation
> +  followed by an invalidate operation
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVCpuCacheFlushAsmCbo (
> +  IN UINTN
> +  );
> +
> +/**
> +Perform a write transfer to another cache or to memory if the
> +data in the copy of the cache block have been modified by a store
> +operation
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVCpuCacheCleanAsmCbo (
> +  IN UINTN
> +  );
> +
> +/**
> +Deallocate the copy of the cache block
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVCpuCacheInvalAsmCbo (
> +  IN UINTN
> +  );
> +
>  #endif // defined (MDE_CPU_RISCV64)
>  
>  #if defined (MDE_CPU_LOONGARCH64)
> diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc b/MdePkg/Include/RiscV64/RiscVasm.inc
> new file mode 100644
> index 000000000000..6f418232d507
> --- /dev/null
> +++ b/MdePkg/Include/RiscV64/RiscVasm.inc
> @@ -0,0 +1,19 @@
> +/*
> + *
> + * RISC-V cache operation encoding.
> + * Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
> + * SPDX-License-Identifier: BSD-2-Clause-Patent
> + *
> + */
> +
> +.macro RISCVCBOFLSH
> +    .word 0x25200f
> +.endm
> +
> +.macro RISCVCBOINVD
> +    .word 0x05200f
> +.endm
> +
> +.macro RISCVCBOCLEN
> +    .word 0x15200f
> +.endm
> diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
> similarity index 57%
> rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
> index e0eea0b5fb25..fe3943ae3f7c 100644
> --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
> @@ -3,10 +3,12 @@
>  // RISC-V cache operation.
>  //
>  // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +// Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
>  //
>  // SPDX-License-Identifier: BSD-2-Clause-Patent
>  //
>  //------------------------------------------------------------------------------
> +.include "RiscVasm.inc"
>  
>  .align 3
>  ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
> @@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheAsmFence):
>  ASM_PFX(RiscVInvalidateDataCacheAsmFence):
>      fence
>      ret
> +
> +ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushAsmCbo)
> +ASM_PFX (RiscVCpuCacheFlushAsmCbo):
> +  RISCVCBOFLSH
> +  ret
> +
> +ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanAsmCbo)
> +ASM_PFX (RiscVCpuCacheCleanAsmCbo):
> +  RISCVCBOCLEN
> +  ret
> +
> +ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalAsmCbo)
> +ASM_PFX (RiscVCpuCacheInvalAsmCbo):
> +  RISCVCBOINVD
> +  ret

I've not validated the assembly insn encodings.

I also think that *FLSH, *CLEN, and *INVD could just as well be FLUSH,
CLEAN, and INVALIDATE.

But those are really minor IMO.

Reviewed-by: Laszlo Ersek <lersek at redhat.com>



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