[edk2-devel] [PATCH v7 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
Dhaval Sharma
dhaval at rivosinc.com
Sun Oct 29 14:46:09 UTC 2023
The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.
Cc: Michael D Kinney <michael.d.kinney at intel.com>
Cc: Liming Gao <gaoliming at byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu at intel.com>
Cc: Laszlo Ersek <lersek at redhat.com>
Signed-off-by: Dhaval Sharma <dhaval at rivosinc.com>
Reviewed-by: Laszlo Ersek <lersek at redhat.com>
---
Notes:
V7:
- Added RB tag
V6:
- Move cache management function declaration in baselib where it belongs
MdePkg/Include/Library/BaseLib.h | 20 ++++++++++++++++++++
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 --------------------
2 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 5d7067ee854e..7142bbfa42f2 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt (
VOID
);
+/**
+ RISC-V invalidate instruction cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateInstCacheAsm (
+ VOID
+ );
+
+/**
+ RISC-V invalidate data cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateDataCacheAsm (
+ VOID
+ );
+
#endif // defined (MDE_CPU_RISCV64)
#if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d08fb9f193ca..d5efcf49a4bf 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -10,26 +10,6 @@
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
-/**
- RISC-V invalidate instruction cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateInstCacheAsm (
- VOID
- );
-
-/**
- RISC-V invalidate data cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateDataCacheAsm (
- VOID
- );
-
/**
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
--
2.39.2
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