[edk2-devel] [PATCH 05/16] UefiCpuPkg/MtrrUnitTest: Update test to cover no-fixed-mtrr cases.
Yuanhao Xie
yuanhao.xie at intel.com
Wed Sep 13 04:26:28 UTC 2023
From: Ray Ni <ray.ni at intel.com>
Signed-off-by: Ray Ni <ray.ni at intel.com>
Cc: Eric Dong <eric.dong at intel.com>
Cc: Rahul Kumar <rahul1.kumar at intel.com>
Cc: Gerd Hoffmann <kraxel at redhat.com>
---
UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c | 43 ++++++++++++++++++++++++-------------------
UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c | 24 +++++++++++++++---------
2 files changed, 39 insertions(+), 28 deletions(-)
diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
index 293f3bc7b5..13cebee32b 100644
--- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
+++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
@@ -13,25 +13,30 @@ STATIC CONST MTRR_LIB_SYSTEM_PARAMETER mDefaultSystemParameter = {
};
STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = {
- { 38, TRUE, TRUE, CacheUncacheable, 12 },
- { 38, TRUE, TRUE, CacheWriteBack, 12 },
- { 38, TRUE, TRUE, CacheWriteThrough, 12 },
- { 38, TRUE, TRUE, CacheWriteProtected, 12 },
- { 38, TRUE, TRUE, CacheWriteCombining, 12 },
-
- { 42, TRUE, TRUE, CacheUncacheable, 12 },
- { 42, TRUE, TRUE, CacheWriteBack, 12 },
- { 42, TRUE, TRUE, CacheWriteThrough, 12 },
- { 42, TRUE, TRUE, CacheWriteProtected, 12 },
- { 42, TRUE, TRUE, CacheWriteCombining, 12 },
-
- { 48, TRUE, TRUE, CacheUncacheable, 12 },
- { 48, TRUE, TRUE, CacheWriteBack, 12 },
- { 48, TRUE, TRUE, CacheWriteThrough, 12 },
- { 48, TRUE, TRUE, CacheWriteProtected, 12 },
- { 48, TRUE, TRUE, CacheWriteCombining, 12 },
-
- { 48, TRUE, TRUE, CacheWriteBack, 12, 7}, // 7 bits for MKTME
+ { 38, TRUE, TRUE, CacheUncacheable, 12 },
+ { 38, TRUE, TRUE, CacheWriteBack, 12 },
+ { 38, TRUE, TRUE, CacheWriteThrough, 12 },
+ { 38, TRUE, TRUE, CacheWriteProtected, 12 },
+ { 38, TRUE, TRUE, CacheWriteCombining, 12 },
+
+ { 42, TRUE, TRUE, CacheUncacheable, 12 },
+ { 42, TRUE, TRUE, CacheWriteBack, 12 },
+ { 42, TRUE, TRUE, CacheWriteThrough, 12 },
+ { 42, TRUE, TRUE, CacheWriteProtected, 12 },
+ { 42, TRUE, TRUE, CacheWriteCombining, 12 },
+
+ { 48, TRUE, TRUE, CacheUncacheable, 12 },
+ { 48, TRUE, TRUE, CacheWriteBack, 12 },
+ { 48, TRUE, TRUE, CacheWriteThrough, 12 },
+ { 48, TRUE, TRUE, CacheWriteProtected, 12 },
+ { 48, TRUE, TRUE, CacheWriteCombining, 12 },
+
+ { 48, TRUE, FALSE, CacheUncacheable, 12 },
+ { 48, TRUE, FALSE, CacheWriteBack, 12 },
+ { 48, TRUE, FALSE, CacheWriteThrough, 12 },
+ { 48, TRUE, FALSE, CacheWriteProtected, 12 },
+ { 48, TRUE, FALSE, CacheWriteCombining, 12 },
+ { 48, TRUE, TRUE, CacheWriteBack, 12, 7}, // 7 bits for MKTME
};
UINT32 mFixedMtrrsIndex[] = {
diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c
index ba1de10034..7df5b9745f 100644
--- a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c
+++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c
@@ -43,7 +43,6 @@ Rand (
if (mRandomInput) {
return rand ();
} else {
- DEBUG ((DEBUG_INFO, "random: %d\n", mNumberIndex));
return mNumbers[mNumberIndex++ % (mNumberCount - 1)];
}
}
@@ -236,8 +235,11 @@ UnitTestMtrrLibAsmReadMsr64 (
{
UINT32 Index;
+ UT_ASSERT_EQUAL (mCpuidVersionInfoEdx.Bits.MTRR, 1);
+
for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) {
if (MsrIndex == mFixedMtrrsIndex[Index]) {
+ UT_ASSERT_EQUAL (mMtrrCapMsr.Bits.FIX, 1);
return mFixedMtrrsValue[Index];
}
}
@@ -245,6 +247,7 @@ UnitTestMtrrLibAsmReadMsr64 (
if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&
(MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))
{
+ UT_ASSERT_TRUE (((MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1) < mMtrrCapMsr.Bits.VCNT);
if (MsrIndex % 2 == 0) {
Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;
return mVariableMtrrsPhysBase[Index].Uint64;
@@ -299,8 +302,11 @@ UnitTestMtrrLibAsmWriteMsr64 (
{
UINT32 Index;
+ UT_ASSERT_EQUAL (mCpuidVersionInfoEdx.Bits.MTRR, 1);
+
for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) {
if (MsrIndex == mFixedMtrrsIndex[Index]) {
+ UT_ASSERT_EQUAL (mMtrrCapMsr.Bits.FIX, 1);
mFixedMtrrsValue[Index] = Value;
return Value;
}
@@ -309,6 +315,7 @@ UnitTestMtrrLibAsmWriteMsr64 (
if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&
(MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))
{
+ UT_ASSERT_TRUE (((MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1) < mMtrrCapMsr.Bits.VCNT);
if (MsrIndex % 2 == 0) {
Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;
mVariableMtrrsPhysBase[Index].Uint64 = Value;
@@ -321,6 +328,10 @@ UnitTestMtrrLibAsmWriteMsr64 (
}
if (MsrIndex == MSR_IA32_MTRR_DEF_TYPE) {
+ if (((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&Value)->Bits.FE == 1) {
+ UT_ASSERT_EQUAL (mMtrrCapMsr.Bits.FIX, 1);
+ }
+
mDefTypeMsr.Uint64 = Value;
return Value;
}
@@ -353,17 +364,12 @@ InitializeMtrrRegs (
SetMem (mFixedMtrrsValue, sizeof (mFixedMtrrsValue), SystemParameter->DefaultCacheType);
for (Index = 0; Index < ARRAY_SIZE (mVariableMtrrsPhysBase); Index++) {
- mVariableMtrrsPhysBase[Index].Uint64 = 0;
- mVariableMtrrsPhysBase[Index].Bits.Type = SystemParameter->DefaultCacheType;
- mVariableMtrrsPhysBase[Index].Bits.Reserved1 = 0;
-
- mVariableMtrrsPhysMask[Index].Uint64 = 0;
- mVariableMtrrsPhysMask[Index].Bits.V = 0;
- mVariableMtrrsPhysMask[Index].Bits.Reserved1 = 0;
+ mVariableMtrrsPhysBase[Index].Uint64 = 0;
+ mVariableMtrrsPhysMask[Index].Uint64 = 0;
}
mDefTypeMsr.Bits.E = 1;
- mDefTypeMsr.Bits.FE = 1;
+ mDefTypeMsr.Bits.FE = 0;
mDefTypeMsr.Bits.Type = SystemParameter->DefaultCacheType;
mDefTypeMsr.Bits.Reserved1 = 0;
mDefTypeMsr.Bits.Reserved2 = 0;
--
2.36.1.windows.1
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