[edk2-devel] [PATCH 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru
Saloni Kasbekar
saloni.kasbekar at intel.com
Wed Sep 13 22:13:59 UTC 2023
Adds the following modules:
- AdlCpu/CpuPcieRp
- AdlCpu/Include
- AdlCpu/IncludePrivate
- AdlCpu/LibraryPrivate
- AdlCpu/PeiReportCpuHob
- AdlCpu DSCs
Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
Cc: Rosen Chuang <rosen.chuang at intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar at intel.com>
---
.../Fru/AdlCpu/CommonLib.dsc | 9 +
.../CpuPcieInfoFruLib.c | 87 ++++++++
.../PeiDxeSmmCpuPcieInfoFruLib.inf | 39 ++++
.../AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc | 8 +
.../Fru/AdlCpu/Include/CpuGenInfo.h | 42 ++++
.../Include/Library/CpuPcieInfoFruLib.h | 45 ++++
.../Include/Register/SaRegsHostBridge.h | 64 ++++++
.../AdlCpu/IncludePrivate/CpuGenInfoFruLib.h | 176 ++++++++++++++++
.../AdlCpu/IncludePrivate/Register/IgdRegs.h | 34 +++
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.c | 193 ++++++++++++++++++
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf | 29 +++
.../PeiReportCpuHobLib/PeiReportCpuHobLib.c | 22 ++
.../PeiReportCpuHobLib/PeiReportCpuHobLib.inf | 26 +++
13 files changed, 774 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
new file mode 100644
index 0000000000..35a3cce916
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
@@ -0,0 +1,9 @@
+## @file
+# Component description file for the AlderLake CPU Common FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
+CpuInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
new file mode 100644
index 0000000000..277b73fe67
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
@@ -0,0 +1,87 @@
+/** @file
+ CPU PCIe information library.
+
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Register/SaRegsHostBridge.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <CpuPcieInfo.h>
+
+/**
+ Get Maximum CPU Pcie Root Port Number
+
+ @retval Maximum CPU Pcie Root Port Number
+**/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ )
+{
+ switch (GetCpuSku ()) {
+ case EnumCpuUlt:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+ case EnumCpuUlx:
+ return CPU_PCIE_ULX_MAX_ROOT_PORT;
+ default:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+ }
+}
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ )
+{
+ if (RpNumber > GetMaxCpuPciePortNum ()) {
+ DEBUG ((DEBUG_ERROR, "GetCpuPcieRpDevFun invalid RpNumber %x", RpNumber));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ switch (RpNumber) {
+ case 0:
+ *RpDev = 6;
+ *RpFun = 0;
+ break;
+ case 1:
+ *RpDev = 1;
+ *RpFun = 0;
+ break;
+ case 2:
+ if (GetCpuSku () == EnumCpuTrad) {
+ *RpDev = 1;
+ *RpFun = 1;
+ } else {
+ *RpDev = 6;
+ *RpFun = 2;
+ }
+ break;
+ default:
+ *RpDev = 6;
+ *RpFun = 0;
+ break;
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
new file mode 100644
index 0000000000..f850f1a5f1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
@@ -0,0 +1,39 @@
+## @file
+# CPU PCIe information library for TigerLake PCH.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmCpuPcieInfoFruLib
+FILE_GUID = 59CA5352-ED46-4449-BF1C-0D0074C4D5B1
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuPcieInfoFruLib
+
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+PrintLib
+PciSegmentLib
+PchPcrLib
+PmcPrivateLib
+PcdLib
+ConfigBlockLib
+CpuPlatformLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+CpuPcieInfoFruLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
new file mode 100644
index 0000000000..644230484e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
@@ -0,0 +1,8 @@
+# @file
+# Component description file for the AlderLake CPU DXE FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+DxeGraphicsPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
+DxeIgdOpRegionInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
new file mode 100644
index 0000000000..482316829d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
@@ -0,0 +1,42 @@
+/** @file
+ Header file for Cpu Information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_GEN_INFO_H_
+#define _CPU_GEN_INFO_H_
+
+#include <CpuRegs.h>
+
+//
+// Processor Definitions
+//
+#define CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE 0x000906A0
+
+///
+/// Enums for CPU Stepping IDs
+///
+typedef enum {
+
+ ///
+ /// AlderLake Mobile Steppings(ULT)
+ ///
+ EnumAdlJ0 = 0,
+ EnumAdlK0 = 2,
+ EnumAdlL0 = 3,
+
+ ///
+ /// AlderLake Mobile Steppings(ULX)
+ ///
+ EnumAdlQ0 = 1,
+ EnumAdlR0 = 4,
+ EnumAdlS0 = 5,
+
+
+ ///
+ /// Max Stepping
+ ///
+ EnumCpuSteppingMax = CPUID_FULL_STEPPING
+} CPU_STEPPING;
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
new file mode 100644
index 0000000000..9dafa98631
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
@@ -0,0 +1,45 @@
+/** @file
+ Header file for CpuPcieInfoFruLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INFO_FRU_LIB_H_
+#define _CPU_PCIE_INFO_FRU_LIB_H_
+
+#include <CpuPcieInfo.h>
+
+#define CPU_PCIE_MAX_ROOT_PORTS 4
+#define CPU_PCIE_MAX_CONTROLLERS 3
+
+#define CPU_PCIE_ULT_MAX_ROOT_PORT 3
+#define CPU_PCIE_ULX_MAX_ROOT_PORT 1
+
+/**
+ Get CPU Maximum Pcie Root Port Number
+
+ @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number
+**/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ );
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+#endif // _CPU_PCIE_INFO_FRU_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
new file mode 100644
index 0000000000..be4bba3283
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
@@ -0,0 +1,64 @@
+/** @file
+ Register names for Host Bridge block
+ <b>Conventions</b>:
+ - Prefixes:
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+ - In general, SA registers are denoted by "_SA_" in register names
+ - Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SA_REGS_HOST_BRIDGE_H_
+#define _SA_REGS_HOST_BRIDGE_H_
+
+#define SA_SEG_NUM 0x00
+//
+// DEVICE 0 (Memory Controller Hub)
+//
+#define SA_MC_BUS 0x00
+#define SA_MC_DEV 0x00
+#define SA_MC_FUN 0x00
+#define R_SA_MC_DEVICE_ID 0x02
+
+//
+// AlderLake CPU Mobile SA Device IDs B0:D0:F0
+//
+#define V_SA_DEVICE_ID_MB_ULT_1 0x4641 ///< AlderLake P (6+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_2 0x4649 ///< AlderLake P (6+4(f)+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_3 0x4621 ///< AlderLake P (4(f)+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_4 0x4609 ///< AlderLake P (2(f)+4(f)+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_5 0x4601 ///< AlderLake P (2+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_6 0x4661 ///< AlderLake P (6+8+2) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_7 0x4629 ///< AlderLake P (4+4+1) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_8 0x4619 ///< AlderLake P (1+4+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_9 0x4659 ///< AlderLake P (1+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_10 0x4645 ///< AlderLake P (6+6+GT) SA DID
+///
+/// Description:
+/// The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit is set.
+///
+#define R_SA_SMRAMC (0x88)
+
+///
+/// Description:
+/// This register contains the Top of low memory address.
+///
+#define R_SA_TOLUD (0xbc)
+///
+/// Description of TOLUD (20:31)
+/// This register contains bits 31 to 20 of an address one byte above the maximum DRAM memory below 4G that is usable by the operating system. Address bits 31 down to 20 programmed to 01h implies a minimum memory size of 1MB. Configuration software must set this value to the smaller of the following 2 choices: maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register.
+/// The Top of Low Usable DRAM is the lowest address above both Graphics Stolen memory and Tseg. BIOS determines the base of Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by Tseg size to determine base of Tseg. All the Bits in this register are locked in LT mode.
+/// This register must be 1MB aligned when reclaim is enabled.
+///
+#define B_SA_TOLUD_TOLUD_MASK (0xfff00000)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
new file mode 100644
index 0000000000..c3597f8459
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
@@ -0,0 +1,176 @@
+ /** @file
+ This file contains Cpu Information for specific generation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_GEN_INFO_FRU_LIB_H_
+#define _CPU_GEN_INFO_FRU_LIB_H_
+#include <CpuRegs.h>
+#include <CpuGenInfo.h>
+#include <Register/CommonMsr.h>
+
+///
+/// Used to identify the CPU used for programming with the VR override table
+///
+typedef enum {
+ EnumUnknownCpuId = 0,
+ EnumMinCpuId = 1,
+
+ ///
+ /// ADL S
+ ///
+ EnumAdlS35Watt881fCpuId = 0x1,
+ EnumAdlS65Watt881fCpuId = 0x3,
+ EnumAdlS125Watt881fCpuId = 0x4,
+ EnumAdlS150Watt881fCpuId = 0x5,
+ EnumAdlS35Watt841fCpuId = 0x6,
+ EnumAdlS65Watt841fCpuId = 0x8,
+ EnumAdlS125Watt841fCpuId = 0x9,
+ EnumAdlS35Watt641fCpuId = 0xA,
+ EnumAdlS65Watt641fCpuId = 0xB,
+ EnumAdlS125Watt641fCpuId = 0xC,
+ EnumAdlS35Watt681fCpuId = 0xD,
+ EnumAdlS35Watt801fCpuId = 0xF,
+ EnumAdlS65Watt801fCpuId = 0x10,
+ EnumAdlS35Watt401fCpuId = 0x12,
+ EnumAdlS65Watt401fCpuId = 0x13,
+ EnumAdlS35Watt601fCpuId = 0x15,
+ EnumAdlS65Watt601fCpuId = 0x16,
+ EnumAdlS35Watt201fCpuId = 0x17,
+ EnumAdlS46Watt201fCpuId = 0x18,
+ EnumAdlS65Watt201fCpuId = 0x19,
+ EnumAdlS58Watt401fCpuId = 0x1A,
+ EnumAdlS60Watt401fCpuId = 0x1B,
+ EnumAdlS63Watt401fCpuId = 0x1C,
+ EnumAdlS65WattBga881fCpuId = 0x1D,
+ EnumAdlS65WattBga841fCpuId = 0x1E,
+ EnumAdlS65WattBga441fCpuId = 0x1F,
+ EnumAdlS65WattBga601fCpuId = 0x20,
+ EnumAdlS65WattBga681fCpuId = 0x21,
+ EnumAdlS65WattBga401fCpuId = 0x22,
+ EnumAdlS55WattHBga881fCpuId = 0x23,
+ EnumAdlS55WattHBga681fCpuId = 0x24,
+ EnumAdlS55WattHBga481fCpuId = 0x25,
+ EnumAdlS55WattHBga441fCpuId = 0x26,
+ EnumAdlSMaxCpuId = EnumAdlS55WattHBga441fCpuId,
+
+ ///
+ /// ADL P
+ ///
+ EnumAdlP15Watt282fCpuId = 0x30,
+ EnumAdlP28Watt482fCpuId = 0x31,
+ EnumAdlP28Watt682fCpuId = 0x32,
+ EnumAdlP45Watt682fCpuId = 0x35,
+ EnumAdlP15Watt142fCpuId = 0x36,
+ EnumAdlP15Watt242fCpuId = 0x37,
+ EnumAdlP45Watt482fCpuId = 0x38,
+ EnumAdlP45Watt442fCpuId = 0x39,
+ EnumAdlP28Watt442fCpuId = 0x3A,
+ EnumAdlP28Watt282fCpuId = 0x3B,
+ EnumAdlP28Watt242fCpuId = 0x3C,
+ EnumAdlP28Watt142fCpuId = 0x3D,
+ EnumAdlP45Watt242fCpuId = 0x3E,
+ EnumAdlP28Watt182fCpuId = 0x3F,
+ EnumAdlP28Watt662fCpuId = 0x40,
+ EnumAdlP28Watt642fCpuId = 0x41,
+ EnumAdlP45Watt642fCpuId = 0x42,
+ EnumAdlPMaxCpuId = EnumAdlP45Watt642fCpuId,
+
+ ///
+ /// ADL M
+ ///
+ EnumAdlM7Watt182fPmicCpuId = 0x50,
+ EnumAdlM5Watt182fPmicCpuId = 0x51,
+ EnumAdlM5Watt142fPmicCpuId = 0x52,
+ EnumAdlM7Watt142fPmicCpuId = 0x53,
+ EnumAdlM7Watt242fHybDiscreteCpuId = 0x54,
+ EnumAdlM7Watt282fHybDiscreteCpuId = 0x55,
+ EnumAdlM7Watt182fHybDiscreteCpuId = 0x56,
+ EnumAdlM9Watt282fHybDiscreteCpuId = 0x57,
+ EnumAdlM9Watt142fHybDiscreteCpuId = 0x58,
+ EnumAdlM9Watt242fHybDiscreteCpuId = 0x59,
+ EnumAdlM12Watt142fHybDiscreteCpuId = 0x60,
+ EnumAdlM12Watt242fHybDiscreteCpuId = 0x61,
+ EnumAdlM12Watt182fHybDiscreteCpuId = 0x62,
+ EnumAdlM12Watt282fHybDiscreteCpuId = 0x63,
+ EnumAdlMMaxCpuId = 0x6F,
+
+
+ ///
+ /// RPL S
+ ///
+ EnumRplS35Watt8161fCpuId = 0x80,
+ EnumRplS65Watt8161fCpuId = 0x81,
+ EnumRplS95Watt8161fCpuId = 0x82,
+ EnumRplS125Watt8161fCpuId = 0x83,
+ EnumRplS150Watt8161fCpuId = 0x84,
+
+ EnumRplS35Watt881fCpuId = 0x85,
+ EnumRplS65Watt881fCpuId = 0x86,
+ EnumRplS125Watt881fCpuId = 0x87,
+
+ EnumRplS125Watt681fCpuId = 0x88,
+
+ EnumRplS65Watt641fCpuId = 0x89,
+ EnumRplS125Watt641fCpuId = 0x8A,
+
+ EnumRplS80Watt801fCpuId = 0x8B,
+ EnumRplS95Watt801fCpuId = 0x8C,
+
+
+
+ ///
+ /// RPL HX S BGA
+ ///
+ EnumRplHx55WattSBga8161fCpuId = 0xA0,
+
+ EnumRplHx55WattSBga8121fCpuId = 0xA2,
+
+ EnumRplHx55WattSBga881fCpuId = 0xA4,
+
+
+
+ EnumRplHx55WattSBga681fCpuId = 0xAA,
+
+ EnumRplHx55WattSBga641fCpuId = 0xAB,
+
+ EnumRplHx55WattSBga441fCpuId = 0xAC,
+
+ EnumRplSMaxCpuId = EnumRplHx55WattSBga441fCpuId,
+
+ ///
+ /// RPL2 S
+ ///
+ EnumRplS35Watt681fCpuId2 = 0xE0,
+ EnumRplS65Watt681fCpuId2 = 0xE1,
+
+ EnumRplS35Watt641fCpuId2 = 0xE2,
+ EnumRplS65Watt641fCpuId2 = 0xE3,
+
+ EnumRplS35Watt401fCpuId2 = 0xE4,
+ EnumRplS58Watt401fCpuId2 = 0xE5,
+ EnumRplS60Watt401fCpuId2 = 0xE6,
+ EnumRplS65Watt401fCpuId2 = 0xE7,
+
+ EnumRplS35Watt201fCpuId2 = 0xE8,
+ EnumRplS46Watt201fCpuId2 = 0xE9,
+ EnumRplS65Watt201fCpuId2 = 0xEA,
+
+ EnumRplS65Watt601fCpuId2 = 0xEB,
+
+ ///
+ /// RPL2 HX S BGA
+ ///
+ EnumRplHx55WattSBga881fCpuId2 = 0xF0,
+ EnumRplHx55WattSBga681fCpuId2 = 0xF1,
+ EnumRplHx55WattSBga641fCpuId2 = 0xF2,
+ EnumRplHx55WattSBga481fCpuId2 = 0xF3,
+ EnumRplHx55WattSBga441fCpuId2 = 0xF4,
+
+ EnumRplSMaxCpuId2 = EnumRplHx55WattSBga441fCpuId2,
+
+
+} CPU_IDENTIFIER;
+
+#endif // _CPU_GEN_INFO_FRU_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
new file mode 100644
index 0000000000..289b293b32
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
@@ -0,0 +1,34 @@
+/** @file
+ Register names for IGD block
+ <b>Conventions</b>:
+ - Prefixes:
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+ - In general, SA registers are denoted by "_SA_" in register names
+ - Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _IGD_REGS_H_
+#define _IGD_REGS_H_
+
+///
+/// Device 2 Register Equates
+///
+//
+// The following equates must be reviewed and revised when the specification is ready.
+//
+#define IGD_BUS_NUM 0x00
+#define IGD_DEV_NUM 0x02
+#define IGD_FUN_NUM 0x00
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
new file mode 100644
index 0000000000..31ef5755a4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
@@ -0,0 +1,193 @@
+/** @file
+ This file contains the Cpu Information for specific generation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <CpuGenInfoFruLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Register/Cpuid.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/CpuInfoFruLib.h>
+#include <Register/ArchitecturalMsr.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Register/CommonMsr.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/PcdLib.h>
+#include <Library/PchInfoLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Register/IgdRegs.h>
+
+
+STATIC CONST CHAR8 mAdlCpuFamilyString[] = "AlderLake";
+typedef struct {
+ UINT32 CPUID;
+ UINT8 CpuSku;
+ CHAR8 *String;
+} CPU_REV;
+
+typedef struct {
+ CPU_IDENTIFIER CpuIdentifier;
+ UINT8 SupportedCores;
+ UINT8 SupportedAtomCores;
+} CPU_CORE_COUNT;
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CPU_REV mProcessorRevisionTable[] = {
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlJ0, EnumCpuUlt, "J0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlK0, EnumCpuUlt, "K0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlL0, EnumCpuUlt, "L0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlQ0, EnumCpuUlt, "Q0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlR0, EnumCpuUlt, "R0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlQ0, EnumCpuUlx, "Q0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlR0, EnumCpuUlx, "R0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlS0, EnumCpuUlx, "S0"}
+};
+
+///
+/// PowerLimits Override table for all SKUs. Non-cTDP parts would have '0' data for TDP level information.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED PPM_OVERRIDE_TABLE mPowerLimitsOverrideTable[] = {
+///
+/// CpuIdentifier TDP MSR PL1 MSR PL2 TdpUp TdpUp TdpNominal TdpNominal TdpDown TdpDown MSR MSR Disablefvm
+/// PL1 PL2 PL1 PL2 PL1 PL2 PL1 PL2 PL4 PL4
+ {EnumAdlP15Watt282fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 282 ADL-P
+ {EnumAdlP15Watt142fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 142 ADL-P
+ {EnumAdlP15Watt242fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 242 ADL-P
+ {EnumAdlP28Watt282fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 282 ADL-P
+ {EnumAdlP28Watt482fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 482 ADL-P
+ {EnumAdlP28Watt682fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP28Watt142fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 142 ADL-P
+ {EnumAdlP28Watt242fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 242 ADL-P
+ {EnumAdlP28Watt442fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 442 ADL-P
+ {EnumAdlP28Watt182fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 182 ADL-P
+ {EnumAdlP28Watt642fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP28Watt662fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP45Watt682fCpuId, 4500, 4500, 11500, 0, 11500, 0, 11500, 0, 11500, 21500, 0}, /// 45W 682 ADL-P
+ {EnumAdlP45Watt242fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 242 ADL-P
+ {EnumAdlP45Watt482fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 482 ADL-P
+ {EnumAdlP45Watt442fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 442 ADL-P
+ {EnumAdlP45Watt642fCpuId, 4500, 4500, 11500, 0, 11500, 0, 11500, 0, 11500, 21500, 0}, /// 45W 642 ADL-P
+ {EnumAdlM7Watt182fPmicCpuId, 700, 700, 2400, 0, 2400, 0, 2400, 0, 2400, 5800, 0}, /// 7W 182 ADL-M PMIC
+ {EnumAdlM7Watt142fPmicCpuId, 700, 700, 2400, 0, 2400, 0, 2400, 0, 2400, 5800, 0}, /// 7W 142 ADL-M PMIC
+ {EnumAdlM5Watt142fPmicCpuId, 500, 500, 2400, 0, 2400, 0, 2400, 0, 2400, 5800, 0}, /// 5W 142 ADL-M PMIC
+ {EnumAdlM5Watt182fPmicCpuId, 500, 500, 2400, 0, 2400, 0, 2400, 0, 2400, 5800, 0}, /// 5W 182 ADL-M PMIC
+ {EnumAdlM7Watt242fHybDiscreteCpuId, 700, 700, 2900, 0, 2900, 0, 2900, 0, 2900, 6800, 0}, /// 7W 242 ADL-M Hybrid/Discrete
+ {EnumAdlM7Watt282fHybDiscreteCpuId, 700, 700, 2900, 0, 2900, 0, 2900, 0, 2900, 6800, 0}, /// 7W 282 ADL-M Hybrid/Discrete
+ {EnumAdlM7Watt182fHybDiscreteCpuId, 700, 700, 2900, 0, 2900, 0, 2900, 0, 2900, 6800, 0}, /// 7W 182 ADL-M Hybrid/Discrete
+ {EnumAdlM9Watt282fHybDiscreteCpuId, 900, 900, 2900, 0, 2900, 0, 2900, 0, 2900, 6800, 0}, /// 9W 282 ADL-M Hybrid/Discrete
+ {EnumAdlM9Watt242fHybDiscreteCpuId, 900, 900, 2900, 0, 2900, 0, 2900, 0, 2900, 6800, 0}, /// 9W 242 ADL-M Hybrid/Discrete
+ {EnumAdlM9Watt142fHybDiscreteCpuId, 900, 900, 2900, 0, 2900, 0, 2900, 0, 2900, 6800, 0}, /// 9W 142 ADL-M Hybrid/Discrete
+ {EnumAdlM12Watt142fHybDiscreteCpuId,1200, 1200, 2900, 0, 2900, 0, 2900, 0, 2900, 6800, 0}, /// 12W 142 ADL-M Hybrid/Discrete
+ {EnumAdlM12Watt242fHybDiscreteCpuId,1200, 1200, 2900, 0, 2900, 0, 2900, 0, 2900, 6800, 0}, /// 12W 242 ADL-M Hybrid/Discrete
+ {EnumAdlM12Watt182fHybDiscreteCpuId,1200, 1200, 2900, 0, 2900, 0, 2900, 0, 2900, 6800, 0}, /// 12W 182 ADL-M Hybrid/Discrete
+ {EnumAdlM12Watt282fHybDiscreteCpuId,1200, 1200, 2900, 0, 2900, 0, 2900, 0, 2900, 6800, 0}, /// 12W 282 ADL-M Hybrid/Discrete
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CPU_CORE_COUNT mCpuCoreCountMappingTable[] = {
+ { EnumAdlP15Watt282fCpuId, 2, 8},
+ { EnumAdlP28Watt282fCpuId, 2, 8},
+ { EnumAdlP28Watt482fCpuId, 4, 8},
+ { EnumAdlP28Watt682fCpuId, 6, 8},
+ { EnumAdlP45Watt682fCpuId, 6, 8},
+ { EnumAdlP45Watt482fCpuId, 4, 8},
+ { EnumAdlP45Watt442fCpuId, 4, 4},
+ { EnumAdlP28Watt442fCpuId, 4, 4},
+ { EnumAdlP15Watt142fCpuId, 1, 4},
+ { EnumAdlP28Watt142fCpuId, 1, 4},
+ { EnumAdlP15Watt242fCpuId, 2, 4},
+ { EnumAdlP28Watt242fCpuId, 2, 4},
+ { EnumAdlP45Watt242fCpuId, 2, 4},
+ { EnumAdlP45Watt642fCpuId, 6, 4},
+ { EnumAdlP28Watt182fCpuId, 1, 8},
+ { EnumAdlP28Watt642fCpuId, 6, 4},
+ { EnumAdlP28Watt662fCpuId, 6, 6},
+ { EnumAdlM7Watt182fPmicCpuId, 1, 8},
+ { EnumAdlM5Watt182fPmicCpuId, 1, 8},
+ { EnumAdlM7Watt142fPmicCpuId, 1, 4},
+ { EnumAdlM5Watt142fPmicCpuId, 1, 4},
+ { EnumAdlM7Watt242fHybDiscreteCpuId, 2, 4},
+ { EnumAdlM7Watt282fHybDiscreteCpuId, 2, 8},
+ { EnumAdlM7Watt182fHybDiscreteCpuId, 1, 8},
+ { EnumAdlM9Watt282fHybDiscreteCpuId, 2, 8},
+ { EnumAdlM9Watt242fHybDiscreteCpuId, 2, 4},
+ { EnumAdlM9Watt142fHybDiscreteCpuId, 1, 4},
+ { EnumAdlM12Watt142fHybDiscreteCpuId, 1, 4},
+ { EnumAdlM12Watt242fHybDiscreteCpuId, 2, 4},
+ { EnumAdlM12Watt182fHybDiscreteCpuId, 1, 8},
+ { EnumAdlM12Watt282fHybDiscreteCpuId, 2, 8},
+
+};
+
+/**
+ Return CPU Sku
+
+ @param[in] UINT32 CpuFamilyModel
+ @param[in] UINT16 CpuDid
+
+ @retval UINT8 CPU Sku
+**/
+UINT8
+GetCpuSkuInfo (
+ IN UINT32 CpuFamilyModel,
+ IN UINT16 CpuDid
+ )
+{
+ UINT8 CpuType;
+ BOOLEAN SkuFound;
+
+ SkuFound = TRUE;
+ CpuType = EnumCpuUnknown;
+
+ switch (CpuFamilyModel) {
+ case CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE:
+ switch (CpuDid) {
+ case V_SA_DEVICE_ID_MB_ULT_1: // AlderLake P (6+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_2: // AlderLake P (6+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_3: // AlderLake P (4(f)+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_4: // AlderLake P (2(f)+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_5: // AlderLake P (2+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_6: // AlderLake P (2+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_7: // AlderLake P (4+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_8: // AlderLake P (1+4+GT) SA DID
+ case V_SA_DEVICE_ID_MB_ULT_9: // AlderLake P (1+8+GT) SA DID
+ case V_SA_DEVICE_ID_MB_ULT_10: // AlderLake P (6+6+GT) SA DID
+ CpuType = EnumCpuUlt;
+ break;
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+ break;
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+
+ if (!SkuFound) {
+ DEBUG ((DEBUG_ERROR, "Unsupported CPU SKU, Device ID: 0x%02X, CPUID: 0x%08X!\n", CpuDid, CpuFamilyModel));
+ ASSERT (FALSE);
+ }
+
+ return CpuType;
+}
+
+
+/**
+ This function returns the supported Physical Address Size
+
+ @retval returns the supported Physical Address Size.
+**/
+UINT8
+GetMaxPhysicalAddressSizeFru (
+ VOID
+ )
+{
+ //
+ // Even though CPUID Leaf CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) MAX_PA will report 46.
+ // For ADL BIOS will return Memory expansion 39 bit (0 - 38) + MKTME (Bits 39-41 must be zero - 3 bit hole in the middle) 42-45 bit is MKTME Keys.
+ //
+ return 39;
+}
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
new file mode 100644
index 0000000000..22bcbdf43c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
@@ -0,0 +1,29 @@
+## @file
+# This file contains the Cpu Information for specific generation.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseCpuInfoFruLib
+FILE_GUID = 72E44627-C719-4B2D-8C5D-963E167E5AAC
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuInfoFruLib
+
+[LibraryClasses]
+BaseLib
+DebugLib
+PchInfoLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseCpuInfoFruLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
new file mode 100644
index 0000000000..7ea605a05b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
@@ -0,0 +1,22 @@
+/** @file
+
+ Source code file for Report CPU HOB library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Library/HobLib.h>
+#include <Library/CpuPlatformLib.h>
+
+VOID
+ReportCpuHob (
+ VOID
+ )
+{
+ ///
+ /// Create a CPU hand-off information
+ ///
+ BuildCpuHob (GetMaxPhysicalAddressSize (), 16);
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
new file mode 100644
index 0000000000..0ba4744eea
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
@@ -0,0 +1,26 @@
+### @file
+# Component information file for the Report CPU HOB library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiReportCpuHobLib
+ FILE_GUID = F19AA754-CE24-448D-B755-1F939B00C23D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = ReportCpuHobLib
+
+[LibraryClasses]
+ BaseLib
+ HobLib
+ CpuPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiReportCpuHobLib.c
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108621): https://edk2.groups.io/g/devel/message/108621
Mute This Topic: https://groups.io/mt/101347734/1813853
Group Owner: devel+owner at edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [edk2-devel-archive at redhat.com]
-=-=-=-=-=-=-=-=-=-=-=-
More information about the edk2-devel-archive
mailing list