<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=gb2312"> <meta name="Generator" content="Microsoft Word 14 (filtered medium)"> <style></style> </head> <body lang="ZH-CN" link="blue" vlink="purple" style="text-justify-trim:punctuation"> <div class="WordSection1"> OK.<o:p></o:p> I have submitted to Bugzilla.<o:p></o:p> Bug 1823 - source code about disabling the DMAR of IOMMU in IntelSiliconPkg<o:p></o:p> <o:p> </o:p> Thank you<o:p></o:p> Jerry Zhou<o:p></o:p> <div> <div style="border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm"> 发件人: Yao, Jiewen [mailto:jiewen.yao@intel.com] 发送时间: 2019年5月20日 14:09 收件人: Zeng, Star; Jerry Zhou(BJ-RD); edk2-devel@lists.01.org; devel@edk2.groups.io 抄送: Ni, Ray; Yao, Jiewen 主题: RE: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code<o:p></o:p> </div> </div> <o:p> </o:p> Thanks.<o:p></o:p> We are also reviewing the VTd disabling flow and may update recently.<o:p></o:p> <o:p> </o:p> If you want to file Bugzilla, please go ahead.<o:p></o:p> <o:p> </o:p> Thank you<o:p></o:p> Yao Jiewen<o:p></o:p> <a name="_MailEndCompose"></a><o:p> </o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0cm 0cm 0cm 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm"> <a name="_____replyseparator"></a>From: Zeng, Star Sent: Sunday, May 19, 2019 8:33 PM To: Jerry Zhou(BJ-RD) <JerryZhou@zhaoxin.com>; edk2-devel@lists.01.org; devel@edk2.groups.io Cc: Yao, Jiewen <jiewen.yao@intel.com>; Ni, Ray <ray.ni@intel.com>; Zeng, Star <star.zeng@intel.com> Subject: RE: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code<o:p></o:p> </div> </div> <o:p> </o:p> Actually, I agree with you.<o:p></o:p> Personally, I think more rigorous flow could be like below.<o:p></o:p> 1. Clear B_GMCD_REG_TE, wait B_GSTS_REG_TE to be cleared.<o:p></o:p> 2. Set B_GMCD_REG_SRTP, wait B_GSTS_REG_RTPS to be set.<o:p></o:p> 3. Zero R_RTADDR_REG.<o:p></o:p> <o:p> </o:p> Not sure original code developer Jiewen’s thought about this.<o:p></o:p> <o:p> </o:p> <o:p> </o:p> You may submit Bugzilla at <a href="https://bugzilla.tianocore.org">https://bugzilla.tianocore.org</a> if you wait.<o:p></o:p> <o:p> </o:p> <o:p> </o:p> Thanks,<o:p></o:p> Star<o:p></o:p> <o:p> </o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0cm 0cm 0cm 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm"> From: Jerry Zhou(BJ-RD) [<a href="mailto:JerryZhou@zhaoxin.com">mailto:JerryZhou@zhaoxin.com</a>] Sent: Monday, May 13, 2019 7:28 PM To: Zeng, Star <<a href="mailto:star.zeng@intel.com">star.zeng@intel.com</a>>; <a href="mailto:edk2-devel@lists.01.org">edk2-devel@lists.01.org</a>; <a href="mailto:devel@edk2.groups.io">devel@edk2.groups.io</a> Cc: Yao, Jiewen <<a href="mailto:jiewen.yao@intel.com">jiewen.yao@intel.com</a>>; Ni, Ray <<a href="mailto:ray.ni@intel.com">ray.ni@intel.com</a>> Subject: 答复: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code<o:p></o:p> </div> </div> <o:p> </o:p> Got it! Thanks for your reply.<o:p></o:p> But you should still poll the B_GSTS_REG_TE bit, not the B_GSTS_REG_RTPS bit, in the judgement code of while() loop.<o:p></o:p> After & operation between Reg32 and B_GSTS_REG_RTPS, the status of B_GSTS_REG_TE will be lost.<o:p></o:p> <o:p> </o:p> A more tedious but more reliable operation sequence is recommended in Vt-d specification 2.4 below:<o:p></o:p> <o:p> </o:p> to update a bit field in this register at offset X with value of Y, software<o:p></o:p> must follow below steps:<o:p></o:p> 1. Tmp = Read GSTS_REG<o:p></o:p> 2. Status = (Tmp & 96FFFFFFh) // Reset the one-shot bits<o:p></o:p> 3. Command = (Status | (Y << X))<o:p></o:p> 4. Write Command to GCMD_REG<o:p></o:p> 5. Wait until GSTS_REG[X] indicates command is serviced.<o:p></o:p> <div> <div style="border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm"> 发件人: Zeng, Star [<a href="mailto:star.zeng@intel.com">mailto:star.zeng@intel.com</a>] 发送时间: 2019年5月13日 18:54 收件人: Jerry Zhou(BJ-RD); <a href="mailto:edk2-devel@lists.01.org">edk2-devel@lists.01.org</a> 抄送: Yao, Jiewen; Ni, Ray; Zeng, Star 主题: RE: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code<o:p></o:p> </div> </div> <o:p> </o:p> Good question, my understanding is setting B_GMCD_REG_SRTP(BIT30) ONLY also means clearing B_GMCD_REG_TE (BIT31).<o:p></o:p> <o:p> </o:p> Thanks,<o:p></o:p> Star<o:p></o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm"> From: Jerry Zhou(BJ-RD) [<a href="mailto:JerryZhou@zhaoxin.com">mailto:JerryZhou@zhaoxin.com</a>] Sent: Monday, May 13, 2019 10:59 AM To: Zeng, Star <<a href="mailto:star.zeng@intel.com">star.zeng@intel.com</a>>; <a href="mailto:edk2-devel@lists.01.org">edk2-devel@lists.01.org</a> Cc: Yao, Jiewen <<a href="mailto:jiewen.yao@intel.com">jiewen.yao@intel.com</a>>; Ni, Ray <<a href="mailto:ray.ni@intel.com">ray.ni@intel.com</a>> Subject: 答复: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code<o:p></o:p> </div> </div> <o:p> </o:p> Hi Star,<o:p></o:p> I'am so interested in DMA protection in UEFI. It's a really good design!<o:p></o:p> But I have a question about the implemention of DisableDmar() in IntelSiliconPkg\feature\vtd\intelvtddxe\VtdReg.c<o:p></o:p> Is it a typing error in the code segment below?<o:p></o:p> <o:p> </o:p> //<o:p></o:p> // Disable VTd<o:p></o:p> //<o:p></o:p> MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);<o:p></o:p> do {<o:p></o:p> Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);<o:p></o:p> } while((Reg32 & B_GSTS_REG_RTPS) == 0);<o:p></o:p> <o:p> </o:p> The software should program the B_GMCD_REG_TE field in global command register and then poll the B_GSTS_REG_TE field in global status register if the DMAR is expected to be disabled or enabled according to Vt-d specification.<o:p></o:p> <o:p> </o:p> Thanks<o:p></o:p> Jerry Zhou<o:p></o:p> Ext:892418<o:p></o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> -----邮件原件----- 发件人: edk2-devel [<a href="mailto:edk2-devel-bounces@lists.01.org">mailto:edk2-devel-bounces@lists.01.org</a>] 代表 Star Zeng 发送时间: 2018年10月24日 11:32 收件人: <a href="mailto:edk2-devel@lists.01.org"> edk2-devel@lists.01.org</a> 抄送: Jiewen Yao; Star Zeng 主题: [edk2] [PATCH] IntelSiliconPkg VTdDxe: Option to force no early access attr request<o:p></o:p> <o:p> </o:p> REF: <a href="https://bugzilla.tianocore.org/show_bug.cgi?id=1272"> https://bugzilla.tianocore.org/show_bug.cgi?id=1272</a><o:p></o:p> <o:p> </o:p> To have high confidence in usage for platform, add option (BIT2 of<o:p></o:p> PcdVTdPolicyPropertyMask) to force no IOMMU access attribute request<o:p></o:p> recording before DMAR table is installed.<o:p></o:p> <o:p> </o:p> Check PcdVTdPolicyPropertyMask BIT2 before RequestAccessAttribute()<o:p></o:p> and ProcessRequestedAccessAttribute(), then RequestAccessAttribute(),<o:p></o:p> ProcessRequestedAccessAttribute() and mAccessRequestXXX variables<o:p></o:p> could be optimized by compiler when PcdVTdPolicyPropertyMask BIT2 = 1.<o:p></o:p> <o:p> </o:p> Test done:<o:p></o:p> 1: Created case that has IOMMU access attribute request before DMAR<o:p></o:p> table is installed, ASSERT was triggered after setting<o:p></o:p> PcdVTdPolicyPropertyMask BIT2 to 1.<o:p></o:p> <o:p> </o:p> 2. Confirmed RequestAccessAttribute(), ProcessRequestedAccessAttribute()<o:p></o:p> and mAccessRequestXXX variables were optimized by compiler after<o:p></o:p> setting PcdVTdPolicyPropertyMask BIT2 to 1.<o:p></o:p> <o:p> </o:p> Cc: Jiewen Yao <<a href="mailto:jiewen.yao@intel.com">jiewen.yao@intel.com</a>><o:p></o:p> Cc: Rangasai V Chaganty <<a href="mailto:rangasai.v.chaganty@intel.com">rangasai.v.chaganty@intel.com</a>><o:p></o:p> Contributed-under: TianoCore Contribution Agreement 1.1<o:p></o:p> Signed-off-by: Star Zeng <<a href="mailto:star.zeng@intel.com">star.zeng@intel.com</a>><o:p></o:p> ---<o:p></o:p> IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c | 8 +++++++-<o:p></o:p> IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c | 7 +++++++<o:p></o:p> IntelSiliconPkg/IntelSiliconPkg.dec | 1 +<o:p></o:p> 3 files changed, 15 insertions(+), 1 deletion(-)<o:p></o:p> <o:p> </o:p> diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c<o:p></o:p> index 86d50eb6f288..7784545631b3 100644<o:p></o:p> --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c<o:p></o:p> +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c<o:p></o:p> @@ -515,7 +515,13 @@ SetupVtd (<o:p></o:p> <o:p> </o:p> ParseDmarAcpiTableRmrr ();<o:p></o:p> <o:p> </o:p> - ProcessRequestedAccessAttribute ();<o:p></o:p> + if ((PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) == 0) {<o:p></o:p> + //<o:p></o:p> + // Support IOMMU access attribute request recording before DMAR table is installed.<o:p></o:p> + // Here is to process the requests.<o:p></o:p> + //<o:p></o:p> + ProcessRequestedAccessAttribute ();<o:p></o:p> + }<o:p></o:p> <o:p> </o:p> for (Index = 0; Index < mVtdUnitNumber; Index++) {<o:p></o:p> DEBUG ((DEBUG_INFO,"VTD Unit %d (Segment: %04x)\n", Index, mVtdUnitInformation[Index].Segment));<o:p></o:p> diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c<o:p></o:p> index 25d7c80af1d4..09948ce50e94 100644<o:p></o:p> --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c<o:p></o:p> +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c<o:p></o:p> @@ -254,6 +254,13 @@ VTdSetAttribute (<o:p></o:p> // Record the entry to driver global variable.<o:p></o:p> // As such once VTd is activated, the setting can be adopted.<o:p></o:p> //<o:p></o:p> + if ((PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) != 0) {<o:p></o:p> + //<o:p></o:p> + // Force no IOMMU access attribute request recording before DMAR table is installed.<o:p></o:p> + //<o:p></o:p> + ASSERT_EFI_ERROR (EFI_NOT_READY);<o:p></o:p> + return EFI_NOT_READY;<o:p></o:p> + }<o:p></o:p> Status = RequestAccessAttribute (Segment, SourceId, DeviceAddress, Length, IoMmuAccess);<o:p></o:p> } else {<o:p></o:p> PERF_CODE (<o:p></o:p> diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec b/IntelSiliconPkg/IntelSiliconPkg.dec<o:p></o:p> index b9646d773b95..900e8f63c64d 100644<o:p></o:p> --- a/IntelSiliconPkg/IntelSiliconPkg.dec<o:p></o:p> +++ b/IntelSiliconPkg/IntelSiliconPkg.dec<o:p></o:p> @@ -64,6 +64,7 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]<o:p></o:p> ## The mask is used to control VTd behavior. <o:p></o:p> # BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If VTD_INFO_PPI is installed in PEI.)<o:p></o:p> # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in normal boot. EndOfPEI in S3)<o:p></o:p> + # BIT2: Force no IOMMU access attribute request recording before DMAR table is installed.<o:p></o:p> # @Prompt The policy for VTd driver behavior.<o:p></o:p> gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x00000002<o:p></o:p> <o:p> </o:p> -- <o:p></o:p> 2.7.0.windows.1<o:p></o:p> <o:p> </o:p> _______________________________________________<o:p></o:p> edk2-devel mailing list<o:p></o:p> <a href="mailto:edk2-devel@lists.01.org">edk2-devel@lists.01.org</a><o:p></o:p> <a href="https://lists.01.org/mailman/listinfo/edk2-devel">https://lists.01.org/mailman/listinfo/edk2-devel</a><o:p></o:p> <o:p> </o:p> <div> 保密声明：<o:p></o:p> </div> <div> 本邮件含有保密或专有信息，仅供指定收件人使用。严禁对本邮件或其内容做任何未经授权的查阅、使用、复制或转发。<o:p></o:p> </div> <div> CONFIDENTIAL NOTE: <o:p></o:p> </div> This email contains confidential or legally privileged information and is for the sole use of its intended recipient. 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