<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="#0563C1" vlink="#954F72"> <div class="WordSection1"> <o:p> </o:p> <o:p> </o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Ni, Ray [mailto:ray.ni@intel.com] Sent: Monday, March 23, 2020 3:33 PM To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; devel@edk2.groups.io Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Schaefer, Daniel (DualStudy) <daniel.schaefer@hpe.com>; Chen, Gilbert <gilbert.chen@hpe.com> Subject: RE: TianoCore Community Design Meeting Minutes - Mar 20, 2020<o:p></o:p> </div> </div> <o:p> </o:p> Please check one comment prefixed with [Ray-2].<o:p></o:p> <o:p> </o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Chang, Abner (HPS SW/FW Technologist) <<a href="mailto:abner.chang@hpe.com">abner.chang@hpe.com</a>> Sent: Monday, March 23, 2020 2:40 PM To: Ni, Ray <<a href="mailto:ray.ni@intel.com">ray.ni@intel.com</a>>; <a href="mailto:devel@edk2.groups.io"> devel@edk2.groups.io</a> Cc: Kinney, Michael D <<a href="mailto:michael.d.kinney@intel.com">michael.d.kinney@intel.com</a>>; Schaefer, Daniel (DualStudy) <<a href="mailto:daniel.schaefer@hpe.com">daniel.schaefer@hpe.com</a>>; Chen, Gilbert <<a href="mailto:gilbert.chen@hpe.com">gilbert.chen@hpe.com</a>> Subject: RE: TianoCore Community Design Meeting Minutes - Mar 20, 2020<o:p></o:p> </div> </div> <o:p> </o:p> <o:p> </o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Ni, Ray [<a href="mailto:ray.ni@intel.com">mailto:ray.ni@intel.com</a>] Sent: Monday, March 23, 2020 1:13 PM To: Chang, Abner (HPS SW/FW Technologist) <<a href="mailto:abner.chang@hpe.com">abner.chang@hpe.com</a>>; <a href="mailto:devel@edk2.groups.io">devel@edk2.groups.io</a> Cc: Kinney, Michael D <<a href="mailto:michael.d.kinney@intel.com">michael.d.kinney@intel.com</a>>; Schaefer, Daniel (DualStudy) <<a href="mailto:daniel.schaefer@hpe.com">daniel.schaefer@hpe.com</a>>; Chen, Gilbert <<a href="mailto:gilbert.chen@hpe.com">gilbert.chen@hpe.com</a>> Subject: RE: TianoCore Community Design Meeting Minutes - Mar 20, 2020<o:p></o:p> </div> </div> <o:p> </o:p> Resend to <a href="mailto:devel@edk2.groups.io">devel@edk2.groups.io</a> with my responses.<o:p></o:p> <o:p> </o:p> <a href="mailto:announce@edk2.groups.io">announce@edk2.groups.io</a> is not for tech discussion and only few people have post permission.<o:p></o:p> [Abner] Ok. I see. My response in below.<o:p></o:p> <o:p> </o:p> <o:p> </o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Chang, Abner (HPS SW/FW Technologist) <<a href="mailto:abner.chang@hpe.com">abner.chang@hpe.com</a>> Sent: Monday, March 23, 2020 12:05 PM To: Ni, Ray <<a href="mailto:ray.ni@intel.com">ray.ni@intel.com</a>>; <a href="mailto:announce@edk2.groups.io"> announce@edk2.groups.io</a> Cc: Kinney, Michael D <<a href="mailto:michael.d.kinney@intel.com">michael.d.kinney@intel.com</a>>; Schaefer, Daniel (DualStudy) <<a href="mailto:daniel.schaefer@hpe.com">daniel.schaefer@hpe.com</a>>; Chen, Gilbert <<a href="mailto:gilbert.chen@hpe.com">gilbert.chen@hpe.com</a>> Subject: RE: TianoCore Community Design Meeting Minutes - Mar 20, 2020<o:p></o:p> </div> </div> <o:p> </o:p> Ray, my responses in line.<o:p></o:p> <o:p> </o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Ni, Ray [<a href="mailto:ray.ni@intel.com">mailto:ray.ni@intel.com</a>] Sent: Friday, March 20, 2020 5:05 PM To: <a href="mailto:announce@edk2.groups.io">announce@edk2.groups.io</a> Cc: Chang, Abner (HPS SW/FW Technologist) <<a href="mailto:abner.chang@hpe.com">abner.chang@hpe.com</a>>; Kinney, Michael D <<a href="mailto:michael.d.kinney@intel.com">michael.d.kinney@intel.com</a>>; Ni, Ray <<a href="mailto:ray.ni@intel.com">ray.ni@intel.com</a>> Subject: TianoCore Community Design Meeting Minutes - Mar 20, 2020<o:p></o:p> </div> </div> <o:p> </o:p> Topic:<o:p></o:p> <o:p> </o:p> 1. EDK2 DxeIpl Abstraction (Abner Chang/HPE)<o:p></o:p> <o:p> </o:p> Slides: <a href="https://edk2.groups.io/g/devel/files/Designs/2020/0320/EDK2%20DxeIpl%20Abstraction.pdf"> https://edk2.groups.io/g/devel/files/Designs/2020/0320/EDK2%20DxeIpl%20Abstraction.pdf</a><o:p></o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> Today's meeting was extended to 2 hours to discuss the overall RISC-V support in EDKII. It makes sense because low-level design depends on the finalize of high-level design.<o:p></o:p> <o:p> </o:p> Today's RISC-V enabling in EDKII work is to provide a UEFI wrapper over RISC-V OpenSBI (Open Source Supervisor Binary Interface), which is an open-source reference implementation (<a href="https://github.com/riscv/opensbi">https://github.com/riscv/opensbi</a>) of RISC-V SBI specification (<a href="https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc">https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc</a>).<o:p></o:p> <o:p> </o:p> OpenSBI itself is a boot loader. If RISC-V SBI specification is treated as UEFI spec and OpenSBI is treated as the EDKII.<o:p></o:p> <o:p> </o:p> Right now, Abner's work is the only effort that enables UEFI in RISC-V platforms.<o:p></o:p> <o:p> </o:p> The EDKII RISC-V environment consists of three phases: SEC-PEI-DXE. A RISC-V specific SEC module statically linked with OpenSBI exposes all interfaces required by the UEFI wrapper.<o:p></o:p> <o:p> </o:p> There are 3 sub-topics discussed in the meeting:<o:p></o:p> <o:p> </o:p> 1. Which mode DXE phase is running at?<o:p></o:p> <o:p> </o:p> RISC-V defines three privileged modes: Machine/Supervisor/User Mode.<o:p></o:p> SEC and PEI run in M mode and DXE can run either in M mode or S mode which is the platform's choice.<o:p></o:p> If DXE runs in S mode, some of the resources cannot be accessed.<o:p></o:p> UEFI spec says RISC-V only runs in M mode during post including DXE. Spec needs update.<o:p></o:p> [Abner] Yes, this must be updated. I will take this.<o:p></o:p> <o:p> </o:p> 2. How to resolve MdeModulePkg's dependency on RiscVPkg?<o:p></o:p> <o:p> </o:p> The dependency is because the M to S mode switch <o:p></o:p> [Abner] This may not accurate. I think you mean the dependency is exposed due to we rely on RISC-V OpenSBI execution mode switch function to put DXE phase in Supervisor mode. We should fix the issue which DXE IPL mixes up the processor architecture in itself, but not to fix switch mode itself.<o:p></o:p> [Ray] Your words are more accurate. But if we split the change to 2 parts: one requires DXE phase runs in M mode, the other requires DXE phase runs in S mode. Only the 2nd part introduces the MdeModulePkg’s dependency on RiscVPkg. We could potentially work on the first part (when the final conclusion is RISC-V does need SEC and PEI phases for UEFI).<o:p></o:p> [Abner] We actually do not have to split DXE phase into two modes. This is actually a very simple DXEIPL dependency issue but seems to me we led this to even far. DXE phase could be just in M-mode or S-mode depends on platform requirements and processor capability. To split DXE phases into two different modes is unnecessary and not much value. Separate SEC/PEI and DXE/BDS into two modes (or in the same mode) is good enough. DXE phases has M-mode actually, that is when the OpenSBI function is trigger in SMode and executed in MMode.<o:p></o:p> [Ray-2] <a href="https://github.com/tianocore/edk2-staging/commit/33a9bd8984163ca2a7cc50627c15087f7574e203">https://github.com/tianocore/edk2-staging/commit/33a9bd8984163ca2a7cc50627c15087f7574e203</a> adds two library instances. One of them is to simply call SwitchStack() to DXE phase which means DXE phase runs in the same mode as PEI phase. The other one calls to OpenSBI to switch to S mode.<o:p></o:p> [Abner] Yes. the NULL instance one (Simple call to SwitchStack()) will never been used and it is there just for building RiscVPkg package. I think I should remove it as Ard mentioned in his comment (I can’t remember who exactly mentioned that). <o:p></o:p> The second one is used for RISC-V platforms, ThisScratch->next_mode = PRV_S is the parameters to switch to either SMode or MMode. Currently it is hardcoded but could be an PCD defined in RiscVPlatformPkg and override by platform dsc.<o:p></o:p> Sorry, I thought “DXE phase” you mentioned refers to the entire DXE phase.<o:p></o:p> <o:p> </o:p> <o:p> </o:p> This project is targeted on having RISC-V edk2 port to align with edk2 different execution phases since 2016 and presented in UEFI plugfest 2016. This is also the current most use cases of PC and server (HPE are focusing on PC/Server area), to skip SEC and PEI is not the initial goal of this project. We can raise another project for skipping SEC and PEI, I assume you were saying the UefiPayloadPkg?<o:p></o:p> <o:p> </o:p> Abner's solution tries to address this dependency issue by introducing another abstract layer. (see slides: <a href="https://edk2.groups.io/g/devel/files/Designs/2020/0320/EDK2%20DxeIpl%20Abstraction.pdf"> https://edk2.groups.io/g/devel/files/Designs/2020/0320/EDK2%20DxeIpl%20Abstraction.pdf</a>)<o:p></o:p> Mike proposes another solution: RiskVPkg exposes the mode switch interfaces (sbi_init ?) through PPI and the PPI definition can be in MdePkg which might be included by PI spec.<o:p></o:p> [Abner] This may not work if the PPI/Protocol still have dependency with RISC-V definitions. But it is ok if could we define a generic PPI/Protocol such as EFI_EXECUTION_MODE_PROTOCOL(PPI) under MdePkg. Then arch provides the implementation, however, this is our midterm plan not for now though. NULL instance of DxeIplHadndoffLib is still a neat choice IMO.<o:p></o:p> [Ray] The original plan was to expose OpenSBI interfaces through PPI/Protocol defined in PI spec and MdePkg. But given the fact OpenSBI is an under-development project and your change is a UEFI wrapper over OpenSBI, it may be hard to propose the OpenSBI interfaces to PI spec. There was an idea raised in the meeting which is to extend UefiPayloadPkg for RISC-V.<o:p></o:p> [Abner] Actually we don’t intend to have OpenSBI EFI protocol defined in PI nor UEFI spec. The EFI version OpenSBI interface is only for RISC-V arch, the spec will be in RISC-V github instead.<o:p></o:p> <o:p> </o:p> UefiplayloadPkg is the firmware payload for CoreBoot or other boot loader. This approach could be classified as another project and different from our approach which is the regular EDK2 implementation aligns with x86 PC/Server firmware arch. And this is the goal of this initial edk2 RISC-V port as well, which is based on edk2 boot phases. For HPE, we won’t use CoreBoot, LinuxBoot or other boot mechanisms for now or even in the future (I can’t see any chance so far) in our mainstream server products. Whether to use UefiPayloadPkg is determined by system vendors, also depends on the demands of firmware support and corporate strategy. We should not mixed up these different firmware mechanisms. Again, we are fine to create another project for UefiPayloadPkg though, but that is far from HPE system firmware direction.<o:p></o:p> <o:p> </o:p> 3. Location of RiscVPkg and RiscVPlatformPkg<o:p></o:p> <o:p> </o:p> RiscVPkg in @edk2-platforms/Silicon/... directory.<o:p></o:p> RiscVPlatformPkg in @edk2-platforms/Platform/... directory.<o:p></o:p> Long term goal is to put all CPU implementation that follows industry standard to UefiCpuPkg, including ARM and RISC-V.<o:p></o:p> [Abner] We can consider this solution to put RISC-V packages in edk2-platforms in temporary. However, the final decision should be made accroding,<o:p></o:p> <ol style="margin-top:0in" start="1" type="1"> <li class="MsoNormal" style="color:#1F497D;mso-list:l0 level1 lfo3">The plan for refining UefiCpuPkg. It is meaningless to put RISC-V packages in edk2-platforms if the plan of UefiCpuPkg refining is something like one or two years.<o:p></o:p></li><li class="MsoNormal" style="color:#1F497D;mso-list:l0 level1 lfo3">How far it is from current UefiCpuPkg implementation to the ideal generic UefiCpuPkg for all archs?<o:p></o:p></li></ol> [Ray] RiscVPlatformPkg in @edk2-platforms doesn’t depend on above 2 questions.<o:p></o:p> [Abner] RiscVPlatformPkg still has dependency with RiscVPkg. To speak frankly, that is not a good idea to separate RiscVPkg and RiscVPlatform packages into two repos, that is a nightmare and burdens to maintain changes in two different repos even the commit in both repos fix the same issue.<o:p></o:p> <o:p> </o:p> 4. Which changes can be in edk2<o:p></o:p> <o:p> </o:p> Need Abner to look at all the changes again. But at least the INF/C changes that enable individual drivers to be built by RISC-V compiler can.<o:p></o:p> [Abner] yes. <o:p></o:p> <o:p> </o:p> Thanks,<o:p></o:p> Ray<o:p></o:p> <o:p></o:p> </div> </div> </div> </div> </div> </div> </body> </html> <div width="1" style="color:white;clear:both">_._,_._,_</div> <hr> Groups.io Links: You receive all messages sent to this group. <a target="_blank" href="https://edk2.groups.io/g/devel/message/56098">View/Reply Online (#56098)</a> | | <a target="_blank" href="https://groups.io/mt/72485353/1813853">Mute This Topic</a> | <a href="https://edk2.groups.io/g/devel/post">New Topic</a> <a href="https://edk2.groups.io/g/devel/editsub/1813853">Your Subscription</a> | <a href="mailto:devel+owner@edk2.groups.io">Contact Group Owner</a> | <a href="https://edk2.groups.io/g/devel/unsub">Unsubscribe</a> [edk2-devel-archive@redhat.com] <div width="1" style="color:white;clear:both">_._,_._,_</div>