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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Thanks Leif and Daniel,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Now all of the commits were reviewed. I will rebase it to the latest edk2-platform master branch and check if any problems there. Will merge it if no problem
found.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Abner<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Schaefer, Daniel
<br>
<b>Sent:</b> Saturday, August 15, 2020 12:53 PM<br>
<b>To:</b> Leif Lindholm <leif@nuviainc.com>; devel@edk2.groups.io<br>
<b>Cc:</b> Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; Chen, Gilbert <gilbert.chen@hpe.com>; Michael D Kinney <michael.d.kinney@intel.com>; Ard Biesheuvel <ard.biesheuvel@linaro.org><br>
<b>Subject:</b> Re: [edk2-devel] [PATCH 1/1] edk2-platforms: Deduplicate RISC-V SMBIOS<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hi Leif,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Great, thanks!<o:p></o:p></p>
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<p class="MsoNormal">Yes, we'll fold it into the commits that introduced the mess in the first place. I just didn't want to make this effort before you sign off on the refactoring. And hope it was easier to review this way.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Yes, we dropped some tables because we rethought how to apply smbios to this flexible RISC-V SoC, which doesn't really fit into the rigid view smbios has of hardware.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Cheers,<o:p></o:p></p>
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<p class="MsoNormal">Daniel<o:p></o:p></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">
<a href="mailto:devel@edk2.groups.io">devel@edk2.groups.io</a> <<a href="mailto:devel@edk2.groups.io">devel@edk2.groups.io</a>> on behalf of Leif Lindholm <<a href="mailto:leif@nuviainc.com">leif@nuviainc.com</a>><br>
<b>Sent:</b> Friday, August 14, 2020 15:40<br>
<b>To:</b> <a href="mailto:devel@edk2.groups.io">devel@edk2.groups.io</a> <<a href="mailto:devel@edk2.groups.io">devel@edk2.groups.io</a>>; Schaefer, Daniel <<a href="mailto:daniel.schaefer@hpe.com">daniel.schaefer@hpe.com</a>><br>
<b>Cc:</b> Chang, Abner (HPS SW/FW Technologist) <<a href="mailto:abner.chang@hpe.com">abner.chang@hpe.com</a>>; Chen, Gilbert <<a href="mailto:gilbert.chen@hpe.com">gilbert.chen@hpe.com</a>>; Michael D Kinney <<a href="mailto:michael.d.kinney@intel.com">michael.d.kinney@intel.com</a>>;
Ard Biesheuvel <<a href="mailto:ard.biesheuvel@linaro.org">ard.biesheuvel@linaro.org</a>><br>
<b>Subject:</b> Re: [edk2-devel] [PATCH 1/1] edk2-platforms: Deduplicate RISC-V SMBIOS</span>
<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span style="font-size:11.0pt">Hi Daniel,<br>
<br>
Thanks for this rework. It looks a massive improvement.<br>
<br>
On Fri, Aug 07, 2020 at 18:44:44 +0200, Daniel Schaefer wrote:<br>
> There was too much code, which wasn't called but it could have generated those SMBIOS table entries:<br>
> <br>
> - Type 4 for each core (4xU51, 1xE51)<br>
> - Type 7 L1 instruction/data for each core<br>
> - Type 7 L2 for U54<br>
> - Type 44 for each core<br>
> - Type 4 for the coreplex<br>
> - Type 7 L2 for the coreplex<br>
> <br>
> Now it only has code for those entries:<br>
> <br>
> - Type 4 for SOC [1x]<br>
> - Type 7 L1 for SOC [1x] (even though every hart has own L1, but my Laptop's Intel i5 does that also)<br>
> - Type 7 L2 for SOC [1x]<br>
> - Type 44 for each hart, associated with CPU [5x]<br>
> <br>
> In addition to simplifying the SMBIOS tables, the code for U54 and E51 is<br>
> combined, like Leif suggested in his review.<br>
> <br>
> Here's what happened to the files:<br>
> <br>
> Expanded:<br>
> <br>
> - Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c<br>
> <br>
> Deleted file:<br>
> <br>
> - Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c<br>
> - Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c<br>
> <br>
> Merged with E51 code into single file:<br>
> <br>
> - Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c<br>
> <br>
> Added SMBIOS Type 7 for L1 Cache, removed duplicated SMBIOS (Type 4 and 7 code):<br>
> <br>
> - Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c<br>
> <br>
> Cc: Abner Chang <<a href="mailto:abner.chang@hpe.com">abner.chang@hpe.com</a>><br>
> Cc: Gilbert Chen <<a href="mailto:gilbert.chen@hpe.com">gilbert.chen@hpe.com</a>><br>
> Cc: Leif Lindholm <<a href="mailto:leif@nuviainc.com">leif@nuviainc.com</a>><br>
> Cc: Michael D Kinney <<a href="mailto:michael.d.kinney@intel.com">michael.d.kinney@intel.com</a>><br>
> Cc: Ard Biesheuvel <<a href="mailto:ard.biesheuvel@linaro.org">ard.biesheuvel@linaro.org</a>><br>
> ---<br>
> Silicon/SiFive/SiFive.dec | 2 -<br>
> .../FreedomU500VC707Board/U500.dsc | 1 -<br>
> .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 -<br>
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 1 -<br>
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 47 ----<br>
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 4 +<br>
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 46 ----<br>
> .../FirmwareContextProcessorSpecificLib.h | 11 +<br>
> .../Include/ProcessorSpecificHobData.h | 3 +-<br>
> Silicon/SiFive/Include/Library/SiFiveE51.h | 60 -----<br>
> Silicon/SiFive/Include/Library/SiFiveU54.h | 50 ++--<br>
> .../Include/Library/SiFiveU54MCCoreplex.h | 55 ----<br>
> .../FirmwareContextProcessorSpecificLib.c | 26 ++<br>
> .../Universal/Pei/PlatformPei/Platform.c | 2 +-<br>
> .../Universal/Pei/PlatformPei/Platform.c | 2 +-<br>
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 58 +----<br>
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 235 -----------------<br>
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 244 +++++++-----------<br>
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 184 -------------<br>
> 19 files changed, 178 insertions(+), 854 deletions(-)<br>
<br>
I know you dropped some tables, but that's a *nice* diffstat.<br>
<br>
I guess this is effectively meant to be folded into existing commits?<br>
If so:<br>
Reviewed-by: Leif Lindholm <<a href="mailto:leif@nuviainc.com">leif@nuviainc.com</a>><br>
If not, I might start grumbling about some unrelated cleanup in this<br>
patch...<br>
<br>
/<br>
Leif<br>
<br>
<o:p></o:p></span></p>
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