From 3a9af32af22020f2cb080ab38c626691585adb3c Mon Sep 17 00:00:00 2001 From: Sheng Wei Date: Tue, 3 Nov 2020 12:22:49 +0800 Subject: [PATCH v4 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Support 5 level paging for mInternalCr3 If mInternalCr3 is non zero, it will use the page table from mInternalCr3. And it will use mInternalIs5LevelPaging to reflect the page table type. If use page table from CR3, reflect the page table type by CR4 LA57 bit. It is a fix for enable CET feature with 5 level paging. PiCpuSmmEntry() will generate the page table of SMM shack memory. If CET feature is enabled, it also includes the SMM shadows shack memory. And we need to set some attributes on SMM shadows shack memory in PiCpuSmmEntry() when CET feature is enabled. Since the page table of SMM shack memory is used in SMI entry, and it does not set to CR3 in PiCpuSmmEntry(). We use mInternalCr3 as page table root when PiCpuSmmEntry() calls ConvertMemoryPageAttributes(). We need to use mInternalIs5LevelPaging determining whether 5-level paging is enabled or not. If mInternalCr3 is zero, ConvertMemoryPageAttributes() will use the page table in CR3, and refects the page table type by CR4 LA57 bit. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015 Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Jiewen Yao Sheng Wei (2): UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo UefiCpuPkg/PiSmmCpuDxeSmm: Return level paging type for Internal CR3 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 10 ++++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 53 ++++++++++++++++++---- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 2 + 3 files changed, 57 insertions(+), 8 deletions(-) -- 2.16.2.windows.1