From 82e77d30ee0d38d36dde94d529fd2b7d2672c89f Mon Sep 17 00:00:00 2001 From: Sheng Wei Date: Thu, 5 Nov 2020 11:36:35 +0800 Subject: [PATCH v5 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Support 5 level paging for mInternalCr3 If mInternalCr3 is non zero, it will use the page table from mInternalCr3. And it will use mInternalIs5LevelPaging to reflect the paging type. If mInternalCr3 is zero, it will use the page table from CR3, and reflect the paging type by CR4 LA57 bit. This patch is a bug fix when enable CET feature with 5 level paging. The page table of SMM shadows shack memory is generated in PiCpuSmmEntry(). This page table is not set to CR3 in PiCpuSmmEntry(), it is only for SMI entry. When CET feature is enabled, we need to set some attributes for SMM shadows shack memory in PiCpuSmmEntry(). We set this page table to mInternalCr3 for update the memory attribute. The CR4 LA57 bit does not reflect the paging type of mInternalCr3, so we need to use a virable (mInternalIs5LevelPaging) to reflect if mInternalCr3 is 5 level paging or 4 level paging. We also use the same function to update the memory attribue with the page table in CR3, use CR4 LA57 bit to reflect the paging type of CR3. So we need to use GetPageTableBase() and Is5LevelPageTableBase() to return the page table and its paging type for GetPageTableEntry() when set the memory attribute. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015 Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Jiewen Yao Sheng Wei (2): UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo UefiCpuPkg/PiSmmCpuDxeSmm: Return level paging type for Internal CR3 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 10 ++++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 57 +++++++++++++++++++--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 2 + 3 files changed, 61 insertions(+), 8 deletions(-) -- 2.16.2.windows.1