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<div style="margin:0px;font-size:12pt"><span style="margin:0px">LGTM. This is the same approach I took last time I looked at this (unsuccessfully...)</span><br>
</div>
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<div style="margin:0px;font-size:12pt">Reviewed-by: Andrei Warkentin <awarkentin@vmware.com></div>
<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton=arm.com@groups.io><br>
<b>Sent:</b> Monday, December 14, 2020 5:23 PM<br>
<b>To:</b> devel@edk2.groups.io <devel@edk2.groups.io><br>
<b>Cc:</b> ard.biesheuvel@arm.com <ard.biesheuvel@arm.com>; leif@nuviainc.com <leif@nuviainc.com>; pete@akeo.ie <pete@akeo.ie>; andrey.warkentin@gmail.com <andrey.warkentin@gmail.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton
<jeremy.linton@arm.com><br>
<b>Subject:</b> [edk2-devel] [PATCH 3/7] Platform/RaspberryPi: Split MMC register defintions</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">The current MMC (really SDHCI) defintions are tied to the<br>
arasan controller. As we intend to reuse the definitions lets<br>
make the base address configurable when the driver loads.<br>
<br>
This assumes we won't ever want to run both the emmc2<br>
and arasan sdhci controller at the same time.<br>
<br>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com><br>
---<br>
.../Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c | 9 ++++-<br>
.../Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h | 42 ++++++++++++----------<br>
2 files changed, 32 insertions(+), 19 deletions(-)<br>
<br>
diff --git a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c<br>
index 88e9126e35..0cb7e85b38 100644<br>
--- a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c<br>
+++ b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c<br>
@@ -16,6 +16,7 @@ STATIC CARD_DETECT_STATE mCardDetectState = CardDetectRequired;<br>
UINT32 LastExecutedCommand = (UINT32) -1;<br>
<br>
<br>
<br>
STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol;<br>
<br>
+STATIC UINTN MMCHS_BASE;<br>
<br>
<br>
<br>
/**<br>
<br>
These SD commands are optional, according to the SD Spec<br>
<br>
@@ -763,7 +764,13 @@ MMCInitialize (<br>
<br>
<br>
DEBUG ((DEBUG_MMCHOST_SD, "ArasanMMCHost: MMCInitialize()\n"));<br>
<br>
<br>
<br>
- if (!PcdGet32 (PcdSdIsArasan)) {<br>
<br>
+ if (PcdGet32 (PcdSdIsArasan)) {<br>
<br>
+ DEBUG ((DEBUG_INFO, "SD is routed to Arasan\n"));<br>
<br>
+ MMCHS_BASE = MMCHS1_BASE;<br>
<br>
+ } else if (RPI_MODEL == 4) {<br>
<br>
+ DEBUG ((DEBUG_INFO, "SD is routed to emmc2\n"));<br>
<br>
+ MMCHS_BASE = MMCHS2_BASE;<br>
<br>
+ } else {<br>
<br>
DEBUG ((DEBUG_INFO, "SD is not routed to Arasan\n"));<br>
<br>
return EFI_REQUEST_UNLOAD_IMAGE;<br>
<br>
}<br>
<br>
diff --git a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h<br>
index fd07b47170..e6892d36cf 100644<br>
--- a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h<br>
+++ b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h<br>
@@ -13,15 +13,18 @@<br>
<br>
<br>
// MMC/SD/SDIO1 register definitions.<br>
<br>
#define MMCHS1_OFFSET 0x00300000<br>
<br>
+#define MMCHS2_OFFSET 0x00340000<br>
<br>
#define MMCHS1_BASE (BCM2836_SOC_REGISTERS + MMCHS1_OFFSET)<br>
<br>
+#define MMCHS2_BASE (BCM2836_SOC_REGISTERS + MMCHS2_OFFSET)<br>
<br>
#define MMCHS1_LENGTH 0x00000100<br>
<br>
+#define MMCHS2_LENGTH 0x00000100<br>
<br>
<br>
<br>
-#define MMCHS_BLK (MMCHS1_BASE + 0x4)<br>
<br>
+#define MMCHS_BLK (MMCHS_BASE + 0x4)<br>
<br>
#define BLEN_512BYTES (0x200UL << 0)<br>
<br>
<br>
<br>
-#define MMCHS_ARG (MMCHS1_BASE + 0x8)<br>
<br>
+#define MMCHS_ARG (MMCHS_BASE + 0x8)<br>
<br>
<br>
<br>
-#define MMCHS_CMD (MMCHS1_BASE + 0xC)<br>
<br>
+#define MMCHS_CMD (MMCHS_BASE + 0xC)<br>
<br>
#define BCE_ENABLE BIT1<br>
<br>
#define DDIR_READ BIT4<br>
<br>
#define DDIR_WRITE (0x0UL << 4)<br>
<br>
@@ -43,13 +46,13 @@<br>
#define INDX(CMD_INDX) (TYPE(CMD_TYPE_NORMAL) | _INDX(CMD_INDX))<br>
<br>
#define INDX_ABORT(CMD_INDX) (TYPE(CMD_TYPE_ABORT) | _INDX(CMD_INDX))<br>
<br>
<br>
<br>
-#define MMCHS_RSP10 (MMCHS1_BASE + 0x10)<br>
<br>
-#define MMCHS_RSP32 (MMCHS1_BASE + 0x14)<br>
<br>
-#define MMCHS_RSP54 (MMCHS1_BASE + 0x18)<br>
<br>
-#define MMCHS_RSP76 (MMCHS1_BASE + 0x1C)<br>
<br>
-#define MMCHS_DATA (MMCHS1_BASE + 0x20)<br>
<br>
+#define MMCHS_RSP10 (MMCHS_BASE + 0x10)<br>
<br>
+#define MMCHS_RSP32 (MMCHS_BASE + 0x14)<br>
<br>
+#define MMCHS_RSP54 (MMCHS_BASE + 0x18)<br>
<br>
+#define MMCHS_RSP76 (MMCHS_BASE + 0x1C)<br>
<br>
+#define MMCHS_DATA (MMCHS_BASE + 0x20)<br>
<br>
<br>
<br>
-#define MMCHS_PRES_STATE (MMCHS1_BASE + 0x24)<br>
<br>
+#define MMCHS_PRES_STATE (MMCHS_BASE + 0x24)<br>
<br>
#define CMDI_MASK BIT0<br>
<br>
#define CMDI_ALLOWED (0x0UL << 0)<br>
<br>
#define CMDI_NOT_ALLOWED BIT0<br>
<br>
@@ -58,17 +61,19 @@<br>
#define DATI_NOT_ALLOWED BIT1<br>
<br>
#define WRITE_PROTECT_OFF BIT19<br>
<br>
<br>
<br>
-#define MMCHS_HCTL (MMCHS1_BASE + 0x28)<br>
<br>
+#define MMCHS_HCTL (MMCHS_BASE + 0x28)<br>
<br>
#define DTW_1_BIT (0x0UL << 1)<br>
<br>
#define DTW_4_BIT BIT1<br>
<br>
#define SDBP_MASK BIT8<br>
<br>
#define SDBP_OFF (0x0UL << 8)<br>
<br>
#define SDBP_ON BIT8<br>
<br>
+#define SDVS_MASK (0x7UL << 9)<br>
<br>
#define SDVS_1_8_V (0x5UL << 9)<br>
<br>
#define SDVS_3_0_V (0x6UL << 9)<br>
<br>
+#define SDVS_3_3_V (0x7UL << 9)<br>
<br>
#define IWE BIT24<br>
<br>
<br>
<br>
-#define MMCHS_SYSCTL (MMCHS1_BASE + 0x2C)<br>
<br>
+#define MMCHS_SYSCTL (MMCHS_BASE + 0x2C)<br>
<br>
#define ICE BIT0<br>
<br>
#define ICS_MASK BIT1<br>
<br>
#define ICS BIT1<br>
<br>
@@ -84,7 +89,7 @@<br>
#define SRC BIT25<br>
<br>
#define SRD BIT26<br>
<br>
<br>
<br>
-#define MMCHS_INT_STAT (MMCHS1_BASE + 0x30)<br>
<br>
+#define MMCHS_INT_STAT (MMCHS_BASE + 0x30)<br>
<br>
#define CC BIT0<br>
<br>
#define TC BIT1<br>
<br>
#define BWR BIT4<br>
<br>
@@ -96,7 +101,7 @@<br>
#define DCRC BIT21<br>
<br>
#define DEB BIT22<br>
<br>
<br>
<br>
-#define MMCHS_IE (MMCHS1_BASE + 0x34)<br>
<br>
+#define MMCHS_IE (MMCHS_BASE + 0x34)<br>
<br>
#define CC_EN BIT0<br>
<br>
#define TC_EN BIT1<br>
<br>
#define BWR_EN BIT4<br>
<br>
@@ -112,7 +117,7 @@<br>
#define BADA_EN BIT29<br>
<br>
#define ALL_EN 0xFFFFFFFF<br>
<br>
<br>
<br>
-#define MMCHS_ISE (MMCHS1_BASE + 0x38)<br>
<br>
+#define MMCHS_ISE (MMCHS_BASE + 0x38)<br>
<br>
#define CC_SIGEN BIT0<br>
<br>
#define TC_SIGEN BIT1<br>
<br>
#define BWR_SIGEN BIT4<br>
<br>
@@ -127,14 +132,15 @@<br>
#define CERR_SIGEN BIT28<br>
<br>
#define BADA_SIGEN BIT29<br>
<br>
<br>
<br>
-#define MMCHS_AC12 (MMCHS1_BASE + 0x3C)<br>
<br>
+#define MMCHS_AC12 (MMCHS_BASE + 0x3C)<br>
<br>
+#define MMCHS_HC2R (MMCHS_BASE + 0x3E)<br>
<br>
<br>
<br>
-#define MMCHS_CAPA (MMCHS1_BASE + 0x40)<br>
<br>
+#define MMCHS_CAPA (MMCHS_BASE + 0x40)<br>
<br>
#define VS30 BIT25<br>
<br>
#define VS18 BIT26<br>
<br>
<br>
<br>
-#define MMCHS_CUR_CAPA (MMCHS1_BASE + 0x48)<br>
<br>
-#define MMCHS_REV (MMCHS1_BASE + 0xFC)<br>
<br>
+#define MMCHS_CUR_CAPA (MMCHS_BASE + 0x48)<br>
<br>
+#define MMCHS_REV (MMCHS_BASE + 0xFC)<br>
<br>
<br>
<br>
#define BLOCK_COUNT_SHIFT 16<br>
<br>
#define RCA_SHIFT 16<br>
<br>
-- <br>
2.13.7<br>
<br>
<br>
<br>
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