<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="#0563C1" vlink="#954F72"> <div class="WordSection1"> Hi Kim,<o:p></o:p> <o:p> </o:p> Ray suggests a one line patch instead of google’s solution.<o:p></o:p> + PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;<o:p></o:p> <o:p> </o:p> Could you help to verify Ray’s solution on that card?<o:p></o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Ni, Ray <ray.ni@intel.com> Sent: Thursday, January 14, 2021 1:59 PM To: Zhong, Zarcd <zarcd.zhong@intel.com>; devel@edk2.groups.io Cc: Wu, Hao A <hao.a.wu@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com> Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in high 32bit of MEM64.<o:p></o:p> </div> </div> <o:p> </o:p> Zarcd,<o:p></o:p> I may not say very clearly. I prefer to just keep below line. Can you check whether that can work?<o:p></o:p> + PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;<o:p></o:p> <o:p> </o:p> Thanks, Ray<o:p></o:p> <o:p> </o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Zhong, Zarcd <<a href="mailto:zarcd.zhong@intel.com">zarcd.zhong@intel.com</a>> Sent: Thursday, January 14, 2021 10:48 AM To: Ni, Ray <<a href="mailto:ray.ni@intel.com">ray.ni@intel.com</a>>; <a href="mailto:devel@edk2.groups.io"> devel@edk2.groups.io</a> Cc: Wu, Hao A <<a href="mailto:hao.a.wu@intel.com">hao.a.wu@intel.com</a>>; Kinney, Michael D <<a href="mailto:michael.d.kinney@intel.com">michael.d.kinney@intel.com</a>> Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in high 32bit of MEM64.<o:p></o:p> </div> </div> <o:p> </o:p> Hi Ray,<o:p></o:p> <o:p> </o:p> Attached patch is updated with below add. Thanks for your remind.<o:p></o:p> <o:p> </o:p> PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;<o:p></o:p> <o:p> </o:p> <o:p> </o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Ni, Ray <<a href="mailto:ray.ni@intel.com">ray.ni@intel.com</a>> Sent: Wednesday, January 13, 2021 3:01 PM To: Zhong, Zarcd <<a href="mailto:zarcd.zhong@intel.com">zarcd.zhong@intel.com</a>>; <a href="mailto:devel@edk2.groups.io">devel@edk2.groups.io</a> Cc: Wu, Hao A <<a href="mailto:hao.a.wu@intel.com">hao.a.wu@intel.com</a>>; Kinney, Michael D <<a href="mailto:michael.d.kinney@intel.com">michael.d.kinney@intel.com</a>> Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in high 32bit of MEM64.<o:p></o:p> </div> </div> <o:p> </o:p> Zarcd,<o:p></o:p> I can understand that this patch is needed for some buggy pci devices whose VF bar behaves strangely. Incompatible PCI protocol can only deal with normal PCI bar. And this patch is just to enhance the error handling logic.<o:p></o:p> <o:p> </o:p> Can you please use below code for error handling?<o:p></o:p> + PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown<o:p></o:p> <o:p> </o:p> I understand that your change is aligned to existing error handling in the beginning of PciIovParseVfBar().<o:p></o:p> But that logic runs before PciIoDevice->VfPciBar[BarIndex].BarType is assigned.<o:p></o:p> The key is to reset the BarType to PciBarTypeUnknown so that the resource summary code doesn’t count this bar.<o:p></o:p> <o:p> </o:p> Thanks,<o:p></o:p> Ray<o:p></o:p> <o:p> </o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Zhong, Zarcd <<a href="mailto:zarcd.zhong@intel.com">zarcd.zhong@intel.com</a>> Sent: Monday, January 4, 2021 5:48 PM To: <a href="mailto:devel@edk2.groups.io">devel@edk2.groups.io</a> Cc: Ni, Ray <<a href="mailto:ray.ni@intel.com">ray.ni@intel.com</a>>; Wu, Hao A <<a href="mailto:hao.a.wu@intel.com">hao.a.wu@intel.com</a>> Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in high 32bit of MEM64.<o:p></o:p> </div> </div> <o:p> </o:p> From 7518212a85269e486d06dcea927a3d34e23372c2 Mon Sep 17 00:00:00 2001<o:p></o:p> From: Zarcd Zhong <<a href="mailto:zarcd.zhong@intel.com">zarcd.zhong@intel.com</a>><o:p></o:p> Date: Mon, 4 Jan 2021 17:32:54 +0800<o:p></o:p> Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in high 32bit of MEM64.<o:p></o:p> <o:p> </o:p> REF: <a href="https://bugzilla.tianocore.org/show_bug.cgi?id=3149"> https://bugzilla.tianocore.org/show_bug.cgi?id=3149</a><o:p></o:p> <o:p> </o:p> Clear length and alignment for low 32bit of MEM64 BAR if sizing fail in high 32bit.<o:p></o:p> <o:p> </o:p> Cc: Ray Ni <<a href="mailto:ray.ni@intel.com">ray.ni@intel.com</a>><o:p></o:p> Cc: Hao A Wu <<a href="mailto:hao.a.wu@intel.com">hao.a.wu@intel.com</a>><o:p></o:p> </div> </div> </div> </body> </html> <div width="1" style="color:white;clear:both">_._,_._,_</div> <hr> Groups.io Links: You receive all messages sent to this group. <a target="_blank" href="https://edk2.groups.io/g/devel/message/70324">View/Reply Online (#70324)</a> | | <a target="_blank" href="https://groups.io/mt/79438989/1813853">Mute This Topic</a> | <a href="https://edk2.groups.io/g/devel/post">New Topic</a> <a href="https://edk2.groups.io/g/devel/editsub/1813853">Your Subscription</a> | <a href="mailto:devel+owner@edk2.groups.io">Contact Group Owner</a> | <a href="https://edk2.groups.io/g/devel/unsub">Unsubscribe</a> [edk2-devel-archive@redhat.com] <div width="1" style="color:white;clear:both">_._,_._,_</div>