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Great commit message, thanks Sunil!</div>
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Maintainers, please take a look and let us know if there's any other concern.</div>
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This patch lets us build the RISC-V platforms using modern toolchains that are provided directly by the distributions, rather than building your own from source.</div>
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Thanks,</div>
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Daniel<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Sunil V L <sunilvl@ventanamicro.com><br>
<b>Sent:</b> Friday, June 11, 2021 22:08<br>
<b>To:</b> devel@edk2.groups.io <devel@edk2.groups.io><br>
<b>Cc:</b> Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; Schaefer, Daniel <daniel.schaefer@hpe.com>; Bob Feng <bob.c.feng@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; Yuwei Chen <yuwei.chen@intel.com>; Heinrich Schuchardt <xypron.glpk@gmx.de><br>
<b>Subject:</b> Re: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations</font>
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<div class="PlainText">Hi,<br>
I just edited the commit message to indicate the module and CC the<br>
maintainers. Could I get the feedback please?<br>
Thanks<br>
Sunil<br>
<br>
On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote:<br>
> Ref: <a href="https://bugzilla.tianocore.org/show_bug.cgi?id=3096">https://bugzilla.tianocore.org/show_bug.cgi?id=3096</a>
<br>
> <br>
> This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20<br>
> relocations generated by PIE enabled compiler. This also needed<br>
> changes to R_RISCV_32 and R_RISCV_64 relocations as explained in<br>
> <a href="https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710">https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710</a><br>
> <br>
> Changes in v2:<br>
> - Addressed Daniel's comment on formatting<br>
> <br>
> Testing:<br>
> 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.<br>
> 2) Debian 10.2.0 and booted QEMU virt model.<br>
> 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.<br>
> <br>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com><br>
> <br>
> Acked-by: Abner Chang <abner.chang@hpe.com><br>
> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com><br>
> Tested-by: <daniel.schaefer@hpe.com><br>
> <br>
> Cc: Bob Feng <bob.c.feng@intel.com><br>
> Cc: Liming Gao <gaoliming@byosoft.com.cn><br>
> Cc: Yuwei Chen <yuwei.chen@intel.com><br>
> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de><br>
> ---<br>
> BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++----<br>
> 1 file changed, 38 insertions(+), 6 deletions(-)<br>
> <br>
> diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c<br>
> index d097db8632..d684318269 100644<br>
> --- a/BaseTools/Source/C/GenFw/Elf64Convert.c<br>
> +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c<br>
> @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;<br>
> STATIC UINT8 *mRiscVPass1Targ = NULL;<br>
> STATIC Elf_Shdr *mRiscVPass1Sym = NULL;<br>
> STATIC Elf64_Half mRiscVPass1SymSecIndex = 0;<br>
> +STATIC INT32 mRiscVPass1Offset;<br>
> +STATIC INT32 mRiscVPass1GotFixup;<br>
> <br>
> //<br>
> // Initialization Function<br>
> @@ -479,11 +481,11 @@ WriteSectionRiscV64 (<br>
> break;<br>
> <br>
> case R_RISCV_32:<br>
> - *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);<br>
> + *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;<br>
> break;<br>
> <br>
> case R_RISCV_64:<br>
> - *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];<br>
> + *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;<br>
> break;<br>
> <br>
> case R_RISCV_HI20:<br>
> @@ -533,6 +535,18 @@ WriteSectionRiscV64 (<br>
> mRiscVPass1SymSecIndex = 0;<br>
> break;<br>
> <br>
> + case R_RISCV_GOT_HI20:<br>
> + Value = (Sym->st_value - Rel->r_offset);<br>
> + mRiscVPass1Offset = RV_X(Value, 0, 12);<br>
> + Value = RV_X(Value, 12, 20);<br>
> + *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));<br>
> +<br>
> + mRiscVPass1Targ = Targ;<br>
> + mRiscVPass1Sym = SymShdr;<br>
> + mRiscVPass1SymSecIndex = Sym->st_shndx;<br>
> + mRiscVPass1GotFixup = 1;<br>
> + break;<br>
> +<br>
> case R_RISCV_PCREL_HI20:<br>
> mRiscVPass1Targ = Targ;<br>
> mRiscVPass1Sym = SymShdr;<br>
> @@ -545,11 +559,17 @@ WriteSectionRiscV64 (<br>
> if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {<br>
> int i;<br>
> Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));<br>
> - Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));<br>
> - if(Value & (RISCV_IMM_REACH/2)) {<br>
> - Value |= ~(RISCV_IMM_REACH-1);<br>
> +<br>
> + if(mRiscVPass1GotFixup) {<br>
> + Value = (UINT32)(mRiscVPass1Offset);<br>
> + } else {<br>
> + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));<br>
> + if(Value & (RISCV_IMM_REACH/2)) {<br>
> + Value |= ~(RISCV_IMM_REACH-1);<br>
> + }<br>
> }<br>
> Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];<br>
> +<br>
> if(-2048 > (INT32)Value) {<br>
> i = (((INT32)Value * -1) / 4096);<br>
> Value2 -= i;<br>
> @@ -569,12 +589,21 @@ WriteSectionRiscV64 (<br>
> }<br>
> }<br>
> <br>
> - *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));<br>
> + if(mRiscVPass1GotFixup) {<br>
> + *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20)<br>
> + | (RV_X(*(UINT32*)Targ, 0, 20));<br>
> + /* Convert LD instruction to ADDI */<br>
> + *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13);<br>
> + } else {<br>
> + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));<br>
> + }<br>
> *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));<br>
> }<br>
> mRiscVPass1Sym = NULL;<br>
> mRiscVPass1Targ = NULL;<br>
> mRiscVPass1SymSecIndex = 0;<br>
> + mRiscVPass1Offset = 0;<br>
> + mRiscVPass1GotFixup = 0;<br>
> break;<br>
> <br>
> case R_RISCV_ADD64:<br>
> @@ -586,6 +615,7 @@ WriteSectionRiscV64 (<br>
> case R_RISCV_GPREL_I:<br>
> case R_RISCV_GPREL_S:<br>
> case R_RISCV_CALL:<br>
> + case R_RISCV_CALL_PLT:<br>
> case R_RISCV_RVC_BRANCH:<br>
> case R_RISCV_RVC_JUMP:<br>
> case R_RISCV_RELAX:<br>
> @@ -1528,6 +1558,7 @@ WriteRelocations64 (<br>
> case R_RISCV_GPREL_I:<br>
> case R_RISCV_GPREL_S:<br>
> case R_RISCV_CALL:<br>
> + case R_RISCV_CALL_PLT:<br>
> case R_RISCV_RVC_BRANCH:<br>
> case R_RISCV_RVC_JUMP:<br>
> case R_RISCV_RELAX:<br>
> @@ -1537,6 +1568,7 @@ WriteRelocations64 (<br>
> case R_RISCV_SET16:<br>
> case R_RISCV_SET32:<br>
> case R_RISCV_PCREL_HI20:<br>
> + case R_RISCV_GOT_HI20:<br>
> case R_RISCV_PCREL_LO12_I:<br>
> break;<br>
> <br>
> -- <br>
> 2.25.1<br>
> <br>
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