<div dir="ltr">The MCH BAR field is the 38:15 bit range. Are the higher bits guaranteed to be clear, so that a 32 bit read is sufficient?<br clear="all"><div><div><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature"><div dir="ltr"><div><br></div><div>Best regards,</div><div>Benjamin</div></div></div></div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Aug 16, 2021 at 11:53 AM Michael Kubacki <<a href="mailto:mikuback@linux.microsoft.com">mikuback@linux.microsoft.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Reviewed-by: Michael Kubacki <<a href="mailto:michael.kubacki@microsoft.com" target="_blank">michael.kubacki@microsoft.com</a>><br>
<br>
On 8/16/2021 12:02 AM, Nate DeSimone wrote:<br>
> The default value for CpuConfigLibPreMemConfig->PeciC10Reset<br>
> should be 1 so that Peci Reset on C10 exit is disabled.<br>
><br>
> Other bug fixes in<br>
> KabylakeSiliconPkg\Cpu\Library\PeiCpuPolicyLibPreMem\PeiCpuPolicyLib.c<br>
><br>
> 1. PCI configuration space can only be read 32-bits at a time.<br>
> Converted MmioRead64 to MmioRead32.<br>
> 2. Added a RShiftU64() call to prevent compiler instrinsics from<br>
> being inserted. Since this is a 64-bit integer shift done in<br>
> IA-32 mode it is possible for intrinsic calls to be added.<br>
><br>
> Cc: Chasel Chiu <<a href="mailto:chasel.chiu@intel.com" target="_blank">chasel.chiu@intel.com</a>><br>
> Cc: Sai Chaganty <<a href="mailto:rangasai.v.chaganty@intel.com" target="_blank">rangasai.v.chaganty@intel.com</a>><br>
> Cc: Benjamin Doron <<a href="mailto:benjamin.doron00@gmail.com" target="_blank">benjamin.doron00@gmail.com</a>><br>
> Cc: Michael Kubacki <<a href="mailto:michael.kubacki@microsoft.com" target="_blank">michael.kubacki@microsoft.com</a>><br>
> Signed-off-by: Nate DeSimone <<a href="mailto:nathaniel.l.desimone@intel.com" target="_blank">nathaniel.l.desimone@intel.com</a>><br>
> ---<br>
> .../Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c | 9 ++++++---<br>
> 1 file changed, 6 insertions(+), 3 deletions(-)<br>
><br>
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c<br>
> index 35041322a7..85baa46208 100644<br>
> --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c<br>
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c<br>
> @@ -1,7 +1,7 @@<br>
> /** @file<br>
> This file is PeiCpuPolicy library.<br>
> <br>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR><br>
> +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR><br>
> SPDX-License-Identifier: BSD-2-Clause-Patent<br>
> <br>
> **/<br>
> @@ -45,13 +45,14 @@ LoadCpuConfigLibPreMemConfigDefault (<br>
> CpuConfigLibPreMemConfig->BootFrequency = 1; // Maximum non-turbo Performance<br>
> CpuConfigLibPreMemConfig->ActiveCoreCount = 0; // All cores active<br>
> CpuConfigLibPreMemConfig->VmxEnable = CPU_FEATURE_ENABLE;<br>
> - CpuConfigLibPreMemConfig->CpuRatio = ((AsmReadMsr64 (MSR_PLATFORM_INFO) >> N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK);<br>
> + CpuConfigLibPreMemConfig->CpuRatio = RShiftU64 (AsmReadMsr64 (MSR_PLATFORM_INFO), N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK;<br>
> +<br>
> ///<br>
> /// FCLK Frequency<br>
> ///<br>
> CpuFamily = GetCpuFamily();<br>
> CpuSku = GetCpuSku();<br>
> - MchBar = MmioRead64 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR) &~BIT0;<br>
> + MchBar = MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR) &~BIT0;<br>
> if (IsPchLinkDmi (CpuFamily) && (MmioRead16 (MmPciBase (SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, SA_PEG10_FUN_NUM) + PCI_VENDOR_ID_OFFSET) != 0xFFFF)) {<br>
> PegDisabled = MmioRead32 ((UINTN) MchBar + R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET) & BIT3;<br>
> } else {<br>
> @@ -67,6 +68,8 @@ LoadCpuConfigLibPreMemConfigDefault (<br>
> } else {<br>
> CpuConfigLibPreMemConfig->FClkFrequency = 0; // 800MHz<br>
> }<br>
> +<br>
> + CpuConfigLibPreMemConfig->PeciC10Reset = 1; // Disables Peci Reset on C10 exit<br>
> }<br>
> <br>
> /**<br>
<br>
</blockquote></div>
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