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<span style="background-color:rgb(255, 255, 255);display:inline !important">Reviewed-by: Andrei Warkentin <awarkentin@vmware.com></span><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Jeremy Linton <jeremy.linton@arm.com><br>
<b>Sent:</b> Thursday, August 19, 2021 11:16 PM<br>
<b>To:</b> devel@edk2.groups.io <devel@edk2.groups.io><br>
<b>Cc:</b> pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com><br>
<b>Subject:</b> [PATCH v3 3/7] Platform/RaspberryPi: Add PCIe SSDT</font>
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<div class="PlainText">Since we plan on toggling between XHCI and PCI the PCI<br>
root needs to be in its own SSDT. This is all thats needed<br>
of UEFI. The SMC conduit is provided directly to the running<br>
OS. When the OS detects this PCIe port on a machine without<br>
a MCFG it attempts to connect to the SMC conduit. The RPi<br>
definition doesn't have any power mgmt, and only provides<br>
a description of the root port.<br>
<br>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com><br>
---<br>
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +<br>
Platform/RaspberryPi/AcpiTables/Pci.asl | 161 +++++++++++++++++++++<br>
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +<br>
3 files changed, 170 insertions(+)<br>
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl<br>
<br>
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf<br>
index f3e8d950c1..da2a6db85f 100644<br>
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf<br>
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf<br>
@@ -39,6 +39,7 @@<br>
Pptt.aslc<br>
SsdtThermal.asl<br>
Xhci.asl<br>
+ Pci.asl<br>
<br>
[Packages]<br>
ArmPkg/ArmPkg.dec<br>
@@ -59,6 +60,8 @@<br>
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase<br>
gArmTokenSpaceGuid.PcdGicDistributorBase<br>
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr<br>
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr<br>
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen<br>
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase<br>
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress<br>
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress<br>
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl<br>
new file mode 100644<br>
index 0000000000..dc2bd7bc9e<br>
--- /dev/null<br>
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl<br>
@@ -0,0 +1,161 @@<br>
+/** @file<br>
+ *<br>
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.<br>
+ * Copyright (c) 2021 Arm<br>
+ *<br>
+ * SPDX-License-Identifier: BSD-2-Clause-Patent<br>
+ *<br>
+ **/<br>
+<br>
+#include <IndustryStandard/Bcm2711.h><br>
+<br>
+#include "AcpiTables.h"<br>
+<br>
+/*<br>
+ * The following can be used to remove parenthesis from<br>
+ * defined macros that the compiler complains about.<br>
+ */<br>
+#define ISOLATE_ARGS(...) __VA_ARGS__<br>
+#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x<br>
+<br>
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)<br>
+#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)<br>
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)<br>
+<br>
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)<br>
+{<br>
+ Scope (\_SB_)<br>
+ {<br>
+ Device(PCI0)<br>
+ {<br>
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge<br>
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge<br>
+ Name(_SEG, Zero) // PCI Segment Group number<br>
+ Name(_BBN, Zero) // PCI Base Bus Number<br>
+ Name(_CCA, 0) // Mark the PCI noncoherent<br>
+<br>
+ // PCIe can only DMA to first 3GB with early SOC's<br>
+ // But we keep the restriction on the later ones<br>
+ // To avoid DMA translation problems.<br>
+ Name (_DMA, ResourceTemplate() {<br>
+ QWordMemory (ResourceProducer,<br>
+ ,<br>
+ MinFixed,<br>
+ MaxFixed,<br>
+ NonCacheable,<br>
+ ReadWrite,<br>
+ 0x0,<br>
+ 0x0, // MIN<br>
+ 0xbfffffff, // MAX<br>
+ 0x0, // TRA<br>
+ 0xc0000000, // LEN<br>
+ ,<br>
+ ,<br>
+ )<br>
+ })<br>
+<br>
+ // PCI Routing Table<br>
+ Name(_PRT, Package() {<br>
+ Package (4) { 0x0000FFFF, 0, zero, 175 },<br>
+ Package (4) { 0x0000FFFF, 1, zero, 176 },<br>
+ Package (4) { 0x0000FFFF, 2, zero, 177 },<br>
+ Package (4) { 0x0000FFFF, 3, zero, 178 }<br>
+ })<br>
+<br>
+ // Root complex resources<br>
+ Method (_CRS, 0, Serialized) {<br>
+ Name (RBUF, ResourceTemplate () {<br>
+<br>
+ // bus numbers assigned to this root<br>
+ WordBusNumber (<br>
+ ResourceProducer,<br>
+ MinFixed, MaxFixed, PosDecode,<br>
+ 0, // AddressGranularity<br>
+ 0, // AddressMinimum - Minimum Bus Number<br>
+ 255, // AddressMaximum - Maximum Bus Number<br>
+ 0, // AddressTranslation - Set to 0<br>
+ 256 // RangeLength - Number of Busses<br>
+ )<br>
+<br>
+ // 32-bit mmio window in 64-bit addr<br>
+ QWordMemory (<br>
+ ResourceProducer, PosDecode,<br>
+ MinFixed, MaxFixed,<br>
+ NonCacheable, ReadWrite, // cacheable<br>
+ 0x00000000, // Granularity<br>
+ 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN<br>
+ 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN<br>
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW<br>
+ 2 // SANITIZED_PCIE_MMIO_LEN + 1<br>
+ ,,,MMI1,,TypeTranslation<br>
+ )<br>
+<br>
+ // root port registers, not to be used if SMCCC is utilized<br>
+ QWordMemory (<br>
+ ResourceConsumer, ,<br>
+ MinFixed, MaxFixed,<br>
+ NonCacheable, ReadWrite, // cacheable<br>
+ 0x00000000, // Granularity<br>
+ 0xFD500000, // Root port begin<br>
+ 0xFD509FFF, // Root port end<br>
+ 0x00000000, // no translation<br>
+ 0x0000A000, // size<br>
+ ,,<br>
+ )<br>
+ }) // end Name(RBUF)<br>
+<br>
+ // Work around ASL's inability to add in a resource definition<br>
+ // or for that matter compute the min,max,len properly<br>
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)<br>
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)<br>
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)<br>
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)<br>
+ Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)<br>
+ Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)<br>
+ Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)<br>
+ Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)<br>
+<br>
+ Return (RBUF)<br>
+ } // end Method(_CRS)<br>
+<br>
+ // OS Control Handoff<br>
+ Name(SUPP, Zero) // PCI _OSC Support Field value<br>
+ Name(CTRL, Zero) // PCI _OSC Control Field value<br>
+<br>
+ // See [1] 6.2.10, [2] 4.5<br>
+ Method(_OSC,4) {<br>
+ // Note, This code is very similar to the code in the PCIe firmware<br>
+ // specification which can be used as a reference<br>
+ // Check for proper UUID<br>
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {<br>
+ // Create DWord-adressable fields from the Capabilities Buffer<br>
+ CreateDWordField(Arg3,0,CDW1)<br>
+ CreateDWordField(Arg3,4,CDW2)<br>
+ CreateDWordField(Arg3,8,CDW3)<br>
+ // Save Capabilities DWord2 & 3<br>
+ Store(CDW2,SUPP)<br>
+ Store(CDW3,CTRL)<br>
+ // Mask out Native HotPlug<br>
+ And(CTRL,0x1E,CTRL)<br>
+ // Always allow native PME, AER (no dependencies)<br>
+ // Never allow SHPC (no SHPC controller in this system)<br>
+ And(CTRL,0x1D,CTRL)<br>
+<br>
+ If(LNotEqual(Arg1,One)) { // Unknown revision<br>
+ Or(CDW1,0x08,CDW1)<br>
+ }<br>
+<br>
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked<br>
+ Or(CDW1,0x10,CDW1)<br>
+ }<br>
+ // Update DWORD3 in the buffer<br>
+ Store(CTRL,CDW3)<br>
+ Return(Arg3)<br>
+ } Else {<br>
+ Or(CDW1,4,CDW1) // Unrecognized UUID<br>
+ Return(Arg3)<br>
+ }<br>
+ } // End _OSC<br>
+ } // PCI0<br>
+ } //end scope sb<br>
+} //end definition block<br>
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c<br>
index 7c5786303d..4c40820858 100644<br>
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c<br>
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c<br>
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {<br>
PcdToken(PcdXhciPci),<br>
NULL<br>
},<br>
+ {<br>
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),<br>
+ PcdToken(PcdXhciPci),<br>
+ 0,<br>
+ NULL<br>
+ },<br>
#endif<br>
{ // DSDT<br>
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),<br>
-- <br>
2.13.7<br>
<br>
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