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<span style="background-color:rgb(255, 255, 255);display:inline !important">Reviewed-by: Andrei Warkentin <awarkentin@vmware.com></span><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Jeremy Linton <jeremy.linton@arm.com><br>
<b>Sent:</b> Thursday, August 19, 2021 11:16 PM<br>
<b>To:</b> devel@edk2.groups.io <devel@edk2.groups.io><br>
<b>Cc:</b> pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com><br>
<b>Subject:</b> [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor</font>
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<div class="PlainText">The existing code fails to create/finish configuring the<br>
pcie subsystem if it fails to get a linkup. This is reasonable<br>
on the RPi4 because it generally won't happen, and the OS<br>
could not see the root port. Now that the OS can see the<br>
root port, its a bit odd if it only shows up when<br>
something is plugged into the first slot. Lets move the<br>
link up check into the config accessor where it will be used<br>
to restrict sending CFG TLP's out the port when nothing is<br>
plugged in. Thus avoiding a SERROR during probe.<br>
<br>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com><br>
---<br>
.../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c | 5 -----<br>
.../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 7 +++++++<br>
2 files changed, 7 insertions(+), 5 deletions(-)<br>
<br>
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c<br>
index 8587d2d36d..4d4c584726 100644<br>
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c<br>
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c<br>
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (<br>
} while (((Data & 0x30) != 0x030) && (Timeout));<br>
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));<br>
<br>
- if ((Data & 0x30) != 0x30) {<br>
- DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));<br>
- return EFI_DEVICE_ERROR;<br>
- }<br>
-<br>
if ((Data & 0x80) != 0x80) {<br>
DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));<br>
return EFI_UNSUPPORTED;<br>
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c<br>
index 6d15e82fa2..b627e5730b 100644<br>
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c<br>
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c<br>
@@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase (<br>
return 0xFFFFFFFF;<br>
}<br>
<br>
+ /* Don't probe slots if the link is down */<br>
+ Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);<br>
+ if ((Data & 0x30) != 0x30) {<br>
+ DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));<br>
+ return 0xFFFFFFFF;<br>
+ }<br>
+<br>
MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);<br>
mPciSegmentLastAccess = Address;<br>
}<br>
-- <br>
2.13.7<br>
<br>
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