<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style> </head> <body dir="ltr"> <div style="font-family: Consolas, Courier, monospace; font-size: 12pt; color: rgb(0, 0, 0);"> Reviewed-by: Andrei Warkentin <awarkentin@vmware.com> </div> <div id="appendonsend"></div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr">From: Jeremy Linton <jeremy.linton@arm.com> Sent: Thursday, August 19, 2021 11:16 PM To: devel@edk2.groups.io <devel@edk2.groups.io> Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>; René Treffer <treffer+groups.io@measite.de> Subject: [PATCH v3 4/7] Silicon/Broadcom/Bcm27xx: Relax PCIe device restriction <div> </div> </div> <div class="BodyFragment"> <div class="PlainText">The CM4 has an actual PCIe slot, so the device filtering need to be a little less restrictive WRT busses with more than 1 device given that switches can now appear in the topology. Since it is possible to start numbering the busses with a non-zero value, the bus restriction should be based on the secondary side of the root port. This isn't likely but its better than hard-coding the limit. Suggested-by: René Treffer <treffer+groups.io@measite.de> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> --- .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c index 44ce3b4b99..6d15e82fa2 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c @@ -19,6 +19,7 @@ #include <Library/PciSegmentLib.h> #include <Library/UefiLib.h> #include <IndustryStandard/Bcm2711.h> +#include <IndustryStandard/Pci30.h> typedef enum { PciCfgWidthUint8 = 0, @@ -78,6 +79,9 @@ PciSegmentLibGetConfigBase ( UINT64 Base; UINT64 Offset; UINT32 Dev; + UINT32 Bus; + UINT32 Data; + UINT32 HostPortSec; Base = PCIE_REG_BASE; Offset = Address & 0xFFF; /* Pick off the 4k register offset */ @@ -89,17 +93,20 @@ PciSegmentLibGetConfigBase ( Base += PCIE_EXT_CFG_DATA; if (mPciSegmentLastAccess != Address) { Dev = EFI_PCI_ADDR_DEV (Address); + Bus = EFI_PCI_ADDR_BUS (Address); + HostPortSec = MmioRead8 (PCIE_REG_BASE + + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); + /* - * Scan things out directly rather than translating the "bus" to a device, etc.. - * only we need to limit each bus to a single device. + * There can only be a single device on bus 1 (downstream of root). + * Subsequent busses (behind a PCIe switch) can have more. */ - if (Dev < 1) { - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); - mPciSegmentLastAccess = Address; - } else { - mPciSegmentLastAccess = 0; + if (Dev > 0 && (Bus <= HostPortSec)) { return 0xFFFFFFFF; } + + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); + mPciSegmentLastAccess = Address; } } return Base + Offset; -- 2.13.7 </div> </div> </body> </html> <div width="1" style="color:white;clear:both">_._,_._,_</div> <hr> Groups.io Links: You receive all messages sent to this group. <a target="_blank" href="https://edk2.groups.io/g/devel/message/79652">View/Reply Online (#79652)</a> | | <a target="_blank" href="https://groups.io/mt/85014307/1813853">Mute This Topic</a> | <a href="https://edk2.groups.io/g/devel/post">New Topic</a> <a href="https://edk2.groups.io/g/devel/editsub/1813853">Your Subscription</a> | <a href="mailto:devel+owner@edk2.groups.io">Contact Group Owner</a> | <a href="https://edk2.groups.io/g/devel/unsub">Unsubscribe</a> [edk2-devel-archive@redhat.com] <div width="1" style="color:white;clear:both">_._,_._,_</div>