<div dir="ltr"><div class="gmail_default" style="font-family:trebuchet ms,sans-serif">Reviewed-by Sean Rhodes <sean@starlabs.systems></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, 30 Mar 2022 at 19:29, Sean Rhodes <sean@starlabs.systems> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">From: Lean Sheng Tan <<a href="mailto:sheng.tan@9elements.com" target="_blank">sheng.tan@9elements.com</a>><br>
<br>
Don't assume a 64bit register always holds an address greater than 4GB.<br>
Check the value in the register and decide which Aperature it should be<br>
assigned to.<br>
<br>
Fixes assertion<br>
"ASSERT [PciHostBridgeDxe] Bridge->MemAbove4G.Base >= 0x0000000100000000ULL".<br>
<br>
Tested with coreboot as bootloader on platforms that have PCI resource<br>
above 4GiB and on platforms that don't have resource above 4GiB.<br>
<br>
Cc: Guo Dong <<a href="mailto:guo.dong@intel.com" target="_blank">guo.dong@intel.com</a>><br>
Cc: Ray Ni <<a href="mailto:ray.ni@intel.com" target="_blank">ray.ni@intel.com</a>><br>
Cc: Maurice Ma <<a href="mailto:maurice.ma@intel.com" target="_blank">maurice.ma@intel.com</a>><br>
Cc: Benjamin You <<a href="mailto:benjamin.you@intel.com" target="_blank">benjamin.you@intel.com</a>><br>
Cc: Sean Rhodes <sean@starlabs.systems><br>
Signed-off-by: Patrick Rudolph <<a href="mailto:patrick.rudolph@9elements.com" target="_blank">patrick.rudolph@9elements.com</a>><br>
---<br>
 .../Library/PciHostBridgeLib/PciHostBridgeSupport.c | 13 +++++++++----<br>
 1 file changed, 9 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c<br>
index 8a890b6b53..e1faa24ae7 100644<br>
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c<br>
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c<br>
@@ -354,14 +354,19 @@ ScanForRootBridges (<br>
           Base  = ((UINT32)Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;<br>
           Limit = (((UINT32)Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)<br>
                    << 16) | 0xfffff;<br>
-          MemAperture = &Mem;<br>
+<br>
           if (Value == BIT0) {<br>
-            Base       |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);<br>
-            Limit      |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);<br>
-            MemAperture = &MemAbove4G;<br>
+            Base  |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);<br>
+            Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);<br>
           }<br>
<br>
           if ((Base > 0) && (Base < Limit)) {<br>
+            if (Base < BASE_4GB) {<br>
+              MemAperture = &Mem;<br>
+            } else {<br>
+              MemAperture = &MemAbove4G;<br>
+            }<br>
+<br>
             if (MemAperture->Base > Base) {<br>
               MemAperture->Base = Base;<br>
             }<br>
-- <br>
2.32.0<br>
<br>
</blockquote></div>


 <div width="1" style="color:white;clear:both">_._,_._,_</div> <hr>   Groups.io Links:<p>   You receive all messages sent to this group.    <p> <a target="_blank" href="https://edk2.groups.io/g/devel/message/88267">View/Reply Online (#88267)</a> |    |  <a target="_blank" href="https://groups.io/mt/90138164/1813853">Mute This Topic</a>  | <a href="https://edk2.groups.io/g/devel/post">New Topic</a><br>    <a href="https://edk2.groups.io/g/devel/editsub/1813853">Your Subscription</a> | <a href="mailto:devel+owner@edk2.groups.io">Contact Group Owner</a> |  <a href="https://edk2.groups.io/g/devel/unsub">Unsubscribe</a>  [edk2-devel-archive@redhat.com]<br> <div width="1" style="color:white;clear:both">_._,_._,_</div>