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<p class="MsoNormal">Hi Benjamin,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Yeah the GMBUS I2C controller gets very temperamental if there is a protocol error. I think you have to go a full reset of the controller to get it back into a working state. I haven’t figured that out completely in my POC code yet so that
is one of the things I suspect you will run into early on <span style="font-family:"Segoe UI Emoji",sans-serif">
😊</span>.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I took a quick look at your proposal, looks good!<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Best Regards,<o:p></o:p></p>
<p class="MsoNormal">Nate<o:p></o:p></p>
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<p class="MsoNormal"><b>From:</b> devel@edk2.groups.io <devel@edk2.groups.io> <b>
On Behalf Of </b>Benjamin Doron<br>
<b>Sent:</b> Friday, April 8, 2022 11:33 AM<br>
<b>To:</b> Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; devel@edk2.groups.io<br>
<b>Subject:</b> Re: [edk2-devel] GSoC 2022: Add S3 resume support to MinPlatform<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Hi Nate,<br>
Thanks! I've looked at the basics of I2C, but I've seen from the iGFX PRM that GMBUS implements some registers and error handling the NAKs differently, but I guess that I'll be dealing with that later.<br>
<br>
Yeah, I was thinking that if we wanted debug up as soon as possible, then the iGFX BAR and P2SB GPIOs would have to be programmed, so that sounds about right. Synchronising with the FSP's config is probably important too, but I suppose you implemented that/we'll
see?<br>
<br>
For now, I have a proposal at <a href="https://docs.google.com/document/d/1CyyerMfPwvZxkBjfE_-H1OlkZPxH98uqpmb9tBAV_ps" target="_blank">
https://docs.google.com/document/d/1CyyerMfPwvZxkBjfE_-H1OlkZPxH98uqpmb9tBAV_ps</a>.<br>
<br>
Best regards,<br>
Benjamin <o:p></o:p></p>
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