<div>According the Xhci Spec, TRB Rings may be larger than a Page, however they shall not cross a 64K byte boundary, so allocate the rings at 64K aligned address to avoid they crossing a 64K byte boundary.</div>
<div> </div>
<div>Signed-off-by: jdzhang <jdzhang@kunluntech.com.cn></div>
<div>---</div>
<div> MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 112 +++++++++++------------</div>
<div> MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h | 4 +</div>
<div> 2 files changed, 56 insertions(+), 60 deletions(-)</div>
<div> </div>
<div>diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c</div>
<div>index 4ae0297607..b020bb064b 100644</div>
<div>--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c</div>
<div>+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c</div>
<div>@@ -473,7 +473,6 @@ XhcInitSched (</div>
<div> {</div>
<div> VOID *Dcbaa;</div>
<div> EFI_PHYSICAL_ADDRESS DcbaaPhy;</div>
<div>- UINT64 CmdRing;</div>
<div> EFI_PHYSICAL_ADDRESS CmdRingPhy;</div>
<div> UINTN Entries;</div>
<div> UINT32 MaxScratchpadBufs;</div>
<div>@@ -602,8 +601,7 @@ XhcInitSched (</div>
<div> // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.</div>
<div> // So we set RCS as inverted PCS init value to let Command Ring empty</div>
<div> //</div>
<div>- CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;</div>
<div>- CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);</div>
<div>+ CmdRingPhy = (UINT64)(UINTN)Xhc->CmdRing.RingPhy;</div>
<div> ASSERT ((CmdRingPhy & 0x3F) == 0);</div>
<div> CmdRingPhy |= XHC_CRCR_RCS;</div>
<div> //</div>
<div>@@ -790,23 +788,28 @@ CreateEventRing (</div>
<div> EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;</div>
<div> UINTN Size;</div>
<div> EFI_PHYSICAL_ADDRESS ERSTPhy;</div>
<div>- EFI_PHYSICAL_ADDRESS DequeuePhy;</div>
<div>+ EFI_STATUS Status;</div>
<div> </div>
<div> ASSERT (EventRing != NULL);</div>
<div>-</div>
<div>+ </div>
<div>+ //To meet the 64KB Boundary Requirement in xhci spec chapter 6 Table 6-1, allocate the Ring segments at 64K aligned address.</div>
<div> Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;</div>
<div>- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);</div>
<div>- ASSERT (Buf != NULL);</div>
<div>- ASSERT (((UINTN)Buf & 0x3F) == 0);</div>
<div>- ZeroMem (Buf, Size);</div>
<div>+ Status = UsbHcAllocateAlignedPages (</div>
<div>+ Xhc->PciIo,</div>
<div>+ EFI_SIZE_TO_PAGES (Size),</div>
<div>+ SIZE_64KB,</div>
<div>+ (VOID **) &(EventRing->EventRingSeg0),</div>
<div>+ &(EventRing->EventRingPhy),</div>
<div>+ &(EventRing->EventRingMap)</div>
<div>+ );</div>
<div>+ ASSERT_EFI_ERROR (Status);</div>
<div>+ </div>
<div>+ ZeroMem (EventRing->EventRingSeg0, Size);</div>
<div> </div>
<div>- EventRing->EventRingSeg0 = Buf;</div>
<div> EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;</div>
<div> EventRing->EventRingDequeue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;</div>
<div> EventRing->EventRingEnqueue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;</div>
<div> </div>
<div>- DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);</div>
<div>-</div>
<div> //</div>
<div> // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'</div>
<div> // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.</div>
<div>@@ -821,8 +824,8 @@ CreateEventRing (</div>
<div> </div>
<div> ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *)Buf;</div>
<div> EventRing->ERSTBase = ERSTBase;</div>
<div>- ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);</div>
<div>- ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);</div>
<div>+ ERSTBase->PtrLo = XHC_LOW_32BIT (EventRing->EventRingPhy);</div>
<div>+ ERSTBase->PtrHi = XHC_HIGH_32BIT (EventRing->EventRingPhy);</div>
<div> ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;</div>
<div> </div>
<div> ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size);</div>
<div>@@ -844,12 +847,12 @@ CreateEventRing (</div>
<div> XhcWriteRuntimeReg (</div>
<div> Xhc,</div>
<div> XHC_ERDP_OFFSET,</div>
<div>- XHC_LOW_32BIT ((UINT64)(UINTN)DequeuePhy)</div>
<div>+ XHC_LOW_32BIT ((UINT64)(UINTN)EventRing->EventRingPhy)</div>
<div> );</div>
<div> XhcWriteRuntimeReg (</div>
<div> Xhc,</div>
<div> XHC_ERDP_OFFSET + 4,</div>
<div>- XHC_HIGH_32BIT ((UINT64)(UINTN)DequeuePhy)</div>
<div>+ XHC_HIGH_32BIT ((UINT64)(UINTN)EventRing->EventRingPhy)</div>
<div> );</div>
<div> //</div>
<div> // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)</div>
<div>@@ -888,16 +891,24 @@ CreateTransferRing (</div>
<div> OUT TRANSFER_RING *TransferRing</div>
<div> )</div>
<div> {</div>
<div>- VOID *Buf;</div>
<div>+ UINTN Size;</div>
<div> LINK_TRB *EndTrb;</div>
<div>- EFI_PHYSICAL_ADDRESS PhyAddr;</div>
<div>-</div>
<div>- Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);</div>
<div>- ASSERT (Buf != NULL);</div>
<div>- ASSERT (((UINTN)Buf & 0x3F) == 0);</div>
<div>- ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);</div>
<div>+ EFI_STATUS Status;</div>
<div>+ </div>
<div>+ //To meet the 64KB Boundary Requirement in xhci spec chapter 6 Table 6-1, allocate the Ring segments at 64K aligned address.</div>
<div>+ Size = sizeof (TRB_TEMPLATE) * TrbNum;</div>
<div>+ Status = UsbHcAllocateAlignedPages (</div>
<div>+ Xhc->PciIo,</div>
<div>+ EFI_SIZE_TO_PAGES (Size),</div>
<div>+ SIZE_64KB,</div>
<div>+ (VOID **) &(TransferRing->RingSeg0),</div>
<div>+ &(TransferRing->RingPhy),</div>
<div>+ &(TransferRing->RingMap)</div>
<div>+ );</div>
<div>+ ASSERT_EFI_ERROR (Status);</div>
<div>+ </div>
<div>+ ZeroMem (TransferRing->RingSeg0, Size);</div>
<div> </div>
<div>- TransferRing->RingSeg0 = Buf;</div>
<div> TransferRing->TrbNumber = TrbNum;</div>
<div> TransferRing->RingEnqueue = (TRB_TEMPLATE *)TransferRing->RingSeg0;</div>
<div> TransferRing->RingDequeue = (TRB_TEMPLATE *)TransferRing->RingSeg0;</div>
<div>@@ -907,11 +918,10 @@ CreateTransferRing (</div>
<div> // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to</div>
<div> // point to the first TRB in the ring.</div>
<div> //</div>
<div>- EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));</div>
<div>+ EndTrb = (LINK_TRB *)((UINTN)TransferRing->RingSeg0 + sizeof (TRB_TEMPLATE) * (TrbNum - 1));</div>
<div> EndTrb->Type = TRB_TYPE_LINK;</div>
<div>- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);</div>
<div>- EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);</div>
<div>- EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);</div>
<div>+ EndTrb->PtrLo = XHC_LOW_32BIT (TransferRing->RingPhy);</div>
<div>+ EndTrb->PtrHi = XHC_HIGH_32BIT (TransferRing->RingPhy);</div>
<div> //</div>
<div> // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.</div>
<div> //</div>
<div>@@ -943,7 +953,7 @@ XhcFreeEventRing (</div>
<div> //</div>
<div> // Free EventRing Segment 0</div>
<div> //</div>
<div>- UsbHcFreeMem (Xhc->MemPool, EventRing->EventRingSeg0, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);</div>
<div>+ UsbHcFreeAlignedPages (Xhc->PciIo, (VOID *)(UINTN)EventRing->EventRingSeg0, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER), (VOID *)EventRing->EventRingMap);</div>
<div> </div>
<div> //</div>
<div> // Free ESRT table</div>
<div>@@ -984,7 +994,7 @@ XhcFreeSched (</div>
<div> }</div>
<div> </div>
<div> if (Xhc->CmdRing.RingSeg0 != NULL) {</div>
<div>- UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);</div>
<div>+ UsbHcFreeAlignedPages (Xhc->PciIo, (VOID *)(UINTN)Xhc->CmdRing.RingSeg0, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER), (VOID *)Xhc->CmdRing.RingMap);</div>
<div> Xhc->CmdRing.RingSeg0 = NULL;</div>
<div> }</div>
<div> </div>
<div>@@ -1041,8 +1051,7 @@ IsTransferRingTrb (</div>
<div> if (CheckedTrb->Type == TRB_TYPE_LINK) {</div>
<div> LinkTrb = (LINK_TRB *)CheckedTrb;</div>
<div> PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64)LinkTrb->PtrHi, 32));</div>
<div>- CheckedTrb = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));</div>
<div>- ASSERT (CheckedTrb == Urb->Ring->RingSeg0);</div>
<div>+ ASSERT (PhyAddr == Urb->Ring->RingPhy);</div>
<div> }</div>
<div> }</div>
<div> </div>
<div>@@ -1150,8 +1159,7 @@ XhcCheckUrbResult (</div>
<div> // Need convert pci device address to host address</div>
<div> //</div>
<div> PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32));</div>
<div>- TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));</div>
<div>-</div>
<div>+ TRBPtr = (TRB_TEMPLATE *)((UINTN)(VOID*)Xhc->EventRing.EventRingSeg0 + (UINTN)(PhyAddr - Xhc->EventRing.EventRingPhy));</div>
<div> //</div>
<div> // Update the status of URB including the pending URB, the URB that is currently checked,</div>
<div> // and URBs in the XHCI's async interrupt transfer list.</div>
<div>@@ -1255,7 +1263,7 @@ EXIT:</div>
<div> High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);</div>
<div> XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);</div>
<div> </div>
<div>- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));</div>
<div>+ PhyAddr = Xhc->EventRing.EventRingPhy + (UINT64)((UINTN)(VOID *)(Xhc->EventRing.EventRingDequeue) - (UINTN)(Xhc->EventRing.EventRingSeg0));</div>
<div> </div>
<div> if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) {</div>
<div> //</div>
<div>@@ -2273,11 +2281,7 @@ XhcInitializeDeviceSlot (</div>
<div> //</div>
<div> // Init the DCS(dequeue cycle state) as the transfer ring's CCS</div>
<div> //</div>
<div>- PhyAddr = UsbHcGetPciAddrForHostAddr (</div>
<div>- Xhc->MemPool,</div>
<div>- ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,</div>
<div>- sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER</div>
<div>- );</div>
<div>+ PhyAddr = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingPhy;</div>
<div> InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;</div>
<div> InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);</div>
<div> </div>
<div>@@ -2489,11 +2493,7 @@ XhcInitializeDeviceSlot64 (</div>
<div> //</div>
<div> // Init the DCS(dequeue cycle state) as the transfer ring's CCS</div>
<div> //</div>
<div>- PhyAddr = UsbHcGetPciAddrForHostAddr (</div>
<div>- Xhc->MemPool,</div>
<div>- ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,</div>
<div>- sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER</div>
<div>- );</div>
<div>+ PhyAddr = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingPhy;</div>
<div> InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;</div>
<div> InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);</div>
<div> </div>
<div>@@ -2623,7 +2623,7 @@ XhcDisableSlotCmd (</div>
<div> if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {</div>
<div> RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;</div>
<div> if (RingSeg != NULL) {</div>
<div>- UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);</div>
<div>+ UsbHcFreeAlignedPages (Xhc->PciIo, (VOID *)(UINTN)RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER), ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingMap);</div>
<div> }</div>
<div> </div>
<div> FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);</div>
<div>@@ -2734,7 +2734,7 @@ XhcDisableSlotCmd64 (</div>
<div> if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {</div>
<div> RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;</div>
<div> if (RingSeg != NULL) {</div>
<div>- UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);</div>
<div>+ UsbHcFreeAlignedPages (Xhc->PciIo, (VOID *)(UINTN)RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER),((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingMap);</div>
<div> }</div>
<div> </div>
<div> FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);</div>
<div>@@ -2954,11 +2954,7 @@ XhcInitializeEndpointContext (</div>
<div> continue;</div>
<div> }</div>
<div> </div>
<div>- PhyAddr = UsbHcGetPciAddrForHostAddr (</div>
<div>- Xhc->MemPool,</div>
<div>- ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,</div>
<div>- sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER</div>
<div>- );</div>
<div>+ PhyAddr = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPhy;</div>
<div> PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);</div>
<div> PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;</div>
<div> InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);</div>
<div>@@ -3153,11 +3149,7 @@ XhcInitializeEndpointContext64 (</div>
<div> continue;</div>
<div> }</div>
<div> </div>
<div>- PhyAddr = UsbHcGetPciAddrForHostAddr (</div>
<div>- Xhc->MemPool,</div>
<div>- ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,</div>
<div>- sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER</div>
<div>- );</div>
<div>+ PhyAddr = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPhy;</div>
<div> PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);</div>
<div> PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;</div>
<div> InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);</div>
<div>@@ -3503,7 +3495,7 @@ XhcSetTrDequeuePointer (</div>
<div> // Send stop endpoint command to transit Endpoint from running to stop state</div>
<div> //</div>
<div> ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));</div>
<div>- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));</div>
<div>+ PhyAddr = Urb->Ring->RingPhy + (UINT64)((UINTN)(VOID *)(Xhc->EventRing.EventRingEnqueue) - (UINTN)(Xhc->EventRing.EventRingSeg0));</div>
<div> CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;</div>
<div> CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);</div>
<div> CmdSetTRDeq.CycleBit = 1;</div>
<div>@@ -3661,7 +3653,7 @@ XhcSetInterface (</div>
<div> if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {</div>
<div> RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;</div>
<div> if (RingSeg != NULL) {</div>
<div>- UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);</div>
<div>+ UsbHcFreeAlignedPages (Xhc->PciIo, (VOID *)(UINTN)RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER), ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingMap);</div>
<div> }</div>
<div> </div>
<div> FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);</div>
<div>@@ -3867,7 +3859,7 @@ XhcSetInterface64 (</div>
<div> if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {</div>
<div> RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;</div>
<div> if (RingSeg != NULL) {</div>
<div>- UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);</div>
<div>+ UsbHcFreeAlignedPages (Xhc->PciIo, (VOID *)(UINTN)RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER), ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingMap);</div>
<div> }</div>
<div> </div>
<div> FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);</div>
<div>diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h</div>
<div>index 7c85f7993b..e9792b5941 100644</div>
<div>--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h</div>
<div>+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h</div>
<div>@@ -144,6 +144,8 @@ typedef struct _TRANSFER_RING {</div>
<div> TRB_TEMPLATE *RingEnqueue;</div>
<div> TRB_TEMPLATE *RingDequeue;</div>
<div> UINT32 RingPCS;</div>
<div>+ EFI_PHYSICAL_ADDRESS RingPhy;</div>
<div>+ VOID *RingMap;</div>
<div> } TRANSFER_RING;</div>
<div> </div>
<div> typedef struct _EVENT_RING {</div>
<div>@@ -153,6 +155,8 @@ typedef struct _EVENT_RING {</div>
<div> TRB_TEMPLATE *EventRingEnqueue;</div>
<div> TRB_TEMPLATE *EventRingDequeue;</div>
<div> UINT32 EventRingCCS;</div>
<div>+ EFI_PHYSICAL_ADDRESS EventRingPhy;</div>
<div>+ VOID *EventRingMap;</div>
<div> } EVENT_RING;</div>
<div> </div>
<div> //</div>
<div>-- </div>
<div>2.20.1.windows.1</div>
<div> </div>
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