<div dir="ltr">Hi Andrei,<div>Here it is: <a href="https://github.com/pttuan/edk2/tree/tphan/riscv_mmu">https://github.com/pttuan/edk2/tree/tphan/riscv_mmu</a></div></div> <div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Mar 9, 2023 at 1:34 PM Warkentin, Andrei <<a href="mailto:andrei.warkentin@intel.com">andrei.warkentin@intel.com</a>> wrote: </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="msg1561334815990968971"> <div lang="EN-US" style="overflow-wrap: break-word;"> <div class="m_1561334815990968971WordSection1"> Hi Tuan, Could you share a GitHub link to a branch with the patch set? Somehow my email client is mangling one of your patches where it’s all one giant line of code. A <div> <div style="border-right:none;border-bottom:none;border-left:none;border-top:1pt solid rgb(225,225,225);padding:3pt 0in 0in"> From: Tuan Phan <<a href="mailto:tphan@ventanamicro.com" target="_blank">tphan@ventanamicro.com</a>> Sent: Thursday, March 9, 2023 1:20 PM To: <a href="mailto:devel@edk2.groups.io" target="_blank">devel@edk2.groups.io</a> Cc: Kinney, Michael D <<a href="mailto:michael.d.kinney@intel.com" target="_blank">michael.d.kinney@intel.com</a>>; Gao, Liming <<a href="mailto:gaoliming@byosoft.com.cn" target="_blank">gaoliming@byosoft.com.cn</a>>; Liu, Zhiguang <<a href="mailto:zhiguang.liu@intel.com" target="_blank">zhiguang.liu@intel.com</a>>; <a href="mailto:sunilvl@ventanamicro.com" target="_blank">sunilvl@ventanamicro.com</a>; <a href="mailto:git@danielschaefer.me" target="_blank">git@danielschaefer.me</a>; Warkentin, Andrei <<a href="mailto:andrei.warkentin@intel.com" target="_blank">andrei.warkentin@intel.com</a>> Subject: RE: [PATCH 0/7] RISC-V: Add MMU support </div> </div> Hi All, Any updates on this series? Thanks, <div style="border-right:none;border-bottom:none;border-left:none;border-top:1pt solid rgb(225,225,225);padding:3pt 0in 0in"> From: <a href="mailto:tphan@ventanamicro.com" target="_blank">Tuan Phan</a> Sent: Monday, March 6, 2023 9:33 AM To: <a href="mailto:devel@edk2.groups.io" target="_blank">devel@edk2.groups.io</a> Cc: <a href="mailto:michael.d.kinney@intel.com" target="_blank">michael.d.kinney@intel.com</a>; <a href="mailto:gaoliming@byosoft.com.cn" target="_blank">gaoliming@byosoft.com.cn</a>; <a href="mailto:zhiguang.liu@intel.com" target="_blank"> zhiguang.liu@intel.com</a>; <a href="mailto:sunilvl@ventanamicro.com" target="_blank">sunilvl@ventanamicro.com</a>; <a href="mailto:git@danielschaefer.me" target="_blank">git@danielschaefer.me</a>; <a href="mailto:andrei.warkentin@intel.com" target="_blank"> andrei.warkentin@intel.com</a>; <a href="mailto:tphan@ventanamicro.com" target="_blank">Tuan Phan</a> Subject: [PATCH 0/7] RISC-V: Add MMU support </div> This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to support security booting on RISC-V. There are three parts: 1. Add MMU core to UefiCpuPkg. MMU will be enabled during CpuDxe initialization. 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD if already done. 3. Enable MMU for RiscVVirt platform and populating its device resources in SEC phase. All resources should be populated in HOB or added to GCD by driver before accessing them when MMU enabled. Tuan Phan (7): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices OvmfPkg/RiscVVirt: Enable MMU with SV39 mode MdePkg/Include/Library/BaseLib.h | 5 + .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/Sec/Memory.c | 17 - OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++ OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 10 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 5 + UefiCpuPkg/CpuDxeRiscV64/Mmu.c | 493 ++++++++++++++++++ UefiCpuPkg/CpuDxeRiscV64/Mmu.h | 33 ++ UefiCpuPkg/CpuDxeRiscV64/MmuCore.S | 29 ++ UefiCpuPkg/UefiCpuPkg.dec | 8 + 16 files changed, 676 insertions(+), 32 deletions(-) create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.c create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.h create mode 100644 UefiCpuPkg/CpuDxeRiscV64/MmuCore.S -- 2.25.1 </div> </div> </div></blockquote></div> <div width="1" style="color:white;clear:both">_._,_._,_</div> <hr> Groups.io Links: You receive all messages sent to this group. <a target="_blank" href="https://edk2.groups.io/g/devel/message/101037">View/Reply Online (#101037)</a> | | <a target="_blank" href="https://groups.io/mt/97430547/1813853">Mute This Topic</a> | <a href="https://edk2.groups.io/g/devel/post">New Topic</a> <a href="https://edk2.groups.io/g/devel/editsub/1813853">Your Subscription</a> | <a href="mailto:devel+owner@edk2.groups.io">Contact Group Owner</a> | <a href="https://edk2.groups.io/g/devel/unsub">Unsubscribe</a> [edk2-devel-archive@redhat.com] <div width="1" style="color:white;clear:both">_._,_._,_</div>