<html xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> <meta name="Title" content=""> <meta name="Keywords" content=""> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body bgcolor="white" lang="EN-US" link="#0563C1" vlink="#954F72"> <div class="WordSection1"> Hi folks <o:p> </o:p> I would like to start a discussion about how to support a new cpu feature in libvirt. CAT support is not fully merged into linux kernel yet, the target release is 4.10, and all patches has been merged into linux tip branch. So there won’t be interface/design changes.<o:p></o:p> <o:p></o:p> ## Background<o:p></o:p> Intel RDT is a toolkit to do resource Qos for cpu such as llc(l3) cache, memory bandwidth usage, these fine granularity resource control features are very useful in a cloud environment which will run logs of noisy instances. Currently, Libvirt has supported CAT/MBMT/MBML already, they are only for resource usage monitor, propose to supporting CAT to control VM’s l3 cache quota. <o:p></o:p> ## CAT interface in kernel<o:p></o:p> In kernel, a new resource interface has been introduced under /sys/fs/resctrl, it’s used for resource control, for more information, refer<o:p></o:p> Intel_rdt_ui [ <a href="https://git.kernel.org/cgit/linux/kernel/git/tip/tip.git/tree/Documentation/x86/intel_rdt_ui.txt?h=x86/cache"> https://git.kernel.org/cgit/linux/kernel/git/tip/tip.git/tree/Documentation/x86/intel_rdt_ui.txt?h=x86/cache</a> ]<o:p></o:p> Kernel requires to provide schemata for l3 cache before add a task to a new partition, these interface is too much detail for a virtual machine user, so propose to let Libvirt manage schemata on the host. <o:p></o:p> <o:p></o:p> ## What will libvirt do? <o:p></o:p> ### Questions:<o:p></o:p> To enable CAT support in libvirt, we need to think about follow questions <o:p></o:p> <ol style="margin-top:0cm" start="1" type="1"> <li class="MsoNormal" style="mso-list:l0 level1 lfo1">Only set CAT when an VM has CPU pin, which is to say, l3 cache is per cpu socket resources. On a host which has 2 cpu sockets, each cpu socket has it own cache, and can not be shared..<o:p></o:p></li><li class="MsoNormal" style="mso-list:l0 level1 lfo1">What the cache allocation policy should be used, this will be looks like:<o:p></o:p></li></ol> <![if !supportLists]>a. <![endif]>VM has it’s own dedicated l3 cache and also can share other l3 cache.<o:p></o:p> <![if !supportLists]>b. <![endif]>VM can only use the caches which allocated to it.<o:p></o:p> <![if !supportLists]>c. <![endif]>Has some pre-defined policies and priority for a VM<o:p></o:p> Like COB [1]<o:p></o:p> <ol style="margin-top:0cm" start="1" type="1"> <li class="MsoNormal" style="mso-list:l0 level1 lfo3">Should reserve some l3 cache for host’s system usage (related to 2)<o:p></o:p></li><li class="MsoNormal" style="mso-list:l0 level1 lfo3">What’s the unit for l3 cache allocation? (related to 2)<o:p></o:p></li></ol> <o:p></o:p> ### Propose Changes<o:p></o:p> <o:p></o:p> XML domain user interface changes:<o:p></o:p> <o:p></o:p> Option 1: explicit specify cache allocation for a VM<o:p></o:p> <o:p></o:p> 1 work with numa node<o:p></o:p> Some cloud orchestration software use numa + vcpu pin together, so we can enable cat supporting with numa infra.<o:p></o:p> <o:p></o:p> Expose how many l3 cache a VM want to reserved and we require that the l3 cache should be bind on some specify cpu socket, just like what we did for numa node. This is an domain xml example which is generated by OpenStack Nova for allocate llc(l3 cache) when booting a new VM <domain> … <cputune> <vcpupin vcpu='0' cpuset='19'/> <vcpupin vcpu='1' cpuset='63'/> <vcpupin vcpu='2' cpuset='83'/> <vcpupin vcpu='3' cpuset='39'/> <vcpupin vcpu='4' cpuset='40'/> <vcpupin vcpu='5' cpuset='84'/> <emulatorpin cpuset='19,39-40,63,83-84'/> </cputune> ... <cpu mode='host-model'> <model fallback='allow'/> <topology sockets='3' cores='1' threads='2'/> <numa> <cell id='0' cpus='0-1' memory='2097152' l3cache='1408' unit='KiB'/> <cell id='1' cpus='2-5' memory='4194304' l3cache='5632' unit='KiB'/> </numa> </cpu> ... </domain> Refer to [<a href="http://libvirt.org/formatdomain.html#elementsCPUTuning">http://libvirt.org/formatdomain.html#elementsCPUTuning</a>] <o:p></o:p> So finally we can calculate on which CPU socket(cell) we need to allocate how may l3cache for a VM.<o:p></o:p> <o:p></o:p> 2. work with vcpu pin<o:p></o:p> <o:p></o:p> Forget numa part, CAT setting should have relationship with cpu core setting, we can apply CAT policy if VM has set cpu pin setting (only VM won’t be schedule to another CPU sockets)<o:p></o:p> <o:p></o:p> Cache allocation on which CPU socket can be calculate as just as 1.<o:p></o:p> <o:p></o:p> We may need to enable both 1 and 2. <o:p></o:p> <o:p></o:p> There are several policy for cache allocation:<o:p></o:p> <o:p></o:p> Let’ take some examples:<o:p></o:p> <o:p></o:p> For intel e5 v4 2699(Signal socket), there are 55M l3 cache on the chip , the default of L3 schemata is L3:0=ffffff , it represents to use 20 bit to control l3 cache, each bit will represent 2.75M, which will be the minimal unit on this host.<o:p></o:p> The allocation policy could be 3 policies :<o:p></o:p> <o:p></o:p> <![if !supportLists]>1. <![endif]>One priority VM:<o:p></o:p> A priority import VM can be allocated a dedicated amount l3 cache (let’s say 2.75 * 4 = 11M) and it can also reach the left 44 M cache which will be shared with other process and VM on the same host. <o:p></o:p> So that we need to create a new ‘Partition’ n-20371<o:p></o:p> <o:p></o:p> root@s2600wt:/sys/fs/resctrl# ls<o:p></o:p> cpus info n-20371 schemata tasks<o:p></o:p> <o:p></o:p> Inside of n-20371 directory:<o:p></o:p> <o:p></o:p> root@s2600wt:/sys/fs/resctrl# ls n-20371/<o:p></o:p> cpus schemata tasks<o:p></o:p> <o:p></o:p> The schemata content will be L3:0=fffff <o:p></o:p> The tasks content will be the pids of that VM<o:p></o:p> <o:p></o:p> Along we need to change the default schemata of system:<o:p></o:p> <o:p></o:p> root@s2600wt:/sys/fs/resctrl# cat schemata<o:p></o:p> L3:0=ffff # which can not use the highest 4 bits, only tasks in n-20371 can reach that.<o:p></o:p> <o:p></o:p> In this design , we can only get 1 priority VM.<o:p></o:p> <o:p></o:p> Let’s change it a bit to have 2 VMs<o:p></o:p> <o:p></o:p> The schemata of the 2 VMs could be:<o:p></o:p> <o:p></o:p> <![if !supportLists]>1. <![endif]>L3:0=ffff0 # could not use the 4 low bits 11M l3 cache<o:p></o:p> <![if !supportLists]>2. <![endif]>L3:0=0ffff # could not use the 4 high bits 11M l3 cache <o:p></o:p> Default schemata changes to<o:p></o:p> <o:p></o:p> L3:0=0fff0 # default system process could only use the middle 33M l3 cache<o:p></o:p> <o:p></o:p> <![if !supportLists]>2. <![endif]>Isolated l3 cache dedicated allocation for each VM(if required)<o:p></o:p> <o:p></o:p> A VM can only use the cache allocated to it.<o:p></o:p> <o:p></o:p> For example<o:p></o:p> VM 1 requires to allocate 11 M <o:p></o:p> It’s schemata will be L3:0=f0000 # <o:p></o:p> VM 2 requires to allocate 11M<o:p></o:p> It’s schemata will be L3:0=f000<o:p></o:p> <o:p></o:p> And default schemata will be L3:0=fff<o:p></o:p> <o:p></o:p> In this case, we can create multiple VMs which each of them can have dedicated l3 cache.<o:p></o:p> The disadvantage is that we the allocated cache could be not be shared efficiently.<o:p></o:p> <o:p></o:p> <![if !supportLists]>3. <![endif]>Isolated l3 cache shared allocation for each VM(if required by user)<o:p></o:p> <o:p></o:p> In this case, we will put some VMs (which consider as noisy neighbors) to a ‘Partition’, restrict them to use the only caches allocated to them, by do this, other much more priority VM can be ensure to have enough l3 cache<o:p></o:p> <o:p></o:p> Then we should decide how much cache the noisy group should have, and put all of their pids in that tasks file. <o:p></o:p> <o:p></o:p> Option 2: set cache priority and apply policies<o:p></o:p> <o:p></o:p> Don’t specify cache amount at all, only define cache usage priority when define a VM domain XML.<o:p></o:p> <o:p></o:p> Cache priority will decide how much the VM can use l3 cache on a host, it’s not a quantized. So user don’t need to think about how much cache it should have when define a domain XML.<o:p></o:p> <o:p></o:p> Libvirt will decide cache allocation by the priority of VM defined and policies using. <o:p></o:p> <o:p></o:p> Disadvantage is that caches ability on different host may be different. Same VM domain XML on different host may have vary caches allocation amount. <o:p></o:p> <o:p></o:p> # Support CAT in libvirt itself or leverage other software<o:p></o:p> <o:p></o:p> COB<o:p></o:p> <o:p></o:p> COB is Intel Cache Orchestrator Balancer (COB). please refer <a href="http://clrgitlab.intel.com/rdt/cob/tree/master">http://clrgitlab.intel.com/rdt/cob/tree/master</a><o:p></o:p> <o:p></o:p> COB supports some pre-defined policies, it will monitor cpu/cache/cache missing and do cache allocation based on policy using.<o:p></o:p> <o:p></o:p> If COB support monitor some specified process (VM process) and accept priority defined, it will be good to reuse. <o:p></o:p> <o:p></o:p> <o:p></o:p> At last the question came out:<o:p></o:p> <ul style="margin-top:0cm" type="disc"> <li class="MsoNormal" style="mso-list:l2 level1 lfo8">Support a fine-grained llc cache control , let user specify cache allocation<o:p></o:p></li><li class="MsoNormal" style="mso-list:l2 level1 lfo8">Support pre-defined policies and user specify llc allocation priority.<o:p></o:p></li></ul> <o:p></o:p> Reference<o:p></o:p> <o:p></o:p> [1] COB <a href="http://clrgitlab.intel.com/rdt/cob/tree/master"> http://clrgitlab.intel.com/rdt/cob/tree/master</a><o:p></o:p> [2] CAT intro: <a href="https://software.intel.com/en-us/articles/software-enabling-for-cache-allocation-technology"> https://software.intel.com/en-us/articles/software-enabling-for-cache-allocation-technology</a> <o:p></o:p> [3] kernel Intel_rdt_ui [ <a href="https://git.kernel.org/cgit/linux/kernel/git/tip/tip.git/tree/Documentation/x86/intel_rdt_ui.txt?h=x86/cache"> https://git.kernel.org/cgit/linux/kernel/git/tip/tip.git/tree/Documentation/x86/intel_rdt_ui.txt?h=x86/cache</a> ]<o:p></o:p> <o:p></o:p> <o:p></o:p> <o:p></o:p> <o:p></o:p> <div> Best Regards<o:p></o:p> </div> <div> <o:p></o:p> </div> <div> Eli Qiao(乔立勇）OpenStack Core team OTC Intel.<o:p></o:p> </div> <div> -- <o:p></o:p> </div> <o:p></o:p> </div> </body> </html>