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<p>Hi all,</p>
<p>Now both qemu and kvm support 5-level paging.</p>
<p>We can start qemu with a "cpu,+la57" to set 57-bit vitrual
address space. <br>
</p>
<p>So VM can be aware that it need to enable 5-level paging.</p>
<p><br>
</p>
<p>We can also set another "cpu,phys-bits=52" to set the VM physical
address space.</p>
<p>Actually, VM can still turn on 5 level paging even without
"phys-bits=52", yet this means</p>
<p>the guest physical address width are limited, meaning less
practical benefits.</p>
<p><br>
</p>
<p>In to support 5-level paging, I suggest to add two attribute for
the domain cpu element in libvirt.</p>
<p><cpu la57='yes', phys-bits='52'\></p>
<p>Here we need to be able to set phys-bits directly, because it
is potentially migration sensitive.</p>
<p>If la57='no', libvirt will ignore phys-bits, no matter whether
hardware support la57.</p>
<p>If la57='yes', libvirt will probe the host capability, and will
throw error if hardware does support la57.</p>
<p>If la57='yes', even phys-bits less than 52, libvirt will also
pass it to qemu though less practical benefits.</p>
<br>
<p><br>
</p>
[info]<br>
<p>[1] <a moz-do-not-send="true"
href="https://lists.gnu.org/archive/html/qemu-devel/2016-12/msg02096.html">[Qemu-devel]
[PATCH]<span> </span>x86: implement la57 paging mode</a></p>
[2] <a moz-do-not-send="true"
href="https://lists.gnu.org/archive/html/qemu-devel/2016-07/msg01950.html">[Qemu-devel]
[PATCH v4 2/5] x86: Allow physical address bits to be set</a>
<p><br>
</p>
<p><br>
</p>
<p>BR</p>
<p>Shaohe Feng<br>
</p>
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