Fwd: AMD x2 chips

[Bryan J. Smith]

On Thu, 2006-02-16 at 06:34 -0500, Bryan J. Smith wrote:
> First off, that's _not_ a technical manual ...
> So what's to say they're not doing the same _inside_ each die?

Here's the deal in a nutshell, I have seen _no_ technical specifics on
_how_ they are doing it.  All I've seen is that their "Direct Connect
Architecture" is used inside of the chip, just like outside.  What that
means is anyone's guess.

Old, "pure" EV6 was up to a 16-node crossbar -- including between CPUs,
memory and I/O.

HyperTransport is just a generic, glueless partial-mesh of nodes -- and
you can have memory _separate_ from CPU (as well as I/O) connected by
HyperTransport (although the memory controller would have to be on the
"same node" as the memory -- or just a full CPU).

In any case, there is _not_ the "complex bridging" of Intel's dual-core.
So as long as the APIC is setup correctly (which is done with little
more than BIOS update), dual-core is pretty much no different -- sans
performance.

Just like multiple 4 CPU boards connected together via HyperTransport.


-- 
Bryan J. Smith             Professional, technical annoyance
mailto:b.j.smith at ieee.org       http://thebs413.blogspot.com
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