4gb (4 memory sticks) at 400Mhz on socket 939 MB -- JEDEC specifications ...

[Bryan J. Smith]

On Sun, 2006-07-09 at 01:40 -0400, hahn at physics.mcmaster.ca wrote:
> I believe this ignores another relevant factor:
> how many chip-selects the dimm uses.

I was purposely not trying to get into memory controller design.  Not
only have I ripped out the AMD and Intel engineering specification
sheets on various chipsets to verify the _exact_ IC technology, width
and number/banking before -- but I've designed memory controllers
myself.

But yes, if you have a total of 128-bit IC width in a 64-bit DIMM,
that's also an issue.  But that's just the tip-of-the-iceberg.

> my understanding is that if a dimm is "double-sided", it means that
> it uses 2 CS's.

There are a lot of "double sided" or "double stacked" or "low density"
or "double rank" or "low rank" or countless other, non-standard,
non-uniform descriptions out there.  I _refuse_ to use them, as they are
not standardized and often confusing.  E.g., does "low density" mean
less total width/fewer chips?  Or does it mean the lower density in the
IC, meaning more total width/more chips?

The *ONLY* way to *ACCURATELY* describe this is to sit down and break
out each DIMM into the *RAW* number of 32-bit "banks" -- and that means
you take the bit-width of the *INDIVIDUAL* ICs on every DIMM and
multiply by number (except for parity/ECC chips).

So, if you want to get really details, we *CAN* do that!  ;->

Furthermore, some chipsets just do _not_ support certain IC
technologies, bit-widths and other sizing.

The chronic issue was the PC100 256MB DIMM for i440BX versus i810/815 --
they used completely _difference_ DIMMs.  The i440BX only supported a
4-bit with in 32-chip (36-chip for ECC) configuration -- clearly a
"double sided" registered DIMM.  The i810/815 used a 8-bit or 16-bit in
a 8 or 4 chip configuration, respectively.  And even that is a
mega-oversimplification!  ;->

> table 46 on p 182 of AMD's bios guide (doc 26094) appears to allow up
> to 6 ranks for ddr400/2T operation.  afaikt, a double-rank dimm is AKA
> double-sided.  unfortunatley AMD also adds some weaselish text about
> how MB vendors should validate, etc...

I only listed the JEDEC specifications and recommendations.  If you want
to go outside of those, which some vendors may do, by all means, do!

Also remember that AMD _might_ be talking about "banks" and not merely
"DIMMs."  "Banks" are 32-bit (like old SIMMs).  "DIMMs" are 64-bit.

BTW, I've seen the term "rank" used 3 different ways.
Everyone seems to want to simply things with a term or two.
Impossible.

Especially when it comes to DDR333 v. DDR400 performance.
Even reporting 3 or 4 timings is woefully incomplete.


-- 
Bryan J. Smith           Professional, technical annoyance
mailto:b.j.smith at ieee.org     http://thebs413.blogspot.com
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