[Crash-utility] [PATCH 4/6] ppc64/book3s: address change in page flags for PowerISA v3.0

[Hari Bathini]

PowerISA v3.0 CPUs expect _PAGE_PRESENT to be at 0x8000_0000_0000_0000
instead of 0x2 and _PAGE_PTE to be at 0x4000_0000_0000_0000 instead of
0x1 in radix mode. These requirements are accomodated by changing the
flags _PAGE_PRESENT & _PAGE_PTE for 64-bit POWER server processors with
kernel commits 849f86a6 & 84c95756. This patch makes the corresponding
changes here.

Signed-off-by: Hari Bathini <hbathini at linux.vnet.ibm.com>
---
 ppc64.c |   12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/ppc64.c b/ppc64.c
index 6b89eaa..8733d64 100644
--- a/ppc64.c
+++ b/ppc64.c
@@ -317,6 +317,16 @@ ppc64_init(int when)
 				m->_page_rw = 0x8UL;
 				m->_page_guarded = 0x10UL;
 			}
+
+			/*
+			 * Starting with kernel v4.6, to accommodate both
+			 * radix and hash MMU modes in a single kernel,
+			 * _PAGE_PTE & _PAGE_PRESENT page flags are changed.
+			 */
+			if (THIS_KERNEL_VERSION >= LINUX(4,6,0)) {
+				m->_page_pte = 0x1UL << 62;
+				m->_page_present = 0x1UL << 63;
+			}
 		}
 
 		if (!(machdep->flags & (VM_ORIG|VM_4_LEVEL))) {
@@ -1336,7 +1346,7 @@ ppc64_translate_pte(ulong pte, void *physaddr, ulonglong pte_rpn_shift)
         ulong paddr;
 
         paddr =  PTOB(pte >> pte_rpn_shift);
-        page_present = (pte & _PAGE_PRESENT);
+        page_present = !!(pte & _PAGE_PRESENT);
 
         if (physaddr) {
                 *((ulong *)physaddr) = paddr;