[Crash-utility] [PATCH 0/5] Second phase of future support for x86_64 5-level page tables

[Dou Liyang]

I found Dave had alread done the first phase of future support for x86_64
5-level page tables(commit 307e7f35f510). when I asked him about the
state of this work, he gave me a more detailed answer and suggestion.
I follow his advice, and do the following job.


1. Refine the original logical:
  1) Create some new common function for getting the offset of page table
  2) Repace the PML4 and UPML with the common PGD:
     machdep->machspec->pml4/upml ==> machdep->pdg
  3) Using the PUD in x86_64

2. Add 5-level page tables support for x86_64_k/uvtop()

This patchset is the second phase of the work, As Dave said, we need to be 
a manner of determining very early on whether the kernel page tables are
using 5-level and  whether each user-space task is using 4- or 5-level page
tables. These will be done after this phase. 

About test work:

I have tested this patchset with 4-level and 5-level paging table.

sadump/ Xen/ Old Linux / RHEL4 are not be tested.

Dou Liyang (5):
  defs.h: Fix the PHYSICAL_PAGE_MASK macro
  x86_64: Extract public page table mapping code
  x86_64: Unify the page table parsing for 4-level mode
  x86_64.c: Add the VMEMMAP support for 5 level page table
  x86_64: Add 5-level paging support for x86_64_k/uvtop()

 defs.h   |  57 ++----
 sadump.c |   9 +-
 x86_64.c | 702 +++++++++++++++++++++++++++++++--------------------------------
 3 files changed, 367 insertions(+), 401 deletions(-)

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2.14.3