[Crash-utility] [PATCH v2] x86_64: Make the conversion between 4level and 5level paging automatically

[Dave Anderson]

----- Original Message -----
> At 07/12/2018 09:08 PM, Dave Anderson wrote:
> > 
> > 
> > ----- Original Message -----
> >>
> >>
> >> At 07/12/2018 02:23 AM, Dave Anderson wrote:
> >>>
> >>>
> >>> ----- Original Message -----
> >>>>
> >>>>
> >>>> ----- Original Message -----
> >>>>> Hi Dave,
> >>>>>
> >>>>> At 07/11/2018 03:33 AM, Dave Anderson wrote:
> >>>>>>
> >>>>>> The final phase of support would be making this work:
> >>>>>>
> >>>>>>      static int
> >>>>>>      x86_64_task_uses_5level(struct task_context *tc)
> >>>>>>      {
> >>>>>>              return FALSE;
> >>>>>>      }
> >>>>>>
> >>>>>> Have you had a chance to look at how that can be done?
> >>>>>>
> >>>>>
> >>>>> I have no idea to check if 5level paging is used in User-space.
> >>>>>
> >>>>> You gave me some methods, and I have try:
> >>>>>
> >>>>>      -The MAP_FIXED flag
> >>>>>      -check if the contents of the page directory or p4d is 'flods'
> >>>>
> >>>> It would be most helpful if you can compare two tasks, one with 5-level
> >>>> and one without, and see if there's anything obviously different.
> >>>> (I don't know what "flods" means)
> >>>
> >>> Ah, sorry, you mean if the top-level page directory folds back into
> >>> itself.
> >>>
> >>> So yes, I wonder if it would be obvious enough by checking whether the
> >>> top-level pgd folds back into itself, and if so, 4-levels of page tables
> >>> are in use?  But if that were the case, it seems that the 5-level
> >>> translation
> >>> code would work on both types of user-space tasks.  I just don't
> >>> understand
> >>> how it's supposed to work.
> >>>
> >>
> >> OK, let me try to clarify if the the 5-level translation code would work
> >> on both types of user-space tasks at first. ;-)
> >>
> 
> Hi Dave,
> 
> As we all know, the kernel with CONFIG_X86_5LEVEL=y can run both in the
> 4-level page table and 5-level page table. It's configured by:
> 
>    - no5lvl in cmdline
>    - the machine supports 5-level paging
>      - CPUID leaf 7 is supported
>      - the leaf has the feature bit set
> 
> then, Kernel using the __pgtable_l5_enabled to record the last result.
> 
> In the Documentation/x86/x86_64/5level-paging.txt:
> 
>    ...
>    To mitigate this, we are not going to allocate virtual address space
>    above 47-bit by default.
> 
>    But userspace can ask for allocation from full address space by
>    specifying hint address (with or without MAP_FIXED) above 47-bits.
>    ...
> 
> IMO, the document only tell us that some user tasks can't using the
> address above 47-bits, this doesn't effect the paging level.
> 
> So, I think we don't need to add check for user tasks, in other word,
> All user tasks must using 5-level paging if __pgtable_l5_enabled = 1.
> Correct?

That make sense, and sounds good to me! 

> 
> BTW, I will try to ask Kirill about it and will cc you. OK? ;-)

OK thanks,
  Dave

 
> >> Thank you so much for you kind explanation!
> >>
> >> 	dou.
> > 
> > Hi Dou,
> > 
> > That leads me to this question:  can you confirm that this crash patch
> > works with a kernel that is configured with CONFIG_X86_5LEVEL, but either:
> > 
> >    (1) the kernel was booted with "no5lvl", or
> >    (2) the host hardware does not have the X86_CR4_LA57 bit set
> > 
> 
> I tested the two cases with the following patch, 'vm -p' and 'kmem -v'
> shows OK.
> 
> ---------------------------8<------------------------------------------
> 
> Author: Dou Liyang <douly.fnst at cn.fujitsu.com>
> Date:   Fri Jul 13 10:43:26 2018 +0800
> 
>      x86_64: Remove the unused x86_64_task_uses_5level()
> 
> diff --git a/x86_64.c b/x86_64.c
> index b07d6f2..96f685b 100644
> --- a/x86_64.c
> +++ b/x86_64.c
> @@ -24,7 +24,6 @@ static int x86_64_uvtop(struct task_context *, ulong,
> physaddr_t *, int);
>   static int x86_64_uvtop_level4(struct task_context *, ulong,
> physaddr_t *, int);
>   static int x86_64_uvtop_level4_xen_wpt(struct task_context *, ulong,
> physaddr_t *, int);
>   static int x86_64_uvtop_level4_rhel4_xen_wpt(struct task_context *,
> ulong, physaddr_t *, int);
> -static int x86_64_task_uses_5level(struct task_context *);
>   static ulong x86_64_vmalloc_start(void);
>   static int x86_64_is_task_addr(ulong);
>   static int x86_64_verify_symbol(const char *, ulong, char);
> @@ -341,6 +340,7 @@ x86_64_init(int when)
>                          if (l5_enabled)
>                                  machdep->flags |= VM_5LEVEL;
>                  }
> +
>                  if (machdep->flags & VM_5LEVEL) {
>                          machdep->machspec->userspace_top =
> USERSPACE_TOP_5LEVEL;
>                          machdep->machspec->page_offset =
> PAGE_OFFSET_5LEVEL;
> @@ -361,7 +361,6 @@ x86_64_init(int when)
>                          machdep->uvtop = x86_64_uvtop_level4;  /*
> 5-level is optional per-task */
>                          machdep->kvbase = (ulong)PAGE_OFFSET;
>                          machdep->identity_map_base = (ulong)PAGE_OFFSET;
> -
>                  }
> 
>                  /*
> @@ -1915,7 +1914,7 @@ x86_64_uvtop_level4(struct task_context *tc, ulong
> uvaddr, physaddr_t *paddr, in
>                  goto no_upage;
> 
>          /* If the VM is in 5-level page table */
> -       if (machdep->flags & VM_5LEVEL && x86_64_task_uses_5level(tc)) {
> +       if (machdep->flags & VM_5LEVEL) {
>                  ulong p4d_pte;
>                  /*
>                   *  p4d = p4d_offset(pgd, address);
> @@ -1986,12 +1985,6 @@ no_upage:
>          return FALSE;
>   }
> 
> -static int
> -x86_64_task_uses_5level(struct task_context *tc)
> -{
> -       return FALSE;
> -}
> -
>   static int
>   x86_64_uvtop_level4_xen_wpt(struct task_context *tc, ulong uvaddr,
> physaddr_t *paddr, int verbose)
>   {
> 
> 
> > Thanks,
> >    Dave
> > 
> > 
> > 
> > 
> > 
> 
> 
>