[Crash-utility] [PATCH v2 2/3] calc_kaslr_offset: check for 5-level paging

[Alexey Makhalov]

If enabled return FALSE. Use LA57 bit in CR4 to
check whether 5-level paging enabled or not.
Replaced *_get_cr3_idtr() set of functions by
*_get_cr3_cr4_idtr().

Signed-off-by: Alexey Makhalov <amakhalov at vmware.com>
---
 defs.h         |  4 ++--
 kaslr_helper.c | 14 +++++++++-----
 sadump.c       |  3 ++-
 vmware_vmss.c  |  3 ++-
 4 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/defs.h b/defs.h
index 00786c2..8c49c2f 100644
--- a/defs.h
+++ b/defs.h
@@ -6623,7 +6623,7 @@ void sadump_unset_zero_excluded(void);
 struct sadump_data;
 struct sadump_data *get_sadump_data(void);
 int sadump_calc_kaslr_offset(ulong *);
-int sadump_get_cr3_idtr(ulong *, ulong *);
+int sadump_get_cr3_cr4_idtr(ulong *, ulong *, ulong *);
 
 /*
  * qemu.c
@@ -6676,7 +6676,7 @@ void get_vmware_vmss_regs(struct bt_info *, ulong *, ulong *);
 int vmware_vmss_memory_dump(FILE *);
 void dump_registers_for_vmss_dump(void);
 int vmware_vmss_valid_regs(struct bt_info *);
-int vmware_vmss_get_cr3_idtr(ulong *, ulong *);
+int vmware_vmss_get_cr3_cr4_idtr(ulong *, ulong *, ulong *);
 int vmware_vmss_phys_base(ulong *phys_base);
 int vmware_vmss_set_phys_base(ulong);
 
diff --git a/kaslr_helper.c b/kaslr_helper.c
index bb19e54..02a7e48 100644
--- a/kaslr_helper.c
+++ b/kaslr_helper.c
@@ -240,7 +240,7 @@ get_vmcoreinfo(ulong elfcorehdr, ulong *addr, int *len)
 }
 
 static int
-qemu_get_cr3_idtr(ulong *cr3, ulong *idtr)
+qemu_get_cr3_cr4_idtr(ulong *cr3, ulong *cr4, ulong *idtr)
 {
 	QEMUCPUState *cpustat;
 
@@ -257,6 +257,7 @@ qemu_get_cr3_idtr(ulong *cr3, ulong *idtr)
 	}
 
 	*cr3 = cpustat->cr[3];
+	*cr4 = cpustat->cr[4];
 	*idtr = cpustat->idt.base;
 
 	return TRUE;
@@ -393,10 +394,11 @@ quit:
 #define PTI_USER_PGTABLE_BIT	PAGE_SHIFT
 #define PTI_USER_PGTABLE_MASK	(1 << PTI_USER_PGTABLE_BIT)
 #define CR3_PCID_MASK		0xFFFull
+#define CR4_LA57		(1 << 12)
 int
 calc_kaslr_offset(ulong *ko, ulong *pb)
 {
-	uint64_t cr3 = 0, idtr = 0, pgd = 0, idtr_paddr;
+	uint64_t cr3 = 0, cr4 = 0, idtr = 0, pgd = 0, idtr_paddr;
 	ulong divide_error_vmcore;
 	ulong kaslr_offset, phys_base;
 	ulong kaslr_offset_kdump, phys_base_kdump;
@@ -408,13 +410,13 @@ calc_kaslr_offset(ulong *ko, ulong *pb)
 
 retry:
 	if (SADUMP_DUMPFILE()) {
-		if (!sadump_get_cr3_idtr(&cr3, &idtr))
+		if (!sadump_get_cr3_cr4_idtr(&cr3, &cr4, &idtr))
 			return FALSE;
 	} else if (QEMU_MEM_DUMP_NO_VMCOREINFO()) {
-		if (!qemu_get_cr3_idtr(&cr3, &idtr))
+		if (!qemu_get_cr3_cr4_idtr(&cr3, &cr4, &idtr))
 			return FALSE;
 	} else if (VMSS_DUMPFILE()) {
-		if (!vmware_vmss_get_cr3_idtr(&cr3, &idtr))
+		if (!vmware_vmss_get_cr3_cr4_idtr(&cr3, &cr4, &idtr))
 			return FALSE;
 	} else
 		return FALSE;
@@ -432,6 +434,8 @@ retry:
 	 *
 	 * TODO: XEN and 5-level is not supported
 	 */
+	if (cr4 & CR4_LA57)
+		return FALSE;
 	vt->kernel_pgd[0] = pgd;
 	machdep->last_pgd_read = vt->kernel_pgd[0];
 	machdep->machspec->physical_mask_shift = __PHYSICAL_MASK_SHIFT_2_6;
diff --git a/sadump.c b/sadump.c
index f313528..0a41ea6 100644
--- a/sadump.c
+++ b/sadump.c
@@ -1703,7 +1703,7 @@ get_sadump_smram_cpu_state_any(struct sadump_smram_cpu_state *smram)
 }
 
 int
-sadump_get_cr3_idtr(ulong *cr3, ulong *idtr)
+sadump_get_cr3_cr4_idtr(ulong *cr3, ulong *cr4, ulong *idtr)
 {
 	struct sadump_smram_cpu_state scs;
 
@@ -1712,6 +1712,7 @@ sadump_get_cr3_idtr(ulong *cr3, ulong *idtr)
 		return FALSE;
 
 	*cr3 = scs.Cr3;
+	*cr4 = scs.Cr4;
 	*idtr = ((uint64_t)scs.IdtUpper)<<32 | (uint64_t)scs.IdtLower;
 
 	return TRUE;
diff --git a/vmware_vmss.c b/vmware_vmss.c
index 8aa0de0..1a9425f 100644
--- a/vmware_vmss.c
+++ b/vmware_vmss.c
@@ -873,12 +873,13 @@ vmware_vmss_valid_regs(struct bt_info *bt)
 }
 
 int
-vmware_vmss_get_cr3_idtr(ulong *cr3, ulong *idtr)
+vmware_vmss_get_cr3_cr4_idtr(ulong *cr3, ulong *idtr)
 {
 	if (vmss.num_vcpus == 0 || vmss.vcpu_regs[0] != REGS_PRESENT_ALL)
 		return FALSE;
 
 	*cr3 = vmss.regs64[0]->cr[3];
+	*cr4 = vmss.regs64[0]->cr[4];
 	*idtr = vmss.regs64[0]->idtr;
 
 	/*
-- 
2.11.0