[dm-devel] [PATCH v3 08/14] x86, dax, libnvdimm: move wb_cache_pmem() to libnvdimm

[Jan Kara]

On Fri 09-06-17 13:24:29, Dan Williams wrote:
> With all calls to this routine re-directed through the pmem driver, we can kill
> the pmem api indirection. arch_wb_cache_pmem() is now optionally supplied by
> the arch specific asm/pmem.h.  Same as before, pmem flushing is only defined
> for x86_64, but it is straightforward to add other archs in the future.
> 
> Cc: <x86 at kernel.org>
> Cc: Jan Kara <jack at suse.cz>
> Cc: Jeff Moyer <jmoyer at redhat.com>
> Cc: Ingo Molnar <mingo at redhat.com>
> Cc: Christoph Hellwig <hch at lst.de>
> Cc: "H. Peter Anvin" <hpa at zytor.com>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Oliver O'Halloran <oohall at gmail.com>
> Cc: Matthew Wilcox <mawilcox at microsoft.com>
> Cc: Ross Zwisler <ross.zwisler at linux.intel.com>
> Signed-off-by: Dan Williams <dan.j.williams at intel.com>

Looks good to me. Just one question below...

> -/**
> - * arch_wb_cache_pmem - write back a cache range with CLWB
> - * @vaddr:	virtual start address
> - * @size:	number of bytes to write back
> - *
> - * Write back a cache range using the CLWB (cache line write back)
> - * instruction. Note that @size is internally rounded up to be cache
> - * line size aligned.
> - */
>  static inline void arch_wb_cache_pmem(void *addr, size_t size)
>  {
> -	u16 x86_clflush_size = boot_cpu_data.x86_clflush_size;
> -	unsigned long clflush_mask = x86_clflush_size - 1;
> -	void *vend = addr + size;
> -	void *p;
> -
> -	for (p = (void *)((unsigned long)addr & ~clflush_mask);
> -	     p < vend; p += x86_clflush_size)
> -		clwb(p);
> +	clean_cache_range(addr,size);
>  }

So this will make compilation break on 32-bit x86 as it does not define
clean_cache_range(). Do we somewhere force we are on x86_64 when pmem is
enabled?

								Honza
-- 
Jan Kara <jack at suse.com>
SUSE Labs, CR