[edk2-devel] [edk2-platforms Patch 03/14] Vlv2TbltDevicePkg: Remove unused modules/libraries
Michael D Kinney
michael.d.kinney at intel.com
Mon Jul 1 02:55:42 UTC 2019
* Delete platform specific SerialPortLib
* Delete platform specific Metronome module
* Delete platform specific BootScriptSaveDxe module
* Delete SmmSwDispatch2OnSmmSwDispatchThunk module
* Delete SmramSaveInfoHandlerSmm module
* Delete unused FSP content
* Delete unused I2C content
* Delete unused Stitch content
* Delete unused portions of PlatformSmm module
Cc: Zailiang Sun <zailiang.sun at intel.com>
Cc: Yi Qian <yi.qian at intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney at intel.com>
---
.../BootScriptSaveDxe/BootScriptSaveDxe.inf | 60 --
.../InternalBootScriptSave.h | 102 ---
.../BootScriptSaveDxe/ScriptSave.c | 626 ---------------
.../FspAzaliaConfigData/AzaliaConfig.bin | Bin 3708 -> 0 bytes
.../FspSupport/BootModePei/BootModePei.c | 42 -
.../FspSupport/BootModePei/BootModePei.inf | 40 -
.../FspHobProcessLibVlv2.c | 421 ----------
.../FspHobProcessLibVlv2.inf | 74 --
.../FspPlatformSecLibVlv2.c | 144 ----
.../FspPlatformSecLibVlv2.inf | 82 --
.../Ia32/AsmSaveSecContext.asm | 45 --
.../SecFspPlatformSecLibVlv2/Ia32/Fsp.inc | 45 --
.../Ia32/PeiCoreEntry.asm | 135 ----
.../Ia32/SecEntry.asm | 338 --------
.../SecFspPlatformSecLibVlv2/Ia32/Stack.S | 71 --
.../SecFspPlatformSecLibVlv2/Ia32/Stack.asm | 76 --
.../SecFspPlatformSecLibVlv2/PlatformInit.c | 36 -
.../SecFspPlatformSecLibVlv2/SaveSecContext.c | 108 ---
.../SecGetPerformance.c | 83 --
.../SecPlatformInformation.c | 77 --
.../SecFspPlatformSecLibVlv2/SecRamInitData.c | 16 -
.../SecTempRamSupport.c | 149 ----
.../SecFspPlatformSecLibVlv2/UartInit.c | 192 -----
.../Include/Protocol/TpmMp.h | 136 ----
.../Include/Protocol/UsbPolicy.h | 126 ---
.../Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c | 46 --
.../Library/I2CLib/I2CLibNull.inf | 39 -
.../Library/I2CLibDxe/I2CLib.c | 735 ------------------
.../Library/I2CLibDxe/I2CLibDxe.inf | 39 -
.../Library/I2CLibDxe/I2CRegs.h | 126 ---
.../Library/I2CLibPei/I2CAccess.h | 44 --
.../Library/I2CLibPei/I2CDelayPei.c | 46 --
.../Library/I2CLibPei/I2CDelayPei.h | 30 -
.../Library/I2CLibPei/I2CIoLibPei.c | 178 -----
.../Library/I2CLibPei/I2CIoLibPei.h | 153 ----
.../Library/I2CLibPei/I2CLibPei.c | 638 ---------------
.../Library/I2CLibPei/I2CLibPei.h | 280 -------
.../Library/I2CLibPei/I2CLibPei.inf | 40 -
.../Library/PlatformFspLib/PlatformFspLib.c | 44 --
.../Library/PlatformFspLib/PlatformFspLib.inf | 49 --
.../SerialPortLib/PlatformSerialPortLib.h | 53 --
.../Library/SerialPortLib/SerialPortLib.c | 246 ------
.../Library/SerialPortLib/SerialPortLib.inf | 52 --
.../Library/SerialPortLib/SioInit.c | 127 ---
.../Library/SerialPortLib/SioInit.h | 62 --
.../Metronome/LegacyMetronome.c | 185 -----
.../Metronome/LegacyMetronome.h | 64 --
.../Vlv2TbltDevicePkg/Metronome/Metronome.inf | 49 --
.../PlatformSmm/SmmScriptSave.c | 252 ------
.../PlatformSmm/SmmScriptSave.h | 50 --
.../SmmSwDispatch2OnSmmSwDispatchThunk.c | 459 -----------
.../SmmSwDispatch2OnSmmSwDispatchThunk.inf | 54 --
.../SmramSaveInfoHandlerSmm.c | 164 ----
.../SmramSaveInfoHandlerSmm.inf | 60 --
.../Stitch/IFWIHeader/Vacant.bin | Bin 3928064 -> 0 bytes
.../Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat | 270 -------
.../Stitch/MNW2_Stitch_Config.txt | 10 -
57 files changed, 7868 deletions(-)
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptSave.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/AsmSaveSecContext.asm
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Fsp.inc
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/PeiCoreEntry.asm
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/SecEntry.asm
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.S
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.asm
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/PlatformInit.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SaveSecContext.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecGetPerformance.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecPlatformInformation.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecRamInitData.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecTempRamSupport.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/UartInit.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLib.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLibDxe.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CRegs.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CAccess.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Metronome/Metronome.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.h
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/Vacant.bin
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat
delete mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.inf b/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.inf
deleted file mode 100644
index d2fa621096..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.inf
+++ /dev/null
@@ -1,60 +0,0 @@
-#
-#
-## @file
-# Component description file for ScriptSave Lite module.
-#
-# This is an implementation of the Boot Script Save protocol.
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-
-#
-#
-#
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = BootScriptSaveDxe
- FILE_GUID = 42BB673D-09F3-4e2e-9FEE-D081131DED5B
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = InitializeScriptSave
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64 EBC
-#
-
-[Sources]
- ScriptSave.c
- InternalBootScriptSave.h
-
-
-[Packages]
- MdePkg/MdePkg.dec
- IntelFrameworkPkg/IntelFrameworkPkg.dec
- MdeModulePkg/MdeModulePkg.dec
-
-
-[LibraryClasses]
- PcdLib
- UefiRuntimeServicesTableLib
- UefiBootServicesTableLib
- MemoryAllocationLib
- UefiDriverEntryPoint
- BaseMemoryLib
- DebugLib
- BaseLib
- S3BootScriptLib
-
-[Protocols]
- gEfiBootScriptSaveProtocolGuid # PROTOCOL ALWAYS_PRODUCED
-
-
-[Depex]
- TRUE
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptSave.h b/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptSave.h
deleted file mode 100644
index f232281e2b..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptSave.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/** @file
-//
-//
- Internal header file for S3 Boot Script Saver driver.
-
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-**/
-
-#ifndef _INTERNAL_BOOT_SCRIPT_SAVE_H_
-#define _INTERNAL_BOOT_SCRIPT_SAVE_H_
-#include <FrameworkDxe.h>
-
-#include <Protocol/BootScriptSave.h>
-#include <Protocol/FirmwareVolume.h>
-
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/UefiDriverEntryPoint.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/S3BootScriptLib.h>
-#include <Library/PcdLib.h>
-#include <Library/SmbusLib.h>
-#include <IndustryStandard/SmBus.h>
-
-/**
- Adds a record into a specified Framework boot script table.
-
- This function is used to store a boot script record into a given boot
- script table. If the table specified by TableName is nonexistent in the
- system, a new table will automatically be created and then the script record
- will be added into the new table. A boot script table can add new script records
- until EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable() is called. Currently, the only
- meaningful table name is EFI_ACPI_S3_RESUME_SCRIPT_TABLE. This function is
- responsible for allocating necessary memory for the script.
-
- This function has a variable parameter list. The exact parameter list depends on
- the OpCode that is passed into the function. If an unsupported OpCode or illegal
- parameter list is passed in, this function returns EFI_INVALID_PARAMETER.
- If there are not enough resources available for storing more scripts, this function returns
- EFI_OUT_OF_RESOURCES.
-
- @param[in] This A pointer to the EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.
- @param[in] TableName Name of the script table. Currently, the only meaningful value is
- EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
- @param[in] OpCode The operation code (opcode) number.
- @param[in] ... Argument list that is specific to each opcode.
-
- @retval EFI_SUCCESS The operation succeeded. A record was added into the
- specified script table.
- @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script is not supported.
- If the opcode is unknow or not supported because of the PCD
- Feature Flags.
- @retval EFI_OUT_OF_RESOURCES There is insufficient memory to store the boot script.
-
-**/
-EFI_STATUS
-EFIAPI
-BootScriptWrite (
- IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL *This,
- IN UINT16 TableName,
- IN UINT16 OpCode,
- ...
- );
-
-/**
- Closes the specified script table.
-
- This function closes the specified boot script table and returns the base address
- of the table. It allocates a new pool to duplicate all the boot scripts in the specified
- table. Once this function is called, the specified table will be destroyed after it is
- copied into the allocated pool. As a result, any attempts to add a script record into a
- closed table will cause a new table to be created. The base address of the allocated pool
- will be returned in Address. After using the boot script table, the caller is responsible
- for freeing the pool that is allocated by this function. If the boot script table,
- such as EFI_ACPI_S3_RESUME_SCRIPT_TABLE, is required to be stored in a nonperturbed
- memory region, the caller should copy the table into the nonperturbed memory region by itself.
-
- @param[in] This A pointer to the EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.
- @param[in] TableName Name of the script table. Currently, the only meaningful value is
- EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
- @param[in] Address A pointer to the physical address where the table begins.
-
- @retval EFI_SUCCESS The table was successfully returned.
- @retval EFI_NOT_FOUND The specified table was not created previously.
- @retval EFI_OUT_OF_RESOURCE Memory is insufficient to hold the reorganized boot script table.
- @retval EFI_UNSUPPORTED The table type is not EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
-
-**/
-EFI_STATUS
-EFIAPI
-BootScriptCloseTable (
- IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL *This,
- IN UINT16 TableName,
- OUT EFI_PHYSICAL_ADDRESS *Address
- );
-#endif //_INTERNAL_BOOT_SCRIPT_SAVE_H_
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c b/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c
deleted file mode 100644
index 837a8c95cd..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c
+++ /dev/null
@@ -1,626 +0,0 @@
-/** @file
- Implementation for S3 Boot Script Saver driver.
-
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-**/
-
-#include "InternalBootScriptSave.h"
-
-EFI_HANDLE mHandle = NULL;
-EFI_BOOT_SCRIPT_SAVE_PROTOCOL mS3ScriptSave = {
- BootScriptWrite,
- BootScriptCloseTable
- };
-
-/**
- Internal function to add IO write opcode to the table.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptIoWrite (
- IN VA_LIST Marker
- )
-{
- S3_BOOT_SCRIPT_LIB_WIDTH Width;
- UINT64 Address;
- UINTN Count;
- UINT8 *Buffer;
-
- Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
- Address = VA_ARG (Marker, UINT64);
- Count = VA_ARG (Marker, UINTN);
- Buffer = VA_ARG (Marker, UINT8 *);
-
- return S3BootScriptSaveIoWrite (Width, Address, Count, Buffer);
-}
-
-/**
- Internal function to add IO read/write opcode to the table.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptIoReadWrite (
- IN VA_LIST Marker
- )
-{
- S3_BOOT_SCRIPT_LIB_WIDTH Width;
- UINT64 Address;
- UINT8 *Data;
- UINT8 *DataMask;
-
- Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
- Address = VA_ARG (Marker, UINT64);
- Data = VA_ARG (Marker, UINT8 *);
- DataMask = VA_ARG (Marker, UINT8 *);
-
- return S3BootScriptSaveIoReadWrite (Width, Address, Data, DataMask);
-}
-
-/**
- Internal function to add memory write opcode to the table.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptMemWrite (
- IN VA_LIST Marker
- )
-{
- S3_BOOT_SCRIPT_LIB_WIDTH Width;
- UINT64 Address;
- UINTN Count;
- UINT8 *Buffer;
-
- Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
- Address = VA_ARG (Marker, UINT64);
- Count = VA_ARG (Marker, UINTN);
- Buffer = VA_ARG (Marker, UINT8 *);
-
- return S3BootScriptSaveMemWrite (Width, Address, Count, Buffer);
-}
-
-/**
- Internal function to add memory read/write opcode to the table.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptMemReadWrite (
- IN VA_LIST Marker
- )
-{
- S3_BOOT_SCRIPT_LIB_WIDTH Width;
- UINT64 Address;
- UINT8 *Data;
- UINT8 *DataMask;
-
- Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
- Address = VA_ARG (Marker, UINT64);
- Data = VA_ARG (Marker, UINT8 *);
- DataMask = VA_ARG (Marker, UINT8 *);
-
- return S3BootScriptSaveMemReadWrite (Width, Address, Data, DataMask);
-}
-
-/**
- Internal function to add PciCfg write opcode to the table.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptPciCfgWrite (
- IN VA_LIST Marker
- )
-{
- S3_BOOT_SCRIPT_LIB_WIDTH Width;
- UINT64 Address;
- UINTN Count;
- UINT8 *Buffer;
-
- Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
- Address = VA_ARG (Marker, UINT64);
- Count = VA_ARG (Marker, UINTN);
- Buffer = VA_ARG (Marker, UINT8 *);
-
- return S3BootScriptSavePciCfgWrite (Width, Address, Count, Buffer);
-}
-
-/**
- Internal function to PciCfg read/write opcode to the table.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptPciCfgReadWrite (
- IN VA_LIST Marker
- )
-{
- S3_BOOT_SCRIPT_LIB_WIDTH Width;
- UINT64 Address;
- UINT8 *Data;
- UINT8 *DataMask;
-
- Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
- Address = VA_ARG (Marker, UINT64);
- Data = VA_ARG (Marker, UINT8 *);
- DataMask = VA_ARG (Marker, UINT8 *);
-
- return S3BootScriptSavePciCfgReadWrite (Width, Address, Data, DataMask);
-}
-
-/**
- Internal function to add PciCfg2 write opcode to the table.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptPciCfg2Write (
- IN VA_LIST Marker
- )
-{
- S3_BOOT_SCRIPT_LIB_WIDTH Width;
- UINT64 Address;
- UINTN Count;
- UINT8 *Buffer;
- UINT16 Segment;
-
- Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
- Address = VA_ARG (Marker, UINT64);
- Count = VA_ARG (Marker, UINTN);
- Buffer = VA_ARG (Marker, UINT8 *);
- Segment = VA_ARG (Marker, UINT16);
-
- return S3BootScriptSavePciCfg2Write (Width, Segment, Address, Count, Buffer);
-}
-
-/**
- Internal function to PciCfg2 read/write opcode to the table.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptPciCfg2ReadWrite (
- IN VA_LIST Marker
- )
-{
- S3_BOOT_SCRIPT_LIB_WIDTH Width;
- UINT16 Segment;
- UINT64 Address;
- UINT8 *Data;
- UINT8 *DataMask;
-
- Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
- Address = VA_ARG (Marker, UINT64);
- Segment = VA_ARG (Marker, UINT16);
- Data = VA_ARG (Marker, UINT8 *);
- DataMask = VA_ARG (Marker, UINT8 *);
-
- return S3BootScriptSavePciCfg2ReadWrite (Width, Segment, Address, Data, DataMask);
-}
-
-/**
- Internal function to add smbus execute opcode to the table.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptSmbusExecute (
- IN VA_LIST Marker
- )
-{
- EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
- EFI_SMBUS_DEVICE_COMMAND Command;
- EFI_SMBUS_OPERATION Operation;
- BOOLEAN PecCheck;
- VOID *Buffer;
- UINTN *DataSize;
- UINTN SmBusAddress;
-
- SlaveAddress.SmbusDeviceAddress = VA_ARG (Marker, UINTN);
- Command = VA_ARG (Marker, EFI_SMBUS_DEVICE_COMMAND);
- Operation = VA_ARG (Marker, EFI_SMBUS_OPERATION);
- PecCheck = VA_ARG (Marker, BOOLEAN);
- SmBusAddress = SMBUS_LIB_ADDRESS (SlaveAddress.SmbusDeviceAddress,Command,0,PecCheck);
- DataSize = VA_ARG (Marker, UINTN *);
- Buffer = VA_ARG (Marker, VOID *);
-
- return S3BootScriptSaveSmbusExecute (SmBusAddress, Operation, DataSize, Buffer);
-}
-
-/**
- Internal function to add stall opcode to the table.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptStall (
- IN VA_LIST Marker
- )
-{
- UINT32 Duration;
-
- Duration = VA_ARG (Marker, UINT32);
-
- return S3BootScriptSaveStall (Duration);
-}
-
-/**
- Internal function to add Save jmp address according to DISPATCH_OPCODE.
- We ignore "Context" parameter.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptDispatch (
- IN VA_LIST Marker
- )
-{
- VOID *EntryPoint;
-
- EntryPoint = (VOID*)(UINTN)VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);
- return S3BootScriptSaveDispatch (EntryPoint);
-}
-
-/**
- Internal function to add memory pool operation to the table.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptMemPoll (
- IN VA_LIST Marker
- )
-{
- S3_BOOT_SCRIPT_LIB_WIDTH Width;
- UINT64 Address;
- UINT8 *BitMask;
- UINT8 *BitValue;
- UINTN Duration;
- UINT64 LoopTimes;
-
- Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
- Address = VA_ARG (Marker, UINT64);
- BitMask = VA_ARG (Marker, UINT8 *);
- BitValue = VA_ARG (Marker, UINT8 *);
- Duration = (UINTN)VA_ARG (Marker, UINT64);
- LoopTimes = VA_ARG (Marker, UINT64);
-
- return S3BootScriptSaveMemPoll (Width, Address, BitMask, BitValue, Duration, LoopTimes);
-}
-
-/**
- Internal function to add Save jmp address according to DISPATCH_OPCODE2.
- The "Context" parameter is not ignored.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
- @retval EFI_SUCCESS Opcode is added.
-
-**/
-EFI_STATUS
-BootScriptDispatch2 (
- IN VA_LIST Marker
- )
-{
- VOID *EntryPoint;
- VOID *Context;
-
- EntryPoint = (VOID*)(UINTN)VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);
- Context = (VOID*)(UINTN)VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);
-
- return S3BootScriptSaveDispatch2 (EntryPoint, Context);
-}
-
-/**
- Internal function to add the opcode link node to the link list.
-
- @param Marker The variable argument list to get the opcode
- and associated attributes.
-
- @retval EFI_OUT_OF_RESOURCES Not enought resource to complete the operations.
- @retval EFI_SUCCESS The opcode entry is added to the link list
- successfully.
-**/
-EFI_STATUS
-BootScriptInformation (
- IN VA_LIST Marker
- )
-{
- UINT32 InformationLength;
- EFI_PHYSICAL_ADDRESS Information;
-
- InformationLength = VA_ARG (Marker, UINT32);
- Information = VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);
- return S3BootScriptSaveInformation (InformationLength, (VOID*)(UINTN)Information);
-}
-
-/**
- Adds a record into a specified Framework boot script table.
-
- This function is used to store a boot script record into a given boot
- script table. If the table specified by TableName is nonexistent in the
- system, a new table will automatically be created and then the script record
- will be added into the new table. A boot script table can add new script records
- until EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable() is called. Currently, the only
- meaningful table name is EFI_ACPI_S3_RESUME_SCRIPT_TABLE. This function is
- responsible for allocating necessary memory for the script.
-
- This function has a variable parameter list. The exact parameter list depends on
- the OpCode that is passed into the function. If an unsupported OpCode or illegal
- parameter list is passed in, this function returns EFI_INVALID_PARAMETER.
- If there are not enough resources available for storing more scripts, this function returns
- EFI_OUT_OF_RESOURCES.
-
- @param This A pointer to the EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.
- @param TableName Name of the script table. Currently, the only meaningful value is
- EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
- @param OpCode The operation code (opcode) number.
- @param ... Argument list that is specific to each opcode.
-
- @retval EFI_SUCCESS The operation succeeded. A record was added into the
- specified script table.
- @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script is not supported.
- If the opcode is unknow or not supported because of the PCD
- Feature Flags.
- @retval EFI_OUT_OF_RESOURCES There is insufficient memory to store the boot script.
-
-**/
-EFI_STATUS
-EFIAPI
-BootScriptWrite (
- IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL *This,
- IN UINT16 TableName,
- IN UINT16 OpCode,
- ...
- )
-{
- EFI_STATUS Status;
- VA_LIST Marker;
-
- if (TableName != FRAMEWORK_EFI_ACPI_S3_RESUME_SCRIPT_TABLE) {
- //
- // Only S3 boot script is supported for now.
- //
- return EFI_OUT_OF_RESOURCES;
- }
-
- //
- // Build script according to opcode.
- //
- switch (OpCode) {
-
- case EFI_BOOT_SCRIPT_IO_WRITE_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptIoWrite (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptIoReadWrite (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptMemWrite (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptMemReadWrite (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptPciCfgWrite (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptPciCfgReadWrite (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptSmbusExecute (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_STALL_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptStall (Marker);
- VA_END (Marker);
-
- break;
-
- case EFI_BOOT_SCRIPT_DISPATCH_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptDispatch (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptDispatch2 (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_INFORMATION_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptInformation (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_MEM_POLL_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptMemPoll (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptPciCfg2Write (Marker);
- VA_END (Marker);
- break;
-
- case EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE:
- VA_START (Marker, OpCode);
- Status = BootScriptPciCfg2ReadWrite (Marker);
- VA_END (Marker);
- break;
-
- default:
- Status = EFI_INVALID_PARAMETER;
- break;
- }
-
- return Status;
-}
-
-/**
- Closes the specified script table.
-
- This function closes the specified boot script table and returns the base address
- of the table. It allocates a new pool to duplicate all the boot scripts in the specified
- table. Once this function is called, the specified table will be destroyed after it is
- copied into the allocated pool. As a result, any attempts to add a script record into a
- closed table will cause a new table to be created. The base address of the allocated pool
- will be returned in Address. After using the boot script table, the caller is responsible
- for freeing the pool that is allocated by this function. If the boot script table,
- such as EFI_ACPI_S3_RESUME_SCRIPT_TABLE, is required to be stored in a nonperturbed
- memory region, the caller should copy the table into the nonperturbed memory region by itself.
-
- @param This A pointer to the EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.
- @param TableName Name of the script table. Currently, the only meaningful value is
- EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
- @param Address A pointer to the physical address where the table begins.
-
- @retval EFI_SUCCESS The table was successfully returned.
- @retval EFI_NOT_FOUND The specified table was not created previously.
- @retval EFI_OUT_OF_RESOURCE Memory is insufficient to hold the reorganized boot script table.
- @retval EFI_UNSUPPORTED The table type is not EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
-
-**/
-EFI_STATUS
-EFIAPI
-BootScriptCloseTable (
- IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL *This,
- IN UINT16 TableName,
- OUT EFI_PHYSICAL_ADDRESS *Address
- )
-{
- if (TableName != FRAMEWORK_EFI_ACPI_S3_RESUME_SCRIPT_TABLE) {
- //
- // Only S3 boot script is supported for now.
- //
- return EFI_NOT_FOUND;
- }
- *Address = (EFI_PHYSICAL_ADDRESS)(UINTN)S3BootScriptCloseTable ();
-
- if (*Address == 0) {
- return EFI_NOT_FOUND;
- }
- return EFI_SUCCESS;
-}
-
-/**
- This routine is entry point of ScriptSave driver.
-
- @param ImageHandle Handle for this drivers loaded image protocol.
- @param SystemTable EFI system table.
-
- @retval EFI_OUT_OF_RESOURCES No enough resource.
- @retval EFI_SUCCESS Succesfully installed the ScriptSave driver.
- @retval other Errors occured.
-
-**/
-EFI_STATUS
-EFIAPI
-InitializeScriptSave (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- return gBS->InstallProtocolInterface (
- &mHandle,
- &gEfiBootScriptSaveProtocolGuid,
- EFI_NATIVE_INTERFACE,
- &mS3ScriptSave
- );
-
-}
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin b/Platform/Intel/Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin
deleted file mode 100644
index da24c02b5d25ce888c630c664095902b4bb035e7..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.c b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.c
deleted file mode 100644
index bf6c7efba5..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/** @file
- This PEIM will parse the hoblist from fsp and report them into pei core.
- This file contains the main entrypoint of the PEIM.
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-#include <PiPei.h>
-#include <Ppi/MasterBootMode.h>
-
-static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
- &gEfiPeiMasterBootModePpiGuid,
- NULL
- },
-};
-
-/**
- This is the entrypoint of PEIM
-
- @param FileHandle Handle of the file being invoked.
- @param PeiServices Describes the list of possible PEI Services.
-
- @retval EFI_SUCCESS if it completed successfully.
-**/
-EFI_STATUS
-EFIAPI
-BootModePeiEntryPoint (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- (*PeiServices)->SetBootMode(PeiServices, BOOT_WITH_FULL_CONFIGURATION);
-
- (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
deleted file mode 100644
index 27200bca15..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
+++ /dev/null
@@ -1,40 +0,0 @@
-## @file
-# FSP PEI Module
-#
-# Parses the hoblist from fsp and report them into pei core. It will install
-# the memory as required.
-#
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = BootModePeim
- FILE_GUID = 2B1D0832-2184-4C8F-A90D-8E4AF9DE5BCD
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = BootModePeiEntryPoint
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32
-#
-
-[Sources]
- BootModePei.c
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- PeimEntryPoint
-
-[Ppis]
- gEfiPeiMasterBootModePpiGuid
-
-[Depex]
- TRUE
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.c b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.c
deleted file mode 100644
index 8a97e25bd4..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.c
+++ /dev/null
@@ -1,421 +0,0 @@
-/** @file
- Null instance of Platform Sec Lib.
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Library/PeiServicesLib.h>
-#include <Library/PeiServicesTablePointerLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/HobLib.h>
-#include <Library/PcdLib.h>
-#include <Library/FspPlatformInfoLib.h>
-
-#include <Guid/GuidHobFsp.h>
-#include <Guid/MemoryTypeInformation.h>
-#include <Ppi/Capsule.h>
-
-#include <PlatformFspLib.h>
-#include <Guid/SmramMemoryReserve.h>
-EFI_GUID gFspReservedMemoryResourceHobTsegGuid = {0xd038747c, 0xd00c, 0x4980, {0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55}};
-
-//
-// Additional pages are used by DXE memory manager.
-// It should be consistent between RetrieveRequiredMemorySize() and GetPeiMemSize()
-//
-#define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE)
-
-/**
- Get the mem size in memory type infromation table.
-
- @param PeiServices PEI Services table.
-
- @return the mem size in memory type infromation table.
-**/
-UINT64
-GetMemorySizeInMemoryTypeInformation (
- IN EFI_PEI_SERVICES **PeiServices
- )
-{
- EFI_PEI_HOB_POINTERS Hob;
- EFI_MEMORY_TYPE_INFORMATION *MemoryData;
- UINT8 Index;
- UINTN TempPageNum;
-
- MemoryData = NULL;
- (*PeiServices)->GetHobList ((CONST EFI_PEI_SERVICES **)PeiServices, (VOID **) &Hob.Raw);
- while (!END_OF_HOB_LIST (Hob)) {
- if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION &&
- CompareGuid (&Hob.Guid->Name, &gEfiMemoryTypeInformationGuid)) {
- MemoryData = (EFI_MEMORY_TYPE_INFORMATION *) (Hob.Raw + sizeof (EFI_HOB_GENERIC_HEADER) + sizeof (EFI_GUID));
- break;
- }
-
- Hob.Raw = GET_NEXT_HOB (Hob);
- }
-
- if (MemoryData == NULL) {
- return 0;
- }
-
- TempPageNum = 0;
- for (Index = 0; MemoryData[Index].Type != EfiMaxMemoryType; Index++) {
- //
- // Accumulate default memory size requirements
- //
- TempPageNum += MemoryData[Index].NumberOfPages;
- }
-
- return TempPageNum * EFI_PAGE_SIZE;
-}
-
-/**
- Get the mem size need to be reserved in PEI phase.
-
- @param PeiServices PEI Services table.
-
- @return the mem size need to be reserved in PEI phase.
-**/
-UINT64
-RetrieveRequiredMemorySize (
- IN EFI_PEI_SERVICES **PeiServices
- )
-{
- UINT64 Size;
-
- Size = GetMemorySizeInMemoryTypeInformation (PeiServices);
- return Size + PEI_ADDITIONAL_MEMORY_SIZE;
-}
-
-/**
- Get the mem size need to be consumed and reserved in PEI phase.
-
- @param PeiServices PEI Services table.
- @param BootMode Current boot mode.
-
- @return the mem size need to be consumed and reserved in PEI phase.
-**/
-UINT64
-GetPeiMemSize (
- IN EFI_PEI_SERVICES **PeiServices,
- IN UINT32 BootMode
- )
-{
- UINT64 Size;
- UINT64 MinSize;
-
- if (BootMode == BOOT_IN_RECOVERY_MODE) {
- return PcdGet32 (PcdPeiRecoveryMinMemSize);
- }
-
- Size = GetMemorySizeInMemoryTypeInformation (PeiServices);
-
- if (BootMode == BOOT_ON_FLASH_UPDATE) {
- //
- // Maybe more size when in CapsuleUpdate phase ?
- //
- MinSize = PcdGet32 (PcdPeiMinMemSize);
- } else {
- MinSize = PcdGet32 (PcdPeiMinMemSize);
- }
-
- return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE;
-}
-
-/**
- BIOS process FspBobList.
-
- @param FspHobList Pointer to the HOB data structure produced by FSP.
-
- @return If platform process the FSP hob list successfully.
-**/
-EFI_STATUS
-EFIAPI
-FspHobProcessForMemoryResource (
- IN VOID *FspHobList
- )
-{
- EFI_PEI_HOB_POINTERS Hob;
- UINT64 LowMemorySize;
- UINT64 FspMemorySize;
- EFI_PHYSICAL_ADDRESS FspMemoryBase;
- UINT64 PeiMemSize;
- EFI_PHYSICAL_ADDRESS PeiMemBase;
- UINT64 S3PeiMemSize;
- EFI_PHYSICAL_ADDRESS S3PeiMemBase;
- BOOLEAN FoundFspMemHob;
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
- PEI_CAPSULE_PPI *Capsule;
- VOID *CapsuleBuffer;
- UINTN CapsuleBufferLength;
- UINT64 RequiredMemSize;
- EFI_PEI_SERVICES **PeiServices;
- UINT64 TsegSize;
- EFI_PHYSICAL_ADDRESS TsegBase;
- BOOLEAN FoundTsegHob;
-
- PeiServices = (EFI_PEI_SERVICES **)GetPeiServicesTablePointer ();
-
- PeiServicesGetBootMode (&BootMode);
-
- PeiMemBase = 0;
- LowMemorySize = 0;
- FspMemorySize = 0;
- FspMemoryBase = 0;
- FoundFspMemHob = FALSE;
- TsegSize = 0;
- TsegBase = 0;
- FoundTsegHob = FALSE;
-
- //
- // Parse the hob list from fsp
- // Report all the resource hob except the memory between 1M and 4G
- //
- Hob.Raw = (UINT8 *)(UINTN)FspHobList;
- DEBUG((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
-
- while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw)) != NULL) {
- DEBUG((DEBUG_INFO, "\nResourceType: 0x%x\n", Hob.ResourceDescriptor->ResourceType));
- if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
- (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED)) {
- DEBUG((DEBUG_INFO, "ResourceAttribute: 0x%x\n", Hob.ResourceDescriptor->ResourceAttribute));
- DEBUG((DEBUG_INFO, "PhysicalStart: 0x%x\n", Hob.ResourceDescriptor->PhysicalStart));
- DEBUG((DEBUG_INFO, "ResourceLength: 0x%x\n", Hob.ResourceDescriptor->ResourceLength));
- DEBUG((DEBUG_INFO, "Owner: %g\n\n", &Hob.ResourceDescriptor->Owner));
- }
-
- if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) // Found the low memory length below 4G
- && (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB)
- && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength <= BASE_4GB)) {
- LowMemorySize += Hob.ResourceDescriptor->ResourceLength;
- Hob.Raw = GET_NEXT_HOB (Hob);
- continue;
- }
-
- if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) // Found the low memory length below 4G
- && (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB)
- && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength <= BASE_4GB)
- && (CompareGuid (&Hob.ResourceDescriptor->Owner, &gFspReservedMemoryResourceHobGuid))) {
- FoundFspMemHob = TRUE;
- FspMemoryBase = Hob.ResourceDescriptor->PhysicalStart;
- FspMemorySize = Hob.ResourceDescriptor->ResourceLength;
- DEBUG((DEBUG_INFO, "Find fsp mem hob, base 0x%x, len 0x%x\n", FspMemoryBase, FspMemorySize));
- }
-
- if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) // Found the low memory length below 4G
- && (Hob.ResourceDescriptor->PhysicalStart >= 0x100000)
- && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength <= 0x100000000)
- && (CompareGuid (&Hob.ResourceDescriptor->Owner, &gFspReservedMemoryResourceHobTsegGuid))) {
- FoundTsegHob = TRUE;
- TsegBase = Hob.ResourceDescriptor->PhysicalStart;
-
-
- if ((Hob.ResourceDescriptor->ResourceLength == 0 ) || (Hob.ResourceDescriptor->ResourceLength > 0x800000)){
- Hob.ResourceDescriptor->ResourceLength = 0x800000;
- }
-
-
- TsegSize = Hob.ResourceDescriptor->ResourceLength;
- DEBUG((EFI_D_ERROR, "Find Tseg mem hob, base 0x%lx, len 0x%lx\n", TsegBase, TsegSize));
- }
-
- //
- // Report the resource hob
- //
- BuildResourceDescriptorHob (
- Hob.ResourceDescriptor->ResourceType,
- Hob.ResourceDescriptor->ResourceAttribute,
- Hob.ResourceDescriptor->PhysicalStart,
- Hob.ResourceDescriptor->ResourceLength
- );
-
- Hob.Raw = GET_NEXT_HOB (Hob);
- }
-
- if (!FoundFspMemHob) {
- DEBUG((DEBUG_INFO, "Didn't find the fsp used memory information.\n"));
- //ASSERT(FALSE);
- }
-
- DEBUG((DEBUG_INFO, "LowMemorySize: 0x%x.\n", LowMemorySize));
- DEBUG((DEBUG_INFO, "FspMemoryBase: 0x%x.\n", FspMemoryBase));
- DEBUG((DEBUG_INFO, "FspMemorySize: 0x%x.\n", FspMemorySize));
-
- if (BootMode == BOOT_ON_S3_RESUME) {
- BuildResourceDescriptorHob (
- EFI_RESOURCE_SYSTEM_MEMORY,
- (
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- // EFI_RESOURCE_ATTRIBUTE_TESTED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
- ),
- BASE_1MB,
- LowMemorySize
- );
-
- Status = GetS3MemoryInfo (&S3PeiMemBase, &S3PeiMemSize);
- ASSERT_EFI_ERROR (Status);
- DEBUG((DEBUG_INFO, "S3 memory %Xh - %Xh bytes\n", S3PeiMemBase, S3PeiMemSize));
-
- //
- // Make sure Stack and PeiMemory are not overlap - JYAO1
- //
-
- Status = PeiServicesInstallPeiMemory (
- S3PeiMemBase,
- S3PeiMemSize
- );
- ASSERT_EFI_ERROR (Status);
- } else {
- PeiMemSize = GetPeiMemSize (PeiServices, BootMode);
- DEBUG((DEBUG_INFO, "PEI memory size = %Xh bytes\n", PeiMemSize));
-
- //
- // Capsule mode
- //
- Capsule = NULL;
- CapsuleBuffer = NULL;
- CapsuleBufferLength = 0;
- if (BootMode == BOOT_ON_FLASH_UPDATE) {
- Status = PeiServicesLocatePpi (
- &gPeiCapsulePpiGuid,
- 0,
- NULL,
- (VOID **) &Capsule
- );
- ASSERT_EFI_ERROR (Status);
-
- if (Status == EFI_SUCCESS) {
- //
- // Make sure Stack and CapsuleBuffer are not overlap - JYAO1
- //
- CapsuleBuffer = (VOID *)(UINTN)BASE_1MB;
- CapsuleBufferLength = (UINTN)(LowMemorySize - PeiMemSize);
- //
- // Call the Capsule PPI Coalesce function to coalesce the capsule data.
- //
- Status = Capsule->Coalesce (PeiServices, &CapsuleBuffer, &CapsuleBufferLength);
- }
- }
-
- RequiredMemSize = RetrieveRequiredMemorySize (PeiServices);
- DEBUG((DEBUG_INFO, "Required memory size = %Xh bytes\n", RequiredMemSize));
-
- //
- // Report the main memory
- //
- BuildResourceDescriptorHob (
- EFI_RESOURCE_SYSTEM_MEMORY,
- (
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_TESTED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
- ),
- BASE_1MB,
- LowMemorySize
- );
-
- //
- // Make sure Stack and CapsuleBuffer are not overlap - JYAO1
- //
-
- //
- // Install efi memory
- //
- PeiMemBase = BASE_1MB + LowMemorySize - PeiMemSize;
- Status = PeiServicesInstallPeiMemory (
- PeiMemBase,
- PeiMemSize - RequiredMemSize
- );
- ASSERT_EFI_ERROR (Status);
-
- if (Capsule != NULL) {
- Status = Capsule->CreateState (PeiServices, CapsuleBuffer, CapsuleBufferLength);
- }
- }
-
- //
- // Report GUIDed HOB for reserving SMRAM regions
- //
- if (FoundTsegHob) {
- EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
-
- SmramHobDescriptorBlock = BuildGuidHob (
- &gEfiSmmPeiSmramMemoryReserveGuid,
- sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK)
- );
- ASSERT (SmramHobDescriptorBlock != NULL);
-
- SmramHobDescriptorBlock->NumberOfSmmReservedRegions = 1;
-
- SmramHobDescriptorBlock->Descriptor[0].PhysicalStart = TsegBase;
- SmramHobDescriptorBlock->Descriptor[0].CpuStart = TsegBase;
- SmramHobDescriptorBlock->Descriptor[0].PhysicalSize = TsegSize;
- SmramHobDescriptorBlock->Descriptor[0].RegionState = EFI_SMRAM_CLOSED;
- }
- return EFI_SUCCESS;
-}
-
-/**
- BIOS process FspBobList for other data (not Memory Resource Descriptor).
-
- @param[in] FspHobList Pointer to the HOB data structure produced by FSP.
-
- @return If platform process the FSP hob list successfully.
-**/
-EFI_STATUS
-EFIAPI
-FspHobProcessForOtherData (
- IN VOID *FspHobList
- )
-{
- EFI_PEI_SERVICES **PeiServices;
-
- PeiServices = (EFI_PEI_SERVICES **)GetPeiServicesTablePointer ();
-
- //
- // Other hob for platform
- //
- PlatformHobCreateFromFsp ((CONST EFI_PEI_SERVICES **) PeiServices, FspHobList);
-
- return EFI_SUCCESS;
-}
-
-/**
- BIOS process FspBobList.
-
- @param[in] FspHobList Pointer to the HOB data structure produced by FSP.
-
- @return If platform process the FSP hob list successfully.
-**/
-EFI_STATUS
-EFIAPI
-FspHobProcess (
- IN VOID *FspHobList
- )
-{
- EFI_STATUS Status;
-
- Status = FspHobProcessForMemoryResource (FspHobList);
- if (EFI_ERROR (Status)) {
- return Status;
- }
- Status = FspHobProcessForOtherData (FspHobList);
-
- return Status;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf
deleted file mode 100644
index b789b27f4c..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf
+++ /dev/null
@@ -1,74 +0,0 @@
-## @file
-#
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PeiFspHobProcessLibVlv2
- FILE_GUID = C7B7070B-E5A8-4b86-9110-BDCA1095F496
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
- LIBRARY_CLASS = FspHobProcessLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64
-#
-
-################################################################################
-#
-# Sources Section - list of files that are required for the build to succeed.
-#
-################################################################################
-
-[Sources]
- FspHobProcessLibVlv2.c
-
-
-################################################################################
-#
-# Package Dependency Section - list of Package files that are required for
-# this module.
-#
-################################################################################
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- IntelFrameworkPkg/IntelFrameworkPkg.dec
- IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
- IntelFspPkg/IntelFspPkg.dec
- IntelFspWrapperPkg/IntelFspWrapperPkg.dec
- Vlv2TbltDevicePkg/PlatformPkg.dec
-
-[LibraryClasses]
- BaseLib
- BaseMemoryLib
- HobLib
- DebugLib
- FspPlatformInfoLib
- PeiServicesLib
- PeiServicesTablePointerLib
- PlatformFspLib
-
-[Pcd]
- gFspWrapperTokenSpaceGuid.PcdPeiMinMemSize
- gFspWrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize
-
-[Guids]
- gFspReservedMemoryResourceHobGuid
- gEfiMemoryTypeInformationGuid
- gEfiSmmPeiSmramMemoryReserveGuid
-
-[Ppis]
- gPeiCapsulePpiGuid
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.c b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.c
deleted file mode 100644
index 2b03cfaec9..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/** @file
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPlatformInformation.h>
-#include <Ppi/SecPerformance.h>
-#include <Ppi/TemporaryRamSupport.h>
-
-#include <Library/LocalApicLib.h>
-
-/**
- This interface conveys state information out of the Security (SEC) phase into PEI.
-
- @param PeiServices Pointer to the PEI Services Table.
- @param StructureSize Pointer to the variable describing size of the input buffer.
- @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
-
-**/
-EFI_STATUS
-EFIAPI
-SecPlatformInformation (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
- );
-
-/**
- This interface conveys performance information out of the Security (SEC) phase into PEI.
-
- This service is published by the SEC phase. The SEC phase handoff has an optional
- EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
- PEI Foundation. As such, if the platform supports collecting performance data in SEC,
- this information is encapsulated into the data structure abstracted by this service.
- This information is collected for the boot-strap processor (BSP) on IA-32.
-
- @param[in] PeiServices The pointer to the PEI Services Table.
- @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
- @param[out] Performance The pointer to performance data collected in SEC phase.
-
- @retval EFI_SUCCESS The data was successfully returned.
-
-**/
-EFI_STATUS
-EFIAPI
-SecGetPerformance (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN PEI_SEC_PERFORMANCE_PPI *This,
- OUT FIRMWARE_SEC_PERFORMANCE *Performance
- );
-
-/**
- This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into
- permanent memory.
-
- @param PeiServices Pointer to the PEI Services Table.
- @param TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the
- Temporary RAM contents.
- @param PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the
- Temporary RAM contents.
- @param CopySize Amount of memory to migrate from temporary to permanent memory.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when
- TemporaryMemoryBase > PermanentMemoryBase.
-
-**/
-EFI_STATUS
-EFIAPI
-SecTemporaryRamSupport (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
- IN UINTN CopySize
- );
-
-EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInformationPpi = {
- SecPlatformInformation
-};
-
-PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
- SecGetPerformance
-};
-
-EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi = {
- SecTemporaryRamSupport
-};
-
-EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gEfiSecPlatformInformationPpiGuid,
- &mSecPlatformInformationPpi
- },
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gPeiSecPerformancePpiGuid,
- &mSecPerformancePpi
- },
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
- &gEfiTemporaryRamSupportPpiGuid,
- &gSecTemporaryRamSupportPpi
- },
-};
-
-/**
- A developer supplied function to perform platform specific operations.
-
- It's a developer supplied function to perform any operations appropriate to a
- given platform. It's invoked just before passing control to PEI core by SEC
- core. Platform developer may modify the SecCoreData passed to PEI Core.
- It returns a platform specific PPI list that platform wishes to pass to PEI core.
- The Generic SEC core module will merge this list to join the final list passed to
- PEI core.
-
- @param SecCoreData The same parameter as passing to PEI core. It
- could be overridden by this function.
-
- @return The platform specific PPI list to be passed to PEI core or
- NULL if there is no need of such platform specific PPI list.
-
-**/
-EFI_PEI_PPI_DESCRIPTOR *
-EFIAPI
-SecPlatformMain (
- IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
- )
-{
- EFI_PEI_PPI_DESCRIPTOR *PpiList;
-
- InitializeApicTimer (0, (UINT32) -1, TRUE, 5);
-
- PpiList = &mPeiSecPlatformPpi[0];
-
- return PpiList;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf
deleted file mode 100644
index 578066d98f..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf
+++ /dev/null
@@ -1,82 +0,0 @@
-## @file
-#
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = SecPeiFspPlatformSecLibVlv2
- FILE_GUID = 6653876C-F6A1-45BB-A027-20455093BC6D
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
- LIBRARY_CLASS = FspPlatformSecLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64
-#
-
-################################################################################
-#
-# Sources Section - list of files that are required for the build to succeed.
-#
-################################################################################
-
-[Sources]
- FspPlatformSecLibVlv2.c
- SecRamInitData.c
- SaveSecContext.c
- SecPlatformInformation.c
- SecGetPerformance.c
- SecTempRamSupport.c
- PlatformInit.c
- UartInit.c
-
-[Sources.IA32]
- Ia32/SecEntry.asm
- Ia32/PeiCoreEntry.asm
- Ia32/AsmSaveSecContext.asm
- Ia32/Stack.asm
-
-################################################################################
-#
-# Package Dependency Section - list of Package files that are required for
-# this module.
-#
-################################################################################
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
- IntelFspWrapperPkg/IntelFspWrapperPkg.dec
-
-[LibraryClasses]
- LocalApicLib
- SerialPortLib
-
-[Ppis]
- gEfiSecPlatformInformationPpiGuid
- gPeiSecPerformancePpiGuid
- gEfiTemporaryRamSupportPpiGuid
-
-[Pcd]
- gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize
- gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase
- gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize
-
-[FixedPcd]
- gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress
- gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
- gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset
- gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress
- gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/AsmSaveSecContext.asm b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/AsmSaveSecContext.asm
deleted file mode 100644
index 2546a09a1a..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/AsmSaveSecContext.asm
+++ /dev/null
@@ -1,45 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-; Module Name:
-;
-; SecEntry.asm
-;
-; Abstract:
-;
-; This is the code that goes from real-mode to protected mode.
-; It consumes the reset vector, calls two basic APIs from FSP binary.
-;
-;------------------------------------------------------------------------------
-
-.686p
-.xmm
-.model flat,c
-.code
-
-;----------------------------------------------------------------------------
-; MMX Usage:
-; MM0 = BIST State
-; MM5 = Save time-stamp counter value high32bit
-; MM6 = Save time-stamp counter value low32bit.
-;
-; It should be same as SecEntry.asm and PeiCoreEntry.asm.
-;----------------------------------------------------------------------------
-
-AsmSaveBistValue PROC PUBLIC
- mov eax, [esp+4]
- movd mm0, eax
- ret
-AsmSaveBistValue ENDP
-
-AsmSaveTickerValue PROC PUBLIC
- mov eax, [esp+4]
- movd mm6, eax
- mov eax, [esp+8]
- movd mm5, eax
- ret
-AsmSaveTickerValue ENDP
-
-END
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Fsp.inc b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Fsp.inc
deleted file mode 100644
index 23295587b4..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Fsp.inc
+++ /dev/null
@@ -1,45 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-; Module Name:
-;
-; Fsp.inc
-;
-; Abstract:
-;
-; Fsp related definitions
-;
-;------------------------------------------------------------------------------
-
-
-;
-; Fv Header
-;
-FVH_SIGINATURE_OFFSET EQU 028h
-FVH_SIGINATURE_VALID_VALUE EQU 04856465Fh ; valid signature:_FVH
-FVH_HEADER_LENGTH_OFFSET EQU 030h
-FVH_EXTHEADER_OFFSET_OFFSET EQU 034h
-FVH_EXTHEADER_SIZE_OFFSET EQU 010h
-
-;
-; Ffs Header
-;
-FSP_HEADER_GUID_DWORD1 EQU 0912740BEh
-FSP_HEADER_GUID_DWORD2 EQU 047342284h
-FSP_HEADER_GUID_DWORD3 EQU 0B08471B9h
-FSP_HEADER_GUID_DWORD4 EQU 00C3F3527h
-FFS_HEADER_SIZE_VALUE EQU 018h
-
-;
-; Section Header
-;
-SECTION_HEADER_TYPE_OFFSET EQU 03h
-RAW_SECTION_HEADER_SIZE_VALUE EQU 04h
-
-;
-; Fsp Header
-;
-FSP_HEADER_IMAGEBASE_OFFSET EQU 01Ch
-FSP_HEADER_TEMPRAMINIT_OFFSET EQU 030h
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/PeiCoreEntry.asm b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/PeiCoreEntry.asm
deleted file mode 100644
index 3d34c62ea4..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/PeiCoreEntry.asm
+++ /dev/null
@@ -1,135 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-; Module Name:
-;
-; SecEntry.asm
-;
-; Abstract:
-;
-; This is the code that goes from real-mode to protected mode.
-; It consumes the reset vector, calls two basic APIs from FSP binary.
-;
-;------------------------------------------------------------------------------
-
-.686p
-.xmm
-.model flat, c
-.code
-
-EXTRN SecStartup:NEAR
-EXTRN PlatformInit:NEAR
-
-CallPeiCoreEntryPoint PROC PUBLIC
- ;
- ; Obtain the hob list pointer
- ;
- mov eax, [esp+4]
- ;
- ; Obtain the stack information
- ; ECX: start of range
- ; EDX: end of range
- ;
- mov ecx, [esp+8]
- mov edx, [esp+0Ch]
-
- ;
- ; Platform init
- ;
- pushad
- push edx
- push ecx
- push eax
- call PlatformInit
- pop eax
- pop eax
- pop eax
- popad
-
- ;
- ; Set stack top pointer
- ;
- mov esp, edx
-
- ;
- ; Push the hob list pointer
- ;
- push eax
-
- ;
- ; Save the value
- ; ECX: start of range
- ; EDX: end of range
- ;
- mov ebp, esp
- push ecx
- push edx
-
- ;
- ; Push processor count to stack first, then BIST status (AP then BSP)
- ;
- mov eax, 1
- cpuid
- shr ebx, 16
- and ebx, 0000000FFh
- cmp bl, 1
- jae PushProcessorCount
-
- ;
- ; Some processors report 0 logical processors. Effectively 0 = 1.
- ; So we fix up the processor count
- ;
- inc ebx
-
-PushProcessorCount:
- push ebx
-
- ;
- ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
- ; for all processor threads
- ;
- xor ecx, ecx
- mov cl, bl
-PushBist:
- movd eax, mm0
- push eax
- loop PushBist
-
- ; Save Time-Stamp Counter
- movd eax, mm5
- push eax
-
- movd eax, mm6
- push eax
-
- ;
- ; Pass entry point of the PEI core
- ;
- mov edi, 0FFFFFFE0h
- push DWORD PTR ds:[edi]
-
- ;
- ; Pass BFV into the PEI Core
- ;
- mov edi, 0FFFFFFFCh
- push DWORD PTR ds:[edi]
-
- ;
- ; Pass stack size into the PEI Core
- ;
- mov ecx, [ebp - 4]
- mov edx, [ebp - 8]
- push ecx ; RamBase
-
- sub edx, ecx
- push edx ; RamSize
-
- ;
- ; Pass Control into the PEI Core
- ;
- call SecStartup
-CallPeiCoreEntryPoint ENDP
-
-END
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/SecEntry.asm b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/SecEntry.asm
deleted file mode 100644
index b7026c433f..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/SecEntry.asm
+++ /dev/null
@@ -1,338 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-; Module Name:
-;
-; SecEntry.asm
-;
-; Abstract:
-;
-; This is the code that goes from real-mode to protected mode.
-; It consumes the reset vector, calls two basic APIs from FSP binary.
-;
-;------------------------------------------------------------------------------
- INCLUDE Fsp.inc
-
-.686p
-.xmm
-.model small, c
-
-EXTRN CallPeiCoreEntryPoint:NEAR
-EXTRN TempRamInitParams:FAR
-
-; Pcds
-EXTRN PcdGet32 (PcdFlashFvFspBase):DWORD
-EXTRN PcdGet32 (PcdFlashFvFspSize):DWORD
-
-_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'
- ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE
-
-;----------------------------------------------------------------------------
-;
-; Procedure: _ModuleEntryPoint
-;
-; Input: None
-;
-; Output: None
-;
-; Destroys: Assume all registers
-;
-; Description:
-;
-; Transition to non-paged flat-model protected mode from a
-; hard-coded GDT that provides exactly two descriptors.
-; This is a bare bones transition to protected mode only
-; used for a while in PEI and possibly DXE.
-;
-; After enabling protected mode, a far jump is executed to
-; transfer to PEI using the newly loaded GDT.
-;
-; Return: None
-;
-; MMX Usage:
-; MM0 = BIST State
-; MM5 = Save time-stamp counter value high32bit
-; MM6 = Save time-stamp counter value low32bit.
-;
-;----------------------------------------------------------------------------
-
-align 4
-_ModuleEntryPoint PROC NEAR C PUBLIC
- fninit ; clear any pending Floating point exceptions
- ;
- ; Store the BIST value in mm0
- ;
- movd mm0, eax
-
- ;
- ; Save time-stamp counter value
- ; rdtsc load 64bit time-stamp counter to EDX:EAX
- ;
- rdtsc
- movd mm5, edx
- movd mm6, eax
-
- ;
- ; Load the GDT table in GdtDesc
- ;
- mov esi, OFFSET GdtDesc
- DB 66h
- lgdt fword ptr cs:[si]
-
- ;
- ; Transition to 16 bit protected mode
- ;
- mov eax, cr0 ; Get control register 0
- or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
- mov cr0, eax ; Activate protected mode
-
- mov eax, cr4 ; Get control register 4
- or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
- mov cr4, eax
-
- ;
- ; Now we're in 16 bit protected mode
- ; Set up the selectors for 32 bit protected mode entry
- ;
- mov ax, SYS_DATA_SEL
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-
- ;
- ; Transition to Flat 32 bit protected mode
- ; The jump to a far pointer causes the transition to 32 bit mode
- ;
- mov esi, offset ProtectedModeEntryLinearAddress
- jmp fword ptr cs:[si]
-
-_ModuleEntryPoint ENDP
-_TEXT_REALMODE ENDS
-
-_TEXT_PROTECTED_MODE SEGMENT PARA PUBLIC USE32 'CODE'
- ASSUME CS:_TEXT_PROTECTED_MODE, DS:_TEXT_PROTECTED_MODE
-
-;----------------------------------------------------------------------------
-;
-; Procedure: ProtectedModeEntryPoint
-;
-; Input: None
-;
-; Output: None
-;
-; Destroys: Assume all registers
-;
-; Description:
-;
-; This function handles:
-; Call two basic APIs from FSP binary
-; Initializes stack with some early data (BIST, PEI entry, etc)
-;
-; Return: None
-;
-;----------------------------------------------------------------------------
-
-align 4
-ProtectedModeEntryPoint PROC NEAR PUBLIC
-
- ; Find the fsp info header
- mov edi, PcdGet32 (PcdFlashFvFspBase)
- mov ecx, PcdGet32 (PcdFlashFvFspSize)
-
- mov eax, dword ptr [edi + FVH_SIGINATURE_OFFSET]
- cmp eax, FVH_SIGINATURE_VALID_VALUE
- jnz FspHeaderNotFound
-
- xor eax, eax
- mov ax, word ptr [edi + FVH_EXTHEADER_OFFSET_OFFSET]
- cmp ax, 0
- jnz FspFvExtHeaderExist
-
- xor eax, eax
- mov ax, word ptr [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
- add edi, eax
- jmp FspCheckFfsHeader
-
-FspFvExtHeaderExist:
- add edi, eax
- mov eax, dword ptr [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
- add edi, eax
-
- ; Round up to 8 byte alignment
- mov eax, edi
- and al, 07h
- jz FspCheckFfsHeader
-
- and edi, 0FFFFFFF8h
- add edi, 08h
-
-FspCheckFfsHeader:
- ; Check the ffs guid
- mov eax, dword ptr [edi]
- cmp eax, FSP_HEADER_GUID_DWORD1
- jnz FspHeaderNotFound
-
- mov eax, dword ptr [edi + 4]
- cmp eax, FSP_HEADER_GUID_DWORD2
- jnz FspHeaderNotFound
-
- mov eax, dword ptr [edi + 8]
- cmp eax, FSP_HEADER_GUID_DWORD3
- jnz FspHeaderNotFound
-
- mov eax, dword ptr [edi + 0Ch]
- cmp eax, FSP_HEADER_GUID_DWORD4
- jnz FspHeaderNotFound
-
- add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
-
- ; Check the section type as raw section
- mov al, byte ptr [edi + SECTION_HEADER_TYPE_OFFSET]
- cmp al, 019h
- jnz FspHeaderNotFound
-
- add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
- jmp FspHeaderFound
-
-FspHeaderNotFound:
- jmp $
-
-FspHeaderFound:
- ; Get the fsp TempRamInit Api address
- mov eax, dword ptr [edi + FSP_HEADER_IMAGEBASE_OFFSET]
- add eax, dword ptr [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
-
- ; Setup the hardcode stack
- mov esp, OFFSET TempRamInitStack
-
- ; Call the fsp TempRamInit Api
- jmp eax
-
-TempRamInitDone:
- cmp eax, 0
- jnz FspApiFailed
-
- ; ECX: start of range
- ; EDX: end of range
- mov esp, edx
- push edx
- push ecx
- push eax ; zero - no hob list yet
- call CallPeiCoreEntryPoint
-
-FspApiFailed:
- jmp $
-
-align 10h
-TempRamInitStack:
- DD OFFSET TempRamInitDone
- DD OFFSET TempRamInitParams
-
-ProtectedModeEntryPoint ENDP
-
-;
-; ROM-based Global-Descriptor Table for the Tiano PEI Phase
-;
-align 16
-PUBLIC BootGdtTable
-
-;
-; GDT[0]: 0x00: Null entry, never used.
-;
-NULL_SEL EQU $ - GDT_BASE ; Selector [0]
-GDT_BASE:
-BootGdtTable DD 0
- DD 0
-;
-; Linear data segment descriptor
-;
-LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 092h ; present, ring 0, data, expand-up, writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; Linear code segment descriptor
-;
-LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 09Bh ; present, ring 0, data, expand-up, not-writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; System data segment descriptor
-;
-SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 093h ; present, ring 0, data, expand-up, not-writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-
-;
-; System code segment descriptor
-;
-SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 09Ah ; present, ring 0, data, expand-up, writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; Spare segment descriptor
-;
-SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0Eh ; Changed from F000 to E000.
- DB 09Bh ; present, ring 0, code, expand-up, writable
- DB 00h ; byte-granular, 16-bit
- DB 0
-;
-; Spare segment descriptor
-;
-SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
- DW 0FFFFh ; limit 0xFFFF
- DW 0 ; base 0
- DB 0
- DB 093h ; present, ring 0, data, expand-up, not-writable
- DB 00h ; byte-granular, 16-bit
- DB 0
-
-;
-; Spare segment descriptor
-;
-SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
- DW 0 ; limit 0
- DW 0 ; base 0
- DB 0
- DB 0 ; present, ring 0, data, expand-up, writable
- DB 0 ; page-granular, 32-bit
- DB 0
-GDT_SIZE EQU $ - BootGdtTable ; Size, in bytes
-
-;
-; GDT Descriptor
-;
-GdtDesc: ; GDT descriptor
- DW GDT_SIZE - 1 ; GDT limit
- DD OFFSET BootGdtTable ; GDT base address
-
-
-ProtectedModeEntryLinearAddress LABEL FWORD
-ProtectedModeEntryLinearOffset LABEL DWORD
- DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code
- DW LINEAR_CODE_SEL
-
-_TEXT_PROTECTED_MODE ENDS
-END
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.S b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.S
deleted file mode 100644
index 9bd29ce0f4..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.S
+++ /dev/null
@@ -1,71 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-# Abstract:
-#
-# Switch the stack from temporary memory to permenent memory.
-#
-#------------------------------------------------------------------------------
-
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# SecSwitchStack (
-# UINT32 TemporaryMemoryBase,
-# UINT32 PermenentMemoryBase
-# )#
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX (SecSwitchStack)
-ASM_PFX(SecSwitchStack):
- #
- # Save standard registers so they can be used to change stack
- #
- pushl %eax
- pushl %ebx
- pushl %ecx
- pushl %edx
-
- #
- # !!CAUTION!! this function address's is pushed into stack after
- # migration of whole temporary memory, so need save it to permenent
- # memory at first!
- #
- movl 20(%esp), %ebx # Save the first parameter
- movl 24(%esp), %ecx # Save the second parameter
-
- #
- # Save this function's return address into permenent memory at first.
- # Then, Fixup the esp point to permenent memory
- #
- movl %esp, %eax
- subl %ebx, %eax
- addl %ecx, %eax
- movl 0(%esp), %edx # copy pushed register's value to permenent memory
- movl %edx, 0(%eax)
- movl 4(%esp), %edx
- movl %edx, 4(%eax)
- movl 8(%esp), %edx
- movl %edx, 8(%eax)
- movl 12(%esp), %edx
- movl %edx, 12(%eax)
- movl 16(%esp), %edx # Update this function's return address into permenent memory
- movl %edx, 16(%eax)
- movl %eax, %esp # From now, esp is pointed to permenent memory
-
- #
- # Fixup the ebp point to permenent memory
- #
- movl %ebp, %eax
- subl %ebx, %eax
- addl %ecx, %eax
- movl %eax, %ebp # From now, ebp is pointed to permenent memory
-
- popl %edx
- popl %ecx
- popl %ebx
- popl %eax
- ret
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.asm b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.asm
deleted file mode 100644
index 95e56cec9b..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.asm
+++ /dev/null
@@ -1,76 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-; Abstract:
-;
-; Switch the stack from temporary memory to permenent memory.
-;
-;------------------------------------------------------------------------------
-
- .586p
- .model flat,C
- .code
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; SecSwitchStack (
-; UINT32 TemporaryMemoryBase,
-; UINT32 PermenentMemoryBase
-; );
-;------------------------------------------------------------------------------
-SecSwitchStack PROC
- ;
- ; Save three register: eax, ebx, ecx
- ;
- push eax
- push ebx
- push ecx
- push edx
-
- ;
- ; !!CAUTION!! this function address's is pushed into stack after
- ; migration of whole temporary memory, so need save it to permenent
- ; memory at first!
- ;
-
- mov ebx, [esp + 20] ; Save the first parameter
- mov ecx, [esp + 24] ; Save the second parameter
-
- ;
- ; Save this function's return address into permenent memory at first.
- ; Then, Fixup the esp point to permenent memory
- ;
- mov eax, esp
- sub eax, ebx
- add eax, ecx
- mov edx, dword ptr [esp] ; copy pushed register's value to permenent memory
- mov dword ptr [eax], edx
- mov edx, dword ptr [esp + 4]
- mov dword ptr [eax + 4], edx
- mov edx, dword ptr [esp + 8]
- mov dword ptr [eax + 8], edx
- mov edx, dword ptr [esp + 12]
- mov dword ptr [eax + 12], edx
- mov edx, dword ptr [esp + 16] ; Update this function's return address into permenent memory
- mov dword ptr [eax + 16], edx
- mov esp, eax ; From now, esp is pointed to permenent memory
-
- ;
- ; Fixup the ebp point to permenent memory
- ;
- mov eax, ebp
- sub eax, ebx
- add eax, ecx
- mov ebp, eax ; From now, ebp is pointed to permenent memory
-
- pop edx
- pop ecx
- pop ebx
- pop eax
- ret
-SecSwitchStack ENDP
-
- END
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/PlatformInit.c b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/PlatformInit.c
deleted file mode 100644
index d4e1c2a425..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/PlatformInit.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/** @file
- This PEIM will parse the hoblist from fsp and report them into pei core.
- This file contains the main entrypoint of the PEIM.
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-#include <PiPei.h>
-#include <Library/DebugLib.h>
-#include <Library/SerialPortLib.h>
-
-VOID EnableInternalUart ();
-
-VOID
-EFIAPI
-PlatformInit (
- IN VOID *FspHobList,
- IN VOID *StartOfRange,
- IN VOID *EndOfRange
- )
-{
- //
- // Platform initialization
- // Enable Serial port here
- //
- EnableInternalUart ();
- SerialPortInitialize ();
-
- DEBUG ((DEBUG_INFO, "PlatformInit\n"));
- DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
- DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));
- DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SaveSecContext.c b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SaveSecContext.c
deleted file mode 100644
index 382e617b27..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SaveSecContext.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/** @file
- This PEIM will parse the hoblist from fsp and report them into pei core.
- This file contains the main entrypoint of the PEIM.
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-#include <PiPei.h>
-#include <Library/DebugLib.h>
-
-#include <Ppi/TopOfTemporaryRam.h>
-#include <Ppi/SecPlatformInformation.h>
-
-/**
- Save BIST value before call FspInit.
-
- @param Bist BIST value.
-**/
-VOID
-AsmSaveBistValue (
- IN UINT32 Bist
- );
-
-/**
- Save Ticker value before call FspInit.
-
- @param Ticker Ticker value.
-**/
-VOID
-AsmSaveTickerValue (
- IN UINT64 Ticker
- );
-
-/**
- Save SEC context before call FspInit.
-
- @param PeiServices Pointer to PEI Services Table.
-**/
-VOID
-EFIAPI
-SaveSecContext (
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- UINT32 *Bist;
- UINT64 *Ticker;
- UINT32 Size;
- UINT32 Count;
- UINT32 TopOfTemporaryRam;
- VOID *TopOfTemporaryRamPpi;
- EFI_STATUS Status;
-
- DEBUG ((DEBUG_INFO, "SaveSecContext - 0x%x\n", PeiServices));
-
- Status = (*PeiServices)->LocatePpi (
- PeiServices,
- &gTopOfTemporaryRamPpiGuid,
- 0,
- NULL,
- (VOID **) &TopOfTemporaryRamPpi
- );
- if (EFI_ERROR (Status)) {
- return ;
- }
-
- DEBUG ((DEBUG_INFO, "TopOfTemporaryRamPpi - 0x%x\n", TopOfTemporaryRamPpi));
-
- //
- // The entries of BIST information, together with the number of them,
- // reside in the bottom of stack, left untouched by normal stack operation.
- // This routine copies the BIST information to the buffer pointed by
- // PlatformInformationRecord for output.
- //
- // |--------------| <- TopOfTemporaryRam
- // |Number of BSPs|
- // |--------------|
- // | BIST |
- // |--------------|
- // | .... |
- // |--------------|
- // | TSC[63:32] |
- // |--------------|
- // | TSC[31:00] |
- // |--------------|
- //
-
- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);
- TopOfTemporaryRam -= sizeof(UINT32) * 2;
- DEBUG ((DEBUG_INFO, "TopOfTemporaryRam - 0x%x\n", TopOfTemporaryRam));
- Count = *(UINT32 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32));
- DEBUG ((DEBUG_INFO, "Count - 0x%x\n", Count));
- Size = Count * sizeof (IA32_HANDOFF_STATUS);
- DEBUG ((DEBUG_INFO, "Size - 0x%x\n", Size));
-
- Bist = (UINT32 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32) - Size);
- DEBUG ((DEBUG_INFO, "Bist - 0x%x\n", *Bist));
- Ticker = (UINT64 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32) - Size - sizeof(UINT64));
- DEBUG ((DEBUG_INFO, "Ticker - 0x%lx\n", *Ticker));
-
- //
- // Just need record BSP
- //
- AsmSaveBistValue (*Bist);
- AsmSaveTickerValue (*Ticker);
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecGetPerformance.c b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecGetPerformance.c
deleted file mode 100644
index c5c22a29c2..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecGetPerformance.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/** @file
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPerformance.h>
-#include <Ppi/TopOfTemporaryRam.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/TimerLib.h>
-#include <Library/DebugLib.h>
-
-/**
- This interface conveys performance information out of the Security (SEC) phase into PEI.
-
- This service is published by the SEC phase. The SEC phase handoff has an optional
- EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
- PEI Foundation. As such, if the platform supports collecting performance data in SEC,
- this information is encapsulated into the data structure abstracted by this service.
- This information is collected for the boot-strap processor (BSP) on IA-32.
-
- @param[in] PeiServices The pointer to the PEI Services Table.
- @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
- @param[out] Performance The pointer to performance data collected in SEC phase.
-
- @retval EFI_SUCCESS The data was successfully returned.
-
-**/
-EFI_STATUS
-EFIAPI
-SecGetPerformance (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN PEI_SEC_PERFORMANCE_PPI *This,
- OUT FIRMWARE_SEC_PERFORMANCE *Performance
- )
-{
- UINT32 Size;
- UINT32 Count;
- UINT32 TopOfTemporaryRam;
- UINT64 Ticker;
- VOID *TopOfTemporaryRamPpi;
- EFI_STATUS Status;
-
- DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));
-
- Status = (*PeiServices)->LocatePpi (
- PeiServices,
- &gTopOfTemporaryRamPpiGuid,
- 0,
- NULL,
- (VOID **) &TopOfTemporaryRamPpi
- );
- if (EFI_ERROR (Status)) {
- return EFI_NOT_FOUND;
- }
-
- //
- // |--------------| <- TopOfTemporaryRam
- // |Number of BSPs|
- // |--------------|
- // | BIST |
- // |--------------|
- // | .... |
- // |--------------|
- // | TSC[63:32] |
- // |--------------|
- // | TSC[31:00] |
- // |--------------|
- //
- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);
- TopOfTemporaryRam -= sizeof(UINT32) * 2;
- Count = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32));
- Size = Count * sizeof (UINT64);
-
- Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);
- Performance->ResetEnd = GetTimeInNanoSecond (Ticker);
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecPlatformInformation.c b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecPlatformInformation.c
deleted file mode 100644
index a1ba35d47d..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecPlatformInformation.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/** @file
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPlatformInformation.h>
-#include <Ppi/TopOfTemporaryRam.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-
-/**
- This interface conveys state information out of the Security (SEC) phase into PEI.
-
- @param PeiServices Pointer to the PEI Services Table.
- @param StructureSize Pointer to the variable describing size of the input buffer.
- @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
-
-**/
-EFI_STATUS
-EFIAPI
-SecPlatformInformation (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
- )
-{
- UINT32 *Bist;
- UINT32 Size;
- UINT32 Count;
- UINT32 TopOfTemporaryRam;
- VOID *TopOfTemporaryRamPpi;
- EFI_STATUS Status;
-
- DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));
-
- Status = (*PeiServices)->LocatePpi (
- PeiServices,
- &gTopOfTemporaryRamPpiGuid,
- 0,
- NULL,
- (VOID **) &TopOfTemporaryRamPpi
- );
- if (EFI_ERROR (Status)) {
- return EFI_NOT_FOUND;
- }
-
- //
- // The entries of BIST information, together with the number of them,
- // reside in the bottom of stack, left untouched by normal stack operation.
- // This routine copies the BIST information to the buffer pointed by
- // PlatformInformationRecord for output.
- //
- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);
- TopOfTemporaryRam -= sizeof(UINT32) * 2;
- Count = *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));
- Size = Count * sizeof (IA32_HANDOFF_STATUS);
-
- if ((*StructureSize) < (UINT64) Size) {
- *StructureSize = Size;
- return EFI_BUFFER_TOO_SMALL;
- }
-
- *StructureSize = Size;
- Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size);
-
- CopyMem (PlatformInformationRecord, Bist, Size);
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecRamInitData.c b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecRamInitData.c
deleted file mode 100644
index 33734e3111..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecRamInitData.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/** @file
- Calling Fsp Apis in SEC
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Library/PcdLib.h>
-
-GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 TempRamInitParams[4] = {
- ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (PcdFlashMicroCodeOffset)),
- ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32 (PcdFlashMicroCodeOffset)),
- FixedPcdGet32 (PcdFlashCodeCacheAddress),
- FixedPcdGet32 (PcdFlashCodeCacheSize)
-};
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecTempRamSupport.c b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecTempRamSupport.c
deleted file mode 100644
index 8dd1367980..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecTempRamSupport.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/** @file
- C functions in SEC
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/TemporaryRamSupport.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugAgentLib.h>
-
-/**
- Switch the stack in the temporary memory to the one in the permanent memory.
-
- This function must be invoked after the memory migration immediately. The relative
- position of the stack in the temporary and permanent memory is same.
-
- @param TemporaryMemoryBase Base address of the temporary memory.
- @param PermenentMemoryBase Base address of the permanent memory.
-**/
-VOID
-EFIAPI
-SecSwitchStack (
- UINT32 TemporaryMemoryBase,
- UINT32 PermenentMemoryBase
- );
-
-/**
- This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into
- permanent memory.
-
- @param PeiServices Pointer to the PEI Services Table.
- @param TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the
- Temporary RAM contents.
- @param PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the
- Temporary RAM contents.
- @param CopySize Amount of memory to migrate from temporary to permanent memory.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when
- TemporaryMemoryBase > PermanentMemoryBase.
-
-**/
-EFI_STATUS
-EFIAPI
-SecTemporaryRamSupport (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
- IN UINTN CopySize
- )
-{
- IA32_DESCRIPTOR IdtDescriptor;
- VOID* OldHeap;
- VOID* NewHeap;
- VOID* OldStack;
- VOID* NewStack;
- DEBUG_AGENT_CONTEXT_POSTMEM_SEC DebugAgentContext;
- BOOLEAN OldStatus;
- UINTN PeiStackSize;
-
- PeiStackSize = (UINTN)PcdGet32 (PcdPeiTemporaryRamStackSize);
- if (PeiStackSize == 0) {
- PeiStackSize = (CopySize >> 1);
- }
-
- ASSERT (PeiStackSize < CopySize);
-
- //
- // |-------------------|---->
- // | Stack | PeiStackSize
- // |-------------------|---->
- // | Heap | PeiTemporayRamSize
- // |-------------------|----> TempRamBase
- //
- // |-------------------|---->
- // | Heap | PeiTemporayRamSize
- // |-------------------|---->
- // | Stack | PeiStackSize
- // |-------------------|----> PermanentMemoryBase
- //
-
- OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
- NewHeap = (VOID*)((UINTN)PermanentMemoryBase + PeiStackSize);
-
- OldStack = (VOID*)((UINTN)TemporaryMemoryBase + CopySize - PeiStackSize);
- NewStack = (VOID*)(UINTN)PermanentMemoryBase;
-
- DebugAgentContext.HeapMigrateOffset = (UINTN)NewHeap - (UINTN)OldHeap;
- DebugAgentContext.StackMigrateOffset = (UINTN)NewStack - (UINTN)OldStack;
-
- OldStatus = SaveAndSetDebugTimerInterrupt (FALSE);
-
- //
- // Initialize Debug Agent to support source level debug in PEI phase after memory ready.
- // It will build HOB and fix up the pointer in IDT table.
- //
- InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, (VOID *) &DebugAgentContext, NULL);
-
- //
- // Migrate Heap
- //
- CopyMem (NewHeap, OldHeap, CopySize - PeiStackSize);
-
- //
- // Migrate Stack
- //
- CopyMem (NewStack, OldStack, PeiStackSize);
-
-
- //
- // We need *not* fix the return address because currently,
- // The PeiCore is executed in flash.
- //
-
- //
- // Rebase IDT table in permanent memory
- //
- AsmReadIdtr (&IdtDescriptor);
- IdtDescriptor.Base = IdtDescriptor.Base - (UINTN)OldStack + (UINTN)NewStack;
-
- AsmWriteIdtr (&IdtDescriptor);
-
-
- //
- // Program MTRR
- //
-
- //
- // SecSwitchStack function must be invoked after the memory migration
- // immediately, also we need fixup the stack change caused by new call into
- // permanent memory.
- //
- SecSwitchStack (
- (UINT32) (UINTN) OldStack,
- (UINT32) (UINTN) NewStack
- );
-
- SaveAndSetDebugTimerInterrupt (OldStatus);
-
- return EFI_SUCCESS;
-}
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/UartInit.c b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/UartInit.c
deleted file mode 100644
index 2a9ab17120..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/UartInit.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/** @file
- This PEIM will parse the hoblist from fsp and report them into pei core.
- This file contains the main entrypoint of the PEIM.
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-#include <PiPei.h>
-#include <Library/IoLib.h>
-#include <Library/SerialPortLib.h>
-
-#define PCI_IDX 0xCF8
-#define PCI_DAT 0xCFC
-
-#define PCI_LPC_BASE (0x8000F800)
-#define PCI_LPC_REG(x) (PCI_LPC_BASE + (x))
-
-#define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address
-#define R_PCH_LPC_PMC_BASE 0x44 // PBASE, 32bit, 512 Bytes
-#define B_PCH_LPC_PMC_BASE_EN BIT1 // Enable Bit
-#define R_PCH_PMC_GEN_PMCON_1 0x20 // General PM Configuration 1
-#define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR BIT14 // SUS Well Power Failure
-#define B_PCH_PMC_GEN_PMCON_PWROK_FLR BIT16 // PWROK Failure
-
-#define R_PCH_LPC_UART_CTRL 0x80 // UART Control
-#define B_PCH_LPC_UART_CTRL_COM1_EN BIT0 // COM1 Enable
-
-#define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base Address
-#define R_PCH_ILB_IRQE 0x88 // IRQ Enable Control
-
-#define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address
-
-#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable
-#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4 BIT4 // UART IRQ4 Enable
-#define PCIEX_BASE_ADDRESS 0xE0000000
-#define PCI_EXPRESS_BASE_ADDRESS PCIEX_BASE_ADDRESS
-#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)
-#define SB_RCBA 0xfed1c000
-
-typedef enum {
- PchA0 = 0,
- PchA1 = 1,
- PchB0 = 2,
- PchB1 = 3,
- PchB2 = 4,
- PchB3 = 5,
- PchC0 = 6,
- PchSteppingMax
-} PCH_STEPPING;
-
-#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
- ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
- (UINTN)(Bus << 20) + \
- (UINTN)(Device << 15) + \
- (UINTN)(Function << 12) + \
- (UINTN)(Register) \
- )
-
-#define DEFAULT_PCI_BUS_NUMBER_PCH 0
-#define PCI_DEVICE_NUMBER_PCH_LPC 31
-#define PCI_FUNCTION_NUMBER_PCH_LPC 0
-
-#define R_PCH_LPC_RID_CC 0x08 // Revision ID & Class Code
-
-#define V_PCH_LPC_RID_0 0x01 // A0 Stepping (17 x 17)
-#define V_PCH_LPC_RID_1 0x02 // A0 Stepping (25 x 27)
-#define V_PCH_LPC_RID_2 0x03 // A1 Stepping (17 x 17)
-#define V_PCH_LPC_RID_3 0x04 // A1 Stepping (25 x 27)
-#define V_PCH_LPC_RID_4 0x05 // B0 Stepping (17 x 17)
-#define V_PCH_LPC_RID_5 0x06 // B0 Stepping (25 x 27)
-#define V_PCH_LPC_RID_6 0x07 // B1 Stepping (17 x 17)
-#define V_PCH_LPC_RID_7 0x08 // B1 Stepping (25 x 27)
-#define V_PCH_LPC_RID_8 0x09 // B2 Stepping (17 x 17)
-#define V_PCH_LPC_RID_9 0x0A // B2 Stepping (25 x 27)
-#define V_PCH_LPC_RID_A 0x0B // B3 Stepping (17 x 17)
-#define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27)
-#define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17)
-#define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27)
-
-/**
- Return Pch stepping type
-
- @param[in] None
-
- @retval PCH_STEPPING Pch stepping type
-
-**/
-PCH_STEPPING
-EFIAPI
-PchStepping (
- VOID
- )
-{
- UINT8 RevId;
-
- RevId = MmioRead8 (
- MmPciAddress (0,
- DEFAULT_PCI_BUS_NUMBER_PCH,
- PCI_DEVICE_NUMBER_PCH_LPC,
- PCI_FUNCTION_NUMBER_PCH_LPC,
- R_PCH_LPC_RID_CC)
- );
-
- switch (RevId) {
- case V_PCH_LPC_RID_0:
- case V_PCH_LPC_RID_1:
- return PchA0;
- break;
-
- case V_PCH_LPC_RID_2:
- case V_PCH_LPC_RID_3:
- return PchA1;
- break;
-
- case V_PCH_LPC_RID_4:
- case V_PCH_LPC_RID_5:
- return PchB0;
- break;
-
- case V_PCH_LPC_RID_6:
- case V_PCH_LPC_RID_7:
- return PchB1;
- break;
-
- case V_PCH_LPC_RID_8:
- case V_PCH_LPC_RID_9:
- return PchB2;
- break;
-
- case V_PCH_LPC_RID_A:
- case V_PCH_LPC_RID_B:
- return PchB3;
- break;
-
- case V_PCH_LPC_RID_C:
- case V_PCH_LPC_RID_D:
- return PchC0;
- break;
-
- default:
- return PchSteppingMax;
- break;
-
- }
-}
-
-/**
- Enable legacy decoding on ICH6
-
- @param[in] none
-
- @retval EFI_SUCCESS Always returns success.
-
-**/
-VOID
-EnableInternalUart(
- VOID
- )
-{
-
- //
- // Program and enable PMC Base.
- //
- IoWrite32 (PCI_IDX, PCI_LPC_REG(R_PCH_LPC_PMC_BASE));
- IoWrite32 (PCI_DAT, (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));
-
- //
- // Enable COM1 for debug message output.
- //
- MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);
-
- //
- // Silicon Steppings
- //
- if (PchStepping()>= PchB0)
- MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ4);
- else
- MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);
- MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));
- MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L
- MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));
- MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L
- MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN);
-
- SerialPortInitialize ();
- SerialPortWrite ((UINT8 *)"EnableInternalUart!\r\n", sizeof("EnableInternalUart!\r\n") - 1);
-
- return ;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h
deleted file mode 100644
index 415e53daf2..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*++
-
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-
-Module Name:
-
- Tpm.h
-
-Abstract:
-
-
---*/
-
-#ifndef __EFI_TPM_MP_DRIVER_PROTOCOL_H__
-#define __EFI_TPM_MP_DRIVER_PROTOCOL_H__
-
-
-#define EFI_TPM_MP_DRIVER_PROTOCOL_GUID \
- { 0xde161cfe, 0x1e60, 0x42a1, 0x8c, 0xc3, 0xee, 0x7e, 0xf0, 0x73, 0x52, 0x12 }
-
-
-EFI_FORWARD_DECLARATION (EFI_TPM_MP_DRIVER_PROTOCOL);
-
-#define TPM_DRIVER_STATUS 0
-#define TPM_DEVICE_STATUS 1
-
-#define TPM_DRIVER_OK 0
-#define TPM_DRIVER_FAILED 1
-#define TPM_DRIVER_NOT_OPENED 2
-#define TPM_DEVICE_OK 0
-#define TPM_DEVICE_UNRECOVERABLE 1
-#define TPM_DEVICE_RECOVERABLE 2
-#define TPM_DEVICE_NOT_FOUND 3
-
-//
-// Prototypes for the TPM MP Driver Protocol
-//
-
-/**
- This service Open the TPM interface
-
- @param[in] This A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL.
-
- @retval EFI_SUCCESS Operation completed successfully
- @retval EFI_DEVICE_ERROR The command was unsuccessful
- @retval EFI_NOT_FOUND The component was not running
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_TPM_MP_INIT) (
- IN EFI_TPM_MP_DRIVER_PROTOCOL *This
- );
-
-/**
- This service close the TPM interface and deactivate TPM
-
- @param[in] This A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL.
-
- @retval EFI_SUCCESS Operation completed successfully
- @retval EFI_DEVICE_ERROR The command was unsuccessful
- @retval EFI_NOT_FOUND The component was not running
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_TPM_MP_CLOSE) (
- IN EFI_TPM_MP_DRIVER_PROTOCOL *This
- );
-
-/**
- This service get the current status infomation of TPM
-
- @param[in] This A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL.
- @param[in] ReqStatusType Requested type of status information, driver or device.
- @param[in] Status Pointer to the returned status.
-
- @retval EFI_SUCCESS Operation completed successfully
- @retval EFI_DEVICE_ERROR The command was unsuccessful
- @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect
- @retval EFI_BUFFER_TOO_SMALL The receive buffer is too small
- @retval EFI_NOT_FOUND The component was not running
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_TPM_MP_GET_STATUS_INFO) (
- IN EFI_TPM_MP_DRIVER_PROTOCOL *This,
- IN UINT32 ReqStatusType,
- OUT UINT32 *Status
- );
-
-/**
- This service transmit data to the TPM and get response from TPM
-
- @param[in] This A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL.
- @param[in] TransmitBuf Pointer to a buffer containing TPM transmit data.
- @param[in] TransmitBufLen Sizeof TPM input buffer in bytes.
- @param[in] ReceiveBuf Pointer to a buffer containing TPM receive data.
- @param[in] ReceiveBufLen On input, size of TPM receive buffer in bytes.
- On output, number of bytes written.
-
- @retval EFI_SUCCESS Operation completed successfully
- @retval EFI_DEVICE_ERROR The command was unsuccessful
- @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect
- @retval EFI_BUFFER_TOO_SMALL The receive buffer is too small
- @retval EFI_NOT_FOUND The component was not running
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_TPM_MP_TRANSMIT) (
- IN EFI_TPM_MP_DRIVER_PROTOCOL *This,
- IN UINT8 *TransmitBuffer,
- IN UINT32 TransmitBufferLen,
- OUT UINT8 *ReceiveBuf,
- IN OUT UINT32 *ReceiveBufLen
- );
-
-
-
-typedef struct _EFI_TPM_MP_DRIVER_PROTOCOL {
- EFI_TPM_MP_INIT Init;
- EFI_TPM_MP_CLOSE Close;
- EFI_TPM_MP_GET_STATUS_INFO GetStatusInfo;
- EFI_TPM_MP_TRANSMIT Transmit;
-} EFI_TPM_MP_DRIVER_PROTOCOL;
-
-extern EFI_GUID gEfiTpmMpDriverProtocolGuid;
-
-#endif
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h
deleted file mode 100644
index 16e9f9c6bc..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*++
-
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-Module Name:
- UsbPolicy.h
-
-Abstract:
-
---*/
-
-#ifndef _USB_POLICY_H_
-#define _USB_POLICY_H_
-
-EFI_FORWARD_DECLARATION (EFI_USB_POLICY_PROTOCOL);
-
-#define USB_POLICY_GUID \
- {\
- 0xf617b358, 0x12cf, 0x414a, 0xa0, 0x69, 0x60, 0x67, 0x7b, 0xda, 0x13, 0xb4\
- }
-
-#define TIANO_CODE_BASE 0x00
-#define ICBD_CODE_BASE 0x01
-
-#define ATUO_TYPE 0x00
-#define USB_FDD_TYPE 0x01
-#define HDD_TYPE 0x02
-#define ZIP_TYPE 0x03
-#define CDROM_TYPE 0x04
-#define SIZE_TYPE 0x05
-
-#define ZIP_FDD 0x80
-
-#define FDD_EMULATION 0x00
-#define HDD_EMULATION 0x01
-
-#define HIGH_SPEED 0x00
-#define FULL_SPEED 0x01
-#define SUPER_SPEED 0x02
-
-#define LEGACY_KB_EN 0x01
-#define LEGACY_KB_DIS 0x00
-#define LEGACY_MS_EN 0x01
-#define LEGACY_MS_DIS 0x00
-#define LEGACY_USB_EN 0x00
-#define LEGACY_USB_DIS 0x01
-#define LEGACY_FREE_SUPP 0x01
-#define LEGACY_FREE_UN_SUPP 0x00
-#define LEGACY_PERIOD_SUPP 0x01
-#define LEGACY_PERIOD_UN_SUPP 0x00
-
-#define LEGACY_USB_TIME_TUE_ENABLE 0x01
-#define LEGACY_USB_TIME_TUE_DISABLE 0x00
-#define USB_HAVE_HUB_INTERNEL 0x01
-#define USB_NOT_HAVE_HUB_INTERNEL 0x00
-
-#define USB_POLICY_PROTOCOL_REVISION_1 1
-#define USB_POLICY_PROTOCOL_REVISION_2 2
-
-#ifndef __GNUC__
-#pragma warning ( disable : 4306 )
-#pragma warning ( disable : 4054 )
-#endif
-
-#define GET_USB_CFG (UsbCfg);\
- do{\
- UINT16 *pSegOfEbda;\
- UINT32 mToEbda;\
- pSegOfEbda = (UINT16 *)(UINTN)0x40E;\
- mToEbda = (UINT32)(((UINTN)(*pSegOfEbda) << 4) + 0x80);\
- UsbCfg = (USB_CFG *)(UINTN)mToEbda;\
- }while(0);
-
-#pragma pack(1)
-typedef struct {
- UINT8 HasUSBKeyboard:1;
- UINT8 HasUSBMouse:1;
- UINT8 LegacyFreeSupport:1;
- UINT8 UsbOperationMode:1;
- UINT8 LegacyKBEnable:1;
- UINT8 LegacyMSEnable:1;
- UINT8 USBPeriodSupport:1;
- UINT8 Reserved:1;
-} USB_DEVICE_INFOR;
-
-typedef struct {
- UINT8 Codebase;
- UINT8 USBHDDForceType;
- UINT8 Configurated;
- UINT8 LpcAcpiBase;
- UINT8 AcpiTimerReg;
- UINT8 Reserved1[0x01];
- UINT8 LegacyUsbEnable;
- USB_DEVICE_INFOR UsbDeviceInfor;
- UINT16 UsbEmulationSize;
- UINT8 Reserved2[0x06];
-} USB_CFG;
-#pragma pack()
-
-typedef struct _EFI_USB_POLICY_PROTOCOL{
- UINT8 Version;
- UINT8 UsbMassStorageEmulationType; // 1: FDD_Type; 2: HDD_Type; other:Auto_Type*
- UINT8 UsbOperationMode; // 0: High_Speed; 1: Full_Speed;
- UINT8 LegacyKBEnable; // 0: Disabled; 1: Enabled*
- UINT8 LegacyMSEnable; // 0: Disabled; 1: Enabled*
- UINT8 USBPeriodSupport; // 0; Unsupport; 1: Support
- UINT8 LegacyUsbEnable; // 1: Disabled; 0: Enabled*
- UINT8 LegacyFreeSupport; // 0: Unsupport; 1: Support
- UINT8 CodeBase;
- UINT8 LpcAcpiBase; // 40h(default)
- UINT8 AcpiTimerReg;
- UINT8 UsbTimeTue;
- UINT8 InternelHubExist; // 1: Host have internel hub on board; 0: No internel hub on board
- UINT8 EnumWaitPortStableStall; // Value for wait port stable when enum a new dev.
- UINT16 UsbEmulationSize; // Mbytes.
- UINT8 UsbZipEmulationType;
- UINT8 Reserved[3]; // Reserved fields for future expansion w/o protocol change
-} EFI_USB_POLICY_PROTOCOL;
-
-extern EFI_GUID gUsbPolicyGuid;
-
-#endif
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c
deleted file mode 100644
index 85f066a9e3..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*++
-
-Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-
-Module Name:
-
- I2CLib.c
-
-
-
---*/
-#ifdef ECP_FLAG
-#include "EdkIIGlueDxe.h"
-#else
-#include <Library/DebugLib.h>
-#include <Library/TimerLib.h>
-#endif
-#include <PchRegs/PchRegsPcu.h>
-#include <PchRegs.h>
-#include <PlatformBaseAddresses.h>
-#include <PchRegs/PchRegsLpss.h>
-#ifdef ECP_FLAG
-#include "I2CLib.h"
-#else
-#include <Library/I2CLib.h>
-#endif
-#include <Protocol/GlobalNvsArea.h>
-#ifndef ECP_FLAG
-#include <Library/UefiBootServicesTableLib.h>
-#endif
-
-EFI_STATUS ByteReadI2C(
- IN UINT8 BusNo,
- IN UINT8 SlaveAddress,
- IN UINT8 Offset,
- IN UINTN ReadBytes,
- OUT UINT8 *ReadBuffer
- )
-{
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
deleted file mode 100644
index d669a4eaf8..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
+++ /dev/null
@@ -1,39 +0,0 @@
-## @file
-# Null instance of Debug Agent Library with empty functions.
-#
-# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = I2CLib
- FILE_GUID = 7f62bf44-2ba7-4c2d-9d4a-91c8906ff053
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = I2CLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64 EBC
-#
-
-[Sources.common]
- I2CLib.c
-
-[LibraryClasses]
- BaseLib
- IoLib
- TimerLib
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- Vlv2TbltDevicePkg/PlatformPkg.dec
- Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
-
-[Protocols]
- gEfiGlobalNvsAreaProtocolGuid
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLib.c b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLib.c
deleted file mode 100644
index 104c2ded43..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLib.c
+++ /dev/null
@@ -1,735 +0,0 @@
-/** @file
- Functions for accessing I2C registers.
-
- Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
---*/
-
-#include <Library/DebugLib.h>
-#include <Library/TimerLib.h>
-#include <PchRegs/PchRegsPcu.h>
-#include <PchRegs.h>
-#include <PlatformBaseAddresses.h>
-#include <PchRegs/PchRegsLpss.h>
-#include <Library/I2CLib.h>
-#include <Protocol/GlobalNvsArea.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <I2CRegs.h>
-
-#define GLOBAL_NVS_OFFSET(Field) (UINTN)((CHAR8*)&((EFI_GLOBAL_NVS_AREA*)0)->Field - (CHAR8*)0)
-
-#define PCIEX_BASE_ADDRESS 0xE0000000
-#define PCI_EXPRESS_BASE_ADDRESS ((VOID *) (UINTN) PCIEX_BASE_ADDRESS)
-#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
- ((UINTN)PCI_EXPRESS_BASE_ADDRESS + \
- (UINTN)(Bus << 20) + \
- (UINTN)(Device << 15) + \
- (UINTN)(Function << 12) + \
- (UINTN)(Register) \
- )
-#define PCI_D31F0_REG_BASE PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)
-
-typedef struct _LPSS_PCI_DEVICE_INFO {
- UINTN Segment;
- UINTN BusNum;
- UINTN DeviceNum;
- UINTN FunctionNum;
- UINTN Bar0;
- UINTN Bar1;
-} LPSS_PCI_DEVICE_INFO;
-
-LPSS_PCI_DEVICE_INFO mLpssPciDeviceList[] = {
- {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1, PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC, 0xFE900000, 0xFE908000},
- {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0, 0xFE910000, 0xFE918000},
- {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1, 0xFE920000, 0xFE928000},
- {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2, 0xFE930000, 0xFE938000},
- {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3, 0xFE940000, 0xFE948000},
- {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4, 0xFE950000, 0xFE958000},
- {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5, 0xFE960000, 0xFE968000},
- {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6, 0xFE970000, 0xFE978000}
-};
-
-#define LPSS_PCI_DEVICE_NUMBER sizeof(mLpssPciDeviceList)/sizeof(LPSS_PCI_DEVICE_INFO)
-
-STATIC UINTN mI2CBaseAddress = 0;
-STATIC UINT16 mI2CSlaveAddress = 0;
-
-UINT16 mI2cMode=B_IC_RESTART_EN | B_IC_SLAVE_DISABLE | B_MASTER_MODE ;
-
-UINTN mI2cNvsBaseAddress[] = {
- GLOBAL_NVS_OFFSET(LDMA2Addr),
- GLOBAL_NVS_OFFSET(I2C1Addr),
- GLOBAL_NVS_OFFSET(I2C2Addr),
- GLOBAL_NVS_OFFSET(I2C3Addr),
- GLOBAL_NVS_OFFSET(I2C4Addr),
- GLOBAL_NVS_OFFSET(I2C5Addr),
- GLOBAL_NVS_OFFSET(I2C6Addr),
- GLOBAL_NVS_OFFSET(I2C7Addr)
- };
-
-/**
- This function get I2Cx controller base address (BAR0).
-
- @param I2cControllerIndex Bus Number of I2C controller.
-
- @return I2C BAR.
-**/
-UINTN
-GetI2cBarAddr(
- IN UINT8 I2cControllerIndex
- )
-{
- EFI_STATUS Status;
- EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
- UINTN AcpiBaseAddr;
- UINTN PciMmBase=0;
-
- ASSERT(gBS!=NULL);
-
- Status = gBS->LocateProtocol (
- &gEfiGlobalNvsAreaProtocolGuid,
- NULL,
- &GlobalNvsArea
- );
-
- //
- // PCI mode from PEI ( Global NVS is not ready).
- //
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_INFO, "GetI2cBarAddr() gEfiGlobalNvsAreaProtocolGuid:%r\n", Status));
- //
- // Global NVS is not ready.
- //
- return 0;
- }
-
- AcpiBaseAddr = *(UINTN*)((CHAR8*)GlobalNvsArea->Area + mI2cNvsBaseAddress[I2cControllerIndex + 1]);
-
- //
- //PCI mode from DXE (global NVS protocal) to LPSS OnReadytoBoot(swith to ACPI).
- //
- if(AcpiBaseAddr==0) {
- PciMmBase = MmPciAddress (
- mLpssPciDeviceList[I2cControllerIndex + 1].Segment,
- mLpssPciDeviceList[I2cControllerIndex + 1].BusNum,
- mLpssPciDeviceList[I2cControllerIndex + 1].DeviceNum,
- mLpssPciDeviceList[I2cControllerIndex + 1].FunctionNum,
- 0
- );
- DEBUG((EFI_D_ERROR, "\nGetI2cBarAddr() I2C Device %x %x %x PciMmBase:%x\n", \
- mLpssPciDeviceList[I2cControllerIndex + 1].BusNum, \
- mLpssPciDeviceList[I2cControllerIndex + 1].DeviceNum, \
- mLpssPciDeviceList[I2cControllerIndex + 1].FunctionNum, PciMmBase));
-
- if (MmioRead32 (PciMmBase) != 0xFFFFFFFF) {
- if((MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_STSCMD)& B_PCH_LPSS_I2C_STSCMD_MSE)) {
- //
- // Get the address allocted.
- //
- mLpssPciDeviceList[I2cControllerIndex + 1].Bar0=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR);
- mLpssPciDeviceList[I2cControllerIndex + 1].Bar1=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR1);
- }
- }
- AcpiBaseAddr =mLpssPciDeviceList[I2cControllerIndex+1].Bar0;
- }
-
- //
- // ACPI mode from BDS: LPSS OnReadytoBoot
- //
- else {
- DEBUG ((EFI_D_INFO, "GetI2cBarAddr() NVS Varialable is updated by this LIB or LPSS \n"));
- }
-
- DEBUG ((EFI_D_INFO, "GetI2cBarAddr() I2cControllerIndex+1 0x%x AcpiBaseAddr:0x%x \n", (I2cControllerIndex + 1), AcpiBaseAddr));
- return AcpiBaseAddr;
-}
-
-
-/**
- This function enables I2C controllers.
-
- @param I2cControllerIndex Bus Number of I2C controllers.
-
- @return Result of the I2C initialization.
-**/
-EFI_STATUS
-ProgramPciLpssI2C (
- IN UINT8 I2cControllerIndex
- )
-{
- UINT32 PmcBase;
- UINTN PciMmBase=0;
- EFI_STATUS Status;
- EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
-
- UINT32 PmcFunctionDsiable[]= {
- B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1,
- B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2,
- B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3,
- B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4,
- B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5,
- B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6,
- B_PCH_PMC_FUNC_DIS_LPSS2_FUNC7
- };
-
- DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() Start\n"));
-
- //
- // Set the VLV Function Disable Register to ZERO
- //
- PmcBase = MmioRead32 (PCI_D31F0_REG_BASE + R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR;
- if(MmioRead32(PmcBase+R_PCH_PMC_FUNC_DIS)&PmcFunctionDsiable[I2cControllerIndex]) {
- DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() End:I2C[%x] is disabled\n",I2cControllerIndex));
- return EFI_NOT_READY;
- }
-
- DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C()------------I2cControllerIndex=%x,PMC=%x\n",I2cControllerIndex,MmioRead32(PmcBase+R_PCH_PMC_FUNC_DIS)));
-
- {
- PciMmBase = MmPciAddress (
- mLpssPciDeviceList[I2cControllerIndex+1].Segment,
- mLpssPciDeviceList[I2cControllerIndex+1].BusNum,
- mLpssPciDeviceList[I2cControllerIndex+1].DeviceNum,
- mLpssPciDeviceList[I2cControllerIndex+1].FunctionNum,
- 0
- );
-
- DEBUG((EFI_D_ERROR, "Program Pci Lpss I2C Device %x %x %x PciMmBase:%x\n", \
- mLpssPciDeviceList[I2cControllerIndex+1].BusNum, \
- mLpssPciDeviceList[I2cControllerIndex+1].DeviceNum, \
- mLpssPciDeviceList[I2cControllerIndex+1].FunctionNum, PciMmBase));
-
- if (MmioRead32 (PciMmBase) != 0xFFFFFFFF) {
- if((MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_STSCMD)& B_PCH_LPSS_I2C_STSCMD_MSE)) {
- //
- // Get the address allocted.
- //
- mLpssPciDeviceList[I2cControllerIndex+1].Bar0=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR);
- mLpssPciDeviceList[I2cControllerIndex+1].Bar1=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR1);
- DEBUG((EFI_D_ERROR, "ProgramPciLpssI2C() bar0:0x%x bar1:0x%x\n",mLpssPciDeviceList[I2cControllerIndex+1].Bar0, mLpssPciDeviceList[I2cControllerIndex+1].Bar1));
- } else {
-
- //
- // Program BAR 0
- //
- ASSERT (((mLpssPciDeviceList[I2cControllerIndex+1].Bar0 & B_PCH_LPSS_I2C_BAR_BA) == mLpssPciDeviceList[I2cControllerIndex+1].Bar0) && (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 != 0));
- MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR), (UINT32) (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 & B_PCH_LPSS_I2C_BAR_BA));
-
- //
- // Program BAR 1
- //
- ASSERT (((mLpssPciDeviceList[I2cControllerIndex+1].Bar1 & B_PCH_LPSS_I2C_BAR1_BA) == mLpssPciDeviceList[I2cControllerIndex+1].Bar1) && (mLpssPciDeviceList[I2cControllerIndex+1].Bar1 != 0));
- MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR1), (UINT32) (mLpssPciDeviceList[I2cControllerIndex+1].Bar1 & B_PCH_LPSS_I2C_BAR1_BA));
-
- //
- // Bus Master Enable & Memory Space Enable
- //
- MmioOr32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_STSCMD), (UINT32) (B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE));
- ASSERT (MmioRead32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0) != 0xFFFFFFFF);
- }
-
- //
- // Release Resets
- //
- MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 + R_PCH_LPIO_I2C_MEM_RESETS,(B_PCH_LPIO_I2C_MEM_RESETS_FUNC | B_PCH_LPIO_I2C_MEM_RESETS_APB));
-
- //
- // Activate Clocks
- //
- MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 + R_PCH_LPSS_I2C_MEM_PCP,0x80020003);//No use for A0
-
- DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() Programmed()\n"));
- }
-
- //
- // BDS: already switched to ACPI mode
- //
- else {
- ASSERT(gBS!=NULL);
- Status = gBS->LocateProtocol (
- &gEfiGlobalNvsAreaProtocolGuid,
- NULL,
- &GlobalNvsArea
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_INFO, "GetI2cBarAddr() gEfiGlobalNvsAreaProtocolGuid:%r\n", Status));
- //
- // gEfiGlobalNvsAreaProtocolGuid is not ready.
- //
- return 0;
- }
- mLpssPciDeviceList[I2cControllerIndex + 1].Bar0 = *(UINTN*)((CHAR8*)GlobalNvsArea->Area + mI2cNvsBaseAddress[I2cControllerIndex + 1]);
- DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C(): is switched to ACPI 0x:%x \n",mLpssPciDeviceList[I2cControllerIndex + 1].Bar0));
- }
- }
-
- DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() End\n"));
-
- return EFI_SUCCESS;
-}
-
-/**
- Disable I2C Bus.
-
- @param VOID.
-
- @return Result of the I2C disabling.
-**/
-RETURN_STATUS
-I2cDisable (
- VOID
- )
-{
- //
- // 0.1 seconds
- //
- UINT32 NumTries = 10000;
-
- MmioWrite32 ( mI2CBaseAddress + R_IC_ENABLE, 0 );
- while ( 0 != ( MmioRead32 ( mI2CBaseAddress + R_IC_ENABLE_STATUS) & 1)) {
- MicroSecondDelay (10);
- NumTries --;
- if(0 == NumTries) {
- return RETURN_NOT_READY;
- }
- }
-
- return RETURN_SUCCESS;
-}
-
-/**
- Enable I2C Bus.
-
- @param VOID.
-
- @return Result of the I2C disabling.
-**/
-RETURN_STATUS
-I2cEnable (
- VOID
- )
-{
- //
- // 0.1 seconds
- //
- UINT32 NumTries = 10000;
-
- MmioWrite32 (mI2CBaseAddress + R_IC_ENABLE, 1);
-
- while (0 == (MmioRead32 (mI2CBaseAddress + R_IC_ENABLE_STATUS) & 1)) {
- MicroSecondDelay (10);
- NumTries --;
- if(0 == NumTries){
- return RETURN_NOT_READY;
- }
- }
-
- return RETURN_SUCCESS;
-}
-
-/**
- Enable I2C Bus.
-
- @param VOID.
-
- @return Result of the I2C enabling.
-**/
-RETURN_STATUS
-I2cBusFrequencySet (
- IN UINTN BusClockHertz
- )
-{
- DEBUG((EFI_D_INFO,"InputFreq BusClockHertz: %d\r\n",BusClockHertz));
-
- //
- // Set the 100 KHz clock divider according to SV result and I2C spec
- //
- MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_HCNT, (UINT16)0x214 );
- MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_LCNT, (UINT16)0x272 );
-
- //
- // Set the 400 KHz clock divider according to SV result and I2C spec
- //
- MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_HCNT, (UINT16)0x50 );
- MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_LCNT, (UINT16)0xAD );
-
- switch ( BusClockHertz ) {
- case 100 * 1000:
- MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x40);//100K
- mI2cMode = V_SPEED_STANDARD;
- break;
- case 400 * 1000:
- MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x32);//400K
- mI2cMode = V_SPEED_FAST;
- break;
- default:
- MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x09);//3.4M
- mI2cMode = V_SPEED_HIGH;
- }
-
- //
- // Select the frequency counter,
- // Enable restart condition,
- // Enable master FSM, disable slave FSM.
- //
- mI2cMode |= B_IC_RESTART_EN | B_IC_SLAVE_DISABLE | B_MASTER_MODE;
-
- return EFI_SUCCESS;
-}
-
-/**
- Initializes the host controller to execute I2C commands.
-
- @param I2cControllerIndex Index of I2C controller in LPSS device. 0 represents I2C0, which is PCI function 1 of LPSS device.
-
- @return EFI_SUCCESS Opcode initialization on the I2C host controller completed.
- @return EFI_DEVICE_ERROR Device error, operation failed.
-**/
-EFI_STATUS
-I2CInit (
- IN UINT8 I2cControllerIndex,
- IN UINT16 SlaveAddress
- )
-{
- EFI_STATUS Status=RETURN_SUCCESS;
- UINT32 NumTries = 0;
- UINTN GnvsI2cBarAddr=0;
-
- //
- // Verify the parameters
- //
- if ((1023 < SlaveAddress) || (6 < I2cControllerIndex)) {
- Status = RETURN_INVALID_PARAMETER;
- DEBUG((EFI_D_INFO,"I2CInit Exit with RETURN_INVALID_PARAMETER\r\n"));
- return Status;
- }
- MmioWrite32 ( mI2CBaseAddress + R_IC_TAR, (UINT16)SlaveAddress );
- mI2CSlaveAddress = SlaveAddress;
-
- //
- // 1.PEI: program and init ( before pci enumeration).
- // 2.DXE:update address and re-init ( after pci enumeration).
- // 3.BDS:update ACPI address and re-init ( after acpi mode is enabled).
- //
- if(mI2CBaseAddress == mLpssPciDeviceList[I2cControllerIndex + 1].Bar0) {
-
- //
- // I2CInit is already called.
- //
- GnvsI2cBarAddr=GetI2cBarAddr(I2cControllerIndex);
-
- if((GnvsI2cBarAddr == 0)||(GnvsI2cBarAddr == mI2CBaseAddress)) {
- DEBUG((EFI_D_INFO,"I2CInit Exit with mI2CBaseAddress:%x == [%x].Bar0\r\n",mI2CBaseAddress,I2cControllerIndex+1));
- return RETURN_SUCCESS;
- }
- }
-
- Status=ProgramPciLpssI2C(I2cControllerIndex);
- if(Status!=EFI_SUCCESS) {
- return Status;
- }
-
-
- mI2CBaseAddress = (UINT32) mLpssPciDeviceList[I2cControllerIndex + 1].Bar0;
- DEBUG ((EFI_D_ERROR, "mI2CBaseAddress = 0x%x \n",mI2CBaseAddress));
-
- //
- // 1 seconds.
- //
- NumTries = 10000;
- while ((1 == ( MmioRead32 ( mI2CBaseAddress + R_IC_STATUS) & STAT_MST_ACTIVITY ))) {
- MicroSecondDelay(10);
- NumTries --;
- if(0 == NumTries) {
- DEBUG((EFI_D_INFO, "Try timeout\r\n"));
- return RETURN_DEVICE_ERROR;
- }
- }
-
- Status = I2cDisable();
- DEBUG((EFI_D_INFO, "I2cDisable Status = %r\r\n", Status));
- I2cBusFrequencySet(400 * 1000);
-
- MmioWrite32(mI2CBaseAddress + R_IC_INTR_MASK, 0x0);
- if (0x7f < SlaveAddress )
- SlaveAddress = ( SlaveAddress & 0x3ff ) | IC_TAR_10BITADDR_MASTER;
- MmioWrite32 ( mI2CBaseAddress + R_IC_TAR, (UINT16)SlaveAddress );
- MmioWrite32 ( mI2CBaseAddress + R_IC_RX_TL, 0);
- MmioWrite32 ( mI2CBaseAddress + R_IC_TX_TL, 0 );
- MmioWrite32 ( mI2CBaseAddress + R_IC_CON, mI2cMode);
- Status = I2cEnable();
-
- DEBUG((EFI_D_INFO, "I2cEnable Status = %r\r\n", Status));
- MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT );
-
- return EFI_SUCCESS;
-}
-
-/**
- Reads a Byte from I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be read
- @param Offset Offset from which the data has to be read
- @param *Byte Address to which the value read has to be stored
- @param Start Whether a RESTART is issued before the byte is sent or received
- @param End Whether STOP is generated after a data byte is sent or received
-
- @return EFI_SUCCESS IF the byte value has been successfully read
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS
-ByteReadI2CBasic(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINTN ReadBytes,
- OUT UINT8 *ReadBuffer,
- IN UINT8 Start,
- IN UINT8 End
- )
-{
-
- EFI_STATUS Status;
- UINT32 I2cStatus;
- UINT16 ReceiveData;
- UINT8 *ReceiveDataEnd;
- UINT8 *ReceiveRequest;
- UINT16 RawIntrStat;
- UINT32 Count=0;
-
- Status = EFI_SUCCESS;
-
- ReceiveDataEnd = &ReadBuffer [ReadBytes];
- if( ReadBytes ) {
-
- ReceiveRequest = ReadBuffer;
- DEBUG((EFI_D_INFO,"Read: ---------------%d bytes to RX\r\n",ReceiveDataEnd - ReceiveRequest));
-
- while ((ReceiveDataEnd > ReceiveRequest) || (ReceiveDataEnd > ReadBuffer)) {
-
- //
- // Check for NACK
- //
- RawIntrStat = (UINT16)MmioRead32 (mI2CBaseAddress + R_IC_RawIntrStat);
- if ( 0 != ( RawIntrStat & I2C_INTR_TX_ABRT )) {
- MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT );
- Status = RETURN_DEVICE_ERROR;
- DEBUG((EFI_D_INFO,"TX ABRT ,%d bytes hasn't been transferred\r\n",ReceiveDataEnd - ReceiveRequest));
- break;
- }
-
- //
- // Determine if another byte was received
- //
- I2cStatus = (UINT16)MmioRead32 (mI2CBaseAddress + R_IC_STATUS);
- if (0 != ( I2cStatus & STAT_RFNE )) {
- ReceiveData = (UINT16)MmioRead32 ( mI2CBaseAddress + R_IC_DATA_CMD );
- *ReadBuffer++ = (UINT8)ReceiveData;
- DEBUG((EFI_D_INFO,"MmioRead32 ,1 byte 0x:%x is received\r\n",ReceiveData));
- }
-
- if(ReceiveDataEnd == ReceiveRequest) {
- MicroSecondDelay ( FIFO_WRITE_DELAY );
- DEBUG((EFI_D_INFO,"ReceiveDataEnd==ReceiveRequest------------%x\r\n",I2cStatus & STAT_RFNE));
- Count++;
- if(Count<1024) {
- //
- // To avoid sys hung without ul-pmc device on RVP,
- // waiting the last request to get data and make (ReceiveDataEnd > ReadBuffer) =TRUE.
- //
- continue;
- } else {
- break;
- }
- }
-
- //
- // Wait until a read request will fit.
- //
- if (0 == (I2cStatus & STAT_TFNF)) {
- DEBUG((EFI_D_INFO,"Wait until a read request will fit\r\n"));
- MicroSecondDelay (10);
- continue;
- }
-
- //
- // Issue the next read request.
- //
- if(End && Start) {
- MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_RESTART|B_CMD_STOP);
- } else if (!End && Start) {
- MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_RESTART);
- } else if (End && !Start) {
- MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_STOP);
- } else if (!End && !Start) {
- MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD);
- }
- MicroSecondDelay (FIFO_WRITE_DELAY);
-
- ReceiveRequest += 1;
- }
- }
-
- return Status;
-}
-
-/**
- Writes a Byte to I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be written
- @param Offset Offset from which the data has to be read
- @param *Byte Address to which the value written is stored
- @param Start Whether a RESTART is issued before the byte is sent or received
- @param End Whether STOP is generated after a data byte is sent or received
-
- @return EFI_SUCCESS IF the byte value has been successfully written
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS ByteWriteI2CBasic(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINTN WriteBytes,
- IN UINT8 *WriteBuffer,
- IN UINT8 Start,
- IN UINT8 End
- )
-{
-
- EFI_STATUS Status;
- UINT32 I2cStatus;
- UINT8 *TransmitEnd;
- UINT16 RawIntrStat;
- UINT32 Count=0;
-
- Status = EFI_SUCCESS;
-
- Status=I2CInit(I2cControllerIndex, SlaveAddress);
- if(Status!=EFI_SUCCESS)
- return Status;
-
- TransmitEnd = &WriteBuffer[WriteBytes];
- if( WriteBytes ) {
- DEBUG((EFI_D_INFO,"Write: --------------%d bytes to TX\r\n",TransmitEnd - WriteBuffer));
- while (TransmitEnd > WriteBuffer) {
- I2cStatus = MmioRead32 (mI2CBaseAddress + R_IC_STATUS);
- RawIntrStat = (UINT16)MmioRead32 (mI2CBaseAddress + R_IC_RawIntrStat);
- if (0 != ( RawIntrStat & I2C_INTR_TX_ABRT)) {
- MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT);
- Status = RETURN_DEVICE_ERROR;
- DEBUG((EFI_D_ERROR,"TX ABRT TransmitEnd:0x%x WriteBuffer:0x%x\r\n", TransmitEnd, WriteBuffer));
- break;
- }
- if (0 == (I2cStatus & STAT_TFNF)) {
- //
- // If TX not full , will send cmd or continue to wait
- //
- MicroSecondDelay (FIFO_WRITE_DELAY);
- continue;
- }
-
- if(End && Start) {
- MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++)|B_CMD_RESTART|B_CMD_STOP);
- } else if (!End && Start) {
- MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++)|B_CMD_RESTART);
- } else if (End && !Start) {
- MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++)|B_CMD_STOP);
- } else if (!End && !Start ) {
- MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++));
- }
-
- //
- // Add a small delay to work around some odd behavior being seen. Without this delay bytes get dropped.
- //
- MicroSecondDelay ( FIFO_WRITE_DELAY );//wait after send cmd
-
- //
- // Time out
- //
- while(1) {
- RawIntrStat = MmioRead16 ( mI2CBaseAddress + R_IC_RawIntrStat );
- if (0 != ( RawIntrStat & I2C_INTR_TX_ABRT)) {
- MmioRead16 (mI2CBaseAddress + R_IC_CLR_TX_ABRT);
- Status = RETURN_DEVICE_ERROR;
- DEBUG((EFI_D_ERROR,"TX ABRT TransmitEnd:0x%x WriteBuffer:0x%x\r\n", TransmitEnd, WriteBuffer));
- }
- if(0 == MmioRead16(mI2CBaseAddress + R_IC_TXFLR)) break;
-
- MicroSecondDelay (FIFO_WRITE_DELAY);
- Count++;
- if(Count<1024) {
- //
- // to avoid sys hung without ul-pmc device on RVP.
- // Waiting the last request to get data and make (ReceiveDataEnd > ReadBuffer) =TRUE.
- //
- continue;
- } else {
- break;
- }
- }//while( 1 )
- }
-
- }
-
- return Status;
-}
-
-/**
- Reads a Byte from I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be read
- @param Offset Offset from which the data has to be read
- @param ReadBytes Number of bytes to be read
- @param *ReadBuffer Address to which the value read has to be stored
-
- @return EFI_SUCCESS IF the byte value has been successfully read
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS ByteReadI2C(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINT8 Offset,
- IN UINTN ReadBytes,
- OUT UINT8 *ReadBuffer
- )
-{
- EFI_STATUS Status;
-
- DEBUG ((EFI_D_INFO, "ByteReadI2C:---offset:0x%x\n",Offset));
- Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress,1,&Offset,TRUE,FALSE);
- Status = ByteReadI2CBasic(I2cControllerIndex, SlaveAddress,ReadBytes,ReadBuffer,TRUE,TRUE);
-
- return Status;
-}
-
-/**
- Writes a Byte to I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be written
- @param Offset Offset from which the data has to be written
- @param WriteBytes Number of bytes to be written
- @param *Byte Address to which the value written is stored
-
- @return EFI_SUCCESS IF the byte value has been successfully read
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS ByteWriteI2C(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINT8 Offset,
- IN UINTN WriteBytes,
- IN UINT8 *WriteBuffer
- )
-{
- EFI_STATUS Status;
-
- DEBUG ((EFI_D_INFO, "ByteWriteI2C:---offset/bytes/buf:0x%x,0x%x,0x%x,0x%x\n",Offset,WriteBytes,WriteBuffer,*WriteBuffer));
- Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress,1,&Offset,TRUE,FALSE);
- Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress,WriteBytes,WriteBuffer,FALSE,TRUE);
-
- return Status;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLibDxe.inf b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLibDxe.inf
deleted file mode 100644
index cd10f1de93..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLibDxe.inf
+++ /dev/null
@@ -1,39 +0,0 @@
-## @file
-# Instance of I2C Library.
-#
-# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = I2CLib
- FILE_GUID = 7f62bf44-2ba7-4c2d-9d4a-91c8906ff053
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = I2CLib|DXE_DRIVER DXE_RUNTIME_DRIVER UEFI_DRIVER UEFI_APPLICATION
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64 EBC
-#
-
-[Sources.common]
- I2CLib.c
-
-[LibraryClasses]
- BaseLib
- IoLib
- TimerLib
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- Vlv2TbltDevicePkg/PlatformPkg.dec
- Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
-
-[Protocols]
- gEfiGlobalNvsAreaProtocolGuid
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CRegs.h b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CRegs.h
deleted file mode 100644
index 57455162f6..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CRegs.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/** @file
- Register Definitions for I2C Driver/PEIM.
-
- Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
---*/
-
-#ifndef I2C_REGS_H
-#define I2C_REGS_H
-
-//
-// FIFO write delay value.
-//
-#define FIFO_WRITE_DELAY 2
-
-//
-// MMIO Register Definitions.
-//
-#define R_IC_CON ( 0x00) // I2C Control
-#define B_IC_RESTART_EN BIT5
-#define B_IC_SLAVE_DISABLE BIT6
-#define V_SPEED_STANDARD 0x02
-#define V_SPEED_FAST 0x04
-#define V_SPEED_HIGH 0x06
-#define B_MASTER_MODE BIT0
-
-#define R_IC_TAR ( 0x04) // I2C Target Address
-#define IC_TAR_10BITADDR_MASTER BIT12
-
-#define R_IC_SAR ( 0x08) // I2C Slave Address
-#define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address
-#define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command
-
-#define B_READ_CMD BIT8 // 1 = read, 0 = write
-#define B_CMD_STOP BIT9 // 1 = STOP
-#define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
-
-#define V_WRITE_CMD_MASK ( 0xFF)
-
-#define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count
-#define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count
-#define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count
-#define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count
-#define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count
-#define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count
-#define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status
-#define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask
-#define I2C_INTR_GEN_CALL BIT11 // General call received
-#define I2C_INTR_START_DET BIT10
-#define I2C_INTR_STOP_DET BIT9
-#define I2C_INTR_ACTIVITY BIT8
-#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
-#define I2C_INTR_TX_EMPTY BIT4
-#define I2C_INTR_TX_OVER BIT3
-#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
-#define I2C_INTR_RX_OVER BIT1
-#define I2C_INTR_RX_UNDER BIT0
-#define R_IC_RawIntrStat ( 0x34) // I2C Raw Interrupt Status
-#define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold
-#define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold
-#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts
-#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt
-#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt
-#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt
-#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
-#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
-#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt
-#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
-#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt
-#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt
-#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt
-#define R_IC_ENABLE ( 0x6C) // I2C Enable
-#define R_IC_STATUS ( 0x70) // I2C Status
-
-#define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits
-
-#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.
-#define STAT_RFF BIT4 // RX FIFO is completely full
-#define STAT_RFNE BIT3 // RX FIFO is not empty
-#define STAT_TFE BIT2 // TX FIFO is completely empty
-#define STAT_TFNF BIT1 // TX FIFO is not full
-
-#define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register
-#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
-#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register
-#define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register
-#define R_IC_DMA_CR ( 0x88) // DMA Control Register
-#define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level
-#define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level
-#define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register
-#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register
-#define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register
-#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register
-#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
-#define R_IC_COMP_TYPE ( 0xFC) // Component Type
-
-#define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD
-#define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4
-#define I2C_FS_SCL_HCNT_VALUE_100M 0x54
-#define I2C_FS_SCL_LCNT_VALUE_100M 0x9a
-#define I2C_HS_SCL_HCNT_VALUE_100M 0x7
-#define I2C_HS_SCL_LCNT_VALUE_100M 0xE
-
-#define IC_TAR_10BITADDR_MASTER BIT12
-#define FIFO_SIZE 32
-#define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status
-#define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask
-#define I2C_INTR_GEN_CALL BIT11 // General call received
-#define I2C_INTR_START_DET BIT10
-#define I2C_INTR_STOP_DET BIT9
-#define I2C_INTR_ACTIVITY BIT8
-#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
-#define I2C_INTR_TX_EMPTY BIT4
-#define I2C_INTR_TX_OVER BIT3
-#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
-#define I2C_INTR_RX_OVER BIT1
-#define I2C_INTR_RX_UNDER BIT0
-
-#define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset
-#define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
-#define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
-#define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock Parameters
-
-#endif
\ No newline at end of file
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CAccess.h b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CAccess.h
deleted file mode 100644
index bf6ef4c747..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CAccess.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/** @file
- Misc Registers Definition.
-
- Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
---*/
-
-#ifndef _I2C_ACCESS_H_
-#define _I2C_ACCESS_H_
-
-#include "I2CIoLibPei.h"
-
-#define DEFAULT_PCI_BUS_NUMBER_PCH 0
-
-#define PCI_DEVICE_NUMBER_PCH_LPC 31
-#define PCI_FUNCTION_NUMBER_PCH_LPC 0
-
-#define R_PCH_LPC_ACPI_BASE 0x40 // ABASE, 16bit
-#define R_PCH_LPC_ACPI_BASEADR 0x400 // ABASE, 16bit
-#define B_PCH_LPC_ACPI_BASE_EN BIT1 // Enable Bit
-#define B_PCH_LPC_ACPI_BASE_BAR 0x0000FF80 // Base Address, 128 Bytes
-#define V_PCH_ACPI_PM1_TMR_MAX_VAL 0x1000000 // The timer is 24 bit overflow
-#define B_PCH_ACPI_PM1_TMR_VAL 0xFFFFFF // The timer value mask
-
-#define R_PCH_ACPI_PM1_TMR 0x08 // Power Management 1 Timer
-#define V_PCH_ACPI_PM1_TMR_FREQUENCY 3579545 // Timer Frequency
-
-
-#define PchLpcPciCfg8(Register) I2CLibPeiMmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
-
-#define PCIEX_BASE_ADDRESS 0xE0000000
-#define PCI_EXPRESS_BASE_ADDRESS ((VOID *) (UINTN) PCIEX_BASE_ADDRESS)
-
-#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
- ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
- (UINTN)(Bus << 20) + \
- (UINTN)(Device << 15) + \
- (UINTN)(Function << 12) + \
- (UINTN)(Register) \
- )
-#endif
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.c b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.c
deleted file mode 100644
index d5f8dfd012..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/** @file
- MicroSecondDelay implementation of ACPI Timer.
-
- Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
---*/
-
-#include "PiPei.h"
-#include "I2CAccess.h"
-#include "I2CDelayPei.h"
-#include <Library/DebugLib.h>
-#include <Library/PeiServicesTablePointerLib.h>
-#include <Ppi/Stall.h>
-
-/**
- Stalls the CPU for at least the given number of microseconds.
- Stalls the CPU for the number of microseconds specified by MicroSeconds.
-
- @param MicroSeconds The minimum number of microseconds to delay.
-
- @return EFI_STATUS
-
-**/
-EFI_STATUS
-EFIAPI
-MicroSecondDelay (
- IN UINTN MicroSeconds
- )
-{
-
- EFI_PEI_STALL_PPI *StallPpi;
- EFI_STATUS Status;
- CONST EFI_PEI_SERVICES **PeiServices;
-
- PeiServices = GetPeiServicesTablePointer();
-
-
- Status = (**PeiServices).LocatePpi (PeiServices, &gEfiPeiStallPpiGuid, 0, NULL, &StallPpi);
- ASSERT(!EFI_ERROR(Status));
-
- StallPpi->Stall (PeiServices, StallPpi, MicroSeconds);
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.h b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.h
deleted file mode 100644
index 604f1f67c5..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/** @file
- MicroSecondDelay implementation of ACPI Timer.
-
- Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __I2C_DELAY_PEI__
-
-#define __I2C_DELAY_PEI__
-#include "PiPei.h"
-
-/**
- Stalls the CPU for at least the given number of microseconds.
-
- Stalls the CPU for the number of microseconds specified by MicroSeconds.
-
- @param MicroSeconds The minimum number of microseconds to delay.
-
- @return MicroSeconds
-
-**/
-EFI_STATUS
-EFIAPI
-MicroSecondDelay (
- IN UINTN MicroSeconds
- );
-
-#endif
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.c b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.c
deleted file mode 100644
index 6a37dbec1d..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/** @file
- Functions for access I2C MMIO register.
-
- Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-#include <Library/DebugLib.h>
-#include <Library/PeiServicesTablePointerLib.h>
-
-/**
- Reads an 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-I2CLibPeiMmioRead8 (
- IN UINTN Address
- )
-{
- UINT8 Value;
-
- Value = *(volatile UINT8*)Address;
- return Value;
-}
-
-/**
- Reads a 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-I2CLibPeiMmioRead16 (
- IN UINTN Address
- )
-{
- UINT16 Value;
-
- ASSERT ((Address & 1) == 0);
- Value = *(volatile UINT16*)Address;
- return Value;
-}
-
-/**
- Writes a 16-bit MMIO register.
-
- Writes the 16-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
- @return Value.
-
-**/
-UINT16
-EFIAPI
-I2CLibPeiMmioWrite16 (
- IN UINTN Address,
- IN UINT16 Value
- )
-{
- ASSERT ((Address & 1) == 0);
- *(volatile UINT16*)Address = Value;
- return Value;
-}
-
-/**
- Reads a 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-I2CLibPeiMmioRead32 (
- IN UINTN Address
- )
-{
- UINT32 Value;
-
- ASSERT ((Address & 3) == 0);
- Value = *(volatile UINT32*)Address;
-
- return Value;
-}
-
-/**
- Writes a 32-bit MMIO register.
-
- Writes the 32-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
- @return Value.
-
-**/
-UINT32
-EFIAPI
-I2CLibPeiMmioWrite32 (
- IN UINTN Address,
- IN UINT32 Value
- )
-{
- ASSERT ((Address & 3) == 0);
- *(volatile UINT32*)Address = Value;
- return Value;
-}
-
-/**
- OR a 32-bit MMIO register.
-
- OR the 32-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The MMIO register to write OR.
- @param Value The value to OR to the MMIO register.
-
- @return Value.
-
-**/
-UINT32
-EFIAPI
-I2CLibPeiMmioOr32 (
- IN UINTN Address,
- IN UINT32 OrData
- )
-{
- return I2CLibPeiMmioWrite32 (Address, I2CLibPeiMmioRead32(Address) | OrData);
-}
-
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.h b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.h
deleted file mode 100644
index b68bc1ed09..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/** @file
- Functions for access I2C MMIO register.
-
- Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __I2C_IOLIB_PEI__
-
-#define __I2C_IOLIB_PEI__
-#include <PiPei.h>
-
-
-/**
- Reads an 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-
-UINT8
-EFIAPI
-I2CLibPeiMmioRead8 (
- IN UINTN Address
- );
-
-
-/**
- Reads a 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-I2CLibPeiMmioRead16 (
- IN UINTN Address
- );
-
-
-/**
- Writes a 16-bit MMIO register.
-
- Writes the 16-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
- @return Value.
-
-**/
-UINT16
-EFIAPI
-I2CLibPeiMmioWrite16 (
- IN UINTN Address,
- IN UINT16 Value
- );
-
-
-/**
- Reads a 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-I2CLibPeiMmioRead32 (
- IN UINTN Address
- );
-
-
-/**
- Writes a 32-bit MMIO register.
-
- Writes the 32-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
- @return Value.
-
-**/
-UINT32
-EFIAPI
-I2CLibPeiMmioWrite32 (
- IN UINTN Address,
- IN UINT32 Value
- );
-
-
-/**
- OR a 32-bit MMIO register.
-
- OR the 32-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The MMIO register to write OR.
- @param Value The value to OR to the MMIO register.
-
- @return Value.
-
-**/
-UINT32
-EFIAPI
-I2CLibPeiMmioOr32 (
- IN UINTN Address,
- IN UINT32 OrData
- );
-
-
-#endif
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.c b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.c
deleted file mode 100644
index dd5cceb70d..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.c
+++ /dev/null
@@ -1,638 +0,0 @@
-/** @file
- I2C PEI Lib Instance.
-
- Copyright (c) 1999- 2015, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include "I2CDelayPei.h"
-#include "I2CIoLibPei.h"
-#include "I2CAccess.h"
-#include "I2CLibPei.h"
-#include <PlatformBaseAddresses.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/PeiServicesTablePointerLib.h>
-#include <Library/HobLib.h>
-#include <PchRegs/PchRegsPcu.h>
-#include <PchRegs/PchRegsLpss.h>
-
-#define LPSS_PCI_DEVICE_NUMBER 8
-
-#define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset
-#define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
-#define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
-#define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock Parameters
-
-#define PEI_TEPM_LPSS_DMA_BAR 0xFE900000
-#define PEI_TEPM_LPSS_I2C0_BAR 0xFE910000
-#define PCI_CONFIG_SPACE_SIZE 0x10000
-
-EFI_GUID mI2CPeiInitGuid = {
- 0x96DED71A, 0xB9E7, 0x4EAD, 0x96, 0x2C, 0x01, 0x69, 0x3C, 0xED, 0x2A, 0x64
-};
-
-
-UINT16 I2CGPIO[]= {
- //
- // 19.1.6 I2C0
- // I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210
- // I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200
- //
- 0x0210,
- 0x0200,
-
- //
- // 19.1.7 I2C1
- // I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0
- // I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0
- //
- 0x01F0,
- 0x01E0,
-
- //
- // 19.1.8 I2C2
- // I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0
- // I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0
- //
- 0x01D0,
- 0x01B0,
-
- //
- // 19.1.9 I2C3
- // I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190
- // I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0
- //
- 0x0190,
- 0x01C0,
-
- //
- // 19.1.10 I2C4
- // I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0
- // I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170
- //
- 0x01A0,
- 0x0170,
-
- //
- // 19.1.11 I2C5
- // I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150
- // I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140
- //
- 0x0150,
- 0x0140,
-
- //
- // 19.1.12 I2C6
- // I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180
- // I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160
- //
- 0x0180,
- 0x0160
-};
-
-/**
- Constructor of this library.
-
- @param VOID
-
- @return EFI_SUCCESS
-**/
-EFI_STATUS
-EFIAPI
-IntelI2CPeiLibConstructor (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- UINTN Index;
-
- for (Index = 0; Index < sizeof(I2CGPIO)/sizeof(UINT16); Index ++) {
- I2CLibPeiMmioWrite32(IO_BASE_ADDRESS+I2CGPIO[Index], 0x2003CC81);
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Programe all I2C controllers on LPSS.
-
- I2C0 is function 1 of LPSS. I2C1 is function 2 of LPSS, etc..
-
- @param VOID
-
- @return EFI_SUCCESS
-**/
-EFI_STATUS
-ProgramPciLpssI2C (
- VOID
- )
-{
- UINT32 PmcBase;
- UINT32 DevID;
- UINTN PciMmBase=0;
- UINTN Index;
- UINTN Bar0;
- UINTN Bar1;
- DEBUG ((EFI_D_INFO, "Pei ProgramPciLpssI2C() Start\n"));
-
- //
- // Set the VLV Function Disable Register to ZERO
- //
- PmcBase = I2CLibPeiMmioRead32(PciD31F0RegBase + R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR;
-
- if(I2CLibPeiMmioRead32(PmcBase + R_PCH_PMC_FUNC_DIS)&
- (B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1 | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2
- | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3 | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4 | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5
- | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6 | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC7)) {
- I2CLibPeiMmioWrite32(
- PmcBase+R_PCH_PMC_FUNC_DIS,
- I2CLibPeiMmioRead32(PmcBase + R_PCH_PMC_FUNC_DIS)& \
- ~(B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1 | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2 \
- | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3 | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4 \
- | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5 | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6|B_PCH_PMC_FUNC_DIS_LPSS2_FUNC7)
- );
- DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() enable all I2C controllers\n"));
- }
-
- for(Index = 0; Index < LPSS_PCI_DEVICE_NUMBER; Index ++) {
-
- PciMmBase = MmPciAddress (
- 0,
- DEFAULT_PCI_BUS_NUMBER_PCH,
- PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
- Index,
- 0
- );
- DevID = I2CLibPeiMmioRead32(PciMmBase);
-
- Bar0 = PEI_TEPM_LPSS_DMA_BAR + (Index * PCI_CONFIG_SPACE_SIZE);
- Bar1 = Bar0 + 0x8000;
-
- DEBUG((EFI_D_ERROR, "Program Pci Lpss I2C Device Function=%x DevID=%08x\n", Index, DevID));
-
- //
- // Check if device present
- //
- if (DevID != 0xFFFFFFFF) {
- if(!(I2CLibPeiMmioRead32 (PciMmBase + R_PCH_LPSS_I2C_STSCMD) & B_PCH_LPSS_I2C_STSCMD_MSE)) {
- //
- // Program BAR 0
- //
- I2CLibPeiMmioWrite32((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR), (UINT32)(Bar0 & B_PCH_LPSS_I2C_BAR_BA));
-
- DEBUG ((EFI_D_ERROR, "I2CBaseAddress1 = 0x%x \n",I2CLibPeiMmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR)));
-
- //
- // Program BAR 1
- //
- I2CLibPeiMmioWrite32 ((UINTN)(PciMmBase + R_PCH_LPSS_I2C_BAR1), (UINT32)(Bar1 & B_PCH_LPSS_I2C_BAR1_BA));
- DEBUG ((EFI_D_ERROR, "I2CBaseAddress1 = 0x%x \n",I2CLibPeiMmioRead32(PciMmBase+R_PCH_LPSS_I2C_BAR1)));
-
- //
- // Bus Master Enable & Memory Space Enable
- //
- I2CLibPeiMmioWrite32((UINTN) (PciMmBase + R_PCH_LPSS_I2C_STSCMD), (UINT32)(B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE));
- }
-
- //
- // Release Resets
- //
- I2CLibPeiMmioWrite32 (Bar0 + R_PCH_LPIO_I2C_MEM_RESETS, (B_PCH_LPIO_I2C_MEM_RESETS_FUNC | B_PCH_LPIO_I2C_MEM_RESETS_APB));
-
- //
- // Activate Clocks
- //
- I2CLibPeiMmioWrite32 (Bar0 + R_PCH_LPSS_I2C_MEM_PCP, 0x80020003);//No use for A0
-
- DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() Programmed()\n"));
- }
-
- }
-
- DEBUG ((EFI_D_INFO, "Pei ProgramPciLpssI2C() End\n"));
-
- return EFI_SUCCESS;
-}
-
-/**
- Disable I2C Bus.
-
- @param I2cControllerIndex Index of I2C controller.
-
- @return EFI_SUCCESS
-**/
-EFI_STATUS
-I2cDisable (
- IN UINT8 I2cControllerIndex
- )
-{
- UINTN I2CBaseAddress;
- UINT32 NumTries = 10000; // 0.1 seconds
-
- I2CBaseAddress = (UINT32) PEI_TEPM_LPSS_I2C0_BAR + I2cControllerIndex * PCI_CONFIG_SPACE_SIZE;
-
- I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_ENABLE, 0);
- while (0 != ( I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_ENABLE_STATUS ) & 1)) {
- MicroSecondDelay (10);
- NumTries --;
- if(0 == NumTries) return EFI_NOT_READY;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Enable I2C Bus.
-
- @param I2cControllerIndex Index of I2C controller.
-
- @return EFI_SUCCESS
-**/
-EFI_STATUS
-I2cEnable (
- IN UINT8 I2cControllerIndex
- )
-{
- UINTN I2CBaseAddress;
- UINT32 NumTries = 10000; // 0.1 seconds
-
- I2CBaseAddress = (UINT32) PEI_TEPM_LPSS_I2C0_BAR+ I2cControllerIndex * PCI_CONFIG_SPACE_SIZE;
- I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_ENABLE, 1);
- while (0 == ( I2CLibPeiMmioRead16 ( I2CBaseAddress + R_IC_ENABLE_STATUS ) & 1)) {
- MicroSecondDelay (10);
- NumTries --;
- if(0 == NumTries) return EFI_NOT_READY;
- }
-
- return EFI_SUCCESS;
-}
-
-
-/**
- Set the I2C controller bus clock frequency.
-
- @param[in] This Address of the library's I2C context structure
- @param[in] PlatformData Address of the platform configuration data
- @param[in] BusClockHertz New I2C bus clock frequency in Hertz
-
- @retval RETURN_SUCCESS The bus frequency was set successfully.
- @retval RETURN_UNSUPPORTED The controller does not support this frequency.
-
-**/
-EFI_STATUS
-I2cBusFrequencySet (
- IN UINTN I2CBaseAddress,
- IN UINTN BusClockHertz,
- IN UINT16 *I2cMode
- )
-{
- DEBUG((EFI_D_INFO,"InputFreq BusClockHertz: %d\r\n",BusClockHertz));
-
- *I2cMode = B_IC_RESTART_EN | B_IC_SLAVE_DISABLE | B_MASTER_MODE;
-
- //
- // Set the 100 KHz clock divider
- //
- // From Table 10 of the I2C specification
- //
- // High: 4.00 uS
- // Low: 4.70 uS
- //
- I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_SS_SCL_HCNT, (UINT16)0x214 );
- I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_SS_SCL_LCNT, (UINT16)0x272 );
-
- //
- // Set the 400 KHz clock divider
- //
- // From Table 10 of the I2C specification
- //
- // High: 0.60 uS
- // Low: 1.30 uS
- //
- I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_FS_SCL_HCNT, (UINT16)0x50 );
- I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_FS_SCL_LCNT, (UINT16)0xAD );
-
- switch ( BusClockHertz ) {
- case 100 * 1000:
- I2CLibPeiMmioWrite32 ( I2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x40);//100K
- *I2cMode |= V_SPEED_STANDARD;
- break;
- case 400 * 1000:
- I2CLibPeiMmioWrite32 ( I2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x32);//400K
- *I2cMode |= V_SPEED_FAST;
- break;
- default:
- I2CLibPeiMmioWrite32 ( I2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x09);//3.4M
- *I2cMode |= V_SPEED_HIGH;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Initializes the host controller to execute I2C commands.
-
- @param I2cControllerIndex Index of I2C controller in LPSS device. 0 represents I2C0, which is PCI function 1 of LPSS device.
-
- @return EFI_SUCCESS Opcode initialization on the I2C host controller completed.
- @return EFI_DEVICE_ERROR Device error, operation failed.
-**/
-EFI_STATUS
-I2CInit (
- UINT8 I2cControllerIndex,
- UINT16 SlaveAddress
- )
-{
- EFI_STATUS Status;
- UINT32 NumTries = 0;
- UINTN I2CBaseAddress;
- UINT16 I2cMode;
- UINTN PciMmBase=0;
-
-
- PciMmBase = MmPciAddress (
- 0,
- DEFAULT_PCI_BUS_NUMBER_PCH,
- PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
- (I2cControllerIndex + 1),
- 0
- );
-
- I2CBaseAddress = I2CLibPeiMmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR);
-
- //
- // Verify the parameters
- //
- if (1023 < SlaveAddress ) {
- Status = EFI_INVALID_PARAMETER;
- DEBUG((EFI_D_INFO,"I2cStartRequest Exit with Status %r\r\n", Status));
- return Status;
- }
-
- if(I2CBaseAddress == (PEI_TEPM_LPSS_I2C0_BAR + I2cControllerIndex * PCI_CONFIG_SPACE_SIZE)) {
- return EFI_SUCCESS;
- }
- ProgramPciLpssI2C();
-
- I2CBaseAddress = (UINT32) (PEI_TEPM_LPSS_I2C0_BAR + I2cControllerIndex * PCI_CONFIG_SPACE_SIZE);
- DEBUG ((EFI_D_ERROR, "I2CBaseAddress = 0x%x \n",I2CBaseAddress));
- NumTries = 10000; // 1 seconds
- while ((1 == ( I2CLibPeiMmioRead32 ( I2CBaseAddress + R_IC_STATUS) & STAT_MST_ACTIVITY ))) {
- MicroSecondDelay(10);
- NumTries --;
- if(0 == NumTries)
- return EFI_DEVICE_ERROR;
- }
-
- Status = I2cDisable (I2cControllerIndex);
- DEBUG((EFI_D_INFO, "I2cDisable Status = %r\r\n", Status));
-
- I2cBusFrequencySet(I2CBaseAddress, 400 * 1000, &I2cMode);//Set I2cMode
-
- I2CLibPeiMmioWrite16(I2CBaseAddress + R_IC_INTR_MASK, 0x0);
- if (0x7F < SlaveAddress) {
- SlaveAddress = (SlaveAddress & 0x3ff ) | IC_TAR_10BITADDR_MASTER;
- }
- I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_TAR, (UINT16) SlaveAddress );
- I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_RX_TL, 0);
- I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_TX_TL, 0 );
- I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_CON, I2cMode);
-
- Status = I2cEnable(I2cControllerIndex);
- DEBUG((EFI_D_INFO, "I2cEnable Status = %r\r\n", Status));
- I2CLibPeiMmioRead16 ( I2CBaseAddress + R_IC_CLR_TX_ABRT );
-
- return EFI_SUCCESS;
-}
-
-/**
- Reads a Byte from I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be read
- @param Offset Offset from which the data has to be read
- @param *Byte Address to which the value read has to be stored
-
- @return EFI_SUCCESS If the byte value has been successfully read
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS ByteReadI2CBasic(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINTN ReadBytes,
- OUT UINT8 *ReadBuffer,
- IN UINT8 Start,
- IN UINT8 End
- )
-{
-
- EFI_STATUS Status;
- UINT32 I2cStatus;
- UINT16 ReceiveData;
- UINT8 *ReceiveDataEnd;
- UINT8 *ReceiveRequest;
- UINT16 RawIntrStat;
- UINTN I2CBaseAddress;
-
- I2CBaseAddress = (UINT32)(PEI_TEPM_LPSS_I2C0_BAR + I2cControllerIndex * PCI_CONFIG_SPACE_SIZE);
-
- Status = EFI_SUCCESS;
-
- I2CInit(I2cControllerIndex, SlaveAddress);
-
- ReceiveDataEnd = &ReadBuffer [ReadBytes];
- if(ReadBytes) {
- ReceiveRequest = ReadBuffer;
- DEBUG((EFI_D_INFO,"Read: ---------------%d bytes to RX\r\n",ReceiveDataEnd - ReceiveRequest));
-
- while ((ReceiveDataEnd > ReceiveRequest) || (ReceiveDataEnd > ReadBuffer)) {
- //
- // Check for NACK
- //
- RawIntrStat = I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_RawIntrStat );
- if ( 0 != (RawIntrStat & I2C_INTR_TX_ABRT )) {
- I2CLibPeiMmioRead16 ( I2CBaseAddress + R_IC_CLR_TX_ABRT );
- Status = RETURN_DEVICE_ERROR;
- DEBUG((EFI_D_INFO,"TX ABRT ,%d bytes hasn't been transferred\r\n",ReceiveDataEnd - ReceiveRequest));
- break;
- }
-
- //
- // Determine if another byte was received
- //
- I2cStatus = I2CLibPeiMmioRead16 ( I2CBaseAddress + R_IC_STATUS );
- if ( 0 != ( I2cStatus & STAT_RFNE )) {
- ReceiveData = I2CLibPeiMmioRead16 ( I2CBaseAddress + R_IC_DATA_CMD );
- *ReadBuffer++ = (UINT8)ReceiveData;
- DEBUG((EFI_D_INFO,"MmioRead32 ,1 byte 0x:%x is received\r\n",ReceiveData));
- }
-
- if(ReceiveDataEnd==ReceiveRequest) {
- //
- // Waiting the last request to get data and make (ReceiveDataEnd > ReadBuffer) =TRUE.
- //
- continue;
- }
-
- //
- // Wait until a read request will fit
- //
- if ( 0 == ( I2cStatus & STAT_TFNF )) {
- MicroSecondDelay ( 10 );
- continue;
- }
-
- //
- // Issue the next read request
- //
- if(End && Start ) {
- I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_RESTART|B_CMD_STOP);
- } else if (!End && Start ) {
- I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_RESTART);
- } else if (End && !Start ) {
- I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_STOP);
- } else if (!End && !Start ) {
- I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD);
- }
- ReceiveRequest += 1;
- }
-
- }
- return Status;
-
-}
-
-/**
- Writes a Byte to I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be written
- @param Offset Offset from which the data has to be read
- @param *Byte Address to which the value written is stored
-
- @return EFI_SUCCESS IF the byte value has been successfully written
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS
-ByteWriteI2CBasic(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINTN WriteBytes,
- IN UINT8 *WriteBuffer,
- IN UINT8 Start,
- IN UINT8 End
- )
-{
-
- EFI_STATUS Status;
- UINT32 I2cStatus;
- UINT8 *TransmitEnd;
- UINT16 RawIntrStat;
- UINTN I2CBaseAddress;
-
- I2CBaseAddress = (UINT32)PEI_TEPM_LPSS_I2C0_BAR+ I2cControllerIndex * PCI_CONFIG_SPACE_SIZE;
-
- Status = EFI_SUCCESS;
-
- I2CInit(I2cControllerIndex, SlaveAddress);
-
- TransmitEnd = &WriteBuffer [WriteBytes];
- if( WriteBytes ) {
-
- DEBUG((EFI_D_INFO,"Write: --------------%d bytes to TX\r\n", TransmitEnd - WriteBuffer));
-
- while ( TransmitEnd > WriteBuffer) {
- I2cStatus = I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_STATUS);
- RawIntrStat = I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_RawIntrStat);
- if ( 0 != (RawIntrStat & I2C_INTR_TX_ABRT)) {
- I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_CLR_TX_ABRT);
- Status = RETURN_DEVICE_ERROR;
- DEBUG((EFI_D_ERROR,"TX ABRT TransmitEnd:0x%x WriteBuffer:0x%x\r\n", TransmitEnd, WriteBuffer));
- break;
- }
- if (0 == ( I2cStatus & STAT_TFNF)) {
- continue;
- }
- if(End && Start) {
- I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++) | B_CMD_RESTART | B_CMD_STOP);
- } else if (!End && Start ) {
- I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++) | B_CMD_RESTART);
- } else if (End && !Start ) {
- I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++) | B_CMD_STOP);
- } else if (!End && !Start ) {
- I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++));
- }
-
- // Add a small delay to work around some odd behavior being seen. Without this delay bytes get dropped.
- MicroSecondDelay ( FIFO_WRITE_DELAY );
- }
-
- }
-
- if(EFI_ERROR(Status)) {
- DEBUG((EFI_D_INFO,"I2cStartRequest Exit with Status %r\r\n",Status));
- }
-
- return Status;
-}
-
-/**
- Reads a Byte from I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be read
- @param Offset Offset from which the data has to be read
- @param ReadBytes Number of bytes to be read
- @param *ReadBuffer Address to which the value read has to be stored
-
- @return EFI_SUCCESS IF the byte value has been successfully read
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS
-ByteReadI2C(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINT8 Offset,
- IN UINTN ReadBytes,
- OUT UINT8 *ReadBuffer
- )
-{
- EFI_STATUS Status;
-
- DEBUG ((EFI_D_ERROR, "ByteReadI2C:---offset:0x%x\n",Offset));
- Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress, 1, &Offset,TRUE,FALSE);
- Status = ByteReadI2CBasic(I2cControllerIndex, SlaveAddress, ReadBytes, ReadBuffer, TRUE, TRUE);
-
- return Status;
-}
-
-/**
- Writes a Byte to I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be written
- @param Offset Offset from which the data has to be written
- @param WriteBytes Number of bytes to be written
- @param *Byte Address to which the value written is stored
-
- @return EFI_SUCCESS IF the byte value has been successfully read
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS ByteWriteI2C(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINT8 Offset,
- IN UINTN WriteBytes,
- IN UINT8 *WriteBuffer
- )
-{
- EFI_STATUS Status;
-
- DEBUG ((EFI_D_ERROR, "ByteWriteI2C:---offset/bytes/buf:0x%x,0x%x,0x%x,0x%x\n",Offset,WriteBytes,WriteBuffer,*WriteBuffer));
- Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress, 1, &Offset, TRUE, FALSE);
- Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress, WriteBytes, WriteBuffer, FALSE, TRUE);
-
- return Status;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.h b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.h
deleted file mode 100644
index 47536aebf7..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/** @file
- I2C PEI Lib Instance.
-
- Copyright (c) 1999- 2015, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef I2C_PEI_REGS_H
-#define I2C_PEI_REGS_H
-
-#include "PiPei.h"
-
-#define R_PCH_LPC_PMC_BASE 0x44
-#define B_PCH_LPC_PMC_BASE_BAR 0xFFFFFE00
-#define R_PCH_PMC_FUNC_DIS 0x34 // Function Disable Register
-#define PCIEX_BASE_ADDRESS 0xE0000000
-#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC7 BIT7 // LPSS SPI Disable
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC6 BIT6 // LPSS HSUART #2 Disable
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC5 BIT5 // LPSS HSUART #1 Disable
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC4 BIT4 // LPSS I2S Disable
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC3 BIT3 // LPSS PCM Disable
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC2 BIT2 // LPSS I2C #2 Disable
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC1 BIT1 // LPSS I2C #1 Disable
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC0 BIT0 // LPSS DMA Disable
-
-
-#define DEFAULT_PCI_BUS_NUMBER_PCH 0
-
-#define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command
-#define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA
-#define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA
-#define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List
-#define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
-#define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable
-#define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable
-#define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable
-#define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable
-
-#define R_PCH_LPSS_I2C_BAR 0x10 // BAR
-#define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address
-#define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator
-#define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable
-#define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
-#define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space
-
-#define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1
-#define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address
-#define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator
-#define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable
-#define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
-#define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space
-
-#define NUM_RETRIES 0xFFFF
-
-//
-// LPIO I2C Module Memory Space Registers
-//
-#define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset
-#define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
-#define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
-
-#define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock Parameters
-
-#define bit(a) 1 << (a)
-
-//
-// MMIO Register Definitions
-//
-
-#define I2C0_REG_SPACE_ADDR_BASE 0xFF138000 //01K
-
-#define R_IC_CON ( 0x00) // I2C Control
-#define B_IC_RESTART_EN BIT5
-#define B_IC_SLAVE_DISABLE BIT6
-#define V_SPEED_STANDARD 0x02
-#define V_SPEED_FAST 0x04
-#define V_SPEED_HIGH 0x06
-#define B_MASTER_MODE BIT0
-
-#define R_IC_TAR ( 0x04) // I2C Target Address
-#define IC_TAR_10BITADDR_MASTER BIT12
-
-#define R_IC_SAR ( 0x08) // I2C Slave Address
-#define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address
-#define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command
-
-#define B_READ_CMD BIT8 // 1 = read, 0 = write
-#define B_CMD_STOP BIT9 // 1 = STOP
-#define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
-
-#define V_WRITE_CMD_MASK ( 0xFF)
-
-#define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count
-#define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count
-#define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count
-#define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count
-#define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count
-#define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count
-#define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status
-#define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask
-#define I2C_INTR_GEN_CALL BIT11 // General call received
-#define I2C_INTR_START_DET BIT10
-#define I2C_INTR_STOP_DET BIT9
-#define I2C_INTR_ACTIVITY BIT8
-#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
-#define I2C_INTR_TX_EMPTY BIT4
-#define I2C_INTR_TX_OVER BIT3
-#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
-#define I2C_INTR_RX_OVER BIT1
-#define I2C_INTR_RX_UNDER BIT0
-#define R_IC_RawIntrStat ( 0x34) // I2C Raw Interrupt Status
-#define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold
-#define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold
-#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts
-#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt
-#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt
-#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt
-#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
-#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
-#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt
-#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
-#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt
-#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt
-#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt
-#define R_IC_ENABLE ( 0x6C) // I2C Enable
-#define R_IC_STATUS ( 0x70) // I2C Status
-
-#define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits
-
-#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.
-#define STAT_RFF BIT4 // RX FIFO is completely full
-#define STAT_RFNE BIT3 // RX FIFO is not empty
-#define STAT_TFE BIT2 // TX FIFO is completely empty
-#define STAT_TFNF BIT1 // TX FIFO is not full
-
-#define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register
-#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
-#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register
-#define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register
-#define R_IC_DMA_CR ( 0x88) // DMA Control Register
-#define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level
-#define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level
-#define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register
-#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register
-#define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register
-#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register
-#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
-#define R_IC_COMP_TYPE ( 0xFC) // Component Type
-
-#define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD
-#define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4
-#define I2C_FS_SCL_HCNT_VALUE_100M 0x54
-#define I2C_FS_SCL_LCNT_VALUE_100M 0x9a
-#define I2C_HS_SCL_HCNT_VALUE_100M 0x7
-#define I2C_HS_SCL_LCNT_VALUE_100M 0xE
-
-//
-// FIFO write workaround value.
-//
-#define FIFO_WRITE_DELAY 2
-#define IC_TAR_10BITADDR_MASTER BIT12
-#define FIFO_SIZE 32
-#define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status
-#define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask
-#define I2C_INTR_GEN_CALL BIT11 // General call received
-#define I2C_INTR_START_DET BIT10
-#define I2C_INTR_STOP_DET BIT9
-#define I2C_INTR_ACTIVITY BIT8
-#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
-#define I2C_INTR_TX_EMPTY BIT4
-#define I2C_INTR_TX_OVER BIT3
-#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
-#define I2C_INTR_RX_OVER BIT1
-#define I2C_INTR_RX_UNDER BIT0
-
-/**
- Programe all I2C controllers on LPSS.
-
- I2C0 is function 1 of LPSS. I2C1 is function 2 of LPSS, etc..
-
- @param VOID
-
- @return EFI_SUCCESS
-**/
-EFI_STATUS
-ProgramPciLpssI2C (
- VOID
- );
-
-/**
- Reads a Byte from I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be read
- @param Offset Offset from which the data has to be read
- @param *Byte Address to which the value read has to be stored
- @param Start Whether a RESTART is issued before the byte is sent or received
- @param End Whether STOP is generated after a data byte is sent or received
-
- @return EFI_SUCCESS If the byte value has been successfully read
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS
-ByteReadI2CBasic(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINTN ReadBytes,
- OUT UINT8 *ReadBuffer,
- IN UINT8 Start,
- IN UINT8 End
- );
-
-/**
- Writes a Byte to I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be written
- @param Offset Offset from which the data has to be read
- @param *Byte Address to which the value written is stored
- @param Start Whether a RESTART is issued before the byte is sent or received
- @param End Whether STOP is generated after a data byte is sent or received
-
- @return EFI_SUCCESS IF the byte value has been successfully written
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS
-ByteWriteI2CBasic(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINTN WriteBytes,
- IN UINT8 *WriteBuffer,
- IN UINT8 Start,
- IN UINT8 End
- );
-
-/**
- Reads a Byte from I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be read
- @param Offset Offset from which the data has to be read
- @param ReadBytes Number of bytes to be read
- @param *ReadBuffer Address to which the value read has to be stored
-
- @return EFI_SUCCESS IF the byte value has been successfully read
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS
-ByteReadI2C(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINT8 Offset,
- IN UINTN ReadBytes,
- OUT UINT8 *ReadBuffer
- );
-
-/**
- Writes a Byte to I2C Device.
-
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
- @param SlaveAddress Device Address from which the byte value has to be written
- @param Offset Offset from which the data has to be written
- @param WriteBytes Number of bytes to be written
- @param *Byte Address to which the value written is stored
-
- @return EFI_SUCCESS IF the byte value has been successfully read
- @return EFI_DEVICE_ERROR Operation Failed, Device Error
-**/
-EFI_STATUS
-ByteWriteI2C(
- IN UINT8 I2cControllerIndex,
- IN UINT8 SlaveAddress,
- IN UINT8 Offset,
- IN UINTN WriteBytes,
- IN UINT8 *WriteBuffer
- );
-
-#endif
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.inf b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.inf
deleted file mode 100644
index a78212a0e7..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.inf
+++ /dev/null
@@ -1,40 +0,0 @@
-## @file
-# Instance of I2C Library.
-#
-# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = I2CLibPei
- FILE_GUID = 8EF61509-890B-4FF2-B352-1C0E9CDDEC8B
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- LIBRARY_CLASS = LockBoxLib|PEIM
- CONSTRUCTOR = IntelI2CPeiLibConstructor
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64 EBC
-#
-
-[Sources.common]
- I2CLibPei.c
- I2CIoLibPei.c
-
-[LibraryClasses]
- TimerLib
-
-[PPIs]
- gEfiPeiStallPpiGuid
-
-
-[Packages]
- MdePkg/MdePkg.dec
- Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
-
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.c b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.c
deleted file mode 100644
index b99c3b0122..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/** @file
-
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-**/
-#include "PiPei.h"
-#include <Library/HobLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Guid/MemoryConfigData.h>
-#include <PlatformFspLib.h>
-
-EFI_STATUS
-PlatformHobCreateFromFsp (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- VOID *HobList
- )
-{
- VOID *HobData;
- VOID *NewHobData;
- UINTN DataSize;
-
- //
- // Other hob, todo: put this into FspWrapPlatformLib
- //
- if ((HobList = GetNextGuidHob (&gEfiMemoryConfigDataGuid, HobList)) != NULL) {
- HobData = GET_GUID_HOB_DATA (HobList);
- DataSize = GET_GUID_HOB_DATA_SIZE(HobList);
- DEBUG((EFI_D_ERROR, "gEfiMemoryConfigDataGuid Hob found: 0x%x.\n", DataSize));
-
- NewHobData = BuildGuidHob (&gEfiMemoryConfigDataGuid, DataSize);
- (*PeiServices)->CopyMem (
- NewHobData,
- HobData,
- DataSize
- );
- }
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf
deleted file mode 100644
index ddd97c5ad9..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-#
-# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-
-#
-#
-#
-#
-# FSP Platform HOB Library
-#
-#
-#
-##
-
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PlatformFspLib
- FILE_GUID = 1305A712-33A6-4fa7-BA59-AEAC3362931A
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PlatformFspLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64 EBC
-#
-
-[Sources]
- PlatformFspLib.c
-
-[Packages]
- MdePkg/MdePkg.dec
- IntelFrameworkPkg/IntelFrameworkPkg.dec
- Vlv2TbltDevicePkg/PlatformPkg.dec
- Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
- IntelFspWrapperPkg/IntelFspWrapperPkg.dec
-
-[LibraryClasses]
- BaseLib
- DebugLib
- HobLib
-
-[Guids]
- gEfiMemoryConfigDataGuid
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
deleted file mode 100644
index fe47e8f68d..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/** @file
- Header file of Serial port hardware definition.
-
- Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __PLATFORM_SERIAL_PORT_LIB_H_
-#define __PLATFORM_SERIAL_PORT_LIB_H_
-
-#include <Base.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/SerialPortLib.h>
-
-//
-// UART Register Offsets
-//
-#define BAUD_LOW_OFFSET 0x00
-#define BAUD_HIGH_OFFSET 0x01
-#define IER_OFFSET 0x01
-#define LCR_SHADOW_OFFSET 0x01
-#define FCR_SHADOW_OFFSET 0x02
-#define IR_CONTROL_OFFSET 0x02
-#define FCR_OFFSET 0x02
-#define EIR_OFFSET 0x02
-#define BSR_OFFSET 0x03
-#define LCR_OFFSET 0x03
-#define MCR_OFFSET 0x04
-#define LSR_OFFSET 0x05
-#define MSR_OFFSET 0x06
-
-//
-// UART Register Bit Defines
-//
-#define LSR_TXRDY 0x20
-#define LSR_RXDA 0x01
-#define DLAB 0x01
-
-#define UART_DATA 8
-#define UART_STOP 1
-#define UART_PARITY 0
-#define UART_BREAK_SET 0
-
-VOID
-InitializeSio (
- VOID
- );
-
-#endif
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
deleted file mode 100644
index f6012593d0..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/** @file
- Serial I/O Port library functions with no library constructor/destructor
-
- Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include "PlatformSerialPortLib.h"
-
-UINT16 gComBase = 0x3f8;
-UINTN gBps = 115200;
-UINT8 gData = 8;
-UINT8 gStop = 1;
-UINT8 gParity = 0;
-UINT8 gBreakSet = 0;
-
-/**
- Initialize Serial Port
-
- The Baud Rate Divisor registers are programmed and the LCR
- is used to configure the communications format. Hard coded
- UART config comes from globals in DebugSerialPlatform lib.
-
- @param None
-
- @retval None
-
-**/
-RETURN_STATUS
-EFIAPI
-UARTInitialize (
- VOID
- )
-{
- UINTN Divisor;
- UINT8 OutputData;
- UINT8 Data;
-
- //
- // Map 5..8 to 0..3
- //
- Data = (UINT8) (gData - (UINT8) 5);
-
- //
- // Calculate divisor for baud generator
- //
- Divisor = 115200 / gBps;
-
- //
- // Set communications format
- //
- OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
- IoWrite8 (gComBase + LCR_OFFSET, OutputData);
-
- //
- // Configure baud rate
- //
- IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8));
- IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff));
-
- //
- // Switch back to bank 0
- //
- OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
- IoWrite8 (gComBase + LCR_OFFSET, OutputData);
-
- return RETURN_SUCCESS;
-}
-
-/**
- Common function to initialize UART Serial device and USB Serial device.
-
- @param None
-
- @retval None
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortInitialize (
- VOID
- )
-{
-
- UARTInitialize ();
-
-
- return RETURN_SUCCESS;
-}
-
-/**
- Write data to serial device.
-
- If the buffer is NULL, then return 0;
- if NumberOfBytes is zero, then return 0.
-
- @param Buffer Point of data buffer which need to be writed.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
- @retval 0 Write data failed.
- @retval !0 Actual number of bytes writed to serial device.
-
-**/
-UINTN
-EFIAPI
-UARTDbgOut (
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
-)
-{
- UINTN Result;
- UINT8 Data;
-
- if (NULL == Buffer) {
- return 0;
- }
-
- Result = NumberOfBytes;
-
- while (NumberOfBytes--) {
- //
- // Wait for the serial port to be ready.
- //
- do {
- Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
- } while ((Data & LSR_TXRDY) == 0);
- IoWrite8 ((UINT16) PcdGet64 (PcdSerialRegisterBase), *Buffer++);
- }
-
- return Result;
-}
-
-/**
- Common function to write data to UART Serial device and USB Serial device.
-
- @param Buffer Point of data buffer which need to be writed.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
-**/
-UINTN
-EFIAPI
-SerialPortWrite (
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
-)
-{
- if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
- UARTDbgOut (Buffer, NumberOfBytes);
- }
-
- return RETURN_SUCCESS;
-}
-
-/**
- Read data from serial device and save the datas in buffer.
-
- If the buffer is NULL, then return 0;
- if NumberOfBytes is zero, then return 0.
-
- @param Buffer Point of data buffer which need to be writed.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
- @retval 0 Read data failed.
- @retval !0 Actual number of bytes raed to serial device.
-
-**/
-UINTN
-EFIAPI
-UARTDbgIn (
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
-)
-{
- UINTN Result;
- UINT8 Data;
-
- if (NULL == Buffer) {
- return 0;
- }
-
- Result = NumberOfBytes;
-
- while (NumberOfBytes--) {
- //
- // Wait for the serial port to be ready.
- //
- do {
- Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
- } while ((Data & LSR_RXDA) == 0);
-
- *Buffer++ = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase));
- }
-
- return Result;
-}
-
-/**
- Common function to Read data from UART serial device, USB serial device and save the datas in buffer.
-
- @param Buffer Point of data buffer which need to be writed.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
-**/
-UINTN
-EFIAPI
-SerialPortRead (
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
-)
-{
- if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
- UARTDbgIn (Buffer, NumberOfBytes);
- }
-
- return RETURN_SUCCESS;
-}
-
-
-/**
- Polls a serial device to see if there is any data waiting to be read.
-
- Polls aserial device to see if there is any data waiting to be read.
- If there is data waiting to be read from the serial device, then TRUE is returned.
- If there is no data waiting to be read from the serial device, then FALSE is returned.
-
- @retval TRUE Data is waiting to be read from the serial device.
- @retval FALSE There is no data waiting to be read from the serial device.
-
-**/
-BOOLEAN
-EFIAPI
-SerialPortPoll (
- VOID
- )
-{
- UINT8 Data;
-
- //
- // Read the serial port status.
- //
- Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
-
- return (BOOLEAN) ((Data & LSR_RXDA) != 0);
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf
deleted file mode 100644
index 0e7a6d3cfc..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf
+++ /dev/null
@@ -1,52 +0,0 @@
-#/** @file
-#
-# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-
-#
-#
-#
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = SerialPortLib
- FILE_GUID = 15B26F43-A389-4bae-BDE3-4BB0719B7D4F
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SerialPortLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64
-#
-
-[Sources]
- SerialPortLib.c
- SioInit.c
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- IntelFrameworkPkg/IntelFrameworkPkg.dec
- Vlv2TbltDevicePkg/PlatformPkg.dec
- Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
-
-[LibraryClasses]
- BaseLib
- PcdLib
- IoLib
- PciLib
- TimerLib
-
-[FixedPcd.common]
- gEfiSerialPortTokenSpaceGuid.PcdSerialBoudRate
- gEfiSerialPortTokenSpaceGuid.PcdSerialRegisterBase
-
-[FeaturePcd]
- gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial
- gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial
- gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c
deleted file mode 100644
index d9d48539dc..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/** @file
-
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-Module Name:
-
- SioInit.c
-
-Abstract:
-
- Functions for LpcSio initialization
-
---*/
-
-#include "PlatformSerialPortLib.h"
-#include "SioInit.h"
-
-typedef struct {
- UINT8 Register;
- UINT8 Value;
-} EFI_SIO_TABLE;
-
-EFI_SIO_TABLE mSioTableWpcn381u[] = {
- {0x29, 0x0A0},
- {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
- {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
- {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
- {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
- {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
- {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
- {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
- {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
- {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
- {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
- {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
- {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
- {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
- {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
- {0x21, 0x001}, // Global Device Enable
- {0x26, 0x000}
-};
-
-EFI_SIO_TABLE mSioTableWdcp376[] = {
- {0x29, 0x0A0},
- {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
- {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
- {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
- {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
- {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
- {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
- {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
- {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
- {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
- {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
- {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
- {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
- {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
- {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
- {0x21, 0x001}, // Global Device Enable
- {0x26, 0x000},
- {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K}, // Select PS2 Keyboard
- {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)}, // Set Base Address MSB
- {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)}, // Set Base Address LSB
- {WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)}, // Set Base Address MSB
- {WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)}, // Set Base Address LSB
- {WPCN381U_IRQ1_REGISTER, 0x011}, // Set to IRQ1
- {0xF0, (SIO_KBC_CLOCK << 6)}, // Select KBC Clock Source
- {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
- {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M}, // Select PS2 Mouse
- {WPCN381U_IRQ1_REGISTER, 0x01c}, // Set to IRQ12
- {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE} // Enable it with Activation bit
-};
-
-/**
- Initialization for SIO.
-
- @param FfsHeader FV this PEIM was loaded from.
- @param PeiServices General purpose services available to every PEIM.
-
- None
-
-**/
-VOID
-InitializeSio (
- VOID
- )
-{
- UINT16 Index;
- UINT16 IndexPort;
- UINT16 DataPort;
-
- //
- // Super I/O initialization for Winbond WPCN381U
- //
- IndexPort = WPCN381U_CONFIG_INDEX;
- DataPort = WPCN381U_CONFIG_DATA;
-
- //
- // Check for Winbond WPCN381U
- //
- IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER); // Winbond WPCN381U Device ID register is 0x20
-
- if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) { // Winbond WPCN381U Device ID is 0xF4
- //
- // Configure WPCN381U SIO
- //
- for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
- IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
- IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
- }
- }
-
- if (IoRead8 (DataPort) == WDCP376_CHIP_ID) { // Winbond WDCP376 Device ID is 0xF1
- //
- // Configure WDCP376 SIO
- //
- for (Index = 0; Index < sizeof (mSioTableWdcp376) / sizeof (EFI_SIO_TABLE); Index++) {
- IoWrite8 (IndexPort, mSioTableWdcp376[Index].Register);
- IoWrite8 (DataPort, mSioTableWdcp376[Index].Value);
- }
- }
- return;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
deleted file mode 100644
index 06fa19b93d..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/** @file
- Header file of Serial port hardware definition.
-
- Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _SIO_INIT_H_
-#define _SIO_INIT_H_
-
-#define WPCN381U_CONFIG_INDEX 0x2E
-#define WPCN381U_CONFIG_DATA 0x2F
-#define WPCN381U_CONFIG_INDEX1 0x164E
-#define WPCN381U_CONFIG_DATA1 0x164F
-#define WPCN381U_CHIP_ID 0xF4
-#define WDCP376_CHIP_ID 0xF1
-
-//
-// SIO Logical Devices Numbers
-//
-#define WPCN381U_LDN_UART0 0x03 // LDN for Serial Port Controller
-#define WPCN381U_LDN_UART1 0x02 // LDN for Parallel Port Controller
-#define WPCN381U_LDN_PS2K 0x06 // LDN for PS2 Keyboard Controller
-#define WPCN381U_LDN_PS2M 0x05 // LDN for PS2 Mouse Controller
-#define WPCN381U_KB_BASE1_ADDRESS 0x60 // Base Address of KB controller
-#define WPCN381U_KB_BASE2_ADDRESS 0x64 // Base Address of KB controller
-#define SIO_KBC_CLOCK 0x01 // 0/1/2 - 8/12/16 MHz KBC Clock Source
-#define WPCN381U_LDN_GPIO 0x07 // LDN for GPIO
-
-//
-// SIO Registers Layout
-//
-#define WPCN381U_LD_SEL_REGISTER 0x07 // Logical Device Select Register Address
-#define WPCN381U_DEV_ID_REGISTER 0x20 // Device Identification Register Address
-#define WPCN381U_ACTIVATE_REGISTER 0x30 // Device Identification Register Address
-#define WPCN381U_BASE1_HI_REGISTER 0x60 // Device BaseAddres Register #1 MSB Address
-#define WPCN381U_BASE1_LO_REGISTER 0x61 // Device BaseAddres Register #1 LSB Address
-#define WPCN381U_BASE2_HI_REGISTER 0x62 // Device BaseAddres Register #1 MSB Address
-#define WPCN381U_BASE2_LO_REGISTER 0x63 // Device Ba1eAddres Register #1 LSB Address
-#define WPCN381U_IRQ1_REGISTER 0x70 // Device IRQ Register #1 Address
-#define WPCN381U_IRQ2_REGISTER 0x71 // Device IRQ Register #2 Address
-
-//
-// SIO Activation Values
-//
-#define WPCN381U_ACTIVATE_VALUE 0x01 // Value to activate Device
-#define WPCN381U_DEACTIVATE_VALUE 0x00 // Value to deactivate Device
-
-//
-// SIO GPIO
-//
-#define WPCN381U_GPIO_BASE_ADDRESS 0x0A20 // SIO GPIO Base Address
-
-//
-// SIO Serial Port Settings
-//
-#define WPCN381U_SERIAL_PORT0_BASE_ADDRESS 0x03F8 // Base Address of Serial Port 0 (COMA / UART0)
-#define WPCN381U_SERIAL_PORT1_BASE_ADDRESS 0x02F8 // Base Address of Serial Port 1 (COMB / UART1)
-
-#endif
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.c b/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.c
deleted file mode 100644
index b1fb4adb34..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/** @file
-
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-Module Name:
-
-
- LegacyMetronome.c
-
-Abstract:
-
- This contains the installation function for the driver.
-
---*/
-
-#include "LegacyMetronome.h"
-
-//
-// Handle for the Metronome Architectural Protocol instance produced by this driver
-//
-EFI_HANDLE mMetronomeHandle = NULL;
-
-//
-// The Metronome Architectural Protocol instance produced by this driver
-//
-EFI_METRONOME_ARCH_PROTOCOL mMetronome = {
- WaitForTick,
- TICK_PERIOD
-};
-
-//
-// The CPU I/O Protocol used to access system hardware
-//
-EFI_CPU_IO_PROTOCOL *mCpuIo = NULL;
-
-//
-// Worker Functions
-//
-
-/**
- Write an 8 bit value to an I/O port and save it to the S3 script
-
- @param Port IO Port
- @param Data Data in IO Port
-
- @retval None.
-
-**/
-VOID
-ScriptWriteIo8 (
- UINT16 Port,
- UINT8 Data
- )
-{
- mCpuIo->Io.Write (
- mCpuIo,
- EfiCpuIoWidthUint8,
- Port,
- 1,
- &Data
- );
-
-}
-
-/**
-
- Read the refresh bit from the REFRESH_PORT
-
- @param None.
-
- @retval Refresh bit.
-
-**/
-UINT8
-ReadRefresh (
- VOID
- )
-{
- UINT8 Data;
-
- mCpuIo->Io.Read (
- mCpuIo,
- EfiCpuIoWidthUint8,
- REFRESH_PORT,
- 1,
- &Data
- );
- return (UINT8) (Data & REFRESH_ON);
-}
-
-/**
-
- Waits for the TickNumber of ticks from a known platform time source.
-
- @param This Pointer to the protocol instance.
- @param TickNumber Tick Number to be waited
-
-
- @retval EFI_SUCCESS If number of ticks occurred.
- @retval EFI_NOT_FOUND Could not locate CPU IO protocol
-
-**/
-EFI_STATUS
-EFIAPI
-WaitForTick (
- IN EFI_METRONOME_ARCH_PROTOCOL *This,
- IN UINT32 TickNumber
- )
-{
- //
- // Wait for TickNumber toggles of the Refresh bit
- //
- for (; TickNumber != 0x00; TickNumber--) {
- while (ReadRefresh () == REFRESH_ON)
- ;
- while (ReadRefresh () == REFRESH_OFF)
- ;
- }
-
- return EFI_SUCCESS;
-}
-
-//
-// Driver Entry Point
-//
-/**
- Install the LegacyMetronome driver. Loads a Metronome Arch Protocol based
- on the Port 61 timer.
-
- @param ImageHandle Handle for the image of this driver
- @param SystemTable Pointer to the EFI System Table
-
- @retval EFI_SUCCESS Metronome Architectural Protocol Installed
-
-**/
-EFI_STATUS
-EFIAPI
-InstallLegacyMetronome (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
-
- //
- // Make sure the Metronome Architectural Protocol is not already installed in the system
- //
- ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiMetronomeArchProtocolGuid);
-
- //
- // Get the CPU I/O Protocol that this driver requires
- // If the CPU I/O Protocol is not found, then ASSERT because the dependency expression
- // should guarantee that it is present in the handle database.
- //
- Status = gBS->LocateProtocol (
- &gEfiCpuIoProtocolGuid,
- NULL,
- (void **)&mCpuIo
- );
- ASSERT_EFI_ERROR (Status);
-
- //
- // Program port 61 timer 1 as refresh timer. We could use ACPI timer in the
- // future.
- //
- ScriptWriteIo8 (TIMER1_CONTROL_PORT, LOAD_COUNTER1_LSB);
- ScriptWriteIo8 (TIMER1_COUNT_PORT, COUNTER1_COUNT);
-
- //
- // Install on a new handle
- //
- Status = gBS->InstallMultipleProtocolInterfaces (
- &mMetronomeHandle,
- &gEfiMetronomeArchProtocolGuid,
- &mMetronome,
- NULL
- );
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.h b/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.h
deleted file mode 100644
index 9599eca702..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*++
-
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-Module Name:
-
- LegacyMetronome.h
-
-Abstract:
-
- Driver implementing the EFI 2.0 metronome protocol using the legacy PORT 61
- timer.
-
---*/
-
-#ifndef _LEGACY_METRONOME_H
-#define _LEGACY_METRONOME_H
-
-//
-// Statements that include other files
-//
-#include "Protocol/Metronome.h"
-#include "Protocol/CpuIo.h"
-#include "Library/DebugLib.h"
-#include "Library/UefiBootServicesTableLib.h"
-
-
-//
-// Private definitions
-//
-#define TICK_PERIOD 300
-#define REFRESH_PORT 0x61
-#define REFRESH_ON 0x10
-#define REFRESH_OFF 0x00
-#define TIMER1_CONTROL_PORT 0x43
-#define TIMER1_COUNT_PORT 0x41
-#define LOAD_COUNTER1_LSB 0x54
-#define COUNTER1_COUNT 0x12
-
-//
-// Function Prototypes
-//
-/**
- Waits for the TickNumber of ticks from a known platform time source.
-
- @param This Pointer to the protocol instance.
- @param TickNumber Tick Number to be waited
-
- @retval EFI_SUCCESS If number of ticks occurred.
- @retval EFI_NOT_FOUND Could not locate CPU IO protocol
-
-**/
-EFI_STATUS
-EFIAPI
-WaitForTick (
- IN EFI_METRONOME_ARCH_PROTOCOL *This,
- IN UINT32 TickNumber
- );
-
-#endif
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Metronome/Metronome.inf b/Platform/Intel/Vlv2TbltDevicePkg/Metronome/Metronome.inf
deleted file mode 100644
index 173370d652..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Metronome/Metronome.inf
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-#
-# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-
-#
-#
-
-# Module Name:
-#
-# LegacyMetronome.inf
-#
-# Abstract:
-#
-# Component description file for LegacyMetronome module
-#
-#--*/
-[defines]
- INF_VERSION = 0x00010005
- BASE_NAME = LegacyMetronome
- FILE_GUID = 07A9330A-F347-11d4-9A49-0090273FC14D
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = InstallLegacyMetronome
-
-[sources.common]
- LegacyMetronome.c
- LegacyMetronome.h
-
-[Packages]
- MdePkg/MdePkg.dec
- IntelFrameworkPkg/IntelFrameworkPkg.dec
-
-[LibraryClasses]
- UefiDriverEntryPoint
- UefiBootServicesTableLib
- DevicePathLib
- UefiLib
-
-[Protocols]
-
-gEfiMetronomeArchProtocolGuid
-gEfiCpuIoProtocolGuid
-
-[Depex]
-gEfiCpuIoProtocolGuid AND gEfiBootScriptSaveProtocolGuid
-
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.c b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.c
deleted file mode 100644
index 26599620ba..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/** @file
-
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-
-Module Name:
-
-
- SmmScriptSave.c
-
-Abstract:
-
- ScriptTableSave module at run time
-
---*/
-
-#include "SmmScriptSave.h"
-
-//
-// internal functions
-//
-
-EFI_STATUS
-BootScriptIoWrite (
- IN EFI_SMM_SCRIPT_TABLE *ScriptTable,
- IN VA_LIST Marker
- );
-
-EFI_STATUS
-BootScriptPciCfgWrite (
- IN EFI_SMM_SCRIPT_TABLE *ScriptTable,
- IN VA_LIST Marker
- );
-
-VOID
-SmmCopyMem (
- IN UINT8 *Destination,
- IN UINT8 *Source,
- IN UINTN ByteCount
- );
-
-//
-// Function implementations
-//
-EFI_STATUS
-SmmBootScriptWrite (
- IN OUT EFI_SMM_SCRIPT_TABLE *ScriptTable,
- IN UINTN Type,
- IN UINT16 OpCode,
- ...
- )
-{
- EFI_STATUS Status;
- VA_LIST Marker;
-
- if (ScriptTable == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Build script according to opcode
- //
- switch ( OpCode ) {
-
- case EFI_BOOT_SCRIPT_IO_WRITE_OPCODE:
- VA_START(Marker, OpCode);
- Status = BootScriptIoWrite (ScriptTable, Marker);
- VA_END(Marker);
- break;
-
- case EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE:
- VA_START(Marker, OpCode);
- Status = BootScriptPciCfgWrite(ScriptTable, Marker);
- VA_END(Marker);
- break;
-
- default:
- Status = EFI_SUCCESS;
- break;
- }
-
- return Status;
-}
-
-
-EFI_STATUS
-SmmBootScriptCreateTable (
- IN OUT EFI_SMM_SCRIPT_TABLE *ScriptTable,
- IN UINTN Type
- )
-{
- BOOT_SCRIPT_POINTERS Script;
- UINT8 *Buffer;
-
- if (ScriptTable == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- Buffer = (UINT8*) ((UINTN)(*ScriptTable));
-
- //
- // Fill Table Header
- //
- Script.Raw = Buffer;
- Script.TableInfo->OpCode = EFI_BOOT_SCRIPT_TABLE_OPCODE;
- Script.TableInfo->Length = sizeof(EFI_BOOT_SCRIPT_TABLE_HEADER);
- Script.TableInfo->TableLength = sizeof(EFI_BOOT_SCRIPT_TABLE_HEADER);
-
- //
- // Update current table pointer
- //
- *ScriptTable = *ScriptTable + sizeof(EFI_BOOT_SCRIPT_TABLE_HEADER);
- return EFI_SUCCESS;
-}
-
-
-EFI_STATUS
-SmmBootScriptCloseTable (
- IN EFI_SMM_SCRIPT_TABLE ScriptTableBase,
- IN EFI_SMM_SCRIPT_TABLE ScriptTablePtr,
- IN UINTN Type
- )
-{
- BOOT_SCRIPT_POINTERS Script;
-
- //
- // Add final "termination" node to script table
- //
- Script.Raw = (UINT8*) ((UINTN)ScriptTablePtr);
- Script.Terminate->OpCode = EFI_BOOT_SCRIPT_TERMINATE_OPCODE;
- Script.Terminate->Length = sizeof (EFI_BOOT_SCRIPT_TERMINATE);
- ScriptTablePtr += sizeof (EFI_BOOT_SCRIPT_TERMINATE);
-
-
- //
- // Update Table Header
- //
- Script.Raw = (UINT8*) ((UINTN)ScriptTableBase);
- Script.TableInfo->OpCode = EFI_BOOT_SCRIPT_TABLE_OPCODE;
- Script.TableInfo->Length = sizeof (EFI_BOOT_SCRIPT_TABLE_HEADER);
- Script.TableInfo->TableLength = (UINT32)(ScriptTablePtr - ScriptTableBase);
-
- return EFI_SUCCESS;
-}
-
-
-EFI_STATUS
-BootScriptIoWrite (
- IN EFI_SMM_SCRIPT_TABLE *ScriptTable,
- IN VA_LIST Marker
- )
-{
- BOOT_SCRIPT_POINTERS Script;
- EFI_BOOT_SCRIPT_WIDTH Width;
- UINTN Address;
- UINTN Count;
- UINT8 *Buffer;
- UINTN NodeLength;
- UINT8 WidthInByte;
-
- Width = VA_ARG(Marker, EFI_BOOT_SCRIPT_WIDTH);
- Address = VA_ARG(Marker, UINTN);
- Count = VA_ARG(Marker, UINTN);
- Buffer = VA_ARG(Marker, UINT8*);
-
- WidthInByte = (UINT8)(0x01 << (Width & 0x03));
- Script.Raw = (UINT8*) ((UINTN)(*ScriptTable));
- NodeLength = sizeof (EFI_BOOT_SCRIPT_IO_WRITE) + (WidthInByte * Count);
-
- //
- // Build script data
- //
- Script.IoWrite->OpCode = EFI_BOOT_SCRIPT_IO_WRITE_OPCODE;
- Script.IoWrite->Length = (UINT8)(NodeLength);
- Script.IoWrite->Width = Width;
- Script.IoWrite->Address = Address;
- Script.IoWrite->Count = (UINT32)Count;
- SmmCopyMem (
- (UINT8*)(Script.Raw + sizeof (EFI_BOOT_SCRIPT_IO_WRITE)),
- Buffer,
- WidthInByte * Count
- );
-
- //
- // Update Script table pointer
- //
- *ScriptTable = *ScriptTable + NodeLength;
- return EFI_SUCCESS;
-}
-
-
-EFI_STATUS
-BootScriptPciCfgWrite (
- IN EFI_SMM_SCRIPT_TABLE *ScriptTable,
- IN VA_LIST Marker
- )
-{
- BOOT_SCRIPT_POINTERS Script;
- EFI_BOOT_SCRIPT_WIDTH Width;
- UINT64 Address;
- UINTN Count;
- UINT8 *Buffer;
- UINTN NodeLength;
- UINT8 WidthInByte;
-
- Width = VA_ARG(Marker, EFI_BOOT_SCRIPT_WIDTH);
- Address = VA_ARG(Marker, UINT64);
- Count = VA_ARG(Marker, UINTN);
- Buffer = VA_ARG(Marker, UINT8*);
-
- WidthInByte = (UINT8)(0x01 << (Width & 0x03));
- Script.Raw = (UINT8*) ((UINTN)(*ScriptTable));
- NodeLength = sizeof (EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE) + (WidthInByte * Count);
-
- //
- // Build script data
- //
- Script.PciWrite->OpCode = EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE;
- Script.PciWrite->Length = (UINT8)(NodeLength);
- Script.PciWrite->Width = Width;
- Script.PciWrite->Address = Address;
- Script.PciWrite->Count = (UINT32)Count;
- SmmCopyMem (
- (UINT8*)(Script.Raw + sizeof (EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE)),
- Buffer,
- WidthInByte * Count
- );
-
- //
- // Update Script table pointer
- //
- *ScriptTable = *ScriptTable + NodeLength;
- return EFI_SUCCESS;
-}
-
-VOID
-SmmCopyMem (
- IN UINT8 *Destination,
- IN UINT8 *Source,
- IN UINTN ByteCount
- )
-{
- UINTN Index;
-
- for (Index = 0; Index < ByteCount; Index++, Destination++, Source++) {
- *Destination = *Source;
- }
-}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.h b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.h
deleted file mode 100644
index d3eca8cdc0..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*++
-
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-
-Module Name:
-
- SmmScriptSave.h
-
-Abstract:
-
- This is an implementation of the BootScript at run time.
-
---*/
-
-#ifndef _RUNTIME_SCRIPT_SAVE_H
-#define _RUNTIME_SCRIPT_SAVE_H
-
-#include "Efi.h"
-#include "EfiBootScript.h"
-
-
-typedef EFI_PHYSICAL_ADDRESS EFI_SMM_SCRIPT_TABLE;
-
-EFI_STATUS
-SmmBootScriptCreateTable (
- IN OUT EFI_SMM_SCRIPT_TABLE *ScriptTable,
- IN UINTN Type
- );
-
-EFI_STATUS
-SmmBootScriptWrite (
- IN OUT EFI_SMM_SCRIPT_TABLE *ScriptTable,
- IN UINTN Type,
- IN UINT16 OpCode,
- ...
- );
-
-EFI_STATUS
-SmmBootScriptCloseTable (
- IN EFI_SMM_SCRIPT_TABLE ScriptTableBase,
- IN EFI_SMM_SCRIPT_TABLE ScriptTablePtr,
- IN UINTN Type
- );
-
-#endif
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.c b/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.c
deleted file mode 100644
index 0dbd6f00e1..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.c
+++ /dev/null
@@ -1,459 +0,0 @@
-/** @file
- SMM SwDispatch2 Protocol on SMM SwDispatch Protocol Thunk driver.
-
- Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-**/
-
-#include <PiDxe.h>
-#include <FrameworkSmm.h>
-
-#include <Protocol/SmmSwDispatch2.h>
-#include <Protocol/SmmSwDispatch.h>
-#include <Protocol/SmmControl.h>
-#include <Protocol/SmmCpu.h>
-
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiDriverEntryPoint.h>
-#include <Library/SmmServicesTableLib.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-
-typedef struct {
- LIST_ENTRY Link;
- EFI_HANDLE DispatchHandle;
- UINTN SwSmiInputValue;
- UINTN DispatchFunction;
-} EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT;
-
-/**
- Register a child SMI source dispatch function for the specified software SMI.
-
- This service registers a function (DispatchFunction) which will be called when the software
- SMI source specified by RegisterContext->SwSmiCpuIndex is detected. On return,
- DispatchHandle contains a unique handle which may be used later to unregister the function
- using UnRegister().
-
- @param[in] This Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance.
- @param[in] DispatchFunction Function to register for handler when the specified software
- SMI is generated.
- @param[in, out] RegisterContext Pointer to the dispatch function's context.
- The caller fills this context in before calling
- the register function to indicate to the register
- function which Software SMI input value the
- dispatch function should be invoked for.
- @param[out] DispatchHandle Handle generated by the dispatcher to track the
- function instance.
-
- @retval EFI_SUCCESS The dispatch function has been successfully
- registered and the SMI source has been enabled.
- @retval EFI_DEVICE_ERROR The SW driver was unable to enable the SMI source.
- @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The SW SMI input value
- is not within valid range.
- @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or SMM) to manage this
- child.
- @retval EFI_OUT_OF_RESOURCES A unique software SMI value could not be assigned
- for this dispatch.
-**/
-EFI_STATUS
-EFIAPI
-SmmSwDispatch2Register (
- IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This,
- IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
- IN OUT EFI_SMM_SW_REGISTER_CONTEXT *RegisterContext,
- OUT EFI_HANDLE *DispatchHandle
- );
-
-/**
- Unregister a child SMI source dispatch function for the specified software SMI.
-
- This service removes the handler associated with DispatchHandle so that it will no longer be
- called in response to a software SMI.
-
- @param[in] This Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance.
- @param[in] DispatchHandle Handle of dispatch function to deregister.
-
- @retval EFI_SUCCESS The dispatch function has been successfully unregistered.
- @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid.
-**/
-EFI_STATUS
-EFIAPI
-SmmSwDispatch2UnRegister (
- IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This,
- IN EFI_HANDLE DispatchHandle
- );
-
-EFI_SMM_SW_DISPATCH2_PROTOCOL gSmmSwDispatch2 = {
- SmmSwDispatch2Register,
- SmmSwDispatch2UnRegister,
- 0 // MaximumSwiValue
-};
-
-EFI_SMM_SW_DISPATCH_PROTOCOL *mSmmSwDispatch;
-UINT8 mSmiTriggerRegister;
-UINT8 mSmiDataRegister;
-
-EFI_SMM_CPU_PROTOCOL *mSmmCpuProtocol;
-LIST_ENTRY mSmmSwDispatch2ThunkQueue = INITIALIZE_LIST_HEAD_VARIABLE (mSmmSwDispatch2ThunkQueue);
-
-/**
- This function find SmmSwDispatch2Context by SwSmiInputValue.
-
- @param SwSmiInputValue The SwSmiInputValue to indentify the SmmSwDispatch2 context
-
- @return SmmSwDispatch2 context
-**/
-EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *
-FindSmmSwDispatch2ContextBySwSmiInputValue (
- IN UINTN SwSmiInputValue
- )
-{
- LIST_ENTRY *Link;
- EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *ThunkContext;
-
- for (Link = mSmmSwDispatch2ThunkQueue.ForwardLink;
- Link != &mSmmSwDispatch2ThunkQueue;
- Link = Link->ForwardLink) {
- ThunkContext = BASE_CR (
- Link,
- EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT,
- Link
- );
- if (ThunkContext->SwSmiInputValue == SwSmiInputValue) {
- return ThunkContext;
- }
- }
- return NULL;
-}
-
-/**
- This function find SmmSwDispatch2Context by DispatchHandle.
-
- @param DispatchHandle The DispatchHandle to indentify the SmmSwDispatch2Thunk context
-
- @return SmmSwDispatch2Thunk context
-**/
-EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *
-FindSmmSwDispatch2ContextByDispatchHandle (
- IN EFI_HANDLE DispatchHandle
- )
-{
- LIST_ENTRY *Link;
- EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *ThunkContext;
-
- for (Link = mSmmSwDispatch2ThunkQueue.ForwardLink;
- Link != &mSmmSwDispatch2ThunkQueue;
- Link = Link->ForwardLink) {
- ThunkContext = BASE_CR (
- Link,
- EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT,
- Link
- );
- if (ThunkContext->DispatchHandle == DispatchHandle) {
- return ThunkContext;
- }
- }
- return NULL;
-}
-
-/**
- Framework dispatch function for a Software SMI handler.
-
- @param DispatchHandle The handle of this dispatch function.
- @param DispatchContext The pointer to the dispatch function's context.
- The SwSmiInputValue field is filled in
- by the software dispatch driver prior to
- invoking this dispatch function.
- The dispatch function will only be called
- for input values for which it is registered.
-
- @return None
-
-**/
-VOID
-EFIAPI
-FrameworkDispatchFunction (
- IN EFI_HANDLE DispatchHandle,
- IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
- )
-{
- EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *ThunkContext;
- EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction;
- EFI_SMM_SW_REGISTER_CONTEXT RegisterContext;
- EFI_SMM_SW_CONTEXT SwContext;
- UINTN Size;
- UINTN Index;
- EFI_SMM_SAVE_STATE_IO_INFO IoInfo;
- EFI_STATUS Status;
-
- //
- // Search context
- //
- ThunkContext = FindSmmSwDispatch2ContextBySwSmiInputValue (DispatchContext->SwSmiInputValue);
- ASSERT (ThunkContext != NULL);
- if (ThunkContext == NULL) {
- return ;
- }
-
- //
- // Construct new context
- //
- RegisterContext.SwSmiInputValue = DispatchContext->SwSmiInputValue;
- Size = sizeof(SwContext);
- SwContext.CommandPort = IoRead8 (mSmiTriggerRegister);
- SwContext.DataPort = IoRead8 (mSmiDataRegister);
-
- //
- // Try to find which CPU trigger SWSMI
- //
- SwContext.SwSmiCpuIndex = 0;
- for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
- Status = mSmmCpuProtocol->ReadSaveState (
- mSmmCpuProtocol,
- sizeof(IoInfo),
- EFI_SMM_SAVE_STATE_REGISTER_IO,
- Index,
- &IoInfo
- );
- if (EFI_ERROR (Status)) {
- continue;
- }
- if (IoInfo.IoPort == mSmiTriggerRegister) {
- //
- // Great! Find it.
- //
- SwContext.SwSmiCpuIndex = Index;
- break;
- }
- }
-
- //
- // Dispatch
- //
- DispatchFunction = (EFI_SMM_HANDLER_ENTRY_POINT2)ThunkContext->DispatchFunction;
- DispatchFunction (
- DispatchHandle,
- &RegisterContext,
- &SwContext,
- &Size
- );
- return ;
-}
-
-/**
- Register a child SMI source dispatch function for the specified software SMI.
-
- This service registers a function (DispatchFunction) which will be called when the software
- SMI source specified by RegisterContext->SwSmiCpuIndex is detected. On return,
- DispatchHandle contains a unique handle which may be used later to unregister the function
- using UnRegister().
-
- @param[in] This Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance.
- @param[in] DispatchFunction Function to register for handler when the specified software
- SMI is generated.
- @param[in, out] RegisterContext Pointer to the dispatch function's context.
- The caller fills this context in before calling
- the register function to indicate to the register
- function which Software SMI input value the
- dispatch function should be invoked for.
- @param[out] DispatchHandle Handle generated by the dispatcher to track the
- function instance.
-
- @retval EFI_SUCCESS The dispatch function has been successfully
- registered and the SMI source has been enabled.
- @retval EFI_DEVICE_ERROR The SW driver was unable to enable the SMI source.
- @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The SW SMI input value
- is not within valid range.
- @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or SMM) to manage this
- child.
- @retval EFI_OUT_OF_RESOURCES A unique software SMI value could not be assigned
- for this dispatch.
-**/
-EFI_STATUS
-EFIAPI
-SmmSwDispatch2Register (
- IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This,
- IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
- IN OUT EFI_SMM_SW_REGISTER_CONTEXT *RegisterContext,
- OUT EFI_HANDLE *DispatchHandle
- )
-{
- EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *ThunkContext;
- EFI_SMM_SW_DISPATCH_CONTEXT DispatchContext;
- EFI_STATUS Status;
- UINTN Index;
-
- if (RegisterContext->SwSmiInputValue == (UINTN)-1) {
- //
- // If SwSmiInputValue is set to (UINTN) -1 then a unique value will be assigned and returned in the structure.
- //
- Status = EFI_NOT_FOUND;
- for (Index = 1; Index < gSmmSwDispatch2.MaximumSwiValue; Index++) {
- DispatchContext.SwSmiInputValue = Index;
- Status = mSmmSwDispatch->Register (
- mSmmSwDispatch,
- FrameworkDispatchFunction,
- &DispatchContext,
- DispatchHandle
- );
- if (!EFI_ERROR (Status)) {
- RegisterContext->SwSmiInputValue = Index;
- break;
- }
- }
- if (RegisterContext->SwSmiInputValue == (UINTN)-1) {
- return EFI_OUT_OF_RESOURCES;
- }
- } else {
- DispatchContext.SwSmiInputValue = RegisterContext->SwSmiInputValue;
- Status = mSmmSwDispatch->Register (
- mSmmSwDispatch,
- FrameworkDispatchFunction,
- &DispatchContext,
- DispatchHandle
- );
- }
- if (!EFI_ERROR (Status)) {
- //
- // Register
- //
- Status = gSmst->SmmAllocatePool (
- EfiRuntimeServicesData,
- sizeof(*ThunkContext),
- (VOID **)&ThunkContext
- );
- ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR (Status)) {
- mSmmSwDispatch->UnRegister (mSmmSwDispatch, *DispatchHandle);
- return EFI_OUT_OF_RESOURCES;
- }
-
- ThunkContext->SwSmiInputValue = RegisterContext->SwSmiInputValue;
- ThunkContext->DispatchFunction = (UINTN)DispatchFunction;
- ThunkContext->DispatchHandle = *DispatchHandle;
- InsertTailList (&mSmmSwDispatch2ThunkQueue, &ThunkContext->Link);
- }
-
- return Status;
-}
-
-/**
- Unregister a child SMI source dispatch function for the specified software SMI.
-
- This service removes the handler associated with DispatchHandle so that it will no longer be
- called in response to a software SMI.
-
- @param[in] This Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance.
- @param[in] DispatchHandle Handle of dispatch function to deregister.
-
- @retval EFI_SUCCESS The dispatch function has been successfully unregistered.
- @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid.
-**/
-EFI_STATUS
-EFIAPI
-SmmSwDispatch2UnRegister (
- IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This,
- IN EFI_HANDLE DispatchHandle
- )
-{
- EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *ThunkContext;
- EFI_STATUS Status;
-
- Status = mSmmSwDispatch->UnRegister (mSmmSwDispatch, DispatchHandle);
- if (!EFI_ERROR (Status)) {
- //
- // Unregister
- //
- ThunkContext = FindSmmSwDispatch2ContextByDispatchHandle (DispatchHandle);
- ASSERT (ThunkContext != NULL);
- if (ThunkContext != NULL) {
- RemoveEntryList (&ThunkContext->Link);
- gSmst->SmmFreePool (ThunkContext);
- }
- }
-
- return Status;
-}
-
-/**
- Entry Point for this thunk driver.
-
- @param[in] ImageHandle Image handle of this driver.
- @param[in] SystemTable A Pointer to the EFI System Table.
-
- @retval EFI_SUCCESS The entry point is executed successfully.
- @retval other Some error occurred when executing this entry point.
-**/
-EFI_STATUS
-EFIAPI
-SmmSwDispatch2ThunkMain (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
- EFI_SMM_CONTROL_PROTOCOL *SmmControl;
- EFI_SMM_CONTROL_REGISTER RegisterInfo;
-
- //
- // Locate Framework SMM SwDispatch Protocol
- //
- Status = gBS->LocateProtocol (
- &gEfiSmmSwDispatchProtocolGuid,
- NULL,
- (VOID **)&mSmmSwDispatch
- );
- ASSERT_EFI_ERROR (Status);
- gSmmSwDispatch2.MaximumSwiValue = mSmmSwDispatch->MaximumSwiValue;
- if (gSmmSwDispatch2.MaximumSwiValue == 0x0) {
- DEBUG ((EFI_D_ERROR, "BUGBUG: MaximumSwiValue is 0, work-around to make it 0xFF\n"));
- gSmmSwDispatch2.MaximumSwiValue = 0xFF;
- }
-
- //
- // Locate Framework SMM Control Protocol
- //
- Status = gBS->LocateProtocol (
- &gEfiSmmControlProtocolGuid,
- NULL,
- (VOID **)&SmmControl
- );
-
- ASSERT_EFI_ERROR (Status);
- Status = SmmControl->GetRegisterInfo (
- SmmControl,
- &RegisterInfo
- );
- ASSERT_EFI_ERROR (Status);
- mSmiTriggerRegister = RegisterInfo.SmiTriggerRegister;
- mSmiDataRegister = RegisterInfo.SmiDataRegister;
-
- //
- // Locate PI SMM CPU protocol
- //
- Status = gSmst->SmmLocateProtocol (
- &gEfiSmmCpuProtocolGuid,
- NULL,
- (VOID **)&mSmmCpuProtocol
- );
- ASSERT_EFI_ERROR (Status);
-
- //
- // Publish PI SMM SwDispatch2 Protocol
- //
- ImageHandle = NULL;
- Status = gSmst->SmmInstallProtocolInterface (
- &ImageHandle,
- &gEfiSmmSwDispatch2ProtocolGuid,
- EFI_NATIVE_INTERFACE,
- &gSmmSwDispatch2
- );
- ASSERT_EFI_ERROR (Status);
- return Status;
-}
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf b/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
deleted file mode 100644
index 4f95fc281e..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
+++ /dev/null
@@ -1,54 +0,0 @@
-## @file
-# Component description file for SMM SwDispatch2 Protocol on SMM SwDispatch Protocol Thunk driver.
-#
-# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-
-#
-#
-#
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = SmmSwDispatch2OnSmmSwDispatchThunk
- FILE_GUID = 1410C6AC-9F4B-495b-9C23-8A5AEB0165E9
- MODULE_TYPE = DXE_SMM_DRIVER
- VERSION_STRING = 1.0
- PI_SPECIFICATION_VERSION = 0x0001000A
- ENTRY_POINT = SmmSwDispatch2ThunkMain
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64
-#
-
-[Sources]
- SmmSwDispatch2OnSmmSwDispatchThunk.c
-
-[Packages]
- MdePkg/MdePkg.dec
- IntelFrameworkPkg/IntelFrameworkPkg.dec
-
-[LibraryClasses]
- UefiDriverEntryPoint
- UefiBootServicesTableLib
- SmmServicesTableLib
- BaseLib
- IoLib
- DebugLib
-
-[Protocols]
- gEfiSmmControlProtocolGuid # PROTOCOL ALWAYS_CONSUMED
- gEfiSmmSwDispatchProtocolGuid # PROTOCOL ALWAYS_CONSUMED
- gEfiSmmCpuProtocolGuid # PROTOCOL ALWAYS_CONSUMED
- gEfiSmmSwDispatch2ProtocolGuid # PROTOCOL ALWAYS_PRODUCED
-
-[Depex]
- gEfiSmmSwDispatchProtocolGuid AND
- gEfiSmmControlProtocolGuid AND
- gEfiSmmCpuProtocolGuid
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c b/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c
deleted file mode 100644
index de257b35b5..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/** @file
- A helper driver to save information to SMRAM after SMRR is enabled.
-
- This driver is for ECP platforms.
-
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-
-
-**/
-
-#include <PiSmm.h>
-#include <Library/DebugLib.h>
-#include <Library/UefiDriverEntryPoint.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/SmmServicesTableLib.h>
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/IoLib.h>
-#include <Protocol/SmmSwDispatch.h>
-#include <Protocol/SmmReadyToLock.h>
-#include <Protocol/SmmControl.h>
-#include <Guid/Vlv2DeviceRefCodePkgTokenSpace.h>
-
-#define SMM_FROM_SMBASE_DRIVER 0x55
-#define SMM_FROM_CPU_DRIVER_SAVE_INFO 0x81
-
-#define EFI_SMRAM_CPU_NVS_HEADER_GUID \
- { \
- 0x429501d9, 0xe447, 0x40f4, 0x86, 0x7b, 0x75, 0xc9, 0x3a, 0x1d, 0xb5, 0x4e \
- }
-
-UINT8 mSmiDataRegister;
-BOOLEAN mLocked = FALSE;
-EFI_GUID mSmramCpuNvsHeaderGuid = EFI_SMRAM_CPU_NVS_HEADER_GUID;
-
-/**
- Dispatch function for a Software SMI handler.
-
- @param DispatchHandle The handle of this dispatch function.
- @param DispatchContext The pointer to the dispatch function's context.
- The SwSmiInputValue field is filled in
- by the software dispatch driver prior to
- invoking this dispatch function.
- The dispatch function will only be called
- for input values for which it is registered.
-
- @return None
-
-**/
-VOID
-EFIAPI
-SmramSaveInfoHandler (
- IN EFI_HANDLE DispatchHandle,
- IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
- )
-{
- ASSERT (DispatchContext != NULL);
- ASSERT (DispatchContext->SwSmiInputValue == SMM_FROM_SMBASE_DRIVER);
-
- if (!mLocked && IoRead8 (mSmiDataRegister) == SMM_FROM_CPU_DRIVER_SAVE_INFO) {
- CopyMem (
- (VOID *)(UINTN)(PcdGetEx64 (&gEfiVLVTokenSpaceGuid, PcdCpuLockBoxDataAddress)),
- (VOID *)(UINTN)(PcdGetEx64 (&gEfiVLVTokenSpaceGuid, PcdCpuSmramCpuDataAddress)),
- (UINTN)(PcdGetEx64 (&gEfiVLVTokenSpaceGuid, PcdCpuLockBoxSize))
- );
- }
-}
-
-/**
- Smm Ready To Lock event notification handler.
-
- It sets a flag indicating that SMRAM has been locked.
-
- @param[in] Protocol Points to the protocol's unique identifier.
- @param[in] Interface Points to the interface instance.
- @param[in] Handle The handle on which the interface was installed.
-
- @retval EFI_SUCCESS Notification handler runs successfully.
- **/
-EFI_STATUS
-EFIAPI
-SmmReadyToLockEventNotify (
- IN CONST EFI_GUID *Protocol,
- IN VOID *Interface,
- IN EFI_HANDLE Handle
- )
-{
- mLocked = TRUE;
- return EFI_SUCCESS;
-}
-
-/**
- Entry point function of this driver.
-
- @param[in] ImageHandle The firmware allocated handle for the EFI image.
- @param[in] SystemTable A pointer to the EFI System Table.
-
- @retval EFI_SUCCESS The entry point is executed successfully.
- @retval other Some error occurs when executing this entry point.
-**/
-EFI_STATUS
-EFIAPI
-SmramSaveInfoHandlerSmmMain (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
- EFI_SMM_SW_DISPATCH_PROTOCOL *SmmSwDispatch;
- EFI_SMM_SW_DISPATCH_CONTEXT SmmSwDispatchContext;
- EFI_HANDLE DispatchHandle;
- EFI_SMM_CONTROL_PROTOCOL *SmmControl;
- EFI_SMM_CONTROL_REGISTER SmmControlRegister;
- VOID *Registration;
-
- //
- // Get SMI data register
- //
- Status = SystemTable->BootServices->LocateProtocol (
- &gEfiSmmControlProtocolGuid,
- NULL,
- (VOID **)&SmmControl
- );
- ASSERT_EFI_ERROR (Status);
- Status = SmmControl->GetRegisterInfo (SmmControl, &SmmControlRegister);
- ASSERT_EFI_ERROR (Status);
- mSmiDataRegister = SmmControlRegister.SmiDataRegister;
-
- //
- // Register software SMI handler
- //
-
- Status = SystemTable->BootServices->LocateProtocol (
- &gEfiSmmSwDispatchProtocolGuid,
- NULL,
- (VOID **)&SmmSwDispatch
- );
- ASSERT_EFI_ERROR (Status);
-
- SmmSwDispatchContext.SwSmiInputValue = SMM_FROM_SMBASE_DRIVER;
- Status = SmmSwDispatch->Register (
- SmmSwDispatch,
- &SmramSaveInfoHandler,
- &SmmSwDispatchContext,
- &DispatchHandle
- );
- ASSERT_EFI_ERROR (Status);
-
- //
- // Register SMM Ready To Lock Protocol notification
- //
- Status = gSmst->SmmRegisterProtocolNotify (
- &gEfiSmmReadyToLockProtocolGuid,
- SmmReadyToLockEventNotify,
- &Registration
- );
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf b/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
deleted file mode 100644
index ec42c84472..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
+++ /dev/null
@@ -1,60 +0,0 @@
-## @file
-#
-# A helper driver to save information to SMRAM after SMRR is enabled.
-#
-# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-
-#
-#
-#
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = SmramSaveInfoHandlerSmm
- FILE_GUID = 63296C52-01CF-4eea-A47C-782A14DA6894
- MODULE_TYPE = DXE_SMM_DRIVER
- VERSION_STRING = 1.0
- PI_SPECIFICATION_VERSION = 0x0001000A
-
- ENTRY_POINT = SmramSaveInfoHandlerSmmMain
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64
-#
-
-[Sources.common]
- SmramSaveInfoHandlerSmm.c
-
-[Packages]
- MdePkg/MdePkg.dec
- IntelFrameworkPkg/IntelFrameworkPkg.dec
- Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
-
-[LibraryClasses]
- UefiDriverEntryPoint
- UefiRuntimeServicesTableLib
- SmmServicesTableLib
- BaseLib
- BaseMemoryLib
- IoLib
-
-[Protocols]
- gEfiSmmSwDispatchProtocolGuid ## CONSUMED
- gEfiSmmControlProtocolGuid ## CONSUMED
- gEfiSmmReadyToLockProtocolGuid ## CONSUMED
-
-[Pcd.common]
- gEfiVLVTokenSpaceGuid.PcdCpuLockBoxDataAddress
- gEfiVLVTokenSpaceGuid.PcdCpuSmramCpuDataAddress
- gEfiVLVTokenSpaceGuid.PcdCpuLockBoxSize
-
-[Depex]
- gEfiSmmSwDispatchProtocolGuid AND
- gEfiSmmControlProtocolGuid
-
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/Vacant.bin b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/Vacant.bin
deleted file mode 100644
index 12d359146014baad9277a951b237fd27e819db6e..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001
literal 3928064
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z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VK
zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM
z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VK
zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM
z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VK
zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM
z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VK
zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM
z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VK
zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM
z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VK
zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM
z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
rFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFz^EdVf>G}
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat
deleted file mode 100644
index 200ca05a23..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat
+++ /dev/null
@@ -1,270 +0,0 @@
- at REM @file
- at REM Windows batch file to build BIOS ROM
- at REM
- at REM Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
- at REM
- at REM SPDX-License-Identifier: BSD-2-Clause-Patent
- at REM
-
- at echo off
-SetLocal EnableDelayedExpansion EnableExtensions
-
-set PLATFORM_BIN_PACKAGE=%WORKSPACE%\Vlv2SocBinPkg
-if not exist %PLATFORM_BIN_PACKAGE% (
- if defined PACKAGES_PATH (
- for %%i IN (%PACKAGES_PATH%) DO (
- if exist %%~fi\Vlv2SocBinPkg (
- set PLATFORM_BIN_PACKAGE=%%~fi\Vlv2SocBinPkg
- goto PlatformBinPackageFound
- )
- )
- ) else (
- echo.
- echo !!! ERROR !!! Cannot find %PLATFORM_NAME% !!!
- echo.
- goto BldFail
- )
-)
-:PlatformBinPackageFound
-
-
-:: Set script defaults
-set exitCode=0
-set BackupRom=1
-set UpdateVBios=1
-set SpiLock=0
-set Stitch_Config=Stitch_Config.txt
-copy /y nul Stitching.log >nul
-
-:: Set default Suffix as: YYYY_MM_DD_HHMM
-set hour=%time: =0%
-reg copy "HKCU\Control Panel\International" "HKCU\Control Panel\International_Temp" /f >nul
-reg add "HKCU\Control Panel\International" /v sShortDate /d "yyyy_MM_dd" /f >nul
-for /f "tokens=1" %%i in ("%date%") do set today=%%i
-reg copy "HKCU\Control Panel\International_Temp" "HKCU\Control Panel\International" /f >nul
-reg delete "HKCU\Control Panel\International_Temp" /f >nul
-set IFWI_Suffix=%today%_%hour:~0,2%%time:~3,2%
-
-:: Process input arguments
-if "%~1"=="?" goto Usage
-if "%~1"=="/?" goto Usage
-if /i "%~1"=="Help" goto Usage
-
-:OptLoop
-if /i "%~1"=="/nV" (
- set UpdateVBios=0
- shift
- goto OptLoop
-)
-if /i "%~1"=="/nB" (
- set BackupRom=0
- shift
- goto OptLoop
-)
-if /i "%~1"=="/yL" (
- set SpiLock=1
- shift
- goto OptLoop
-)
-
-if /i "%~1"=="/B" (
- if "%~2"=="" goto Usage
- if not exist %~2 echo BIOS not found. & goto Usage
- set BIOS_Names=%~2
- set BIOS_File_Name=%~n2
- shift & shift
- goto OptLoop
-)
-if /i "%~1"=="/C" (
- if "%~2"=="" goto Usage
- if not exist %~2 echo ConfigFile not found. & goto Usage
- set Stitch_Config=%~2
- shift & shift
- goto OptLoop
-)
-if /i "%~1"=="/S" (
- if "%~2"=="" goto Usage
- set IFWI_Suffix=%~2
- shift & shift
- goto OptLoop
-)
-
-if "%BIOS_File_Name:~0,4%"=="MNW2" (
- set Stitch_Config= MNW2_Stitch_Config.txt
-)
-if "%BIOS_File_Name:~3,4%"=="MNW2" (
- set Stitch_Config= MNW2_Stitch_Config.txt
-)
-
-:: if no rom specified by user, search in ./ for ROM files
-if "%BIOS_Names%"=="" (
- set "BIOS_Names= "
- for /f "tokens=*" %%i in ('dir /b *.rom') do set BIOS_Names=!BIOS_Names! %%i
- if "!BIOS_Names!"==" " (
- echo NO .ROM files found !!!
- goto Usage
- )
-)
-
-:: Parse the Stitch_Config File
-if not exist %Stitch_Config% (
- echo Stitch Configuration File %Stitch_Config% not found.
- goto ScriptFail
-)
-for /f "delims== tokens=1,2" %%i in (%Stitch_Config%) do (
- if /i "%%i"=="HEADER" set IFWI_HEADER=%%j
- if /i "%%i"=="SEC_VERSION" set SEC_VERSION=%%j
- if /i "%%i"=="Source" (
- if /i "%%j"=="ALPHA" set Source_Prefix=A_
- if /i "%%j"=="BF" set Source_Prefix=BF_
- if /i "%%j"=="BE" set Source_Prefix=BE_
- if /i "%%j"=="PV" set Source_Prefix=PV_
- if /i "%%j"=="PR1" set Source_Prefix=PR1_
- )
-)
-
-if %SpiLock% EQU 1 (
- set IFWI_HEADER_FILE=IFWIHeader\!IFWI_HEADER!_SPILOCK.bin
-) else (
- set IFWI_HEADER_FILE=IFWIHeader\!IFWI_HEADER!.bin
-)
-
-:: **********************************************************************
-:: The Main Stitching Loop
-:: **********************************************************************
-echo %date% %time% >>Stitching.log 2>&1
-echo %date% %time%
-echo.
-for %%i in (%BIOS_Names%) do (
-
- REM ----- Do NOT use :: for comments Inside of code blocks() -------
- set BIOS_Rom=%%i
- set BIOS_Name=%%~ni
- set BIOS_Version=!BIOS_Name:~-7,7!
-
- REM extract PlatformType from BIOS filename
- set Platform_Type=!BIOS_Name:~0,4!
-
- REM Special treat for BayLake FFD8
- set Temp_Name=!BIOS_Name:~0,7!
-
-
- REM Capitalize and validate the Platform_Type
- if /i "!Platform_Type!"=="MNW2" (
- set Platform_Type=MNW2
- ) else (
- echo Error - Unsupported PlatformType: !Platform_Type!
- goto Usage
- )
-
-
- REM search BIOS_Name for Arch substring: either IA32 or X64
- if not "!BIOS_Name!"=="!BIOS_Name:_IA32_=!" (
- set Arch=IA32
- ) else if not "!BIOS_Name!"=="!BIOS_Name:_X64_=!" (
- set Arch=X64
- ) else (
- echo Error: Could not determine Architecture for !BIOS_Rom!
- goto Usage
- )
- set IFWI_Prefix=!Platform_Type!_IFWI_%Source_Prefix%!Arch!_!!BIOS_Version!
-
- REM search BIOS_Name for Build_Target substring: either R or D
- if not "!BIOS_Name!"=="!BIOS_Name:_R_=!" (
- set Build_Target=Release
- set IFWI_Prefix=!IFWI_Prefix!_R
- ) else if not "!BIOS_Name!"=="!BIOS_Name:_D_=!" (
- set Build_Target=Debug
- set IFWI_Prefix=!IFWI_Prefix!_D
- ) else (
- echo Error: Could not determine Build Target for !BIOS_Rom!
- goto Usage
- )
-
- REM Create a BIOS backup before Stitching
- if %BackupRom% EQU 1 (
- echo Creating backup of original BIOS rom.
- copy /y !BIOS_Rom! !BIOS_Rom!.orig >nul
- )
-
- echo. >>Stitching.log
- echo ********** Stitching !BIOS_Rom! ********** >>Stitching.log
- echo. >>Stitching.log
- echo.
- echo Stitching IFWI for !BIOS_Rom! ...
- echo ---------------------------------------------------------------------------
- echo IFWI Header: !IFWI_HEADER_FILE!, SEC version: !SEC_VERSION!,
- echo BIOS Version: !BIOS_Version!
-
- echo Platform Type: !Platform_Type!, IFWI Prefix: %BIOS_ID%
- echo ---------------------------------------------------------------------------
-
- echo -----------------------------
- echo.
- echo Generating IFWI... %BIOS_ID%.bin
- echo.
-
- copy /b/y !IFWI_HEADER_FILE! + %PLATFORM_BIN_PACKAGE%\SEC\!SEC_VERSION!\VLV_SEC_REGION.bin + %PLATFORM_BIN_PACKAGE%\SEC\!SEC_VERSION!\Vacant.bin + !BIOS_Rom! %BIOS_ID%.bin
- echo.
- echo ===========================================================================
-)
- at echo off
-
-::**********************************************************************
-:: end of main loop
-::**********************************************************************
-
-echo.
-echo -- All specified ROM files Stitched. --
-echo.
-goto Exit
-
-:Usage
-echo.
-echo **************************************************************************************************
-echo This Script is used to Stitch together BIOS, GOP Driver, Microcode Patch and TXE FW
-echo into a single Integrated Firmware Image (IFWI).
-echo.
-echo Usage: IFWIStitch.bat [flags] [/B BIOS.ROM] [/C Stitch_Config] [/S IFWI_Suffix]
-echo.
-echo This script has NO Required arguments, so that the user can just double click from the GUI.
-echo However, this requires that the BIOS.ROM file name is formatted correctly.
-echo.
-echo /nG Do NOT update the GOP driver. (applies to all ROM files for this run)
-echo /nV Do NOT update the VBIOS. (applies to all ROM files for this run)
-echo /nM Do NOT update the Microcode. (applies to all ROM files for this run)
-echo /nB Do NOT backup BIOS.ROMs. (Default will backup to BIOS.ROM.Orig)
-echo.
-echo BIOS.ROM: A single BIOS ROM file to use for stitching
-echo (DEFAULT: ALL .ROM files inside the current directory)
-echo Stitch_Config: Text file containing version info of each FW component
-echo (DEFAULT: Stitch_Config.txt)
-echo IFWI_Suffix: Suffix to append to the end of the IFWI filename
-echo (DEFAULT: YYYY_MM_DD_HHMM)
-echo.
-echo Examples:
-echo IFIWStitch.bat : Stitch all ROMs with defaults
-echo IFIWStitch.bat /B C:/MyRoms/testBIOS.rom : Stitch single ROM with defaults
-echo IFIWStitch.bat /B ../testBIOS.rom /S test123 : Stitch single ROM and add custom suffix
-echo IFIWStitch.bat /nM /nB /B testBIOS.rom /S test456 : Stitch single ROM, keep uCode from .rom,
-echo don't create backup, and add custom suffix.
-echo ****************************************************************************************************
-pause
-exit /b 1
-
-:ScriptFail
-set exitCode=1
-
-:Exit
-echo -- See Stitching.log for more info. --
-echo.
-echo %date% %time%
-echo.
-if "%Platform_Type%"=="MNW2" (
- echo .
-) else (
- echo only support MNW2 for this project!
-pause
-)
-exit /b %exitCode%
-EndLocal
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt
deleted file mode 100644
index 82abe6548f..0000000000
--- a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#
-
-HEADER=IFWI_HEADER
-SEC_VERSION=1.0.2.1060v5
-
--
2.21.0.windows.1
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