[edk2-devel] [edk2-platforms: Patch 6/8] Platform/Vlv2TbltDevicePkg: Import Vlv2TbltDevicePkg from edk2
Sun, Zailiang
zailiang.sun at intel.com
Mon May 13 02:52:17 UTC 2019
Reviewed-by: Zailiang Sun <zailiang.sun at intel.com>
> -----Original Message-----
> From: Kinney, Michael D
> Sent: Friday, May 10, 2019 11:35 AM
> To: devel at edk2.groups.io
> Cc: Sun, Zailiang <zailiang.sun at intel.com>; Qian, Yi <yi.qian at intel.com>;
> Kubacki, Michael A <michael.a.kubacki at intel.com>; Leif Lindholm
> <leif.lindholm at linaro.org>; Ard Biesheuvel <ard.biesheuvel at linaro.org>
> Subject: [edk2-platforms: Patch 6/8] Platform/Vlv2TbltDevicePkg: Import
> Vlv2TbltDevicePkg from edk2
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=1374
>
> Import Vlv2TbltDevicePkg from edk2/master.
>
> Cc: Zailiang Sun <zailiang.sun at intel.com>
> Cc: Yi Qian <yi.qian at intel.com>
> Cc: Michael Kubacki <michael.a.kubacki at intel.com>
> Cc: Leif Lindholm <leif.lindholm at linaro.org>
> Cc: Ard Biesheuvel <ard.biesheuvel at linaro.org>
> Signed-off-by: Michael D Kinney <michael.d.kinney at intel.com>
> ---
> Platform/Intel/Vlv2TbltDevicePkg/.gitignore | 5 +
> .../AcpiPlatform/AcpiPlatform.c | 1338 +++++
> .../AcpiPlatform/AcpiPlatform.h | 219 +
> .../AcpiPlatform/AcpiPlatform.inf | 89 +
> .../AcpiPlatform/AcpiPlatformHooks.c | 493 ++
> .../AcpiPlatform/AcpiPlatformHooks.h | 127 +
> .../AcpiPlatform/AcpiPlatformHooksLib.h | 91 +
> .../Vlv2TbltDevicePkg/AcpiPlatform/Osfr.h | 56 +
> .../FirmwareUpdate/FirmwareUpdate.c | 922 ++++
> .../FirmwareUpdate/FirmwareUpdate.h | 185 +
> .../FirmwareUpdate/FirmwareUpdate.inf | 83 +
> .../FirmwareUpdate/FirmwareUpdateStrings.uni | 45 +
> Platform/Intel/Vlv2TbltDevicePkg/BfmLib.exe | Bin 0 -> 499712 bytes
> Platform/Intel/Vlv2TbltDevicePkg/BiosIdD.env | 25 +
> Platform/Intel/Vlv2TbltDevicePkg/BiosIdR.env | 25 +
> .../Intel/Vlv2TbltDevicePkg/BiosIdx64D.env | 25 +
> .../Intel/Vlv2TbltDevicePkg/BiosIdx64R.env | 25 +
> .../BootScriptSaveDxe/BootScriptSaveDxe.inf | 60 +
> .../InternalBootScriptSave.h | 102 +
> .../BootScriptSaveDxe/ScriptSave.c | 626 +++
> .../Intel/Vlv2TbltDevicePkg/Build_IFWI.bat | 200 +
> .../Intel/Vlv2TbltDevicePkg/Build_IFWI.sh | 104 +
> Platform/Intel/Vlv2TbltDevicePkg/FCE.exe | Bin 0 -> 632832 bytes
> .../Capsule/GenerateCapsule/GenCapsuleAll.bat | 35 +
> .../Capsule/GenerateCapsule/GenCapsuleAll.sh | 28 +
> .../GenerateCapsule/GenCapsuleMinnowMax.bat | 131 +
> .../GenerateCapsule/GenCapsuleMinnowMax.sh | 65 +
> .../GenCapsuleMinnowMaxRelease.bat | 131 +
> .../GenCapsuleMinnowMaxRelease.sh | 65 +
> .../GenerateCapsule/GenCapsuleSampleColor.bat | 137 +
> .../GenerateCapsule/GenCapsuleSampleColor.sh | 70 +
> .../Feature/Capsule/GenerateCapsule/Lvfs.ddf | 14 +
> .../LvfsGenCapsuleMinnowMax.bat | 139 +
> .../LvfsGenCapsuleMinnowMaxRelease.bat | 139 +
> .../LvfsGenCapsuleSampleColor.bat | 145 +
> ...aceGuid.PcdFmpDevicePkcs7CertBufferXdr.inc | 1 +
> ...aceGuid.PcdFmpDevicePkcs7CertBufferXdr.inc | 1 +
> ...aceGuid.PcdFmpDevicePkcs7CertBufferXdr.inc | 1 +
> .../GenerateCapsule/template.metainfo.xml | 27 +
> .../Library/FmpDeviceLib/FmpDeviceLib.c | 589 +++
> .../Library/FmpDeviceLib/FmpDeviceLib.inf | 46 +
> .../Library/FmpDeviceLibSample/FmpDeviceLib.c | 412 ++
> .../FmpDeviceLibSample/FmpDeviceLib.inf | 34 +
> .../PlatformFlashAccessLib.c | 685 +++
> .../PlatformFlashAccessLib.inf | 54 +
> .../SystemFirmwareDescriptor.aslc | 83 +
> .../SystemFirmwareDescriptor.inf | 40 +
> .../SystemFirmwareDescriptorPei.c | 60 +
> .../SystemFirmwareUpdateConfig.ini | 66 +
> .../SystemFirmwareUpdateConfigGcc.ini | 66 +
> .../Vlv2TbltDevicePkg/FmpBlueSampleDevice.dsc | 55 +
> .../Vlv2TbltDevicePkg/FmpCertificate.dsc | 22 +
> .../FmpGreenSampleDevice.dsc | 55 +
> .../Vlv2TbltDevicePkg/FmpMinnowMaxSystem.dsc | 59 +
> .../Vlv2TbltDevicePkg/FmpRedSampleDevice.dsc | 55 +
> .../FspAzaliaConfigData/AzaliaConfig.bin | Bin 0 -> 3708 bytes
> .../FspSupport/BootModePei/BootModePei.c | 42 +
> .../FspSupport/BootModePei/BootModePei.inf | 40 +
> .../FspHobProcessLibVlv2.c | 421 ++
> .../FspHobProcessLibVlv2.inf | 74 +
> .../FspPlatformSecLibVlv2.c | 144 +
> .../FspPlatformSecLibVlv2.inf | 82 +
> .../Ia32/AsmSaveSecContext.asm | 45 +
> .../SecFspPlatformSecLibVlv2/Ia32/Fsp.inc | 45 +
> .../Ia32/PeiCoreEntry.asm | 135 +
> .../Ia32/SecEntry.asm | 338 ++
> .../SecFspPlatformSecLibVlv2/Ia32/Stack.S | 71 +
> .../SecFspPlatformSecLibVlv2/Ia32/Stack.asm | 76 +
> .../SecFspPlatformSecLibVlv2/PlatformInit.c | 36 +
> .../SecFspPlatformSecLibVlv2/SaveSecContext.c | 108 +
> .../SecGetPerformance.c | 83 +
> .../SecPlatformInformation.c | 77 +
> .../SecFspPlatformSecLibVlv2/SecRamInitData.c | 16 +
> .../SecTempRamSupport.c | 149 +
> .../SecFspPlatformSecLibVlv2/UartInit.c | 192 +
> .../Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.c | 68 +
> .../Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.inf | 49 +
> .../Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbInfo.c | 170 +
> .../FvbRuntimeDxe/FvbRuntimeDxe.inf | 80 +
> .../FvbRuntimeDxe/FvbService.c | 1098 ++++
> .../FvbRuntimeDxe/FvbService.h | 182 +
> .../FvbRuntimeDxe/FvbServiceDxe.c | 199 +
> .../FvbRuntimeDxe/FvbServiceSmm.c | 127 +
> .../FvbRuntimeDxe/FvbSmm.inf | 82 +
> .../FvbRuntimeDxe/FvbSmmCommon.h | 73 +
> .../FvbRuntimeDxe/FvbSmmDxe.c | 944 ++++
> .../FvbRuntimeDxe/FvbSmmDxe.h | 232 +
> .../FvbRuntimeDxe/FvbSmmDxe.inf | 50 +
> Platform/Intel/Vlv2TbltDevicePkg/GenBiosId | Bin 0 -> 12236 bytes
> .../Intel/Vlv2TbltDevicePkg/GenBiosId.exe | Bin 0 -> 384000 bytes
> .../Include/AlertStandardFormatTable.h | 122 +
> .../Vlv2TbltDevicePkg/Include/ChipsetAccess.h | 28 +
> .../Include/CommonIncludes.h | 115 +
> .../Intel/Vlv2TbltDevicePkg/Include/CpuType.h | 59 +
> .../Vlv2TbltDevicePkg/Include/FileHandleLib.h | 499 ++
> .../Include/Guid/AcpiTableStorage.h | 30 +
> .../Include/Guid/AlertStandardFormat.h | 86 +
> .../Vlv2TbltDevicePkg/Include/Guid/BiosId.h | 30 +
> .../Include/Guid/BoardFeatures.h | 214 +
> .../Include/Guid/EfiVpdData.h | 156 +
> .../Include/Guid/FirmwareId.h | 61 +
> .../Include/Guid/HwWatchdogTimerHob.h | 134 +
> .../Vlv2TbltDevicePkg/Include/Guid/IdccData.h | 104 +
> .../Vlv2TbltDevicePkg/Include/Guid/ItkData.h | 70 +
> .../Include/Guid/MemoryConfigData.h | 32 +
> .../Include/Guid/OsSelection.h | 85 +
> .../Include/Guid/PciLanInfo.h | 39 +
> .../Include/Guid/PlatformCpuInfo.h | 180 +
> .../Include/Guid/PlatformInfo.h | 433 ++
> .../Include/Guid/SensorInfoVariable.h | 279 +
> .../Include/Guid/SetupVariable.h | 1344 +++++
> .../Intel/Vlv2TbltDevicePkg/Include/Hpet.h | 40 +
> .../Include/Library/BiosIdLib.h | 104 +
> .../Include/Library/CpuIA32.h | 345 ++
> .../Include/Library/EfiRegTableLib.h | 196 +
> .../Vlv2TbltDevicePkg/Include/Library/Esrt.h | 74 +
> .../Vlv2TbltDevicePkg/Include/Library/Fd.h | 264 +
> .../Include/Library/FlashDeviceLib.h | 122 +
> .../Include/Library/I2CLib.h | 58 +
> .../Include/Library/I2cMmioConfigLib.h | 23 +
> .../Include/Library/I2cPort_platform.h | 26 +
> .../Include/Library/PlatformFsaLib.h | 50 +
> .../Include/Library/PlatformFspLib.h | 23 +
> .../Include/Library/SpiFlash.H | 239 +
> .../Include/Library/StallSmmLib.h | 40 +
> .../Include/Library/UsbDeviceModeLib.h | 181 +
> .../Intel/Vlv2TbltDevicePkg/Include/Mcfg.h | 69 +
> .../Vlv2TbltDevicePkg/Include/McfgTable.h | 65 +
> .../Vlv2TbltDevicePkg/Include/Platform.h | 133 +
> .../Include/PlatformBootMode.h | 35 +
> .../Include/PlatformDefinitions.h | 43 +
> .../Include/Ppi/MfgMemoryTest.h | 42 +
> .../Include/Ppi/Sha256Hash.h | 131 +
> .../Vlv2TbltDevicePkg/Include/Ppi/Speaker.h | 65 +
> .../Include/Ppi/UsbController.h | 85 +
> .../Include/Protocol/CK505ClockPlatformInfo.h | 126 +
> .../Include/Protocol/EnhancedSpeedstep.h | 76 +
> .../Include/Protocol/GlobalNvsArea.h | 475 ++
> .../Include/Protocol/HwWatchdogTimer.h | 235 +
> .../Include/Protocol/I2cAcpi.h | 107 +
> .../Include/Protocol/I2cBus.h | 164 +
> .../Include/Protocol/I2cBusMcg.h | 163 +
> .../Include/Protocol/I2cHostMcg.h | 138 +
> .../Include/Protocol/I2cMasterMcg.h | 519 ++
> .../Include/Protocol/I2cSlave.h | 194 +
> .../Include/Protocol/LpcWpc83627Policy.h | 92 +
> .../Include/Protocol/LpcWpce791Policy.h | 55 +
> .../Include/Protocol/MmioDevice.h | 84 +
> .../Include/Protocol/Observable.h | 186 +
> .../Include/Protocol/PlatformGopPolicy.h | 68 +
> .../Include/Protocol/PlatformIdeInit.h | 43 +
> .../Include/Protocol/SetupMode.h | 79 +
> .../Include/Protocol/SmbiosSlotPopulation.h | 47 +
> .../Include/Protocol/Speaker.h | 65 +
> .../Include/Protocol/TcoReset.h | 67 +
> .../Include/Protocol/TpmMp.h | 136 +
> .../Include/Protocol/UsbPolicy.h | 126 +
> .../Include/Protocol/VlvPlatformPolicy.h | 102 +
> .../Vlv2TbltDevicePkg/Include/SetupMode.h | 85 +
> .../IntelGopDepex/IntelGopDriver.depex | 1 +
> .../Library/BiosIdLib/BiosIdLib.c | 337 ++
> .../Library/BiosIdLib/BiosIdLib.inf | 50 +
> .../Library/CpuIA32Lib/CpuIA32Lib.inf | 41 +
> .../Library/CpuIA32Lib/EfiCpuVersion.c | 70 +
> .../Library/CpuIA32Lib/IA32/CpuIA32.S | 223 +
> .../Library/CpuIA32Lib/IA32/CpuIA32.asm | 206 +
> .../Library/CpuIA32Lib/IA32/CpuIA32.c | 177 +
> .../Library/CpuIA32Lib/X64/Cpu.S | 207 +
> .../Library/CpuIA32Lib/X64/Cpu.asm | 222 +
> .../Library/EfiRegTableLib/EfiRegTableLib.c | 282 ++
> .../Library/EfiRegTableLib/EfiRegTableLib.inf | 47 +
> .../Library/FlashDeviceLib/FlashDeviceLib.c | 461 ++
> .../Library/FlashDeviceLib/FlashDeviceLib.inf | 44 +
> .../FlashDeviceLib/FlashDeviceLibDxe.c | 56 +
> .../FlashDeviceLib/FlashDeviceLibDxe.inf | 43 +
> .../FlashDeviceLibDxeRuntimeSmm.c | 173 +
> .../FlashDeviceLib/SpiChipDefinitions.h | 835 +++
> .../Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c | 46 +
> .../Library/I2CLib/I2CLibNull.inf | 39 +
> .../Library/I2CLibDxe/I2CLib.c | 735 +++
> .../Library/I2CLibDxe/I2CLibDxe.inf | 39 +
> .../Library/I2CLibDxe/I2CRegs.h | 126 +
> .../Library/I2CLibPei/I2CAccess.h | 44 +
> .../Library/I2CLibPei/I2CDelayPei.c | 46 +
> .../Library/I2CLibPei/I2CDelayPei.h | 30 +
> .../Library/I2CLibPei/I2CIoLibPei.c | 178 +
> .../Library/I2CLibPei/I2CIoLibPei.h | 153 +
> .../Library/I2CLibPei/I2CLibPei.c | 638 +++
> .../Library/I2CLibPei/I2CLibPei.h | 280 +
> .../Library/I2CLibPei/I2CLibPei.inf | 40 +
> .../IntelPchAcpiTimerLib/CommonHeader.h | 27 +
> .../IntelPchAcpiTimerLib.c | 255 +
> .../IntelPchAcpiTimerLib.inf | 51 +
> .../BoardClkGens/BoardClkGens.c | 430 ++
> .../BoardClkGens/BoardClkGens.h | 255 +
> .../MultiPlatformLib/BoardGpios/BoardGpios.c | 531 ++
> .../MultiPlatformLib/BoardGpios/BoardGpios.h | 324 ++
> .../BoardJumpers/BoardJumpers.c | 30 +
> .../BoardJumpers/BoardJumpers.h | 30 +
> .../BoardOemIds/BoardOemIds.c | 43 +
> .../BoardOemIds/BoardOemIds.h | 29 +
> .../BoardSsidSvid/BoardSsidSvid.c | 38 +
> .../BoardSsidSvid/BoardSsidSvid.h | 35 +
> .../MultiPlatformLib/MultiPlatformLib.c | 120 +
> .../MultiPlatformLib/MultiPlatformLib.h | 89 +
> .../MultiPlatformLib/MultiPlatformLib.inf | 77 +
> .../MultiPlatformLib/PlatformInfoHob.c | 54 +
> .../Library/PchPlatformLib/PchPlatformLib.inf | 50 +
> .../PchPlatformLib/PchPlatformLibrary.c | 131 +
> .../PchPlatformLib/PchPlatformLibrary.h | 35 +
> .../Library/PchSmmLib/CommonHeader.h | 32 +
> .../Library/PchSmmLib/PchSmmLib.c | 157 +
> .../Library/PchSmmLib/PchSmmLib.inf | 46 +
> .../Library/PlatformBdsLib/BdsPlatform.c | 3098 ++++++++++++
> .../Library/PlatformBdsLib/BdsPlatform.h | 516 ++
> .../Library/PlatformBdsLib/PlatformBdsLib.inf | 127 +
> .../PlatformBdsLib/PlatformBdsStrings.uni | 30 +
> .../Library/PlatformBdsLib/PlatformData.c | 306 ++
> .../Library/PlatformCmosLib/PlatformCmosLib.c | 106 +
> .../PlatformCmosLib/PlatformCmosLib.inf | 30 +
> .../Library/PlatformFspLib/PlatformFspLib.c | 44 +
> .../Library/PlatformFspLib/PlatformFspLib.inf | 49 +
> .../Library/ResetSystemLib/ResetSystemLib.c | 235 +
> .../Library/ResetSystemLib/ResetSystemLib.inf | 47 +
> .../SerialPortLib/PlatformSerialPortLib.h | 53 +
> .../Library/SerialPortLib/SerialPortLib.c | 246 +
> .../Library/SerialPortLib/SerialPortLib.inf | 52 +
> .../Library/SerialPortLib/SioInit.c | 127 +
> .../Library/SerialPortLib/SioInit.h | 62 +
> .../Library/SmbusLib/CommonHeader.h | 26 +
> .../Library/SmbusLib/SmbusLib.c | 873 ++++
> .../Library/SmbusLib/SmbusLib.inf | 46 +
> .../Library/StallSmmLib/StallSmm.c | 89 +
> .../Library/StallSmmLib/StallSmmLib.inf | 51 +
> .../Tpm2DeviceLibSeCDxe/Tpm2DeviceLibSeC.c | 117 +
> .../Tpm2DeviceLibSeCDxe/Tpm2DeviceLibSeC.inf | 61 +
> .../Tpm2DeviceLibSeCPei/Tpm2DeviceLibSeC.c | 145 +
> .../Tpm2DeviceLibSeCPei/Tpm2DeviceLibSeC.inf | 60 +
> .../Intel/Vlv2TbltDevicePkg/Logo/Logo.bmp | Bin 0 -> 94434 bytes
> .../Metronome/LegacyMetronome.c | 185 +
> .../Metronome/LegacyMetronome.h | 64 +
> .../Vlv2TbltDevicePkg/Metronome/Metronome.inf | 49 +
> .../MonoStatusCode/EfiStatusCode.h | 178 +
> .../MonoStatusCode/MonoStatusCode.c | 132 +
> .../MonoStatusCode/MonoStatusCode.h | 128 +
> .../MonoStatusCode/MonoStatusCode.inf | 72 +
> .../MonoStatusCode/PeiPostCode.c | 121 +
> .../MonoStatusCode/PlatformStatusCode.c | 381 ++
> .../MonoStatusCode/PlatformStatusCode.h | 138 +
> .../Library/GenericBdsLib/BdsBoot.c | 4490 +++++++++++++++++
> .../Library/GenericBdsLib/BdsConnect.c | 429 ++
> .../Library/GenericBdsLib/BdsConsole.c | 1061 ++++
> .../Library/GenericBdsLib/BdsMisc.c | 1575 ++++++
> .../Library/GenericBdsLib/DevicePath.c | 27 +
> .../Library/GenericBdsLib/GenericBdsLib.inf | 142 +
> .../Library/GenericBdsLib/GenericBdsLib.uni | 19 +
> .../GenericBdsLib/GenericBdsStrings.uni | 30 +
> .../Library/GenericBdsLib/InternalBdsLib.h | 173 +
> .../Library/GenericBdsLib/String.c | 26 +
> .../Library/GenericBdsLib/String.h | 42 +
> .../PciPlatform/BoardPciPlatform.c | 55 +
> .../PciPlatform/PciPlatform.c | 367 ++
> .../PciPlatform/PciPlatform.h | 83 +
> .../PciPlatform/PciPlatform.inf | 65 +
> .../Vlv2TbltDevicePkg/PlatformCapsule.dsc | 39 +
> .../Vlv2TbltDevicePkg/PlatformCapsule.fdf | 52 +
> .../Vlv2TbltDevicePkg/PlatformCapsuleGcc.dsc | 38 +
> .../Vlv2TbltDevicePkg/PlatformCapsuleGcc.fdf | 52 +
> .../PlatformCpuInfoDxe/PlatformCpuInfoDxe.c | 60 +
> .../PlatformCpuInfoDxe/PlatformCpuInfoDxe.h | 29 +
> .../PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf | 55 +
> .../PlatformDxe/AzaliaVerbTable.h | 247 +
> .../Vlv2TbltDevicePkg/PlatformDxe/BoardId.c | 223 +
> .../PlatformDxe/BoardIdDecode.c | 129 +
> .../PlatformDxe/BoardIdDecode.h | 61 +
> .../PlatformDxe/ClockControl.c | 202 +
> .../PlatformDxe/Configuration.h | 692 +++
> .../Intel/Vlv2TbltDevicePkg/PlatformDxe/ExI.c | 89 +
> .../PlatformDxe/IchPlatformPolicy.c | 484 ++
> .../PlatformDxe/IchRegTable.c | 134 +
> .../PlatformDxe/IchTcoReset.c | 211 +
> .../Vlv2TbltDevicePkg/PlatformDxe/IdccInfo.c | 72 +
> .../PlatformDxe/LegacySpeaker.c | 161 +
> .../PlatformDxe/LegacySpeaker.h | 69 +
> .../PlatformDxe/Observable/Observable.c | 582 +++
> .../PlatformDxe/Observable/Observable.h | 137 +
> .../Vlv2TbltDevicePkg/PlatformDxe/PciBus.h | 379 ++
> .../Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c | 506 ++
> .../Vlv2TbltDevicePkg/PlatformDxe/Platform.c | 1820 +++++++
> .../PlatformDxe/PlatformDxe.h | 722 +++
> .../PlatformDxe/PlatformDxe.inf | 149 +
> .../Intel/Vlv2TbltDevicePkg/PlatformDxe/Rtc.c | 154 +
> .../Vlv2TbltDevicePkg/PlatformDxe/SensorVar.c | 112 +
> .../PlatformDxe/SioPlatformPolicy.c | 82 +
> .../PlatformDxe/SlotConfig.c | 148 +
> .../PlatformDxe/SlotConfig.h | 80 +
> .../PlatformGopPolicy/PlatformGopPolicy.c | 201 +
> .../PlatformGopPolicy/PlatformGopPolicy.inf | 51 +
> .../PlatformInfoDxe/PlatformInfoDxe.c | 169 +
> .../PlatformInfoDxe/PlatformInfoDxe.h | 30 +
> .../PlatformInfoDxe/PlatformInfoDxe.inf | 52 +
> .../PlatformInitPei/BootMode.c | 434 ++
> .../PlatformInitPei/CpuInitPeim.c | 44 +
> .../Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c | 319 ++
> .../PlatformInitPei/FlashMap.c | 143 +
> .../PlatformInitPei/LegacySpeaker.c | 168 +
> .../PlatformInitPei/LegacySpeaker.h | 71 +
> .../PlatformInitPei/MchInit.c | 72 +
> .../PlatformInitPei/MemoryCallback.c | 338 ++
> .../PlatformInitPei/MemoryPeim.c | 408 ++
> .../PlatformInitPei/PchInitPeim.c | 808 +++
> .../PlatformInitPei/PlatformEarlyInit.c | 1195 +++++
> .../PlatformInitPei/PlatformEarlyInit.h | 1499 ++++++
> .../PlatformInitPei/PlatformInfoInit.c | 181 +
> .../PlatformInitPei/PlatformInitPei.inf | 117 +
> .../PlatformInitPei/PlatformSsaInitPeim.c | 58 +
> .../PlatformInitPei/Recovery.c | 361 ++
> .../Vlv2TbltDevicePkg/PlatformInitPei/Stall.c | 91 +
> .../Vlv2TbltDevicePkg/PlatformPei/BootMode.c | 346 ++
> .../PlatformPei/CommonHeader.h | 60 +
> .../PlatformPei/MemoryCallback.c | 154 +
> .../Vlv2TbltDevicePkg/PlatformPei/Platform.c | 1198 +++++
> .../Vlv2TbltDevicePkg/PlatformPei/Platform.h | 213 +
> .../PlatformPei/PlatformPei.inf | 129 +
> .../Vlv2TbltDevicePkg/PlatformPei/Stall.c | 90 +
> .../Intel/Vlv2TbltDevicePkg/PlatformPkg.dec | 211 +
> .../Intel/Vlv2TbltDevicePkg/PlatformPkg.fdf | 1073 ++++
> .../Vlv2TbltDevicePkg/PlatformPkgConfig.dsc | 107 +
> .../Vlv2TbltDevicePkg/PlatformPkgGcc.fdf | 1033 ++++
> .../Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc | 1711 +++++++
> .../Vlv2TbltDevicePkg/PlatformPkgIA32.dsc | 1699 +++++++
> .../Vlv2TbltDevicePkg/PlatformPkgX64.dsc | 1714 +++++++
> .../PlatformSetupDxe/Boot.vfi | 72 +
> .../PlatformSetupDxe/Configuration.h | 56 +
> .../PlatformSetupDxe/DebugConfig.vfi | 118 +
> .../PlatformSetupDxe/FwVersionStrings.uni | 40 +
> .../PlatformSetupDxe/Main.vfi | 331 ++
> .../PlatformSetupDxe/PlatformSetupDxe.c | 929 ++++
> .../PlatformSetupDxe/PlatformSetupDxe.h | 97 +
> .../PlatformSetupDxe/PlatformSetupDxe.inf | 141 +
> .../PlatformSetupDxe/Security.vfi | 104 +
> .../PlatformSetupDxe/SetupFunctions.c | 85 +
> .../PlatformSetupDxe/SetupInfoRecords.c | 1855 +++++++
> .../PlatformSetupDxe/SouthClusterConfig.vfi | 933 ++++
> .../PlatformSetupDxe/SystemComponent.vfi | 81 +
> .../PlatformSetupDxe/Thermal.vfi | 106 +
> .../PlatformSetupDxe/UnCore.vfi | 235 +
> .../PlatformSetupDxe/UqiList.uni | 452 ++
> .../PlatformSetupDxe/Vfr.vfr | 123 +
> .../PlatformSetupDxe/VfrStrings.uni | 1417 ++++++
> .../Vlv2TbltDevicePkg/PlatformSmm/Platform.c | 997 ++++
> .../PlatformSmm/PlatformSmm.inf | 93 +
> .../Vlv2TbltDevicePkg/PlatformSmm/S3Save.c | 377 ++
> .../PlatformSmm/SmmPlatform.h | 240 +
> .../PlatformSmm/SmmScriptSave.c | 252 +
> .../PlatformSmm/SmmScriptSave.h | 50 +
> .../Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.c | 148 +
> .../Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.h | 36 +
> .../Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.inf | 49 +
> Platform/Intel/Vlv2TbltDevicePkg/Readme.md | 233 +
> .../SaveMemoryConfig/SaveMemoryConfig.c | 181 +
> .../SaveMemoryConfig/SaveMemoryConfig.h | 66 +
> .../SaveMemoryConfig/SaveMemoryConfig.inf | 60 +
> .../SmBiosMiscDxe/CommonHeader.h | 39 +
> .../MiscBaseBoardManufacturer.uni | 33 +
> .../MiscBaseBoardManufacturerData.c | 58 +
> .../MiscBaseBoardManufacturerFunction.c | 238 +
> .../SmBiosMiscDxe/MiscBiosVendor.uni | 26 +
> .../SmBiosMiscDxe/MiscBiosVendorData.c | 101 +
> .../SmBiosMiscDxe/MiscBiosVendorFunction.c | 336 ++
> .../SmBiosMiscDxe/MiscBootInformationData.c | 34 +
> .../MiscBootInformationFunction.c | 82 +
> .../SmBiosMiscDxe/MiscChassisManufacturer.uni | 28 +
> .../MiscChassisManufacturerData.c | 57 +
> .../MiscChassisManufacturerFunction.c | 158 +
> .../SmBiosMiscDxe/MiscMemoryDevice.uni | 35 +
> .../SmBiosMiscDxe/MiscMemoryDeviceData.c | 45 +
> .../SmBiosMiscDxe/MiscMemoryDeviceFunction.c | 319 ++
> .../MiscNumberOfInstallableLanguagesData.c | 38 +
> ...MiscNumberOfInstallableLanguagesFunction.c | 251 +
> .../SmBiosMiscDxe/MiscOemString.uni | 25 +
> .../SmBiosMiscDxe/MiscOemStringData.c | 34 +
> .../SmBiosMiscDxe/MiscOemStringFunction.c | 89 +
> .../SmBiosMiscDxe/MiscOemType0x90.uni | 31 +
> .../SmBiosMiscDxe/MiscOemType0x90Data.c | 36 +
> .../SmBiosMiscDxe/MiscOemType0x90Function.c | 442 ++
> .../SmBiosMiscDxe/MiscOemType0x94.uni | 42 +
> .../SmBiosMiscDxe/MiscOemType0x94Data.c | 54 +
> .../SmBiosMiscDxe/MiscOemType0x94Function.c | 1218 +++++
> .../SmBiosMiscDxe/MiscOnboardDevice.uni | 26 +
> .../SmBiosMiscDxe/MiscOnboardDeviceData.c | 48 +
> .../SmBiosMiscDxe/MiscOnboardDeviceFunction.c | 135 +
> .../SmBiosMiscDxe/MiscPhysicalArray.uni | 25 +
> .../SmBiosMiscDxe/MiscPhysicalArrayData.c | 38 +
> .../SmBiosMiscDxe/MiscPhysicalArrayFunction.c | 101 +
> .../MiscPortInternalConnectorDesignator.uni | 31 +
> .../MiscPortInternalConnectorDesignatorData.c | 56 +
> ...cPortInternalConnectorDesignatorFunction.c | 152 +
> .../SmBiosMiscDxe/MiscProcessorCache.uni | 22 +
> .../SmBiosMiscDxe/MiscProcessorCacheData.c | 33 +
> .../MiscProcessorCacheFunction.c | 189 +
> .../MiscProcessorInformation.uni | 27 +
> .../MiscProcessorInformationData.c | 71 +
> .../MiscProcessorInformationFunction.c | 448 ++
> .../SmBiosMiscDxe/MiscResetCapabilitiesData.c | 43 +
> .../MiscResetCapabilitiesFunction.c | 85 +
> .../SmBiosMiscDxe/MiscSubclassDriver.h | 188 +
> .../SmBiosMiscDxe/MiscSubclassDriver.uni | 35 +
> .../MiscSubclassDriverDataTable.c | 98 +
> .../MiscSubclassDriverEntryPoint.c | 182 +
> .../MiscSystemLanguageString.uni | 24 +
> .../MiscSystemLanguageStringData.c | 34 +
> .../MiscSystemLanguageStringFunction.c | 93 +
> .../SmBiosMiscDxe/MiscSystemManufacturer.uni | 30 +
> .../MiscSystemManufacturerData.c | 48 +
> .../MiscSystemManufacturerFunction.c | 364 ++
> .../SmBiosMiscDxe/MiscSystemOptionString.uni | 24 +
> .../MiscSystemOptionStringData.c | 31 +
> .../MiscSystemOptionStringFunction.c | 93 +
> .../MiscSystemSlotDesignation.uni | 34 +
> .../MiscSystemSlotDesignationData.c | 246 +
> .../MiscSystemSlotDesignationFunction.c | 127 +
> .../SmBiosMiscDxe/SmBiosMiscDxe.inf | 139 +
> .../SmmSwDispatch2OnSmmSwDispatchThunk.c | 459 ++
> .../SmmSwDispatch2OnSmmSwDispatchThunk.inf | 54 +
> .../SmramSaveInfoHandlerSmm.c | 164 +
> .../SmramSaveInfoHandlerSmm.inf | 60 +
> .../Stitch/Gcc/NvStorageFtwSpare.bin | Bin 0 -> 262144 bytes
> .../Stitch/Gcc/NvStorageFtwWorking.bin | Bin 0 -> 8192 bytes
> .../Stitch/Gcc/NvStorageVariable.bin | Bin 0 -> 253952 bytes
> .../Stitch/IFWIHeader/IFWI_HEADER.bin | Bin 0 -> 4096 bytes
> .../Stitch/IFWIHeader/IFWI_HEADER_SPILOCK.bin | Bin 0 -> 4096 bytes
> .../Stitch/IFWIHeader/Vacant.bin | Bin 0 -> 3928064 bytes
> .../Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat | 270 +
> .../Stitch/MNW2_Stitch_Config.txt | 10 +
> .../Intel/Vlv2TbltDevicePkg/UiApp/FrontPage.c | 33 +
> .../Intel/Vlv2TbltDevicePkg/UiApp/UiApp.inf | 32 +
> .../VlvPlatformInitDxe/IgdOpRegion.c | 929 ++++
> .../VlvPlatformInitDxe/IgdOpRegion.h | 235 +
> .../VlvPlatformInitDxe/VlvPlatformInit.c | 287 ++
> .../VlvPlatformInitDxe/VlvPlatformInit.h | 65 +
> .../VlvPlatformInitDxe/VlvPlatformInitDxe.inf | 74 +
> .../Vlv2TbltDevicePkg/Wpce791/LpcDriver.c | 340 ++
> .../Vlv2TbltDevicePkg/Wpce791/LpcDriver.h | 112 +
> .../Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.c | 366 ++
> .../Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.h | 103 +
> .../Intel/Vlv2TbltDevicePkg/Wpce791/LpcSio.c | 126 +
> .../Intel/Vlv2TbltDevicePkg/Wpce791/LpcSio.h | 101 +
> .../Vlv2TbltDevicePkg/Wpce791/Wpce791.inf | 63 +
> Platform/Intel/Vlv2TbltDevicePkg/bld_vlv.bat | 332 ++
> Platform/Intel/Vlv2TbltDevicePkg/bld_vlv.sh | 256 +
> Platform/Intel/Vlv2TbltDevicePkg/cln.sh | 62 +
> 452 files changed, 95411 insertions(+)
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/.gitignore
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooksLib.h
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/Osfr.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareU
> pdate.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareU
> pdate.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareU
> pdate.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareU
> pdateStrings.uni
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/BfmLib.exe
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/BiosIdD.env
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/BiosIdR.env
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/BiosIdx64D.env
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/BiosIdx64R.env
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptSav
> e.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Build_IFWI.bat
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Build_IFWI.sh
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FCE.exe
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/GenC
> apsuleAll.bat
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/GenC
> apsuleAll.sh
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/GenC
> apsuleMinnowMax.bat
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/GenC
> apsuleMinnowMax.sh
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/GenC
> apsuleMinnowMaxRelease.bat
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/GenC
> apsuleMinnowMaxRelease.sh
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/GenC
> apsuleSampleColor.bat
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/GenC
> apsuleSampleColor.sh
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs.d
> df
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/LvfsG
> enCapsuleMinnowMax.bat
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/LvfsG
> enCapsuleMinnowMaxRelease.bat
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/LvfsG
> enCapsuleSampleColor.bat
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/NewR
> oot.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferXdr.i
> nc
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/SAMP
> LE_DEVELOPMENT.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7
> CertBufferXdr.inc
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/SAMP
> LE_DEVELOPMENT_SAMPLE_PRODUCTION.cer.gFmpDevicePkgTokenSpace
> Guid.PcdFmpDevicePkcs7CertBufferXdr.inc
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/templ
> ate.metainfo.xml
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib/F
> mpDeviceLib.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib/F
> mpDeviceLib.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLibSa
> mple/FmpDeviceLib.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLibSa
> mple/FmpDeviceLib.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/PlatformFlashAc
> cessLib/PlatformFlashAccessLib.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/PlatformFlashAc
> cessLib/PlatformFlashAccessLib.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescrip
> tor/SystemFirmwareDescriptor.aslc
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescrip
> tor/SystemFirmwareDescriptor.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescrip
> tor/SystemFirmwareDescriptorPei.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpdate
> Config/SystemFirmwareUpdateConfig.ini
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpdate
> Config/SystemFirmwareUpdateConfigGcc.ini
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FmpBlueSampleDevice.dsc
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/FmpCertificate.dsc
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FmpGreenSampleDevice.dsc
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FmpMinnowMaxSystem.dsc
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FmpRedSampleDevice.dsc
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.
> c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.i
> nf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLib
> Vlv2/FspHobProcessLibVlv2.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLib
> Vlv2/FspHobProcessLibVlv2.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/FspPlatformSecLibVlv2.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/FspPlatformSecLibVlv2.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/Ia32/AsmSaveSecContext.asm
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/Ia32/Fsp.inc
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/Ia32/PeiCoreEntry.asm
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/Ia32/SecEntry.asm
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/Ia32/Stack.S
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/Ia32/Stack.asm
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/PlatformInit.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/SaveSecContext.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/SecGetPerformance.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/SecPlatformInformation.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/SecRamInitData.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/SecTempRamSupport.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLib
> Vlv2/UartInit.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbInfo.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbRuntimeDxe.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceDxe.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceSmm.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmm.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmCommon.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.inf
> create mode 100755 Platform/Intel/Vlv2TbltDevicePkg/GenBiosId
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/GenBiosId.exe
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/ChipsetAccess.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/CommonIncludes.h
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Include/CpuType.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/FileHandleLib.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/BiosId.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/IdccData.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/ItkData.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Include/Hpet.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/CpuIA32.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/Esrt.h
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Include/Library/Fd.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2CLib.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Include/Mcfg.h
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Include/McfgTable.h
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Include/Platform.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/PlatformBootMode.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/PlatformDefinitions.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/Speaker.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/UsbController.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformInfo.
> h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/Observable.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/Speaker.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Include/SetupMode.h
> create mode 100644
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> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/EfiCpuVersion.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.asm
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> Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.S
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.asm
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> Platform/Intel/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c
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> Platform/Intel/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.inf
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> Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibDxe.
> c
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> Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibDxe.
> inf
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> Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibDxe
> RuntimeSmm.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitions.
> h
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> Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
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> Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLib.c
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> Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLibDxe.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CRegs.h
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> Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CAccess.h
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> create mode 100644
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> Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.c
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> Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/CommonHe
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> Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpi
> TimerLib.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpi
> TimerLib.inf
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> oardClkGens.c
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> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/B
> oardClkGens.h
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> rdGpios.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/Boa
> rdGpios.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/B
> oardJumpers.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/B
> oardJumpers.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/B
> oardOemIds.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/B
> oardOemIds.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/B
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> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/B
> oardSsidSvid.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib
> .c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib
> .h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib
> .inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/PlatformInfoHob
> .c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf
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> y.c
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> Platform/Intel/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrar
> y.h
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> Platform/Intel/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.inf
> create mode 100644
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> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsString
> s.uni
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> Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformData.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLi
> b.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLi
> b.inf
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> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.i
> nf
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> Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib
> .h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
> create mode 100644
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> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmm.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmmLib.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2Devic
> eLibSeC.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2Devic
> eLibSeC.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2Devic
> eLibSeC.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2Devic
> eLibSeC.inf
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> create mode 100644
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> Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.inf
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> create mode 100644
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> create mode 100644
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> create mode 100644
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> create mode 100644
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> ary/GenericBdsLib/BdsConsole.c
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> create mode 100644
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> ary/GenericBdsLib/DevicePath.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Libr
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> create mode 100644
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> ary/GenericBdsLib/GenericBdsLib.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Libr
> ary/GenericBdsLib/GenericBdsStrings.uni
> create mode 100644
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> create mode 100644
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> create mode 100644
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> create mode 100644
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> create mode 100644
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> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf
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> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsule.fdf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsuleGcc.dsc
> create mode 100644
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> create mode 100644
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> .c
> create mode 100644
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> .h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoDxe
> .inf
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> create mode 100644
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> Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf
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> Platform/Intel/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.
> h
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> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorData.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorFunction.
> c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationDat
> a.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationFun
> ction.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturer
> .uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturer
> Data.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturer
> Function.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDevice.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceData.
> c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceFunct
> ion.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstallable
> LanguagesData.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstallable
> LanguagesFunction.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemString.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringData.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringFunction.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Data.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Functi
> on.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Data.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Functi
> on.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDevice.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceData.
> c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceFunct
> ion.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArray.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayData.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayFunctio
> n.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnect
> orDesignator.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnect
> orDesignatorData.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnect
> orDesignatorFunction.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCache.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheData.
> c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheFunc
> tion.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformatio
> n.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformatio
> nData.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformatio
> nFunction.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesDat
> a.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesFun
> ction.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverDataT
> able.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverEntryP
> oint.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageStri
> ng.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageStri
> ngData.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageStri
> ngFunction.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacture
> r.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacture
> rData.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacture
> rFunction.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionString.
> uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionString
> Data.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStringF
> unction.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignati
> on.uni
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignati
> onData.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignati
> onFunction.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThun
> k/SmmSwDispatch2OnSmmSwDispatchThunk.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThun
> k/SmmSwDispatch2OnSmmSwDispatchThunk.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveI
> nfoHandlerSmm.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveI
> nfoHandlerSmm.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwSpare.bin
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwWorking.bin
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageVariable.bin
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER.bin
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER_SPILOC
> K.bin
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/Vacant.bin
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/UiApp/FrontPage.c
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/UiApp/UiApp.inf
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcDriver.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcDriver.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.c
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.h
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcSio.c
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcSio.h
> create mode 100644
> Platform/Intel/Vlv2TbltDevicePkg/Wpce791/Wpce791.inf
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/bld_vlv.bat
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/bld_vlv.sh
> create mode 100644 Platform/Intel/Vlv2TbltDevicePkg/cln.sh
>
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/.gitignore
> b/Platform/Intel/Vlv2TbltDevicePkg/.gitignore
> new file mode 100644
> index 0000000000..c7698262ad
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/.gitignore
> @@ -0,0 +1,5 @@
> +AutoPlatformCFG.txt
> +Stitch/Stitching.log
> +Stitch/MNW*.bin
> +Stitch/MNW*.rom
> +Stitch/MNW*.rom.orig
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c
> b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c
> new file mode 100644
> index 0000000000..5c03f66edb
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c
> @@ -0,0 +1,1338 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
> +
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +
> +
> +
> +Module Name:
> +
> + AcpiPlatform.c
> +
> +Abstract:
> +
> + ACPI Platform Driver
> +
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <Protocol/TcgService.h>
> +#include <Protocol/FirmwareVolume2.h>
> +#include "AcpiPlatform.h"
> +#include "AcpiPlatformHooks.h"
> +#include "AcpiPlatformHooksLib.h"
> +#include "Platform.h"
> +#include <Hpet.h>
> +#include <Mcfg.h>
> +#include "Osfr.h"
> +#include <Guid/GlobalVariable.h>
> +#include <Guid/SetupVariable.h>
> +#include <Guid/PlatformInfo.h>
> +#include <Protocol/CpuIo.h>
> +#include <Guid/BoardFeatures.h>
> +#include <Protocol/AcpiSupport.h>
> +#include <Protocol/AcpiS3Save.h>
> +#include <Protocol/Ps2Policy.h>
> +#include <Library/CpuIA32.h>
> +#include <SetupMode.h>
> +#include <Guid/AcpiTableStorage.h>
> +#include <Guid/EfiVpdData.h>
> +#include <PchAccess.h>
> +#include <Guid/Vlv2Variable.h>
> +#include <Guid/PlatformCpuInfo.h>
> +#include <IndustryStandard/WindowsSmmSecurityMitigationTable.h>
> +
> +
> +CHAR16 EfiPlatformCpuInfoVariable[] = L"PlatformCpuInfo";
> +CHAR16 gACPIOSFRModelStringVariableName[] =
> ACPI_OSFR_MODEL_STRING_VARIABLE_NAME;
> +CHAR16 gACPIOSFRRefDataBlockVariableName[] =
> ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME;
> +CHAR16 gACPIOSFRMfgStringVariableName[] =
> ACPI_OSFR_MFG_STRING_VARIABLE_NAME;
> +
> +EFI_CPU_IO_PROTOCOL *mCpuIo;
> +EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
> +#ifndef __GNUC__
> +#pragma optimize("", off)
> +#endif
> +BOOLEAN mFirstNotify;
> +EFI_PLATFORM_INFO_HOB *mPlatformInfo;
> +EFI_GUID mSystemConfigurationGuid =
> SYSTEM_CONFIGURATION_GUID;
> +SYSTEM_CONFIGURATION mSystemConfiguration;
> +SYSTEM_CONFIGURATION mSystemConfig;
> +
> +UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
> +UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) /
> sizeof( mSmbusRsvdAddresses[0] );
> +
> +/**
> + Locate the first instance of a protocol. If the protocol requested is an
> + FV protocol, then it will return the first FV that contains the ACPI table
> + storage file.
> +
> + @param[in] Protocol The protocol to find.
> + @param[in] Instance Return pointer to the first instance of the
> protocol.
> + @param[in] Type The type of protocol to locate.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> + @retval EFI_NOT_FOUND The protocol could not be located.
> + @retval EFI_OUT_OF_RESOURCES There are not enough resources to
> find the protocol.
> +
> +**/
> +EFI_STATUS
> +LocateSupportProtocol (
> + IN EFI_GUID *Protocol,
> + OUT VOID **Instance,
> + IN UINT32 Type
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE *HandleBuffer;
> + UINTN NumberOfHandles;
> + EFI_FV_FILETYPE FileType;
> + UINT32 FvStatus;
> + EFI_FV_FILE_ATTRIBUTES Attributes;
> + UINTN Size;
> + UINTN Index;
> +
> + FvStatus = 0;
> +
> + //
> + // Locate protocol.
> + //
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + Protocol,
> + NULL,
> + &NumberOfHandles,
> + &HandleBuffer
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + // Defined errors at this time are not found and out of resources.
> + //
> + return Status;
> + }
> +
> + //
> + // Looking for FV with ACPI storage file.
> + //
> + for (Index = 0; Index < NumberOfHandles; Index++) {
> + //
> + // Get the protocol on this handle.
> + // This should not fail because of LocateHandleBuffer.
> + //
> + Status = gBS->HandleProtocol (
> + HandleBuffer[Index],
> + Protocol,
> + Instance
> + );
> + ASSERT (!EFI_ERROR (Status));
> +
> + if (!Type) {
> + //
> + // Not looking for the FV protocol, so find the first instance of the
> + // protocol. There should not be any errors because our handle buffer
> + // should always contain at least one or LocateHandleBuffer would have
> + // returned not found.
> + //
> + break;
> + }
> +
> + //
> + // See if it has the ACPI storage file.
> + //
> + Status = ((EFI_FIRMWARE_VOLUME_PROTOCOL *) (*Instance))-
> >ReadFile (
> + *Instance,
> + &gEfiAcpiTableStorageGuid,
> + NULL,
> + &Size,
> + &FileType,
> + &Attributes,
> + &FvStatus
> + );
> +
> + //
> + // If we found it, then we are done.
> + //
> + if (!EFI_ERROR (Status)) {
> + break;
> + }
> + }
> +
> + //
> + // Our exit status is determined by the success of the previous operations.
> + // If the protocol was found, Instance already points to it.
> + //
> + //
> + // Free any allocated buffers.
> + //
> + gBS->FreePool (HandleBuffer);
> +
> + return Status;
> +}
> +
> +/**
> + This function will update any runtime platform specific information.
> + This currently includes:
> + Setting OEM table values, ID, table ID, creator ID and creator revision.
> + Enabling the proper processor entries in the APIC tables.
> +
> + @param[in] Table The table to update.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +
> +**/
> +EFI_STATUS
> +PlatformUpdateTables (
> + IN OUT EFI_ACPI_COMMON_HEADER *Table
> + )
> +{
> + EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
> + UINT8 *CurrPtr;
> + UINT8 *EndPtr;
> + ACPI_APIC_STRUCTURE_PTR *ApicPtr;
> + UINT8 CurrProcessor;
> + EFI_STATUS Status;
> + EFI_MP_SERVICES_PROTOCOL *MpService;
> + UINTN MaximumNumberOfCPUs;
> + UINTN NumberOfEnabledCPUs;
> + UINTN BspIndex;
> + EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE *AsfEntry;
> + EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER
> *HpetTbl;
> + UINT64 OemIdValue;
> + UINT8 Index;
> + EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *Facp;
> + EFI_ACPI_OSFR_TABLE *OsfrTable;
> + EFI_ACPI_OSFR_OCUR_OBJECT *pOcurObject;
> + EFI_ACPI_OSFR_OCUR_OBJECT OcurObject =
> {{0xB46F133D, 0x235F, 0x4634, 0x9F, 0x03, 0xB1, 0xC0, 0x1C, 0x54, 0x78, 0x5B},
> 0, 0, 0, 0, 0};
> + CHAR16 *OcurMfgStringBuffer = NULL;
> + CHAR16 *OcurModelStringBuffer = NULL;
> + UINT8 *OcurRefDataBlockBuffer = NULL;
> + UINTN OcurMfgStringBufferSize;
> + UINTN OcurModelStringBufferSize;
> + UINTN OcurRefDataBlockBufferSize;
> +#if defined (IDCC2_SUPPORTED) && IDCC2_SUPPORTED
> + EFI_ACPI_ASPT_TABLE *pSpttTable;
> +#endif
> + UINT16 NumberOfHpets;
> + UINT16 HpetCapIdValue;
> + UINT32 HpetBlockID;
> + EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer;
> + UINT8 TempVal;
> + EFI_ACPI_3_0_IO_APIC_STRUCTURE *IOApicType;
> + EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER
> *APICTableHeader;
> + EFI_ACPI_WSMT_TABLE *WsmtTable;
> +
> + CurrPtr = NULL;
> + EndPtr = NULL;
> + ApicPtr = NULL;
> + CurrProcessor = 0;
> +
> +
> + if (Table->Signature !=
> EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) {
> + TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
> + //
> + // Update the OEMID.
> + //
> + OemIdValue = mPlatformInfo->AcpiOemId;
> +
> + *(UINT32 *)(TableHeader->OemId) = (UINT32)OemIdValue;
> + *(UINT16 *)(TableHeader->OemId + 4) = *(UINT16*)(((UINT8
> *)&OemIdValue) + 4);
> +
> + if ((Table->Signature !=
> EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE)) {
> + //
> + // Update the OEM Table ID.
> + //
> + TableHeader->OemTableId = mPlatformInfo->AcpiOemTableId;
> + }
> +
> + //
> + // Update the OEM Table ID.
> + //
> + TableHeader->OemRevision = EFI_ACPI_OEM_REVISION;
> +
> + //
> + // Update the creator ID.
> + //
> + TableHeader->CreatorId = EFI_ACPI_CREATOR_ID;
> +
> + //
> + // Update the creator revision.
> + //
> + TableHeader->CreatorRevision = EFI_ACPI_CREATOR_REVISION;
> + }
> +
> + //
> + // Complete this function.
> + //
> + //
> + // Locate the MP services protocol.
> + //
> + //
> + // Find the MP Protocol. This is an MP platform, so MP protocol must be
> + // there.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiMpServiceProtocolGuid,
> + NULL,
> + (VOID **) &MpService
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Determine the number of processors.
> + //
> + MpService->GetNumberOfProcessors (
> + MpService,
> + &MaximumNumberOfCPUs,
> + &NumberOfEnabledCPUs
> + );
> +
> + ASSERT (MaximumNumberOfCPUs <= MAX_CPU_NUM &&
> NumberOfEnabledCPUs >= 1);
> +
> +
> + //
> + // Assign a invalid intial value for update.
> + //
> + //
> + // Update the processors in the APIC table.
> + //
> + switch (Table->Signature) {
> + case EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE_SIGNATURE:
> + //
> + // Update the table if ASF is enabled. Otherwise, return error so caller
> will not install.
> + //
> + if (mSystemConfig.Asf == 1) {
> + return EFI_UNSUPPORTED;
> + }
> + AsfEntry = (EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE *) Table;
> + TempVal = (mNumberSmbusAddress <
> ASF_ADDR_DEVICE_ARRAY_LENGTH)? mNumberSmbusAddress :
> ASF_ADDR_DEVICE_ARRAY_LENGTH;
> + for (Index = 0; Index < TempVal; Index++) {
> + AsfEntry->AsfAddr.FixedSmbusAddresses[Index] =
> mSmbusRsvdAddresses[Index];
> + }
> + break;
> +
> + case EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:
> +
> + Status = MpService->WhoAmI (
> + MpService,
> + &BspIndex
> + );
> +
> + //
> + // PCAT_COMPAT Set to 1 indicate 8259 vectors should be disabled.
> + //
> + APICTableHeader =
> (EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *)Table;
> + APICTableHeader->Flags |= EFI_ACPI_3_0_PCAT_COMPAT;
> +
> + CurrPtr = (UINT8 *) &((EFI_ACPI_DESCRIPTION_HEADER *) Table)[1];
> + CurrPtr = CurrPtr + 8;
> +
> + //
> + // Size of Local APIC Address & Flag.
> + //
> + EndPtr = (UINT8 *) Table;
> + EndPtr = EndPtr + Table->Length;
> + while (CurrPtr < EndPtr) {
> + ApicPtr = (ACPI_APIC_STRUCTURE_PTR *) CurrPtr;
> + switch (ApicPtr->AcpiApicCommon.Type) {
> + case EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC:
> + //
> + // ESS override
> + // Fix for Ordering of MADT to be maintained as it is in MADT table.
> + //
> + // Update processor enabled or disabled and keep the local APIC
> + // order in MADT intact.
> + //
> + // Sanity check to make sure proc-id is not arbitrary.
> + //
> + DEBUG ((EFI_D_ERROR, "ApicPtr->AcpiLocalApic.AcpiProcessorId
> = %x, MaximumNumberOfCPUs = %x\n", \
> + ApicPtr->AcpiLocalApic.AcpiProcessorId, MaximumNumberOfCPUs));
> + if(ApicPtr->AcpiLocalApic.AcpiProcessorId >
> MaximumNumberOfCPUs) {
> + ApicPtr->AcpiLocalApic.AcpiProcessorId =
> (UINT8)MaximumNumberOfCPUs;
> + }
> +
> + ApicPtr->AcpiLocalApic.Flags = 0;
> +
> + for (CurrProcessor = 0; CurrProcessor < MaximumNumberOfCPUs;
> CurrProcessor++) {
> + Status = MpService->GetProcessorInfo (
> + MpService,
> + CurrProcessor,
> + &ProcessorInfoBuffer
> + );
> +
> + if (Status == EFI_SUCCESS && ProcessorInfoBuffer.ProcessorId ==
> ApicPtr->AcpiLocalApic.ApicId) {
> + //
> + // Check to see whether or not a processor (or thread) is enabled.
> + //
> + if ((BspIndex == CurrProcessor) || ((ProcessorInfoBuffer.StatusFlag
> & PROCESSOR_ENABLED_BIT) != 0)) {
> + //
> + // Go on and check if Hyper Threading is enabled. If HT not enabled
> + // hide this thread from OS by not setting the flag to 1. This is the
> + // software way to disable Hyper Threading. Basically we just hide
> it
> + // from the OS.
> + //
> + ApicPtr->AcpiLocalApic.Flags =
> EFI_ACPI_1_0_LOCAL_APIC_ENABLED;
> +
> +
> + if(ProcessorInfoBuffer.Location.Thread != 0) {
> + ApicPtr->AcpiLocalApic.Flags = 0;
> + }
> +
> + AppendCpuMapTableEntry (&(ApicPtr->AcpiLocalApic));
> + }
> + break;
> + }
> + }
> +
> + //
> + // If no APIC-ID match, the cpu may not be populated.
> + //
> + break;
> +
> + case EFI_ACPI_3_0_IO_APIC:
> +
> + IOApicType = (EFI_ACPI_3_0_IO_APIC_STRUCTURE *)CurrPtr;
> + IOApicType->IoApicId = 0x02;
> + //
> + // IO APIC entries can be patched here.
> + //
> + break;
> + }
> +
> + CurrPtr = CurrPtr + ApicPtr->AcpiApicCommon.Length;
> + }
> + break;
> +
> + case EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
> +
> + Facp = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *) Table;
> + Facp->Flags &= (UINT32)(~(3<<2));
> +
> + break;
> +
> + case
> EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
> + //
> + // Patch the memory resource.
> + //
> + PatchDsdtTable ((EFI_ACPI_DESCRIPTION_HEADER *) Table);
> + break;
> +
> + case
> EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
> + //
> + // Gv3 support
> + //
> + // TBD: Need re-design based on the ValleyTrail platform.
> + //
> + break;
> +
> + case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
> + //
> + // Adjust HPET Table to correct the Base Address.
> + //
> + // Enable HPET always as Hpet.asi always indicates that Hpet is enabled.
> + //
> + MmioOr8 (R_PCH_PCH_HPET + R_PCH_PCH_HPET_GCFG,
> B_PCH_PCH_HPET_GCFG_EN);
> +
> +
> + HpetTbl = (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER *)
> Table;
> + HpetTbl->BaseAddressLower32Bit.Address = HPET_BASE_ADDRESS;
> + HpetTbl->EventTimerBlockId =
> *((UINT32*)(UINTN)HPET_BASE_ADDRESS);
> +
> + HpetCapIdValue = *(UINT16 *)(UINTN)(HPET_BASE_ADDRESS);
> + NumberOfHpets = HpetCapIdValue & B_PCH_PCH_HPET_GCID_NT; //
> Bits [8:12] contains the number of Hpets
> + HpetBlockID = EFI_ACPI_EVENT_TIMER_BLOCK_ID;
> +
> + if((NumberOfHpets) && (NumberOfHpets &
> B_PCH_PCH_HPET_GCID_NT)) {
> + HpetBlockID |= (NumberOfHpets);
> + }
> + HpetTbl->EventTimerBlockId = HpetBlockID;
> +
> + break;
> +
> + case
> EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE
> _BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:
> + //
> + // Update MCFG base and end bus number.
> + //
> +
> ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE *)
> Table)->Segment[0].BaseAddress
> + = mPlatformInfo->PciData.PciExpressBase;
> +
> ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE *)
> Table)->Segment[0].EndBusNumber
> + = (UINT8)RShiftU64 (mPlatformInfo->PciData.PciExpressSize, 20) - 1;
> + break;
> +
> +
> + case EFI_ACPI_OSFR_TABLE_SIGNATURE:
> + //
> + // Get size of OSFR variable.
> + //
> + OcurMfgStringBufferSize = 0;
> + Status = gRT->GetVariable (
> + gACPIOSFRMfgStringVariableName,
> + &gACPIOSFRMfgStringVariableGuid,
> + NULL,
> + &OcurMfgStringBufferSize,
> + NULL
> + );
> + if (Status != EFI_BUFFER_TOO_SMALL) {
> + //
> + // Variable must not be present on the system.
> + //
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Allocate memory for variable data.
> + //
> + OcurMfgStringBuffer = AllocatePool (OcurMfgStringBufferSize);
> + Status = gRT->GetVariable (
> + gACPIOSFRMfgStringVariableName,
> + &gACPIOSFRMfgStringVariableGuid,
> + NULL,
> + &OcurMfgStringBufferSize,
> + OcurMfgStringBuffer
> + );
> + if (!EFI_ERROR (Status)) {
> + OcurModelStringBufferSize = 0;
> + Status = gRT->GetVariable (
> + gACPIOSFRModelStringVariableName,
> + &gACPIOSFRModelStringVariableGuid,
> + NULL,
> + &OcurModelStringBufferSize,
> + NULL
> + );
> + if (Status != EFI_BUFFER_TOO_SMALL) {
> + //
> + // Variable must not be present on the system.
> + //
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Allocate memory for variable data.
> + //
> + OcurModelStringBuffer = AllocatePool (OcurModelStringBufferSize);
> + Status = gRT->GetVariable (
> + gACPIOSFRModelStringVariableName,
> + &gACPIOSFRModelStringVariableGuid,
> + NULL,
> + &OcurModelStringBufferSize,
> + OcurModelStringBuffer
> + );
> + if (!EFI_ERROR (Status)) {
> + OcurRefDataBlockBufferSize = 0;
> + Status = gRT->GetVariable (
> + gACPIOSFRRefDataBlockVariableName,
> + &gACPIOSFRRefDataBlockVariableGuid,
> + NULL,
> + &OcurRefDataBlockBufferSize,
> + NULL
> + );
> + if (Status == EFI_BUFFER_TOO_SMALL) {
> + //
> + // Allocate memory for variable data.
> + //
> + OcurRefDataBlockBuffer = AllocatePool (OcurRefDataBlockBufferSize);
> + Status = gRT->GetVariable (
> + gACPIOSFRRefDataBlockVariableName,
> + &gACPIOSFRRefDataBlockVariableGuid,
> + NULL,
> + &OcurRefDataBlockBufferSize,
> + OcurRefDataBlockBuffer
> + );
> + }
> + OsfrTable = (EFI_ACPI_OSFR_TABLE *) Table;
> + //
> + // Currently only one object is defined: OCUR_OSFR_TABLE.
> + //
> + OsfrTable->ObjectCount = 1;
> + //
> + // Initialize table length to fixed portion of the ACPI OSFR table.
> + //
> + OsfrTable->Header.Length = sizeof
> (EFI_ACPI_OSFR_TABLE_FIXED_PORTION);
> + *(UINT32 *)((UINTN) OsfrTable + sizeof
> (EFI_ACPI_OSFR_TABLE_FIXED_PORTION)) = \
> + (UINT32) (sizeof (EFI_ACPI_OSFR_TABLE_FIXED_PORTION) + sizeof
> (UINT32));
> + pOcurObject = (EFI_ACPI_OSFR_OCUR_OBJECT *)((UINTN) OsfrTable
> + sizeof (EFI_ACPI_OSFR_TABLE_FIXED_PORTION) + \
> + sizeof (UINT32));
> + CopyMem (pOcurObject, &OcurObject, sizeof
> (EFI_ACPI_OSFR_OCUR_OBJECT));
> + pOcurObject->ManufacturerNameStringOffset = (UINT32)((UINTN)
> pOcurObject - (UINTN) OsfrTable + \
> + sizeof (EFI_ACPI_OSFR_OCUR_OBJECT));
> + pOcurObject->ModelNameStringOffset = (UINT32)((UINTN)
> pOcurObject - (UINTN) OsfrTable + \
> + sizeof (EFI_ACPI_OSFR_OCUR_OBJECT) + OcurMfgStringBufferSize);
> + if (OcurRefDataBlockBufferSize > 0) {
> + pOcurObject->MicrosoftReferenceOffset = (UINT32)((UINTN)
> pOcurObject - (UINTN) OsfrTable + \
> + sizeof (EFI_ACPI_OSFR_OCUR_OBJECT) + OcurMfgStringBufferSize +
> OcurModelStringBufferSize);
> + }
> + CopyMem ((UINTN *)((UINTN) pOcurObject + sizeof
> (EFI_ACPI_OSFR_OCUR_OBJECT)), OcurMfgStringBuffer, \
> + OcurMfgStringBufferSize);
> + CopyMem ((UINTN *)((UINTN) pOcurObject + sizeof
> (EFI_ACPI_OSFR_OCUR_OBJECT) + OcurMfgStringBufferSize), \
> + OcurModelStringBuffer, OcurModelStringBufferSize);
> + if (OcurRefDataBlockBufferSize > 0) {
> + CopyMem ((UINTN *)((UINTN) pOcurObject + sizeof
> (EFI_ACPI_OSFR_OCUR_OBJECT) + OcurMfgStringBufferSize + \
> + OcurModelStringBufferSize),OcurRefDataBlockBuffer,
> OcurRefDataBlockBufferSize);
> + }
> + OsfrTable->Header.Length += (UINT32)(OcurMfgStringBufferSize +
> OcurModelStringBufferSize + OcurRefDataBlockBufferSize);
> + OsfrTable->Header.Length += sizeof (EFI_ACPI_OSFR_OCUR_OBJECT)
> + sizeof (UINT32);
> + }
> + }
> + gBS->FreePool (OcurMfgStringBuffer);
> + gBS->FreePool (OcurModelStringBuffer);
> + gBS->FreePool (OcurRefDataBlockBuffer);
> + break;
> +
> +
> + case
> EFI_ACPI_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE:
> + WsmtTable = (EFI_ACPI_WSMT_TABLE *) Table;
> + //
> + // Update Microsoft WSMT table Protections flags.
> + //
> + WsmtTable->ProtectionFlags = ((WsmtTable->ProtectionFlags) |
> (EFI_WSMT_PROTECTION_FLAGS_FIXED_COMM_BUFFERS |
> EFI_WSMT_PROTECTION_FLAGS_COMM_BUFFER_NESTED_PTR_PROTECTIO
> N ));
> + break;
> +
> +
> + default:
> + break;
> + }
> +
> + //
> + //
> + // Update the hardware signature in the FACS structure.
> + //
> + //
> + // Locate the SPCR table and update based on current settings.
> + // The user may change CR settings via setup or other methods.
> + // The SPCR table must match.
> + //
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +
> +Routine Description:
> +
> + GC_TODO: Add function description.
> +
> +Arguments:
> +
> + Event - GC_TODO: add argument description
> + Context - GC_TODO: add argument description
> +
> +Returns:
> +
> + GC_TODO: add return values
> +
> +**/
> +STATIC
> +VOID
> +EFIAPI
> +OnReadyToBoot (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> + EFI_ACPI_TABLE_VERSION TableVersion;
> + EFI_ACPI_SUPPORT_PROTOCOL *AcpiSupport;
> + EFI_ACPI_S3_SAVE_PROTOCOL *AcpiS3Save;
> + SYSTEM_CONFIGURATION SetupVarBuffer;
> + UINTN VariableSize;
> + EFI_PLATFORM_CPU_INFO *PlatformCpuInfoPtr = NULL;
> + EFI_PLATFORM_CPU_INFO PlatformCpuInfo;
> + EFI_PEI_HOB_POINTERS GuidHob;
> +
> + if (mFirstNotify) {
> + return;
> + }
> +
> + mFirstNotify = TRUE;
> +
> + //
> + // To avoid compiler warning of "C4701: potentially uninitialized local
> variable 'PlatformCpuInfo' used".
> + //
> + PlatformCpuInfo.CpuVersion.FullCpuId = 0;
> +
> + //
> + // Get Platform CPU Info HOB.
> + //
> + PlatformCpuInfoPtr = NULL;
> + ZeroMem (&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));
> + VariableSize = sizeof(EFI_PLATFORM_CPU_INFO);
> + Status = gRT->GetVariable(
> + EfiPlatformCpuInfoVariable,
> + &gEfiVlv2VariableGuid,
> + NULL,
> + &VariableSize,
> + PlatformCpuInfoPtr
> + );
> + if (EFI_ERROR(Status)) {
> + GuidHob.Raw = GetHobList ();
> + if (GuidHob.Raw != NULL) {
> + if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformCpuInfoGuid,
> GuidHob.Raw)) != NULL) {
> + PlatformCpuInfoPtr = GET_GUID_HOB_DATA (GuidHob.Guid);
> + }
> + }
> + }
> +
> + if ((PlatformCpuInfoPtr != NULL)) {
> + CopyMem(&PlatformCpuInfo, PlatformCpuInfoPtr,
> sizeof(EFI_PLATFORM_CPU_INFO));
> + }
> +
> + //
> + // Update the ACPI parameter blocks finally.
> + //
> + VariableSize = sizeof (SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable (
> + L"Setup",
> + &mSystemConfigurationGuid,
> + NULL,
> + &VariableSize,
> + &SetupVarBuffer
> + );
> + if (EFI_ERROR (Status) || VariableSize != sizeof(SYSTEM_CONFIGURATION))
> {
> + //The setup variable is corrupted
> + VariableSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &mSystemConfigurationGuid,
> + NULL,
> + &VariableSize,
> + &SetupVarBuffer
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + //
> + // Find the AcpiSupport protocol.
> + //
> + Status = LocateSupportProtocol (&gEfiAcpiSupportProtocolGuid, (VOID **)
> &AcpiSupport, 0);
> + ASSERT_EFI_ERROR (Status);
> +
> + TableVersion = EFI_ACPI_TABLE_VERSION_2_0;
> +
> + //
> + // Publish ACPI 1.0 or 2.0 Tables.
> + //
> + Status = AcpiSupport->PublishTables (
> + AcpiSupport,
> + TableVersion
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // S3 script save.
> + //
> + Status = gBS->LocateProtocol (&gEfiAcpiS3SaveProtocolGuid, NULL, (VOID
> **) &AcpiS3Save);
> + if (!EFI_ERROR (Status)) {
> + AcpiS3Save->S3Save (AcpiS3Save, NULL);
> + }
> +
> +}
> +
> +VOID
> +PR1FSASetting (
> + IN VOID
> + )
> +{
> + //
> + // for FSA on PR1.
> + //
> + if (mPlatformInfo->BoardId == BOARD_ID_BL_FFRD && mPlatformInfo-
> >BoardRev >= PR1) {
> + DEBUG((EFI_D_ERROR, "Set FSA status = 1 for FFRD PR1\n"));
> + mGlobalNvsArea.Area->FsaStatus = mSystemConfiguration.PchFSAOn;
> + }
> + if (mPlatformInfo->BoardId == BOARD_ID_BL_FFRD8) {
> + DEBUG((EFI_D_ERROR, "Set FSA status = 1 for FFRD8\n"));
> + mGlobalNvsArea.Area->FsaStatus = mSystemConfiguration.PchFSAOn;
> + }
> +
> +}
> +
> +/**
> + Entry point for Acpi platform driver.
> +
> + @param[in] ImageHandle A handle for the image that is initializing this
> driver.
> + @param[in] SystemTable A pointer to the EFI system table.
> +
> + @retval EFI_SUCCESS Driver initialized successfully.
> + @retval EFI_LOAD_ERROR Failed to Initialize or has been loaded.
> + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +AcpiPlatformEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_STATUS AcpiStatus;
> + EFI_ACPI_SUPPORT_PROTOCOL *AcpiSupport;
> + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
> + INTN Instance;
> + EFI_ACPI_COMMON_HEADER *CurrentTable;
> + UINTN TableHandle;
> + UINT32 FvStatus;
> + UINTN Size;
> + EFI_EVENT Event;
> + EFI_ACPI_TABLE_VERSION TableVersion;
> + UINTN VarSize;
> + UINTN SysCfgSize;
> + EFI_HANDLE Handle;
> + EFI_PS2_POLICY_PROTOCOL *Ps2Policy;
> + EFI_PEI_HOB_POINTERS GuidHob;
> + UINT8 PortData;
> + EFI_MP_SERVICES_PROTOCOL *MpService;
> + UINTN MaximumNumberOfCPUs;
> + UINTN NumberOfEnabledCPUs;
> + PCH_STEPPING pchStepping;
> +
> + mFirstNotify = FALSE;
> +
> + TableVersion = EFI_ACPI_TABLE_VERSION_2_0;
> + Instance = 0;
> + CurrentTable = NULL;
> + TableHandle = 0;
> +
> + //
> + // Update HOB variable for PCI resource information.
> + // Get the HOB list. If it is not present, then ASSERT.
> + //
> + GuidHob.Raw = GetHobList ();
> + if (GuidHob.Raw != NULL) {
> + if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid,
> GuidHob.Raw)) != NULL) {
> + mPlatformInfo = GET_GUID_HOB_DATA (GuidHob.Guid);
> + }
> + }
> +
> + //
> + // Search for the Memory Configuration GUID HOB. If it is not present,
> then
> + // there's nothing we can do. It may not exist on the update path.
> + //
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"Setup",
> + &mSystemConfigurationGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &mSystemConfigurationGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + //
> + // Find the AcpiSupport protocol.
> + //
> + Status = LocateSupportProtocol (&gEfiAcpiSupportProtocolGuid, (VOID **)
> &AcpiSupport, 0);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Locate the firmware volume protocol.
> + //
> + Status = LocateSupportProtocol (&gEfiFirmwareVolume2ProtocolGuid,
> (VOID **) &FwVol, 1);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Read the current system configuration variable store.
> + //
> + SysCfgSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable (
> + L"Setup",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &SysCfgSize,
> + &mSystemConfig
> + );
> + if (EFI_ERROR (Status) || SysCfgSize != sizeof(SYSTEM_CONFIGURATION))
> {
> + //The setup variable is corrupted
> + SysCfgSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &SysCfgSize,
> + &mSystemConfig
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> +
> + Status = EFI_SUCCESS;
> + Instance = 0;
> +
> + //
> + // TBD: Need re-design based on the ValleyTrail platform.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiMpServiceProtocolGuid,
> + NULL,
> + (VOID **) &MpService
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Determine the number of processors.
> + //
> + MpService->GetNumberOfProcessors (
> + MpService,
> + &MaximumNumberOfCPUs,
> + &NumberOfEnabledCPUs
> + );
> +
> + //
> + // Allocate and initialize the NVS area for SMM and ASL communication.
> + //
> + Status = gBS->AllocatePool (
> + EfiACPIMemoryNVS,
> + sizeof (EFI_GLOBAL_NVS_AREA),
> + (void **)&mGlobalNvsArea.Area
> + );
> + ASSERT_EFI_ERROR (Status);
> + gBS->SetMem (
> + mGlobalNvsArea.Area,
> + sizeof (EFI_GLOBAL_NVS_AREA),
> + 0
> + );
> + DEBUG((EFI_D_ERROR, "mGlobalNvsArea.Area is at 0x%X\n",
> mGlobalNvsArea.Area));
> +
> + //
> + // Update global NVS area for ASL and SMM init code to use.
> + //
> + mGlobalNvsArea.Area->ApicEnable = 1;
> + mGlobalNvsArea.Area->EmaEnable = 0;
> +
> + mGlobalNvsArea.Area->NumberOfBatteries = 1;
> + mGlobalNvsArea.Area->BatteryCapacity0 = 100;
> + mGlobalNvsArea.Area->BatteryStatus0 = 84;
> + mGlobalNvsArea.Area->OnboardCom = 1;
> + mGlobalNvsArea.Area->IdeMode = 0;
> + mGlobalNvsArea.Area->PowerState = 0;
> +
> + mGlobalNvsArea.Area->LogicalProcessorCount =
> (UINT8)NumberOfEnabledCPUs;
> +
> + mGlobalNvsArea.Area->PassiveThermalTripPoint =
> mSystemConfiguration.PassiveThermalTripPoint;
> + mGlobalNvsArea.Area->PassiveTc1Value =
> mSystemConfiguration.PassiveTc1Value;
> + mGlobalNvsArea.Area->PassiveTc2Value =
> mSystemConfiguration.PassiveTc2Value;
> + mGlobalNvsArea.Area->PassiveTspValue =
> mSystemConfiguration.PassiveTspValue;
> + mGlobalNvsArea.Area->CriticalThermalTripPoint =
> mSystemConfiguration.CriticalThermalTripPoint;
> +
> + mGlobalNvsArea.Area->IgdPanelType =
> mSystemConfiguration.IgdFlatPanel;
> + mGlobalNvsArea.Area->IgdPanelScaling =
> mSystemConfiguration.PanelScaling;
> + mGlobalNvsArea.Area->IgdSciSmiMode = 0;
> + mGlobalNvsArea.Area->IgdTvFormat = 0;
> + mGlobalNvsArea.Area->IgdTvMinor = 0;
> + mGlobalNvsArea.Area->IgdSscConfig = 1;
> + mGlobalNvsArea.Area->IgdBiaConfig =
> mSystemConfiguration.IgdLcdIBia;
> + mGlobalNvsArea.Area->IgdBlcConfig =
> mSystemConfiguration.IgdLcdIGmchBlc;
> + mGlobalNvsArea.Area->IgdDvmtMemSize =
> mSystemConfiguration.IgdDvmt50TotalAlloc;
> + mGlobalNvsArea.Area->IgdPAVP =
> mSystemConfiguration.PavpMode;
> +
> + mGlobalNvsArea.Area->AlsEnable =
> mSystemConfiguration.AlsEnable;
> + mGlobalNvsArea.Area->BacklightControlSupport = 2;
> + mGlobalNvsArea.Area->BrightnessPercentage = 100;
> + mGlobalNvsArea.Area->IgdState = 1;
> + mGlobalNvsArea.Area->LidState = 1;
> +
> + mGlobalNvsArea.Area->DeviceId1 = 0x80000100 ;
> + mGlobalNvsArea.Area->DeviceId2 = 0x80000400 ;
> + mGlobalNvsArea.Area->DeviceId3 = 0x80000200 ;
> + mGlobalNvsArea.Area->DeviceId4 = 0x04;
> + mGlobalNvsArea.Area->DeviceId5 = 0x05;
> + mGlobalNvsArea.Area->NumberOfValidDeviceId = 4 ;
> + mGlobalNvsArea.Area->CurrentDeviceList = 0x0F ;
> + mGlobalNvsArea.Area->PreviousDeviceList = 0x0F ;
> +
> + mGlobalNvsArea.Area->UartSelection =
> mSystemConfiguration.UartInterface;
> + mGlobalNvsArea.Area->PcuUart1Enable =
> mSystemConfiguration.PcuUart1;
> + mGlobalNvsArea.Area->NativePCIESupport = 1;
> + mGlobalNvsArea.Area->RtcBattery = mSystemConfiguration.RtcBattery;
> +
> +
> +
> +
> +
> + //
> + // Update BootMode: 0:ACPI mode; 1:PCI mode
> + //
> + mGlobalNvsArea.Area->LpssSccMode =
> mSystemConfiguration.LpssPciModeEnabled;
> + if (mSystemConfiguration.LpssMipiHsi == 0) {
> + mGlobalNvsArea.Area->MipiHsiAddr = 0;
> + mGlobalNvsArea.Area->MipiHsiLen = 0;
> + mGlobalNvsArea.Area->MipiHsi1Addr = 0;
> + mGlobalNvsArea.Area->MipiHsi1Len = 0;
> + }
> +
> + //
> + // Platform Flavor
> + //
> + mGlobalNvsArea.Area->PlatformFlavor = mPlatformInfo->PlatformFlavor;
> +
> + //
> + // Update the Platform id
> + //
> + mGlobalNvsArea.Area->BoardID = mPlatformInfo->BoardId;
> +
> + //
> + // Update the Board Revision
> + //
> + mGlobalNvsArea.Area->FabID = mPlatformInfo->BoardRev;
> +
> + //
> + // Update SOC Stepping
> + //
> + mGlobalNvsArea.Area->SocStepping = (UINT8)(PchStepping());
> +
> + mGlobalNvsArea.Area->OtgMode = mSystemConfiguration.PchUsbOtg;
> +
> + pchStepping = PchStepping();
> + if (mSystemConfiguration.UsbAutoMode == 1) {
> + //
> + // Auto mode is enabled.
> + //
> + if (PchA0 == pchStepping) {
> + //
> + // For A0, EHCI is enabled as default.
> + //
> + mSystemConfiguration.PchUsb20 = 1;
> + mSystemConfiguration.PchUsb30Mode = 0;
> + mSystemConfiguration.UsbXhciSupport = 0;
> + DEBUG ((EFI_D_INFO, "EHCI is enabled as default. SOC 0x%x\n",
> pchStepping));
> + } else {
> + //
> + // For A1 and later, XHCI is enabled as default.
> + //
> + mSystemConfiguration.PchUsb20 = 0;
> + mSystemConfiguration.PchUsb30Mode = 1;
> + mSystemConfiguration.UsbXhciSupport = 1;
> + DEBUG ((EFI_D_INFO, "XHCI is enabled as default. SOC 0x%x\n",
> pchStepping));
> + }
> + }
> +
> + mGlobalNvsArea.Area->XhciMode =
> mSystemConfiguration.PchUsb30Mode;
> +
> + mGlobalNvsArea.Area->Stepping = mPlatformInfo->IchRevision;
> +
> + //
> + // Override invalid Pre-Boot Driver and XhciMode combination.
> + //
> + if ((mSystemConfiguration.UsbXhciSupport == 0) &&
> (mSystemConfiguration.PchUsb30Mode == 3)) {
> + mGlobalNvsArea.Area->XhciMode = 2;
> + }
> + if ((mSystemConfiguration.UsbXhciSupport == 1) &&
> (mSystemConfiguration.PchUsb30Mode == 2)) {
> + mGlobalNvsArea.Area->XhciMode = 3;
> + }
> +
> + DEBUG ((EFI_D_ERROR, "ACPI NVS XHCI:0x%x\n", mGlobalNvsArea.Area-
> >XhciMode));
> +
> + mGlobalNvsArea.Area->PmicEnable =
> GLOBAL_NVS_DEVICE_DISABLE;
> + mGlobalNvsArea.Area->BatteryChargingSolution =
> GLOBAL_NVS_DEVICE_DISABLE;
> + mGlobalNvsArea.Area->ISPDevSel =
> mSystemConfiguration.ISPDevSel;
> + mGlobalNvsArea.Area->LpeEnable =
> mSystemConfiguration.Lpe;
> + mGlobalNvsArea.Area->LpeAudioReportedByDSDT =
> mSystemConfiguration.LpeAudioReportedByDSDT;
> +
> + if (mSystemConfiguration.ISPEn == 0) {
> + mGlobalNvsArea.Area->ISPDevSel =
> GLOBAL_NVS_DEVICE_DISABLE;
> + }
> +
> + mGlobalNvsArea.Area->WittEnable =
> mSystemConfiguration.WittEnable;
> + mGlobalNvsArea.Area->UtsEnable =
> mSystemConfiguration.UtsEnable;
> + mGlobalNvsArea.Area->SarEnable =
> mSystemConfiguration.SAR1;
> +
> +
> + mGlobalNvsArea.Area->ReservedO = 1;
> +
> + SettingI2CTouchAddress();
> + mGlobalNvsArea.Area->IdleReserve= mSystemConfiguration.IdleReserve;
> + //
> + // Read BMBOUND and store it in GlobalNVS to pass into ASL.
> + //
> + // BUGBUG: code was moved into silicon reference code.
> + //
> + if (mSystemConfiguration.eMMCBootMode== 1) {
> + //
> + // Auto detect mode.
> + //
> + DEBUG ((EFI_D_ERROR, "Auto detect mode------------start\n"));
> +
> + //
> + // Silicon Steppings.
> + //
> + switch (PchStepping()) {
> + case PchA0: // A0/A1
> + case PchA1:
> + DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 Configuration\n"));
> + mSystemConfiguration.LpsseMMCEnabled = 1;
> + mSystemConfiguration.LpsseMMC45Enabled = 0;
> + break;
> +
> + case PchB0: // B0 and later.
> + default:
> + DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5
> Configuration\n"));
> + mSystemConfiguration.LpsseMMCEnabled = 0;
> + mSystemConfiguration.LpsseMMC45Enabled = 1;
> + break;
> + }
> + } else if (mSystemConfiguration.eMMCBootMode == 2) {
> + //
> + // eMMC 4.41
> + //
> + DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 Configuration\n"));
> + mSystemConfiguration.LpsseMMCEnabled = 1;
> + mSystemConfiguration.LpsseMMC45Enabled = 0;
> + } else if (mSystemConfiguration.eMMCBootMode == 3) {
> + //
> + // eMMC 4.5
> + //
> + DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 Configuration\n"));
> + mSystemConfiguration.LpsseMMCEnabled = 0;
> + mSystemConfiguration.LpsseMMC45Enabled = 1;
> +
> + } else {
> + //
> + // Disable eMMC controllers.
> + //
> + DEBUG ((EFI_D_ERROR, "Disable eMMC controllers\n"));
> + mSystemConfiguration.LpsseMMCEnabled = 0;
> + mSystemConfiguration.LpsseMMC45Enabled = 0;
> + }
> +
> + mGlobalNvsArea.Area->emmcVersion = 0;
> + if (mSystemConfiguration.LpsseMMCEnabled) {
> + DEBUG ((EFI_D_ERROR, "mGlobalNvsArea.Area->emmcVersion = 0\n"));
> + mGlobalNvsArea.Area->emmcVersion = 0;
> + }
> +
> + if (mSystemConfiguration.LpsseMMC45Enabled) {
> + DEBUG ((EFI_D_ERROR, "mGlobalNvsArea.Area->emmcVersion = 1\n"));
> + mGlobalNvsArea.Area->emmcVersion = 1;
> + }
> +
> + mGlobalNvsArea.Area->SdCardRemovable =
> mSystemConfiguration.SdCardRemovable;
> +
> + //
> + // Microsoft IOT
> + //
> + if ((mSystemConfiguration.LpssHsuart0FlowControlEnabled == 1) && \
> + (mSystemConfiguration.LpssPwm0Enabled == 0) && \
> + (mSystemConfiguration.LpssPwm1Enabled == 0)) {
> + mGlobalNvsArea.Area->MicrosoftIoT = GLOBAL_NVS_DEVICE_ENABLE;
> + DEBUG ((EFI_D_ERROR, "JP1 is set to be MSFT IOT configuration.\n"));
> + } else {
> + mGlobalNvsArea.Area->MicrosoftIoT = GLOBAL_NVS_DEVICE_DISABLE;
> + DEBUG ((EFI_D_ERROR, "JP1 is not set to be MSFT IOT configuration.\n"));
> + }
> +
> + //
> + // SIO related option.
> + //
> + Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, (void
> **)&mCpuIo);
> + ASSERT_EFI_ERROR (Status);
> +
> + mGlobalNvsArea.Area->WPCN381U = GLOBAL_NVS_DEVICE_DISABLE;
> +
> + mGlobalNvsArea.Area->DockedSioPresent =
> GLOBAL_NVS_DEVICE_DISABLE;
> +
> + if (mGlobalNvsArea.Area->DockedSioPresent !=
> GLOBAL_NVS_DEVICE_ENABLE) {
> + //
> + // Check ID for SIO WPCN381U.
> + //
> + Status = mCpuIo->Io.Read (
> + mCpuIo,
> + EfiCpuIoWidthUint8,
> + WPCN381U_CONFIG_INDEX,
> + 1,
> + &PortData
> + );
> + ASSERT_EFI_ERROR (Status);
> + if (PortData != 0xFF) {
> + PortData = 0x20;
> + Status = mCpuIo->Io.Write (
> + mCpuIo,
> + EfiCpuIoWidthUint8,
> + WPCN381U_CONFIG_INDEX,
> + 1,
> + &PortData
> + );
> + ASSERT_EFI_ERROR (Status);
> + Status = mCpuIo->Io.Read (
> + mCpuIo,
> + EfiCpuIoWidthUint8,
> + WPCN381U_CONFIG_DATA,
> + 1,
> + &PortData
> + );
> + ASSERT_EFI_ERROR (Status);
> + if ((PortData == WPCN381U_CHIP_ID) || (PortData ==
> WDCP376_CHIP_ID)) {
> + mGlobalNvsArea.Area->WPCN381U = GLOBAL_NVS_DEVICE_ENABLE;
> + mGlobalNvsArea.Area->OnboardCom = GLOBAL_NVS_DEVICE_ENABLE;
> + mGlobalNvsArea.Area->OnboardComCir =
> GLOBAL_NVS_DEVICE_DISABLE;
> + }
> + }
> + }
> +
> +
> +
> + //
> + // Get Ps2 policy to set. Will be use if present.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiPs2PolicyProtocolGuid,
> + NULL,
> + (VOID **)&Ps2Policy
> + );
> + if (!EFI_ERROR (Status)) {
> + Status = Ps2Policy->Ps2InitHardware (ImageHandle);
> + }
> +
> + mGlobalNvsArea.Area->SDIOMode =
> mSystemConfiguration.LpssSdioMode;
> +
> + Handle = NULL;
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Handle,
> + &gEfiGlobalNvsAreaProtocolGuid,
> + &mGlobalNvsArea,
> + NULL
> + );
> +
> + //
> + // Read tables from the storage file.
> + //
> + while (!EFI_ERROR (Status)) {
> + CurrentTable = NULL;
> +
> + Status = FwVol->ReadSection (
> + FwVol,
> + &gEfiAcpiTableStorageGuid,
> + EFI_SECTION_RAW,
> + Instance,
> + (VOID **) &CurrentTable,
> + &Size,
> + &FvStatus
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + //
> + // Allow platform specific code to reject the table or update it.
> + //
> + AcpiStatus = AcpiPlatformHooksIsActiveTable (CurrentTable);
> +
> + if (!EFI_ERROR (AcpiStatus)) {
> + //
> + // Perform any table specific updates.
> + //
> + AcpiStatus = PlatformUpdateTables (CurrentTable);
> + if (!EFI_ERROR (AcpiStatus)) {
> + //
> + // Add the table.
> + //
> + TableHandle = 0;
> + AcpiStatus = AcpiSupport->SetAcpiTable (
> + AcpiSupport,
> + CurrentTable,
> + TRUE,
> + TableVersion,
> + &TableHandle
> + );
> + ASSERT_EFI_ERROR (AcpiStatus);
> + }
> + }
> +
> + //
> + // Increment the instance.
> + //
> + Instance++;
> + }
> + }
> +
> + Status = EfiCreateEventReadyToBootEx (
> + TPL_NOTIFY,
> + OnReadyToBoot,
> + NULL,
> + &Event
> + );
> +
> + //
> + // Finished.
> + //
> + return EFI_SUCCESS;
> +}
> +
> +UINT8
> +ReadCmosBank1Byte (
> + IN UINT8 Index
> + )
> +{
> + UINT8 Data;
> +
> + IoWrite8(0x72, Index);
> + Data = IoRead8 (0x73);
> + return Data;
> +}
> +
> +VOID
> +WriteCmosBank1Byte (
> + IN UINT8 Index,
> + IN UINT8 Data
> + )
> +{
> + IoWrite8 (0x72, Index);
> + IoWrite8 (0x73, Data);
> +}
> +
> +
> +
> +VOID
> +SettingI2CTouchAddress (
> + IN VOID
> + )
> +{
> + if (mSystemConfiguration.I2CTouchAd == 0) {
> + //
> + // If setup menu select auto set I2C Touch Address base on board id.
> + //
> + if (mPlatformInfo->BoardId == BOARD_ID_BL_RVP ||
> + mPlatformInfo->BoardId == BOARD_ID_BL_STHI ||
> + mPlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ) {
> + //
> + //RVP
> + //
> + mGlobalNvsArea.Area->I2CTouchAddress = 0x4B;
> + } else if (mPlatformInfo->BoardId == BOARD_ID_BL_FFRD) {
> + //
> + //FFRD
> + //
> + mGlobalNvsArea.Area->I2CTouchAddress = 0x4A;
> + } else if (mPlatformInfo->BoardId == BOARD_ID_BB_RVP) {
> + mGlobalNvsArea.Area->I2CTouchAddress = 0x4C;
> + } else if (mPlatformInfo->BoardId == BOARD_ID_CVH) {
> + mGlobalNvsArea.Area->I2CTouchAddress = 0x4C;
> + } else if (mPlatformInfo->BoardId == BOARD_ID_BL_FFRD8) {
> + //
> + //FFRD8 uses 0x4A.
> + //
> + mGlobalNvsArea.Area->I2CTouchAddress = 0x4A;
> + }
> + } else {
> + mGlobalNvsArea.Area->I2CTouchAddress =
> mSystemConfiguration.I2CTouchAd;
> + }
> + DEBUG((EFI_D_ERROR, "GlobalNvsArea.Area->I2CTouchAddress:
> [%02x]\n", mGlobalNvsArea.Area->I2CTouchAddress));
> +}
> +
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.h
> b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.h
> new file mode 100644
> index 0000000000..598756846a
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.h
> @@ -0,0 +1,219 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + AcpiPlatform.h
> +
> +Abstract:
> +
> + This is an implementation of the ACPI platform driver. Requirements for
> + this driver are defined in the Tiano ACPI External Product Specification,
> + revision 0.3.6.
> +
> +
> +--*/
> +
> +#ifndef _ACPI_PLATFORM_H_
> +#define _ACPI_PLATFORM_H_
> +
> +//
> +// Statements that include other header files.
> +//
> +#include <FrameworkDxe.h>
> +#include <PiDxe.h>
> +#include <Base.h>
> +#include <Library/UefiLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Library/DebugLib.h>
> +#include <Protocol/FirmwareVolume.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/HighPrecisionEventTimerTable.h>
> +#include <IndustryStandard/Acpi.h>
> +#include <Protocol/AcpiSystemDescriptionTable.h>
> +#include <Protocol/MpService.h>
> +#include <Protocol/CpuIo.h>
> +#include <IndustryStandard/Acpi30.h>
> +#include <IndustryStandard/Acpi20.h>
> +#include <Library/HobLib.h>
> +#include <AlertStandardFormatTable.h>
> +#include <Guid/SetupVariable.h>
> +#include <Protocol/GlobalNvsArea.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <PchRegs.h>
> +#include <Library/PchPlatformLib.h>
> +//
> +// Global variables.
> +//
> +extern EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
> +
> +//
> +// ACPI table information used to initialize tables.
> +#define EFI_ACPI_OEM_REVISION 0x00000003
> +#define EFI_ACPI_CREATOR_ID SIGNATURE_32 ('V', 'L', 'V', '2')
> +#define EFI_ACPI_CREATOR_REVISION 0x0100000D
> +
> +#define WPCN381U_CONFIG_INDEX 0x2E
> +#define WPCN381U_CONFIG_DATA 0x2F
> +#define WPCN381U_CHIP_ID 0xF4
> +#define WDCP376_CHIP_ID 0xF1
> +
> +#define MOBILE_PLATFORM 1
> +#define DESKTOP_PLATFORM 2
> +
> +//
> +// Define macros to build data structure signatures from characters.
> +//
> +#ifndef EFI_SIGNATURE_16
> +#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8))
> +#endif
> +#ifndef EFI_SIGNATURE_32
> +#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) |
> (EFI_SIGNATURE_16 (C, D) << 16))
> +#endif
> +#ifndef EFI_SIGNATURE_64
> +#define EFI_SIGNATURE_64(A, B, C, D, E, F, G, H) \
> + (EFI_SIGNATURE_32 (A, B, C, D) | ((UINT64) (EFI_SIGNATURE_32 (E, F, G,
> H)) << 32))
> +#endif
> +
> +
> +#define GV3_SSDT_OEM_TABLE_IDBASE 0x4000
> +
> +//
> +// Private Driver Data.
> +//
> +//
> +// Define Union of IO APIC & Local APIC structure.
> +//
> +typedef union {
> + EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic;
> + EFI_ACPI_2_0_IO_APIC_STRUCTURE AcpiIoApic;
> + struct {
> + UINT8 Type;
> + UINT8 Length;
> + } AcpiApicCommon;
> +} ACPI_APIC_STRUCTURE_PTR;
> +
> +//
> +// Protocol private structure definition.
> +//
> +
> +/**
> + Entry point of the ACPI platform driver.
> +
> + @param[in] ImageHandle EFI_HANDLE: A handle for the image that is
> initializing this driver.
> + @param[in] SystemTable EFI_SYSTEM_TABLE: A pointer to the EFI
> system table.
> +
> + @retval EFI_SUCCESS Driver initialized successfully.
> + @retval EFI_LOAD_ERROR Failed to Initialize or has been loaded.
> + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources.
> +
> +**/
> +EFI_STATUS
> +InstallAcpiPlatform (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + );
> +
> +/**
> + Get Acpi Table Version.
> +
> + @param[in] ImageHandle EFI_HANDLE: A handle for the image that is
> initializing this driver.
> + @param[in] SystemTable EFI_SYSTEM_TABLE: A pointer to the EFI
> system table.
> +
> + @retval EFI_SUCCESS: Driver initialized successfully.
> + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded.
> + @retval EFI_OUT_OF_RESOURCES: Could not allocate needed resources.
> +
> +--*/
> +EFI_ACPI_TABLE_VERSION
> +GetAcpiTableVersion (
> + VOID
> + );
> +
> +/**
> + The funtion returns Oem specific information of Acpi Platform.
> +
> + @param[in] OemId OemId returned.
> + @param[in] OemTableId OemTableId returned.
> + @param[in] OemRevision OemRevision returned.
> +
> + @retval EFI_STATUS Status of function execution.
> +
> +**/
> +EFI_STATUS
> +AcpiPlatformGetOemFields (
> + OUT UINT8 *OemId,
> + OUT UINT64 *OemTableId,
> + OUT UINT32 *OemRevision
> + );
> +
> +/**
> + The function returns Acpi table version.
> +
> + @param[in]
> +
> + @retval EFI_ACPI_TABLE_VERSION Acpi table version encoded as a
> UINT32.
> +
> +**/
> +EFI_ACPI_TABLE_VERSION
> +AcpiPlatformGetAcpiSetting (
> + VOID
> + );
> +
> +/**
> + Entry point for Acpi platform driver.
> +
> + @param[in] ImageHandle A handle for the image that is initializing this
> driver.
> + @param[in] SystemTable A pointer to the EFI system table.
> +
> + @retval EFI_SUCCESS Driver initialized successfully.
> + @retval EFI_LOAD_ERROR Failed to Initialize or has been loaded.
> + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +AcpiPlatformEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + );
> +
> +UINT8
> +ReadCmosBank1Byte (
> + IN UINT8 Index
> + );
> +
> +VOID
> +WriteCmosBank1Byte (
> + IN UINT8 Index,
> + IN UINT8 Data
> + );
> +
> +VOID
> +SelectNFCDevice (
> + IN VOID
> + );
> +
> +VOID
> +SettingI2CTouchAddress (
> + IN VOID
> + );
> +
> +extern
> +EFI_STATUS
> +EFIAPI
> +IsctDxeEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf
> new file mode 100644
> index 0000000000..c59920db03
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf
> @@ -0,0 +1,89 @@
> +#
> +#
> +# Copyright (c) 1999 - 2019, Intel Corporation. All rights reserved
> +#
> +
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
> +
> +#
> +#
> +# Module Name:
> +#
> +# AcpiPlatformBB.inf
> +#
> +# Abstract:
> +#
> +#
> +
> +
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = AcpiPlatform
> + FILE_GUID = F0F6F006-DAB4-44b2-A7A1-0F72EEDCA716
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = AcpiPlatformEntryPoint
> +
> +[sources.common]
> + AcpiPlatformHooks.c
> + AcpiPlatform.c
> +
> +[Packages]
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + MdePkg/MdePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + HobLib
> + UefiRuntimeServicesTableLib
> + UefiDriverEntryPoint
> + BaseMemoryLib
> + DebugLib
> + HobLib
> + IoLib
> + PchPlatformLib
> +
> +[Guids]
> + gACPIOSFRMfgStringVariableGuid
> + gEfiAcpiTableStorageGuid
> + gACPIOSFRMfgStringVariableGuid
> + gEfiBoardFeaturesGuid
> + gEfiPlatformInfoGuid
> + gEfiNormalSetupGuid
> + gACPIOSFRRefDataBlockVariableGuid
> + gACPIOSFRModelStringVariableGuid
> + gEfiPlatformCpuInfoGuid
> + gEfiVlv2VariableGuid
> +
> +[Protocols]
> + gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED
> + gEnhancedSpeedstepProtocolGuid
> + gEfiPlatformCpuProtocolGuid
> + gEfiAcpiSupportProtocolGuid
> + gEfiAcpiS3SaveProtocolGuid
> + gEfiCpuIoProtocolGuid
> + gEfiPs2PolicyProtocolGuid
> + gEfiFirmwareVolume2ProtocolGuid
> + gEfiMpServiceProtocolGuid
> + gEfiGlobalNvsAreaProtocolGuid
> + gEfiTcgProtocolGuid
> + gEfiFirmwareVolume2ProtocolGuid
> + gIgdOpRegionProtocolGuid
> +
> +[Pcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
> +
> +[Depex]
> + gEfiVariableArchProtocolGuid AND
> + gEfiVariableWriteArchProtocolGuid AND
> + gEfiAcpiSupportProtocolGuid AND
> + gEfiMpServiceProtocolGuid AND
> + gEfiCpuIoProtocolGuid
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.c
> b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.c
> new file mode 100644
> index 0000000000..ebe783e29e
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.c
> @@ -0,0 +1,493 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + AcpiPlatformHooks.c
> +
> +Abstract:
> +
> + ACPI Platform Driver Hooks
> +
> +--*/
> +
> +//
> +// Statements that include other files.
> +//
> +#include "AcpiPlatform.h"
> +#include "AcpiPlatformHooks.h"
> +#include "Platform.h"
> +
> +//
> +// Prototypes of the various hook functions.
> +//
> +#include "AcpiPlatformHooksLib.h"
> +
> +extern SYSTEM_CONFIGURATION mSystemConfiguration;
> +
> +ENHANCED_SPEEDSTEP_PROTOCOL *mEistProtocol = NULL;
> +
> +EFI_CPU_ID_MAP mCpuApicIdAcpiIdMapTable[MAX_CPU_NUM];
> +
> +EFI_STATUS
> +AppendCpuMapTableEntry (
> + IN EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE *AcpiLocalApic
> + )
> +{
> + BOOLEAN Added;
> + UINTN Index;
> +
> + for (Index = 0; Index < MAX_CPU_NUM; Index++) {
> + if ((mCpuApicIdAcpiIdMapTable[Index].ApicId == AcpiLocalApic->ApicId)
> && mCpuApicIdAcpiIdMapTable[Index].Flags) {
> + return EFI_SUCCESS;
> + }
> + }
> +
> + Added = FALSE;
> + for (Index = 0; Index < MAX_CPU_NUM; Index++) {
> + if (!mCpuApicIdAcpiIdMapTable[Index].Flags) {
> + mCpuApicIdAcpiIdMapTable[Index].Flags = 1;
> + mCpuApicIdAcpiIdMapTable[Index].ApicId = AcpiLocalApic->ApicId;
> + mCpuApicIdAcpiIdMapTable[Index].AcpiProcessorId = AcpiLocalApic-
> >AcpiProcessorId;
> + Added = TRUE;
> + break;
> + }
> + }
> +
> + ASSERT (Added);
> + return EFI_SUCCESS;
> +}
> +
> +UINT32
> +ProcessorId2ApicId (
> + UINT32 AcpiProcessorId
> + )
> +{
> + UINTN Index;
> +
> + ASSERT (AcpiProcessorId < MAX_CPU_NUM);
> + for (Index = 0; Index < MAX_CPU_NUM; Index++) {
> + if (mCpuApicIdAcpiIdMapTable[Index].Flags &&
> (mCpuApicIdAcpiIdMapTable[Index].AcpiProcessorId == AcpiProcessorId)) {
> + return mCpuApicIdAcpiIdMapTable[Index].ApicId;
> + }
> + }
> +
> + return (UINT32) -1;
> +}
> +
> +UINT8
> +GetProcNumberInPackage (
> + IN UINT8 Package
> + )
> +{
> + UINTN Index;
> + UINT8 Number;
> +
> + Number = 0;
> + for (Index = 0; Index < MAX_CPU_NUM; Index++) {
> + if (mCpuApicIdAcpiIdMapTable[Index].Flags &&
> (((mCpuApicIdAcpiIdMapTable[Index].ApicId >> 0x04) & 0x01) == Package)) {
> + Number++;
> + }
> + }
> +
> + return Number;
> +}
> +
> +EFI_STATUS
> +LocateCpuEistProtocol (
> + IN UINT32 CpuIndex,
> + OUT ENHANCED_SPEEDSTEP_PROTOCOL **EistProtocol
> + )
> +{
> + UINTN HandleCount;
> + EFI_HANDLE *HandleBuffer;
> + ENHANCED_SPEEDSTEP_PROTOCOL *EistProt;
> + UINTN Index;
> + UINT32 ApicId;
> + EFI_STATUS Status;
> +
> + HandleCount = 0;
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEnhancedSpeedstepProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> +
> + Index = 0;
> + EistProt = NULL;
> + Status = EFI_NOT_FOUND;
> + while (Index < HandleCount) {
> + gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gEnhancedSpeedstepProtocolGuid,
> + (VOID **) &EistProt
> + );
> + //
> + // Adjust the CpuIndex by +1 due to the AcpiProcessorId is 1 based.
> + //
> + ApicId = ProcessorId2ApicId (CpuIndex+1);
> + if (ApicId == (UINT32) -1) {
> + break;
> + }
> +
> + if (EistProt->ProcApicId == ApicId) {
> + Status = EFI_SUCCESS;
> + break;
> + }
> +
> + Index++;
> + }
> +
> + if (HandleBuffer != NULL) {
> + gBS->FreePool (HandleBuffer);
> + }
> +
> + if (!EFI_ERROR (Status)) {
> + *EistProtocol = EistProt;
> + } else {
> + *EistProtocol = NULL;
> + }
> +
> + return Status;
> +}
> +
> +EFI_STATUS
> +PlatformHookInit (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = gBS->LocateProtocol (
> + &gEnhancedSpeedstepProtocolGuid,
> + NULL,
> + (VOID **) &mEistProtocol
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> +/**
> + Called for every ACPI table found in the BIOS flash.
> + Returns whether a table is active or not. Inactive tables
> + are not published in the ACPI table list.
> +
> + This hook can be used to implement optional SSDT tables or
> + enabling/disabling specific functionality (e.g. SPCR table)
> + based on a setup switch or platform preference. In case of
> + optional SSDT tables,the platform flash will include all the
> + SSDT tables but will return EFI_SUCCESS only for those tables
> + that need to be published.
> +
> + @param[in] *Table Pointer to the active table.
> +
> + @retval EFI_SUCCESS if the table is active.
> + @retval EFI_UNSUPPORTED if the table is not active.
> +
> +**/
> +EFI_STATUS
> +AcpiPlatformHooksIsActiveTable (
> + IN OUT EFI_ACPI_COMMON_HEADER *Table
> + )
> +{
> + EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
> +
> + TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
> +
> + if (TableHeader->Signature ==
> EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE) {
> +
> + }
> +
> + if ((mSystemConfiguration.ENDBG2 == 0) && (CompareMem
> (&TableHeader->OemTableId, "INTLDBG2", 8) == 0)) {
> + return EFI_UNSUPPORTED;
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Update the GV3 SSDT table.
> +
> + @param[in][out] *TableHeader The table to be set.
> +
> + @retval EFI_SUCCESS Returns Success.
> +
> +**/
> +EFI_STATUS
> +PatchGv3SsdtTable (
> + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader
> + )
> +{
> + UINT8 *CurrPtr;
> + UINT8 *SsdtPointer;
> + UINT32 Signature;
> + UINT32 CpuFixes;
> + UINT32 NpssFixes;
> + UINT32 SpssFixes;
> + UINT32 CpuIndex;
> + UINT32 PackageSize;
> + UINT32 NewPackageSize;
> + UINT32 AdjustSize;
> + UINTN EntryIndex;
> + UINTN TableIndex;
> + EFI_ACPI_NAME_COMMAND *PssTable;
> + EFI_PSS_PACKAGE *PssTableItemPtr;
> + ENHANCED_SPEEDSTEP_PROTOCOL *EistProt;
> + EIST_INFORMATION *EistInfo;
> + EFI_ACPI_CPU_PSS_STATE *PssState;
> + EFI_ACPI_NAMEPACK_DWORD *NamePtr;
> + //
> + // Loop through the ASL looking for values that we must fix up.
> + //
> + NpssFixes = 0;
> + SpssFixes = 0;
> + CpuFixes = 0;
> + CpuIndex = 0;
> + CurrPtr = (UINT8 *) TableHeader;
> +
> + EistProt = NULL;
> + for (SsdtPointer = CurrPtr; SsdtPointer <= (CurrPtr +
> ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length); SsdtPointer++) {
> + Signature = *(UINT32 *) SsdtPointer;
> + switch (Signature) {
> +
> + case SIGNATURE_32 ('_', 'P', 'R', '_'):
> + //
> + // _CPUX ('0' to '0xF')
> + //
> + CpuIndex = *(SsdtPointer + 7);
> + if (CpuIndex >= '0' && CpuIndex <= '9') {
> + CpuIndex -= '0';
> + } else {
> + if (CpuIndex > '9') {
> + CpuIndex -= '7';
> + }
> + }
> +
> + CpuFixes++;
> + LocateCpuEistProtocol (CpuIndex, &EistProt);
> + break;
> +
> + case SIGNATURE_32 ('D', 'O', 'M', 'N'):
> +
> + NamePtr = ACPI_NAME_COMMAND_FROM_NAMEPACK_STR
> (SsdtPointer);
> + if (NamePtr->StartByte != AML_NAME_OP) {
> + continue;
> + }
> +
> + if (NamePtr->Size != AML_NAME_DWORD_SIZE) {
> + continue;
> + }
> +
> + NamePtr->Value = 0;
> +
> + if (mCpuApicIdAcpiIdMapTable[CpuIndex].Flags) {
> + NamePtr->Value = (mCpuApicIdAcpiIdMapTable[CpuIndex].ApicId >>
> 0x04) & 0x01;
> + }
> + break;
> +
> + case SIGNATURE_32 ('N', 'C', 'P', 'U'):
> +
> + NamePtr = ACPI_NAME_COMMAND_FROM_NAMEPACK_STR
> (SsdtPointer);
> + if (NamePtr->StartByte != AML_NAME_OP) {
> + continue;
> + }
> +
> + if (NamePtr->Size != AML_NAME_DWORD_SIZE) {
> + continue;
> + }
> +
> + NamePtr->Value = 0;
> + if (mCpuApicIdAcpiIdMapTable[CpuIndex].Flags) {
> + NamePtr->Value = GetProcNumberInPackage
> ((mCpuApicIdAcpiIdMapTable[CpuIndex].ApicId >> 0x04) & 0x01);
> + }
> + break;
> +
> + case SIGNATURE_32 ('N', 'P', 'S', 'S'):
> + case SIGNATURE_32 ('S', 'P', 'S', 'S'):
> + if (EistProt == NULL) {
> + continue;
> + }
> +
> + PssTable = ACPI_NAME_COMMAND_FROM_NAME_STR (SsdtPointer);
> + if (PssTable->StartByte != AML_NAME_OP) {
> + continue;
> + }
> +
> + EistProt->GetEistTable (EistProt, &EistInfo, (VOID **) &PssState);
> +
> + AdjustSize = PssTable->NumEntries * sizeof (EFI_PSS_PACKAGE);
> + AdjustSize -= EistInfo->NumStates * sizeof (EFI_PSS_PACKAGE);
> + PackageSize = (PssTable->Size & 0xF) + ((PssTable->Size & 0xFF00) >>
> 4);
> + NewPackageSize = PackageSize - AdjustSize;
> + PssTable->Size = (UINT16) ((NewPackageSize & 0xF) +
> ((NewPackageSize & 0x0FF0) << 4));
> +
> + //
> + // Set most significant two bits of byte zero to 01, meaning two bytes
> used.
> + //
> + PssTable->Size |= 0x40;
> +
> + //
> + // Set unused table to Noop Code.
> + //
> + SetMem( (UINT8 *) PssTable + NewPackageSize +
> AML_NAME_PREFIX_SIZE, AdjustSize, AML_NOOP_OP);
> + PssTable->NumEntries = (UINT8) EistInfo->NumStates;
> + PssTableItemPtr = (EFI_PSS_PACKAGE *) ((UINT8 *) PssTable + sizeof
> (EFI_ACPI_NAME_COMMAND));
> +
> + //
> + // Update the size.
> + //
> + for (TableIndex = 0; TableIndex < EistInfo->NumStates; TableIndex++) {
> + EntryIndex = EistInfo->NumStates - TableIndex - 1;
> + PssTableItemPtr->CoreFreq = PssState[EntryIndex].CoreFrequency *
> PssState[EntryIndex].Control;
> + PssTableItemPtr->Power = PssState[EntryIndex].Power * 1000;
> + if (PssTable->NameStr == SIGNATURE_32 ('N', 'P', 'S', 'S')) {
> + PssTableItemPtr->BMLatency =
> PssState[EntryIndex].BusMasterLatency;
> + PssTableItemPtr->TransLatency =
> PssState[EntryIndex].TransitionLatency;
> + } else {
> + //
> + // This method should be supported by SMM PPM Handler.
> + //
> + PssTableItemPtr->BMLatency =
> PssState[EntryIndex].BusMasterLatency * 2;
> + PssTableItemPtr->TransLatency =
> PssState[EntryIndex].TransitionLatency * 10;
> + }
> +
> + PssTableItemPtr->Control = PssState[EntryIndex].Control;
> + PssTableItemPtr->Status = PssState[EntryIndex].Status;
> + PssTableItemPtr++;
> + }
> +
> + if (PssTable->NameStr == SIGNATURE_32 ('N', 'P', 'S', 'S')) {
> + NpssFixes++;
> + } else {
> + SpssFixes++;
> + }
> +
> + SsdtPointer = (UINT8 *) PssTable + PackageSize;
> + break;
> + }
> + }
> +
> + //
> + // N fixes together currently.
> + //
> + ASSERT (CpuFixes == (UINT32) MAX_CPU_NUM);
> + ASSERT (SpssFixes == NpssFixes);
> + ASSERT (CpuFixes >= SpssFixes);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Update the DSDT table.
> +
> + @param[in][out] *TableHeader The table to be set.
> +
> + @retval EFI_SUCCESS Returns EFI_SUCCESS.
> +
> +**/
> +EFI_STATUS
> +PatchDsdtTable (
> + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader
> + )
> +{
> +
> + UINT8 *CurrPtr;
> + UINT8 *DsdtPointer;
> + UINT32 *Signature;
> + UINT8 *EndPtr;
> + UINT8 *Operation;
> + UINT32 *Address;
> + UINT16 *Size;
> +
> + //
> + // Fix PCI32 resource "FIX0" -- PSYS system status area
> + //
> + CurrPtr = (UINT8*) &((EFI_ACPI_DESCRIPTION_HEADER*) TableHeader)[0];
> + EndPtr = (UINT8*) TableHeader;
> + EndPtr = EndPtr + TableHeader->Length;
> + while (CurrPtr < (EndPtr-2)) {
> + //
> + // Removed the _S3 tag to indicate that we do not support S3. The 4th
> byte is blank space
> + // since there are only 3 char "_S3".
> + //
> + if (mSystemConfiguration.AcpiSuspendState == 0) {
> + //
> + // For iasl compiler version 20061109.
> + //
> + if ((CurrPtr[0] == '_') && (CurrPtr[1] == 'S') && (CurrPtr[2] == '3') &&
> (CurrPtr[3] == '_')) {
> + break;
> + }
> + //
> + // For iasl compiler version 20040527.
> + //
> + if ((CurrPtr[0] == '\\') && (CurrPtr[1] == '_') && (CurrPtr[2] == 'S') &&
> (CurrPtr[3] == '3')) {
> + break;
> + }
> + }
> + CurrPtr++;
> + }
> + CurrPtr = (UINT8*) &((EFI_ACPI_DESCRIPTION_HEADER*) TableHeader)[0];
> + EndPtr = (UINT8*) TableHeader;
> + EndPtr = EndPtr + TableHeader->Length;
> + while (CurrPtr < (EndPtr-2)) {
> + //
> + // For mipi dsi port select _DEP.
> + //
> + if (mSystemConfiguration.MipiDsi== 1) {
> + //
> + // For iasl compiler version 20061109.
> + //
> + if ((CurrPtr[0] == 'N') && (CurrPtr[1] == 'D') && (CurrPtr[2] == 'E') &&
> (CurrPtr[3] == 'P')) {
> + CurrPtr[0] = '_';
> + break;
> + }
> +
> + } else {
> + if ((CurrPtr[0] == 'P') && (CurrPtr[1] == 'D') && (CurrPtr[2] == 'E') &&
> (CurrPtr[3] == 'P')) {
> + CurrPtr[0] = '_';
> + break;
> + }
> +
> + }
> + CurrPtr++;
> + }
> + //
> + // Loop through the ASL looking for values that we must fix up.
> + //
> + CurrPtr = (UINT8 *) TableHeader;
> + for (DsdtPointer = CurrPtr; DsdtPointer <= (CurrPtr +
> ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length); DsdtPointer++) {
> + Signature = (UINT32 *) DsdtPointer;
> +
> + switch (*Signature) {
> + //
> + // GNVS operation region.
> + //
> + case (SIGNATURE_32 ('G', 'N', 'V', 'S')):
> + //
> + // Conditional match. For Region Objects, the Operator will always be
> the
> + // byte immediately before the specific name. Therefore, subtract 1 to
> check
> + // the Operator.
> + //
> + Operation = DsdtPointer - 1;
> + if (*Operation == AML_OPREGION_OP) {
> + Address = (UINT32 *) (DsdtPointer + 6);
> + *Address = (UINT32) (UINTN) mGlobalNvsArea.Area;
> + Size = (UINT16 *) (DsdtPointer + 11);
> + *Size = sizeof (EFI_GLOBAL_NVS_AREA);
> + }
> + break;
> + default:
> + break;
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.h
> b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.h
> new file mode 100644
> index 0000000000..4718949610
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.h
> @@ -0,0 +1,127 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + AcpiPlatformHooks.h
> +
> +Abstract:
> +
> + This is an implementation of the ACPI platform driver. Requirements for
> + this driver are defined in the Tiano ACPI External Product Specification,
> + revision 0.3.6.
> +
> +--*/
> +
> +#ifndef _ACPI_PLATFORM_HOOKS_H_
> +#define _ACPI_PLATFORM_HOOKS_H_
> +
> +//
> +// Statements that include other header files
> +//
> +
> +#include <IndustryStandard/Acpi.h>
> +#include "Platform.h"
> +#include <Protocol/EnhancedSpeedstep.h>
> +
> +#define AML_NAME_OP 0x08
> +#define AML_METHOD_OP 0x14
> +#define AML_OPREGION_OP 0x80
> +#define AML_PACKAGE_OP 0x12 // Package operator.
> +#define AML_NAME_PREFIX_SIZE 0x06
> +#define AML_NAME_DWORD_SIZE 0x0C
> +
> +#pragma pack(1)
> +
> +typedef struct {
> + UINT8 AcpiProcessorId;
> + UINT8 ApicId;
> + UINT16 Flags;
> +} EFI_CPU_ID_MAP;
> +
> +typedef struct {
> + UINT8 StartByte;
> + UINT32 NameStr;
> + UINT8 Size;
> + UINT32 Value;
> +} EFI_ACPI_NAMEPACK_DWORD;
> +
> +typedef struct {
> + UINT8 StartByte;
> + UINT32 NameStr;
> + UINT8 OpCode;
> + UINT16 Size; // Hardcode to 16bit width because the table we
> use is fixed size
> + UINT8 NumEntries;
> +} EFI_ACPI_NAME_COMMAND;
> +
> +typedef struct {
> + UINT8 PackageOp;
> + UINT8 PkgLeadByte;
> + UINT8 NumEntries;
> + UINT8 DwordPrefix0;
> + UINT32 CoreFreq;
> + UINT8 DwordPrefix1;
> + UINT32 Power;
> + UINT8 DwordPrefix2;
> + UINT32 TransLatency;
> + UINT8 DwordPrefix3;
> + UINT32 BMLatency;
> + UINT8 DwordPrefix4;
> + UINT32 Control;
> + UINT8 DwordPrefix5;
> + UINT32 Status;
> +} EFI_PSS_PACKAGE;
> +
> +typedef struct {
> + UINT8 PackageOp;
> + UINT8 PkgLeadByte;
> + UINT8 NumEntries;
> + UINT8 BytePrefix0;
> + UINT8 Entries;
> + UINT8 BytePrefix1;
> + UINT8 Revision;
> + UINT8 BytePrefix2;
> + UINT8 Domain;
> + UINT8 BytePrefix3;
> + UINT8 Coordinate;
> + UINT8 BytePrefix4;
> + UINT8 ProcNumber;
> +} EFI_PSD_PACKAGE;
> +
> +#pragma pack()
> +
> +#define ACPI_NAME_COMMAND_FROM_NAME_STR(a) BASE_CR (a,
> EFI_ACPI_NAME_COMMAND, NameStr)
> +#define ACPI_NAME_COMMAND_FROM_NAMEPACK_STR(a) BASE_CR (a,
> EFI_ACPI_NAMEPACK_DWORD, NameStr)
> +
> +EFI_STATUS
> +PlatformHookInit (
> + VOID
> + );
> +
> +
> +EFI_STATUS
> +PatchDsdtTable (
> + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader
> + );
> +
> +EFI_STATUS
> +PatchGv3SsdtTable (
> + IN OUT EFI_ACPI_DESCRIPTION_HEADER *Table
> + );
> +
> +EFI_STATUS
> +PatchErstTable (
> + IN OUT EFI_ACPI_DESCRIPTION_HEADER *Table
> + );
> +
> +EFI_STATUS
> +AppendCpuMapTableEntry (
> + IN EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE *AcpiLocalApic
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooksLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooksLib.h
> new file mode 100644
> index 0000000000..a253d64ec0
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooksLib.h
> @@ -0,0 +1,91 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + AcpiPlatformHooksLib.h
> +
> +Abstract:
> +
> + This is an implementation of the ACPI platform driver. Requirements for
> + this driver are defined in the Tiano ACPI External Product Specification,
> + revision 0.3.6.
> +
> +--*/
> +
> +#ifndef _ACPI_PLATFORM_HOOKS_LIB_H_
> +#define _ACPI_PLATFORM_HOOKS_LIB_H_
> +
> +//
> +// Statements that include other header files.
> +//
> +#include <IndustryStandard/Acpi.h>
> +
> +/**
> + Returns the ACPI table version that the platform wants.
> +
> + @param[in] None
> +
> + @retval EFI_ACPI_TABLE_VERSION_NONE if ACPI is to be disabled.
> + @retval EFI_ACPI_TABLE_VERSION_1_0B if 1.0b.
> + @retval EFI_ACPI_TABLE_VERSION_2_00 if 2.00.
> +**/
> +EFI_ACPI_TABLE_VERSION
> +AcpiPlatformHooksGetAcpiTableVersion (
> + VOID
> + );
> +
> +/**
> + Returns the OEMID, OEM Table ID, OEM Revision.
> +
> + @param[in] None
> +
> + @retval OemId OEM ID string for ACPI tables, maximum 6 ASCII
> characters.
> + This is an OEM-supplied string that identifies the OEM.
> + @retval OemTableId An OEM-supplied string that the OEM uses to
> identify
> + the particular data table. This field is particularly useful
> + when defining a definition block to distinguish definition block
> + functions. The OEM assigns each dissimilar table a new OEM
> Table ID.
> + @retval OemRevision An OEM-supplied revision number for ACPI tables.
> + Larger numbers are assumed to be newer revisions.
> +
> +**/
> +EFI_STATUS
> +AcpiPlatformHooksGetOemFields (
> + OUT UINT8 *OemId,
> + OUT UINT64 *OemTableId,
> + OUT UINT32 *OemRevision
> + );
> +
> + /**
> + Called for every ACPI table found in the BIOS flash.
> + Returns whether a table is active or not. Inactive tables
> + are not published in the ACPI table list. This hook can be
> + used to implement optional SSDT tables or enabling/disabling
> + specific functionality (e.g. SPCR table) based on a setup
> + switch or platform preference. In case of optional SSDT tables,
> + the platform flash will include all the SSDT tables but will
> + return EFI_SUCCESS only for those tables that need to be
> + published.
> + This hook can also be used to update the table data. The header
> + is updated by the common code. For example, if a platform wants
> + to use an SSDT table to export some platform settings to the
> + ACPI code, it needs to update the data inside that SSDT based
> + on platform preferences in this hook.
> +
> + @param[in] None
> +
> + @retval EFI_SUCCESS if the table is active.
> + @retval EFI_UNSUPPORTED if the table is not active.
> +**/
> +EFI_STATUS
> +AcpiPlatformHooksIsActiveTable (
> + IN OUT EFI_ACPI_COMMON_HEADER *Table
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/Osfr.h
> b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/Osfr.h
> new file mode 100644
> index 0000000000..4d98db7592
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/AcpiPlatform/Osfr.h
> @@ -0,0 +1,56 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + Osfr.h
> +
> +Abstract:
> +
> + This file describes the contents of the ACPI OSFR Table.
> +
> +--*/
> +
> +#ifndef _OSFR_H
> +#define _OSFR_H
> +
> +//
> +// Statements that include other files.
> +//
> +#include <IndustryStandard/Acpi10.h>
> +#include <IndustryStandard/Acpi20.h>
> +
> +#pragma pack (1)
> +
> +#define EFI_ACPI_OSFR_TABLE_REVISION 0x1
> +//#define EFI_ACPI_OSFR_TABLE_SIGNATURE 'RFSO'
> +#define EFI_ACPI_OSFR_TABLE_SIGNATURE SIGNATURE_32('O', 'S', 'F',
> 'R') //'RFSO'
> +
> +typedef struct {
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + UINT32 ObjectCount;
> + UINT32 TableDWORDs [64];
> +} EFI_ACPI_OSFR_TABLE;
> +
> +typedef struct {
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + UINT32 ObjectCount;
> +} EFI_ACPI_OSFR_TABLE_FIXED_PORTION;
> +
> +typedef struct {
> + EFI_GUID ObjectUUID;
> + UINT32 Reserved1;
> + UINT32 ManufacturerNameStringOffset;
> + UINT32 ModelNameStringOffset;
> + UINT32 Reserved2;
> + UINT32 MicrosoftReferenceOffset;
> +} EFI_ACPI_OSFR_OCUR_OBJECT;
> +
> +#pragma pack ()
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> Update.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> Update.c
> new file mode 100644
> index 0000000000..a2fc54e20e
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> Update.c
> @@ -0,0 +1,922 @@
> +/** @file
> +
> +Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include "FirmwareUpdate.h"
> +
> +EFI_HII_HANDLE HiiHandle;
> +
> +//
> +// MinnowMax Flash Layout
> +//
> +//Start (hex) End (hex) Length (hex) Area Name
> +//----------- --------- ------------ ---------
> +//00000000 007FFFFF 00800000 Flash Image
> +//
> +//00000000 00000FFF 00001000 Descriptor Region
> +//00001000 003FFFFF 003FF000 TXE Region
> +//00500000 007FFFFF 00400000 BIOS Region
> +//
> +FV_REGION_INFO mRegionInfo[] = {
> + {FixedPcdGet32 (PcdFlashDescriptorBase), FixedPcdGet32
> (PcdFlashDescriptorSize), TRUE},
> + {FixedPcdGet32 (PcdTxeRomBase), FixedPcdGet32 (PcdTxeRomSize),
> TRUE},
> + {FixedPcdGet32 (PcdBiosRomBase), FixedPcdGet32 (PcdBiosRomSize),
> TRUE}
> +};
> +
> +UINTN mRegionInfoCount = ARRAY_SIZE (mRegionInfo);
> +
> +FV_INPUT_DATA mInputData = {0};
> +
> +EFI_SPI_PROTOCOL *mSpiProtocol;
> +
> +EFI_STATUS
> +GetRegionIndex (
> + IN EFI_PHYSICAL_ADDRESS Address,
> + OUT UINTN *RegionIndex
> + )
> +{
> + UINTN Index;
> +
> + for (Index = 0; Index < mRegionInfoCount; Index++) {
> + if (Address >= mRegionInfo[Index].Base &&
> + Address < (mRegionInfo[Index].Base + mRegionInfo[Index].Size)
> + ) {
> + break;
> + }
> + }
> +
> + *RegionIndex = Index;
> + if (Index >= mRegionInfoCount) {
> + return EFI_NOT_FOUND;
> + }
> + return EFI_SUCCESS;
> +}
> +
> +BOOLEAN
> +UpdateBlock (
> + IN EFI_PHYSICAL_ADDRESS Address
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> +
> + if (mInputData.FullFlashUpdate) {
> + return TRUE;
> + }
> +
> + Status = GetRegionIndex (Address, &Index);
> + if ((!EFI_ERROR(Status)) && mRegionInfo[Index].Update) {
> + return TRUE;
> + }
> +
> + return FALSE;
> +}
> +
> +EFI_STATUS
> +MarkRegionState (
> + IN EFI_PHYSICAL_ADDRESS Address,
> + IN BOOLEAN Update
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> +
> + Status = GetRegionIndex (Address, &Index);
> + if (!EFI_ERROR(Status)) {
> + mRegionInfo[Index].Update = Update;
> + }
> +
> + return Status;
> +}
> +
> +UINTN
> +InternalPrintToken (
> + IN CONST CHAR16 *Format,
> + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *Console,
> + IN VA_LIST Marker
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Return;
> + CHAR16 *Buffer;
> + UINTN BufferSize;
> +
> + ASSERT (Format != NULL);
> + ASSERT (((UINTN) Format & BIT0) == 0);
> + ASSERT (Console != NULL);
> +
> + BufferSize = (PcdGet32 (PcdUefiLibMaxPrintBufferSize) + 1) * sizeof
> (CHAR16);
> +
> + Buffer = (CHAR16 *) AllocatePool(BufferSize);
> + ASSERT (Buffer != NULL);
> +
> + Return = UnicodeVSPrint (Buffer, BufferSize, Format, Marker);
> +
> + if (Console != NULL && Return > 0) {
> + //
> + // To be extra safe make sure Console has been initialized.
> + //
> + Status = Console->OutputString (Console, Buffer);
> + if (EFI_ERROR (Status)) {
> + Return = 0;
> + }
> + }
> +
> + FreePool (Buffer);
> +
> + return Return;
> +}
> +
> +UINTN
> +EFIAPI
> +PrintToken (
> + IN UINT16 Token,
> + IN EFI_HII_HANDLE Handle,
> + ...
> + )
> +{
> + VA_LIST Marker;
> + UINTN Return;
> + CHAR16 *Format;
> +
> + VA_START (Marker, Handle);
> +
> + Format = HiiGetString (Handle, Token, NULL);
> + ASSERT (Format != NULL);
> +
> + Return = InternalPrintToken (Format, gST->ConOut, Marker);
> +
> + FreePool (Format);
> +
> + VA_END (Marker);
> +
> + return Return;
> +}
> +
> +EFI_STATUS
> +ParseCommandLine (
> + IN UINTN Argc,
> + IN CHAR16 **Argv
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> +
> + //
> + // Check to make sure that the command line has enough arguments for
> minimal
> + // operation. The minimum is just the file name.
> + //
> + if (Argc < 2 || Argc > 4) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Loop through command line arguments.
> + //
> + for (Index = 1; Index < Argc; Index++) {
> + //
> + // Make sure the string is valid.
> + //
> + if (StrLen (Argv[Index]) == 0) {;
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_ZEROLENGTH_ARG),
> HiiHandle);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check to see if this is an option or the file name.
> + //
> + if ((Argv[Index])[0] == L'-' || (Argv[Index])[0] == L'/') {
> + //
> + // Parse the arguments.
> + //
> + if ((StrCmp (Argv[Index], L"-h") == 0) ||
> + (StrCmp (Argv[Index], L"--help") == 0) ||
> + (StrCmp (Argv[Index], L"/?") == 0) ||
> + (StrCmp (Argv[Index], L"/h") == 0)) {
> + //
> + // Print Help Information.
> + //
> + return EFI_INVALID_PARAMETER;
> + } else if (StrCmp (Argv[Index], L"-m") == 0) {
> + //
> + // Parse the MAC address here.
> + //
> + Status = ConvertMac(Argv[Index+1]);
> + if (EFI_ERROR(Status)) {
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_INVAILD_MAC),
> HiiHandle);
> + return Status;
> + }
> +
> + //
> + // Save the MAC address to mInputData.MacValue.
> + //
> + mInputData.UpdateMac= TRUE;
> + Index++;
> + } else {
> + //
> + // Invalid option was provided.
> + //
> + return EFI_INVALID_PARAMETER;
> + }
> + }
> + if ((Index == Argc - 1) && (StrCmp (Argv[Index - 1], L"-m") != 0)) {
> + //
> + // The only parameter that is not an option is the firmware image. Check
> + // to make sure that the file exists.
> + //
> + Status = ShellIsFile (Argv[Index]);
> + if (EFI_ERROR (Status)) {
> + PrintToken (STRING_TOKEN
> (STR_FWUPDATE_FILE_NOT_FOUND_ERROR), HiiHandle, Argv[Index]);
> + return EFI_INVALID_PARAMETER;
> + }
> + if (StrLen (Argv[Index]) > INPUT_STRING_LEN) {
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_PATH_ERROR),
> HiiHandle, Argv[Index]);
> + return EFI_INVALID_PARAMETER;
> + }
> + StrCpy (mInputData.FileName, Argv[Index]);
> + mInputData.UpdateFromFile = TRUE;
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +INTN
> +EFIAPI
> +ShellAppMain (
> + IN UINTN Argc,
> + IN CHAR16 **Argv
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> + UINT32 FileSize;
> + UINT32 BufferSize;
> + UINT8 *FileBuffer;
> + UINT8 *Buffer;
> + EFI_PHYSICAL_ADDRESS Address;
> + UINTN CountOfBlocks;
> + EFI_TPL OldTpl;
> + BOOLEAN ResetRequired;
> + BOOLEAN FlashError;
> +
> + Index = 0;
> + FileSize = 0;
> + BufferSize = 0;
> + FileBuffer = NULL;
> + Buffer = NULL;
> + Address = 0;
> + CountOfBlocks = 0;
> + ResetRequired = FALSE;
> + FlashError = FALSE;
> +
> + Status = EFI_SUCCESS;
> +
> + mInputData.FullFlashUpdate = TRUE;
> +
> + //
> + // Publish our HII data.
> + //
> + HiiHandle = HiiAddPackages (
> + &gEfiCallerIdGuid,
> + NULL,
> + FirmwareUpdateStrings,
> + NULL
> + );
> + if (HiiHandle == NULL) {
> + Status = EFI_OUT_OF_RESOURCES;
> + goto Done;
> + }
> +
> + //
> + // Locate the SPI protocol.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiSpiProtocolGuid,
> + NULL,
> + (VOID **)&mSpiProtocol
> + );
> + if (EFI_ERROR (Status)) {
> + PrintToken (STRING_TOKEN (STR_SPI_NOT_FOUND), HiiHandle);
> + return EFI_DEVICE_ERROR;
> + }
> +
> + //
> + // Parse the command line.
> + //
> + Status = ParseCommandLine (Argc, Argv);
> + if (EFI_ERROR (Status)) {
> + PrintHelpInfo ();
> + Status = EFI_SUCCESS;
> + goto Done;
> + }
> +
> + //
> + // Display sign-on information.
> + //
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_FIRMWARE_VOL_UPDATE),
> HiiHandle);
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_VERSION), HiiHandle);
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_COPYRIGHT), HiiHandle);
> +
> + //
> + // Test to see if the firmware needs to be updated.
> + //
> + if (mInputData.UpdateFromFile) {
> + //
> + // Get the file to use in the update.
> + //
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_READ_FILE), HiiHandle,
> mInputData.FileName);
> + Status = ReadFileData (mInputData.FileName, &FileBuffer, &FileSize);
> + if (EFI_ERROR (Status)) {
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_READ_FILE_ERROR),
> HiiHandle, mInputData.FileName);
> + goto Done;
> + }
> +
> + //
> + // Check that the file and flash sizes match.
> + //
> + if (FileSize != PcdGet32 (PcdFlashChipSize)) {
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_SIZE), HiiHandle);
> + Status = EFI_UNSUPPORTED;
> + goto Done;
> + }
> +
> + //
> + // Display flash update information.
> + //
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_UPDATING_FIRMWARE),
> HiiHandle);
> +
> + //
> + // Update it.
> + //
> + Buffer = FileBuffer;
> + BufferSize = FileSize;
> + Address = PcdGet32 (PcdFlashChipBase);
> + CountOfBlocks = (UINTN) (BufferSize / BLOCK_SIZE);
> +
> + //
> + // Raise TPL to TPL_NOTIFY to block any event handler,
> + // while still allowing RaiseTPL(TPL_NOTIFY) within
> + // output driver during Print().
> + //
> + OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
> + for (Index = 0; Index < CountOfBlocks; Index++) {
> + //
> + // Handle block based on address and contents.
> + //
> + if (!UpdateBlock (Address)) {
> + DEBUG((EFI_D_INFO, "Skipping block at 0x%lx\n", Address));
> + } else if (!EFI_ERROR (InternalCompareBlock (Address, Buffer))) {
> + DEBUG((EFI_D_INFO, "Skipping block at 0x%lx (already
> programmed)\n", Address));
> + } else {
> + //
> + // Display a dot for each block being updated.
> + //
> + Print (L".");
> +
> + //
> + // Flag that the flash image will be changed and the system must be
> rebooted
> + // to use the change.
> + //
> + ResetRequired = TRUE;
> +
> + //
> + // Make updating process uninterruptable,
> + // so that the flash memory area is not accessed by other entities
> + // which may interfere with the updating process.
> + //
> + Status = InternalEraseBlock (Address);
> + ASSERT_EFI_ERROR(Status);
> + if (EFI_ERROR (Status)) {
> + gBS->RestoreTPL (OldTpl);
> + FlashError = TRUE;
> + goto Done;
> + }
> + Status = InternalWriteBlock (
> + Address,
> + Buffer,
> + (BufferSize > BLOCK_SIZE ? BLOCK_SIZE : BufferSize)
> + );
> + if (EFI_ERROR (Status)) {
> + gBS->RestoreTPL (OldTpl);
> + FlashError = TRUE;
> + goto Done;
> + }
> + }
> +
> + //
> + // Move to next block to update.
> + //
> + Address += BLOCK_SIZE;
> + Buffer += BLOCK_SIZE;
> + if (BufferSize > BLOCK_SIZE) {
> + BufferSize -= BLOCK_SIZE;
> + } else {
> + BufferSize = 0;
> + }
> + }
> + gBS->RestoreTPL (OldTpl);
> +
> + //
> + // Print result of update.
> + //
> + if (!FlashError) {
> + if (ResetRequired) {
> + Print (L"\n");
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_UPDATE_SUCCESS),
> HiiHandle);
> + } else {
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_NO_RESET), HiiHandle);
> + }
> + } else {
> + goto Done;
> + }
> + }
> +
> + //
> + // All flash updates are done so see if the system needs to be reset.
> + //
> + if (ResetRequired && !FlashError) {
> + //
> + // Update successful.
> + //
> + for (Index = 5; Index > 0; Index--) {
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_SHUTDOWN), HiiHandle,
> Index);
> + gBS->Stall (1000000);
> + }
> +
> + gRT->ResetSystem (EfiResetShutdown, EFI_SUCCESS, 0, NULL);
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_MANUAL_RESET),
> HiiHandle);
> + CpuDeadLoop ();
> + }
> +
> +Done:
> + //
> + // Print flash update failure message if error detected.
> + //
> + if (FlashError) {
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_UPDATE_FAILED),
> HiiHandle, Index);
> + }
> +
> + //
> + // Do cleanup.
> + //
> + if (HiiHandle != NULL) {
> + HiiRemovePackages (HiiHandle);
> + }
> + if (FileBuffer) {
> + gBS->FreePool (FileBuffer);
> + }
> +
> + return Status;
> +}
> +
> +STATIC
> +EFI_STATUS
> +InternalEraseBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress
> + )
> +/*++
> +
> +Routine Description:
> +
> + Erase the whole block.
> +
> +Arguments:
> +
> + BaseAddress - Base address of the block to be erased.
> +
> +Returns:
> +
> + EFI_SUCCESS - The command completed successfully.
> + Other - Device error or wirte-locked, operation failed.
> +
> +--*/
> +{
> + EFI_STATUS Status;
> + UINTN NumBytes;
> +
> + NumBytes = BLOCK_SIZE;
> +
> + Status = SpiFlashBlockErase ((UINTN) BaseAddress, &NumBytes);
> +
> + return Status;
> +}
> +
> +#if 0
> +STATIC
> +EFI_STATUS
> +InternalReadBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + OUT VOID *ReadBuffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 BlockSize;
> +
> + BlockSize = BLOCK_SIZE;
> +
> + Status = SpiFlashRead ((UINTN) BaseAddress, &BlockSize, ReadBuffer);
> +
> + return Status;
> +}
> +#endif
> +
> +STATIC
> +EFI_STATUS
> +InternalCompareBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + IN UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + VOID *CompareBuffer;
> + UINT32 NumBytes;
> + INTN CompareResult;
> +
> + NumBytes = BLOCK_SIZE;
> + CompareBuffer = AllocatePool (NumBytes);
> + if (CompareBuffer == NULL) {
> + Status = EFI_OUT_OF_RESOURCES;
> + goto Done;
> + }
> +
> + Status = SpiFlashRead ((UINTN) BaseAddress, &NumBytes,
> CompareBuffer);
> + if (EFI_ERROR (Status)) {
> + goto Done;
> + }
> + CompareResult = CompareMem (CompareBuffer, Buffer, BLOCK_SIZE);
> + if (CompareResult != 0) {
> + Status = EFI_VOLUME_CORRUPTED;
> + }
> +
> +Done:
> + if (CompareBuffer != NULL) {
> + FreePool (CompareBuffer);
> + }
> +
> + return Status;
> +}
> +
> +STATIC
> +EFI_STATUS
> +InternalWriteBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + IN UINT8 *Buffer,
> + IN UINT32 BufferSize
> + )
> +/*++
> +
> +Routine Description:
> +
> + Write a block of data.
> +
> +Arguments:
> +
> + BaseAddress - Base address of the block.
> + Buffer - Data buffer.
> + BufferSize - Size of the buffer.
> +
> +Returns:
> +
> + EFI_SUCCESS - The command completed successfully.
> + EFI_INVALID_PARAMETER - Invalid parameter, can not proceed.
> + Other - Device error or wirte-locked, operation failed.
> +
> +--*/
> +{
> + EFI_STATUS Status;
> +
> + Status = SpiFlashWrite ((UINTN) BaseAddress, &BufferSize, Buffer);
> + ASSERT_EFI_ERROR(Status);
> + if (EFI_ERROR (Status)) {
> + DEBUG((EFI_D_ERROR, "\nFlash write error."));
> + return Status;
> + }
> +
> + WriteBackInvalidateDataCacheRange ((VOID *) (UINTN) BaseAddress,
> BLOCK_SIZE);
> +
> + Status = InternalCompareBlock (BaseAddress, Buffer);
> + if (EFI_ERROR (Status)) {
> + DEBUG((EFI_D_ERROR, "\nError when writing to BaseAddress %lx with
> different at offset %x.", BaseAddress, Status));
> + } else {
> + DEBUG((EFI_D_INFO, "\nVerified data written to Block at %lx is correct.",
> BaseAddress));
> + }
> +
> + return Status;
> +
> +}
> +
> +STATIC
> +EFI_STATUS
> +ReadFileData (
> + IN CHAR16 *FileName,
> + OUT UINT8 **Buffer,
> + OUT UINT32 *BufferSize
> + )
> +{
> + EFI_STATUS Status;
> + SHELL_FILE_HANDLE FileHandle;
> + UINT64 Size;
> + VOID *NewBuffer;
> + UINTN ReadSize;
> +
> + FileHandle = NULL;
> + NewBuffer = NULL;
> + Size = 0;
> +
> + Status = ShellOpenFileByName (FileName, &FileHandle,
> EFI_FILE_MODE_READ, 0);
> + if (EFI_ERROR (Status)) {
> + goto Done;
> + }
> +
> + Status = FileHandleIsDirectory (FileHandle);
> + if (!EFI_ERROR (Status)) {
> + Status = EFI_NOT_FOUND;
> + goto Done;
> + }
> +
> + Status = FileHandleGetSize (FileHandle, &Size);
> + if (EFI_ERROR (Status)) {
> + goto Done;
> + }
> +
> + NewBuffer = AllocatePool ((UINTN) Size);
> +
> + ReadSize = (UINTN) Size;
> + Status = FileHandleRead (FileHandle, &ReadSize, NewBuffer);
> + if (EFI_ERROR (Status)) {
> + goto Done;
> + } else if (ReadSize != (UINTN) Size) {
> + Status = EFI_INVALID_PARAMETER;
> + goto Done;
> + }
> +
> +Done:
> + if (FileHandle != NULL) {
> + ShellCloseFile (&FileHandle);
> + }
> +
> + if (EFI_ERROR (Status)) {
> + if (NewBuffer != NULL) {
> + FreePool (NewBuffer);
> + }
> + } else {
> + *Buffer = NewBuffer;
> + *BufferSize = (UINT32) Size;
> + }
> +
> + return Status;
> +}
> +
> +STATIC
> +VOID
> +PrintHelpInfo (
> + VOID
> + )
> +/*++
> +
> +Routine Description:
> +
> + Print out help information.
> +
> +Arguments:
> +
> + None.
> +
> +Returns:
> +
> + None.
> +
> +--*/
> +{
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_FIRMWARE_VOL_UPDATE),
> HiiHandle);
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_VERSION), HiiHandle);
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_COPYRIGHT), HiiHandle);
> +
> + Print (L"\n");
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE), HiiHandle);
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_1), HiiHandle);
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_2), HiiHandle);
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_3), HiiHandle);
> + PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_4), HiiHandle);
> +
> + Print (L"\n");
> +}
> +
> +/**
> + Read NumBytes bytes of data from the address specified by
> + PAddress into Buffer.
> +
> + @param[in] Address The starting physical address of the read.
> + @param[in,out] NumBytes On input, the number of bytes to read. On
> output, the number
> + of bytes actually read.
> + @param[out] Buffer The destination data buffer for the read.
> +
> + @retval EFI_SUCCESS Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiFlashRead (
> + IN UINTN Address,
> + IN OUT UINT32 *NumBytes,
> + OUT UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + UINTN Offset = 0;
> +
> + ASSERT ((NumBytes != NULL) && (Buffer != NULL));
> +
> + Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);
> +
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + 1, //SPI_READ,
> + 0, //SPI_WREN,
> + TRUE,
> + TRUE,
> + FALSE,
> + Offset,
> + BLOCK_SIZE,
> + Buffer,
> + EnumSpiRegionAll
> + );
> + return Status;
> +
> +}
> +
> +/**
> + Write NumBytes bytes of data from Buffer to the address specified by
> + PAddresss.
> +
> + @param[in] Address The starting physical address of the write.
> + @param[in,out] NumBytes On input, the number of bytes to write. On
> output,
> + the actual number of bytes written.
> + @param[in] Buffer The source data buffer for the write.
> +
> + @retval EFI_SUCCESS Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiFlashWrite (
> + IN UINTN Address,
> + IN OUT UINT32 *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Offset;
> + UINT32 Length;
> + UINT32 RemainingBytes;
> +
> + ASSERT ((NumBytes != NULL) && (Buffer != NULL));
> + ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase));
> +
> + Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);
> +
> + ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize));
> +
> + Status = EFI_SUCCESS;
> + RemainingBytes = *NumBytes;
> +
> + while (RemainingBytes > 0) {
> + if (RemainingBytes > SIZE_4KB) {
> + Length = SIZE_4KB;
> + } else {
> + Length = RemainingBytes;
> + }
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_PROG,
> + SPI_WREN,
> + TRUE,
> + TRUE,
> + TRUE,
> + (UINT32) Offset,
> + Length,
> + Buffer,
> + EnumSpiRegionAll
> + );
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + RemainingBytes -= Length;
> + Offset += Length;
> + Buffer += Length;
> + }
> +
> + //
> + // Actual number of bytes written.
> + //
> + *NumBytes -= RemainingBytes;
> +
> + return Status;
> +}
> +
> +/**
> + Erase the block starting at Address.
> +
> + @param[in] Address The starting physical address of the block to be
> erased.
> + This library assume that caller garantee that the PAddress
> + is at the starting address of this block.
> + @param[in] NumBytes On input, the number of bytes of the logical
> block to be erased.
> + On output, the actual number of bytes erased.
> +
> + @retval EFI_SUCCESS. Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiFlashBlockErase (
> + IN UINTN Address,
> + IN UINTN *NumBytes
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Offset;
> + UINTN RemainingBytes;
> +
> + ASSERT (NumBytes != NULL);
> + ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase));
> +
> + Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);
> +
> + ASSERT ((*NumBytes % SIZE_4KB) == 0);
> + ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize));
> +
> + Status = EFI_SUCCESS;
> + RemainingBytes = *NumBytes;
> +
> + while (RemainingBytes > 0) {
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_SERASE,
> + SPI_WREN,
> + FALSE,
> + TRUE,
> + FALSE,
> + (UINT32) Offset,
> + 0,
> + NULL,
> + EnumSpiRegionAll
> + );
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + RemainingBytes -= SIZE_4KB;
> + Offset += SIZE_4KB;
> + }
> +
> + //
> + // Actual number of bytes erased.
> + //
> + *NumBytes -= RemainingBytes;
> +
> + return Status;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +ConvertMac (
> + CHAR16 *Str
> + )
> +{
> + UINTN Index;
> + UINT8 Temp[MAC_ADD_STR_LEN];
> +
> + if (Str == NULL)
> + return EFI_INVALID_PARAMETER;
> +
> + if (StrLen(Str) != MAC_ADD_STR_LEN)
> + return EFI_INVALID_PARAMETER;
> +
> + for (Index = 0; Index < MAC_ADD_STR_LEN; Index++) {
> + if (Str[Index] >= 0x30 && Str[Index] <= 0x39) {
> + Temp[Index] = (UINT8)Str[Index] - 0x30;
> + } else if (Str[Index] >= 0x41 && Str[Index] <= 0x46) {
> + Temp[Index] = (UINT8)Str[Index] - 0x37;
> + } else if (Str[Index] >= 0x61 && Str[Index] <= 0x66) {
> + Temp[Index] = (UINT8)Str[Index] - 0x57;
> + } else {
> + return EFI_INVALID_PARAMETER;
> + }
> + }
> +
> + for (Index = 0; Index < MAC_ADD_BYTE_COUNT; Index++) {
> + mInputData.MacValue[Index] = (Temp[2 * Index] << 4) + Temp[2 * Index
> + 1];
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> Update.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> Update.h
> new file mode 100644
> index 0000000000..745fb3aca4
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> Update.h
> @@ -0,0 +1,185 @@
> +/** @file
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef _FIRMWARE_UPDATE_H_
> +#define _FIRMWARE_UPDATE_H_
> +
> +#include <Uefi.h>
> +
> +#include <PiDxe.h>
> +
> +#include <Guid/FileInfo.h>
> +
> +#include <Protocol/FirmwareVolumeBlock.h>
> +#include <Protocol/LoadedImage.h>
> +#include <Protocol/SimpleFileSystem.h>
> +#include <Protocol/Spi.h>
> +
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/CacheMaintenanceLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/FileHandleLib.h>
> +#include <Library/HiiLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/ShellLib.h>
> +#include <Library/UefiApplicationEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +
> +//
> +// Function Prototypes.
> +//
> +STATIC
> +EFI_STATUS
> +ReadFileData (
> + IN CHAR16 *FileName,
> + OUT UINT8 **Buffer,
> + OUT UINT32 *BufferSize
> + );
> +
> +STATIC
> +EFI_STATUS
> +InternalEraseBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress
> + );
> +
> +#if 0
> +STATIC
> +EFI_STATUS
> +InternalReadBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + OUT VOID *ReadBuffer
> + );
> +#endif
> +
> +STATIC
> +EFI_STATUS
> +InternalCompareBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + IN UINT8 *Buffer
> + );
> +
> +STATIC
> +EFI_STATUS
> +InternalWriteBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + IN UINT8 *Buffer,
> + IN UINT32 BufferSize
> + );
> +
> +STATIC
> +VOID
> +PrintHelpInfo (
> + VOID
> + );
> +
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SpiFlashRead (
> + IN UINTN Address,
> + IN OUT UINT32 *NumBytes,
> + OUT UINT8 *Buffer
> + );
> +
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SpiFlashWrite (
> + IN UINTN Address,
> + IN OUT UINT32 *NumBytes,
> + IN UINT8 *Buffer
> + );
> +
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SpiFlashBlockErase (
> + IN UINTN Address,
> + IN UINTN *NumBytes
> + );
> +
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +ConvertMac (
> + CHAR16 *Str
> + );
> +
> +EFI_STATUS
> +InitializeFVUPDATE (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + );
> +
> +//
> +// Flash specific definitions.
> +// - Should we use a PCD for this information?
> +//
> +#define BLOCK_SIZE SIZE_4KB
> +
> +//
> +// Flash region layout and update information.
> +//
> +typedef struct {
> + EFI_PHYSICAL_ADDRESS Base;
> + UINTN Size;
> + BOOLEAN Update;
> +} FV_REGION_INFO;
> +
> +//
> +// MAC Address information.
> +//
> +#define MAC_ADD_STR_LEN 12
> +#define MAC_ADD_STR_SIZE (MAC_ADD_STR_LEN + 1)
> +#define MAC_ADD_BYTE_COUNT 6
> +#define MAC_ADD_TMP_STR_LEN 2
> +#define MAC_ADD_TMP_STR_SIZE (MAC_ADD_TMP_STR_LEN + 1)
> +
> +//
> +// Command Line Data.
> +//
> +#define INPUT_STRING_LEN 255
> +#define INPUT_STRING_SIZE (INPUT_STRING_LEN + 1)
> +typedef struct {
> + BOOLEAN UpdateFromFile;
> + CHAR16 FileName[INPUT_STRING_SIZE];
> + BOOLEAN UpdateMac;
> + UINT8 MacValue[MAC_ADD_BYTE_COUNT];
> + BOOLEAN FullFlashUpdate;
> +} FV_INPUT_DATA;
> +
> +//
> +// Prefix Opcode Index on the host SPI controller.
> +//
> +typedef enum {
> + SPI_WREN, // Prefix Opcode 0: Write Enable.
> + SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register.
> +} PREFIX_OPCODE_INDEX;
> +
> +//
> +// Opcode Menu Index on the host SPI controller.
> +//
> +typedef enum {
> + SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address.
> + SPI_READ, // Opcode 1: READ, Read cycle with address.
> + SPI_RDSR, // Opcode 2: Read Status Register, No address.
> + SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters,
> No address.
> + SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address.
> + SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address.
> + SPI_PROG, // Opcode 6: Byte Program, Write cycle with address.
> + SPI_WRSR, // Opcode 7: Write Status Register, No address.
> +} SPI_OPCODE_INDEX;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> Update.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> Update.inf
> new file mode 100644
> index 0000000000..25104a86ed
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> Update.inf
> @@ -0,0 +1,83 @@
> +## @file
> +# Implements a Tunnel Mountain specific flash update program. This will
> allow
> +# users to update all regions of the flash as needed in a given update.
> +#
> +# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = FirmwareUpdate
> + FILE_GUID = AEFAF26C-FB6D-4fef-AF7A-9D78FF201FCA
> + MODULE_TYPE = UEFI_APPLICATION
> + VERSION_STRING = 1.0
> + ENTRY_POINT = ShellCEntryLib
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = X64
> +#
> +
> +[Sources]
> + FirmwareUpdateStrings.uni
> + FirmwareUpdate.c
> + FirmwareUpdate.h
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + ShellPkg/ShellPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + CacheMaintenanceLib
> + DebugLib
> + FileHandleLib
> + #FlashDeviceLib
> + #SpiFlashCommonLib
> + MemoryAllocationLib
> + PcdLib
> + ShellCEntryLib
> + ShellLib
> + UefiApplicationEntryPoint
> + UefiBootServicesTableLib
> + UefiLib
> + UefiRuntimeServicesTableLib
> +
> +[Protocols]
> + gEfiLoadedImageProtocolGuid # PROTOCOL ALWAYS_CONSUMED
> + gEfiFirmwareVolumeBlockProtocolGuid # PROTOCOL
> ALWAYS_CONSUMED
> + gEfiSpiProtocolGuid
> +
> +[Pcd]
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize ##
> CONSUMES
> +
> +[FixedPcd]
> +# gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +# gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
> +# gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +# gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
> +# gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +# gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
> +
> + gPlatformModuleTokenSpaceGuid.PcdFlashChipBase
> + gPlatformModuleTokenSpaceGuid.PcdFlashChipSize
> + gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase
> + gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize
> + gPlatformModuleTokenSpaceGuid.PcdTxeRomBase
> + gPlatformModuleTokenSpaceGuid.PcdTxeRomSize
> + gPlatformModuleTokenSpaceGuid.PcdBiosRomBase
> + gPlatformModuleTokenSpaceGuid.PcdBiosRomSize
> +
> +[BuildOptions]
> + MSFT:*_*_X64_CC_FLAGS = /Od
> + INTEL:*_*_X64_CC_FLAGS = /Od
> \ No newline at end of file
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> UpdateStrings.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> UpdateStrings.uni
> new file mode 100644
> index 0000000000..9418edfbf9
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Application/FirmwareUpdate/Firmware
> UpdateStrings.uni
> @@ -0,0 +1,45 @@
> +// *++
> +//
> +// Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// -- *
> +
> +#langdef en-US "English"
> +#langdef fr-FR "Français"
> +
> +#string STR_FWUPDATE_FIRMWARE_VOL_UPDATE #language en-US
> "Intel(R) UDK2014 Firmware Update Utility for the Intel(R) MinnowMax\n"
> +#string STR_FWUPDATE_COPYRIGHT #language en-US "Copyright(c)
> Intel Corporation 2006 - 2014\n"
> + #language fr-FR "Déposer(c) la Société commerciale
> de Intel 2006 - 2014\n"
> +#string STR_FWUPDATE_VERSION #language en-US "Version 0.72\n"
> +
> +#string STR_FWUPDATE_ZEROLENGTH_ARG #language en-US
> "Argument with zero length is not allowed\n"
> + #language fr-FR "L'argument avec zéro longueur n'est
> pas permis\n"
> +#string STR_FWUPDATE_INVAILD_MAC #language en-US "Invalid MAC
> address.\n"
> +
> #string STR_FWUPDATE_READ_FILE #language en-US
> "\nReading file %s\n"
> +#string STR_FWUPDATE_READ_FILE_ERROR #language en-US "Unable to
> read file %s\n"
> +#string STR_FWUPDATE_SIZE #language en-US "File size should be
> 16MB\n"
> + #language fr-FR "Doit être 16 MB\n"
> +#string STR_FWUPDATE_UPDATE_SUCCESS #language en-US "Update
> successful\n"
> + #language fr-FR "Met à jour prospère\n"
> +#string STR_FWUPDATE_UPDATE_FAILED #language en-US "\nUpdate
> failed. Please make sure the flash is not write protected.\n"
> +#string STR_FWUPDATE_RESET #language en-US "\rResetting
> system in %d seconds ..."
> + #language fr-FR "\rLe système qui remettre à l'état
> initial dans %d les secondes ..."
> +#string STR_FWUPDATE_SHUTDOWN #language en-US "\rShutdown
> system in %d seconds ..."
>
> +#string STR_FWUPDATE_MANUAL_RESET #language en-US "\nPls
> manually reset system ...\n"
> + #language fr-FR "\nS'il vous plaît manuellement remet
> à l'état initial le système ...\n"
> +#string STR_FWUPDATE_NO_RESET #language en-US "Already up to
> date\n"
> +#string STR_MISSING_MAC_ARG #language en-US "Option -m
> specified without MAC address.\n"
> +#string STR_INVALID_MAC_ARG #language en-US "Invalid MAC
> address format used (e.g. -m 0011AA33CC55).\n"
> +#string STR_FWUPDATE_FILE_NOT_FOUND_ERROR #language en-US
> "File %s not found.\n"
> +#string STR_FWUPDATE_PATH_ERROR #language en-US "File
> path/name too long.\n"
> +#string STR_FWUPDATE_UPDATING_FIRMWARE #language en-US
> "\nUpdating Firmware. This may take a few minutes.\n"
> +#string STR_FWUPDATE_UPDATING_MAC #language en-US
> "\nUpdating MAC Address.\n"
> +#string STR_SPI_NOT_FOUND #language en-US "\nSPI Protocol is
> not found.\n"
> +
> +#string STR_FWUPDATE_USAGE #language en-US "Usage:
> FirmwareUpdate [IMAGEFILE]\n"
> +#string STR_FWUPDATE_USAGE_1 #language en-US "\n"
> +#string STR_FWUPDATE_USAGE_2 #language en-US " Programs the
> 8MB IMAGEFILE for the MinnowMax.\n"
> +#string STR_FWUPDATE_USAGE_3 #language en-US " \n"
> +#string STR_FWUPDATE_USAGE_4 #language en-US " \n"
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/BfmLib.exe
> b/Platform/Intel/Vlv2TbltDevicePkg/BfmLib.exe
> new file mode 100644
> index
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> z5RYmjru?fgW;mC~P|P<^Fcbpx8<Yz_CL%_C`dLV45#aX1k5AJlIs!#&63PWLj&Y
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> zNYSZ3kKN47Dt4+HQ?w^x!Z%M^lKRJ{-$x35Ctt+{zsnqcCFfnn4)$`)BS-vimu(T)
> zKcvRb`nkp)Y0S~A7yWRfSa<5eLCQb&)J*KqP3dADi+Ie>bovoQHh at S!2Q_?1{
> OyR;
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> zot13f!E+;Sz_zwd78B~s=UAJ>p6zIspXiYGR6{tqdIvw+^c5B)&O9=4%;r$(<>Kh
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> zVoTys=_Ne2af0Pg>0)`QEyL3N|Hym)__(Vo|9_fJ=+LH2z*H(fgDqHT!D>MYX_
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> zo*VKo at 5Qon|1nx9(tasZ3jXQ*G|yUnGKv+Auc`WBHLF=dR at 0F9_h<54IIn<e
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> zvXMzkmw%#gWO)=ES=dZol+J5{I^I=U2S*mp_P)zN3+r$>T^%ayx%2S0JYwY>
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> z_+ubcy({ezdzvnf9r&u42D|(kF1$$8ly5;tUClxXR~5HV>gAhWBVc1+a8!K*BQ&
> =1
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> z=%p&FORDtYBfu>f+U$T3u|<%KNO6$pR5KzHLg8Zev%p0IT2b~R213CfB+8*V
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> z;I8apMKX0@)<G4EU1vKKTrG7VySRcIn}ExfMR&DJ03Quuzcvgbco=9;n8L`cs82
> ok
> zGoaWRQTu3 at eiL7RTz?K8VZRh%A)tO(OF+$jvw`v{5^M@#I#mcZvwZY%hZIq
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> *=h$*AN?MyI<T5y
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> zJz!`#ZdZDgC?=UN=~a`<>{N!<{jqhZESU^%kg#R9pTcL=T2Ap(6*kAMXBZ~%c=
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> zs#UvCSi`p4I>0=bT|0cUdggBGqxbfL9s(~H>AkQ0qNMkfG1hXiSNZcu?}hnY?+J
> =`
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> zGZfA+?mIUG)kdcEd40AU3}mG8<vRp0+cYw8^(20YV<)&W*~~hFt502pleeF
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> zog45561GiXt{u&a!z##+#kMeud0aYBP6}1poEwmHfSNwgPfZyg?PQ3?6R+_AT
> z5YK
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> +oKQc+!
> z1^KRUnj{;`=7D$fy=?!?Z1N=^m)H?}ik&25aerVRA6YC$i>wf7yGH8x`YgBhv10N
> 8
> zhLSs1kSwIeawtnM#1Z|un?Jygi($II2%1|>f?D~CL1Czsc(~z$m~mO6R;Mx_hx
> Q3_
> z^f#2am+hFL^J09olVP%Xeh<_8%yT|RI~nq1B};r;8nm=<%}AGPb}=`&hQHLJ(N
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> =WRAe}#7gV!n;AGGNa5XeYyD%v+h>hdH04oeZ7uqO{U1&F!FO3v&Z=
> z{wn5j7tX8Q;$nUoFpp170E&$BOU?%H7-
> sP~I}<P`U8#Ke2+YMqdfV8k4YY{`XQ(FQ
> zqn!+stGR*cebwZ1w38te+m|yD)>hRvQkW1>RsL#K<t~!0&TLLgq$W2fe>JDv
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> z3{iFL^>xg0=pH%^xuwi1gZ^y)T0%`%@QjXjGECV1TVwzsIHoH2Y61Z*`Kt<^clb
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> zBch!QQ69bj1C)0S0c0qT at zG9(GzI-bk-XLiGBIN+`<E$TA;AitlZNrpPKF8gCxzbQ
> z5G-7tAYMP?x?)02Z(Bx3I~h9RX at 0VUcetFar?j at 7P1ZIQO;&8~mYz(R_-
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> zpY)}D8fnQv?7FT-
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> zW!ZP3q)b?rvc7IES9Y(Q1b;Br+ at qM&o`zxNo{KSYzGOD1z$AseyCk8cu=k_DQ)
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> 68r(vk
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> zjq4^{TX205moqeL=%As4hh}s0RbnKgH=wU2E_q;#QZ{im0lnoM5PeJAC;ka6l9
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> Z?tP at 4ETG%X2LX=K57
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> pjUc
> z2eTG%qx(bnsU1BBUSj0C8$|3rbr5=kQEtrbjLBxqNH-
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> z<^{&|3T1lDm58Z5;y#q3(%lc at HTTs<4-JOvLRL|0h1j3Jg*R_uk6cO>JIb+Zjsvf#
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> z0XODLjM>eY{ccPvW4_0jE;pu`G50X$2{&d1V`wJSKJ3OUK}`I!D)Wi$ug{m5FA
> Wxz
> zBxb;Ok%nY1g)IYv7wdyy5`f#Lq4}tJsz7&azLI4H*nJxpb_*2OK7cZ$W4bn|?1r?L
> zu#N6>3xAP<fum6Aj|Tjw`8Y2HmnTXLPXxCEo3mY9o`GrT$K~7SDlR_*l_Bp(^
> W+=k
> zY`FH&_Ku?M(eC-
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> z;fpc&lq?);V{5kwQQk0vsf+pf415Eyc9R=<BEZO85<Ve{=!I_d&mdYr320!e4DFA
> r
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> zXXBU!DFz7x!-sbqJ>OY?Io$=$Rk*g};s{^=rJoQn2sky^bXjo4@}Jk0dir*j`ByBS
> zg8-atw#yB_lbiC<fY5#n4EdG%9FR~o6n0+XjDD4{-
> R{AHMbEe68}pmHuFbpsLC~wC
> z96t2V1+%H5+8q42y3KB1s9g!=Nv3#MnWFnqWU9SJH0oh<6x<oVskYdCJi^Bt
> Y8SeX
> zukx{|_Hy^}B|grno#a0LkdIT$;ZKT>NcvpVUL?PEEYt9e>Jvu`pMZxCo0HLZv46d
> Q
> zaro9t7^|rc%WA4#fD#V>J0Pd3qsPpjLXOsz8S6<BWvSrc1x_KZWw=)2x)ayUx
> VGSW
> z5|=~1`I!G;c7h?bVbOnz1oY^k1-SR0{_LK&f$zfhihb|zXJ2P?SsyMPJJ^m!lZW5+
> z7`A>P96RVZA0C2^bBmC;*Q}s4&Z*ttK9=xtO8mmwCO2X(BhF6rh8OYCb at 2S
> oH7#zn
> z7;vUc3il0_4bJ1kIcm}Fi*TGVrp<;z1D3x5emV#&z)vsZ$ERp<y2l(@1Inp&)DOi`
> zKa#tCim?nx;f?eoT0WIP$I;ipm%QF~uPneFjO%3gYQpaqaAlGp(0l7)n%=e|7~8
> =S
> zofz9~0{^)K&cQTftaTZEZ{{XFdqV8g*|!E0w8udgc8f3VMd01tg+9y6`sPgdL6gJ|
> z{5m0WeIf;1S-
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> zVQ?Y?qK?{Ka^qb*gGfvn`fuddUgHgO9ohuGQ)ukG)?tu9_80D<BM0z(Pc4bPh
> }i*=
> z^2ivzSk7pZ<Er+Tn16pv%}(qfDDNsYJ=)oH!2gBuk7O at F_BhUedjqxLQA&opIY
> 4`P
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> mYIxq=4Ycsd!7~xJydMI
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> H&4`d
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> zNC8jN*MuJWyPyIrh{;%6+qMF!__74+X?JobVyU^w?P_tp06hZ4p$j;yNv!XF5
> 5z$$
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> z9y9zSO&bha#KZ7W<=BSyXZ(-
> 6G at wSWS&Miv$Z16db&N^{^bbHPe!04PSSCM_%rn@`
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> hpqd^Zrh>5V5{0fd!mN
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> z4nTg1eBBhRrAJ|PEUdg|`tD+o<FI)T`WDoMQI2<Kp`XJ8&cB464cxG8o=>Zwu
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> zL|f+LN#bd97N at QGj2`6LYc8^x3=2$kg<}2#Eo29CH6S*bAKx$um;)!vgD}4Ims}
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> +
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> 3Y
> zI14~|{zaZkKfaSTanyleaHPw)bbk`SG}xW!_Zq-!J)r*u0Q#>7 at IB_e^HvDoQvk-
> {
> z-
> T}i6c`gKmH2tgLGVOxrKMB_Xa5L(B0Oy>{E6c(BOaqwbn>_bsxWvB`K>RHLrt?d
> H
> zHv>N6z26I$`MDp!^ga$?xX%HYzdr#G|8)TI=YlEZkKx&pcY*hSr*BQ_x>#~&QY
> {3`
> zLzpm}`~IYQ{;s4t0=NfI1Ec}w$MF0aSKj>h+5B7KThTG$XLC*bm(zXW!%6iV;3#1
> 8
> zJHfy2L*^M7y2t5!39_}g<xdiKTK-
> ;w%)JCjv^Ih*iMKYw{1RmDB}$@Y6JRsMuVoW(
> zH2OcwzyIJ(;oNs(J~)5jqWke-
> 9KCt(%@=s}^09Bq!@a*I?oGdX^aVa`dB?PNA3*p&
> zxbMmP96>kzzv)NfwZ(HkGso~TFZ^c_{!c&p^heKA-
> }>k?ALY(W at YkUKj(c^CEAb(}
> z^2xV7>8Oz>uX}P$FfiV3`r47dJo-
> bW+TS5DAADuEzQYywLYgtZDdI_bY`LvFK;dNH
> zna^-ukG<DV<AH^caeGy_dgyGp at ZXB`8J;fdn(GAq0-5>`_%d&n-~7;Tf%h{-
> B at d?c
> zj*js;K6lB(u)PFW2zcRh{`>~b at DS%k{JjCsoM-a)e(U+Yc;+0EzuT?n_gT+(SkIWF
> zHNyY0^?axGjP9c6r+eVCSe&DEd=+ysxaYv--0$dDk{Y)aE(huJ;c`y*?BS%Is~(2?
> zQ+U4{F6YKMxKxO|8SZ&-7s7o#+{gY1ddT435BF!_-
> U9b$;W}^~xX*k!sV;zf><@95
> z67GRVlelq&aB%m+t-
> *y^H<g3S!DJLJ8)S;E)i&+t>9Vx at W8amwn;Ozbdx&*nzf{-B
> z#ee=6p~G>%^sQJGw-
> 5Ajz8pXDtZjvysPLhH%WBTD+}V1b_QHXrdhl1IoU9|Z4+6_-
> zes+m$oz(PanAFAu^h(YS4Bx9DD~U1T6BzIKOaBD)%K>@;TLE2wEr88{b$}Is3jy
> Z>
> z&H*e0JpXFwUjrNiJPUXR at HF5k;3>cnz!QMS0gnL=0}cTW0v-
> h14`BGa0e1oR1Ev9c
> z00qD(U?<=zKrf&JumbQZFvg5^tKZuVef4OoaGyUkJN$z8JBIM2!MJqEbAtJipK
> QZF
> z2iO5%JN*FQGk_-
> m{{(mqBCZDX1113`4i!goUA7y5{;duIz6SUnU@^k20`vh20Q1||
> zhO(}ax>$L6Y};5SH^S3REg`c7`c1cN3E;yx-a96Q=}?daDig;`h#$r=jVvyVdE^81
> ziDTS+&S0VY&C1`%2$XJ)RBE;SNNMak?0fscbdkbob at BMO9~Z|$<)EHK&pSZB
> Y$5D)
> z%QhjTWaBgn_s?qesv&9Ed&WJ(fioO9!+|p#IKzQ695};)GaNX>fioO9!+|p#IKz
> Q6
> K9QaSjfqw%w5I}YS
>
> literal 0
> HcmV?d00001
>
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/BiosIdD.env
> b/Platform/Intel/Vlv2TbltDevicePkg/BiosIdD.env
> new file mode 100644
> index 0000000000..85313dfbd7
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/BiosIdD.env
> @@ -0,0 +1,25 @@
> +#/** @file
> +# This file is used to define the BIOS ID parameters of the build.
> +# This file is processed by GenBiosId.
> +# The BIOS ID format conforms to "BIOS Revision Identification
> Specification", Rev. 0.7, 6/27/2001.
> +#
> +# BIOS ID string format:
> +#
> $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE
> )$(VERSION_MINOR).YYMMDDHHMM
> +# All fields must have a fixed length.
> +# Example: "TRFTCRB1.86C.0008.D03.0506081529"
> +#
> +# Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#**/
> +
> +BOARD_REV = 1
> +OEM_ID = I32
> +BUILD_TYPE = D
> +
> +BOARD_ID = BLAKCRB
> +VERSION_MAJOR = 0084
> +VERSION_MINOR = 01
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/BiosIdR.env
> b/Platform/Intel/Vlv2TbltDevicePkg/BiosIdR.env
> new file mode 100644
> index 0000000000..4af249dc19
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/BiosIdR.env
> @@ -0,0 +1,25 @@
> +#/** @file
> +# This file is used to define the BIOS ID parameters of the build.
> +# This file is processed by GenBiosId.
> +# The BIOS ID format conforms to "BIOS Revision Identification
> Specification", Rev. 0.7, 6/27/2001.
> +#
> +# BIOS ID string format:
> +#
> $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE
> )$(VERSION_MINOR).YYMMDDHHMM
> +# All fields must have a fixed length.
> +# Example: "TRFTCRB1.86C.0008.D03.0506081529"
> +#
> +# Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#**/
> +
> +BOARD_REV = 1
> +OEM_ID = I32
> +BUILD_TYPE = R
> +
> +BOARD_ID = BLAKCRB
> +VERSION_MAJOR = 0084
> +VERSION_MINOR = 01
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/BiosIdx64D.env
> b/Platform/Intel/Vlv2TbltDevicePkg/BiosIdx64D.env
> new file mode 100644
> index 0000000000..a2173b7e44
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/BiosIdx64D.env
> @@ -0,0 +1,25 @@
> +#/** @file
> +# This file is used to define the BIOS ID parameters of the build.
> +# This file is processed by GenBiosId.
> +# The BIOS ID format conforms to "BIOS Revision Identification
> Specification", Rev. 0.7, 6/27/2001.
> +#
> +# BIOS ID string format:
> +#
> $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE
> )$(VERSION_MINOR).YYMMDDHHMM
> +# All fields must have a fixed length.
> +# Example: "TRFTCRB1.86C.0008.D03.0506081529"
> +#
> +# Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#**/
> +
> +BOARD_REV = 1
> +OEM_ID = X64
> +BUILD_TYPE = D
> +
> +VERSION_MAJOR = 0084
> +VERSION_MINOR = 01
> +BOARD_ID = BBAYCRB
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/BiosIdx64R.env
> b/Platform/Intel/Vlv2TbltDevicePkg/BiosIdx64R.env
> new file mode 100644
> index 0000000000..c235177e1b
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/BiosIdx64R.env
> @@ -0,0 +1,25 @@
> +#/** @file
> +# This file is used to define the BIOS ID parameters of the build.
> +# This file is processed by GenBiosId.
> +# The BIOS ID format conforms to "BIOS Revision Identification
> Specification", Rev. 0.7, 6/27/2001.
> +#
> +# BIOS ID string format:
> +#
> $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE
> )$(VERSION_MINOR).YYMMDDHHMM
> +# All fields must have a fixed length.
> +# Example: "TRFTCRB1.86C.0008.D03.0506081529"
> +#
> +# Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#**/
> +
> +BOARD_REV = 1
> +OEM_ID = X64
> +BUILD_TYPE = R
> +
> +VERSION_MAJOR = 0084
> +VERSION_MINOR = 01
> +BOARD_ID = BBAYCRB
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.i
> nf
> b/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.i
> nf
> new file mode 100644
> index 0000000000..d2fa621096
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.i
> nf
> @@ -0,0 +1,60 @@
> +#
> +#
> +## @file
> +# Component description file for ScriptSave Lite module.
> +#
> +# This is an implementation of the Boot Script Save protocol.
> +# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = BootScriptSaveDxe
> + FILE_GUID = 42BB673D-09F3-4e2e-9FEE-D081131DED5B
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> +
> + ENTRY_POINT = InitializeScriptSave
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + ScriptSave.c
> + InternalBootScriptSave.h
> +
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> +
> +
> +[LibraryClasses]
> + PcdLib
> + UefiRuntimeServicesTableLib
> + UefiBootServicesTableLib
> + MemoryAllocationLib
> + UefiDriverEntryPoint
> + BaseMemoryLib
> + DebugLib
> + BaseLib
> + S3BootScriptLib
> +
> +[Protocols]
> + gEfiBootScriptSaveProtocolGuid # PROTOCOL ALWAYS_PRODUCED
> +
> +
> +[Depex]
> + TRUE
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptS
> ave.h
> b/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptS
> ave.h
> new file mode 100644
> index 0000000000..f232281e2b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptS
> ave.h
> @@ -0,0 +1,102 @@
> +/** @file
> +//
> +//
> + Internal header file for S3 Boot Script Saver driver.
> +
> + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef _INTERNAL_BOOT_SCRIPT_SAVE_H_
> +#define _INTERNAL_BOOT_SCRIPT_SAVE_H_
> +#include <FrameworkDxe.h>
> +
> +#include <Protocol/BootScriptSave.h>
> +#include <Protocol/FirmwareVolume.h>
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Library/S3BootScriptLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/SmbusLib.h>
> +#include <IndustryStandard/SmBus.h>
> +
> +/**
> + Adds a record into a specified Framework boot script table.
> +
> + This function is used to store a boot script record into a given boot
> + script table. If the table specified by TableName is nonexistent in the
> + system, a new table will automatically be created and then the script
> record
> + will be added into the new table. A boot script table can add new script
> records
> + until EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable() is called. Currently,
> the only
> + meaningful table name is EFI_ACPI_S3_RESUME_SCRIPT_TABLE. This
> function is
> + responsible for allocating necessary memory for the script.
> +
> + This function has a variable parameter list. The exact parameter list
> depends on
> + the OpCode that is passed into the function. If an unsupported OpCode or
> illegal
> + parameter list is passed in, this function returns EFI_INVALID_PARAMETER.
> + If there are not enough resources available for storing more scripts, this
> function returns
> + EFI_OUT_OF_RESOURCES.
> +
> + @param[in] This A pointer to the
> EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.
> + @param[in] TableName Name of the script table. Currently, the only
> meaningful value is
> + EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
> + @param[in] OpCode The operation code (opcode) number.
> + @param[in] ... Argument list that is specific to each opcode.
> +
> + @retval EFI_SUCCESS The operation succeeded. A record was added
> into the
> + specified script table.
> + @retval EFI_INVALID_PARAMETER The parameter is illegal or the given
> boot script is not supported.
> + If the opcode is unknow or not supported because of the
> PCD
> + Feature Flags.
> + @retval EFI_OUT_OF_RESOURCES There is insufficient memory to store
> the boot script.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BootScriptWrite (
> + IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL *This,
> + IN UINT16 TableName,
> + IN UINT16 OpCode,
> + ...
> + );
> +
> +/**
> + Closes the specified script table.
> +
> + This function closes the specified boot script table and returns the base
> address
> + of the table. It allocates a new pool to duplicate all the boot scripts in the
> specified
> + table. Once this function is called, the specified table will be destroyed
> after it is
> + copied into the allocated pool. As a result, any attempts to add a script
> record into a
> + closed table will cause a new table to be created. The base address of the
> allocated pool
> + will be returned in Address. After using the boot script table, the caller is
> responsible
> + for freeing the pool that is allocated by this function. If the boot script table,
> + such as EFI_ACPI_S3_RESUME_SCRIPT_TABLE, is required to be stored in a
> nonperturbed
> + memory region, the caller should copy the table into the nonperturbed
> memory region by itself.
> +
> + @param[in] This A pointer to the
> EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.
> + @param[in] TableName Name of the script table. Currently, the only
> meaningful value is
> + EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
> + @param[in] Address A pointer to the physical address where the
> table begins.
> +
> + @retval EFI_SUCCESS The table was successfully returned.
> + @retval EFI_NOT_FOUND The specified table was not created
> previously.
> + @retval EFI_OUT_OF_RESOURCE Memory is insufficient to hold the
> reorganized boot script table.
> + @retval EFI_UNSUPPORTED The table type is not
> EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BootScriptCloseTable (
> + IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL *This,
> + IN UINT16 TableName,
> + OUT EFI_PHYSICAL_ADDRESS *Address
> + );
> +#endif //_INTERNAL_BOOT_SCRIPT_SAVE_H_
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c
> b/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c
> new file mode 100644
> index 0000000000..837a8c95cd
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c
> @@ -0,0 +1,626 @@
> +/** @file
> + Implementation for S3 Boot Script Saver driver.
> +
> +Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include "InternalBootScriptSave.h"
> +
> +EFI_HANDLE mHandle = NULL;
> +EFI_BOOT_SCRIPT_SAVE_PROTOCOL mS3ScriptSave = {
> + BootScriptWrite,
> + BootScriptCloseTable
> + };
> +
> +/**
> + Internal function to add IO write opcode to the table.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptIoWrite (
> + IN VA_LIST Marker
> + )
> +{
> + S3_BOOT_SCRIPT_LIB_WIDTH Width;
> + UINT64 Address;
> + UINTN Count;
> + UINT8 *Buffer;
> +
> + Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
> + Address = VA_ARG (Marker, UINT64);
> + Count = VA_ARG (Marker, UINTN);
> + Buffer = VA_ARG (Marker, UINT8 *);
> +
> + return S3BootScriptSaveIoWrite (Width, Address, Count, Buffer);
> +}
> +
> +/**
> + Internal function to add IO read/write opcode to the table.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptIoReadWrite (
> + IN VA_LIST Marker
> + )
> +{
> + S3_BOOT_SCRIPT_LIB_WIDTH Width;
> + UINT64 Address;
> + UINT8 *Data;
> + UINT8 *DataMask;
> +
> + Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
> + Address = VA_ARG (Marker, UINT64);
> + Data = VA_ARG (Marker, UINT8 *);
> + DataMask = VA_ARG (Marker, UINT8 *);
> +
> + return S3BootScriptSaveIoReadWrite (Width, Address, Data, DataMask);
> +}
> +
> +/**
> + Internal function to add memory write opcode to the table.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptMemWrite (
> + IN VA_LIST Marker
> + )
> +{
> + S3_BOOT_SCRIPT_LIB_WIDTH Width;
> + UINT64 Address;
> + UINTN Count;
> + UINT8 *Buffer;
> +
> + Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
> + Address = VA_ARG (Marker, UINT64);
> + Count = VA_ARG (Marker, UINTN);
> + Buffer = VA_ARG (Marker, UINT8 *);
> +
> + return S3BootScriptSaveMemWrite (Width, Address, Count, Buffer);
> +}
> +
> +/**
> + Internal function to add memory read/write opcode to the table.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptMemReadWrite (
> + IN VA_LIST Marker
> + )
> +{
> + S3_BOOT_SCRIPT_LIB_WIDTH Width;
> + UINT64 Address;
> + UINT8 *Data;
> + UINT8 *DataMask;
> +
> + Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
> + Address = VA_ARG (Marker, UINT64);
> + Data = VA_ARG (Marker, UINT8 *);
> + DataMask = VA_ARG (Marker, UINT8 *);
> +
> + return S3BootScriptSaveMemReadWrite (Width, Address, Data, DataMask);
> +}
> +
> +/**
> + Internal function to add PciCfg write opcode to the table.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptPciCfgWrite (
> + IN VA_LIST Marker
> + )
> +{
> + S3_BOOT_SCRIPT_LIB_WIDTH Width;
> + UINT64 Address;
> + UINTN Count;
> + UINT8 *Buffer;
> +
> + Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
> + Address = VA_ARG (Marker, UINT64);
> + Count = VA_ARG (Marker, UINTN);
> + Buffer = VA_ARG (Marker, UINT8 *);
> +
> + return S3BootScriptSavePciCfgWrite (Width, Address, Count, Buffer);
> +}
> +
> +/**
> + Internal function to PciCfg read/write opcode to the table.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptPciCfgReadWrite (
> + IN VA_LIST Marker
> + )
> +{
> + S3_BOOT_SCRIPT_LIB_WIDTH Width;
> + UINT64 Address;
> + UINT8 *Data;
> + UINT8 *DataMask;
> +
> + Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
> + Address = VA_ARG (Marker, UINT64);
> + Data = VA_ARG (Marker, UINT8 *);
> + DataMask = VA_ARG (Marker, UINT8 *);
> +
> + return S3BootScriptSavePciCfgReadWrite (Width, Address, Data,
> DataMask);
> +}
> +
> +/**
> + Internal function to add PciCfg2 write opcode to the table.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptPciCfg2Write (
> + IN VA_LIST Marker
> + )
> +{
> + S3_BOOT_SCRIPT_LIB_WIDTH Width;
> + UINT64 Address;
> + UINTN Count;
> + UINT8 *Buffer;
> + UINT16 Segment;
> +
> + Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
> + Address = VA_ARG (Marker, UINT64);
> + Count = VA_ARG (Marker, UINTN);
> + Buffer = VA_ARG (Marker, UINT8 *);
> + Segment = VA_ARG (Marker, UINT16);
> +
> + return S3BootScriptSavePciCfg2Write (Width, Segment, Address, Count,
> Buffer);
> +}
> +
> +/**
> + Internal function to PciCfg2 read/write opcode to the table.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptPciCfg2ReadWrite (
> + IN VA_LIST Marker
> + )
> +{
> + S3_BOOT_SCRIPT_LIB_WIDTH Width;
> + UINT16 Segment;
> + UINT64 Address;
> + UINT8 *Data;
> + UINT8 *DataMask;
> +
> + Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
> + Address = VA_ARG (Marker, UINT64);
> + Segment = VA_ARG (Marker, UINT16);
> + Data = VA_ARG (Marker, UINT8 *);
> + DataMask = VA_ARG (Marker, UINT8 *);
> +
> + return S3BootScriptSavePciCfg2ReadWrite (Width, Segment, Address, Data,
> DataMask);
> +}
> +
> +/**
> + Internal function to add smbus execute opcode to the table.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptSmbusExecute (
> + IN VA_LIST Marker
> + )
> +{
> + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
> + EFI_SMBUS_DEVICE_COMMAND Command;
> + EFI_SMBUS_OPERATION Operation;
> + BOOLEAN PecCheck;
> + VOID *Buffer;
> + UINTN *DataSize;
> + UINTN SmBusAddress;
> +
> + SlaveAddress.SmbusDeviceAddress = VA_ARG (Marker, UINTN);
> + Command = VA_ARG (Marker,
> EFI_SMBUS_DEVICE_COMMAND);
> + Operation = VA_ARG (Marker, EFI_SMBUS_OPERATION);
> + PecCheck = VA_ARG (Marker, BOOLEAN);
> + SmBusAddress = SMBUS_LIB_ADDRESS
> (SlaveAddress.SmbusDeviceAddress,Command,0,PecCheck);
> + DataSize = VA_ARG (Marker, UINTN *);
> + Buffer = VA_ARG (Marker, VOID *);
> +
> + return S3BootScriptSaveSmbusExecute (SmBusAddress, Operation,
> DataSize, Buffer);
> +}
> +
> +/**
> + Internal function to add stall opcode to the table.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptStall (
> + IN VA_LIST Marker
> + )
> +{
> + UINT32 Duration;
> +
> + Duration = VA_ARG (Marker, UINT32);
> +
> + return S3BootScriptSaveStall (Duration);
> +}
> +
> +/**
> + Internal function to add Save jmp address according to DISPATCH_OPCODE.
> + We ignore "Context" parameter.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptDispatch (
> + IN VA_LIST Marker
> + )
> +{
> + VOID *EntryPoint;
> +
> + EntryPoint = (VOID*)(UINTN)VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);
> + return S3BootScriptSaveDispatch (EntryPoint);
> +}
> +
> +/**
> + Internal function to add memory pool operation to the table.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptMemPoll (
> + IN VA_LIST Marker
> + )
> +{
> + S3_BOOT_SCRIPT_LIB_WIDTH Width;
> + UINT64 Address;
> + UINT8 *BitMask;
> + UINT8 *BitValue;
> + UINTN Duration;
> + UINT64 LoopTimes;
> +
> + Width = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);
> + Address = VA_ARG (Marker, UINT64);
> + BitMask = VA_ARG (Marker, UINT8 *);
> + BitValue = VA_ARG (Marker, UINT8 *);
> + Duration = (UINTN)VA_ARG (Marker, UINT64);
> + LoopTimes = VA_ARG (Marker, UINT64);
> +
> + return S3BootScriptSaveMemPoll (Width, Address, BitMask, BitValue,
> Duration, LoopTimes);
> +}
> +
> +/**
> + Internal function to add Save jmp address according to
> DISPATCH_OPCODE2.
> + The "Context" parameter is not ignored.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enough resource to do operation.
> + @retval EFI_SUCCESS Opcode is added.
> +
> +**/
> +EFI_STATUS
> +BootScriptDispatch2 (
> + IN VA_LIST Marker
> + )
> +{
> + VOID *EntryPoint;
> + VOID *Context;
> +
> + EntryPoint = (VOID*)(UINTN)VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);
> + Context = (VOID*)(UINTN)VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);
> +
> + return S3BootScriptSaveDispatch2 (EntryPoint, Context);
> +}
> +
> +/**
> + Internal function to add the opcode link node to the link list.
> +
> + @param Marker The variable argument list to get the opcode
> + and associated attributes.
> +
> + @retval EFI_OUT_OF_RESOURCES Not enought resource to complete the
> operations.
> + @retval EFI_SUCCESS The opcode entry is added to the link list
> + successfully.
> +**/
> +EFI_STATUS
> +BootScriptInformation (
> + IN VA_LIST Marker
> + )
> +{
> + UINT32 InformationLength;
> + EFI_PHYSICAL_ADDRESS Information;
> +
> + InformationLength = VA_ARG (Marker, UINT32);
> + Information = VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);
> + return S3BootScriptSaveInformation (InformationLength,
> (VOID*)(UINTN)Information);
> +}
> +
> +/**
> + Adds a record into a specified Framework boot script table.
> +
> + This function is used to store a boot script record into a given boot
> + script table. If the table specified by TableName is nonexistent in the
> + system, a new table will automatically be created and then the script
> record
> + will be added into the new table. A boot script table can add new script
> records
> + until EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable() is called. Currently,
> the only
> + meaningful table name is EFI_ACPI_S3_RESUME_SCRIPT_TABLE. This
> function is
> + responsible for allocating necessary memory for the script.
> +
> + This function has a variable parameter list. The exact parameter list
> depends on
> + the OpCode that is passed into the function. If an unsupported OpCode or
> illegal
> + parameter list is passed in, this function returns EFI_INVALID_PARAMETER.
> + If there are not enough resources available for storing more scripts, this
> function returns
> + EFI_OUT_OF_RESOURCES.
> +
> + @param This A pointer to the
> EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.
> + @param TableName Name of the script table. Currently, the only
> meaningful value is
> + EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
> + @param OpCode The operation code (opcode) number.
> + @param ... Argument list that is specific to each opcode.
> +
> + @retval EFI_SUCCESS The operation succeeded. A record was added
> into the
> + specified script table.
> + @retval EFI_INVALID_PARAMETER The parameter is illegal or the given
> boot script is not supported.
> + If the opcode is unknow or not supported because of the
> PCD
> + Feature Flags.
> + @retval EFI_OUT_OF_RESOURCES There is insufficient memory to store
> the boot script.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BootScriptWrite (
> + IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL *This,
> + IN UINT16 TableName,
> + IN UINT16 OpCode,
> + ...
> + )
> +{
> + EFI_STATUS Status;
> + VA_LIST Marker;
> +
> + if (TableName != FRAMEWORK_EFI_ACPI_S3_RESUME_SCRIPT_TABLE) {
> + //
> + // Only S3 boot script is supported for now.
> + //
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + //
> + // Build script according to opcode.
> + //
> + switch (OpCode) {
> +
> + case EFI_BOOT_SCRIPT_IO_WRITE_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptIoWrite (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptIoReadWrite (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptMemWrite (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptMemReadWrite (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptPciCfgWrite (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptPciCfgReadWrite (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptSmbusExecute (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_STALL_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptStall (Marker);
> + VA_END (Marker);
> +
> + break;
> +
> + case EFI_BOOT_SCRIPT_DISPATCH_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptDispatch (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptDispatch2 (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_INFORMATION_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptInformation (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_MEM_POLL_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptMemPoll (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptPciCfg2Write (Marker);
> + VA_END (Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE:
> + VA_START (Marker, OpCode);
> + Status = BootScriptPciCfg2ReadWrite (Marker);
> + VA_END (Marker);
> + break;
> +
> + default:
> + Status = EFI_INVALID_PARAMETER;
> + break;
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Closes the specified script table.
> +
> + This function closes the specified boot script table and returns the base
> address
> + of the table. It allocates a new pool to duplicate all the boot scripts in the
> specified
> + table. Once this function is called, the specified table will be destroyed
> after it is
> + copied into the allocated pool. As a result, any attempts to add a script
> record into a
> + closed table will cause a new table to be created. The base address of the
> allocated pool
> + will be returned in Address. After using the boot script table, the caller is
> responsible
> + for freeing the pool that is allocated by this function. If the boot script table,
> + such as EFI_ACPI_S3_RESUME_SCRIPT_TABLE, is required to be stored in a
> nonperturbed
> + memory region, the caller should copy the table into the nonperturbed
> memory region by itself.
> +
> + @param This A pointer to the
> EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.
> + @param TableName Name of the script table. Currently, the only
> meaningful value is
> + EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
> + @param Address A pointer to the physical address where the table
> begins.
> +
> + @retval EFI_SUCCESS The table was successfully returned.
> + @retval EFI_NOT_FOUND The specified table was not created
> previously.
> + @retval EFI_OUT_OF_RESOURCE Memory is insufficient to hold the
> reorganized boot script table.
> + @retval EFI_UNSUPPORTED The table type is not
> EFI_ACPI_S3_RESUME_SCRIPT_TABLE.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BootScriptCloseTable (
> + IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL *This,
> + IN UINT16 TableName,
> + OUT EFI_PHYSICAL_ADDRESS *Address
> + )
> +{
> + if (TableName != FRAMEWORK_EFI_ACPI_S3_RESUME_SCRIPT_TABLE) {
> + //
> + // Only S3 boot script is supported for now.
> + //
> + return EFI_NOT_FOUND;
> + }
> + *Address = (EFI_PHYSICAL_ADDRESS)(UINTN)S3BootScriptCloseTable ();
> +
> + if (*Address == 0) {
> + return EFI_NOT_FOUND;
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This routine is entry point of ScriptSave driver.
> +
> + @param ImageHandle Handle for this drivers loaded image protocol.
> + @param SystemTable EFI system table.
> +
> + @retval EFI_OUT_OF_RESOURCES No enough resource.
> + @retval EFI_SUCCESS Succesfully installed the ScriptSave driver.
> + @retval other Errors occured.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeScriptSave (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + return gBS->InstallProtocolInterface (
> + &mHandle,
> + &gEfiBootScriptSaveProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + &mS3ScriptSave
> + );
> +
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Build_IFWI.bat
> b/Platform/Intel/Vlv2TbltDevicePkg/Build_IFWI.bat
> new file mode 100644
> index 0000000000..887206703a
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Build_IFWI.bat
> @@ -0,0 +1,200 @@
> + at REM @file
> + at REM Windows batch file to build BIOS ROM
> + at REM
> + at REM Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> + at REM SPDX-License-Identifier: BSD-2-Clause-Patent
> + at REM
> +
> + at echo off
> +
> +SetLocal EnableDelayedExpansion EnableExtensions
> +
> + at REM Go to work space directory.
> +cd ..
> +cd ..
> +
> +:: Assign initial values
> +set exitCode=0
> +set "Build_Flags= "
> +set "Stitch_Flags= "
> +set Arch=X64
> +set PLATFORM_PACKAGE=Vlv2TbltDevicePkg
> +
> +set PLATFORM_PATH=%WORKSPACE%
> +if not exist %PLATFORM_PATH%\%PLATFORM_PACKAGE% (
> + if defined PACKAGES_PATH (
> + for %%i IN (%PACKAGES_PATH%) DO (
> + if exist %%~fi\%PLATFORM_PACKAGE% (
> + set PLATFORM_PATH=%%~fi
> + goto PlatformPackageFound
> + )
> + )
> + ) else (
> + echo.
> + echo !!! ERROR !!! Cannot find %PLATFORM_PACKAGE% !!!
> + echo.
> + goto Exit
> + )
> +)
> +:PlatformPackageFound
> +
> +:: Parse Optional arguments
> +:OptLoop
> +if /i "%~1"=="/?" goto Usage
> +
> +if /i "%~1"=="/q" (
> + set Build_Flags=%Build_Flags% /q
> + shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/l" (
> + set Build_Flags=%Build_Flags% /l
> + shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/y" (
> + set Build_Flags=%Build_Flags% /y
> + shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/m" (
> + set Build_Flags=%Build_Flags% /m
> + shift
> + goto OptLoop
> +)
> +if /i "%~1" == "/c" (
> + set Build_Flags=%Build_Flags% /c
> + shift
> + goto OptLoop
> +)
> +if /i "%~1" == "/ECP" (
> + set Build_Flags=%Build_Flags% /ecp
> + shift
> + goto OptLoop
> +)
> +
> +if /i "%~1"=="/s" (
> + set Build_Flags=%Build_Flags% /s
> + shift
> + goto OptLoop
> +)
> +
> +if /i "%~1"=="/x64" (
> + set Arch=X64
> + set Build_Flags=%Build_Flags% /x64
> + shift
> + goto OptLoop
> +)
> +
> +if /i "%~1"=="/IA32" (
> + set Arch=IA32
> + set Build_Flags=%Build_Flags% /IA32
> + shift
> + goto OptLoop
> +)
> +
> +if /i "%~1"=="/nG" (
> + set Stitch_Flags=%Stitch_Flags% /nG
> + shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/nM" (
> + set Stitch_Flags=%Stitch_Flags% /nM
> + shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/nB" (
> + set Stitch_Flags=%Stitch_Flags% /nB
> + shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/yL" (
> + set Stitch_Flags=%Stitch_Flags% /yL
> + shift
> + goto OptLoop
> +)
> +
> +
> +:: Require 2 input parameters
> +if "%~2"=="" goto Usage
> +
> +:: Assign required arguments
> +set Platform_Type=%~1
> +set Build_Target=%~2
> +
> +if "%~3"=="" (
> + set "IFWI_Suffix= "
> +) else set "IFWI_Suffix=/S %~3"
> +
> +:: Build BIOS
> +echo
> ==========================================================
> ============
> +echo Build_IFWI: Calling BIOS build Script...
> +
> +call %PLATFORM_PATH%\%PLATFORM_PACKAGE%\bld_vlv.bat %Build_Fla
> gs% %Platform_Type% %Build_Target%
> +
> +if %ERRORLEVEL% NEQ 0 (
> + echo echo -- Error Building BIOS & echo.
> + set exitCode=1
> + goto exit
> +)
> +echo.
> +echo Finished Building BIOS.
> + at REM Set BIOS_ID environment variable here.
> +call %WORKSPACE%\Conf\BiosId.bat
> +echo BIOS_ID=%BIOS_ID%
> +
> +:: Set the Board_Id, Build_Type, Version_Major, and Version_Minor
> environment variables
> +find /v "#" %WORKSPACE%\Conf\BiosId.env > ver_strings
> +for /f "tokens=1,3" %%i in (ver_strings) do set %%i=%%j
> +del /f/q ver_strings >nul
> +set
> BIOS_Name=%BOARD_ID%_%Arch%_%BUILD_TYPE%_%VERSION_MAJOR%
> _%VERSION_MINOR%.ROM
> +
> +:: Start Integration process
> +echo
> ==========================================================
> ============
> +echo Build_IFWI: Calling IFWI Stitching Script...
> +pushd %PLATFORM_PATH%\%PLATFORM_PACKAGE%\Stitch
> +
> + :: IFWIStitch.bat [/nG] [/nM] [/nB] [/B BIOS.rom] [/C StitchConfig] [/S
> IFWISuffix]
> + call IFWIStitch.bat %Stitch_Flags% /B %BIOS_Name% %IFWI_Suffix%
> +
> + @echo off
> +popd
> +if %ERRORLEVEL% NEQ 0 (
> + echo echo -- Error Stitching %BIOS_Nam% & echo.
> + set exitCode=1
> +)
> +echo.
> +echo Build_IFWI is finished.
> +echo The final IFWI file is located
> in %ROOT_DIR%\Vlv2TbltDevicePkg\Stitch\
> +echo
> ==========================================================
> ============
> +goto Exit
> +
> +:Usage
> +echo Script to build BIOS firmware and stitch the entire IFWI.
> +echo.
> +echo Usage: Build_IFWI.bat [options] PlatformType BuildTarget [IFWI
> Suffix]
> +echo.
> +echo /c CleanAll before building
> +echo /x64 Set Arch to X64 (default: X64)
> +echo /IA32 Set Arch to IA32 (default: X64)
> +echo /yL Enable SPI lock
> +echo.
> +echo Platform Types: MNW2
> +echo Build Targets: Release, Debug
> +echo IFWI Suffix: Suffix to append to end of IFWI filename (default:
> MM_DD_YYYY)
> +echo.
> +echo See Stitch/Stitch_Config.txt for additional stitching settings.
> +echo.
> +echo If capsule update is needed, please update CAPSULE_ENABLE =
> TRUE in Config.dsc.
> +echo If recovery is needed, please update RECOVERY_ENABLE = TRUE in
> Config.dsc.
> +echo If either of above is TRUE, please set OPENSSL_PATH in windows
> evironment
> +echo and put openssl.exe there, to generate final capsule image.
> +echo.
> +set exitCode=1
> +
> +:Exit
> + at REM CD to platform package.
> +cd %PLATFORM_PATH%
> +exit /b %exitCode%
> +
> +EndLocal
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Build_IFWI.sh
> b/Platform/Intel/Vlv2TbltDevicePkg/Build_IFWI.sh
> new file mode 100644
> index 0000000000..4a11a1cba9
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Build_IFWI.sh
> @@ -0,0 +1,104 @@
> +#!/usr/bin/env bash
> +##*******************************************************
> ***************
> +## Function define
> +##*******************************************************
> ***************
> +function Usage ( ) {
> + echo
> + echo "Script to build BIOS firmware and stitch the entire IFWI."
> + echo
> + echo "Usage: Build_IFWI.bat [options] PlatformType BuildTarget "
> + echo
> + echo
> + echo " /yL [option] : Enable SPI lock"
> + echo " Platform Types: MNW2"
> + echo " Build Targets: Release, Debug"
> + echo
> + echo " See Stitch/Stitch_Config.txt for additional stitching settings."
> + echo
> + echo
> + exit 0
> +}
> +
> +## Assign initial values
> +exitCode=0
> +Build_Flags=
> +Stitch_Flags=
> +Arch=X64
> +PLATFORM_PACKAGE=Vlv2TbltDevicePkg
> +
> +## Parse Optional arguments
> +if [ "$1" == "/?" ]; then
> + Usage
> +fi
> +
> +for (( i=1; i<=$#; ))
> + do
> + if [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/Q" ]; then
> + Build_Flags="$Build_Flags /q"
> + shift
> + elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/L" ]; then
> + Build_Flags="$Build_Flags /l"
> + shift
> + elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/C" ]; then
> + Build_Flags="$Build_Flags /c"
> + shift
> + elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/ECP" ]; then
> + Build_Flags="$Build_Flags /ecp"
> + shift
> + elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/X64" ]; then
> + Arch=X64
> + Build_Flags="$Build_Flags /x64"
> + shift
> + elif [ "$1" == "/nG" ]; then
> + Stitch_Flags="$Stitch_Flags /nG"
> + shift
> + elif [ "$1" == "/nM" ]; then
> + Stitch_Flags="$Stitch_Flags /nM"
> + shift
> + elif [ "$1" == "/nB" ]; then
> + Stitch_Flags="$Stitch_Flags /nB"
> + shift
> + elif [ "$1" == "/nV" ]; then
> + Stitch_Flags="$Stitch_Flags /nV"
> + shift
> + elif [ "$1" == "/yL" ]; then
> + Build_Flags="$Build_Flags /yL"
> + shift
> + else
> + break
> + fi
> + done
> +
> +## Require 2 input parameters
> +if [ "$2" == "" ]; then
> + Usage
> +fi
> +
> +## Assign required arguments
> +Platform_Type=$1
> +Build_Target=$2
> +if [ "$3" == "" ]; then
> + IFWI_Suffix=
> +else
> + IFWI_Suffix="/S $3"
> +fi
> +
> +## Go to root directory
> +cd ..
> +
> +## Build BIOS
> +echo
> "==========================================================
> ============"
> +echo "Build_IFWI: Calling BIOS build Script..."
> +./$PLATFORM_PACKAGE/bld_vlv.sh $Build_Flags $Platform_Type
> $Build_Target
> +
> +echo
> +echo Finished Building BIOS.
> +
> +## Start Integration process
> +echo
> ==========================================================
> ============
> +echo Skip "Build_IFWI: Calling IFWI Stitching Script..."
> +
> +echo
> +echo Build_IFWI is finished.
> +echo The final IFWI file is located in Stitch
> +echo
> ==========================================================
> ============
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FCE.exe
> b/Platform/Intel/Vlv2TbltDevicePkg/FCE.exe
> new file mode 100644
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> zXk8TzgwX>>O&Hsb%Cma6%m%`TwGHlG+)3+G+da2|;63=<&G*x2{k4_{H58
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> zyDOhpMf!FRStH at 6p1Py5W3+#M>7{QZ996Yi|I`-uw at 8A|^+v+^=Sf-
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> MAZB$Jf^L
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> k9J
> z_%D6(gf?CQgB}f<VK}nBd)IG==fQm1P5iz40z>SDa)}#f<_U(fi{-
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> z-{uK7pGThSa$9G(v#$0&+kJV$zP5wAzRF)=uyLy8_s!Kj;pY{(H7i}3E^nmYP}cKJ
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> zg#K~akxPB#eM#d#U57psQm4n9>@|OxJV(Cgr`1!Q3As at j+rHkDBENe2d~Un
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> zCWm$3G`7VHVZm0#*gX^H8D#s8I(fOj5FDp1*U5cm8d}<fO>mBSA#`fg|BFi7
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> zCgq=?iqb at C(y75Mu#*WUGST`?B*a#$V!;TFUFFbtu$2b?ASs<XMVFkMq(M
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> zfkYC)A}^S>DbN)Trh~v(8uD&qlA9mpUZn)?Qe+|Vks8P{L=~g7jY_vgEOSjsQ6
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> zy`U5uw7RB>MsqosO0p&?Mu$d=lA?8q at Y<sa$?d4vv3jUnJ5{S}D|0o956y at A
> hxqz|
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> zUo8qfF$wGdC8&le6F}O)HoT*C3Dn47G}xn|Ri&mp*`nbkFlQ7aYtu10LDN<it5
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> zm=ES*k9lB9$e%HT7*2O|
> zM!HUoy0NhF8ADKGd5l{~$Fb`t$~Z!05|P%MF<zIC#)F~g6Y)A at ykwYW$x>As
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> z3c{MC86aQKmp>x=@FcYotSWSbh66}O)qfT6<<Je|8OxoNtW-k-
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> z%fU*c9Ik`W21g8N<-
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> zHc7j63RoPYBNikSnMm8P<;cQ1J(R(o%CN|G4=)UrCP|G01(X59QW+K*7T!m6
> L`k8-
> z#IUqK#lqkVW{Bft$*32ufGtb{hh-
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> zsJ{yJ^`NbdIExuCYPK?`<9rY;XiKxb!XXC2tPwRAvN<c$wuL&gP^Y05X0&MY3uk
> +2
> z5Xz3e-I#`GE!F(QbnH}yKKp;mC+Y=NQ;=rXc6N3sF3yJ<-o!=?kI8hFg!3hw+a-
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> zB#nPKQ)2oP*$f_65jdk_F3Zr;yxtBZVMnzE$zX=gWFUtZO`Haro;niV_S~YSi^Pv
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> zH|9KinlHAJkQZ>Sfq4gNW0p!FgVvx1-
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> zC)JlxO8;iNvH|UL$fp*hjoK7VHM2D<sLLQ;JFJYjqG4r0n{oc2{Ru5+8ui$*a+K`6
> zPO=NbdY3e>#hg%&ls|CKY)3IoZOoPw&i~jtAGOz^4rDe1ltFJa>XyPjXw(?Wbj
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> zrday8>N47SWUJK>&?bkaM|<sPP0A1I)~Ge at W8o!hzSyg!AFg(dx|?w{!F4?9{
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> z(Bg#j`*-=m`p{CVCTOP*wc~z at ACv~xuVjG$t#UEBV=V+yJ%vH^f3#-
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> Wa+
> zm26~@dLY^i4WW8V(c)wP(9sGoN&v^fk4XtN-
> ^xBBsgjTrTH}g=+KVsX*EkXuS4vp_
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> zy^6Ba%kKE~oI57}=HffgD7)~ktp|2THU##*)VQ$a3*+{j*3ffl-
> *uZ7T=(a>C$4WP
> z at D)FN*ZhfJ{K at P~7T^3`<Adkty?EvF at h9K&+ACM=7(4Ir%lwNz at tv=xXZ@^
> j?u at mk
> z{PeV+mAn!B%8EHV{^h}km+iabk{#RbFZpHLy~pmX|9Zu_4@{U=5Io?SSy~&q
> `{@e`
> zzI<-
> p_J?17<iht}d;HYf{`bli%dVUMP~D}IK38*2wE2Tezx=Inn=d@}fam3}KmF4u
> S@?P5ULO$Ea$Ja;8f&T|O4^B`3
>
> literal 0
> HcmV?d00001
>
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleAll.bat
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleAll.bat
> new file mode 100644
> index 0000000000..8f589565fa
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleAll.bat
> @@ -0,0 +1,35 @@
> + at REM @file
> + at REM Windows batch file to generate UEFI capsules for system firmware
> and
> + at REM firmware for sample devices
> + at REM
> + at REM Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> + at REM SPDX-License-Identifier: BSD-2-Clause-Patent
> + at REM
> +
> + at echo off
> +setlocal
> +cd /d %~dp0
> +
> +rmdir /s /q %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules
> +mkdir %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules
> +mkdir %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\SampleDevelop
> ment
> +mkdir %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\NewCert
> +mkdir %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert
> +copy %WORKSPACE%\Build\Vlv2TbltDevicePkg\DEBUG_VS2015x86\X64\Ca
> psuleApp.efi %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\SampleDev
> elopment\CapsuleApp.efi
> +copy %WORKSPACE%\Build\Vlv2TbltDevicePkg\RELEASE_VS2015x86\X64\C
> apsuleApp.efi %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\SampleDe
> velopment\CapsuleAppRelease.efi
> +copy %WORKSPACE%\Build\Vlv2TbltDevicePkg\DEBUG_VS2015x86\X64\Ca
> psuleApp.efi %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\NewCert\C
> apsuleApp.efi
> +copy %WORKSPACE%\Build\Vlv2TbltDevicePkg\RELEASE_VS2015x86\X64\C
> apsuleApp.efi %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\NewCert\
> CapsuleAppRelease.efi
> +copy %WORKSPACE%\Build\Vlv2TbltDevicePkg\DEBUG_VS2015x86\X64\Ca
> psuleApp.efi %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert\C
> apsuleApp.efi
> +copy %WORKSPACE%\Build\Vlv2TbltDevicePkg\RELEASE_VS2015x86\X64\C
> apsuleApp.efi %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert\
> CapsuleAppRelease.efi
> +
> +call GenCapsuleMinnowMax.bat
> +call GenCapsuleMinnowMaxRelease.bat
> +call GenCapsuleSampleColor.bat Blue 149da854-7d19-4faa-a91e-
> 862ea1324be6
> +call GenCapsuleSampleColor.bat Green 79179bfd-704d-4c90-9e02-
> 0ab8d968c18a
> +call GenCapsuleSampleColor.bat Red 72e2945a-00da-448e-9aa7-
> 075ad840f9d4
> +
> +call LvfsGenCapsuleMinnowMax.bat
> +call LvfsGenCapsuleMinnowMaxRelease.bat
> +call LvfsGenCapsuleSampleColor.bat Blue 149da854-7d19-4faa-a91e-
> 862ea1324be6
> +call LvfsGenCapsuleSampleColor.bat Green 79179bfd-704d-4c90-9e02-
> 0ab8d968c18a
> +call LvfsGenCapsuleSampleColor.bat Red 72e2945a-00da-448e-9aa7-
> 075ad840f9d4
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleAll.sh
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleAll.sh
> new file mode 100644
> index 0000000000..040024553a
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleAll.sh
> @@ -0,0 +1,28 @@
> +# @file
> +# Linux script file to generate UEFI capsules for system firmware and
> +# firmware for sample devices
> +#
> +# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +cd $(dirname $0)
> +
> +rm -R $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules
> +mkdir $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules
> +mkdir
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/SampleDevelopment
> +mkdir $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/NewCert
> +mkdir $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/TestCert
> +cp
> $WORKSPACE/Build/Vlv2TbltDevicePkg/DEBUG_GCC49/X64/CapsuleApp.efi
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/SampleDevelopment/Caps
> uleApp.efi
> +cp
> $WORKSPACE/Build/Vlv2TbltDevicePkg/RELEASE_GCC49/X64/CapsuleApp.ef
> i
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/SampleDevelopment/Caps
> uleAppRelease.efi
> +cp
> $WORKSPACE/Build/Vlv2TbltDevicePkg/DEBUG_GCC49/X64/CapsuleApp.efi
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/NewCert/CapsuleApp.efi
> +cp
> $WORKSPACE/Build/Vlv2TbltDevicePkg/RELEASE_GCC49/X64/CapsuleApp.ef
> i
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/NewCert/CapsuleAppRele
> ase.efi
> +cp
> $WORKSPACE/Build/Vlv2TbltDevicePkg/DEBUG_GCC49/X64/CapsuleApp.efi
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/TestCert/CapsuleApp.efi
> +cp
> $WORKSPACE/Build/Vlv2TbltDevicePkg/RELEASE_GCC49/X64/CapsuleApp.ef
> i
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/TestCert/CapsuleAppRelea
> se.efi
> +
> +. GenCapsuleMinnowMax.sh
> +. GenCapsuleMinnowMaxRelease.sh
> +. GenCapsuleSampleColor.sh Blue 149DA854-7D19-4FAA-A91E-
> 862EA1324BE6
> +. GenCapsuleSampleColor.sh Green 79179BFD-704D-4C90-9E02-
> 0AB8D968C18A
> +. GenCapsuleSampleColor.sh Red 72E2945A-00DA-448E-9AA7-
> 075AD840F9D4
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMax.bat
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMax.bat
> new file mode 100644
> index 0000000000..6e4afd201e
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMax.bat
> @@ -0,0 +1,131 @@
> + at REM @file
> + at REM Windows batch file to generate UEFI capsules for system firmware
> + at REM
> + at REM Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> + at REM SPDX-License-Identifier: BSD-2-Clause-Patent
> + at REM
> +
> + at echo off
> +setlocal
> +
> +set FMP_CAPSULE_VENDOR=Intel
> +set FMP_CAPSULE_GUID=4096267B-DA0A-42EB-B5EB-FEF31D207CB4
> +set FMP_CAPSULE_FILE=MinnowMax.cap
> +set FMP_CAPSULE_VERSION=0x0000000C
> +set FMP_CAPSULE_STRING=0.0.0.12
> +set FMP_CAPSULE_NAME="Intel MinnowMax DEBUG
> UEFI %FMP_CAPSULE_STRING%"
> +set FMP_CAPSULE_LSV=0x00000000
> +set FMP_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +set
> FMP_CAPSULE_PAYLOAD=%WORKSPACE%\Build\Vlv2TbltDevicePkg\DEBUG
> _VS2015x86\FV\Vlv.ROM
> +set WINDOWS_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +
> +if not exist "%FMP_CAPSULE_PAYLOAD%" exit /b
> +
> +if exist "%FMP_CAPSULE_KEY%" (
> + REM
> + REM Sign capsule using signtool
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signing-tool-path="c:\Program Files (x86)\Windows Kits\8.1\bin\x86" ^
> + --pfx-file %FMP_CAPSULE_KEY% ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\SampleDevelopment
> +
> + if exist "%WINDOWS_CAPSULE_KEY%" (
> + CreateWindowsCapsule.py ^
> + UEFI ^
> + %FMP_CAPSULE_STRING% ^
> + %FMP_CAPSULE_GUID% ^
> + %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_VERSION% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_NAME% %WINDOWS_CAPSULE_KEY%
> +
> + xcopy /s/e/v/i/y
> WindowsCapsule %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\Sampl
> eDevelopment\MinnowMaxWindowsCapsule
> + rmdir /s /q WindowsCapsule
> + )
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +if exist "NewCert.pem" (
> + REM
> + REM Sign capsule using OpenSSL with a new certificate
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-cert=NewCert.pem ^
> + --other-public-cert=NewSub.pub.pem ^
> + --trusted-public-cert=NewRoot.pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\NewCert
> +
> + if exist "%WINDOWS_CAPSULE_KEY%" (
> + CreateWindowsCapsule.py ^
> + UEFI ^
> + %FMP_CAPSULE_STRING% ^
> + %FMP_CAPSULE_GUID% ^
> + %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_VERSION% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_NAME% %WINDOWS_CAPSULE_KEY%
> +
> + xcopy /s/e/v/i/y
> WindowsCapsule %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\NewC
> ert\MinnowMaxWindowsCapsule
> + rmdir /s /q WindowsCapsule
> + )
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +REM
> +REM Sign capsule using OpenSSL with EDK II Test Certificate
> +REM
> +call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestCert.p
> em ^
> + --other-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestSub.p
> ub.pem ^
> + --trusted-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestRoot.
> pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Ca
> psules\TestCert
> +
> +if exist "%WINDOWS_CAPSULE_KEY%" (
> + CreateWindowsCapsule.py ^
> + UEFI ^
> + %FMP_CAPSULE_STRING% ^
> + %FMP_CAPSULE_GUID% ^
> + %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_VERSION% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_NAME% %WINDOWS_CAPSULE_KEY%
> +
> + xcopy /s/e/v/i/y
> WindowsCapsule %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCe
> rt\MinnowMaxWindowsCapsule
> + rmdir /s /q WindowsCapsule
> +)
> +
> +erase %FMP_CAPSULE_FILE%
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMax.sh
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMax.sh
> new file mode 100644
> index 0000000000..4fb963c93c
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMax.sh
> @@ -0,0 +1,65 @@
> +# @file
> +# Linux script file to generate UEFI capsules for system firmware
> +#
> +# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +FMP_CAPSULE_VENDOR=Intel
> +FMP_CAPSULE_GUID=4096267B-DA0A-42EB-B5EB-FEF31D207CB4
> +FMP_CAPSULE_FILE=MinnowMax.cap
> +FMP_CAPSULE_VERSION=0x0000000C
> +FMP_CAPSULE_STRING=0.0.0.12
> +FMP_CAPSULE_NAME="Intel MinnowMax DEBUG UEFI
> $FMP_CAPSULE_STRING"
> +FMP_CAPSULE_LSV=0x00000000
> +FMP_CAPSULE_PAYLOAD=$WORKSPACE/Build/Vlv2TbltDevicePkg/DEBUG_
> GCC49/FV/Vlv.ROM
> +
> +if [ ! -e "$FMP_CAPSULE_PAYLOAD" ] ; then
> + return
> +fi
> +
> +if [ -e NewCert.pem ]; then
> + #
> + # Sign capsule using OpenSSL with a new certificate
> + #
> + GenerateCapsule \
> + --encode \
> + -v \
> + --guid $FMP_CAPSULE_GUID \
> + --fw-version $FMP_CAPSULE_VERSION \
> + --lsv $FMP_CAPSULE_LSV \
> + --capflag PersistAcrossReset \
> + --capflag InitiateReset \
> + --signer-private-cert=NewCert.pem \
> + --other-public-cert=NewSub.pub.pem \
> + --trusted-public-cert=NewRoot.pub.pem \
> + -o $FMP_CAPSULE_FILE \
> + $FMP_CAPSULE_PAYLOAD
> +
> + cp $FMP_CAPSULE_FILE
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/NewCert
> +
> + rm $FMP_CAPSULE_FILE
> +fi
> +
> +#
> +# Sign capsule using OpenSSL with EDK II Test Certificate
> +#
> +GenerateCapsule \
> + --encode \
> + -v \
> + --guid $FMP_CAPSULE_GUID \
> + --fw-version $FMP_CAPSULE_VERSION \
> + --lsv $FMP_CAPSULE_LSV \
> + --capflag PersistAcrossReset \
> + --capflag InitiateReset \
> + --signer-private-
> cert=$WORKSPACE/edk2/BaseTools/Source/Python/Pkcs7Sign/TestCert.pe
> m \
> + --other-public-
> cert=$WORKSPACE/edk2/BaseTools/Source/Python/Pkcs7Sign/TestSub.pub.
> pem \
> + --trusted-public-
> cert=$WORKSPACE/edk2/BaseTools/Source/Python/Pkcs7Sign/TestRoot.pu
> b.pem \
> + -o $FMP_CAPSULE_FILE \
> + $FMP_CAPSULE_PAYLOAD
> +
> +cp $FMP_CAPSULE_FILE
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/TestCert
> +
> +rm $FMP_CAPSULE_FILE
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMaxRelease.bat
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMaxRelease.bat
> new file mode 100644
> index 0000000000..43c609e4b2
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMaxRelease.bat
> @@ -0,0 +1,131 @@
> + at REM @file
> + at REM Windows batch file to generate UEFI capsules for system firmware
> + at REM
> + at REM Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> + at REM SPDX-License-Identifier: BSD-2-Clause-Patent
> + at REM
> +
> + at echo off
> +setlocal
> +
> +set FMP_CAPSULE_VENDOR=Intel
> +set FMP_CAPSULE_GUID=4096267B-DA0A-42EB-B5EB-FEF31D207CB4
> +set FMP_CAPSULE_FILE=MinnowMaxRelease.cap
> +set FMP_CAPSULE_VERSION=0x0000000C
> +set FMP_CAPSULE_STRING=0.0.0.12
> +set FMP_CAPSULE_NAME="Intel MinnowMax RELEASE
> UEFI %FMP_CAPSULE_STRING%"
> +set FMP_CAPSULE_LSV=0x00000000
> +set FMP_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +set
> FMP_CAPSULE_PAYLOAD=%WORKSPACE%\Build\Vlv2TbltDevicePkg\RELEAS
> E_VS2015x86\FV\Vlv.ROM
> +set WINDOWS_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +
> +if not exist "%FMP_CAPSULE_PAYLOAD%" exit /b
> +
> +if exist "%FMP_CAPSULE_KEY%" (
> + REM
> + REM Sign capsule using signtool
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signing-tool-path="c:\Program Files (x86)\Windows Kits\8.1\bin\x86" ^
> + --pfx-file %FMP_CAPSULE_KEY% ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\SampleDevelopment
> +
> + if exist "%WINDOWS_CAPSULE_KEY%" (
> + CreateWindowsCapsule.py ^
> + UEFI ^
> + %FMP_CAPSULE_STRING% ^
> + %FMP_CAPSULE_GUID% ^
> + %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_VERSION% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_NAME% %WINDOWS_CAPSULE_KEY%
> +
> + xcopy /s/e/v/i/y
> WindowsCapsule %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\Sampl
> eDevelopment\MinnowMaxReleaseWindowsCapsule
> + rmdir /s /q WindowsCapsule
> + )
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +if exist "NewCert.pem" (
> + REM
> + REM Sign capsule using OpenSSL with a new certificate
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-cert=NewCert.pem ^
> + --other-public-cert=NewSub.pub.pem ^
> + --trusted-public-cert=NewRoot.pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\NewCert
> +
> + if exist "%WINDOWS_CAPSULE_KEY%" (
> + CreateWindowsCapsule.py ^
> + UEFI ^
> + %FMP_CAPSULE_STRING% ^
> + %FMP_CAPSULE_GUID% ^
> + %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_VERSION% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_NAME% %WINDOWS_CAPSULE_KEY%
> +
> + xcopy /s/e/v/i/y
> WindowsCapsule %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\NewC
> ert\MinnowMaxReleaseWindowsCapsule
> + rmdir /s /q WindowsCapsule
> + )
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +REM
> +REM Sign capsule using OpenSSL with EDK II Test Certificate
> +REM
> +call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestCert.p
> em ^
> + --other-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestSub.p
> ub.pem ^
> + --trusted-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestRoot.
> pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Ca
> psules\TestCert
> +
> +if exist "%WINDOWS_CAPSULE_KEY%" (
> + CreateWindowsCapsule.py ^
> + UEFI ^
> + %FMP_CAPSULE_STRING% ^
> + %FMP_CAPSULE_GUID% ^
> + %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_VERSION% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_NAME% %WINDOWS_CAPSULE_KEY%
> +
> + xcopy /s/e/v/i/y
> WindowsCapsule %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCe
> rt\MinnowMaxReleaseWindowsCapsule
> + rmdir /s /q WindowsCapsule
> +)
> +
> +erase %FMP_CAPSULE_FILE%
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMaxRelease.sh
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMaxRelease.sh
> new file mode 100644
> index 0000000000..29d46dad1e
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleMinnowMaxRelease.sh
> @@ -0,0 +1,65 @@
> +# @file
> +# Linux script file to generate UEFI capsules for system firmware
> +#
> +# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +FMP_CAPSULE_VENDOR=Intel
> +FMP_CAPSULE_GUID=4096267B-DA0A-42EB-B5EB-FEF31D207CB4
> +FMP_CAPSULE_FILE=MinnowMaxRelease.cap
> +FMP_CAPSULE_VERSION=0x0000000C
> +FMP_CAPSULE_STRING=0.0.0.12
> +FMP_CAPSULE_NAME="Intel MinnowMax RELEASE UEFI
> $FMP_CAPSULE_STRING"
> +FMP_CAPSULE_LSV=0x00000000
> +FMP_CAPSULE_PAYLOAD=$WORKSPACE/Build/Vlv2TbltDevicePkg/RELEASE
> _GCC49/FV/Vlv.ROM
> +
> +if [ ! -e "$FMP_CAPSULE_PAYLOAD" ] ; then
> + return
> +fi
> +
> +if [ -e NewCert.pem ]; then
> + #
> + # Sign capsule using OpenSSL with a new certificate
> + #
> + GenerateCapsule \
> + --encode \
> + -v \
> + --guid $FMP_CAPSULE_GUID \
> + --fw-version $FMP_CAPSULE_VERSION \
> + --lsv $FMP_CAPSULE_LSV \
> + --capflag PersistAcrossReset \
> + --capflag InitiateReset \
> + --signer-private-cert=NewCert.pem \
> + --other-public-cert=NewSub.pub.pem \
> + --trusted-public-cert=NewRoot.pub.pem \
> + -o $FMP_CAPSULE_FILE \
> + $FMP_CAPSULE_PAYLOAD
> +
> + cp $FMP_CAPSULE_FILE
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/NewCert
> +
> + rm $FMP_CAPSULE_FILE
> +fi
> +
> +#
> +# Sign capsule using OpenSSL with EDK II Test Certificate
> +#
> +GenerateCapsule \
> + --encode \
> + -v \
> + --guid $FMP_CAPSULE_GUID \
> + --fw-version $FMP_CAPSULE_VERSION \
> + --lsv $FMP_CAPSULE_LSV \
> + --capflag PersistAcrossReset \
> + --capflag InitiateReset \
> + --signer-private-
> cert=$WORKSPACE/edk2/BaseTools/Source/Python/Pkcs7Sign/TestCert.pe
> m \
> + --other-public-
> cert=$WORKSPACE/edk2/BaseTools/Source/Python/Pkcs7Sign/TestSub.pub.
> pem \
> + --trusted-public-
> cert=$WORKSPACE/edk2/BaseTools/Source/Python/Pkcs7Sign/TestRoot.pu
> b.pem \
> + -o $FMP_CAPSULE_FILE \
> + $FMP_CAPSULE_PAYLOAD
> +
> +cp $FMP_CAPSULE_FILE
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/TestCert
> +
> +rm $FMP_CAPSULE_FILE
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleSampleColor.bat
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleSampleColor.bat
> new file mode 100644
> index 0000000000..3e9f94c530
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleSampleColor.bat
> @@ -0,0 +1,137 @@
> + at REM @file
> + at REM Windows batch file to generate UEFI capsules for a sample device
> + at REM
> + at REM Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> + at REM SPDX-License-Identifier: BSD-2-Clause-Patent
> + at REM
> +
> + at echo off
> +setlocal
> +
> +set COLOR=%1
> +
> +set FMP_CAPSULE_VENDOR=Intel
> +set FMP_CAPSULE_GUID=%2
> +set FMP_CAPSULE_FILE=%COLOR%.cap
> +set FMP_CAPSULE_VERSION=0x00000010
> +set FMP_CAPSULE_STRING=0.0.0.16
> +set FMP_CAPSULE_NAME="%COLOR% Progress
> Bar %FMP_CAPSULE_STRING%"
> +set FMP_CAPSULE_LSV=0x00000000
> +set FMP_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +set FMP_CAPSULE_PAYLOAD=Payload.bin
> +set WINDOWS_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +
> +echo "%COLOR% Progress Bar" > %FMP_CAPSULE_PAYLOAD%
> +
> +if not exist "%FMP_CAPSULE_PAYLOAD%" exit
> +
> +if exist "%FMP_CAPSULE_KEY%" (
> + REM
> + REM Sign capsule using signtool
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signing-tool-path="c:\Program Files (x86)\Windows Kits\8.1\bin\x86" ^
> + --pfx-file %FMP_CAPSULE_KEY% ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\SampleDevelopment
> +
> + if exist "%WINDOWS_CAPSULE_KEY%" (
> + CreateWindowsCapsule.py ^
> + UEFI ^
> + %FMP_CAPSULE_STRING% ^
> + %FMP_CAPSULE_GUID% ^
> + %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_VERSION% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_NAME% %WINDOWS_CAPSULE_KEY%
> +
> + xcopy /s/e/v/i/y
> WindowsCapsule %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\Sampl
> eDevelopment\%COLOR%WindowsCapsule
> + rmdir /s /q WindowsCapsule
> + )
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +if exist "NewCert.pem" (
> + REM
> + REM Sign capsule using OpenSSL with a new certificate
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-cert=NewCert.pem ^
> + --other-public-cert=NewSub.pub.pem ^
> + --trusted-public-cert=NewRoot.pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\NewCert
> +
> + if exist "%WINDOWS_CAPSULE_KEY%" (
> + CreateWindowsCapsule.py ^
> + UEFI ^
> + %FMP_CAPSULE_STRING% ^
> + %FMP_CAPSULE_GUID% ^
> + %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_VERSION% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_NAME% %WINDOWS_CAPSULE_KEY%
> +
> + xcopy /s/e/v/i/y
> WindowsCapsule %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\NewC
> ert\%COLOR%WindowsCapsule
> + rmdir /s /q WindowsCapsule
> + )
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +REM
> +REM Sign capsule using OpenSSL with EDK II Test Certificate
> +REM
> +call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestCert.p
> em ^
> + --other-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestSub.p
> ub.pem ^
> + --trusted-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestRoot.
> pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Ca
> psules\TestCert
> +
> +if exist "%WINDOWS_CAPSULE_KEY%" (
> + CreateWindowsCapsule.py ^
> + UEFI ^
> + %FMP_CAPSULE_STRING% ^
> + %FMP_CAPSULE_GUID% ^
> + %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_VERSION% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_VENDOR% ^
> + %FMP_CAPSULE_NAME% %WINDOWS_CAPSULE_KEY%
> +
> + xcopy /s/e/v/i/y
> WindowsCapsule %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCe
> rt\%COLOR%WindowsCapsule
> + rmdir /s /q WindowsCapsule
> +)
> +
> +erase %FMP_CAPSULE_FILE%
> +
> +erase %FMP_CAPSULE_PAYLOAD%
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleSampleColor.sh
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleSampleColor.sh
> new file mode 100644
> index 0000000000..a1c6f28cde
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ge
> nCapsuleSampleColor.sh
> @@ -0,0 +1,70 @@
> +# @file
> +# Linux script file to generate UEFI capsules for a sample device
> +#
> +# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +COLOR=$1
> +
> +FMP_CAPSULE_VENDOR=Intel
> +FMP_CAPSULE_GUID=$2
> +FMP_CAPSULE_FILE=$COLOR.cap
> +FMP_CAPSULE_VERSION=0x00000010
> +FMP_CAPSULE_STRING=0.0.0.16
> +FMP_CAPSULE_NAME="$COLOR Progress Bar $FMP_CAPSULE_STRING"
> +FMP_CAPSULE_LSV=0x00000000
> +FMP_CAPSULE_PAYLOAD=Payload.bin
> +
> +echo "$COLOR Progress Bar" > $FMP_CAPSULE_PAYLOAD
> +
> +if [ ! -e "$FMP_CAPSULE_PAYLOAD" ] ; then
> + return
> +fi
> +
> +if [ -e NewCert.pem ]; then
> + #
> + # Sign capsule using OpenSSL with a new certificate
> + #
> + GenerateCapsule \
> + --encode \
> + -v \
> + --guid $FMP_CAPSULE_GUID \
> + --fw-version $FMP_CAPSULE_VERSION \
> + --lsv $FMP_CAPSULE_LSV \
> + --capflag PersistAcrossReset \
> + --capflag InitiateReset \
> + --signer-private-cert=NewCert.pem \
> + --other-public-cert=NewSub.pub.pem \
> + --trusted-public-cert=NewRoot.pub.pem \
> + -o $FMP_CAPSULE_FILE \
> + $FMP_CAPSULE_PAYLOAD
> +
> + cp $FMP_CAPSULE_FILE
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/NewCert
> +
> + rm $FMP_CAPSULE_FILE
> +fi
> +
> +#
> +# Sign capsule using OpenSSL with EDK II Test Certificate
> +#
> +GenerateCapsule \
> + --encode \
> + -v \
> + --guid $FMP_CAPSULE_GUID \
> + --fw-version $FMP_CAPSULE_VERSION \
> + --lsv $FMP_CAPSULE_LSV \
> + --capflag PersistAcrossReset \
> + --capflag InitiateReset \
> + --signer-private-
> cert=$WORKSPACE/edk2/BaseTools/Source/Python/Pkcs7Sign/TestCert.pe
> m \
> + --other-public-
> cert=$WORKSPACE/edk2/BaseTools/Source/Python/Pkcs7Sign/TestSub.pub.
> pem \
> + --trusted-public-
> cert=$WORKSPACE/edk2/BaseTools/Source/Python/Pkcs7Sign/TestRoot.pu
> b.pem \
> + -o $FMP_CAPSULE_FILE \
> + $FMP_CAPSULE_PAYLOAD
> +
> +cp $FMP_CAPSULE_FILE
> $WORKSPACE/Build/Vlv2TbltDevicePkg/Capsules/TestCert
> +
> +rm $FMP_CAPSULE_FILE
> +
> +rm $FMP_CAPSULE_PAYLOAD
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> .ddf
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> .ddf
> new file mode 100644
> index 0000000000..f2c925a6dd
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> .ddf
> @@ -0,0 +1,14 @@
> +.OPTION EXPLICIT ; Generate errors on variable typos
> +
> +.Set CabinetNameTemplate=firmware.cab ; The name of the file
> +.set DiskDirectoryTemplate=CDROM ; All cabinets go in a single directory
> +.Set Cabinet=on ;
> +.Set Compress=on ;
> +.Set DiskDirectory1=.
> +.Set MaxDiskSize=99999744 ; multiple of 512
> +
> +;*** Files to zip ;
> +;
> +firmware.bin
> +firmware.metainfo.xml
> +;***
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> GenCapsuleMinnowMax.bat
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> GenCapsuleMinnowMax.bat
> new file mode 100644
> index 0000000000..dd8274a1cc
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> GenCapsuleMinnowMax.bat
> @@ -0,0 +1,139 @@
> + at REM @file
> + at REM Windows batch file to generate UEFI capsules for system firmware
> + at REM
> + at REM Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> + at REM
> + at REM SPDX-License-Identifier: BSD-2-Clause-Patent
> + at REM
> +
> + at echo off
> +setlocal
> +
> +set FMP_CAPSULE_VENDOR=Intel
> +set FMP_CAPSULE_GUID=4096267b-da0a-42eb-b5eb-fef31d207cb4
> +set FMP_CAPSULE_BASE_NAME=MinnowMax
> +set FMP_CAPSULE_FILE=%FMP_CAPSULE_BASE_NAME%.cap
> +set FMP_CAPSULE_VERSION=0x0000000C
> +set FMP_CAPSULE_VERSION_DECIMAL=12
> +set FMP_CAPSULE_STRING=0.0.0.12
> +set FMP_CAPSULE_NAME="Intel %FMP_CAPSULE_BASE_NAME% DEBUG
> UEFI %FMP_CAPSULE_STRING%"
> +set FMP_CAPSULE_LSV=0x00000000
> +set FMP_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +set
> FMP_CAPSULE_PAYLOAD=%WORKSPACE%\Build\Vlv2TbltDevicePkg\DEBUG
> _VS2015x86\FV\Vlv.ROM
> +set WINDOWS_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +
> +if not exist "%FMP_CAPSULE_PAYLOAD%" exit /b
> +
> +if exist "%FMP_CAPSULE_KEY%" (
> + REM
> + REM Sign capsule using signtool
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signing-tool-path="c:\Program Files (x86)\Windows Kits\8.1\bin\x86" ^
> + --pfx-file %FMP_CAPSULE_KEY% ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\SampleDevelopment
> +
> + copy %FMP_CAPSULE_FILE% firmware.bin
> + copy template.metainfo.xml firmware.metainfo.xml
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_GUID', '%FMP_CAPSULE_GUID%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_BASE_NAME', '%FMP_CAPSULE_BASE_NAME%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_VERSION_DECIMAL',
> '%FMP_CAPSULE_VERSION_DECIMAL%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_STRING', '%FMP_CAPSULE_STRING%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_DATE', '%date%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + makecab /f Lvfs.ddf
> + copy
> firmware.cab %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert\
> %FMP_CAPSULE_BASE_NAME%-%FMP_CAPSULE_STRING%.cab
> +
> + erase firmware.cab
> + erase setup.inf
> + erase setup.rpt
> +
> + erase firmware.metainfo.xml
> + erase firmware.bin
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +if exist "NewCert.pem" (
> + REM
> + REM Sign capsule using OpenSSL with a new certificate
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-cert=NewCert.pem ^
> + --other-public-cert=NewSub.pub.pem ^
> + --trusted-public-cert=NewRoot.pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\NewCert
> +
> + copy %FMP_CAPSULE_FILE% firmware.bin
> + copy template.metainfo.xml firmware.metainfo.xml
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_GUID', '%FMP_CAPSULE_GUID%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_BASE_NAME', '%FMP_CAPSULE_BASE_NAME%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_VERSION_DECIMAL',
> '%FMP_CAPSULE_VERSION_DECIMAL%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_STRING', '%FMP_CAPSULE_STRING%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_DATE', '%date%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + makecab /f Lvfs.ddf
> + copy
> firmware.cab %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert\
> %FMP_CAPSULE_BASE_NAME%-%FMP_CAPSULE_STRING%.cab
> +
> + erase firmware.cab
> + erase setup.inf
> + erase setup.rpt
> +
> + erase firmware.metainfo.xml
> + erase firmware.bin
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +REM
> +REM Sign capsule using OpenSSL with EDK II Test Certificate
> +REM
> +call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestCert.p
> em ^
> + --other-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestSub.p
> ub.pem ^
> + --trusted-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestRoot.
> pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Ca
> psules\TestCert
> +
> +copy %FMP_CAPSULE_FILE% firmware.bin
> +copy template.metainfo.xml firmware.metainfo.xml
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_GUID', '%FMP_CAPSULE_GUID%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_BASE_NAME', '%FMP_CAPSULE_BASE_NAME%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_VERSION_DECIMAL',
> '%FMP_CAPSULE_VERSION_DECIMAL%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_STRING', '%FMP_CAPSULE_STRING%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_DATE', '%date%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> +makecab /f Lvfs.ddf
> +copy
> firmware.cab %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert\
> %FMP_CAPSULE_BASE_NAME%-%FMP_CAPSULE_STRING%.cab
> +
> +erase firmware.cab
> +erase setup.inf
> +erase setup.rpt
> +
> +erase firmware.metainfo.xml
> +erase firmware.bin
> +erase %FMP_CAPSULE_FILE%
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> GenCapsuleMinnowMaxRelease.bat
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> GenCapsuleMinnowMaxRelease.bat
> new file mode 100644
> index 0000000000..2b68a98f98
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> GenCapsuleMinnowMaxRelease.bat
> @@ -0,0 +1,139 @@
> + at REM @file
> + at REM Windows batch file to generate UEFI capsules for system firmware
> + at REM
> + at REM Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> + at REM
> + at REM SPDX-License-Identifier: BSD-2-Clause-Patent
> + at REM
> +
> + at echo off
> +setlocal
> +
> +set FMP_CAPSULE_VENDOR=Intel
> +set FMP_CAPSULE_GUID=4096267b-da0a-42eb-b5eb-fef31d207cb4
> +set FMP_CAPSULE_BASE_NAME=MinnowMaxRelease
> +set FMP_CAPSULE_FILE=%FMP_CAPSULE_BASE_NAME%.cap
> +set FMP_CAPSULE_VERSION=0x0000000C
> +set FMP_CAPSULE_VERSION_DECIMAL=12
> +set FMP_CAPSULE_STRING=0.0.0.12
> +set FMP_CAPSULE_NAME="Intel %FMP_CAPSULE_BASE_NAME% RELEASE
> UEFI %FMP_CAPSULE_STRING%"
> +set FMP_CAPSULE_LSV=0x00000000
> +set FMP_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +set
> FMP_CAPSULE_PAYLOAD=%WORKSPACE%\Build\Vlv2TbltDevicePkg\RELEAS
> E_VS2015x86\FV\Vlv.ROM
> +set WINDOWS_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +
> +if not exist "%FMP_CAPSULE_PAYLOAD%" exit /b
> +
> +if exist "%FMP_CAPSULE_KEY%" (
> + REM
> + REM Sign capsule using signtool
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signing-tool-path="c:\Program Files (x86)\Windows Kits\8.1\bin\x86" ^
> + --pfx-file %FMP_CAPSULE_KEY% ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\SampleDevelopment
> +
> + copy %FMP_CAPSULE_FILE% firmware.bin
> + copy template.metainfo.xml firmware.metainfo.xml
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_GUID', '%FMP_CAPSULE_GUID%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_BASE_NAME', '%FMP_CAPSULE_BASE_NAME%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_VERSION_DECIMAL',
> '%FMP_CAPSULE_VERSION_DECIMAL%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_STRING', '%FMP_CAPSULE_STRING%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_DATE', '%date%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + makecab /f Lvfs.ddf
> + copy
> firmware.cab %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert\
> %FMP_CAPSULE_BASE_NAME%-%FMP_CAPSULE_STRING%.cab
> +
> + erase firmware.cab
> + erase setup.inf
> + erase setup.rpt
> +
> + erase firmware.metainfo.xml
> + erase firmware.bin
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +if exist "NewCert.pem" (
> + REM
> + REM Sign capsule using OpenSSL with a new certificate
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-cert=NewCert.pem ^
> + --other-public-cert=NewSub.pub.pem ^
> + --trusted-public-cert=NewRoot.pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\NewCert
> +
> + copy %FMP_CAPSULE_FILE% firmware.bin
> + copy template.metainfo.xml firmware.metainfo.xml
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_GUID', '%FMP_CAPSULE_GUID%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_BASE_NAME', '%FMP_CAPSULE_BASE_NAME%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_VERSION_DECIMAL',
> '%FMP_CAPSULE_VERSION_DECIMAL%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_STRING', '%FMP_CAPSULE_STRING%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_DATE', '%date%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + makecab /f Lvfs.ddf
> + copy
> firmware.cab %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert\
> %FMP_CAPSULE_BASE_NAME%-%FMP_CAPSULE_STRING%.cab
> +
> + erase firmware.cab
> + erase setup.inf
> + erase setup.rpt
> +
> + erase firmware.metainfo.xml
> + erase firmware.bin
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +REM
> +REM Sign capsule using OpenSSL with EDK II Test Certificate
> +REM
> +call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestCert.p
> em ^
> + --other-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestSub.p
> ub.pem ^
> + --trusted-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestRoot.
> pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Ca
> psules\TestCert
> +
> +copy %FMP_CAPSULE_FILE% firmware.bin
> +copy template.metainfo.xml firmware.metainfo.xml
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_GUID', '%FMP_CAPSULE_GUID%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_BASE_NAME', '%FMP_CAPSULE_BASE_NAME%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_VERSION_DECIMAL',
> '%FMP_CAPSULE_VERSION_DECIMAL%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_STRING', '%FMP_CAPSULE_STRING%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_DATE', '%date%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> +makecab /f Lvfs.ddf
> +copy
> firmware.cab %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert\
> %FMP_CAPSULE_BASE_NAME%-%FMP_CAPSULE_STRING%.cab
> +
> +erase firmware.cab
> +erase setup.inf
> +erase setup.rpt
> +
> +erase firmware.metainfo.xml
> +erase firmware.bin
> +erase %FMP_CAPSULE_FILE%
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> GenCapsuleSampleColor.bat
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> GenCapsuleSampleColor.bat
> new file mode 100644
> index 0000000000..1dbbe7341d
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Lvfs
> GenCapsuleSampleColor.bat
> @@ -0,0 +1,145 @@
> + at REM @file
> + at REM Windows batch file to generate UEFI capsules for a sample device
> + at REM
> + at REM Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> + at REM
> + at REM SPDX-License-Identifier: BSD-2-Clause-Patent
> + at REM
> +
> + at echo off
> +setlocal
> +
> +set COLOR=%1
> +
> +set FMP_CAPSULE_VENDOR=Intel
> +set FMP_CAPSULE_GUID=%2
> +set FMP_CAPSULE_BASE_NAME=%COLOR%
> +set FMP_CAPSULE_FILE=%FMP_CAPSULE_BASE_NAME%.cap
> +set FMP_CAPSULE_VERSION=0x00000010
> +set FMP_CAPSULE_VERSION_DECIMAL=16
> +set FMP_CAPSULE_STRING=0.0.0.16
> +set FMP_CAPSULE_NAME="%FMP_CAPSULE_BASE_NAME% Progress
> Bar %FMP_CAPSULE_STRING%"
> +set FMP_CAPSULE_LSV=0x00000000
> +set FMP_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +set FMP_CAPSULE_PAYLOAD=Payload.bin
> +set WINDOWS_CAPSULE_KEY=SAMPLE_DEVELOPMENT.pfx
> +
> +echo "%COLOR% Progress Bar" > %FMP_CAPSULE_PAYLOAD%
> +
> +if not exist "%FMP_CAPSULE_PAYLOAD%" exit
> +
> +if exist "%FMP_CAPSULE_KEY%" (
> + REM
> + REM Sign capsule using signtool
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signing-tool-path="c:\Program Files (x86)\Windows Kits\8.1\bin\x86" ^
> + --pfx-file %FMP_CAPSULE_KEY% ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\SampleDevelopment
> +
> + copy %FMP_CAPSULE_FILE% firmware.bin
> + copy template.metainfo.xml firmware.metainfo.xml
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_GUID', '%FMP_CAPSULE_GUID%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_BASE_NAME', '%FMP_CAPSULE_BASE_NAME%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_VERSION_DECIMAL',
> '%FMP_CAPSULE_VERSION_DECIMAL%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_STRING', '%FMP_CAPSULE_STRING%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_DATE', '%date%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + makecab /f Lvfs.ddf
> + copy
> firmware.cab %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert\
> %FMP_CAPSULE_BASE_NAME%-%FMP_CAPSULE_STRING%.cab
> +
> + erase firmware.cab
> + erase setup.inf
> + erase setup.rpt
> +
> + erase firmware.metainfo.xml
> + erase firmware.bin
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +if exist "NewCert.pem" (
> + REM
> + REM Sign capsule using OpenSSL with a new certificate
> + REM
> + call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-cert=NewCert.pem ^
> + --other-public-cert=NewSub.pub.pem ^
> + --trusted-public-cert=NewRoot.pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +
> copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Caps
> ules\NewCert
> +
> + copy %FMP_CAPSULE_FILE% firmware.bin
> + copy template.metainfo.xml firmware.metainfo.xml
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_GUID', '%FMP_CAPSULE_GUID%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_BASE_NAME', '%FMP_CAPSULE_BASE_NAME%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_VERSION_DECIMAL',
> '%FMP_CAPSULE_VERSION_DECIMAL%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_STRING', '%FMP_CAPSULE_STRING%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> + powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_DATE', '%date%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> + makecab /f Lvfs.ddf
> + copy
> firmware.cab %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert\
> %FMP_CAPSULE_BASE_NAME%-%FMP_CAPSULE_STRING%.cab
> +
> + erase firmware.cab
> + erase setup.inf
> + erase setup.rpt
> +
> + erase firmware.metainfo.xml
> + erase firmware.bin
> + erase %FMP_CAPSULE_FILE%
> +)
> +
> +REM
> +REM Sign capsule using OpenSSL with EDK II Test Certificate
> +REM
> +call GenerateCapsule ^
> + --encode ^
> + -v ^
> + --guid %FMP_CAPSULE_GUID% ^
> + --fw-version %FMP_CAPSULE_VERSION% ^
> + --lsv %FMP_CAPSULE_LSV% ^
> + --capflag PersistAcrossReset ^
> + --capflag InitiateReset ^
> + --signer-private-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestCert.p
> em ^
> + --other-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestSub.p
> ub.pem ^
> + --trusted-public-
> cert=%WORKSPACE%\edk2\BaseTools\Source\Python\Pkcs7Sign\TestRoot.
> pub.pem ^
> + -o %FMP_CAPSULE_FILE% ^
> + %FMP_CAPSULE_PAYLOAD%
> +
> +copy %FMP_CAPSULE_FILE% %WORKSPACE%\Build\Vlv2TbltDevicePkg\Ca
> psules\TestCert
> +
> +copy %FMP_CAPSULE_FILE% firmware.bin
> +copy template.metainfo.xml firmware.metainfo.xml
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_GUID', '%FMP_CAPSULE_GUID%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_BASE_NAME', '%FMP_CAPSULE_BASE_NAME%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_VERSION_DECIMAL',
> '%FMP_CAPSULE_VERSION_DECIMAL%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_STRING', '%FMP_CAPSULE_STRING%' | Out-File
> firmware.metainfo.xml -encoding ASCII"
> +powershell -Command "(gc firmware.metainfo.xml) -replace
> 'FMP_CAPSULE_DATE', '%date%' | Out-File firmware.metainfo.xml -
> encoding ASCII"
> +makecab /f Lvfs.ddf
> +copy
> firmware.cab %WORKSPACE%\Build\Vlv2TbltDevicePkg\Capsules\TestCert\
> %FMP_CAPSULE_BASE_NAME%-%FMP_CAPSULE_STRING%.cab
> +
> +erase firmware.cab
> +erase setup.inf
> +erase setup.rpt
> +
> +erase firmware.metainfo.xml
> +erase firmware.bin
> +erase %FMP_CAPSULE_FILE%
> +
> +erase %FMP_CAPSULE_PAYLOAD%
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ne
> wRoot.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferX
> dr.inc
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ne
> wRoot.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferX
> dr.inc
> new file mode 100644
> index 0000000000..d3f5a12faa
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/Ne
> wRoot.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferX
> dr.inc
> @@ -0,0 +1 @@
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/SA
> MPLE_DEVELOPMENT.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceP
> kcs7CertBufferXdr.inc
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/SA
> MPLE_DEVELOPMENT.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceP
> kcs7CertBufferXdr.inc
> new file mode 100644
> index 0000000000..d3f5a12faa
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/SA
> MPLE_DEVELOPMENT.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceP
> kcs7CertBufferXdr.inc
> @@ -0,0 +1 @@
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/SA
> MPLE_DEVELOPMENT_SAMPLE_PRODUCTION.cer.gFmpDevicePkgTokenSpa
> ceGuid.PcdFmpDevicePkcs7CertBufferXdr.inc
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/SA
> MPLE_DEVELOPMENT_SAMPLE_PRODUCTION.cer.gFmpDevicePkgTokenSpa
> ceGuid.PcdFmpDevicePkcs7CertBufferXdr.inc
> new file mode 100644
> index 0000000000..d3f5a12faa
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/SA
> MPLE_DEVELOPMENT_SAMPLE_PRODUCTION.cer.gFmpDevicePkgTokenSpa
> ceGuid.PcdFmpDevicePkcs7CertBufferXdr.inc
> @@ -0,0 +1 @@
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/tem
> plate.metainfo.xml
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/te
> mplate.metainfo.xml
> new file mode 100644
> index 0000000000..5d550c1f48
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/te
> mplate.metainfo.xml
> @@ -0,0 +1,27 @@
> +<?xml version="1.0" encoding="UTF-8"?>
> +<component type="firmware">
> + <id>com.intel.FMP_CAPSULE_BASE_NAME.firmware</id>
> + <name>FMP_CAPSULE_BASE_NAME</name>
> + <summary>System firmware for the
> FMP_CAPSULE_BASE_NAME</summary>
> + <description>
> + Description of System firmware for the FMP_CAPSULE_BASE_NAME
> + </description>
> + <provides>
> + <firmware type="flashed">FMP_CAPSULE_GUID</firmware>
> + </provides>
> + <url type="homepage">http://www.tianocore.org</url>
> + <metadata_license>CC0-1.0</metadata_license>
> + <project_license>BSD</project_license>
> + <developer_name>Tianocore</developer_name>
> + <releases>
> + <release version="FMP_CAPSULE_VERSION_DECIMAL"
> date="FMP_CAPSULE_DATE">
> + <description>
> + Build FMP_CAPSULE_STRING
> + </description>
> + </release>
> + </releases>
> + <!-- most OEMs do not need to do this... -->
> + <custom>
> + <value key="LVFS::InhibitDownload"/>
> + </custom>
> +</component>
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib/
> FmpDeviceLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib
> /FmpDeviceLib.c
> new file mode 100644
> index 0000000000..a863d69381
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib
> /FmpDeviceLib.c
> @@ -0,0 +1,589 @@
> +/**
> +
> +Copyright (c) 2016, Microsoft Corporation. All rights reserved.
> +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiDxe.h>
> +
> +#include <Library/FmpDeviceLib.h>
> +
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +#include <Library/PlatformFlashAccessLib.h>
> +
> +//#include <Protocol/FirmwareManagement.h>
> +
> +//#include <Guid/SystemResourceTable.h>
> +
> +typedef struct {
> + PLATFORM_FIRMWARE_TYPE FirmwareType;
> + FLASH_ADDRESS_TYPE AddressType;
> + EFI_PHYSICAL_ADDRESS BaseAddress;
> + UINTN Length;
> + UINTN ImageOffset;
> +} UPDATE_CONFIG_DATA;
> +
> +UPDATE_CONFIG_DATA mUpdateConfigData[] = {
> + { PlatformFirmwareTypeSystemFirmware,
> FlashAddressTypeRelativeAddress, 0x00000000, 0x00040000, 0x00000000 },
> + { PlatformFirmwareTypeSystemFirmware,
> FlashAddressTypeRelativeAddress, 0x000C0000, 0x00050000, 0x000C0000 },
> + { PlatformFirmwareTypeSystemFirmware,
> FlashAddressTypeRelativeAddress, 0x00110000, 0x00210000, 0x00110000 },
> + { PlatformFirmwareTypeSystemFirmware,
> FlashAddressTypeRelativeAddress, 0x00320000, 0x00070000, 0x00320000 },
> + { PlatformFirmwareTypeSystemFirmware,
> FlashAddressTypeRelativeAddress, 0x00390000, 0x00070000, 0x00390000 }
> +};
> +
> +/**
> + Used to pass the FMP install function to this lib. This allows the library to
> + have control of the handle that the FMP instance is installed on. This
> allows
> + the library to use DriverBinding protocol model to locate its device(s) in the
> + system.
> +
> + @param[in] Func Function pointer to FMP install function.
> +
> + @retval EFI_SUCCESS Library has saved function pointer and will call
> + function pointer on each DriverBinding Start.
> + @retval EFI_UNSUPPORTED Library doesn't use driver binding and only
> supports
> + a single instance.
> + @retval other error Error occurred. Don't install FMP
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +RegisterFmpInstaller (
> + IN FMP_DEVICE_LIB_REGISTER_FMP_INSTALLER Func
> + )
> +{
> + //
> + // This is a system firmware update that does not use Driver Binding
> Protocol
> + //
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +/**
> + Returns the size, in bytes, of the firmware image currently stored in the
> + firmware device. This function is used to by the GetImage() and
> + GetImageInfo() services of the Firmware Management Protocol. If the
> image
> + size can not be determined from the firmware device, then 0 must be
> returned.
> +
> + @param[out] Size Pointer to the size, in bytes, of the firmware image
> + currently stored in the firmware device.
> +
> + @retval EFI_SUCCESS The size of the firmware image currently
> + stored in the firmware device was returned.
> + @retval EFI_INVALID_PARAMETER Size is NULL.
> + @retval EFI_UNSUPPORTED The firmware device does not support
> reporting
> + the size of the currently stored firmware image.
> + @retval EFI_DEVICE_ERROR An error occured attempting to determine
> the
> + size of the firmware image currently stored in
> + in the firmware device.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetSize (
> + IN UINTN *Size
> + )
> +{
> + if (Size == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> + *Size = PcdGet32 (PcdBiosRomBase);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Used to return a library supplied guid that will be the ImageTypeId guid of
> + the FMP descriptor. This is optional but can be used if at runtime the guid
> + needs to be determined.
> +
> + @param[out] Guid Double Guid Ptr that will be updated to point to guid.
> + This should be from static memory and will not be freed.
> +
> + @return EFI_UNSUPPORTED Library instance doesn't need dynamic guid.
> + @return Error Any error will cause the wrapper to use the GUID
> + defined by PCD.
> + @return EFI_SUCCESS Guid ptr should be updated to point to static
> memeory
> + which contains a valid guid.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetImageTypeIdGuidPtr (
> + OUT EFI_GUID **Guid
> + )
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Returns values used to fill in the AttributesSupported and
> AttributesSettings
> + fields of the EFI_FIRMWARE_IMAGE_DESCRIPTOR structure that is
> returned by the
> + GetImageInfo() service of the Firmware Management Protocol. The
> following
> + bit values from the Firmware Management Protocol may be combined:
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE
> + IMAGE_ATTRIBUTE_RESET_REQUIRED
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED
> + IMAGE_ATTRIBUTE_IN_USE
> + IMAGE_ATTRIBUTE_UEFI_IMAGE
> +
> + @param[out] Supported Attributes supported by this firmware device.
> + @param[out] Setting Attributes settings for this firmware device.
> +
> + @retval EFI_SUCCESS The attributes supported by the firmware
> + device were returned.
> + @retval EFI_INVALID_PARAMETER Supported is NULL.
> + @retval EFI_INVALID_PARAMETER Setting is NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetAttributes (
> + IN OUT UINT64 *Supported,
> + IN OUT UINT64 *Setting
> + )
> +{
> + if (Supported == NULL || Setting == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> + *Supported = (IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE
> + );
> + *Setting = (IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE
> + );
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Gets the current Lowest Supported Version.
> +
> + This is a protection mechanism so that a previous version with known issue
> is
> + not applied. ONLY implement this if your running firmware has a method
> to
> + return this at runtime. If EFI_UNSUPPORTED is returned, then the Lowest
> + Supported Version is stored in a UEFI Variable.
> +
> + @param[out] Version On return this value represents the current Lowest
> + Supported Version (in same format as GetVersion).
> +
> + @retval EFI_SUCCESS The Lowest Supported Version was correctly
> retrieved
> + @retval EFI_UNSUPPORTED Device firmware doesn't support reporting
> LSV
> + @retval EFI_DEVICE_ERROR Error occurred when trying to get the LSV
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetLowestSupportedVersion (
> + IN OUT UINT32 *LowestSupportedVersion
> + )
> +{
> + //
> + // Retrieve the lowest support version from a PCD
> + // NOTE: This method of using a PCD can only be used for the system
> firmware
> + // FMP instance that is updated every time the system firmware is
> + // updated. If system firmware updates support partial updates that
> + // would not include the system firmware FMP instance, then a PCD can
> + // not be used and the value must come from the currently running
> system
> + // firmware image.
> + //
> + *LowestSupportedVersion = PcdGet32
> (PcdSystemFirmwareFmpLowestSupportedVersion);
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Returns the Null-terminated Unicode string that is used to fill in the
> + VersionName field of the EFI_FIRMWARE_IMAGE_DESCRIPTOR structure
> that is
> + returned by the GetImageInfo() service of the Firmware Management
> Protocol.
> + The returned string must be allocated using
> EFI_BOOT_SERVICES.AllocatePool().
> +
> + @note It is recommended that all firmware devices support a method to
> report
> + the VersionName string from the currently stored firmware image.
> +
> + @param[out] VersionString The version string retrieved from the
> currently
> + stored firmware image.
> +
> + @retval EFI_SUCCESS The version string of currently stored
> + firmware image was returned in Version.
> + @retval EFI_INVALID_PARAMETER VersionString is NULL.
> + @retval EFI_UNSUPPORTED The firmware device does not support a
> method
> + to report the version string of the currently
> + stored firmware image.
> + @retval EFI_DEVICE_ERROR An error occurred attempting to retrieve
> the
> + version string of the currently stored
> + firmware image.
> + @retval EFI_OUT_OF_RESOURCES There are not enough resources to
> allocate the
> + buffer for the version string of the currently
> + stored firmware image.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetVersionString (
> + OUT CHAR16 **VersionString
> + )
> +{
> + if (VersionString == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Retrieve the version string from a PCD
> + // NOTE: This method of using a PCD can only be used for the system
> firmware
> + // FMP instance that is updated every time the system firmware is
> + // updated. If system firmware updates support partial updates that
> + // would not include the system firmware FMP instance, then a PCD can
> + // not be used and the value must come from the currently running
> system
> + // firmware image.
> + //
> + *VersionString = (CHAR16 *)AllocateCopyPool (
> + PcdGetSize (PcdSystemFirmwareFmpVersionString),
> + PcdGetPtr (PcdSystemFirmwareFmpVersionString)
> + );
> + if (*VersionString == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Gets the current running version.
> +
> + ONLY implement this if your running firmware has a method to return this
> at
> + runtime.
> +
> + @param[out] Version On return this value represents the current running
> + version.
> +
> + @retval EFI_SUCCESS The version was correctly retrieved.
> + @retval EFI_UNSUPPORTED Device firmware doesn't support reporting
> current
> + version.
> + @retval EFI_DEVICE_ERROR Error occurred when trying to get the version.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetVersion (
> + IN OUT UINT32 *Version
> + )
> +{
> + //
> + // Retrieve the version string from a PCD
> + // NOTE: This method of using a PCD can only be used for the system
> firmware
> + // FMP instance that is updated every time the system firmware is
> + // updated. If system firmware updates support partial updates that
> + // would not include the system firmware FMP instance, then a PCD can
> + // not be used and the value must come from the currently running
> system
> + // firmware image.
> + //
> + *Version = PcdGet32 (PcdSystemFirmwareFmpVersion);
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Retrieves a copy of the current firmware image of the device.
> +
> + This function allows a copy of the current firmware image to be created
> and
> + saved. The saved copy could later been used, for example, in firmware
> image
> + recovery or rollback.
> +
> + @param[out] Image Points to the buffer where the current image is
> copied
> + to.
> + @param[out] ImageSize On entry, points to the size of the buffer pointed
> to
> + by Image, in bytes. On return, points to the length of
> + the image, in bytes.
> +
> + @retval EFI_SUCCESS The image was successfully read from the
> device.
> + @retval EFI_BUFFER_TOO_SMALL The buffer specified by ImageSize is
> too small
> + to hold the image. The current buffer size
> + needed to hold the image is returned in
> + ImageSize.
> + @retval EFI_INVALID_PARAMETER The Image was NULL.
> + @retval EFI_NOT_FOUND The current image is not copied to the
> buffer.
> + @retval EFI_UNSUPPORTED The operation is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetImage (
> + IN OUT VOID *Image,
> + IN OUT UINTN *ImageSize
> + )
> +{
> + //
> + // Check for invalid p;arameters
> + //
> + if (Image == NULL || ImageSize == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Make sure the buffer is big enough to hold the device image
> + //
> + if (*ImageSize < PcdGet32 (PcdBiosRomSize)) {
> + *ImageSize = PcdGet32 (PcdBiosRomSize);
> + return EFI_BUFFER_TOO_SMALL;
> + }
> +
> + //
> + // Copy the device image to the buffer
> + //
> + *ImageSize = PcdGet32 (PcdBiosRomSize);
> + CopyMem (
> + Image,
> + (VOID *)(UINTN)PcdGet32 (PcdBiosRomBase),
> + *ImageSize
> + );
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Updates the firmware image of the device.
> +
> + This function updates the hardware with the new firmware image. This
> function
> + returns EFI_UNSUPPORTED if the firmware image is not updatable. If the
> + firmware image is updatable, the function should perform the following
> minimal
> + validations before proceeding to do the firmware image update.
> + - Validate the image is a supported image for this device. The function
> + returns EFI_ABORTED if the image is unsupported. The function can
> + optionally provide more detailed information on why the image is not a
> + supported image.
> + - Validate the data from VendorCode if not null. Image validation must be
> + performed before VendorCode data validation. VendorCode data is
> ignored
> + or considered invalid if image validation failed. The function returns
> + EFI_ABORTED if the data is invalid.
> +
> + VendorCode enables vendor to implement vendor-specific firmware
> image update
> + policy. Null if the caller did not specify the policy or use the default
> + policy. As an example, vendor can implement a policy to allow an option to
> + force a firmware image update when the abort reason is due to the new
> firmware
> + image version is older than the current firmware image version or bad
> image
> + checksum. Sensitive operations such as those wiping the entire firmware
> image
> + and render the device to be non-functional should be encoded in the
> image
> + itself rather than passed with the VendorCode. AbortReason enables
> vendor to
> + have the option to provide a more detailed description of the abort reason
> to
> + the caller.
> +
> + @param[in] Image Points to the new image.
> + @param[in] ImageSize Size of the new image in bytes.
> + @param[in] VendorCode This enables vendor to implement vendor-
> specific
> + firmware image update policy. Null indicates the
> + caller did not specify the policy or use the
> + default policy.
> + @param[in] Progress A function used by the driver to report the
> + progress of the firmware update.
> + @param[in] CapsuleFwVersion FMP Payload Header version of the image.
> + @param[out] AbortReason A pointer to a pointer to a null-terminated
> + string providing more details for the aborted
> + operation. The buffer is allocated by this
> + function with AllocatePool(), and it is the
> + caller's responsibility to free it with a call
> + to FreePool().
> +
> + @retval EFI_SUCCESS The device was successfully updated with the
> + new image.
> + @retval EFI_ABORTED The operation is aborted.
> + @retval EFI_INVALID_PARAMETER The Image was NULL.
> + @retval EFI_UNSUPPORTED The operation is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceSetImage (
> + IN CONST VOID *Image,
> + IN UINTN ImageSize,
> + IN CONST VOID *VendorCode,
> + IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS
> Progress,
> + IN UINT32 CapsuleFwVersion,
> + OUT CHAR16 **AbortReason
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 Updateable;
> + UINTN Percentage;
> + UINTN Index;
> + UPDATE_CONFIG_DATA *ConfigData;
> + UINTN TotalSize;
> + UINTN BytesWritten;
> +
> + Updateable = 0;
> + Status = FmpDeviceCheckImage (Image, ImageSize, &Updateable);
> + if (EFI_ERROR (Status)) {
> + DEBUG((DEBUG_ERROR, "FmpDeviceSetImage - Check Image failed
> with %r.\n", Status));
> + return Status;
> + }
> +
> + if (Updateable != IMAGE_UPDATABLE_VALID) {
> + DEBUG((DEBUG_ERROR, "FmpDeviceSetImage - Check Image returned
> that the Image was not valid for update. Updatable value = 0x%X.\n",
> Updateable));
> + return EFI_ABORTED;
> + }
> +
> + if (Progress == NULL) {
> + DEBUG((DEBUG_ERROR, "FmpDeviceSetImage - Invalid progress
> callback\n"));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Status = Progress (15);
> + if (EFI_ERROR (Status)) {
> + DEBUG((DEBUG_ERROR, "FmpDeviceSetImage - Progress Callback failed
> with Status %r.\n", Status));
> + }
> +
> + //
> + // Write the image to the firmware device
> + //
> + Progress (20);
> + if (EFI_ERROR (Status)) {
> + DEBUG((DEBUG_ERROR, "FmpDeviceSetImage - Progress Callback failed
> with Status %r.\n", Status));
> + }
> +
> + //
> + // Simulate update with delays between progress updates
> + //
> + for (Percentage = 20; Percentage <= 100; Percentage++) {
> + //
> + // Wait 0.05 seconds
> + //
> +// gBS->Stall (50000);
> +
> +// Progress (Percentage);
> +// if (EFI_ERROR (Status)) {
> +// DEBUG((DEBUG_ERROR, "FmpDeviceSetImage - Progress Callback
> failed with Status %r.\n", Status));
> +// }
> + }
> +
> + DEBUG ((DEBUG_INFO, "FmpDeviceSetImage - %d Images ...\n",
> ARRAY_SIZE (mUpdateConfigData)));
> +
> + if (ARRAY_SIZE (mUpdateConfigData) == 0) {
> + DEBUG((DEBUG_INFO, "PlatformUpdate: BaseAddress - 0x%lx
> ImageOffset - 0x%x Length - 0x%x\n", 0, 0, ImageSize));
> + Status = PerformFlashWriteWithProgress (
> + PlatformFirmwareTypeSystemFirmware, // FirmwareType
> + 0x00000000, // FlashAddress
> + FlashAddressTypeRelativeAddress, // FlashAddressType
> + (VOID *)(UINTN)Image, // Buffer
> + ImageSize, // BufferLength
> + Progress, // Progress
> + 20, // StartPercentage
> + 100 // EndPercentage
> + );
> + }
> +
> +
> + //
> + // Compute total size of update
> + //
> + for (Index = 0, TotalSize = 0; Index < ARRAY_SIZE (mUpdateConfigData);
> Index++) {
> + TotalSize += mUpdateConfigData[Index].Length;
> + }
> +
> + BytesWritten = 0;
> + for (Index = 0, ConfigData = mUpdateConfigData; Index < ARRAY_SIZE
> (mUpdateConfigData); Index++, ConfigData++) {
> + DEBUG((DEBUG_INFO, "PlatformUpdate(%d): BaseAddress - 0x%lx
> ImageOffset - 0x%x Length - 0x%x\n",
> + Index,
> + ConfigData->BaseAddress,
> + ConfigData->ImageOffset,
> + ConfigData->Length
> + ));
> + Status = PerformFlashWriteWithProgress (
> + ConfigData->FirmwareType, // FirmwareType
> + ConfigData->BaseAddress, // FlashAddress
> + ConfigData->AddressType, // FlashAddressType
> + (VOID *)((UINTN)Image + (UINTN)ConfigData->ImageOffset), //
> Buffer
> + ConfigData->Length, // BufferLength
> + Progress, // Progress
> + 20 + (BytesWritten * 80) / TotalSize, // StartPercentage
> + 20 + ((BytesWritten + ConfigData->Length) * 80) / TotalSize //
> EndPercentage
> + );
> + if (EFI_ERROR(Status)) {
> + break;
> + }
> + BytesWritten += ConfigData->Length;
> + }
> +
> + DEBUG ((DEBUG_INFO, "FmpDeviceSetImage - %r\n", Status));
> +
> + return Status;
> +}
> +
> +/**
> +Checks if the firmware image is valid for the device.
> +
> +This function allows firmware update application to validate the firmware
> image without
> +invoking the SetImage() first.
> +
> + at param[in] Image Points to the new image.
> + at param[in] ImageSize Size of the new image in bytes.
> + at param[out] ImageUpdatable Indicates if the new image is valid for
> update. It also provides,
> +if available, additional information if the image is invalid.
> +
> + at retval EFI_SUCCESS The image was successfully checked.
> + at retval EFI_INVALID_PARAMETER The Image was NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceCheckImage (
> + IN CONST VOID *Image,
> + IN UINTN ImageSize,
> + OUT UINT32 *ImageUpdateable
> + )
> +{
> + if (ImageUpdateable == NULL) {
> + DEBUG((DEBUG_ERROR, "CheckImage - ImageUpdateable Pointer
> Parameter is NULL.\n"));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + //Set to valid and then if any tests fail it will update this flag.
> + //
> + *ImageUpdateable = IMAGE_UPDATABLE_VALID;
> +
> + if (Image == NULL) {
> + DEBUG((DEBUG_ERROR, "CheckImage - Image Pointer Parameter is
> NULL.\n"));
> + //
> + // Not sure if this is needed
> + //
> + *ImageUpdateable = IMAGE_UPDATABLE_INVALID;
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Make sure the image size is correct
> + //
> + if (ImageSize != PcdGet32 (PcdBiosRomSize)) {
> + *ImageUpdateable = IMAGE_UPDATABLE_INVALID;
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Device firmware should trigger lock mechanism so that device fw can not
> be
> + updated or tampered with. This lock mechanism is generally only cleared
> by a
> + full system reset (not just sleep state/low power mode)
> +
> + @retval EFI_SUCCESS The device was successfully locked.
> + @retval EFI_UNSUPPORTED The hardware device/firmware doesn't
> support locking
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceLock (
> + VOID
> + )
> +{
> + DEBUG ((DEBUG_INFO, "VLV2: FmpDeviceLock() for system FLASH\n"));
> + // TODO: Add lock logic
> + return EFI_UNSUPPORTED;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib/
> FmpDeviceLib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib
> /FmpDeviceLib.inf
> new file mode 100644
> index 0000000000..6fd618974f
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib
> /FmpDeviceLib.inf
> @@ -0,0 +1,46 @@
> +##
> +# Copyright (c) 2016, Microsoft Corporation
> +
> +# All rights reserved.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = Vlv2FmpDeviceLib
> + FILE_GUID = 83723F51-39B5-4D99-A974-90132AB55F83
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = FmpDeviceLib|DXE_DRIVER
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +[Sources]
> + FmpDeviceLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + FmpDevicePkg/FmpDevicePkg.dec
> + SignedCapsulePkg/SignedCapsulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + BaseLib
> + BaseMemoryLib
> + MemoryAllocationLib
> + UefiBootServicesTableLib
> + PlatformFlashAccessLib
> +
> +[Pcd]
> + gPlatformModuleTokenSpaceGuid.PcdBiosRomBase
> + gPlatformModuleTokenSpaceGuid.PcdBiosRomSize
> +
> gPlatformModuleTokenSpaceGuid.PcdSystemFirmwareFmpLowestSupporte
> dVersion
> + gPlatformModuleTokenSpaceGuid.PcdSystemFirmwareFmpVersion
> + gPlatformModuleTokenSpaceGuid.PcdSystemFirmwareFmpVersionString
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib
> Sample/FmpDeviceLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib
> Sample/FmpDeviceLib.c
> new file mode 100644
> index 0000000000..80ce83a14b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib
> Sample/FmpDeviceLib.c
> @@ -0,0 +1,412 @@
> +/**
> +
> +Copyright (c) 2016, Microsoft Corporation
> +
> +All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +
> +#include <PiDxe.h>
> +#include <Library/DebugLib.h>
> +#include <Protocol/FirmwareManagement.h>
> +#include <Library/BaseLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/FmpDeviceLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +/**
> + Used to pass the FMP install function to this lib.
> + This allows the library to have control of the handle
> + that the FMP instance is installed on. This allows the library
> + to use DriverBinding protocol model to locate its device(s) in the
> + system.
> +
> + @param[in] Function pointer to FMP install function.
> +
> + @retval EFI_SUCCESS Library has saved function pointer and will call
> function pointer on each DriverBinding Start.
> + @retval EFI_UNSUPPORTED Library doesn't use driver binding and only
> supports a single instance.
> + @retval other error Error occurred. Don't install FMP
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +RegisterFmpInstaller(
> +IN FMP_DEVICE_LIB_REGISTER_FMP_INSTALLER Func
> +)
> +{
> + // Because this is a sample lib with very simple fake device we don't use
> + // the driverbinding protocol to locate our device.
> + //
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +/**
> +Used to get the size of the image in bytes.
> +NOTE - Do not return zero as that will identify the device as
> +not updatable.
> +
> + at retval UINTN that represents the size of the firmware.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetSize (
> + IN UINTN *Size
> + )
> +{
> + if (Size == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> + *Size = 0x1000;
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +Used to return a library supplied guid that will be the ImageTypeId guid of
> the FMP descriptor.
> +This is optional but can be used if at runtime the guid needs to be
> determined.
> +
> + at param Guid: Double Guid Ptr that will be updated to point to guid. This
> should be from static memory
> +and will not be freed.
> + at return EFI_UNSUPPORTED: if you library instance doesn't need dynamic
> guid return this.
> + at return Error: Any error will cause the wrapper to use the GUID defined by
> PCD
> + at return EFI_SUCCESS: Guid ptr should be updated to point to static
> memeory which contains a valid guid
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetImageTypeIdGuidPtr(
> + OUT EFI_GUID** Guid)
> +{
> + //this instance doesn't need dynamic guid detection.
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Returns values used to fill in the AttributesSupported and
> AttributesSettings
> + fields of the EFI_FIRMWARE_IMAGE_DESCRIPTOR structure that is
> returned by the
> + GetImageInfo() service of the Firmware Management Protocol. The
> following
> + bit values from the Firmware Management Protocol may be combined:
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE
> + IMAGE_ATTRIBUTE_RESET_REQUIRED
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED
> + IMAGE_ATTRIBUTE_IN_USE
> + IMAGE_ATTRIBUTE_UEFI_IMAGE
> +
> + @param[out] Supported Attributes supported by this firmware device.
> + @param[out] Setting Attributes settings for this firmware device.
> +
> + @retval EFI_SUCCESS The attributes supported by the firmware
> + device were returned.
> + @retval EFI_INVALID_PARAMETER Supported is NULL.
> + @retval EFI_INVALID_PARAMETER Setting is NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetAttributes (
> + IN OUT UINT64 *Supported,
> + IN OUT UINT64 *Setting
> + )
> +{
> + if (Supported == NULL || Setting == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> + *Supported = (IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> IMAGE_ATTRIBUTE_IN_USE);
> + *Setting = (IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> IMAGE_ATTRIBUTE_IN_USE);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +Gets the current Lowest Supported Version.
> +This is a protection mechanism so that a previous version with known issue
> is not
> +applied.
> +
> +ONLY implement this if your running firmware has a method to return this
> at runtime.
> +
> + at param[out] Version On return this value represents the
> +current Lowest Supported Version (in same format as GetVersion).
> +
> + at retval EFI_SUCCESS The Lowest Supported Version was correctly
> retrieved
> + at retval EFI_UNSUPPORTED Device firmware doesn't support reporting
> LSV
> + at retval EFI_DEVICE_ERROR Error occurred when trying to get the LSV
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetLowestSupportedVersion (
> + IN OUT UINT32* LowestSupportedVersion
> + )
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +/**
> + Returns the Null-terminated Unicode string that is used to fill in the
> + VersionName field of the EFI_FIRMWARE_IMAGE_DESCRIPTOR structure
> that is
> + returned by the GetImageInfo() service of the Firmware Management
> Protocol.
> + The returned string must be allocated using
> EFI_BOOT_SERVICES.AllocatePool().
> +
> + @note It is recommended that all firmware devices support a method to
> report
> + the VersionName string from the currently stored firmware image.
> +
> + @param[out] VersionString The version string retrieved from the
> currently
> + stored firmware image.
> +
> + @retval EFI_SUCCESS The version string of currently stored
> + firmware image was returned in Version.
> + @retval EFI_INVALID_PARAMETER VersionString is NULL.
> + @retval EFI_UNSUPPORTED The firmware device does not support a
> method
> + to report the version string of the currently
> + stored firmware image.
> + @retval EFI_DEVICE_ERROR An error occurred attempting to retrieve
> the
> + version string of the currently stored
> + firmware image.
> + @retval EFI_OUT_OF_RESOURCES There are not enough resources to
> allocate the
> + buffer for the version string of the currently
> + stored firmware image.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetVersionString (
> + OUT CHAR16 **VersionString
> + )
> +{
> + if (VersionString == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> + *VersionString = NULL;
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> +Gets the current running version.
> +ONLY implement this if your running firmware has a method to return this
> at runtime.
> +
> + at param[out] Version On return this value represents the current
> running version
> +
> + at retval EFI_SUCCESS The version was correctly retrieved
> + at retval EFI_UNSUPPORTED Device firmware doesn't support reporting
> current version
> + at retval EFI_DEVICE_ERROR Error occurred when trying to get the version
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetVersion(
> +IN OUT UINT32* Version
> +)
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +/**
> +Retrieves a copy of the current firmware image of the device.
> +
> +This function allows a copy of the current firmware image to be created and
> saved.
> +The saved copy could later been used, for example, in firmware image
> recovery or rollback.
> +
> + at param[out] Image Points to the buffer where the current image is
> copied to.
> + at param[out] ImageSize On entry, points to the size of the buffer
> pointed to by Image, in bytes.
> +On return, points to the length of the image, in bytes.
> +
> + at retval EFI_SUCCESS The device was successfully updated with the
> new image.
> + at retval EFI_BUFFER_TOO_SMALL The buffer specified by ImageSize is too
> small to hold the
> +image. The current buffer size needed to hold the image is returned
> +in ImageSize.
> + at retval EFI_INVALID_PARAMETER The Image was NULL.
> + at retval EFI_NOT_FOUND The current image is not copied to the buffer.
> + at retval EFI_UNSUPPORTED The operation is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceGetImage(
> +IN OUT VOID *Image,
> +IN OUT UINTN *ImageSize
> +)
> +/*++
> +
> +Routine Description:
> +
> + This is a function used to read the current firmware from the device into
> memory.
> + This is an optional function and can return EFI_UNSUPPORTED. This is
> useful for
> + test and diagnostics.
> +
> +Arguments:
> + Image -- Buffer to place the image into.
> + ImageSize -- Size of the Image buffer.
> +
> +Return Value:
> +
> + EFI_STATUS code.
> + If not possible or not practical return EFI_UNSUPPORTED.
> +
> +--*/
> +{
> + return EFI_UNSUPPORTED;
> +}//GetImage()
> +
> +
> +/**
> +Updates the firmware image of the device.
> +
> +This function updates the hardware with the new firmware image.
> +This function returns EFI_UNSUPPORTED if the firmware image is not
> updatable.
> +If the firmware image is updatable, the function should perform the
> following minimal validations
> +before proceeding to do the firmware image update.
> +- Validate the image is a supported image for this device. The function
> returns EFI_ABORTED if
> +the image is unsupported. The function can optionally provide more
> detailed information on
> +why the image is not a supported image.
> +- Validate the data from VendorCode if not null. Image validation must be
> performed before
> +VendorCode data validation. VendorCode data is ignored or considered
> invalid if image
> +validation failed. The function returns EFI_ABORTED if the data is invalid.
> +
> +VendorCode enables vendor to implement vendor-specific firmware image
> update policy. Null if
> +the caller did not specify the policy or use the default policy. As an example,
> vendor can implement
> +a policy to allow an option to force a firmware image update when the abort
> reason is due to the new
> +firmware image version is older than the current firmware image version or
> bad image checksum.
> +Sensitive operations such as those wiping the entire firmware image and
> render the device to be
> +non-functional should be encoded in the image itself rather than passed
> with the VendorCode.
> +AbortReason enables vendor to have the option to provide a more detailed
> description of the abort
> +reason to the caller.
> +
> + at param[in] Image Points to the new image.
> + at param[in] ImageSize Size of the new image in bytes.
> + at param[in] VendorCode This enables vendor to implement vendor-
> specific firmware image update policy.
> +Null indicates the caller did not specify the policy or use the default policy.
> + at param[in] Progress A function used by the driver to report the
> progress of the firmware update.
> + at param[in] CapsuleFwVersion FMP Payload Header version of the image
> + at param[out] AbortReason A pointer to a pointer to a null-terminated
> string providing more
> +details for the aborted operation. The buffer is allocated by this function
> +with AllocatePool(), and it is the caller's responsibility to free it with a
> +call to FreePool().
> +
> + at retval EFI_SUCCESS The device was successfully updated with the
> new image.
> + at retval EFI_ABORTED The operation is aborted.
> + at retval EFI_INVALID_PARAMETER The Image was NULL.
> + at retval EFI_UNSUPPORTED The operation is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceSetImage (
> +IN CONST VOID *Image,
> +IN UINTN ImageSize,
> +IN CONST VOID *VendorCode,
> +IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS
> Progress,
> +IN UINT32 CapsuleFwVersion,
> +OUT CHAR16 **AbortReason
> +)
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + UINT32 Updateable = 0;
> +
> + Status = FmpDeviceCheckImage(Image, ImageSize, &Updateable);
> + if (EFI_ERROR(Status))
> + {
> + DEBUG((DEBUG_ERROR, "SetImage - Check Image failed with %r.\n",
> Status));
> + goto cleanup;
> + }
> +
> + if (Updateable != IMAGE_UPDATABLE_VALID)
> + {
> + DEBUG((DEBUG_ERROR, "SetImage - Check Image returned that the
> Image was not valid for update. Updatable value = 0x%X.\n", Updateable));
> + Status = EFI_ABORTED;
> + goto cleanup;
> + }
> +
> + if (Progress == NULL)
> + {
> + DEBUG((DEBUG_ERROR, "SetImage - Invalid progress callback\n"));
> + Status = EFI_INVALID_PARAMETER;
> + goto cleanup;
> + }
> +
> + Status = Progress(15);
> + if (EFI_ERROR(Status))
> + {
> + DEBUG((DEBUG_ERROR, "SetImage - Progress Callback failed with
> Status %r.\n", Status));
> + }
> +
> + {
> + UINTN p;
> +
> + for (p = 20; p < 100; p++) {
> + gBS->Stall (100000); //us = 0.1 seconds
> + Progress (p);
> + }
> + }
> +
> + //TODO: add support for VendorCode, and AbortReason
> +cleanup:
> + return Status;
> +}// SetImage()
> +
> +
> +
> +/**
> +Checks if the firmware image is valid for the device.
> +
> +This function allows firmware update application to validate the firmware
> image without
> +invoking the SetImage() first.
> +
> + at param[in] Image Points to the new image.
> + at param[in] ImageSize Size of the new image in bytes.
> + at param[out] ImageUpdatable Indicates if the new image is valid for
> update. It also provides,
> +if available, additional information if the image is invalid.
> +
> + at retval EFI_SUCCESS The image was successfully checked.
> + at retval EFI_INVALID_PARAMETER The Image was NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceCheckImage(
> +IN CONST VOID *Image,
> +IN UINTN ImageSize,
> +OUT UINT32 *ImageUpdateable
> +)
> +{
> + EFI_STATUS status = EFI_SUCCESS;
> +
> + if (ImageUpdateable == NULL)
> + {
> + DEBUG((DEBUG_ERROR, "CheckImage - ImageUpdateable Pointer
> Parameter is NULL.\n"));
> + status = EFI_INVALID_PARAMETER;
> + goto cleanup;
> + }
> +
> + //
> + //Set to valid and then if any tests fail it will update this flag.
> + //
> + *ImageUpdateable = IMAGE_UPDATABLE_VALID;
> +
> + if (Image == NULL)
> + {
> + DEBUG((DEBUG_ERROR, "CheckImage - Image Pointer Parameter is
> NULL.\n"));
> + *ImageUpdateable = IMAGE_UPDATABLE_INVALID; //not sure if this is
> needed
> + return EFI_INVALID_PARAMETER;
> + }
> +
> +cleanup:
> + return status;
> +}// CheckImage()
> +
> +/**
> +Device firmware should trigger lock mechanism so that device fw can not be
> updated or tampered with.
> +This lock mechanism is generally only cleared by a full system reset (not just
> sleep state/low power mode)
> +
> + at retval EFI_SUCCESS The device was successfully locked.
> + at retval EFI_UNSUPPORTED The hardware device/firmware doesn't
> support locking
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FmpDeviceLock(
> +)
> +{
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib
> Sample/FmpDeviceLib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib
> Sample/FmpDeviceLib.inf
> new file mode 100644
> index 0000000000..af31fbcffb
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib
> Sample/FmpDeviceLib.inf
> @@ -0,0 +1,34 @@
> +##
> +# Copyright (c) 2016, Microsoft Corporation
> +
> +# All rights reserved.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = Vlv2FmpDeviceLibSample
> + FILE_GUID = 582DF9AB-E626-42A8-A11C-3FEA098FF3FA
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = FmpDeviceLib|DXE_DRIVER
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +[Sources]
> + FmpDeviceLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + FmpDevicePkg/FmpDevicePkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + BaseLib
> + UefiBootServicesTableLib #for stall...remove later as stall is only needed
> to show progress
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/PlatformFlash
> AccessLib/PlatformFlashAccessLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/PlatformFlash
> AccessLib/PlatformFlashAccessLib.c
> new file mode 100644
> index 0000000000..079c3ef2d6
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/PlatformFlash
> AccessLib/PlatformFlashAccessLib.c
> @@ -0,0 +1,685 @@
> +/** @file
> + Platform Flash Access library.
> +
> + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#include <Uefi.h>
> +
> +#include <PiDxe.h>
> +
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PlatformFlashAccessLib.h>
> +//#include <Library/FlashDeviceLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Protocol/Spi.h>
> +#include <Library/CacheMaintenanceLib.h>
> +#include "PchAccess.h"
> +#include <Library/IoLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/PrintLib.h>
> +
> +//#define SECTOR_SIZE_64KB 0x10000 // Common 64kBytes sector size
> +//#define ALINGED_SIZE SECTOR_SIZE_64KB
> +
> +#define BLOCK_SIZE 0x1000
> +#define ALINGED_SIZE BLOCK_SIZE
> +
> +#define R_PCH_LPC_BIOS_CNTL 0xDC
> +#define B_PCH_LPC_BIOS_CNTL_SMM_BWP 0x20 ///< SMM
> BIOS write protect disable
> +
> +//
> +// Prefix Opcode Index on the host SPI controller
> +//
> +typedef enum {
> + SPI_WREN, // Prefix Opcode 0: Write Enable
> + SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register
> +} PREFIX_OPCODE_INDEX;
> +//
> +// Opcode Menu Index on the host SPI controller
> +//
> +typedef enum {
> + SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address
> + SPI_READ, // Opcode 1: READ, Read cycle with address
> + SPI_RDSR, // Opcode 2: Read Status Register, No address
> + SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters,
> No address
> + SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address
> + SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address
> + SPI_PROG, // Opcode 6: Byte Program, Write cycle with address
> + SPI_WRSR, // Opcode 7: Write Status Register, No address
> +} SPI_OPCODE_INDEX;
> +
> +STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress;
> +
> +EFI_SPI_PROTOCOL *mSpiProtocol;
> +
> +/**
> + Read NumBytes bytes of data from the address specified by
> + PAddress into Buffer.
> +
> + @param[in] Address The starting physical address of the read.
> + @param[in,out] NumBytes On input, the number of bytes to read. On
> output, the number
> + of bytes actually read.
> + @param[out] Buffer The destination data buffer for the read.
> +
> + @retval EFI_SUCCESS Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiFlashRead (
> + IN UINTN Address,
> + IN OUT UINT32 *NumBytes,
> + OUT UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + UINTN Offset = 0;
> +
> + ASSERT ((NumBytes != NULL) && (Buffer != NULL));
> +
> +
> + //if (Address >= (UINTN)PcdGet32 (PcdGbeRomBase) && Address <
> (UINTN)PcdGet32 (PcdPDRRomBase)) {
> + Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);
> +
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + 1, //SPI_READ,
> + 0, //SPI_WREN,
> + TRUE,
> + TRUE,
> + FALSE,
> + Offset,
> + BLOCK_SIZE,
> + Buffer,
> + EnumSpiRegionAll
> + );
> + return Status;
> +}
> +
> +/**
> + Write NumBytes bytes of data from Buffer to the address specified by
> + PAddresss.
> +
> + @param[in] Address The starting physical address of the write.
> + @param[in,out] NumBytes On input, the number of bytes to write. On
> output,
> + the actual number of bytes written.
> + @param[in] Buffer The source data buffer for the write.
> +
> + @retval EFI_SUCCESS Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiFlashWrite (
> + IN UINTN Address,
> + IN OUT UINT32 *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Offset;
> + UINT32 Length;
> + UINT32 RemainingBytes;
> +
> + ASSERT ((NumBytes != NULL) && (Buffer != NULL));
> + ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase));
> +
> + Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);
> +
> + ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize));
> +
> + Status = EFI_SUCCESS;
> + RemainingBytes = *NumBytes;
> +
> + while (RemainingBytes > 0) {
> + if (RemainingBytes > SIZE_4KB) {
> + Length = SIZE_4KB;
> + } else {
> + Length = RemainingBytes;
> + }
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_PROG,
> + SPI_WREN,
> + TRUE,
> + TRUE,
> + TRUE,
> + (UINT32) Offset,
> + Length,
> + Buffer,
> + EnumSpiRegionAll
> + );
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + RemainingBytes -= Length;
> + Offset += Length;
> + Buffer += Length;
> + }
> +
> + //
> + // Actual number of bytes written
> + //
> + *NumBytes -= RemainingBytes;
> +
> + return Status;
> +}
> +
> +
> +EFI_STATUS
> +InternalReadBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + OUT VOID *ReadBuffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 BlockSize;
> +
> + BlockSize = BLOCK_SIZE;
> +
> + Status = SpiFlashRead ((UINTN) BaseAddress, &BlockSize, ReadBuffer);
> +
> + return Status;
> +}
> +
> +/**
> + Erase the block starting at Address.
> +
> + @param[in] Address The starting physical address of the block to be
> erased.
> + This library assume that caller garantee that the PAddress
> + is at the starting address of this block.
> + @param[in] NumBytes On input, the number of bytes of the logical
> block to be erased.
> + On output, the actual number of bytes erased.
> +
> + @retval EFI_SUCCESS. Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiFlashBlockErase (
> + IN UINTN Address,
> + IN UINTN *NumBytes
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Offset;
> + UINTN RemainingBytes;
> +
> + ASSERT (NumBytes != NULL);
> + ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase));
> +
> + Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);
> +
> + ASSERT ((*NumBytes % SIZE_4KB) == 0);
> + ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize));
> +
> + Status = EFI_SUCCESS;
> + RemainingBytes = *NumBytes;
> +
> + //
> + // To adjust the Offset with Bios/Gbe
> + //
> +// if (Address >= (UINTN)PcdGet32 (PcdFlashChipBase)) {
> +// Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);
> +
> + while (RemainingBytes > 0) {
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_SERASE,
> + SPI_WREN,
> + FALSE,
> + TRUE,
> + FALSE,
> + (UINT32) Offset,
> + 0,
> + NULL,
> + EnumSpiRegionAll
> + );
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + RemainingBytes -= SIZE_4KB;
> + Offset += SIZE_4KB;
> + }
> +// }
> +
> + //
> + // Actual number of bytes erased
> + //
> + *NumBytes -= RemainingBytes;
> +
> + return Status;
> +}
> +
> +/**
> +
> +Routine Description:
> +
> + Erase the whole block.
> +
> +Arguments:
> +
> + BaseAddress - Base address of the block to be erased.
> +
> +Returns:
> +
> + EFI_SUCCESS - The command completed successfully.
> + Other - Device error or wirte-locked, operation failed.
> +
> +**/
> +EFI_STATUS
> +InternalEraseBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress
> + )
> +{
> + EFI_STATUS Status;
> + UINTN NumBytes;
> +
> + NumBytes = BLOCK_SIZE;
> +
> + Status = SpiFlashBlockErase ((UINTN) BaseAddress, &NumBytes);
> +
> + return Status;
> +}
> +
> +EFI_STATUS
> +InternalCompareBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + IN UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + VOID *CompareBuffer;
> + UINT32 NumBytes;
> + INTN CompareResult;
> +
> + NumBytes = BLOCK_SIZE;
> + CompareBuffer = AllocatePool (NumBytes);
> + if (CompareBuffer == NULL) {
> + Status = EFI_OUT_OF_RESOURCES;
> + goto Done;
> + }
> +
> + Status = SpiFlashRead ((UINTN) BaseAddress, &NumBytes,
> CompareBuffer);
> + if (EFI_ERROR (Status)) {
> + goto Done;
> + }
> + CompareResult = CompareMem (CompareBuffer, Buffer, BLOCK_SIZE);
> + if (CompareResult != 0) {
> + Status = EFI_VOLUME_CORRUPTED;
> + }
> +
> +Done:
> + if (CompareBuffer != NULL) {
> + FreePool (CompareBuffer);
> + }
> +
> + return Status;
> +}
> +
> +/**
> +
> +Routine Description:
> +
> + Write a block of data.
> +
> +Arguments:
> +
> + BaseAddress - Base address of the block.
> + Buffer - Data buffer.
> + BufferSize - Size of the buffer.
> +
> +Returns:
> +
> + EFI_SUCCESS - The command completed successfully.
> + EFI_INVALID_PARAMETER - Invalid parameter, can not proceed.
> + Other - Device error or wirte-locked, operation failed.
> +
> +**/
> +EFI_STATUS
> +InternalWriteBlock (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + IN UINT8 *Buffer,
> + IN UINT32 BufferSize
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = SpiFlashWrite ((UINTN) BaseAddress, &BufferSize, Buffer);
> +
> + if (EFI_ERROR (Status)) {
> + DEBUG((DEBUG_ERROR, "\nFlash write error."));
> + return Status;
> + }
> +
> + WriteBackInvalidateDataCacheRange ((VOID *) (UINTN) BaseAddress,
> BLOCK_SIZE);
> +
> + Status = InternalCompareBlock (BaseAddress, Buffer);
> + if (EFI_ERROR (Status)) {
> + DEBUG((DEBUG_ERROR, "\nError when writing to BaseAddress %x with
> different at offset %x.", BaseAddress, Status));
> + } else {
> + DEBUG((DEBUG_INFO, "\nVerified data written to Block at %x is correct.",
> BaseAddress));
> + }
> +
> + return Status;
> +
> +}
> +
> +/**
> + Perform flash write operation with progress indicator. The start and end
> + completion percentage values are passed into this function. If the
> requested
> + flash write operation is broken up, then completion percentage between
> the
> + start and end values may be passed to the provided Progress function.
> The
> + caller of this function is required to call the Progress function for the
> + start and end completion percentage values. This allows the Progress,
> + StartPercentage, and EndPercentage parameters to be ignored if the
> requested
> + flash write operation can not be broken up
> +
> + @param[in] FirmwareType The type of firmware.
> + @param[in] FlashAddress The address of flash device to be accessed.
> + @param[in] FlashAddressType The type of flash device address.
> + @param[in] Buffer The pointer to the data buffer.
> + @param[in] Length The length of data buffer in bytes.
> + @param[in] Progress A function used report the progress of the
> + firmware update. This is an optional parameter
> + that may be NULL.
> + @param[in] StartPercentage The start completion percentage value that
> may
> + be used to report progress during the flash
> + write operation.
> + @param[in] EndPercentage The end completion percentage value that
> may
> + be used to report progress during the flash
> + write operation.
> +
> + @retval EFI_SUCCESS The operation returns successfully.
> + @retval EFI_WRITE_PROTECTED The flash device is read only.
> + @retval EFI_UNSUPPORTED The flash device access is unsupported.
> + @retval EFI_INVALID_PARAMETER The input parameter is not valid.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PerformFlashWriteWithProgress (
> + IN PLATFORM_FIRMWARE_TYPE FirmwareType,
> + IN EFI_PHYSICAL_ADDRESS FlashAddress,
> + IN FLASH_ADDRESS_TYPE FlashAddressType,
> + IN VOID *Buffer,
> + IN UINTN Length,
> + IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress,
> OPTIONAL
> + IN UINTN StartPercentage,
> + IN UINTN EndPercentage
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + UINTN Index;
> + EFI_PHYSICAL_ADDRESS Address;
> + UINTN CountOfBlocks;
> + EFI_TPL OldTpl;
> + BOOLEAN FlashError;
> + UINT8 *Buf;
> + UINTN LpcBaseAddress;
> + UINT8 Data8Or;
> + UINT8 Data8And;
> + UINT8 BiosCntl;
> +
> + Index = 0;
> + Address = 0;
> + CountOfBlocks = 0;
> + FlashError = FALSE;
> + Buf = Buffer;
> +
> + DEBUG((DEBUG_INFO | DEBUG_ERROR, "PerformFlashWrite - 0x%x(%x) -
> 0x%x\n", (UINTN)FlashAddress, (UINTN)FlashAddressType, Length));
> + if (FlashAddressType == FlashAddressTypeRelativeAddress) {
> + FlashAddress = FlashAddress + mInternalFdAddress;
> + }
> +
> + CountOfBlocks = (UINTN) (Length / BLOCK_SIZE);
> + Address = FlashAddress;
> +
> + LpcBaseAddress = MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + 0
> + );
> + BiosCntl = MmioRead8 (LpcBaseAddress + R_PCH_LPC_BIOS_CNTL);
> + if ((BiosCntl & B_PCH_LPC_BIOS_CNTL_SMM_BWP) ==
> B_PCH_LPC_BIOS_CNTL_SMM_BWP) {
> + ///
> + /// Clear SMM_BWP bit (D31:F0:RegDCh[5])
> + ///
> + Data8And = (UINT8) ~B_PCH_LPC_BIOS_CNTL_SMM_BWP;
> + Data8Or = 0x00;
> +
> + MmioAndThenOr8 (
> + LpcBaseAddress + R_PCH_LPC_BIOS_CNTL,
> + Data8And,
> + Data8Or
> + );
> + DEBUG((DEBUG_INFO, "PerformFlashWrite Clear SMM_BWP bit\n"));
> + }
> +
> + //
> + // Raise TPL to TPL_NOTIFY to block any event handler,
> + // while still allowing RaiseTPL(TPL_NOTIFY) within
> + // output driver during Print()
> + //
> + OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
> + for (Index = 0; Index < CountOfBlocks; Index++) {
> + if (Progress != NULL) {
> + Progress (StartPercentage + ((Index * (EndPercentage -
> StartPercentage)) / CountOfBlocks));
> + }
> + //
> + // Handle block based on address and contents.
> + //
> + if (!EFI_ERROR (InternalCompareBlock (Address, Buf))) {
> + DEBUG((DEBUG_INFO, "Skipping block at 0x%lx (already
> programmed)\n", Address));
> + } else {
> + //
> + // Make updating process uninterruptable,
> + // so that the flash memory area is not accessed by other entities
> + // which may interfere with the updating process
> + //
> + Status = InternalEraseBlock (Address);
> + if (EFI_ERROR(Status)) {
> + gBS->RestoreTPL (OldTpl);
> + FlashError = TRUE;
> + goto Done;
> + }
> + Status = InternalWriteBlock (
> + Address,
> + Buf,
> + (UINT32)(Length > BLOCK_SIZE ? BLOCK_SIZE : Length)
> + );
> + if (EFI_ERROR(Status)) {
> + gBS->RestoreTPL (OldTpl);
> + FlashError = TRUE;
> + goto Done;
> + }
> + }
> +
> + //
> + // Move to next block to update.
> + //
> + Address += BLOCK_SIZE;
> + Buf += BLOCK_SIZE;
> + if (Length > BLOCK_SIZE) {
> + Length -= BLOCK_SIZE;
> + } else {
> + Length = 0;
> + }
> + }
> + gBS->RestoreTPL (OldTpl);
> +
> +Done:
> + if ((BiosCntl & B_PCH_LPC_BIOS_CNTL_SMM_BWP) ==
> B_PCH_LPC_BIOS_CNTL_SMM_BWP) {
> + //
> + // Restore original control setting
> + //
> + MmioWrite8 (LpcBaseAddress + R_PCH_LPC_BIOS_CNTL, BiosCntl);
> + }
> +
> + if (Progress != NULL) {
> + Progress (EndPercentage);
> + }
> +
> + if (FlashError) {
> + return EFI_WRITE_PROTECTED;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Perform flash write operation.
> +
> + @param[in] FirmwareType The type of firmware.
> + @param[in] FlashAddress The address of flash device to be accessed.
> + @param[in] FlashAddressType The type of flash device address.
> + @param[in] Buffer The pointer to the data buffer.
> + @param[in] Length The length of data buffer in bytes.
> +
> + @retval EFI_SUCCESS The operation returns successfully.
> + @retval EFI_WRITE_PROTECTED The flash device is read only.
> + @retval EFI_UNSUPPORTED The flash device access is unsupported.
> + @retval EFI_INVALID_PARAMETER The input parameter is not valid.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PerformFlashWrite (
> + IN PLATFORM_FIRMWARE_TYPE FirmwareType,
> + IN EFI_PHYSICAL_ADDRESS FlashAddress,
> + IN FLASH_ADDRESS_TYPE FlashAddressType,
> + IN VOID *Buffer,
> + IN UINTN Length
> + )
> +{
> + return PerformFlashWriteWithProgress (
> + FirmwareType,
> + FlashAddress,
> + FlashAddressType,
> + Buffer,
> + Length,
> + NULL,
> + 0,
> + 0
> + );
> +}
> +
> +/**
> + Perform microcode write operation.
> +
> + @param[in] FlashAddress The address of flash device to be accessed.
> + @param[in] Buffer The pointer to the data buffer.
> + @param[in] Length The length of data buffer in bytes.
> +
> + @retval EFI_SUCCESS The operation returns successfully.
> + @retval EFI_WRITE_PROTECTED The flash device is read only.
> + @retval EFI_UNSUPPORTED The flash device access is unsupported.
> + @retval EFI_INVALID_PARAMETER The input parameter is not valid.
> +**/
> +EFI_STATUS
> +EFIAPI
> +MicrocodeFlashWrite (
> + IN EFI_PHYSICAL_ADDRESS FlashAddress,
> + IN VOID *Buffer,
> + IN UINTN Length
> + )
> +{
> + EFI_PHYSICAL_ADDRESS AlignedFlashAddress;
> + VOID *AlignedBuffer;
> + UINTN AlignedLength;
> + UINTN OffsetHead;
> + UINTN OffsetTail;
> + EFI_STATUS Status;
> +
> + DEBUG((DEBUG_INFO, "MicrocodeFlashWrite - 0x%x - 0x%x\n",
> (UINTN)FlashAddress, Length));
> +
> + //
> + // Need make buffer 64K aligned to support ERASE
> + //
> + // [Aligned] FlashAddress [Aligned]
> + // | | |
> + // V V V
> + // +--------------+========+------------+
> + // | OffsetHeader | Length | OffsetTail |
> + // +--------------+========+------------+
> + // ^
> + // |<-----------AlignedLength----------->
> + // |
> + // AlignedFlashAddress
> + //
> + OffsetHead = FlashAddress & (ALINGED_SIZE - 1);
> + OffsetTail = (FlashAddress + Length) & (ALINGED_SIZE - 1);
> + if (OffsetTail != 0) {
> + OffsetTail = ALINGED_SIZE - OffsetTail;
> + }
> +
> + if ((OffsetHead != 0) || (OffsetTail != 0)) {
> + AlignedFlashAddress = FlashAddress - OffsetHead;
> + AlignedLength = Length + OffsetHead + OffsetTail;
> +
> + AlignedBuffer = AllocatePool(AlignedLength);
> + if (AlignedBuffer == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + //
> + // Save original buffer
> + //
> + if (OffsetHead != 0) {
> + CopyMem((UINT8 *)AlignedBuffer, (VOID
> *)(UINTN)AlignedFlashAddress, OffsetHead);
> + }
> + if (OffsetTail != 0) {
> + CopyMem((UINT8 *)AlignedBuffer + OffsetHead + Length, (VOID
> *)(UINTN)(AlignedFlashAddress + OffsetHead + Length), OffsetTail);
> + }
> + //
> + // Override new buffer
> + //
> + CopyMem((UINT8 *)AlignedBuffer + OffsetHead, Buffer, Length);
> + } else {
> + AlignedFlashAddress = FlashAddress;
> + AlignedBuffer = Buffer;
> + AlignedLength = Length;
> + }
> +
> + Status = PerformFlashWrite(
> + PlatformFirmwareTypeSystemFirmware,
> + AlignedFlashAddress,
> + FlashAddressTypeAbsoluteAddress,
> + AlignedBuffer,
> + AlignedLength
> + );
> + if ((OffsetHead != 0) || (OffsetTail != 0)) {
> + FreePool (AlignedBuffer);
> + }
> + return Status;
> +}
> +
> +/**
> + Platform Flash Access Lib Constructor.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PerformFlashAccessLibConstructor (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + mInternalFdAddress =
> (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32(PcdFlashAreaBaseAddress);
> + DEBUG((DEBUG_INFO, "PcdFlashAreaBaseAddress - 0x%x\n",
> mInternalFdAddress));
> +
> + Status = gBS->LocateProtocol (
> + &gEfiSpiProtocolGuid,
> + NULL,
> + (VOID **) &mSpiProtocol
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/PlatformFlash
> AccessLib/PlatformFlashAccessLib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/PlatformFlash
> AccessLib/PlatformFlashAccessLib.inf
> new file mode 100644
> index 0000000000..9b29b05bac
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/Library/PlatformFlash
> AccessLib/PlatformFlashAccessLib.inf
> @@ -0,0 +1,54 @@
> +## @file
> +# Platform Flash Access library.
> +#
> +# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformFlashAccessLib
> + FILE_GUID = 31CF9CEC-DA4E-4505-AA20-33364A291A95
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PlatformFlashAccessLib
> + LIBRARY_CLASS = MicrocodeFlashAccessLib
> + CONSTRUCTOR = PerformFlashAccessLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + PlatformFlashAccessLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + SignedCapsulePkg/SignedCapsulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + BaseMemoryLib
> + IoLib
> + PcdLib
> + DebugLib
> + MemoryAllocationLib
> + CacheMaintenanceLib
> +
> +[Guids]
> + gEdkiiSystemFmpCapsuleConfigFileGuid ## SOMETIMES_CONSUMES
> ## GUID
> +
> +[Protocols]
> + gEfiSpiProtocolGuid ## CONSUMES
> +
> +[Pcd]
> + gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress ##
> SOMETIMES_CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdFlashChipBase ##
> SOMETIMES_CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdFlashChipSize ##
> SOMETIMES_CONSUMES
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ##
> SOMETIMES_CONSUMES
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescr
> iptor/SystemFirmwareDescriptor.aslc
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescr
> iptor/SystemFirmwareDescriptor.aslc
> new file mode 100644
> index 0000000000..884da36b97
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescr
> iptor/SystemFirmwareDescriptor.aslc
> @@ -0,0 +1,83 @@
> +/** @file
> + System Firmware descriptor.
> +
> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Protocol/FirmwareManagement.h>
> +#include <Guid/EdkiiSystemFmpCapsule.h>
> +
> +#define PACKAGE_VERSION 0xFFFFFFFF
> +#define PACKAGE_VERSION_STRING L"Unknown"
> +
> +#define CURRENT_FIRMWARE_VERSION 0x00000002
> +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002"
> +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001
> +
> +#define IMAGE_ID SIGNATURE_64('V', 'L', 'V', '2', '_', '_', 'F', 'd')
> +#define IMAGE_ID_STRING L"Vlv2Fd"
> +
> +// PcdSystemFmpCapsuleImageTypeIdGuid
> +#define IMAGE_TYPE_ID_GUID { 0x4096267b, 0xda0a, 0x42eb,
> { 0xb5, 0xeb, 0xfe, 0xf3, 0x1d, 0x20, 0x7c, 0xb4 } }
> +
> +typedef struct {
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
> + // real string data
> + CHAR16
> ImageIdNameStr[sizeof(IMAGE_ID_STRING)/sizeof(CHAR16)];
> + CHAR16
> VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING)/sizeof(CH
> AR16)];
> + CHAR16
> PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING)/sizeof(CHAR1
> 6)];
> +} IMAGE_DESCRIPTOR;
> +
> +IMAGE_DESCRIPTOR mImageDescriptor =
> +{
> + {
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE,
> + sizeof(EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR),
> + sizeof(IMAGE_DESCRIPTOR),
> + PACKAGE_VERSION, // PackageVersion
> + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), //
> PackageVersionName
> + 1, // ImageIndex;
> + {0x0}, // Reserved
> + IMAGE_TYPE_ID_GUID, // ImageTypeId;
> + IMAGE_ID, // ImageId;
> + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), //
> ImageIdName;
> + CURRENT_FIRMWARE_VERSION, // Version;
> + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), //
> VersionName;
> + {0x0}, // Reserved2
> + FixedPcdGet32(PcdFlashAreaSize), // Size;
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported;
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting;
> + 0x0, // Compatibilities;
> + LOWEST_SUPPORTED_FIRMWARE_VERSION, //
> LowestSupportedImageVersion;
> + 0x00000000, // LastAttemptVersion;
> + 0, // LastAttemptStatus;
> + {0x0}, // Reserved3
> + 0, // HardwareInstance;
> + },
> + // real string data
> + {IMAGE_ID_STRING},
> + {CURRENT_FIRMWARE_VERSION_STRING},
> + {PACKAGE_VERSION_STRING},
> +};
> +
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +{
> + //
> + // Reference the table being generated to prevent the optimizer from
> + // removing the data structure from the executable
> + //
> + return (VOID*)&mImageDescriptor;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescr
> iptor/SystemFirmwareDescriptor.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescr
> iptor/SystemFirmwareDescriptor.inf
> new file mode 100644
> index 0000000000..dd85c86d95
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescr
> iptor/SystemFirmwareDescriptor.inf
> @@ -0,0 +1,40 @@
> +## @file
> +# System Firmware descriptor.
> +#
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SystemFirmwareDescriptor
> + FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + ENTRY_POINT = SystemFirmwareDescriptorPeimEntry
> +
> +[Sources]
> + SystemFirmwareDescriptorPei.c
> + SystemFirmwareDescriptor.aslc
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + SignedCapsulePkg/SignedCapsulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + PcdLib
> + PeiServicesLib
> + DebugLib
> + PeimEntryPoint
> +
> +[FixedPcd]
> + gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize
> +
> +[Pcd]
> +
> gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescri
> ptor
> +
> +[Depex]
> + TRUE
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescr
> iptor/SystemFirmwareDescriptorPei.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescr
> iptor/SystemFirmwareDescriptorPei.c
> new file mode 100644
> index 0000000000..d21ee52184
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareDescr
> iptor/SystemFirmwareDescriptorPei.c
> @@ -0,0 +1,60 @@
> +/** @file
> + System Firmware descriptor producer.
> +
> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/DebugLib.h>
> +#include <Protocol/FirmwareManagement.h>
> +#include <Guid/EdkiiSystemFmpCapsule.h>
> +
> +/**
> + Entrypoint for SystemFirmwareDescriptor PEIM.
> +
> + @param[in] FileHandle Handle of the file being invoked.
> + @param[in] PeiServices Describes the list of possible PEI Services.
> +
> + @retval EFI_SUCCESS PPI successfully installed.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SystemFirmwareDescriptorPeimEntry (
> + IN EFI_PEI_FILE_HANDLE FileHandle,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor;
> + UINTN Size;
> + UINTN Index;
> + UINT32 AuthenticationStatus;
> +
> + //
> + // Search RAW section.
> + //
> + Index = 0;
> + while (TRUE) {
> + Status = PeiServicesFfsFindSectionData3(EFI_SECTION_RAW, Index,
> FileHandle, (VOID **)&Descriptor, &AuthenticationStatus);
> + if (EFI_ERROR(Status)) {
> + // Should not happen, must something wrong in FDF.
> + ASSERT(FALSE);
> + return EFI_NOT_FOUND;
> + }
> + if (Descriptor->Signature ==
> EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) {
> + break;
> + }
> + Index++;
> + }
> +
> + DEBUG((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR
> size - 0x%x\n", Descriptor->Length));
> +
> + Size = Descriptor->Length;
> + PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor);
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpda
> teConfig/SystemFirmwareUpdateConfig.ini
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpda
> teConfig/SystemFirmwareUpdateConfig.ini
> new file mode 100644
> index 0000000000..126cd123b1
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpda
> teConfig/SystemFirmwareUpdateConfig.ini
> @@ -0,0 +1,66 @@
> +## @file
> +#
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Head]
> +NumOfUpdate = 6
> +NumOfRecovery = 1
> +Update0 = Vlv2FvMicrocode
> +Update1 = Vlv2FvBinary
> +Update2 = Vlv2FvMain
> +Update3 = Vlv2FvRecovery2
> +Update4 = Vlv2FvRecovery
> +Update5 = Vlv2FvNvRam
> +Recovery0 = Vlv2FvMain
> +
> +[Vlv2FvMicrocode]
> +FirmwareType = 0 # SystemFirmware
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00000000 # Base address offset on flash
> +Length = 0x00040000 # Length
> +ImageOffset = 0x00000000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> +[Vlv2FvNvRam]
> +FirmwareType = 1 # NvRam
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00040000 # Base address offset on flash
> +Length = 0x00080000 # Length
> +ImageOffset = 0x00040000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> +[Vlv2FvBinary]
> +FirmwareType = 0 # SystemFirmware
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x000C0000 # Base address offset on flash
> +Length = 0x00050000 # Length
> +ImageOffset = 0x000C0000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> +[Vlv2FvMain]
> +FirmwareType = 0 # SystemFirmware
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00110000 # Base address offset on flash
> +Length = 0x00210000 # Length
> +ImageOffset = 0x00110000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> +[Vlv2FvRecovery2]
> +FirmwareType = 0 # SystemFirmware
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00320000 # Base address offset on flash
> +Length = 0x00070000 # Length
> +ImageOffset = 0x00320000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> +[Vlv2FvRecovery]
> +FirmwareType = 0 # SystemFirmware
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00390000 # Base address offset on flash
> +Length = 0x00070000 # Length
> +ImageOffset = 0x00390000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpda
> teConfig/SystemFirmwareUpdateConfigGcc.ini
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpda
> teConfig/SystemFirmwareUpdateConfigGcc.ini
> new file mode 100644
> index 0000000000..e22f136f8e
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpda
> teConfig/SystemFirmwareUpdateConfigGcc.ini
> @@ -0,0 +1,66 @@
> +## @file
> +#
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Head]
> +NumOfUpdate = 6
> +NumOfRecovery = 1
> +Update0 = Vlv2FvMicrocode
> +Update1 = Vlv2FvBinary
> +Update2 = Vlv2FvMain
> +Update3 = Vlv2FvRecovery2
> +Update4 = Vlv2FvRecovery
> +Update5 = Vlv2FvNvRam
> +Recovery0 = Vlv2FvMain
> +
> +[Vlv2FvMicrocode]
> +FirmwareType = 0 # SystemFirmware
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00000000 # Base address offset on flash
> +Length = 0x00040000 # Length
> +ImageOffset = 0x00000000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> +[Vlv2FvNvRam]
> +FirmwareType = 1 # NvRam
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00040000 # Base address offset on flash
> +Length = 0x00080000 # Length
> +ImageOffset = 0x00040000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> +[Vlv2FvBinary]
> +FirmwareType = 0 # SystemFirmware
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x000C0000 # Base address offset on flash
> +Length = 0x00050000 # Length
> +ImageOffset = 0x000C0000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> +[Vlv2FvMain]
> +FirmwareType = 0 # SystemFirmware
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00110000 # Base address offset on flash
> +Length = 0x00215000 # Length
> +ImageOffset = 0x00110000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> +[Vlv2FvRecovery2]
> +FirmwareType = 0 # SystemFirmware
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00325000 # Base address offset on flash
> +Length = 0x0006B000 # Length
> +ImageOffset = 0x00325000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> +[Vlv2FvRecovery]
> +FirmwareType = 0 # SystemFirmware
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00390000 # Base address offset on flash
> +Length = 0x00070000 # Length
> +ImageOffset = 0x00390000 # Image offset of this SystemFirmware image
> +FileGuid = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 #
> PcdEdkiiSystemFirmwareFileGuid
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FmpBlueSampleDevice.dsc
> b/Platform/Intel/Vlv2TbltDevicePkg/FmpBlueSampleDevice.dsc
> new file mode 100644
> index 0000000000..3bd9f150b3
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FmpBlueSampleDevice.dsc
> @@ -0,0 +1,55 @@
> +#/** @file
> +# FmpDxe driver for Blue Sample device firmware update.
> +#
> +# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#**/
> +
> + FmpDevicePkg/FmpDxe/FmpDxe.inf {
> + <Defines>
> + #
> + # ESRT and FMP GUID for sample device capsule update
> + #
> + FILE_GUID = $(FMP_BLUE_SAMPLE_DEVICE)
> + <PcdsFixedAtBuild>
> + #
> + # Unicode name string that is used to populate FMP Image Descriptor for
> this capsule update module
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceImageIdName|L"Sample
> Firmware Device"
> +
> + #
> + # ESRT and FMP Lowest Support Version for this capsule update module
> + # 000.000.000.000
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceBuildTimeLowestSupported
> Version|0x00000000
> +
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceProgressWatchdogTimeInSe
> conds|2
> +
> + #
> + # Capsule Update Progress Bar Color. Set to Blue (RGB) (0, 0, 255)
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceProgressColor|0x000000FF
> +
> + #
> + # Certificates used to authenticate capsule update image
> + #
> + !include Vlv2TbltDevicePkg/FmpCertificate.dsc
> +
> + <LibraryClasses>
> + #
> + # Generic libraries that are used "as is" by all FMP modules
> + #
> +
> FmpPayloadHeaderLib|FmpDevicePkg/Library/FmpPayloadHeaderLibV1/Fm
> pPayloadHeaderLibV1.inf
> +
> FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/Fmp
> AuthenticationLibPkcs7.inf
> + #
> + # Platform specific capsule policy library
> + #
> +
> CapsuleUpdatePolicyLib|FmpDevicePkg/Library/CapsuleUpdatePolicyLibNull
> /CapsuleUpdatePolicyLibNull.inf
> + #
> + # Device specific library that processes a capsule and updates the FW
> storage device
> + #
> +
> FmpDeviceLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLibSa
> mple/FmpDeviceLib.inf
> + }
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FmpCertificate.dsc
> b/Platform/Intel/Vlv2TbltDevicePkg/FmpCertificate.dsc
> new file mode 100644
> index 0000000000..237ec87ac8
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FmpCertificate.dsc
> @@ -0,0 +1,22 @@
> +#/** @file
> +# FMP Certificates shared by multiple FmpDxe drivers for firmware update.
> +#
> +# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#**/
> +
> +!if $(CAPSULE_PKCS7_CERT) ==
> SAMPLE_DEVELOPMENT_SAMPLE_PRODUCTION
> + !include
> Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/SAMPLE_DEVELOPM
> ENT_SAMPLE_PRODUCTION.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpD
> evicePkcs7CertBufferXdr.inc
> +!endif
> +!if $(CAPSULE_PKCS7_CERT) == SAMPLE_DEVELOPMENT
> + !include
> Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/SAMPLE_DEVELOPM
> ENT.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferXdr.
> inc
> +!endif
> +!if $(CAPSULE_PKCS7_CERT) == EDKII_TEST
> + !include
> BaseTools/Source/Python/Pkcs7Sign/TestRoot.cer.gFmpDevicePkgTokenSpa
> ceGuid.PcdFmpDevicePkcs7CertBufferXdr.inc
> +!endif
> +!if $(CAPSULE_PKCS7_CERT) == NEW_ROOT
> + !include
> Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/NewRoot.cer.gFmpD
> evicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferXdr.inc
> +!endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FmpGreenSampleDevice.dsc
> b/Platform/Intel/Vlv2TbltDevicePkg/FmpGreenSampleDevice.dsc
> new file mode 100644
> index 0000000000..61bdd36a96
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FmpGreenSampleDevice.dsc
> @@ -0,0 +1,55 @@
> +#/** @file
> +# FmpDxe driver for Green Sample device firmware update.
> +#
> +# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#**/
> +
> + FmpDevicePkg/FmpDxe/FmpDxe.inf {
> + <Defines>
> + #
> + # ESRT and FMP GUID for sample device capsule update
> + #
> + FILE_GUID = $(FMP_GREEN_SAMPLE_DEVICE)
> + <PcdsFixedAtBuild>
> + #
> + # Unicode name string that is used to populate FMP Image Descriptor for
> this capsule update module
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceImageIdName|L"Sample
> Firmware Device"
> +
> + #
> + # ESRT and FMP Lowest Support Version for this capsule update module
> + # 000.000.000.000
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceBuildTimeLowestSupported
> Version|0x00000000
> +
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceProgressWatchdogTimeInSe
> conds|2
> +
> + #
> + # Capsule Update Progress Bar Color. Set to Green (RGB) (0, 255, 0)
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceProgressColor|0x0000FF00
> +
> + #
> + # Certificates used to authenticate capsule update image
> + #
> + !include Vlv2TbltDevicePkg/FmpCertificate.dsc
> +
> + <LibraryClasses>
> + #
> + # Generic libraries that are used "as is" by all FMP modules
> + #
> +
> FmpPayloadHeaderLib|FmpDevicePkg/Library/FmpPayloadHeaderLibV1/Fm
> pPayloadHeaderLibV1.inf
> +
> FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/Fmp
> AuthenticationLibPkcs7.inf
> + #
> + # Platform specific capsule policy library
> + #
> +
> CapsuleUpdatePolicyLib|FmpDevicePkg/Library/CapsuleUpdatePolicyLibNull
> /CapsuleUpdatePolicyLibNull.inf
> + #
> + # Device specific library that processes a capsule and updates the FW
> storage device
> + #
> +
> FmpDeviceLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLibSa
> mple/FmpDeviceLib.inf
> + }
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FmpMinnowMaxSystem.dsc
> b/Platform/Intel/Vlv2TbltDevicePkg/FmpMinnowMaxSystem.dsc
> new file mode 100644
> index 0000000000..304519b294
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FmpMinnowMaxSystem.dsc
> @@ -0,0 +1,59 @@
> +#/** @file
> +# FmpDxe driver for Minnow Max system firmware update.
> +#
> +# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#**/
> +
> + FmpDevicePkg/FmpDxe/FmpDxe.inf {
> + <Defines>
> + #
> + # ESRT and FMP GUID for system firmware capsule update
> + #
> + FILE_GUID = $(FMP_MINNOW_MAX_SYSTEM)
> + <PcdsFixedAtBuild>
> + #
> + # Unicode name string that is used to populate FMP Image Descriptor for
> this capsule update module
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceImageIdName|L"Minnow
> Max System Firmware Device"
> +
> + #
> + # ESRT and FMP Lowest Support Version for this capsule update module
> + # 000.000.000.000
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceBuildTimeLowestSupported
> Version|0x00000000
> +
> +
> gPlatformModuleTokenSpaceGuid.PcdSystemFirmwareFmpLowestSupporte
> dVersion|0x00000000
> +
> gPlatformModuleTokenSpaceGuid.PcdSystemFirmwareFmpVersion|0x00000
> 000
> +
> gPlatformModuleTokenSpaceGuid.PcdSystemFirmwareFmpVersionString|"0
> 00.000.000.000"
> +
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceProgressWatchdogTimeInSe
> conds|4
> +
> + #
> + # Capsule Update Progress Bar Color. Set to Purple (RGB) (255, 0, 255)
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceProgressColor|0x00FF00FF
> +
> + #
> + # Certificates used to authenticate capsule update image
> + #
> + !include Vlv2TbltDevicePkg/FmpCertificate.dsc
> +
> + <LibraryClasses>
> + #
> + # Generic libraries that are used "as is" by all FMP modules
> + #
> +
> FmpPayloadHeaderLib|FmpDevicePkg/Library/FmpPayloadHeaderLibV1/Fm
> pPayloadHeaderLibV1.inf
> +
> FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/Fmp
> AuthenticationLibPkcs7.inf
> + #
> + # Platform specific capsule policy library
> + #
> +
> CapsuleUpdatePolicyLib|FmpDevicePkg/Library/CapsuleUpdatePolicyLibNull
> /CapsuleUpdatePolicyLibNull.inf
> + #
> + # Device specific library that processes a capsule and updates the FW
> storage device
> + #
> +
> FmpDeviceLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLib/F
> mpDeviceLib.inf
> + }
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FmpRedSampleDevice.dsc
> b/Platform/Intel/Vlv2TbltDevicePkg/FmpRedSampleDevice.dsc
> new file mode 100644
> index 0000000000..59851f2b41
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FmpRedSampleDevice.dsc
> @@ -0,0 +1,55 @@
> +#/** @file
> +# FmpDxe driver for Red Sample device firmware update.
> +#
> +# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#**/
> +
> + FmpDevicePkg/FmpDxe/FmpDxe.inf {
> + <Defines>
> + #
> + # ESRT and FMP GUID for sample device capsule update
> + #
> + FILE_GUID = $(FMP_RED_SAMPLE_DEVICE)
> + <PcdsFixedAtBuild>
> + #
> + # Unicode name string that is used to populate FMP Image Descriptor for
> this capsule update module
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceImageIdName|L"Sample
> Firmware Device"
> +
> + #
> + # ESRT and FMP Lowest Support Version for this capsule update module
> + # 000.000.000.000
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceBuildTimeLowestSupported
> Version|0x00000000
> +
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceProgressWatchdogTimeInSe
> conds|2
> +
> + #
> + # Capsule Update Progress Bar Color. Set to Blue (RGB) (255, 0, 0)
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceProgressColor|0x00FF0000
> +
> + #
> + # Certificates used to authenticate capsule update image
> + #
> + !include Vlv2TbltDevicePkg/FmpCertificate.dsc
> +
> + <LibraryClasses>
> + #
> + # Generic libraries that are used "as is" by all FMP modules
> + #
> +
> FmpPayloadHeaderLib|FmpDevicePkg/Library/FmpPayloadHeaderLibV1/Fm
> pPayloadHeaderLibV1.inf
> +
> FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/Fmp
> AuthenticationLibPkcs7.inf
> + #
> + # Platform specific capsule policy library
> + #
> +
> CapsuleUpdatePolicyLib|FmpDevicePkg/Library/CapsuleUpdatePolicyLibNull
> /CapsuleUpdatePolicyLibNull.inf
> + #
> + # Device specific library that processes a capsule and updates the FW
> storage device
> + #
> +
> FmpDeviceLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/FmpDeviceLibSa
> mple/FmpDeviceLib.inf
> + }
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin
> b/Platform/Intel/Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..da24c02b5d25ce888c630c6640
> 95902b4bb035e7
> GIT binary patch
> literal 3708
> zcmd^>Pl#JZ9LMK3`)XRdt$F?9>(+TQNqa~UwYzRL6+{xdH3}71P at h!~iwKK?Q
> Ysja
> zyX|(<qQVxzbj5>fq4Da)Ts;(X@!&zpF$WI;5lLww$LD8u(;7lcLET;q4D-G_leaV9
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> df(Yj
> zx{Q{={HK>X>1pl1uVg3l=gxJ~cL&<PZ)v%co*%q_JNnyNCp|Z$e>&eufBh)t{i$
> qa
> zymz6Ko;kF<fYxKYbk8T9^zHTcrQ*MT^i#$MdK~@MXPtDW{K}NLuFTl3<m0X=
> (-m=j
> zxoZ39zGO`wT at kSrDa94Z8J=B&PSA<u4bN^KJufTqyc{q*yDGXWlW|oJ8lGK47
> HtDf
> zGYxc2)@+UWHJLIsS#>R$wk^39x8#&*q1$rZw$W`_Fm2JUDS6xE|21XSG|_d
> wU+4RE
> znKN}^tDE}4qiNQxW^7I6<C;>Yro`3NRa-
> ~bRo2weO(nLeSfk1ro?RE+MR!%+ at QkN|
> zrz?1RVBOP<7MszNaYi3BJiC@!v at JCm(@cx`ZMA0GY9(%~l4+||7vWKaClMY+
> c+gjQ
> z+voj#HEa4xy9}OWcz*^@GMnznsNr~Yq{O;PtS`?xHS5iqf=FDD$QES96{Kg1=%
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> zMS0m3VWGl$E3CW1e9u<Gcp?p(Fh7yUJWDV&4O^=))-
> zRfRj$~oyy~jx8oGwAp=;=d
> zgfMm;)-J+a4^~2$ISxBz80x{6z}V-ob`s`B_psR-kDkb~#xiTnvqsGtCt0KC8g{rB
> zP3}XBd%`+dBTUHSrj18!G|jbT+HgnXu7tKL6RwMAeYprzYp?|qQi3JV)FNz&%jj
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> zX^A6!(MI~Di}ai+pbL7+7W9NGXwC#()Zf`6<3)4 at UD4NUh4BhH(b+iB$8Ey<5`
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> zdQz(``s;53YS<Qi?D>E-M4TfHuF7zggR5<Dbs4T!2V8}46~a{+uCj2&9^kCPc!hIM
> z_&yD;%5c?#s}Qb2xGE303gIe*t1?_onwngSH)>SiJXdw*(`=pbI(mb%kTWcEhB
> rA2
> zIYZCcqnz27oLR(~l{m8=XBH05tjw7?&V+lSxhFc{O#D8_N*nw2{oOo<qvGU<2c
> vs-
> z?0LODv*+M8doKOUJ#Jx-
> XV~NJ!5(viJsyY4fIW_$SqhgaTq?L!aQOgxCKq*<{&yGX
> zkp9CRfsW}z{=PoG_IH0bPe#Y_=;&{`NR8(s_2z*{We?Ke!e^Mkh0nBIcm&&M
> 8Xkpk
> zF$Whu%LFd=n5yL9Lf}H+A~)n2c_4 at 3;w!jVgA4M2EaX1N8(HTwj~tK_ag)35G
> wbjA
> z<7<!4yD>cc9uFV911CMxhZ~yh!&U!3uUB~VR348M9xdb1!oZ`MA&-
> 1bp24F$9_ib7
> z<ZJTq-
> I*QoNaN8iJj&vc3_L2~(UBpKUc#eGc(jH`zW(_d9mX{LDbsp*BzSZdk50Na
> zcXQ(|dCtUn&NkhnXLF`O4mZf-207bMj(qny&$*(TN|D!!-
> 0qRzC2~AVUbAKu`urxx
> z`Ax-mm+>y+Jd at Xo-
> 0u1OCdZW_uj7pLY=(Nlvx(3VIzscz9+{7(zIzV1OU&2I*UZ;H
> zWLQt8t)~8r)UF%R=vCNs4M)egTR9b1a<AD+Zl9~<;0B$b6LgZBH1p_r^nC7h$
> MgT}
> zgGV!?HL*tx4`Z4waK8)dxiws$?v`7l^(fC>yTo1d^~nE5K0H#7;CB7D2Hf7NN4M
> @8
> zHA%Q at KgMm@!(F>wZry{scKj6e==4xMQYkzSwVSzj1<zInp82egsOc-
> z^wE0cJ=zy<
> zWce8N=$~Zy5}xe6gC{=Avx6)jBg^0SxppDYAJgysBGC8IOFqyO^vV7}@Au<m
> e3Aa)
> og+TA{`cR;E`u>AJKSaMh8|ZiFi`_ua(_elr(C^Vdb2!j{0U29Y3;+NC
>
> literal 0
> HcmV?d00001
>
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModeP
> ei.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModeP
> ei.c
> new file mode 100644
> index 0000000000..bf6c7efba5
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModeP
> ei.c
> @@ -0,0 +1,42 @@
> +/** @file
> + This PEIM will parse the hoblist from fsp and report them into pei core.
> + This file contains the main entrypoint of the PEIM.
> +
> + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +
> +#include <PiPei.h>
> +#include <Ppi/MasterBootMode.h>
> +
> +static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> + &gEfiPeiMasterBootModePpiGuid,
> + NULL
> + },
> +};
> +
> +/**
> + This is the entrypoint of PEIM
> +
> + @param FileHandle Handle of the file being invoked.
> + @param PeiServices Describes the list of possible PEI Services.
> +
> + @retval EFI_SUCCESS if it completed successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +BootModePeiEntryPoint (
> + IN EFI_PEI_FILE_HANDLE FileHandle,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + (*PeiServices)->SetBootMode(PeiServices,
> BOOT_WITH_FULL_CONFIGURATION);
> +
> + (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModeP
> ei.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModeP
> ei.inf
> new file mode 100644
> index 0000000000..27200bca15
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModeP
> ei.inf
> @@ -0,0 +1,40 @@
> +## @file
> +# FSP PEI Module
> +#
> +# Parses the hoblist from fsp and report them into pei core. It will install
> +# the memory as required.
> +#
> +# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = BootModePeim
> + FILE_GUID = 2B1D0832-2184-4C8F-A90D-8E4AF9DE5BCD
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + ENTRY_POINT = BootModePeiEntryPoint
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32
> +#
> +
> +[Sources]
> + BootModePei.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> + PeimEntryPoint
> +
> +[Ppis]
> + gEfiPeiMasterBootModePpiGuid
> +
> +[Depex]
> + TRUE
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLi
> bVlv2/FspHobProcessLibVlv2.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLi
> bVlv2/FspHobProcessLibVlv2.c
> new file mode 100644
> index 0000000000..8a97e25bd4
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLi
> bVlv2/FspHobProcessLibVlv2.c
> @@ -0,0 +1,421 @@
> +/** @file
> + Null instance of Platform Sec Lib.
> +
> + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Library/PeiServicesLib.h>
> +#include <Library/PeiServicesTablePointerLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/FspPlatformInfoLib.h>
> +
> +#include <Guid/GuidHobFsp.h>
> +#include <Guid/MemoryTypeInformation.h>
> +#include <Ppi/Capsule.h>
> +
> +#include <PlatformFspLib.h>
> +#include <Guid/SmramMemoryReserve.h>
> +EFI_GUID gFspReservedMemoryResourceHobTsegGuid = {0xd038747c,
> 0xd00c, 0x4980, {0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55}};
> +
> +//
> +// Additional pages are used by DXE memory manager.
> +// It should be consistent between RetrieveRequiredMemorySize() and
> GetPeiMemSize()
> +//
> +#define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE)
> +
> +/**
> + Get the mem size in memory type infromation table.
> +
> + @param PeiServices PEI Services table.
> +
> + @return the mem size in memory type infromation table.
> +**/
> +UINT64
> +GetMemorySizeInMemoryTypeInformation (
> + IN EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_PEI_HOB_POINTERS Hob;
> + EFI_MEMORY_TYPE_INFORMATION *MemoryData;
> + UINT8 Index;
> + UINTN TempPageNum;
> +
> + MemoryData = NULL;
> + (*PeiServices)->GetHobList ((CONST EFI_PEI_SERVICES **)PeiServices,
> (VOID **) &Hob.Raw);
> + while (!END_OF_HOB_LIST (Hob)) {
> + if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION &&
> + CompareGuid (&Hob.Guid->Name, &gEfiMemoryTypeInformationGuid))
> {
> + MemoryData = (EFI_MEMORY_TYPE_INFORMATION *) (Hob.Raw +
> sizeof (EFI_HOB_GENERIC_HEADER) + sizeof (EFI_GUID));
> + break;
> + }
> +
> + Hob.Raw = GET_NEXT_HOB (Hob);
> + }
> +
> + if (MemoryData == NULL) {
> + return 0;
> + }
> +
> + TempPageNum = 0;
> + for (Index = 0; MemoryData[Index].Type != EfiMaxMemoryType; Index++)
> {
> + //
> + // Accumulate default memory size requirements
> + //
> + TempPageNum += MemoryData[Index].NumberOfPages;
> + }
> +
> + return TempPageNum * EFI_PAGE_SIZE;
> +}
> +
> +/**
> + Get the mem size need to be reserved in PEI phase.
> +
> + @param PeiServices PEI Services table.
> +
> + @return the mem size need to be reserved in PEI phase.
> +**/
> +UINT64
> +RetrieveRequiredMemorySize (
> + IN EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + UINT64 Size;
> +
> + Size = GetMemorySizeInMemoryTypeInformation (PeiServices);
> + return Size + PEI_ADDITIONAL_MEMORY_SIZE;
> +}
> +
> +/**
> + Get the mem size need to be consumed and reserved in PEI phase.
> +
> + @param PeiServices PEI Services table.
> + @param BootMode Current boot mode.
> +
> + @return the mem size need to be consumed and reserved in PEI phase.
> +**/
> +UINT64
> +GetPeiMemSize (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN UINT32 BootMode
> + )
> +{
> + UINT64 Size;
> + UINT64 MinSize;
> +
> + if (BootMode == BOOT_IN_RECOVERY_MODE) {
> + return PcdGet32 (PcdPeiRecoveryMinMemSize);
> + }
> +
> + Size = GetMemorySizeInMemoryTypeInformation (PeiServices);
> +
> + if (BootMode == BOOT_ON_FLASH_UPDATE) {
> + //
> + // Maybe more size when in CapsuleUpdate phase ?
> + //
> + MinSize = PcdGet32 (PcdPeiMinMemSize);
> + } else {
> + MinSize = PcdGet32 (PcdPeiMinMemSize);
> + }
> +
> + return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE;
> +}
> +
> +/**
> + BIOS process FspBobList.
> +
> + @param FspHobList Pointer to the HOB data structure produced by FSP.
> +
> + @return If platform process the FSP hob list successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FspHobProcessForMemoryResource (
> + IN VOID *FspHobList
> + )
> +{
> + EFI_PEI_HOB_POINTERS Hob;
> + UINT64 LowMemorySize;
> + UINT64 FspMemorySize;
> + EFI_PHYSICAL_ADDRESS FspMemoryBase;
> + UINT64 PeiMemSize;
> + EFI_PHYSICAL_ADDRESS PeiMemBase;
> + UINT64 S3PeiMemSize;
> + EFI_PHYSICAL_ADDRESS S3PeiMemBase;
> + BOOLEAN FoundFspMemHob;
> + EFI_STATUS Status;
> + EFI_BOOT_MODE BootMode;
> + PEI_CAPSULE_PPI *Capsule;
> + VOID *CapsuleBuffer;
> + UINTN CapsuleBufferLength;
> + UINT64 RequiredMemSize;
> + EFI_PEI_SERVICES **PeiServices;
> + UINT64 TsegSize;
> + EFI_PHYSICAL_ADDRESS TsegBase;
> + BOOLEAN FoundTsegHob;
> +
> + PeiServices = (EFI_PEI_SERVICES **)GetPeiServicesTablePointer ();
> +
> + PeiServicesGetBootMode (&BootMode);
> +
> + PeiMemBase = 0;
> + LowMemorySize = 0;
> + FspMemorySize = 0;
> + FspMemoryBase = 0;
> + FoundFspMemHob = FALSE;
> + TsegSize = 0;
> + TsegBase = 0;
> + FoundTsegHob = FALSE;
> +
> + //
> + // Parse the hob list from fsp
> + // Report all the resource hob except the memory between 1M and 4G
> + //
> + Hob.Raw = (UINT8 *)(UINTN)FspHobList;
> + DEBUG((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
> +
> + while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,
> Hob.Raw)) != NULL) {
> + DEBUG((DEBUG_INFO, "\nResourceType: 0x%x\n",
> Hob.ResourceDescriptor->ResourceType));
> + if ((Hob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_SYSTEM_MEMORY) ||
> + (Hob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_MEMORY_RESERVED)) {
> + DEBUG((DEBUG_INFO, "ResourceAttribute: 0x%x\n",
> Hob.ResourceDescriptor->ResourceAttribute));
> + DEBUG((DEBUG_INFO, "PhysicalStart: 0x%x\n",
> Hob.ResourceDescriptor->PhysicalStart));
> + DEBUG((DEBUG_INFO, "ResourceLength: 0x%x\n",
> Hob.ResourceDescriptor->ResourceLength));
> + DEBUG((DEBUG_INFO, "Owner: %g\n\n", &Hob.ResourceDescriptor-
> >Owner));
> + }
> +
> + if ((Hob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_SYSTEM_MEMORY) // Found the low memory length below
> 4G
> + && (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB)
> + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor-
> >ResourceLength <= BASE_4GB)) {
> + LowMemorySize += Hob.ResourceDescriptor->ResourceLength;
> + Hob.Raw = GET_NEXT_HOB (Hob);
> + continue;
> + }
> +
> + if ((Hob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_MEMORY_RESERVED) // Found the low memory length
> below 4G
> + && (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB)
> + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor-
> >ResourceLength <= BASE_4GB)
> + && (CompareGuid (&Hob.ResourceDescriptor->Owner,
> &gFspReservedMemoryResourceHobGuid))) {
> + FoundFspMemHob = TRUE;
> + FspMemoryBase = Hob.ResourceDescriptor->PhysicalStart;
> + FspMemorySize = Hob.ResourceDescriptor->ResourceLength;
> + DEBUG((DEBUG_INFO, "Find fsp mem hob, base 0x%x, len 0x%x\n",
> FspMemoryBase, FspMemorySize));
> + }
> +
> + if ((Hob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_MEMORY_RESERVED) // Found the low memory length
> below 4G
> + && (Hob.ResourceDescriptor->PhysicalStart >= 0x100000)
> + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor-
> >ResourceLength <= 0x100000000)
> + && (CompareGuid (&Hob.ResourceDescriptor->Owner,
> &gFspReservedMemoryResourceHobTsegGuid))) {
> + FoundTsegHob = TRUE;
> + TsegBase = Hob.ResourceDescriptor->PhysicalStart;
> +
> +
> + if ((Hob.ResourceDescriptor->ResourceLength == 0 ) ||
> (Hob.ResourceDescriptor->ResourceLength > 0x800000)){
> + Hob.ResourceDescriptor->ResourceLength = 0x800000;
> + }
> +
> +
> + TsegSize = Hob.ResourceDescriptor->ResourceLength;
> + DEBUG((EFI_D_ERROR, "Find Tseg mem hob, base 0x%lx, len 0x%lx\n",
> TsegBase, TsegSize));
> + }
> +
> + //
> + // Report the resource hob
> + //
> + BuildResourceDescriptorHob (
> + Hob.ResourceDescriptor->ResourceType,
> + Hob.ResourceDescriptor->ResourceAttribute,
> + Hob.ResourceDescriptor->PhysicalStart,
> + Hob.ResourceDescriptor->ResourceLength
> + );
> +
> + Hob.Raw = GET_NEXT_HOB (Hob);
> + }
> +
> + if (!FoundFspMemHob) {
> + DEBUG((DEBUG_INFO, "Didn't find the fsp used memory
> information.\n"));
> + //ASSERT(FALSE);
> + }
> +
> + DEBUG((DEBUG_INFO, "LowMemorySize: 0x%x.\n", LowMemorySize));
> + DEBUG((DEBUG_INFO, "FspMemoryBase: 0x%x.\n", FspMemoryBase));
> + DEBUG((DEBUG_INFO, "FspMemorySize: 0x%x.\n", FspMemorySize));
> +
> + if (BootMode == BOOT_ON_S3_RESUME) {
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + (
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + // EFI_RESOURCE_ATTRIBUTE_TESTED |
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
> + ),
> + BASE_1MB,
> + LowMemorySize
> + );
> +
> + Status = GetS3MemoryInfo (&S3PeiMemBase, &S3PeiMemSize);
> + ASSERT_EFI_ERROR (Status);
> + DEBUG((DEBUG_INFO, "S3 memory %Xh - %Xh bytes\n", S3PeiMemBase,
> S3PeiMemSize));
> +
> + //
> + // Make sure Stack and PeiMemory are not overlap - JYAO1
> + //
> +
> + Status = PeiServicesInstallPeiMemory (
> + S3PeiMemBase,
> + S3PeiMemSize
> + );
> + ASSERT_EFI_ERROR (Status);
> + } else {
> + PeiMemSize = GetPeiMemSize (PeiServices, BootMode);
> + DEBUG((DEBUG_INFO, "PEI memory size = %Xh bytes\n", PeiMemSize));
> +
> + //
> + // Capsule mode
> + //
> + Capsule = NULL;
> + CapsuleBuffer = NULL;
> + CapsuleBufferLength = 0;
> + if (BootMode == BOOT_ON_FLASH_UPDATE) {
> + Status = PeiServicesLocatePpi (
> + &gPeiCapsulePpiGuid,
> + 0,
> + NULL,
> + (VOID **) &Capsule
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + if (Status == EFI_SUCCESS) {
> + //
> + // Make sure Stack and CapsuleBuffer are not overlap - JYAO1
> + //
> + CapsuleBuffer = (VOID *)(UINTN)BASE_1MB;
> + CapsuleBufferLength = (UINTN)(LowMemorySize - PeiMemSize);
> + //
> + // Call the Capsule PPI Coalesce function to coalesce the capsule data.
> + //
> + Status = Capsule->Coalesce (PeiServices, &CapsuleBuffer,
> &CapsuleBufferLength);
> + }
> + }
> +
> + RequiredMemSize = RetrieveRequiredMemorySize (PeiServices);
> + DEBUG((DEBUG_INFO, "Required memory size = %Xh bytes\n",
> RequiredMemSize));
> +
> + //
> + // Report the main memory
> + //
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + (
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_TESTED |
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
> + ),
> + BASE_1MB,
> + LowMemorySize
> + );
> +
> + //
> + // Make sure Stack and CapsuleBuffer are not overlap - JYAO1
> + //
> +
> + //
> + // Install efi memory
> + //
> + PeiMemBase = BASE_1MB + LowMemorySize - PeiMemSize;
> + Status = PeiServicesInstallPeiMemory (
> + PeiMemBase,
> + PeiMemSize - RequiredMemSize
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + if (Capsule != NULL) {
> + Status = Capsule->CreateState (PeiServices, CapsuleBuffer,
> CapsuleBufferLength);
> + }
> + }
> +
> + //
> + // Report GUIDed HOB for reserving SMRAM regions
> + //
> + if (FoundTsegHob) {
> + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
> +
> + SmramHobDescriptorBlock = BuildGuidHob (
> + &gEfiSmmPeiSmramMemoryReserveGuid,
> + sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK)
> + );
> + ASSERT (SmramHobDescriptorBlock != NULL);
> +
> + SmramHobDescriptorBlock->NumberOfSmmReservedRegions = 1;
> +
> + SmramHobDescriptorBlock->Descriptor[0].PhysicalStart = TsegBase;
> + SmramHobDescriptorBlock->Descriptor[0].CpuStart = TsegBase;
> + SmramHobDescriptorBlock->Descriptor[0].PhysicalSize = TsegSize;
> + SmramHobDescriptorBlock->Descriptor[0].RegionState =
> EFI_SMRAM_CLOSED;
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + BIOS process FspBobList for other data (not Memory Resource Descriptor).
> +
> + @param[in] FspHobList Pointer to the HOB data structure produced by
> FSP.
> +
> + @return If platform process the FSP hob list successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FspHobProcessForOtherData (
> + IN VOID *FspHobList
> + )
> +{
> + EFI_PEI_SERVICES **PeiServices;
> +
> + PeiServices = (EFI_PEI_SERVICES **)GetPeiServicesTablePointer ();
> +
> + //
> + // Other hob for platform
> + //
> + PlatformHobCreateFromFsp ((CONST EFI_PEI_SERVICES **) PeiServices,
> FspHobList);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + BIOS process FspBobList.
> +
> + @param[in] FspHobList Pointer to the HOB data structure produced by
> FSP.
> +
> + @return If platform process the FSP hob list successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FspHobProcess (
> + IN VOID *FspHobList
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = FspHobProcessForMemoryResource (FspHobList);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + Status = FspHobProcessForOtherData (FspHobList);
> +
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLi
> bVlv2/FspHobProcessLibVlv2.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLi
> bVlv2/FspHobProcessLibVlv2.inf
> new file mode 100644
> index 0000000000..b789b27f4c
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLi
> bVlv2/FspHobProcessLibVlv2.inf
> @@ -0,0 +1,74 @@
> +## @file
> +#
> +# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +#########################################################
> #######################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +#########################################################
> #######################
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PeiFspHobProcessLibVlv2
> + FILE_GUID = C7B7070B-E5A8-4b86-9110-BDCA1095F496
> + MODULE_TYPE = SEC
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = FspHobProcessLib
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +#########################################################
> #######################
> +#
> +# Sources Section - list of files that are required for the build to succeed.
> +#
> +#########################################################
> #######################
> +
> +[Sources]
> + FspHobProcessLibVlv2.c
> +
> +
> +#########################################################
> #######################
> +#
> +# Package Dependency Section - list of Package files that are required for
> +# this module.
> +#
> +#########################################################
> #######################
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
> + IntelFspPkg/IntelFspPkg.dec
> + IntelFspWrapperPkg/IntelFspWrapperPkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + HobLib
> + DebugLib
> + FspPlatformInfoLib
> + PeiServicesLib
> + PeiServicesTablePointerLib
> + PlatformFspLib
> +
> +[Pcd]
> + gFspWrapperTokenSpaceGuid.PcdPeiMinMemSize
> + gFspWrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize
> +
> +[Guids]
> + gFspReservedMemoryResourceHobGuid
> + gEfiMemoryTypeInformationGuid
> + gEfiSmmPeiSmramMemoryReserveGuid
> +
> +[Ppis]
> + gPeiCapsulePpiGuid
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/FspPlatformSecLibVlv2.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/FspPlatformSecLibVlv2.c
> new file mode 100644
> index 0000000000..2b03cfaec9
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/FspPlatformSecLibVlv2.c
> @@ -0,0 +1,144 @@
> +/** @file
> +
> + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/SecPlatformInformation.h>
> +#include <Ppi/SecPerformance.h>
> +#include <Ppi/TemporaryRamSupport.h>
> +
> +#include <Library/LocalApicLib.h>
> +
> +/**
> + This interface conveys state information out of the Security (SEC) phase
> into PEI.
> +
> + @param PeiServices Pointer to the PEI Services Table.
> + @param StructureSize Pointer to the variable describing size of the
> input buffer.
> + @param PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> + @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecPlatformInformation (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT UINT64 *StructureSize,
> + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord
> + );
> +
> +/**
> + This interface conveys performance information out of the Security (SEC)
> phase into PEI.
> +
> + This service is published by the SEC phase. The SEC phase handoff has an
> optional
> + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the
> + PEI Foundation. As such, if the platform supports collecting performance
> data in SEC,
> + this information is encapsulated into the data structure abstracted by this
> service.
> + This information is collected for the boot-strap processor (BSP) on IA-32.
> +
> + @param[in] PeiServices The pointer to the PEI Services Table.
> + @param[in] This The pointer to this instance of the
> PEI_SEC_PERFORMANCE_PPI.
> + @param[out] Performance The pointer to performance data collected in
> SEC phase.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecGetPerformance (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN PEI_SEC_PERFORMANCE_PPI *This,
> + OUT FIRMWARE_SEC_PERFORMANCE *Performance
> + );
> +
> +/**
> + This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates
> temporary RAM into
> + permanent memory.
> +
> + @param PeiServices Pointer to the PEI Services Table.
> + @param TemporaryMemoryBase Source Address in temporary memory
> from which the SEC or PEIM will copy the
> + Temporary RAM contents.
> + @param PermanentMemoryBase Destination Address in permanent
> memory into which the SEC or PEIM will copy the
> + Temporary RAM contents.
> + @param CopySize Amount of memory to migrate from temporary
> to permanent memory.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> + @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize >
> TemporaryMemoryBase when
> + TemporaryMemoryBase > PermanentMemoryBase.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecTemporaryRamSupport (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
> + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
> + IN UINTN CopySize
> + );
> +
> +EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInformationPpi = {
> + SecPlatformInformation
> +};
> +
> +PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
> + SecGetPerformance
> +};
> +
> +EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi
> = {
> + SecTemporaryRamSupport
> +};
> +
> +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gEfiSecPlatformInformationPpiGuid,
> + &mSecPlatformInformationPpi
> + },
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gPeiSecPerformancePpiGuid,
> + &mSecPerformancePpi
> + },
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> + &gEfiTemporaryRamSupportPpiGuid,
> + &gSecTemporaryRamSupportPpi
> + },
> +};
> +
> +/**
> + A developer supplied function to perform platform specific operations.
> +
> + It's a developer supplied function to perform any operations appropriate
> to a
> + given platform. It's invoked just before passing control to PEI core by SEC
> + core. Platform developer may modify the SecCoreData passed to PEI Core.
> + It returns a platform specific PPI list that platform wishes to pass to PEI
> core.
> + The Generic SEC core module will merge this list to join the final list passed
> to
> + PEI core.
> +
> + @param SecCoreData The same parameter as passing to PEI core. It
> + could be overridden by this function.
> +
> + @return The platform specific PPI list to be passed to PEI core or
> + NULL if there is no need of such platform specific PPI list.
> +
> +**/
> +EFI_PEI_PPI_DESCRIPTOR *
> +EFIAPI
> +SecPlatformMain (
> + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
> + )
> +{
> + EFI_PEI_PPI_DESCRIPTOR *PpiList;
> +
> + InitializeApicTimer (0, (UINT32) -1, TRUE, 5);
> +
> + PpiList = &mPeiSecPlatformPpi[0];
> +
> + return PpiList;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/FspPlatformSecLibVlv2.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/FspPlatformSecLibVlv2.inf
> new file mode 100644
> index 0000000000..578066d98f
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/FspPlatformSecLibVlv2.inf
> @@ -0,0 +1,82 @@
> +## @file
> +#
> +# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +#########################################################
> #######################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +#########################################################
> #######################
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SecPeiFspPlatformSecLibVlv2
> + FILE_GUID = 6653876C-F6A1-45BB-A027-20455093BC6D
> + MODULE_TYPE = SEC
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = FspPlatformSecLib
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +#########################################################
> #######################
> +#
> +# Sources Section - list of files that are required for the build to succeed.
> +#
> +#########################################################
> #######################
> +
> +[Sources]
> + FspPlatformSecLibVlv2.c
> + SecRamInitData.c
> + SaveSecContext.c
> + SecPlatformInformation.c
> + SecGetPerformance.c
> + SecTempRamSupport.c
> + PlatformInit.c
> + UartInit.c
> +
> +[Sources.IA32]
> + Ia32/SecEntry.asm
> + Ia32/PeiCoreEntry.asm
> + Ia32/AsmSaveSecContext.asm
> + Ia32/Stack.asm
> +
> +#########################################################
> #######################
> +#
> +# Package Dependency Section - list of Package files that are required for
> +# this module.
> +#
> +#########################################################
> #######################
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + UefiCpuPkg/UefiCpuPkg.dec
> + IntelFspWrapperPkg/IntelFspWrapperPkg.dec
> +
> +[LibraryClasses]
> + LocalApicLib
> + SerialPortLib
> +
> +[Ppis]
> + gEfiSecPlatformInformationPpiGuid
> + gPeiSecPerformancePpiGuid
> + gEfiTemporaryRamSupportPpiGuid
> +
> +[Pcd]
> + gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize
> + gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase
> + gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize
> +
> +[FixedPcd]
> + gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress
> + gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
> + gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset
> + gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress
> + gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/AsmSaveSecContext.asm
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/AsmSaveSecContext.asm
> new file mode 100644
> index 0000000000..2546a09a1a
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/AsmSaveSecContext.asm
> @@ -0,0 +1,45 @@
> +;------------------------------------------------------------------------------
> +;
> +; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;
> +; Module Name:
> +;
> +; SecEntry.asm
> +;
> +; Abstract:
> +;
> +; This is the code that goes from real-mode to protected mode.
> +; It consumes the reset vector, calls two basic APIs from FSP binary.
> +;
> +;------------------------------------------------------------------------------
> +
> +.686p
> +.xmm
> +.model flat,c
> +.code
> +
> +;----------------------------------------------------------------------------
> +; MMX Usage:
> +; MM0 = BIST State
> +; MM5 = Save time-stamp counter value high32bit
> +; MM6 = Save time-stamp counter value low32bit.
> +;
> +; It should be same as SecEntry.asm and PeiCoreEntry.asm.
> +;----------------------------------------------------------------------------
> +
> +AsmSaveBistValue PROC PUBLIC
> + mov eax, [esp+4]
> + movd mm0, eax
> + ret
> +AsmSaveBistValue ENDP
> +
> +AsmSaveTickerValue PROC PUBLIC
> + mov eax, [esp+4]
> + movd mm6, eax
> + mov eax, [esp+8]
> + movd mm5, eax
> + ret
> +AsmSaveTickerValue ENDP
> +
> +END
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/Fsp.inc
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/Fsp.inc
> new file mode 100644
> index 0000000000..23295587b4
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/Fsp.inc
> @@ -0,0 +1,45 @@
> +;------------------------------------------------------------------------------
> +;
> +; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;
> +; Module Name:
> +;
> +; Fsp.inc
> +;
> +; Abstract:
> +;
> +; Fsp related definitions
> +;
> +;------------------------------------------------------------------------------
> +
> +
> +;
> +; Fv Header
> +;
> +FVH_SIGINATURE_OFFSET EQU 028h
> +FVH_SIGINATURE_VALID_VALUE EQU 04856465Fh ; valid signature:_FVH
> +FVH_HEADER_LENGTH_OFFSET EQU 030h
> +FVH_EXTHEADER_OFFSET_OFFSET EQU 034h
> +FVH_EXTHEADER_SIZE_OFFSET EQU 010h
> +
> +;
> +; Ffs Header
> +;
> +FSP_HEADER_GUID_DWORD1 EQU 0912740BEh
> +FSP_HEADER_GUID_DWORD2 EQU 047342284h
> +FSP_HEADER_GUID_DWORD3 EQU 0B08471B9h
> +FSP_HEADER_GUID_DWORD4 EQU 00C3F3527h
> +FFS_HEADER_SIZE_VALUE EQU 018h
> +
> +;
> +; Section Header
> +;
> +SECTION_HEADER_TYPE_OFFSET EQU 03h
> +RAW_SECTION_HEADER_SIZE_VALUE EQU 04h
> +
> +;
> +; Fsp Header
> +;
> +FSP_HEADER_IMAGEBASE_OFFSET EQU 01Ch
> +FSP_HEADER_TEMPRAMINIT_OFFSET EQU 030h
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/PeiCoreEntry.asm
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/PeiCoreEntry.asm
> new file mode 100644
> index 0000000000..3d34c62ea4
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/PeiCoreEntry.asm
> @@ -0,0 +1,135 @@
> +;------------------------------------------------------------------------------
> +;
> +; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;
> +; Module Name:
> +;
> +; SecEntry.asm
> +;
> +; Abstract:
> +;
> +; This is the code that goes from real-mode to protected mode.
> +; It consumes the reset vector, calls two basic APIs from FSP binary.
> +;
> +;------------------------------------------------------------------------------
> +
> +.686p
> +.xmm
> +.model flat, c
> +.code
> +
> +EXTRN SecStartup:NEAR
> +EXTRN PlatformInit:NEAR
> +
> +CallPeiCoreEntryPoint PROC PUBLIC
> + ;
> + ; Obtain the hob list pointer
> + ;
> + mov eax, [esp+4]
> + ;
> + ; Obtain the stack information
> + ; ECX: start of range
> + ; EDX: end of range
> + ;
> + mov ecx, [esp+8]
> + mov edx, [esp+0Ch]
> +
> + ;
> + ; Platform init
> + ;
> + pushad
> + push edx
> + push ecx
> + push eax
> + call PlatformInit
> + pop eax
> + pop eax
> + pop eax
> + popad
> +
> + ;
> + ; Set stack top pointer
> + ;
> + mov esp, edx
> +
> + ;
> + ; Push the hob list pointer
> + ;
> + push eax
> +
> + ;
> + ; Save the value
> + ; ECX: start of range
> + ; EDX: end of range
> + ;
> + mov ebp, esp
> + push ecx
> + push edx
> +
> + ;
> + ; Push processor count to stack first, then BIST status (AP then BSP)
> + ;
> + mov eax, 1
> + cpuid
> + shr ebx, 16
> + and ebx, 0000000FFh
> + cmp bl, 1
> + jae PushProcessorCount
> +
> + ;
> + ; Some processors report 0 logical processors. Effectively 0 = 1.
> + ; So we fix up the processor count
> + ;
> + inc ebx
> +
> +PushProcessorCount:
> + push ebx
> +
> + ;
> + ; We need to implement a long-term solution for BIST capture. For now,
> we just copy BSP BIST
> + ; for all processor threads
> + ;
> + xor ecx, ecx
> + mov cl, bl
> +PushBist:
> + movd eax, mm0
> + push eax
> + loop PushBist
> +
> + ; Save Time-Stamp Counter
> + movd eax, mm5
> + push eax
> +
> + movd eax, mm6
> + push eax
> +
> + ;
> + ; Pass entry point of the PEI core
> + ;
> + mov edi, 0FFFFFFE0h
> + push DWORD PTR ds:[edi]
> +
> + ;
> + ; Pass BFV into the PEI Core
> + ;
> + mov edi, 0FFFFFFFCh
> + push DWORD PTR ds:[edi]
> +
> + ;
> + ; Pass stack size into the PEI Core
> + ;
> + mov ecx, [ebp - 4]
> + mov edx, [ebp - 8]
> + push ecx ; RamBase
> +
> + sub edx, ecx
> + push edx ; RamSize
> +
> + ;
> + ; Pass Control into the PEI Core
> + ;
> + call SecStartup
> +CallPeiCoreEntryPoint ENDP
> +
> +END
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/SecEntry.asm
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/SecEntry.asm
> new file mode 100644
> index 0000000000..b7026c433f
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/SecEntry.asm
> @@ -0,0 +1,338 @@
> +;------------------------------------------------------------------------------
> +;
> +; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;
> +; Module Name:
> +;
> +; SecEntry.asm
> +;
> +; Abstract:
> +;
> +; This is the code that goes from real-mode to protected mode.
> +; It consumes the reset vector, calls two basic APIs from FSP binary.
> +;
> +;------------------------------------------------------------------------------
> + INCLUDE Fsp.inc
> +
> +.686p
> +.xmm
> +.model small, c
> +
> +EXTRN CallPeiCoreEntryPoint:NEAR
> +EXTRN TempRamInitParams:FAR
> +
> +; Pcds
> +EXTRN PcdGet32 (PcdFlashFvFspBase):DWORD
> +EXTRN PcdGet32 (PcdFlashFvFspSize):DWORD
> +
> +_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'
> + ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE
> +
> +;----------------------------------------------------------------------------
> +;
> +; Procedure: _ModuleEntryPoint
> +;
> +; Input: None
> +;
> +; Output: None
> +;
> +; Destroys: Assume all registers
> +;
> +; Description:
> +;
> +; Transition to non-paged flat-model protected mode from a
> +; hard-coded GDT that provides exactly two descriptors.
> +; This is a bare bones transition to protected mode only
> +; used for a while in PEI and possibly DXE.
> +;
> +; After enabling protected mode, a far jump is executed to
> +; transfer to PEI using the newly loaded GDT.
> +;
> +; Return: None
> +;
> +; MMX Usage:
> +; MM0 = BIST State
> +; MM5 = Save time-stamp counter value high32bit
> +; MM6 = Save time-stamp counter value low32bit.
> +;
> +;----------------------------------------------------------------------------
> +
> +align 4
> +_ModuleEntryPoint PROC NEAR C PUBLIC
> + fninit ; clear any pending Floating point exceptions
> + ;
> + ; Store the BIST value in mm0
> + ;
> + movd mm0, eax
> +
> + ;
> + ; Save time-stamp counter value
> + ; rdtsc load 64bit time-stamp counter to EDX:EAX
> + ;
> + rdtsc
> + movd mm5, edx
> + movd mm6, eax
> +
> + ;
> + ; Load the GDT table in GdtDesc
> + ;
> + mov esi, OFFSET GdtDesc
> + DB 66h
> + lgdt fword ptr cs:[si]
> +
> + ;
> + ; Transition to 16 bit protected mode
> + ;
> + mov eax, cr0 ; Get control register 0
> + or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
> + mov cr0, eax ; Activate protected mode
> +
> + mov eax, cr4 ; Get control register 4
> + or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit
> #10)
> + mov cr4, eax
> +
> + ;
> + ; Now we're in 16 bit protected mode
> + ; Set up the selectors for 32 bit protected mode entry
> + ;
> + mov ax, SYS_DATA_SEL
> + mov ds, ax
> + mov es, ax
> + mov fs, ax
> + mov gs, ax
> + mov ss, ax
> +
> + ;
> + ; Transition to Flat 32 bit protected mode
> + ; The jump to a far pointer causes the transition to 32 bit mode
> + ;
> + mov esi, offset ProtectedModeEntryLinearAddress
> + jmp fword ptr cs:[si]
> +
> +_ModuleEntryPoint ENDP
> +_TEXT_REALMODE ENDS
> +
> +_TEXT_PROTECTED_MODE SEGMENT PARA PUBLIC USE32 'CODE'
> + ASSUME CS:_TEXT_PROTECTED_MODE,
> DS:_TEXT_PROTECTED_MODE
> +
> +;----------------------------------------------------------------------------
> +;
> +; Procedure: ProtectedModeEntryPoint
> +;
> +; Input: None
> +;
> +; Output: None
> +;
> +; Destroys: Assume all registers
> +;
> +; Description:
> +;
> +; This function handles:
> +; Call two basic APIs from FSP binary
> +; Initializes stack with some early data (BIST, PEI entry, etc)
> +;
> +; Return: None
> +;
> +;----------------------------------------------------------------------------
> +
> +align 4
> +ProtectedModeEntryPoint PROC NEAR PUBLIC
> +
> + ; Find the fsp info header
> + mov edi, PcdGet32 (PcdFlashFvFspBase)
> + mov ecx, PcdGet32 (PcdFlashFvFspSize)
> +
> + mov eax, dword ptr [edi + FVH_SIGINATURE_OFFSET]
> + cmp eax, FVH_SIGINATURE_VALID_VALUE
> + jnz FspHeaderNotFound
> +
> + xor eax, eax
> + mov ax, word ptr [edi + FVH_EXTHEADER_OFFSET_OFFSET]
> + cmp ax, 0
> + jnz FspFvExtHeaderExist
> +
> + xor eax, eax
> + mov ax, word ptr [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv
> Header
> + add edi, eax
> + jmp FspCheckFfsHeader
> +
> +FspFvExtHeaderExist:
> + add edi, eax
> + mov eax, dword ptr [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv
> Header
> + add edi, eax
> +
> + ; Round up to 8 byte alignment
> + mov eax, edi
> + and al, 07h
> + jz FspCheckFfsHeader
> +
> + and edi, 0FFFFFFF8h
> + add edi, 08h
> +
> +FspCheckFfsHeader:
> + ; Check the ffs guid
> + mov eax, dword ptr [edi]
> + cmp eax, FSP_HEADER_GUID_DWORD1
> + jnz FspHeaderNotFound
> +
> + mov eax, dword ptr [edi + 4]
> + cmp eax, FSP_HEADER_GUID_DWORD2
> + jnz FspHeaderNotFound
> +
> + mov eax, dword ptr [edi + 8]
> + cmp eax, FSP_HEADER_GUID_DWORD3
> + jnz FspHeaderNotFound
> +
> + mov eax, dword ptr [edi + 0Ch]
> + cmp eax, FSP_HEADER_GUID_DWORD4
> + jnz FspHeaderNotFound
> +
> + add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
> +
> + ; Check the section type as raw section
> + mov al, byte ptr [edi + SECTION_HEADER_TYPE_OFFSET]
> + cmp al, 019h
> + jnz FspHeaderNotFound
> +
> + add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
> + jmp FspHeaderFound
> +
> +FspHeaderNotFound:
> + jmp $
> +
> +FspHeaderFound:
> + ; Get the fsp TempRamInit Api address
> + mov eax, dword ptr [edi + FSP_HEADER_IMAGEBASE_OFFSET]
> + add eax, dword ptr [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
> +
> + ; Setup the hardcode stack
> + mov esp, OFFSET TempRamInitStack
> +
> + ; Call the fsp TempRamInit Api
> + jmp eax
> +
> +TempRamInitDone:
> + cmp eax, 0
> + jnz FspApiFailed
> +
> + ; ECX: start of range
> + ; EDX: end of range
> + mov esp, edx
> + push edx
> + push ecx
> + push eax ; zero - no hob list yet
> + call CallPeiCoreEntryPoint
> +
> +FspApiFailed:
> + jmp $
> +
> +align 10h
> +TempRamInitStack:
> + DD OFFSET TempRamInitDone
> + DD OFFSET TempRamInitParams
> +
> +ProtectedModeEntryPoint ENDP
> +
> +;
> +; ROM-based Global-Descriptor Table for the Tiano PEI Phase
> +;
> +align 16
> +PUBLIC BootGdtTable
> +
> +;
> +; GDT[0]: 0x00: Null entry, never used.
> +;
> +NULL_SEL EQU $ - GDT_BASE ; Selector [0]
> +GDT_BASE:
> +BootGdtTable DD 0
> + DD 0
> +;
> +; Linear data segment descriptor
> +;
> +LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 092h ; present, ring 0, data, expand-up, writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +;
> +; Linear code segment descriptor
> +;
> +LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 09Bh ; present, ring 0, data, expand-up, not-writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +;
> +; System data segment descriptor
> +;
> +SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 093h ; present, ring 0, data, expand-up, not-writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +
> +;
> +; System code segment descriptor
> +;
> +SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 09Ah ; present, ring 0, data, expand-up, writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +;
> +; Spare segment descriptor
> +;
> +SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0Eh ; Changed from F000 to E000.
> + DB 09Bh ; present, ring 0, code, expand-up, writable
> + DB 00h ; byte-granular, 16-bit
> + DB 0
> +;
> +; Spare segment descriptor
> +;
> +SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
> + DW 0FFFFh ; limit 0xFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 093h ; present, ring 0, data, expand-up, not-writable
> + DB 00h ; byte-granular, 16-bit
> + DB 0
> +
> +;
> +; Spare segment descriptor
> +;
> +SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
> + DW 0 ; limit 0
> + DW 0 ; base 0
> + DB 0
> + DB 0 ; present, ring 0, data, expand-up, writable
> + DB 0 ; page-granular, 32-bit
> + DB 0
> +GDT_SIZE EQU $ - BootGdtTable ; Size, in bytes
> +
> +;
> +; GDT Descriptor
> +;
> +GdtDesc: ; GDT descriptor
> + DW GDT_SIZE - 1 ; GDT limit
> + DD OFFSET BootGdtTable ; GDT base address
> +
> +
> +ProtectedModeEntryLinearAddress LABEL FWORD
> +ProtectedModeEntryLinearOffset LABEL DWORD
> + DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code
> + DW LINEAR_CODE_SEL
> +
> +_TEXT_PROTECTED_MODE ENDS
> +END
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/Stack.S
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/Stack.S
> new file mode 100644
> index 0000000000..9bd29ce0f4
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/Stack.S
> @@ -0,0 +1,71 @@
> +#------------------------------------------------------------------------------
> +#
> +# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +# Abstract:
> +#
> +# Switch the stack from temporary memory to permenent memory.
> +#
> +#------------------------------------------------------------------------------
> +
> +
> +#------------------------------------------------------------------------------
> +# VOID
> +# EFIAPI
> +# SecSwitchStack (
> +# UINT32 TemporaryMemoryBase,
> +# UINT32 PermenentMemoryBase
> +# )#
> +#------------------------------------------------------------------------------
> +ASM_GLOBAL ASM_PFX (SecSwitchStack)
> +ASM_PFX(SecSwitchStack):
> + #
> + # Save standard registers so they can be used to change stack
> + #
> + pushl %eax
> + pushl %ebx
> + pushl %ecx
> + pushl %edx
> +
> + #
> + # !!CAUTION!! this function address's is pushed into stack after
> + # migration of whole temporary memory, so need save it to permenent
> + # memory at first!
> + #
> + movl 20(%esp), %ebx # Save the first parameter
> + movl 24(%esp), %ecx # Save the second parameter
> +
> + #
> + # Save this function's return address into permenent memory at first.
> + # Then, Fixup the esp point to permenent memory
> + #
> + movl %esp, %eax
> + subl %ebx, %eax
> + addl %ecx, %eax
> + movl 0(%esp), %edx # copy pushed register's value to permenent
> memory
> + movl %edx, 0(%eax)
> + movl 4(%esp), %edx
> + movl %edx, 4(%eax)
> + movl 8(%esp), %edx
> + movl %edx, 8(%eax)
> + movl 12(%esp), %edx
> + movl %edx, 12(%eax)
> + movl 16(%esp), %edx # Update this function's return address into
> permenent memory
> + movl %edx, 16(%eax)
> + movl %eax, %esp # From now, esp is pointed to permenent
> memory
> +
> + #
> + # Fixup the ebp point to permenent memory
> + #
> + movl %ebp, %eax
> + subl %ebx, %eax
> + addl %ecx, %eax
> + movl %eax, %ebp # From now, ebp is pointed to permenent
> memory
> +
> + popl %edx
> + popl %ecx
> + popl %ebx
> + popl %eax
> + ret
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/Stack.asm
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/Stack.asm
> new file mode 100644
> index 0000000000..95e56cec9b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/Ia32/Stack.asm
> @@ -0,0 +1,76 @@
> +;------------------------------------------------------------------------------
> +;
> +; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;
> +; Abstract:
> +;
> +; Switch the stack from temporary memory to permenent memory.
> +;
> +;------------------------------------------------------------------------------
> +
> + .586p
> + .model flat,C
> + .code
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EFIAPI
> +; SecSwitchStack (
> +; UINT32 TemporaryMemoryBase,
> +; UINT32 PermenentMemoryBase
> +; );
> +;------------------------------------------------------------------------------
> +SecSwitchStack PROC
> + ;
> + ; Save three register: eax, ebx, ecx
> + ;
> + push eax
> + push ebx
> + push ecx
> + push edx
> +
> + ;
> + ; !!CAUTION!! this function address's is pushed into stack after
> + ; migration of whole temporary memory, so need save it to permenent
> + ; memory at first!
> + ;
> +
> + mov ebx, [esp + 20] ; Save the first parameter
> + mov ecx, [esp + 24] ; Save the second parameter
> +
> + ;
> + ; Save this function's return address into permenent memory at first.
> + ; Then, Fixup the esp point to permenent memory
> + ;
> + mov eax, esp
> + sub eax, ebx
> + add eax, ecx
> + mov edx, dword ptr [esp] ; copy pushed register's value to
> permenent memory
> + mov dword ptr [eax], edx
> + mov edx, dword ptr [esp + 4]
> + mov dword ptr [eax + 4], edx
> + mov edx, dword ptr [esp + 8]
> + mov dword ptr [eax + 8], edx
> + mov edx, dword ptr [esp + 12]
> + mov dword ptr [eax + 12], edx
> + mov edx, dword ptr [esp + 16] ; Update this function's return address
> into permenent memory
> + mov dword ptr [eax + 16], edx
> + mov esp, eax ; From now, esp is pointed to permenent
> memory
> +
> + ;
> + ; Fixup the ebp point to permenent memory
> + ;
> + mov eax, ebp
> + sub eax, ebx
> + add eax, ecx
> + mov ebp, eax ; From now, ebp is pointed to permenent memory
> +
> + pop edx
> + pop ecx
> + pop ebx
> + pop eax
> + ret
> +SecSwitchStack ENDP
> +
> + END
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/PlatformInit.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/PlatformInit.c
> new file mode 100644
> index 0000000000..d4e1c2a425
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/PlatformInit.c
> @@ -0,0 +1,36 @@
> +/** @file
> + This PEIM will parse the hoblist from fsp and report them into pei core.
> + This file contains the main entrypoint of the PEIM.
> +
> + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +
> +#include <PiPei.h>
> +#include <Library/DebugLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +VOID EnableInternalUart ();
> +
> +VOID
> +EFIAPI
> +PlatformInit (
> + IN VOID *FspHobList,
> + IN VOID *StartOfRange,
> + IN VOID *EndOfRange
> + )
> +{
> + //
> + // Platform initialization
> + // Enable Serial port here
> + //
> + EnableInternalUart ();
> + SerialPortInitialize ();
> +
> + DEBUG ((DEBUG_INFO, "PlatformInit\n"));
> + DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
> + DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));
> + DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SaveSecContext.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SaveSecContext.c
> new file mode 100644
> index 0000000000..382e617b27
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SaveSecContext.c
> @@ -0,0 +1,108 @@
> +/** @file
> + This PEIM will parse the hoblist from fsp and report them into pei core.
> + This file contains the main entrypoint of the PEIM.
> +
> + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +
> +#include <PiPei.h>
> +#include <Library/DebugLib.h>
> +
> +#include <Ppi/TopOfTemporaryRam.h>
> +#include <Ppi/SecPlatformInformation.h>
> +
> +/**
> + Save BIST value before call FspInit.
> +
> + @param Bist BIST value.
> +**/
> +VOID
> +AsmSaveBistValue (
> + IN UINT32 Bist
> + );
> +
> +/**
> + Save Ticker value before call FspInit.
> +
> + @param Ticker Ticker value.
> +**/
> +VOID
> +AsmSaveTickerValue (
> + IN UINT64 Ticker
> + );
> +
> +/**
> + Save SEC context before call FspInit.
> +
> + @param PeiServices Pointer to PEI Services Table.
> +**/
> +VOID
> +EFIAPI
> +SaveSecContext (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + UINT32 *Bist;
> + UINT64 *Ticker;
> + UINT32 Size;
> + UINT32 Count;
> + UINT32 TopOfTemporaryRam;
> + VOID *TopOfTemporaryRamPpi;
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_INFO, "SaveSecContext - 0x%x\n", PeiServices));
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gTopOfTemporaryRamPpiGuid,
> + 0,
> + NULL,
> + (VOID **) &TopOfTemporaryRamPpi
> + );
> + if (EFI_ERROR (Status)) {
> + return ;
> + }
> +
> + DEBUG ((DEBUG_INFO, "TopOfTemporaryRamPpi - 0x%x\n",
> TopOfTemporaryRamPpi));
> +
> + //
> + // The entries of BIST information, together with the number of them,
> + // reside in the bottom of stack, left untouched by normal stack operation.
> + // This routine copies the BIST information to the buffer pointed by
> + // PlatformInformationRecord for output.
> + //
> + // |--------------| <- TopOfTemporaryRam
> + // |Number of BSPs|
> + // |--------------|
> + // | BIST |
> + // |--------------|
> + // | .... |
> + // |--------------|
> + // | TSC[63:32] |
> + // |--------------|
> + // | TSC[31:00] |
> + // |--------------|
> + //
> +
> + TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi -
> sizeof(UINT32);
> + TopOfTemporaryRam -= sizeof(UINT32) * 2;
> + DEBUG ((DEBUG_INFO, "TopOfTemporaryRam - 0x%x\n",
> TopOfTemporaryRam));
> + Count = *(UINT32 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32));
> + DEBUG ((DEBUG_INFO, "Count - 0x%x\n", Count));
> + Size = Count * sizeof (IA32_HANDOFF_STATUS);
> + DEBUG ((DEBUG_INFO, "Size - 0x%x\n", Size));
> +
> + Bist = (UINT32 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32) - Size);
> + DEBUG ((DEBUG_INFO, "Bist - 0x%x\n", *Bist));
> + Ticker = (UINT64 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32) - Size -
> sizeof(UINT64));
> + DEBUG ((DEBUG_INFO, "Ticker - 0x%lx\n", *Ticker));
> +
> + //
> + // Just need record BSP
> + //
> + AsmSaveBistValue (*Bist);
> + AsmSaveTickerValue (*Ticker);
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecGetPerformance.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecGetPerformance.c
> new file mode 100644
> index 0000000000..c5c22a29c2
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecGetPerformance.c
> @@ -0,0 +1,83 @@
> +/** @file
> +
> + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/SecPerformance.h>
> +#include <Ppi/TopOfTemporaryRam.h>
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + This interface conveys performance information out of the Security (SEC)
> phase into PEI.
> +
> + This service is published by the SEC phase. The SEC phase handoff has an
> optional
> + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the
> + PEI Foundation. As such, if the platform supports collecting performance
> data in SEC,
> + this information is encapsulated into the data structure abstracted by this
> service.
> + This information is collected for the boot-strap processor (BSP) on IA-32.
> +
> + @param[in] PeiServices The pointer to the PEI Services Table.
> + @param[in] This The pointer to this instance of the
> PEI_SEC_PERFORMANCE_PPI.
> + @param[out] Performance The pointer to performance data collected in
> SEC phase.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecGetPerformance (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN PEI_SEC_PERFORMANCE_PPI *This,
> + OUT FIRMWARE_SEC_PERFORMANCE *Performance
> + )
> +{
> + UINT32 Size;
> + UINT32 Count;
> + UINT32 TopOfTemporaryRam;
> + UINT64 Ticker;
> + VOID *TopOfTemporaryRamPpi;
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gTopOfTemporaryRamPpiGuid,
> + 0,
> + NULL,
> + (VOID **) &TopOfTemporaryRamPpi
> + );
> + if (EFI_ERROR (Status)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // |--------------| <- TopOfTemporaryRam
> + // |Number of BSPs|
> + // |--------------|
> + // | BIST |
> + // |--------------|
> + // | .... |
> + // |--------------|
> + // | TSC[63:32] |
> + // |--------------|
> + // | TSC[31:00] |
> + // |--------------|
> + //
> + TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi -
> sizeof(UINT32);
> + TopOfTemporaryRam -= sizeof(UINT32) * 2;
> + Count = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof
> (UINT32));
> + Size = Count * sizeof (UINT64);
> +
> + Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) -
> Size - sizeof (UINT32) * 2);
> + Performance->ResetEnd = GetTimeInNanoSecond (Ticker);
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecPlatformInformation.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecPlatformInformation.c
> new file mode 100644
> index 0000000000..a1ba35d47d
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecPlatformInformation.c
> @@ -0,0 +1,77 @@
> +/** @file
> +
> + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/SecPlatformInformation.h>
> +#include <Ppi/TopOfTemporaryRam.h>
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + This interface conveys state information out of the Security (SEC) phase
> into PEI.
> +
> + @param PeiServices Pointer to the PEI Services Table.
> + @param StructureSize Pointer to the variable describing size of the
> input buffer.
> + @param PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> + @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecPlatformInformation (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT UINT64 *StructureSize,
> + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord
> + )
> +{
> + UINT32 *Bist;
> + UINT32 Size;
> + UINT32 Count;
> + UINT32 TopOfTemporaryRam;
> + VOID *TopOfTemporaryRamPpi;
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gTopOfTemporaryRamPpiGuid,
> + 0,
> + NULL,
> + (VOID **) &TopOfTemporaryRamPpi
> + );
> + if (EFI_ERROR (Status)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // The entries of BIST information, together with the number of them,
> + // reside in the bottom of stack, left untouched by normal stack operation.
> + // This routine copies the BIST information to the buffer pointed by
> + // PlatformInformationRecord for output.
> + //
> + TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof
> (UINT32);
> + TopOfTemporaryRam -= sizeof(UINT32) * 2;
> + Count = *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof
> (UINT32)));
> + Size = Count * sizeof (IA32_HANDOFF_STATUS);
> +
> + if ((*StructureSize) < (UINT64) Size) {
> + *StructureSize = Size;
> + return EFI_BUFFER_TOO_SMALL;
> + }
> +
> + *StructureSize = Size;
> + Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size);
> +
> + CopyMem (PlatformInformationRecord, Bist, Size);
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecRamInitData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecRamInitData.c
> new file mode 100644
> index 0000000000..33734e3111
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecRamInitData.c
> @@ -0,0 +1,16 @@
> +/** @file
> + Calling Fsp Apis in SEC
> +
> + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Library/PcdLib.h>
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32
> TempRamInitParams[4] = {
> + ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) +
> FixedPcdGet32 (PcdFlashMicroCodeOffset)),
> + ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) -
> FixedPcdGet32 (PcdFlashMicroCodeOffset)),
> + FixedPcdGet32 (PcdFlashCodeCacheAddress),
> + FixedPcdGet32 (PcdFlashCodeCacheSize)
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecTempRamSupport.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecTempRamSupport.c
> new file mode 100644
> index 0000000000..8dd1367980
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/SecTempRamSupport.c
> @@ -0,0 +1,149 @@
> +/** @file
> + C functions in SEC
> +
> + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/TemporaryRamSupport.h>
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugAgentLib.h>
> +
> +/**
> + Switch the stack in the temporary memory to the one in the permanent
> memory.
> +
> + This function must be invoked after the memory migration immediately.
> The relative
> + position of the stack in the temporary and permanent memory is same.
> +
> + @param TemporaryMemoryBase Base address of the temporary memory.
> + @param PermenentMemoryBase Base address of the permanent
> memory.
> +**/
> +VOID
> +EFIAPI
> +SecSwitchStack (
> + UINT32 TemporaryMemoryBase,
> + UINT32 PermenentMemoryBase
> + );
> +
> +/**
> + This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates
> temporary RAM into
> + permanent memory.
> +
> + @param PeiServices Pointer to the PEI Services Table.
> + @param TemporaryMemoryBase Source Address in temporary memory
> from which the SEC or PEIM will copy the
> + Temporary RAM contents.
> + @param PermanentMemoryBase Destination Address in permanent
> memory into which the SEC or PEIM will copy the
> + Temporary RAM contents.
> + @param CopySize Amount of memory to migrate from temporary
> to permanent memory.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> + @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize >
> TemporaryMemoryBase when
> + TemporaryMemoryBase > PermanentMemoryBase.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecTemporaryRamSupport (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
> + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
> + IN UINTN CopySize
> + )
> +{
> + IA32_DESCRIPTOR IdtDescriptor;
> + VOID* OldHeap;
> + VOID* NewHeap;
> + VOID* OldStack;
> + VOID* NewStack;
> + DEBUG_AGENT_CONTEXT_POSTMEM_SEC DebugAgentContext;
> + BOOLEAN OldStatus;
> + UINTN PeiStackSize;
> +
> + PeiStackSize = (UINTN)PcdGet32 (PcdPeiTemporaryRamStackSize);
> + if (PeiStackSize == 0) {
> + PeiStackSize = (CopySize >> 1);
> + }
> +
> + ASSERT (PeiStackSize < CopySize);
> +
> + //
> + // |-------------------|---->
> + // | Stack | PeiStackSize
> + // |-------------------|---->
> + // | Heap | PeiTemporayRamSize
> + // |-------------------|----> TempRamBase
> + //
> + // |-------------------|---->
> + // | Heap | PeiTemporayRamSize
> + // |-------------------|---->
> + // | Stack | PeiStackSize
> + // |-------------------|----> PermanentMemoryBase
> + //
> +
> + OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
> + NewHeap = (VOID*)((UINTN)PermanentMemoryBase + PeiStackSize);
> +
> + OldStack = (VOID*)((UINTN)TemporaryMemoryBase + CopySize -
> PeiStackSize);
> + NewStack = (VOID*)(UINTN)PermanentMemoryBase;
> +
> + DebugAgentContext.HeapMigrateOffset = (UINTN)NewHeap -
> (UINTN)OldHeap;
> + DebugAgentContext.StackMigrateOffset = (UINTN)NewStack -
> (UINTN)OldStack;
> +
> + OldStatus = SaveAndSetDebugTimerInterrupt (FALSE);
> +
> + //
> + // Initialize Debug Agent to support source level debug in PEI phase after
> memory ready.
> + // It will build HOB and fix up the pointer in IDT table.
> + //
> + InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, (VOID *)
> &DebugAgentContext, NULL);
> +
> + //
> + // Migrate Heap
> + //
> + CopyMem (NewHeap, OldHeap, CopySize - PeiStackSize);
> +
> + //
> + // Migrate Stack
> + //
> + CopyMem (NewStack, OldStack, PeiStackSize);
> +
> +
> + //
> + // We need *not* fix the return address because currently,
> + // The PeiCore is executed in flash.
> + //
> +
> + //
> + // Rebase IDT table in permanent memory
> + //
> + AsmReadIdtr (&IdtDescriptor);
> + IdtDescriptor.Base = IdtDescriptor.Base - (UINTN)OldStack +
> (UINTN)NewStack;
> +
> + AsmWriteIdtr (&IdtDescriptor);
> +
> +
> + //
> + // Program MTRR
> + //
> +
> + //
> + // SecSwitchStack function must be invoked after the memory migration
> + // immediately, also we need fixup the stack change caused by new call
> into
> + // permanent memory.
> + //
> + SecSwitchStack (
> + (UINT32) (UINTN) OldStack,
> + (UINT32) (UINTN) NewStack
> + );
> +
> + SaveAndSetDebugTimerInterrupt (OldStatus);
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/UartInit.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/UartInit.c
> new file mode 100644
> index 0000000000..2a9ab17120
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecL
> ibVlv2/UartInit.c
> @@ -0,0 +1,192 @@
> +/** @file
> + This PEIM will parse the hoblist from fsp and report them into pei core.
> + This file contains the main entrypoint of the PEIM.
> +
> + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +
> +#include <PiPei.h>
> +#include <Library/IoLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +#define PCI_IDX 0xCF8
> +#define PCI_DAT 0xCFC
> +
> +#define PCI_LPC_BASE (0x8000F800)
> +#define PCI_LPC_REG(x) (PCI_LPC_BASE + (x))
> +
> +#define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base
> Address
> +#define R_PCH_LPC_PMC_BASE 0x44 // PBASE, 32bit, 512 Bytes
> +#define B_PCH_LPC_PMC_BASE_EN BIT1 // Enable Bit
> +#define R_PCH_PMC_GEN_PMCON_1 0x20 // General PM
> Configuration 1
> +#define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR BIT14 // SUS Well
> Power Failure
> +#define B_PCH_PMC_GEN_PMCON_PWROK_FLR BIT16 // PWROK
> Failure
> +
> +#define R_PCH_LPC_UART_CTRL 0x80 // UART Control
> +#define B_PCH_LPC_UART_CTRL_COM1_EN BIT0 // COM1 Enable
> +
> +#define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base
> Address
> +#define R_PCH_ILB_IRQE 0x88 // IRQ Enable Control
> +
> +#define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base
> Address
> +
> +#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3
> Enable
> +#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4 BIT4 // UART IRQ4
> Enable
> +#define PCIEX_BASE_ADDRESS 0xE0000000
> +#define PCI_EXPRESS_BASE_ADDRESS PCIEX_BASE_ADDRESS
> +#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32)
> (31 << 15)
> +#define SB_RCBA 0xfed1c000
> +
> +typedef enum {
> + PchA0 = 0,
> + PchA1 = 1,
> + PchB0 = 2,
> + PchB1 = 3,
> + PchB2 = 4,
> + PchB3 = 5,
> + PchC0 = 6,
> + PchSteppingMax
> +} PCH_STEPPING;
> +
> +#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
> + ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
> + (UINTN)(Bus << 20) + \
> + (UINTN)(Device << 15) + \
> + (UINTN)(Function << 12) + \
> + (UINTN)(Register) \
> + )
> +
> +#define DEFAULT_PCI_BUS_NUMBER_PCH 0
> +#define PCI_DEVICE_NUMBER_PCH_LPC 31
> +#define PCI_FUNCTION_NUMBER_PCH_LPC 0
> +
> +#define R_PCH_LPC_RID_CC 0x08 // Revision ID & Class Code
> +
> +#define V_PCH_LPC_RID_0 0x01 // A0 Stepping (17 x 17)
> +#define V_PCH_LPC_RID_1 0x02 // A0 Stepping (25 x 27)
> +#define V_PCH_LPC_RID_2 0x03 // A1 Stepping (17 x 17)
> +#define V_PCH_LPC_RID_3 0x04 // A1 Stepping (25 x 27)
> +#define V_PCH_LPC_RID_4 0x05 // B0 Stepping (17 x 17)
> +#define V_PCH_LPC_RID_5 0x06 // B0 Stepping (25 x 27)
> +#define V_PCH_LPC_RID_6 0x07 // B1 Stepping (17 x 17)
> +#define V_PCH_LPC_RID_7 0x08 // B1 Stepping (25 x 27)
> +#define V_PCH_LPC_RID_8 0x09 // B2 Stepping (17 x 17)
> +#define V_PCH_LPC_RID_9 0x0A // B2 Stepping (25 x 27)
> +#define V_PCH_LPC_RID_A 0x0B // B3 Stepping (17 x 17)
> +#define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27)
> +#define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17)
> +#define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27)
> +
> +/**
> + Return Pch stepping type
> +
> + @param[in] None
> +
> + @retval PCH_STEPPING Pch stepping type
> +
> +**/
> +PCH_STEPPING
> +EFIAPI
> +PchStepping (
> + VOID
> + )
> +{
> + UINT8 RevId;
> +
> + RevId = MmioRead8 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_RID_CC)
> + );
> +
> + switch (RevId) {
> + case V_PCH_LPC_RID_0:
> + case V_PCH_LPC_RID_1:
> + return PchA0;
> + break;
> +
> + case V_PCH_LPC_RID_2:
> + case V_PCH_LPC_RID_3:
> + return PchA1;
> + break;
> +
> + case V_PCH_LPC_RID_4:
> + case V_PCH_LPC_RID_5:
> + return PchB0;
> + break;
> +
> + case V_PCH_LPC_RID_6:
> + case V_PCH_LPC_RID_7:
> + return PchB1;
> + break;
> +
> + case V_PCH_LPC_RID_8:
> + case V_PCH_LPC_RID_9:
> + return PchB2;
> + break;
> +
> + case V_PCH_LPC_RID_A:
> + case V_PCH_LPC_RID_B:
> + return PchB3;
> + break;
> +
> + case V_PCH_LPC_RID_C:
> + case V_PCH_LPC_RID_D:
> + return PchC0;
> + break;
> +
> + default:
> + return PchSteppingMax;
> + break;
> +
> + }
> +}
> +
> +/**
> + Enable legacy decoding on ICH6
> +
> + @param[in] none
> +
> + @retval EFI_SUCCESS Always returns success.
> +
> +**/
> +VOID
> +EnableInternalUart(
> + VOID
> + )
> +{
> +
> + //
> + // Program and enable PMC Base.
> + //
> + IoWrite32 (PCI_IDX, PCI_LPC_REG(R_PCH_LPC_PMC_BASE));
> + IoWrite32 (PCI_DAT, (PMC_BASE_ADDRESS |
> B_PCH_LPC_PMC_BASE_EN));
> +
> + //
> + // Enable COM1 for debug message output.
> + //
> + MmioAndThenOr32 (PMC_BASE_ADDRESS +
> R_PCH_PMC_GEN_PMCON_1, (UINT32)
> (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR +
> B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);
> +
> + //
> + // Silicon Steppings
> + //
> + if (PchStepping()>= PchB0)
> + MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8)
> V_PCH_ILB_IRQE_UARTIRQEN_IRQ4);
> + else
> + MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8)
> V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);
> + MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));
> + MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L
> + MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));
> + MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L
> + MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8)
> B_PCH_LPC_UART_CTRL_COM1_EN);
> +
> + SerialPortInitialize ();
> + SerialPortWrite ((UINT8 *)"EnableInternalUart!\r\n",
> sizeof("EnableInternalUart!\r\n") - 1);
> +
> + return ;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.c
> new file mode 100644
> index 0000000000..11832bd295
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.c
> @@ -0,0 +1,68 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + FvInfoPei.c
> +
> +Abstract:
> +
> + EFI 2.0 PEIM to initialize the cache and program for unlock processor
> +
> +
> +
> +--*/
> +
> +#include <PiPei.h>
> +#include <Guid/FirmwareFileSystem2.h>
> +#include <Ppi/FirmwareVolumeInfo.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +EFI_PEI_FIRMWARE_VOLUME_INFO_PPI mAddtionFVPpi = {
> + EFI_FIRMWARE_FILE_SYSTEM2_GUID,
> + (VOID*)(UINTN)FixedPcdGet32(PcdFlashFvRecovery2Base),
> + FixedPcdGet32(PcdFlashFvRecovery2Size),
> + NULL,
> + NULL
> +};
> +
> +EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
> + (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gEfiPeiFirmwareVolumeInfoPpiGuid,
> + &mAddtionFVPpi
> +};
> +
> +
> +/**
> + Add Recovery Fv Info to the Pei Core.
> +
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval Status
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeimInitializeFvInfo (
> + IN EFI_PEI_FILE_HANDLE FileHandle,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +
> +//
> +// GC_TODO: FfsHeader - add argument and description to function
> comment
> +//
> +{
> + EFI_STATUS Status;
> + Status = (**PeiServices).InstallPpi (PeiServices, &mPpiList[0]);
> + ASSERT_EFI_ERROR (Status);
> +
> + DEBUG ((EFI_D_INFO, "\nFvInfo Add Fv Info\n"));
> +
> + return Status;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.inf
> new file mode 100644
> index 0000000000..397c2ce2a9
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.inf
> @@ -0,0 +1,49 @@
> +#
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +# Module Name:
> +#
> +# CpuPeim.inf
> +#
> +# Abstract:
> +#
> +# Component description file for CPU module
> +#
> +#
> +#--*/
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = FvInfoPei
> + FILE_GUID = 64AAEAE0-92DF-4980-8668-6EB5EAAF4393
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PeimInitializeFvInfo
> +
> +[sources.common]
> + FvInfoPei.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + PeimEntryPoint
> + DebugLib
> +
> +[Pcd.common]
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size
> +
> +[Ppis]
> + gEfiPeiFirmwareVolumeInfoPpiGuid
> +
> +[Depex]
> + TRUE
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbInfo.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbInfo.c
> new file mode 100644
> index 0000000000..d3b9145db0
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbInfo.c
> @@ -0,0 +1,170 @@
> +/**@file
> + Defines data structure that is the volume header found.
> + These data is intent to decouple FVB driver with FV header.
> +
> +Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <Protocol/FirmwareVolumeBlock.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +#include <Guid/FirmwareFileSystem2.h>
> +#include <Guid/SystemNvDataGuid.h>
> +
> +#define FIRMWARE_BLOCK_SIZE 0x8000
> +#define FVB_MEDIA_BLOCK_SIZE (FIRMWARE_BLOCK_SIZE * 2)
> +
> +#define FV_RECOVERY_BASE_ADDRESS
> FixedPcdGet32(PcdFlashFvRecoveryBase)
> +#define RECOVERY_BIOS_BLOCK_NUM
> (FixedPcdGet32(PcdFlashFvRecoverySize) / FVB_MEDIA_BLOCK_SIZE)
> +
> +#define FV_MAIN_BASE_ADDRESS FixedPcdGet32(PcdFlashFvMainBase)
> +#define MAIN_BIOS_BLOCK_NUM
> (FixedPcdGet32(PcdFlashFvMainSize) / FVB_MEDIA_BLOCK_SIZE)
> +
> +#define NV_STORAGE_BASE_ADDRESS
> FixedPcdGet32(PcdFlashNvStorageVariableBase)
> +#define SYSTEM_NV_BLOCK_NUM
> ((FixedPcdGet32(PcdFlashNvStorageVariableSize)+
> FixedPcdGet32(PcdFlashNvStorageFtwWorkingSize) +
> FixedPcdGet32(PcdFlashNvStorageFtwSpareSize))/ FVB_MEDIA_BLOCK_SIZE)
> +
> +typedef struct {
> + EFI_PHYSICAL_ADDRESS BaseAddress;
> + EFI_FIRMWARE_VOLUME_HEADER FvbInfo;
> + EFI_FV_BLOCK_MAP_ENTRY End[1];
> +} EFI_FVB2_MEDIA_INFO;
> +
> +//
> +// This data structure contains a template of all correct FV headers, which is
> used to restore
> +// Fv header if it's corrupted.
> +//
> +EFI_FVB2_MEDIA_INFO mPlatformFvbMediaInfo[] = {
> + //
> + // Main BIOS FVB
> + //
> + {
> + FV_MAIN_BASE_ADDRESS,
> + {
> + {0,}, //ZeroVector[16]
> + EFI_FIRMWARE_FILE_SYSTEM2_GUID,
> + FVB_MEDIA_BLOCK_SIZE * MAIN_BIOS_BLOCK_NUM,
> + EFI_FVH_SIGNATURE,
> + 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details
> on EFI_FVB_ATTRIBUTES_2
> + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof
> (EFI_FV_BLOCK_MAP_ENTRY),
> + 0, //CheckSum which will be calucated dynamically.
> + 0, //ExtHeaderOffset
> + {0,}, //Reserved[1]
> + 2, //Revision
> + {
> + {
> + MAIN_BIOS_BLOCK_NUM,
> + FVB_MEDIA_BLOCK_SIZE,
> + }
> + }
> + },
> + {
> + {
> + 0,
> + 0
> + }
> + }
> + },
> +
> + //
> + // Systen NvStorage FVB
> + //
> + {
> + NV_STORAGE_BASE_ADDRESS,
> + {
> + {0,}, //ZeroVector[16]
> + EFI_SYSTEM_NV_DATA_FV_GUID,
> + FVB_MEDIA_BLOCK_SIZE * SYSTEM_NV_BLOCK_NUM,
> + EFI_FVH_SIGNATURE,
> + 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details
> on EFI_FVB_ATTRIBUTES_2
> + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof
> (EFI_FV_BLOCK_MAP_ENTRY),
> + 0, //CheckSum which will be calucated dynamically.
> + 0, //ExtHeaderOffset
> + {0,}, //Reserved[1]
> + 2, //Revision
> + {
> + {
> + SYSTEM_NV_BLOCK_NUM,
> + FVB_MEDIA_BLOCK_SIZE,
> + }
> + }
> + },
> + {
> + {
> + 0,
> + 0
> + }
> + }
> + },
> +
> + //
> + // Recovery BIOS FVB
> + //
> + {
> + FV_RECOVERY_BASE_ADDRESS,
> + {
> + {0,}, //ZeroVector[16]
> + EFI_FIRMWARE_FILE_SYSTEM2_GUID,
> + FVB_MEDIA_BLOCK_SIZE * RECOVERY_BIOS_BLOCK_NUM,
> + EFI_FVH_SIGNATURE,
> + 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details
> on EFI_FVB_ATTRIBUTES_2
> + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof
> (EFI_FV_BLOCK_MAP_ENTRY),
> + 0, //CheckSum which will be calucated dynamically.
> + 0, //ExtHeaderOffset
> + {0,}, //Reserved[1]
> + 2, //Revision
> + {
> + {
> + RECOVERY_BIOS_BLOCK_NUM,
> + FVB_MEDIA_BLOCK_SIZE,
> + }
> + }
> + },
> + {
> + {
> + 0,
> + 0
> + }
> + }
> + }
> +};
> +
> +EFI_STATUS
> +GetFvbInfo (
> + IN EFI_PHYSICAL_ADDRESS FvBaseAddress,
> + OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo
> + )
> +{
> + UINTN Index;
> + EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
> +
> + for (Index = 0; Index < sizeof (mPlatformFvbMediaInfo) / sizeof
> (EFI_FVB2_MEDIA_INFO); Index += 1) {
> + if (mPlatformFvbMediaInfo[Index].BaseAddress == FvBaseAddress) {
> + FvHeader = &mPlatformFvbMediaInfo[Index].FvbInfo;
> +
> + //
> + // Update the checksum value of FV header.
> + //
> + FvHeader->Checksum = CalculateCheckSum16 ((UINT16 *) FvHeader,
> FvHeader->HeaderLength);
> +
> + *FvbInfo = FvHeader;
> +
> + DEBUG ((EFI_D_INFO, "\nBaseAddr: 0x%lx \n", FvBaseAddress));
> + DEBUG ((EFI_D_INFO, "FvLength: 0x%lx \n", (*FvbInfo)->FvLength));
> + DEBUG ((EFI_D_INFO, "HeaderLength: 0x%x \n", (*FvbInfo)-
> >HeaderLength));
> + DEBUG ((EFI_D_INFO, "FvBlockMap[0].NumBlocks: 0x%x \n",
> (*FvbInfo)->BlockMap[0].NumBlocks));
> + DEBUG ((EFI_D_INFO, "FvBlockMap[0].BlockLength: 0x%x \n",
> (*FvbInfo)->BlockMap[0].Length));
> + DEBUG ((EFI_D_INFO, "FvBlockMap[1].NumBlocks: 0x%x \n",
> (*FvbInfo)->BlockMap[1].NumBlocks));
> + DEBUG ((EFI_D_INFO, "FvBlockMap[1].BlockLength: 0x%x \n\n",
> (*FvbInfo)->BlockMap[1].Length));
> +
> + return EFI_SUCCESS;
> + }
> + }
> + return EFI_NOT_FOUND;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbRuntimeDxe.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbRuntimeDxe.inf
> new file mode 100644
> index 0000000000..670db13465
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbRuntimeDxe.inf
> @@ -0,0 +1,80 @@
> +## @file
> +# This driver implement the EFI_FIRMWARE_VOLUMEN_PROTOCOL.
> +#
> +# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = FvbRuntimeDxe
> + FILE_GUID = FD3B7E55-FA7B-4e07-AE1D-208B81FB0BAD
> + MODULE_TYPE = DXE_RUNTIME_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = DxeFvbInitialize
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +# VIRTUAL_ADDRESS_MAP_CALLBACK = FvbVirtualddressChangeEvent
> +#
> +
> +[Sources]
> + FvbInfo.c
> + FvbService.h
> + FvbService.c
> + FvbServiceDxe.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + FlashDeviceLib
> + PcdLib
> + MemoryAllocationLib
> + CacheMaintenanceLib
> + IoLib
> + BaseMemoryLib
> + DebugLib
> + BaseLib
> + UefiLib
> + UefiRuntimeLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> +
> +[Guids]
> + gEfiFirmwareFileSystem2Guid # ALWAYS_CONSUMED
> + gEfiSystemNvDataFvGuid # ALWAYS_CONSUMED
> + gEfiEventVirtualAddressChangeGuid
> +
> +[Protocols]
> + gEfiDevicePathProtocolGuid # PROTOCOL ALWAYS_PRODUCED
> + gEfiFirmwareVolumeBlockProtocolGuid # PROTOCOL
> ALWAYS_PRODUCED
> +
> +[FixedPcd]
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase
> +
> +[Pcd]
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +
> +
> +[Depex]
> + gEfiSpiProtocolGuid AND gEfiRuntimeArchProtocolGuid
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.c
> new file mode 100644
> index 0000000000..aa4fab013d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.c
> @@ -0,0 +1,1098 @@
> +/** @file
> + Firmware Volume Block Driver for Lakeport Platform.
> +
> + Firmware volume block driver for FWH or SPI device.
> + It depends on which Flash Device Library to be linked with this driver.
> +
> +Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include "FvbService.h"
> +
> +//
> +// Global variable for this FVB driver which contains
> +// the private data of all firmware volume block instances.
> +//
> +FWB_GLOBAL mFvbModuleGlobal;
> +
> +//
> +// This platform driver knows there are 3 FVs on
> +// FD, which are FvRecovery, FvMain and FvNvStorage.
> +//
> +UINT32 mPlatformFvBaseAddress[] = {
> + FixedPcdGet32(PcdFlashNvStorageVariableBase),
> +};
> +
> +FV_MEMMAP_DEVICE_PATH mFvMemmapDevicePathTemplate = {
> + {
> + {
> + HARDWARE_DEVICE_PATH,
> + HW_MEMMAP_DP,
> + {
> + (UINT8)(sizeof (MEMMAP_DEVICE_PATH)),
> + (UINT8)(sizeof (MEMMAP_DEVICE_PATH) >> 8)
> + }
> + },
> + EfiMemoryMappedIO,
> + (EFI_PHYSICAL_ADDRESS) 0,
> + (EFI_PHYSICAL_ADDRESS) 0,
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> +};
> +
> +FV_PIWG_DEVICE_PATH mFvPIWGDevicePathTemplate = {
> + {
> + {
> + MEDIA_DEVICE_PATH,
> + MEDIA_PIWG_FW_VOL_DP,
> + {
> + (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH)),
> + (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH) >> 8)
> + }
> + },
> + { 0 }
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> +};
> +
> +//
> +// Template structure used when installing FVB protocol.
> +//
> +EFI_FW_VOL_BLOCK_DEVICE mFvbDeviceTemplate = {
> + FVB_DEVICE_SIGNATURE,
> + NULL,
> + 0, // Instance
> + {
> + FvbProtocolGetAttributes,
> + FvbProtocolSetAttributes,
> + FvbProtocolGetPhysicalAddress,
> + FvbProtocolGetBlockSize,
> + FvbProtocolRead,
> + FvbProtocolWrite,
> + FvbProtocolEraseBlocks,
> + NULL
> + } // FwVolBlockInstance
> +};
> +
> +
> +/**
> + Get the pointer to EFI_FW_VOL_INSTANCE from the buffer pointed
> + by mFvbModuleGlobal.FvInstance based on a index.
> + Each EFI_FW_VOL_INSTANCE is with variable length as
> + we have a block map at the end of the EFI_FIRMWARE_VOLUME_HEADER.
> +
> + @param[in] Instance The index of the EFI_FW_VOL_INSTANCE.
> +
> + @return A pointer to EFI_FW_VOL_INSTANCE.
> +
> +**/
> +EFI_FW_VOL_INSTANCE *
> +GetFvbInstance (
> + IN UINTN Instance
> + )
> +{
> + EFI_FW_VOL_INSTANCE *FwhRecord;
> +
> + if ( Instance >= mFvbModuleGlobal.NumFv ) {
> + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
> + return NULL;
> + }
> +
> + //
> + // Find the right instance of the FVB private data.
> + //
> + FwhRecord = mFvbModuleGlobal.FvInstance;
> + while ( Instance > 0 ) {
> + FwhRecord = (EFI_FW_VOL_INSTANCE *) ((UINTN)((UINT8 *)FwhRecord)
> +
> + FwhRecord->VolumeHeader.HeaderLength +
> + (sizeof (EFI_FW_VOL_INSTANCE) - sizeof
> (EFI_FIRMWARE_VOLUME_HEADER)));
> + Instance --;
> + }
> +
> + return FwhRecord;
> +
> +}
> +
> +
> +/**
> + Get the EFI_FVB_ATTRIBUTES_2 of a FV.
> +
> + @param[in] The index of the EFI_FW_VOL_INSTANCE.
> +
> + @return EFI_FVB_ATTRIBUTES_2 of the FV identified by Instance.
> +
> +**/
> +STATIC
> +EFI_FVB_ATTRIBUTES_2
> +FvbGetVolumeAttributes (
> + IN UINTN Instance
> + )
> +{
> + EFI_FW_VOL_INSTANCE * FwInstance = NULL;
> + FwInstance = GetFvbInstance(Instance);
> + ASSERT (FwInstance != NULL);
> +
> + if ( FwInstance != NULL ) {
> + return FwInstance->VolumeHeader.Attributes;
> + } else {
> + return 0;
> + }
> +}
> +
> +
> +/**
> + Retrieves the starting address of an LBA in an FV. It also
> + return a few other attribut of the FV.
> +
> + @param[in] Instance The index of the EFI_FW_VOL_INSTANCE.
> + @param[in] Lba The logical block address.
> + @param[out] LbaAddress On output, contains the physical starting
> address
> + of the Lba.
> + @param[out] LbaLength On output, contains the length of the block.
> + @param[out] NumOfBlocks A pointer to a caller allocated UINTN in
> which the
> + number of consecutive blocks starting with Lba is
> + returned. All blocks in this range have a size of
> + BlockSize.
> +
> + @retval EFI_SUCCESS Successfully returns.
> + @retval EFI_INVALID_PARAMETER Instance not found.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +FvbGetLbaAddress (
> + IN UINTN Instance,
> + IN EFI_LBA Lba,
> + OUT UINTN *LbaAddress,
> + OUT UINTN *LbaLength,
> + OUT UINTN *NumOfBlocks
> + )
> +{
> + UINT32 NumBlocks = 0;
> + UINT32 BlockLength = 0;
> + UINTN Offset;
> + EFI_LBA StartLba;
> + EFI_LBA NextLba;
> + EFI_FW_VOL_INSTANCE *FwhInstance;
> + EFI_FV_BLOCK_MAP_ENTRY *BlockMap = NULL;
> +
> + //
> + // Find the right instance of the FVB private data.
> + //
> + FwhInstance = GetFvbInstance (Instance);
> +
> + StartLba = 0;
> + Offset = 0;
> + BlockMap = &(FwhInstance->VolumeHeader.BlockMap[0]);
> + ASSERT (BlockMap != NULL);
> +
> + //
> + // Parse the blockmap of the FV to find which map entry the Lba belongs
> to.
> + //
> + while (TRUE) {
> + if ( BlockMap != NULL) {
> + NumBlocks = BlockMap->NumBlocks;
> + BlockLength = BlockMap->Length;
> + }
> +
> + if ( NumBlocks == 0 || BlockLength == 0) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + NextLba = StartLba + NumBlocks;
> +
> + //
> + // The map entry found.
> + //
> + if (Lba >= StartLba && Lba < NextLba) {
> + Offset = Offset + (UINTN)MultU64x32((Lba - StartLba), BlockLength);
> + if ( LbaAddress && FwhInstance ) {
> + *LbaAddress = FwhInstance->FvBase + Offset;
> + }
> +
> + if (LbaLength ) {
> + *LbaLength = BlockLength;
> + }
> +
> + if (NumOfBlocks ) {
> + *NumOfBlocks = (UINTN)(NextLba - Lba);
> + }
> + return EFI_SUCCESS;
> + }
> +
> + StartLba = NextLba;
> + Offset = Offset + NumBlocks * BlockLength;
> + BlockMap++;
> + }
> +}
> +
> +
> +/**
> + Reads specified number of bytes into a buffer from the specified block.
> +
> + @param[in] Instance The FV instance to be read from.
> + @param[in] Lba The logical block address to be read from.
> + @param[in] BlockOffset Offset into the block at which to begin
> reading.
> + @param[in] NumBytes Pointer that on input contains the total
> size of
> + the buffer. On output, it contains the total number
> + of bytes read.
> + @param[in] Buffer Pointer to a caller allocated buffer that will
> be
> + used to hold the data read.
> +
> +
> + @retval EFI_SUCCESS The firmware volume was read successfully
> and
> + contents are in Buffer.
> + @retval EFI_BAD_BUFFER_SIZE Read attempted across a LBA
> boundary. On output,
> + NumBytes contains the total number of bytes returned
> + in Buffer.
> + @retval EFI_ACCESS_DENIED The firmware volume is in the
> ReadDisabled state.
> + @retval EFI_DEVICE_ERROR The block device is not functioning
> correctly and
> + could not be read.
> + @retval EFI_INVALID_PARAMETER Instance not found, or NumBytes,
> Buffer are NULL.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +FvbReadBlock (
> + IN UINTN Instance,
> + IN EFI_LBA Lba,
> + IN UINTN BlockOffset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> + EFI_FVB_ATTRIBUTES_2 Attributes;
> + UINTN LbaAddress;
> + UINTN LbaLength;
> + EFI_STATUS Status;
> +
> + if ( (NumBytes == NULL) || (Buffer == NULL)) {
> + return (EFI_INVALID_PARAMETER);
> + }
> + if (*NumBytes == 0) {
> + return (EFI_INVALID_PARAMETER);
> + }
> +
> + Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, &LbaLength,
> NULL);
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + Attributes = FvbGetVolumeAttributes (Instance);
> +
> + if ( (Attributes & EFI_FVB2_READ_STATUS) == 0) {
> + return (EFI_ACCESS_DENIED);
> + }
> +
> + if (BlockOffset > LbaLength) {
> + return (EFI_INVALID_PARAMETER);
> + }
> +
> + if (LbaLength < ( *NumBytes + BlockOffset ) ) {
> + *NumBytes = (UINT32) (LbaLength - BlockOffset);
> + Status = EFI_BAD_BUFFER_SIZE;
> + }
> +
> + LibFvbFlashDeviceRead (LbaAddress + BlockOffset, NumBytes, Buffer);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Writes specified number of bytes from the input buffer to the block.
> +
> + @param[in] Instance The FV instance to be written to.
> + @param[in] Lba The starting logical block index to write to.
> + @param[in] BlockOffset Offset into the block at which to begin
> writing.
> + @param[in] NumBytes Pointer that on input contains the total size
> of
> + the buffer. On output, it contains the total number
> + of bytes actually written.
> + @param[in] Buffer Pointer to a caller allocated buffer that
> contains
> + the source for the write.
> + @retval EFI_SUCCESS The firmware volume was written
> successfully.
> + @retval EFI_BAD_BUFFER_SIZE Write attempted across a LBA
> boundary. On output,
> + NumBytes contains the total number of bytes
> + actually writte.
> + @retval EFI_ACCESS_DENIED The firmware volume is in the
> WriteDisabled state.
> + @retval EFI_DEVICE_ERROR The block device is not functioning
> correctly and
> + could not be written.
> + @retval EFI_INVALID_PARAMETER Instance not found, or NumBytes,
> Buffer are NULL.
> +
> +**/
> +EFI_STATUS
> +FvbWriteBlock (
> + IN UINTN Instance,
> + IN EFI_LBA Lba,
> + IN UINTN BlockOffset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> + EFI_FVB_ATTRIBUTES_2 Attributes;
> + UINTN LbaAddress;
> + UINTN LbaLength;
> + EFI_STATUS Status;
> + EFI_STATUS Status1;
> +
> + if ( (NumBytes == NULL) || (Buffer == NULL)) {
> + return (EFI_INVALID_PARAMETER);
> + }
> + if (*NumBytes == 0) {
> + return (EFI_INVALID_PARAMETER);
> + }
> +
> + Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, &LbaLength,
> NULL);
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + //
> + // Check if the FV is write enabled.
> + //
> + Attributes = FvbGetVolumeAttributes (Instance);
> + if ( (Attributes & EFI_FVB2_WRITE_STATUS) == 0) {
> + return (EFI_ACCESS_DENIED);
> + }
> +
> + //
> + // Perform boundary checks and adjust NumBytes.
> + //
> + if (BlockOffset > LbaLength) {
> + return (EFI_INVALID_PARAMETER);
> + }
> +
> + if ( LbaLength < ( *NumBytes + BlockOffset ) ) {
> + DEBUG ((EFI_D_ERROR,
> + "FvWriteBlock: Reducing Numbytes from 0x%x to 0x%x\n",
> + *NumBytes,
> + (UINT32)(LbaLength-BlockOffset))
> + );
> + *NumBytes = (UINT32) (LbaLength - BlockOffset);
> + Status = EFI_BAD_BUFFER_SIZE;
> + }
> +
> + LibFvbFlashDeviceBlockLock (LbaAddress, LbaLength, FALSE);
> +
> + Status1 = LibFvbFlashDeviceWrite (LbaAddress + BlockOffset, NumBytes,
> Buffer);
> +
> + LibFvbFlashDeviceBlockLock (LbaAddress, LbaLength, TRUE);
> + WriteBackInvalidateDataCacheRange ((VOID *) (LbaAddress + BlockOffset),
> *NumBytes);
> +
> + if ( EFI_ERROR (Status1) ) {
> + return Status1;
> + }
> +
> + return Status;
> +}
> +
> +
> +/**
> + Erases and initializes a firmware volume block.
> +
> + @param[in] Instance The FV instance to be erased.
> + @param[in] Lba The logical block index to be erased.
> +
> + @retval EFI_SUCCESS The erase request was successfully completed.
> + @retval EFI_ACCESS_DENIED The firmware volume is in the
> WriteDisabled state.
> + @retval EFI_DEVICE_ERROR The block device is not functioning
> correctly and
> + could not be written. Firmware device may have been
> + partially erased.
> + @retval EFI_INVALID_PARAMETER Instance not found.
> +
> +**/
> +EFI_STATUS
> +FvbEraseBlock (
> + IN UINTN Instance,
> + IN EFI_LBA Lba
> + )
> +{
> + EFI_FVB_ATTRIBUTES_2 Attributes;
> + UINTN LbaAddress;
> + UINTN LbaLength;
> + EFI_STATUS Status;
> +
> + //
> + // Check if the FV is write enabled.
> + //
> + Attributes = FvbGetVolumeAttributes (Instance);
> +
> + if( (Attributes & EFI_FVB2_WRITE_STATUS) == 0) {
> + return (EFI_ACCESS_DENIED);
> + }
> +
> + //
> + // Get the starting address of the block for erase.
> + //
> + Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, &LbaLength,
> NULL);
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + LibFvbFlashDeviceBlockLock (LbaAddress, LbaLength, FALSE);
> +
> + Status = LibFvbFlashDeviceBlockErase (LbaAddress, LbaLength);
> +
> + LibFvbFlashDeviceBlockLock (LbaAddress, LbaLength, TRUE);
> +
> + WriteBackInvalidateDataCacheRange ((VOID *) LbaAddress, LbaLength);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Modifies the current settings of the firmware volume according to the
> + input parameter, and returns the new setting of the volume.
> +
> + @param[in] Instance The FV instance whose attributes is going to
> be
> + modified.
> + @param[in] Attributes On input, it is a pointer to
> EFI_FVB_ATTRIBUTES_2
> + containing the desired firmware volume settings.
> + On successful return, it contains the new settings
> + of the firmware volume.
> +
> + @retval EFI_SUCCESS Successfully returns.
> + @retval EFI_ACCESS_DENIED The volume setting is locked and cannot
> be modified.
> + @retval EFI_INVALID_PARAMETER Instance not found, or The attributes
> requested are
> + in conflict with the capabilities as declared in the
> + firmware volume header.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +FvbSetVolumeAttributes (
> + IN UINTN Instance,
> + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + )
> +{
> + EFI_FW_VOL_INSTANCE *FwhInstance = NULL;
> + EFI_FVB_ATTRIBUTES_2 OldAttributes = 0;
> + EFI_FVB_ATTRIBUTES_2 *AttribPtr = NULL;
> + EFI_FVB_ATTRIBUTES_2 UnchangedAttributes;
> + UINT32 Capabilities;
> + UINT32 OldStatus, NewStatus;
> +
> + //
> + // Find the right instance of the FVB private data.
> + //
> + FwhInstance = GetFvbInstance (Instance);
> +
> + AttribPtr = (EFI_FVB_ATTRIBUTES_2 *) & (FwhInstance-
> >VolumeHeader.Attributes);
> + ASSERT (AttribPtr != NULL);
> +
> + if ( AttribPtr != NULL) {
> + OldAttributes = *AttribPtr;
> + }
> +
> + Capabilities = OldAttributes & EFI_FVB2_CAPABILITIES;
> + OldStatus = OldAttributes & EFI_FVB2_STATUS;
> + NewStatus = *Attributes & EFI_FVB2_STATUS;
> +
> + UnchangedAttributes = EFI_FVB2_READ_DISABLED_CAP | \
> + EFI_FVB2_READ_ENABLED_CAP | \
> + EFI_FVB2_WRITE_DISABLED_CAP | \
> + EFI_FVB2_WRITE_ENABLED_CAP | \
> + EFI_FVB2_LOCK_CAP | \
> + EFI_FVB2_STICKY_WRITE | \
> + EFI_FVB2_MEMORY_MAPPED | \
> + EFI_FVB2_ERASE_POLARITY | \
> + EFI_FVB2_READ_LOCK_CAP | \
> + EFI_FVB2_WRITE_LOCK_CAP | \
> + EFI_FVB2_ALIGNMENT;
> +
> + //
> + // Some attributes of FV is read only can *not* be set.
> + //
> + if ((OldAttributes & UnchangedAttributes) ^ (*Attributes &
> UnchangedAttributes)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // If firmware volume is locked, no status bit can be updated.
> + //
> + if ( OldAttributes & EFI_FVB2_LOCK_STATUS ) {
> + if ( OldStatus ^ NewStatus ) {
> + return EFI_ACCESS_DENIED;
> + }
> + }
> +
> + //
> + // Test read disable.
> + //
> + if ((Capabilities & EFI_FVB2_READ_DISABLED_CAP) == 0) {
> + if ((NewStatus & EFI_FVB2_READ_STATUS) == 0) {
> + return EFI_INVALID_PARAMETER;
> + }
> + }
> +
> + //
> + // Test read enable.
> + //
> + if ((Capabilities & EFI_FVB2_READ_ENABLED_CAP) == 0) {
> + if (NewStatus & EFI_FVB2_READ_STATUS) {
> + return EFI_INVALID_PARAMETER;
> + }
> + }
> +
> + //
> + // Test write disable.
> + //
> + if ((Capabilities & EFI_FVB2_WRITE_DISABLED_CAP) == 0) {
> + if ((NewStatus & EFI_FVB2_WRITE_STATUS) == 0) {
> + return EFI_INVALID_PARAMETER;
> + }
> + }
> +
> + //
> + // Test write enable.
> + //
> + if ((Capabilities & EFI_FVB2_WRITE_ENABLED_CAP) == 0) {
> + if (NewStatus & EFI_FVB2_WRITE_STATUS) {
> + return EFI_INVALID_PARAMETER;
> + }
> + }
> +
> + //
> + // Test lock.
> + //
> + if ((Capabilities & EFI_FVB2_LOCK_CAP) == 0) {
> + if (NewStatus & EFI_FVB2_LOCK_STATUS) {
> + return EFI_INVALID_PARAMETER;
> + }
> + }
> +
> + *AttribPtr = (*AttribPtr) & (0xFFFFFFFF & (~EFI_FVB2_STATUS));
> + *AttribPtr = (*AttribPtr) | NewStatus;
> + *Attributes = *AttribPtr;
> +
> + return EFI_SUCCESS;
> +}
> +
> +//
> +// FVB protocol APIs.
> +//
> +/**
> + Retrieves the physical address of the device.
> +
> + @param[in] This A pointer to
> EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL.
> + @param[out] Address Output buffer containing the address.
> +
> + retval EFI_SUCCESS The function always return successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolGetPhysicalAddress (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + OUT EFI_PHYSICAL_ADDRESS *Address
> + )
> +{
> + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
> + EFI_FW_VOL_INSTANCE *FvInstance;
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> + FvInstance = GetFvbInstance(FvbDevice->Instance);
> +
> + if (FvInstance != NULL) {
> + *Address = FvInstance->FvBase;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Retrieve the size of a logical block.
> +
> + @param[in] This Calling context.
> + @param[in] Lba Indicates which block to return the size for.
> + @param[out] BlockSize A pointer to a caller allocated UINTN in which
> + the size of the block is returned.
> + @param[out] NumOfBlocks A pointer to a caller allocated UINTN in which
> the
> + number of consecutive blocks starting with Lba is
> + returned. All blocks in this range have a size of
> + BlockSize.
> +
> + @retval EFI_SUCCESS The function always return successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolGetBlockSize (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + OUT UINTN *BlockSize,
> + OUT UINTN *NumOfBlocks
> + )
> +{
> + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
> +
> + DEBUG((EFI_D_INFO,
> + "FvbProtocolGetBlockSize: Lba: 0x%lx BlockSize: 0x%x NumOfBlocks:
> 0x%x\n",
> + Lba,
> + BlockSize,
> + NumOfBlocks)
> + );
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> +
> + return FvbGetLbaAddress (
> + FvbDevice->Instance,
> + Lba,
> + NULL,
> + BlockSize,
> + NumOfBlocks
> + );
> +}
> +
> +
> +/**
> + Retrieves Volume attributes. No polarity translations are done.
> +
> + @param[in] This Calling context.
> + @param[out] Attributes Output buffer which contains attributes.
> +
> + @retval EFI_SUCCESS The function always return successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolGetAttributes (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + )
> +{
> + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> +
> + *Attributes = FvbGetVolumeAttributes (FvbDevice->Instance);
> +
> + DEBUG ((EFI_D_INFO,
> + "FvbProtocolGetAttributes: This: 0x%x Attributes: 0x%x\n",
> + This,
> + *Attributes)
> + );
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Sets Volume attributes. No polarity translations are done.
> +
> + @param[in] This Calling context.
> + @param[out] Attributes Output buffer which contains attributes.
> +
> + @retval EFI_SUCCESS The function always return successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolSetAttributes (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + )
> +{
> + EFI_STATUS Status;
> + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
> +
> + DEBUG((EFI_D_INFO,
> + "FvbProtocolSetAttributes: Before SET - This: 0x%x Attributes: 0x%x\n",
> + This,
> + *Attributes)
> + );
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> +
> + Status = FvbSetVolumeAttributes (FvbDevice->Instance, Attributes);
> +
> + DEBUG((EFI_D_INFO,
> + "FvbProtocolSetAttributes: After SET - This: 0x%x Attributes: 0x%x\n",
> + This,
> + *Attributes)
> + );
> +
> + return Status;
> +}
> +
> +
> +/**
> + The EraseBlock() function erases one or more blocks as denoted by the
> + variable argument list. The entire parameter list of blocks must be verified
> + prior to erasing any blocks. If a block is requested that does not exist
> + within the associated firmware volume (it has a larger index than the last
> + block of the firmware volume), the EraseBlock() function must return
> + EFI_INVALID_PARAMETER without modifying the contents of the firmware
> volume.
> +
> + @param[in] This Calling context.
> + @param[in] ... Starting LBA followed by Number of Lba to erase.
> + a -1 to terminate the list.
> +
> + @retval EFI_SUCCESS The erase request was successfully completed.
> + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled
> state.
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and
> + could not be written. Firmware device may have been
> + partially erased.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolEraseBlocks (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + ...
> + )
> +{
> + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
> + EFI_FW_VOL_INSTANCE *FwhInstance;
> + UINTN NumOfBlocks = 0;
> + VA_LIST args;
> + EFI_LBA StartingLba;
> + UINTN NumOfLba;
> + EFI_STATUS Status;
> +
> + DEBUG((EFI_D_INFO, "FvbProtocolEraseBlocks: \n"));
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> +
> + FwhInstance = GetFvbInstance (FvbDevice->Instance);
> +
> + if (FwhInstance != NULL) {
> + NumOfBlocks = FwhInstance->NumOfBlocks;
> + }
> +
> + VA_START (args, This);
> +
> + do {
> + StartingLba = VA_ARG (args, EFI_LBA);
> + if ( StartingLba == EFI_LBA_LIST_TERMINATOR ) {
> + break;
> + }
> +
> + NumOfLba = VA_ARG (args, UINTN);
> +
> + //
> + // Check input parameters.
> + //
> + if (NumOfLba == 0) {
> + VA_END (args);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if ( ( StartingLba + NumOfLba ) > NumOfBlocks ) {
> + return EFI_INVALID_PARAMETER;
> + }
> + } while ( 1 );
> +
> + VA_END (args);
> +
> + VA_START (args, This);
> + do {
> + StartingLba = VA_ARG (args, EFI_LBA);
> + if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
> + break;
> + }
> +
> + NumOfLba = VA_ARG (args, UINTN);
> +
> + while ( NumOfLba > 0 ) {
> + Status = FvbEraseBlock (FvbDevice->Instance, StartingLba);
> + if ( EFI_ERROR(Status)) {
> + VA_END (args);
> + return Status;
> + }
> + StartingLba ++;
> + NumOfLba --;
> + }
> +
> + } while ( 1 );
> +
> + VA_END (args);
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Writes data beginning at Lba:Offset from FV. The write terminates either
> + when *NumBytes of data have been written, or when a block boundary is
> + reached. *NumBytes is updated to reflect the actual number of bytes
> + written. The write opertion does not include erase. This routine will
> + attempt to write only the specified bytes. If the writes do not stick,
> + it will return an error.
> +
> + @param[in] This Calling context.
> + @param[in] Lba Block in which to begin write.
> + @param[in] Offset Offset in the block at which to begin write.
> + @param[in,out] NumBytes On input, indicates the requested write size.
> On
> + output, indicates the actual number of bytes written
> + @param[in] Buffer Buffer containing source data for the write.
> +
> + @retval EFI_SUCCESS The firmware volume was written successfully.
> + @retval EFI_BAD_BUFFER_SIZE Write attempted across a LBA boundary.
> On output,
> + NumBytes contains the total number of bytes
> + actually written.
> + @retval EFI_ACCESS_DENIED The firmware volume is in the
> WriteDisabled state.
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and
> + could not be written.
> + @retval EFI_INVALID_PARAMETER NumBytes or Buffer are NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolWrite (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> +
> + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> +
> + DEBUG((EFI_D_INFO,
> + "FvbProtocolWrite: Lba: 0x%lx Offset: 0x%x NumBytes: 0x%x, Buffer:
> 0x%x\n",
> + Lba,
> + Offset,
> + *NumBytes,
> + Buffer)
> + );
> +
> + return FvbWriteBlock (FvbDevice->Instance, Lba, Offset, NumBytes,
> Buffer);
> +}
> +
> +
> +/**
> + Reads data beginning at Lba:Offset from FV. The Read terminates either
> + when *NumBytes of data have been read, or when a block boundary is
> + reached. *NumBytes is updated to reflect the actual number of bytes
> + written. The write opertion does not include erase. This routine will
> + attempt to write only the specified bytes. If the writes do not stick,
> + it will return an error.
> +
> + @param[in] This Calling context.
> + @param[in] Lba Block in which to begin write.
> + @param[in] Offset Offset in the block at which to begin write
> + @param[in,out] NumBytes On input, indicates the requested write size.
> On
> + output, indicates the actual number of bytes written.
> + @param[in] Buffer Buffer containing source data for the write.
> +
> +
> +Returns:
> + @retval EFI_SUCCESS The firmware volume was read successfully
> and
> + contents are in Buffer.
> + @retval EFI_BAD_BUFFER_SIZE Read attempted across a LBA boundary.
> On output,
> + NumBytes contains the total number of bytes returned
> + in Buffer.
> + @retval EFI_ACCESS_DENIED The firmware volume is in the
> ReadDisabled state
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and
> + could not be read.
> + @retval EFI_INVALID_PARAMETER NumBytes or Buffer are NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolRead (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + OUT UINT8 *Buffer
> + )
> +{
> +
> + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
> + EFI_STATUS Status;
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> + Status = FvbReadBlock (FvbDevice->Instance, Lba, Offset, NumBytes,
> Buffer);
> + DEBUG((EFI_D_INFO,
> + "FvbProtocolRead: Lba: 0x%lx Offset: 0x%x NumBytes: 0x%x, Buffer:
> 0x%x\n",
> + Lba,
> + Offset,
> + *NumBytes,
> + Buffer)
> + );
> +
> + return Status;
> +}
> +
> +
> +/**
> + Check the integrity of firmware volume header.
> +
> + @param[in] FwVolHeader A pointer to a firmware volume header.
> +
> + @retval TRUE The firmware volume is consistent.
> + @retval FALSE The firmware volume has corrupted.
> +
> +**/
> +BOOLEAN
> +IsFvHeaderValid (
> + IN EFI_PHYSICAL_ADDRESS FvBase,
> + IN CONST EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader
> + )
> +{
> + if (FvBase == PcdGet32(PcdFlashNvStorageVariableBase)) {
> + if (CompareMem (&FwVolHeader->FileSystemGuid,
> &gEfiSystemNvDataFvGuid, sizeof(EFI_GUID)) != 0 ) {
> + return FALSE;
> + }
> + } else {
> + if (CompareMem (&FwVolHeader->FileSystemGuid,
> &gEfiFirmwareFileSystem2Guid, sizeof(EFI_GUID)) != 0 ) {
> + return FALSE;
> + }
> + }
> + if ( (FwVolHeader->Revision != EFI_FVH_REVISION) ||
> + (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
> + (FwVolHeader->FvLength == ((UINTN) -1)) ||
> + ((FwVolHeader->HeaderLength & 0x01 ) !=0) ) {
> + return FALSE;
> + }
> +
> + if (CalculateCheckSum16 ((UINT16 *) FwVolHeader, FwVolHeader-
> >HeaderLength) != 0) {
> + return FALSE;
> + }
> +
> + return TRUE;
> +}
> +
> +
> +/**
> + The function does the necessary initialization work for
> + Firmware Volume Block Driver.
> +
> + @retval EFI_SUCCESS This funtion always return EFI_SUCCESS.
> + It will ASSERT on errors.
> +
> +**/
> +EFI_STATUS
> +FvbInitialize (
> + VOID
> + )
> +{
> + EFI_FW_VOL_INSTANCE *FwhInstance;
> + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
> + EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
> + EFI_FV_BLOCK_MAP_ENTRY *PtrBlockMapEntry;
> + EFI_PHYSICAL_ADDRESS BaseAddress;
> + EFI_STATUS Status;
> + UINTN BufferSize;
> + UINTN TmpHeaderLength;
> + UINTN Idx;
> + UINT32 MaxLbaSize;
> +
> + //
> + // Calculate the total size for all firmware volume block instances.
> + //
> + BufferSize = 0;
> + for (Idx = 0; Idx < 1; Idx++) {
> + FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN)
> mPlatformFvBaseAddress[Idx];
> + BufferSize += (FvHeader->HeaderLength +
> + sizeof (EFI_FW_VOL_INSTANCE) -
> + sizeof (EFI_FIRMWARE_VOLUME_HEADER)
> + );
> + }
> +
> + mFvbModuleGlobal.FvInstance = (EFI_FW_VOL_INSTANCE *)
> AllocateRuntimeZeroPool (BufferSize);
> + ASSERT (NULL != mFvbModuleGlobal.FvInstance);
> +
> +
> + MaxLbaSize = 0;
> + FwhInstance = mFvbModuleGlobal.FvInstance;
> + mFvbModuleGlobal.NumFv = 0;
> +
> + for (Idx = 0; Idx < 1; Idx++) {
> + BaseAddress = mPlatformFvBaseAddress[Idx];
> + FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN)
> BaseAddress;
> +
> + if (!IsFvHeaderValid (BaseAddress, FwVolHeader)) {
> + //
> + // If not valid, get FvbInfo from the information carried in
> + // FVB driver.
> + //
> + DEBUG ((EFI_D_ERROR, "Fvb: FV header @ 0x%lx invalid\n",
> BaseAddress));
> + Status = GetFvbInfo (BaseAddress, &FwVolHeader);
> + ASSERT_EFI_ERROR(Status);
> + //
> + // Write back a healthy FV header.
> + //
> + DEBUG ((EFI_D_ERROR, "FwBlockService.c: Writing back healthy FV
> header\n"));
> + LibFvbFlashDeviceBlockLock ((UINTN)BaseAddress, FwVolHeader-
> >BlockMap->Length, FALSE);
> +
> + Status = LibFvbFlashDeviceBlockErase ((UINTN)BaseAddress,
> FwVolHeader->BlockMap->Length);
> +
> + TmpHeaderLength = (UINTN) FwVolHeader->HeaderLength;
> + Status = LibFvbFlashDeviceWrite (
> + (UINTN)BaseAddress,
> + &TmpHeaderLength,
> + (UINT8 *) FwVolHeader
> + );
> +
> + LibFvbFlashDeviceBlockLock ((UINTN)BaseAddress, FwVolHeader-
> >BlockMap->Length, TRUE);
> +
> + WriteBackInvalidateDataCacheRange (
> + (VOID *) (UINTN) BaseAddress,
> + FwVolHeader->BlockMap->Length
> + );
> +
> + }
> +
> + CopyMem (&(FwhInstance->VolumeHeader), FwVolHeader,
> FwVolHeader->HeaderLength);
> +
> + FwVolHeader = &(FwhInstance->VolumeHeader);
> + FwhInstance->FvBase = (UINTN)BaseAddress;
> +
> + //
> + // Process the block map for each FV.
> + //
> + FwhInstance->NumOfBlocks = 0;
> + for (PtrBlockMapEntry = FwVolHeader->BlockMap; PtrBlockMapEntry-
> >NumBlocks != 0; PtrBlockMapEntry++) {
> + //
> + // Get the maximum size of a block.
> + //
> + if (MaxLbaSize < PtrBlockMapEntry->Length) {
> + MaxLbaSize = PtrBlockMapEntry->Length;
> + }
> + FwhInstance->NumOfBlocks += PtrBlockMapEntry->NumBlocks;
> + }
> +
> + //
> + // Add a FVB Protocol Instance.
> + //
> + mFvbModuleGlobal.NumFv++;
> + InstallFvbProtocol (FwhInstance, mFvbModuleGlobal.NumFv - 1);
> +
> + //
> + // Move on to the next FwhInstance.
> + //
> + FwhInstance = (EFI_FW_VOL_INSTANCE *) ((UINTN)((UINT8
> *)FwhInstance) +
> + FwVolHeader->HeaderLength +
> + (sizeof (EFI_FW_VOL_INSTANCE) - sizeof
> (EFI_FIRMWARE_VOLUME_HEADER)));
> +
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.h
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.h
> new file mode 100644
> index 0000000000..89e0212f98
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.h
> @@ -0,0 +1,182 @@
> +/** @file
> + The header file for Firmware volume block driver.
> +
> +Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef _FW_BLOCK_SERVICE_H
> +#define _FW_BLOCK_SERVICE_H
> +
> +#include <Guid/EventGroup.h>
> +#include <Guid/FirmwareFileSystem2.h>
> +#include <Guid/SystemNvDataGuid.h>
> +#include <Protocol/DevicePath.h>
> +#include <Protocol/FirmwareVolumeBlock.h>
> +
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/CacheMaintenanceLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/FlashDeviceLib.h>
> +#include <Library/DevicePathLib.h>
> +
> +//
> +// Define two helper macro to extract the Capability field or Status field in
> FVB
> +// bit fields.
> +//
> +#define EFI_FVB2_CAPABILITIES (EFI_FVB2_READ_DISABLED_CAP | \
> + EFI_FVB2_READ_ENABLED_CAP | \
> + EFI_FVB2_WRITE_DISABLED_CAP | \
> + EFI_FVB2_WRITE_ENABLED_CAP | \
> + EFI_FVB2_LOCK_CAP \
> + )
> +
> +#define EFI_FVB2_STATUS (EFI_FVB2_READ_STATUS |
> EFI_FVB2_WRITE_STATUS | EFI_FVB2_LOCK_STATUS)
> +
> +
> +typedef struct {
> + UINTN FvBase;
> + UINTN NumOfBlocks;
> + //
> + // Note!!!: VolumeHeader must be the last element
> + // of the structure.
> + //
> + EFI_FIRMWARE_VOLUME_HEADER VolumeHeader;
> +} EFI_FW_VOL_INSTANCE;
> +
> +typedef struct {
> + EFI_FW_VOL_INSTANCE *FvInstance;
> + UINT32 NumFv;
> +} FWB_GLOBAL;
> +
> +//
> +// Fvb Protocol instance data.
> +//
> +#define FVB_DEVICE_FROM_THIS(a) CR(a, EFI_FW_VOL_BLOCK_DEVICE,
> FwVolBlockInstance, FVB_DEVICE_SIGNATURE)
> +#define FVB_EXTEND_DEVICE_FROM_THIS(a) CR(a,
> EFI_FW_VOL_BLOCK_DEVICE, FvbExtension, FVB_DEVICE_SIGNATURE)
> +#define FVB_DEVICE_SIGNATURE SIGNATURE_32('F','V','B','C')
> +
> +typedef struct {
> + MEDIA_FW_VOL_DEVICE_PATH FvDevPath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevPath;
> +} FV_PIWG_DEVICE_PATH;
> +
> +typedef struct {
> + MEMMAP_DEVICE_PATH MemMapDevPath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevPath;
> +} FV_MEMMAP_DEVICE_PATH;
> +
> +typedef struct {
> + UINT32 Signature;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + UINTN Instance;
> + EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL FwVolBlockInstance;
> +} EFI_FW_VOL_BLOCK_DEVICE;
> +
> +EFI_STATUS
> +GetFvbInfo (
> + IN EFI_PHYSICAL_ADDRESS FvBaseAddress,
> + OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo
> + );
> +
> +//
> +// Protocol APIs
> +//
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolGetAttributes (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolSetAttributes (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolGetPhysicalAddress (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + OUT EFI_PHYSICAL_ADDRESS *Address
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolGetBlockSize (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + OUT UINTN *BlockSize,
> + OUT UINTN *NumOfBlocks
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolRead (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + OUT UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolWrite (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbProtocolEraseBlocks (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + ...
> + );
> +
> +EFI_FW_VOL_INSTANCE *
> +GetFvbInstance (
> + IN UINTN Instance
> + );
> +
> +BOOLEAN
> +IsFvHeaderValid (
> + IN EFI_PHYSICAL_ADDRESS FvBase,
> + IN CONST EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader
> + );
> +
> +VOID
> +InstallFvbProtocol (
> + IN EFI_FW_VOL_INSTANCE *FwhInstance,
> + IN UINTN InstanceNum
> + );
> +
> +EFI_STATUS
> +FvbInitialize (
> + VOID
> + );
> +
> +extern FWB_GLOBAL mFvbModuleGlobal;
> +extern EFI_FW_VOL_BLOCK_DEVICE mFvbDeviceTemplate;
> +extern FV_MEMMAP_DEVICE_PATH mFvMemmapDevicePathTemplate;
> +extern FV_PIWG_DEVICE_PATH mFvPIWGDevicePathTemplate;
> +extern UINT32 mPlatformFvBaseAddress[3];
> +
> +#endif
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceDxe.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceDxe.c
> new file mode 100644
> index 0000000000..32aa216728
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceDxe.c
> @@ -0,0 +1,199 @@
> +/** @file
> + Firmware Volume Block Driver for Lakeport Platform.
> +
> + Firmware volume block driver for FWH or SPI device.
> + It depends on which Flash Device Library to be linked with this driver.
> +
> +Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <Library/UefiRuntimeLib.h>
> +#include "FvbService.h"
> +
> +extern FWB_GLOBAL mFvbModuleGlobal;
> +
> +/**
> + Call back function on EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
> +
> + Fixup internal data so that the driver is callable in EFI runtime
> + in virtual mode. Convert the mFvbModuleGlobal date items to there
> + virtual address.
> +
> + @param Event Event whose notification function is being invoked.
> + @param Context The context of the Notification context. Not used in
> + this call back function.
> +
> +**/
> +VOID
> +EFIAPI
> +FvbVirtualddressChangeEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_FW_VOL_INSTANCE *FwhInstance;
> + UINTN Index;
> +
> + //
> + // Convert the base address of all the instances.
> + //
> + for (Index = 0; Index < mFvbModuleGlobal.NumFv; Index++) {
> + FwhInstance = GetFvbInstance (Index);
> + EfiConvertPointer (0, (VOID **) &FwhInstance->FvBase);
> + }
> +
> + EfiConvertPointer (0, (VOID **) &mFvbModuleGlobal.FvInstance);
> +}
> +
> +
> +/**
> + The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol
> + for each FV in the system.
> +
> + @param[in] FwhInstance The pointer to a FW volume instance structure,
> + which contains the information about one FV.
> + @param[in] InstanceNum The instance number which can be used as a ID
> + to locate this FwhInstance in other functions.
> +
> + @retval VOID
> +
> +**/
> +VOID
> +InstallFvbProtocol (
> + IN EFI_FW_VOL_INSTANCE *FwhInstance,
> + IN UINTN InstanceNum
> + )
> +{
> + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
> + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
> + EFI_STATUS Status;
> + EFI_HANDLE FwbHandle;
> + EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *OldFwbInterface;
> +
> + FvbDevice = (EFI_FW_VOL_BLOCK_DEVICE *) AllocateRuntimeCopyPool (
> + sizeof (EFI_FW_VOL_BLOCK_DEVICE),
> + &mFvbDeviceTemplate
> + );
> + ASSERT (FvbDevice != NULL);
> +
> + FvbDevice->Instance = InstanceNum;
> + FwVolHeader = &FwhInstance->VolumeHeader;
> +
> + //
> + // Set up the devicepath.
> + //
> + DEBUG ((EFI_D_INFO, "FwBlockService.c: Setting up DevicePath for
> 0x%lx:\n", FwhInstance->FvBase));
> + if (FwVolHeader->ExtHeaderOffset == 0) {
> + //
> + // FV does not contains extension header, then produce
> MEMMAP_DEVICE_PATH.
> + //
> + FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)
> AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH),
> &mFvMemmapDevicePathTemplate);
> + ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)-
> >MemMapDevPath.StartingAddress = FwhInstance->FvBase;
> + ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)-
> >MemMapDevPath.EndingAddress = FwhInstance->FvBase +
> FwVolHeader->FvLength - 1;
> + } else {
> + FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)
> AllocateRuntimeCopyPool (sizeof (FV_PIWG_DEVICE_PATH),
> &mFvPIWGDevicePathTemplate);
> + CopyGuid (
> + &((FV_PIWG_DEVICE_PATH *)FvbDevice->DevicePath)-
> >FvDevPath.FvName,
> + (GUID *)(UINTN)(FwhInstance->FvBase + FwVolHeader-
> >ExtHeaderOffset)
> + );
> + }
> +
> + //
> + // Find a handle with a matching device path that has supports FW Block
> protocol.
> + //
> + Status = gBS->LocateDevicePath (
> + &gEfiFirmwareVolumeBlockProtocolGuid,
> + &FvbDevice->DevicePath,
> + &FwbHandle
> + );
> + if (EFI_ERROR (Status) ) {
> + //
> + // LocateDevicePath fails so install a new interface and device path.
> + //
> + DEBUG ((EFI_D_INFO, "FwBlockService.c: LocateDevicePath failed, install
> new interface 0x%lx:\n", FwhInstance->FvBase));
> + FwbHandle = NULL;
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &FwbHandle,
> + &gEfiFirmwareVolumeBlockProtocolGuid,
> + &FvbDevice->FwVolBlockInstance,
> + &gEfiDevicePathProtocolGuid,
> + FvbDevice->DevicePath,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> + DEBUG ((EFI_D_INFO, "FwBlockService.c: IMPI FirmwareVolBlockProt,
> DevPath 0x%lx: %r\n", FwhInstance->FvBase, Status));
> +
> + } else if (IsDevicePathEnd (FvbDevice->DevicePath)) {
> + //
> + // Device allready exists, so reinstall the FVB protocol.
> + //
> + DEBUG ((EFI_D_ERROR, "FwBlockService.c: LocateDevicePath succeeded,
> reinstall interface 0x%lx:\n", FwhInstance->FvBase));
> + Status = gBS->HandleProtocol (
> + FwbHandle,
> + &gEfiFirmwareVolumeBlockProtocolGuid,
> + (VOID **) &OldFwbInterface
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gBS->ReinstallProtocolInterface (
> + FwbHandle,
> + &gEfiFirmwareVolumeBlockProtocolGuid,
> + OldFwbInterface,
> + &FvbDevice->FwVolBlockInstance
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + } else {
> + //
> + // There was a FVB protocol on an End Device Path node.
> + //
> + ASSERT (FALSE);
> + }
> +
> +}
> +
> +
> +/**
> + The driver entry point for Firmware Volume Block Driver.
> +
> + The function does the necessary initialization work for
> + Firmware Volume Block Driver.
> +
> + @param[in] ImageHandle The firmware allocated handle for the UEFI
> image.
> + @param[in] SystemTable A pointer to the EFI system table.
> +
> + @retval EFI_SUCCESS This funtion always return EFI_SUCCESS.
> + It will ASSERT on errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +DxeFvbInitialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_EVENT Event;
> +
> + Status = gBS->CreateEventEx (
> + EVT_NOTIFY_SIGNAL,
> + TPL_NOTIFY,
> + FvbVirtualddressChangeEvent,
> + NULL,
> + &gEfiEventVirtualAddressChangeGuid,
> + &Event
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + FvbInitialize ();
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceSmm.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceSmm.c
> new file mode 100644
> index 0000000000..d1360bb90d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceSmm.c
> @@ -0,0 +1,127 @@
> +/** @file
> + SMM Firmware Volume Block Driver for Lakeport Platform.
> +
> + Firmware volume block driver for FWH or SPI device.
> + It depends on which Flash Device Library to be linked with this driver.
> +
> +Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <PiSmm.h>
> +#include <Library/SmmServicesTableLib.h>
> +#include "FvbSmmCommon.h"
> +#include "FvbService.h"
> +
> +/**
> + The function installs EFI_SMM_FIRMWARE_VOLUME_BLOCK protocol
> + for each FV in the system.
> +
> + @param[in] FwhInstance The pointer to a FW volume instance structure,
> + which contains the information about one FV.
> + @param[in] InstanceNum The instance number which can be used as a ID
> + to locate this FwhInstance in other functions.
> +
> + @retval VOID
> +
> +**/
> +VOID
> +InstallFvbProtocol (
> + IN EFI_FW_VOL_INSTANCE *FwhInstance,
> + IN UINTN InstanceNum
> + )
> +{
> + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
> + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
> + EFI_STATUS Status;
> + EFI_HANDLE FvbHandle;
> +
> + FvbDevice = (EFI_FW_VOL_BLOCK_DEVICE *) AllocateRuntimeCopyPool (
> + sizeof (EFI_FW_VOL_BLOCK_DEVICE),
> + &mFvbDeviceTemplate
> + );
> + ASSERT (FvbDevice != NULL);
> +
> + FvbDevice->Instance = InstanceNum;
> + FwVolHeader = &FwhInstance->VolumeHeader;
> +
> + //
> + // Set up the devicepath.
> + //
> + if (FwVolHeader->ExtHeaderOffset == 0) {
> + //
> + // FV does not contains extension header, then produce
> MEMMAP_DEVICE_PATH.
> + //
> + FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)
> AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH),
> &mFvMemmapDevicePathTemplate);
> + ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)-
> >MemMapDevPath.StartingAddress = FwhInstance->FvBase;
> + ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)-
> >MemMapDevPath.EndingAddress = FwhInstance->FvBase +
> FwVolHeader->FvLength - 1;
> + } else {
> + FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)
> AllocateRuntimeCopyPool (sizeof (FV_PIWG_DEVICE_PATH),
> &mFvPIWGDevicePathTemplate);
> + CopyGuid (
> + &((FV_PIWG_DEVICE_PATH *)FvbDevice->DevicePath)-
> >FvDevPath.FvName,
> + (GUID *)(UINTN)(FwhInstance->FvBase + FwVolHeader-
> >ExtHeaderOffset)
> + );
> + }
> +
> + //
> + // Install the SMM Firmware Volume Block Protocol and Device Path
> Protocol.
> + //
> + FvbHandle = NULL;
> + Status = gSmst->SmmInstallProtocolInterface (
> + &FvbHandle,
> + &gEfiSmmFirmwareVolumeBlockProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + &FvbDevice->FwVolBlockInstance
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gSmst->SmmInstallProtocolInterface (
> + &FvbHandle,
> + &gEfiDevicePathProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + FvbDevice->DevicePath
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Notify the Fvb wrapper driver SMM fvb is ready.
> + //
> + FvbHandle = NULL;
> + Status = gBS->InstallProtocolInterface (
> + &FvbHandle,
> + &gEfiSmmFirmwareVolumeBlockProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + &FvbDevice->FwVolBlockInstance
> + );
> +}
> +
> +
> +/**
> + The driver entry point for SMM Firmware Volume Block Driver.
> +
> + The function does the necessary initialization work
> + Firmware Volume Block Driver.
> +
> + @param[in] ImageHandle The firmware allocated handle for the UEFI
> image.
> + @param[in] SystemTable A pointer to the EFI system table.
> +
> + @retval EFI_SUCCESS This funtion always return EFI_SUCCESS.
> + It will ASSERT on errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbSmmInitialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + FvbInitialize ();
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmm.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmm.inf
> new file mode 100644
> index 0000000000..4e33c3b9fb
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmm.inf
> @@ -0,0 +1,82 @@
> +## @file
> +# This driver implement the EFI_SMM_FIRMWARE_VOLUMEN_PROTOCOL.
> +#
> +# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = FvbSmm
> + FILE_GUID = A4EC8ADB-B7A8-47d1-8E52-EC820D0ACF6F
> + MODULE_TYPE = DXE_SMM_DRIVER
> + VERSION_STRING = 1.0
> + PI_SPECIFICATION_VERSION = 0x0001000A
> + ENTRY_POINT = FvbSmmInitialize
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +# VIRTUAL_ADDRESS_MAP_CALLBACK = FvbVirtualddressChangeEvent
> +#
> +
> +[Sources]
> + FvbInfo.c
> + FvbService.h
> + FvbService.c
> + FvbServiceSmm.c
> + FvbSmmCommon.h
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + FlashDeviceLib
> + PcdLib
> + MemoryAllocationLib
> + CacheMaintenanceLib
> + IoLib
> + BaseMemoryLib
> + DebugLib
> + BaseLib
> + UefiLib
> + SmmLib
> + SmmServicesTableLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> +
> +[Guids]
> + gEfiFirmwareFileSystem2Guid # ALWAYS_CONSUMED
> + gEfiSystemNvDataFvGuid # ALWAYS_CONSUMED
> + gEfiEventVirtualAddressChangeGuid
> +
> +[Protocols]
> + gEfiDevicePathProtocolGuid # PROTOCOL ALWAYS_PRODUCED
> + gEfiSmmFirmwareVolumeBlockProtocolGuid # PROTOCOL
> ALWAYS_PRODUCED
> +
> +[FixedPcd]
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase
> +
> +[Pcd]
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +
> +[Depex]
> + gEfiSmmSpiProtocolGuid
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmCommon.h
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmCommon.h
> new file mode 100644
> index 0000000000..236e487111
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmCommon.h
> @@ -0,0 +1,73 @@
> +/** @file
> +
> + The common header file for SMM FVB module and SMM FVB runtime
> Module.
> +
> +Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved. <BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef _SMM_FVB_COMMON_H_
> +#define _SMM_FVB_COMMON_H_
> +
> +#include <Protocol/SmmFirmwareVolumeBlock.h>
> +
> +#define EFI_FUNCTION_GET_ATTRIBUTES 1
> +#define EFI_FUNCTION_SET_ATTRIBUTES 2
> +#define EFI_FUNCTION_GET_PHYSICAL_ADDRESS 3
> +#define EFI_FUNCTION_GET_BLOCK_SIZE 4
> +#define EFI_FUNCTION_READ 5
> +#define EFI_FUNCTION_WRITE 6
> +#define EFI_FUNCTION_ERASE_BLOCKS 7
> +
> +typedef struct {
> + UINTN Function;
> + EFI_STATUS ReturnStatus;
> + UINT8 Data[1];
> +} SMM_FVB_COMMUNICATE_FUNCTION_HEADER;
> +
> +
> +///
> +/// Size of SMM communicate header, without including the payload.
> +///
> +#define SMM_COMMUNICATE_HEADER_SIZE (OFFSET_OF
> (EFI_SMM_COMMUNICATE_HEADER, Data))
> +
> +///
> +/// Size of SMM FVB communicate function header, without including the
> payload.
> +///
> +#define SMM_FVB_COMMUNICATE_HEADER_SIZE (OFFSET_OF
> (SMM_FVB_COMMUNICATE_FUNCTION_HEADER, Data))
> +
> +typedef struct {
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_FVB_ATTRIBUTES_2 Attributes;
> +} SMM_FVB_ATTRIBUTES_HEADER;
> +
> +typedef struct {
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_PHYSICAL_ADDRESS Address;
> +} SMM_FVB_PHYSICAL_ADDRESS_HEADER;
> +
> +typedef struct {
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_LBA Lba;
> + UINTN BlockSize;
> + UINTN NumOfBlocks;
> +} SMM_FVB_BLOCK_SIZE_HEADER;
> +
> +typedef struct {
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_LBA Lba;
> + UINTN Offset;
> + UINTN NumBytes;
> +} SMM_FVB_READ_WRITE_HEADER;
> +
> +typedef struct {
> + EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_LBA StartLba;
> + UINTN NumOfLba;
> +} SMM_FVB_BLOCKS_HEADER;
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.c
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.c
> new file mode 100644
> index 0000000000..e46c65c3fc
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.c
> @@ -0,0 +1,944 @@
> +/** @file
> +
> + Implement the Firmware Volume Block (FVB) services based on SMM FVB
> + module and install FVB protocol.
> +
> +Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved. <BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include "FvbSmmDxe.h"
> +
> +EFI_HANDLE mHandle = NULL;
> +EFI_SMM_COMMUNICATION_PROTOCOL *mSmmCommunication = NULL;
> +
> +//
> +// Template structure used when installing FVB protocol.
> +//
> +EFI_FVB_DEVICE mFvbDeviceTemplate = {
> + FVB_DEVICE_SIGNATURE,
> + NULL,
> + {
> + FvbGetAttributes,
> + FvbSetAttributes,
> + FvbGetPhysicalAddress,
> + FvbGetBlockSize,
> + FvbRead,
> + FvbWrite,
> + FvbEraseBlocks,
> + NULL
> + },
> + NULL
> +};
> +
> +FV_MEMMAP_DEVICE_PATH mFvMemmapDevicePathTemplate = {
> + {
> + {
> + HARDWARE_DEVICE_PATH,
> + HW_MEMMAP_DP,
> + {
> + (UINT8)(sizeof (MEMMAP_DEVICE_PATH)),
> + (UINT8)(sizeof (MEMMAP_DEVICE_PATH) >> 8)
> + }
> + },
> + EfiMemoryMappedIO,
> + (EFI_PHYSICAL_ADDRESS) 0,
> + (EFI_PHYSICAL_ADDRESS) 0,
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> +};
> +
> +FV_PIWG_DEVICE_PATH mFvPIWGDevicePathTemplate = {
> + {
> + {
> + MEDIA_DEVICE_PATH,
> + MEDIA_PIWG_FW_VOL_DP,
> + {
> + (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH)),
> + (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH) >> 8)
> + }
> + },
> + { 0 }
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> +};
> +
> +/**
> + Initialize the communicate buffer using DataSize and Function.
> +
> + The communicate size is: SMM_COMMUNICATE_HEADER_SIZE +
> SMM_VARIABLE_COMMUNICATE_HEADER_SIZE +
> + DataSize.
> +
> + @param[out] CommunicateBuffer The communicate buffer. Caller
> should free it after use.
> + @param[out] DataPtr Points to the data in the communicate buffer.
> Caller should not free it.
> + @param[in] DataSize The payload size.
> + @param[in] Function The function number used to initialize the
> communicate header.
> +
> + @retval EFI_INVALID_PARAMETER The data size is too big.
> + @retval EFI_SUCCESS Find the specified variable.
> +
> +**/
> +EFI_STATUS
> +InitCommunicateBuffer (
> + OUT VOID **CommunicateBuffer,
> + OUT VOID **DataPtr,
> + IN UINTN DataSize,
> + IN UINTN Function
> + )
> +{
> + EFI_SMM_COMMUNICATE_HEADER *SmmCommunicateHeader;
> + SMM_FVB_COMMUNICATE_FUNCTION_HEADER
> *SmmFvbFunctionHeader;
> +
> + //
> + // The whole buffer size: SMM_COMMUNICATE_HEADER_SIZE +
> SMM_FVB_COMMUNICATE_HEADER_SIZE + DataSize.
> + //
> + SmmCommunicateHeader = AllocatePool (DataSize +
> SMM_COMMUNICATE_HEADER_SIZE +
> SMM_FVB_COMMUNICATE_HEADER_SIZE);
> + ASSERT (SmmCommunicateHeader != NULL);
> +
> + //
> + // Prepare data buffer.
> + //
> + CopyGuid (&SmmCommunicateHeader->HeaderGuid,
> &gEfiSmmFirmwareVolumeBlockProtocolGuid);
> + SmmCommunicateHeader->MessageLength = DataSize +
> SMM_FVB_COMMUNICATE_HEADER_SIZE;
> +
> + SmmFvbFunctionHeader =
> (SMM_FVB_COMMUNICATE_FUNCTION_HEADER *)
> SmmCommunicateHeader->Data;
> + SmmFvbFunctionHeader->Function = Function;
> +
> + *CommunicateBuffer = SmmCommunicateHeader;
> + *DataPtr = SmmFvbFunctionHeader->Data;
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Send the data in communicate buffer to SMM.
> +
> + @param[out] SmmCommunicateHeader The communicate buffer.
> + @param[in] DataSize The payload size.
> +
> +**/
> +EFI_STATUS
> +SendCommunicateBuffer (
> + IN EFI_SMM_COMMUNICATE_HEADER *SmmCommunicateHeader,
> + IN UINTN DataSize
> + )
> +{
> + EFI_STATUS Status;
> + UINTN CommSize;
> + SMM_FVB_COMMUNICATE_FUNCTION_HEADER
> *SmmFvbFunctionHeader;
> +
> + CommSize = DataSize + SMM_COMMUNICATE_HEADER_SIZE +
> SMM_FVB_COMMUNICATE_HEADER_SIZE;
> + Status = mSmmCommunication->Communicate (
> + mSmmCommunication,
> + SmmCommunicateHeader,
> + &CommSize
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + SmmFvbFunctionHeader =
> (SMM_FVB_COMMUNICATE_FUNCTION_HEADER *)
> SmmCommunicateHeader->Data;
> + return SmmFvbFunctionHeader->ReturnStatus;
> +}
> +
> +/**
> + This function retrieves the attributes and current settings of the block.
> +
> + @param[in] This Indicates the
> EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param[out] Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the
> attributes
> + and current settings are returned. Type
> EFI_FVB_ATTRIBUTES_2
> + is defined in EFI_FIRMWARE_VOLUME_HEADER.
> +
> + @retval EFI_SUCCESS The firmware volume attributes were
> returned.
> + @retval EFI_INVALID_PARAMETER Attributes is NULL.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbGetAttributes (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + )
> +{
> + EFI_STATUS Status;
> + UINTN PayloadSize;
> + EFI_SMM_COMMUNICATE_HEADER *SmmCommunicateHeader;
> + SMM_FVB_ATTRIBUTES_HEADER *SmmFvbAttributesHeader;
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_FVB_DEVICE *FvbDevice;
> +
> + if (Attributes == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> + SmmFvb = FvbDevice->SmmFvbInstance;
> +
> + //
> + // Initialize the communicate buffer.
> + //
> + PayloadSize = sizeof (SMM_FVB_ATTRIBUTES_HEADER);
> + Status = InitCommunicateBuffer (
> + (VOID **)&SmmCommunicateHeader,
> + (VOID **)&SmmFvbAttributesHeader,
> + PayloadSize,
> + EFI_FUNCTION_GET_ATTRIBUTES
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + SmmFvbAttributesHeader->SmmFvb = SmmFvb;
> + SmmFvbAttributesHeader->Attributes = 0;
> +
> + //
> + // Send data to SMM.
> + //
> + Status = SendCommunicateBuffer (SmmCommunicateHeader,
> PayloadSize);
> +
> + //
> + // Get data from SMM.
> + //
> + *Attributes = SmmFvbAttributesHeader->Attributes;
> + FreePool (SmmCommunicateHeader);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Sets Volume attributes. No polarity translations are done.
> +
> + @param[in] This Calling context.
> + @param[out] Attributes Output buffer which contains attributes.
> +
> + @retval EFI_SUCCESS Set the Attributes successfully.
> + @retval EFI_INVALID_PARAMETER Attributes is NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbSetAttributes (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + )
> +{
> + EFI_STATUS Status;
> + UINTN PayloadSize;
> + EFI_SMM_COMMUNICATE_HEADER *SmmCommunicateHeader;
> + SMM_FVB_ATTRIBUTES_HEADER *SmmFvbAttributesHeader;
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_FVB_DEVICE *FvbDevice;
> +
> + if (Attributes == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> + SmmFvb = FvbDevice->SmmFvbInstance;
> +
> + //
> + // Initialize the communicate buffer.
> + //
> + PayloadSize = sizeof (SMM_FVB_ATTRIBUTES_HEADER);
> + Status = InitCommunicateBuffer (
> + (VOID **)&SmmCommunicateHeader,
> + (VOID **)&SmmFvbAttributesHeader,
> + PayloadSize,
> + EFI_FUNCTION_SET_ATTRIBUTES
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + SmmFvbAttributesHeader->SmmFvb = SmmFvb;
> + SmmFvbAttributesHeader->Attributes = *Attributes;
> +
> + //
> + // Send data to SMM.
> + //
> + Status = SendCommunicateBuffer (SmmCommunicateHeader,
> PayloadSize);
> +
> + //
> + // Get data from SMM.
> + //
> + *Attributes = SmmFvbAttributesHeader->Attributes;
> + FreePool (SmmCommunicateHeader);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Retrieves the physical address of the FVB instance.
> +
> + @param[in] SmmFvb A pointer to
> EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL.
> + @param[out] Address Output buffer containing the address.
> +
> + @retval EFI_SUCCESS Get the address successfully.
> + @retval Others Failed to get address.
> +
> +**/
> +EFI_STATUS
> +GetPhysicalAddress (
> + IN EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb,
> + OUT EFI_PHYSICAL_ADDRESS *Address
> + )
> +{
> + EFI_STATUS Status;
> + UINTN PayloadSize;
> + EFI_SMM_COMMUNICATE_HEADER *SmmCommunicateHeader;
> + SMM_FVB_PHYSICAL_ADDRESS_HEADER
> *SmmFvbPhysicalAddressHeader;
> +
> + //
> + // Initialize the communicate buffer.
> + //
> + PayloadSize = sizeof (SMM_FVB_PHYSICAL_ADDRESS_HEADER);
> + Status = InitCommunicateBuffer (
> + (VOID **)&SmmCommunicateHeader,
> + (VOID **)&SmmFvbPhysicalAddressHeader,
> + PayloadSize,
> + EFI_FUNCTION_GET_PHYSICAL_ADDRESS
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + SmmFvbPhysicalAddressHeader->SmmFvb = SmmFvb;
> + SmmFvbPhysicalAddressHeader->Address = 0;
> +
> + //
> + // Send data to SMM.
> + //
> + Status = SendCommunicateBuffer (SmmCommunicateHeader,
> PayloadSize);
> +
> + //
> + // Get data from SMM.
> + //
> + *Address = SmmFvbPhysicalAddressHeader->Address;
> + FreePool (SmmCommunicateHeader);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Retrieves the physical address of the FVB instance.
> +
> + @param[in] This A pointer to
> EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL.
> + @param[out] Address Output buffer containing the address.
> +
> + @retval EFI_SUCCESS Get the address successfully.
> + @retval Others Failed to get the address.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbGetPhysicalAddress (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + OUT EFI_PHYSICAL_ADDRESS *Address
> + )
> +{
> + EFI_STATUS Status;
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_FVB_DEVICE *FvbDevice;
> +
> + if (Address == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> + SmmFvb = FvbDevice->SmmFvbInstance;
> +
> + Status = GetPhysicalAddress (SmmFvb, Address);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Retrieve the size of a logical block.
> +
> + @param[in] This Calling context.
> + @param[in] Lba Indicates which block to return the size for.
> + @param[out] BlockSize A pointer to a caller allocated UINTN in which
> + the size of the block is returned.
> + @param[out] NumOfBlocks A pointer to a caller allocated UINTN in which
> the
> + number of consecutive blocks starting with Lba is
> + returned. All blocks in this range have a size of
> + BlockSize.
> +
> + @retval EFI_SUCCESS Get BlockSize and NumOfBlocks successfully.
> + @retval EFI_INVALID_PARAMETER BlockSize or NumOfBlocks are NULL.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbGetBlockSize (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + OUT UINTN *BlockSize,
> + OUT UINTN *NumOfBlocks
> + )
> +{
> + EFI_STATUS Status;
> + UINTN PayloadSize;
> + EFI_SMM_COMMUNICATE_HEADER *SmmCommunicateHeader;
> + SMM_FVB_BLOCK_SIZE_HEADER *SmmFvbBlockSizeHeader;
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_FVB_DEVICE *FvbDevice;
> +
> + if ((BlockSize == NULL) || (NumOfBlocks == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> + SmmFvb = FvbDevice->SmmFvbInstance;
> +
> + //
> + // Initialize the communicate buffer.
> + //
> + PayloadSize = sizeof (SMM_FVB_BLOCK_SIZE_HEADER);
> + Status = InitCommunicateBuffer (
> + (VOID **)&SmmCommunicateHeader,
> + (VOID **)&SmmFvbBlockSizeHeader,
> + PayloadSize,
> + EFI_FUNCTION_GET_BLOCK_SIZE
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + SmmFvbBlockSizeHeader->SmmFvb = SmmFvb;
> + SmmFvbBlockSizeHeader->Lba = Lba;
> +
> + //
> + // Send data to SMM.
> + //
> + Status = SendCommunicateBuffer (SmmCommunicateHeader,
> PayloadSize);
> +
> + //
> + // Get data from SMM.
> + //
> + *BlockSize = SmmFvbBlockSizeHeader->BlockSize;
> + *NumOfBlocks = SmmFvbBlockSizeHeader->NumOfBlocks;
> + FreePool (SmmCommunicateHeader);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Reads data beginning at Lba:Offset from FV. The Read terminates either
> + when *NumBytes of data have been read, or when a block boundary is
> + reached. *NumBytes is updated to reflect the actual number of bytes
> + written. The write opertion does not include erase. This routine will
> + attempt to write only the specified bytes. If the writes do not stick,
> + it will return an error.
> +
> + @param[in] This Calling context
> + @param[in] Lba Block in which to begin write
> + @param[in] Offset Offset in the block at which to begin write
> + @param[in,out] NumBytes On input, indicates the requested write size.
> On
> + output, indicates the actual number of bytes written
> + @param[in] Buffer Buffer containing source data for the write.
> +
> + @retval EFI_SUCCESS The firmware volume was read successfully
> and
> + contents are in Buffer.
> + @retval EFI_BAD_BUFFER_SIZE Read attempted across a LBA boundary.
> On output,
> + NumBytes contains the total number of bytes returned
> + in Buffer.
> + @retval EFI_ACCESS_DENIED The firmware volume is in the
> ReadDisabled state
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and
> + could not be read.
> + @retval EFI_INVALID_PARAMETER NumBytes or Buffer are NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbRead (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + OUT UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINTN PayloadSize;
> + EFI_SMM_COMMUNICATE_HEADER *SmmCommunicateHeader;
> + SMM_FVB_READ_WRITE_HEADER *SmmFvbReadWriteHeader;
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_FVB_DEVICE *FvbDevice;
> +
> + if ((NumBytes == NULL) || (Buffer == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> + SmmFvb = FvbDevice->SmmFvbInstance;
> +
> + //
> + // Initialize the communicate buffer.
> + //
> + PayloadSize = sizeof (SMM_FVB_READ_WRITE_HEADER) + *NumBytes;
> + Status = InitCommunicateBuffer (
> + (VOID **)&SmmCommunicateHeader,
> + (VOID **)&SmmFvbReadWriteHeader,
> + PayloadSize, EFI_FUNCTION_READ
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + SmmFvbReadWriteHeader->SmmFvb = SmmFvb;
> + SmmFvbReadWriteHeader->Lba = Lba;
> + SmmFvbReadWriteHeader->Offset = Offset;
> + SmmFvbReadWriteHeader->NumBytes = *NumBytes;
> +
> + //
> + // Send data to SMM.
> + //
> + Status = SendCommunicateBuffer (SmmCommunicateHeader,
> PayloadSize);
> +
> + //
> + // Get data from SMM.
> + //
> + *NumBytes = SmmFvbReadWriteHeader->NumBytes;
> + if (!EFI_ERROR (Status)) {
> + CopyMem (Buffer, (UINT8 *)(SmmFvbReadWriteHeader + 1),
> *NumBytes);
> + }
> + FreePool (SmmCommunicateHeader);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Writes data beginning at Lba:Offset from FV. The write terminates either
> + when *NumBytes of data have been written, or when a block boundary is
> + reached. *NumBytes is updated to reflect the actual number of bytes
> + written. The write opertion does not include erase. This routine will
> + attempt to write only the specified bytes. If the writes do not stick,
> + it will return an error.
> +
> + @param[in] This Calling context.
> + @param[in] Lba Block in which to begin write.
> + @param[in] Offset Offset in the block at which to begin write.
> + @param[in,out] NumBytes On input, indicates the requested write size.
> On
> + output, indicates the actual number of bytes written.
> + @param[in] Buffer Buffer containing source data for the write.
> +
> + @retval EFI_SUCCESS The firmware volume was written successfully.
> + @retval EFI_BAD_BUFFER_SIZE Write attempted across a LBA boundary.
> On output,
> + NumBytes contains the total number of bytes
> + actually written.
> + @retval EFI_ACCESS_DENIED The firmware volume is in the
> WriteDisabled state.
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and
> + could not be written.
> + @retval EFI_INVALID_PARAMETER NumBytes or Buffer are NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbWrite (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINTN PayloadSize;
> + EFI_SMM_COMMUNICATE_HEADER *SmmCommunicateHeader;
> + SMM_FVB_READ_WRITE_HEADER *SmmFvbReadWriteHeader;
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_FVB_DEVICE *FvbDevice;
> +
> + if ((NumBytes == NULL) || (Buffer == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> + SmmFvb = FvbDevice->SmmFvbInstance;
> +
> + //
> + // Initialize the communicate buffer.
> + //
> + PayloadSize = sizeof (SMM_FVB_READ_WRITE_HEADER) + *NumBytes;
> + Status = InitCommunicateBuffer (
> + (VOID **)&SmmCommunicateHeader,
> + (VOID **)&SmmFvbReadWriteHeader,
> + PayloadSize,
> + EFI_FUNCTION_WRITE
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + SmmFvbReadWriteHeader->SmmFvb = SmmFvb;
> + SmmFvbReadWriteHeader->Lba = Lba;
> + SmmFvbReadWriteHeader->Offset = Offset;
> + SmmFvbReadWriteHeader->NumBytes = *NumBytes;
> + CopyMem ((UINT8 *)(SmmFvbReadWriteHeader + 1), Buffer, *NumBytes);
> +
> + //
> + // Send data to SMM.
> + //
> + Status = SendCommunicateBuffer (SmmCommunicateHeader,
> PayloadSize);
> +
> + //
> + // Get data from SMM.
> + //
> + *NumBytes = SmmFvbReadWriteHeader->NumBytes;
> + FreePool (SmmCommunicateHeader);
> +
> + return Status;
> +}
> +
> +
> +/**
> + The EraseBlock() function erases NumOfLba blocks started from
> StartingLba.
> +
> + @param[in] This Calling context.
> + @param[in] StartingLba Starting LBA followed to erase.
> + @param[in] NumOfLba Number of block to erase.
> +
> + @retval EFI_SUCCESS The erase request was successfully completed.
> + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled
> state.
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and
> + could not be written. Firmware device may have been
> + partially erased.
> +
> +**/
> +EFI_STATUS
> +EraseBlock (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA StartingLba,
> + IN UINTN NumOfLba
> + )
> +{
> + EFI_STATUS Status;
> + UINTN PayloadSize;
> + EFI_SMM_COMMUNICATE_HEADER *SmmCommunicateHeader;
> + SMM_FVB_BLOCKS_HEADER *SmmFvbBlocksHeader;
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> + EFI_FVB_DEVICE *FvbDevice;
> +
> + FvbDevice = FVB_DEVICE_FROM_THIS (This);
> + SmmFvb = FvbDevice->SmmFvbInstance;
> +
> + //
> + // Initialize the communicate buffer.
> + //
> + PayloadSize = sizeof (SMM_FVB_BLOCKS_HEADER);
> + Status = InitCommunicateBuffer (
> + (VOID **)&SmmCommunicateHeader,
> + (VOID **)&SmmFvbBlocksHeader,
> + PayloadSize,
> + EFI_FUNCTION_ERASE_BLOCKS
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + SmmFvbBlocksHeader->SmmFvb = SmmFvb;
> + SmmFvbBlocksHeader->StartLba = StartingLba;
> + SmmFvbBlocksHeader->NumOfLba = NumOfLba;
> +
> + //
> + // Send data to SMM.
> + //
> + Status = SendCommunicateBuffer (SmmCommunicateHeader,
> PayloadSize);
> +
> + //
> + // Get data from SMM.
> + //
> + FreePool (SmmCommunicateHeader);
> +
> + return Status;
> +}
> +
> +
> +/**
> + The EraseBlocks() function erases one or more blocks as denoted by the
> + variable argument list. The entire parameter list of blocks must be verified
> + prior to erasing any blocks. If a block is requested that does not exist
> + within the associated firmware volume (it has a larger index than the last
> + block of the firmware volume), the EraseBlock() function must return
> + EFI_INVALID_PARAMETER without modifying the contents of the firmware
> volume.
> +
> + @param[in] This Calling context/
> + @param[in] ... Starting LBA followed by Number of Lba to erase.
> + a -1 to terminate the list.
> +/
> + @retval EFI_SUCCESS The erase request was successfully completed
> + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled
> state/
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and
> + could not be written. Firmware device may have been
> + partially erased/
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbEraseBlocks (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + ...
> + )
> +{
> + EFI_STATUS Status;
> + VA_LIST Marker;
> + EFI_LBA StartingLba;
> + UINTN NumOfLba;
> +
> + Status = EFI_SUCCESS;
> +
> + //
> + // Check the parameter.
> + //
> + VA_START (Marker, This);
> + do {
> + StartingLba = VA_ARG (Marker, EFI_LBA);
> + if (StartingLba == EFI_LBA_LIST_TERMINATOR ) {
> + break;
> + }
> +
> + NumOfLba = VA_ARG (Marker, UINTN);
> + if (NumOfLba == 0) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + } while ( 1 );
> + VA_END (Marker);
> +
> + //
> + // Erase the blocks.
> + //
> + VA_START (Marker, This);
> + do {
> + StartingLba = VA_ARG (Marker, EFI_LBA);
> + if (StartingLba == EFI_LBA_LIST_TERMINATOR ) {
> + break;
> + }
> + NumOfLba = VA_ARG (Marker, UINTN);
> + Status = EraseBlock (This, StartingLba, NumOfLba);
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + } while ( 1 );
> + VA_END (Marker);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Install the FVB protocol which based on SMM FVB protocol.
> +
> + @param[in] SmmFvb The SMM FVB protocol.
> +
> +**/
> +VOID
> +InstallFvb (
> + IN EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE FvbHandle;
> + EFI_FVB_DEVICE *FvbDevice;
> + EFI_FIRMWARE_VOLUME_HEADER *VolumeHeader;
> + EFI_PHYSICAL_ADDRESS Address;
> + EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *OldFvbInterface;
> +
> + FvbDevice = AllocateRuntimeCopyPool (sizeof (EFI_FVB_DEVICE),
> &mFvbDeviceTemplate);
> + ASSERT (FvbDevice != NULL);
> + FvbDevice->SmmFvbInstance = SmmFvb;
> +
> + Status = gBS->LocateProtocol (
> + &gEfiSmmCommunicationProtocolGuid,
> + NULL,
> + (VOID **) &mSmmCommunication
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = GetPhysicalAddress (SmmFvb, &Address);
> + ASSERT_EFI_ERROR (Status);
> +
> + VolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN)Address;
> +
> + //
> + // Set up the devicepath.
> + //
> + if (VolumeHeader->ExtHeaderOffset == 0) {
> + //
> + // FV does not contains extension header, then produce
> MEMMAP_DEVICE_PATH.
> + //
> + FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)
> AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH),
> &mFvMemmapDevicePathTemplate);
> + ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)-
> >MemMapDevPath.StartingAddress = (UINTN)Address;
> + ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)-
> >MemMapDevPath.EndingAddress = (UINTN)Address + VolumeHeader-
> >FvLength - 1;
> + } else {
> + FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)
> AllocateRuntimeCopyPool (sizeof (FV_PIWG_DEVICE_PATH),
> &mFvPIWGDevicePathTemplate);
> + CopyGuid (
> + &((FV_PIWG_DEVICE_PATH *)FvbDevice->DevicePath)-
> >FvDevPath.FvName,
> + (GUID *)(UINTN)((UINTN)Address + VolumeHeader->ExtHeaderOffset)
> + );
> + }
> +
> + //
> + // Find a handle with a matching device path that has supports FW Block
> protocol.
> + //
> + Status = gBS->LocateDevicePath (
> + &gEfiFirmwareVolumeBlockProtocolGuid,
> + &FvbDevice->DevicePath,
> + &FvbHandle
> + );
> + if (EFI_ERROR (Status) ) {
> + //
> + // LocateDevicePath fails so install a new interface and device path.
> + //
> + FvbHandle = NULL;
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &FvbHandle,
> + &gEfiFirmwareVolumeBlockProtocolGuid,
> + &FvbDevice->FvbInstance,
> + &gEfiDevicePathProtocolGuid,
> + FvbDevice->DevicePath,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> + } else if (IsDevicePathEnd (FvbDevice->DevicePath)) {
> + //
> + // Device allready exists, so reinstall the FVB protocol.
> + //
> + Status = gBS->HandleProtocol (
> + FvbHandle,
> + &gEfiFirmwareVolumeBlockProtocolGuid,
> + (VOID **) &OldFvbInterface
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gBS->ReinstallProtocolInterface (
> + FvbHandle,
> + &gEfiFirmwareVolumeBlockProtocolGuid,
> + OldFvbInterface,
> + &FvbDevice->FvbInstance
> + );
> + ASSERT_EFI_ERROR (Status);
> + } else {
> + //
> + // There was a FVB protocol on an End Device Path node.
> + //
> + ASSERT (FALSE);
> + }
> +}
> +
> +
> +/**
> + SMM Firmware Volume Block Protocol notification event handler.
> +
> + Discover NV Variable Store and install Variable Write Arch Protocol.
> +
> + @param[in] Event Event whose notification function is being invoked.
> + @param[in] Context Pointer to the notification function's context.
> +**/
> +VOID
> +EFIAPI
> +SmmFvbReady (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE *HandleBuffer;
> + UINTN HandleCount;
> + UINTN Index;
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvb;
> +
> + //
> + // Locate all handles of Smm Fvb protocol.
> + //
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiSmmFirmwareVolumeBlockProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> + if (EFI_ERROR (Status)) {
> + return ;
> + }
> +
> + //
> + // Install FVB protocol.
> + //
> + for (Index = 0; Index < HandleCount; Index++) {
> + SmmFvb = NULL;
> + Status = gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gEfiSmmFirmwareVolumeBlockProtocolGuid,
> + (VOID **) &SmmFvb
> + );
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> +
> + InstallFvb (SmmFvb);
> + }
> +
> + FreePool (HandleBuffer);
> +}
> +
> +
> +/**
> + The driver entry point for Firmware Volume Block Driver.
> +
> + The function does the necessary initialization work
> + Firmware Volume Block Driver.
> +
> + @param[in] ImageHandle The firmware allocated handle for the UEFI
> image.
> + @param[in] SystemTable A pointer to the EFI system table.
> +
> + @retval EFI_SUCCESS This funtion always return EFI_SUCCESS.
> + It will ASSERT on errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbSmmDxeInitialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + VOID *SmmFvbRegistration;
> +
> + //
> + // Smm FVB driver is ready.
> + //
> + EfiCreateProtocolNotifyEvent (
> + &gEfiSmmFirmwareVolumeBlockProtocolGuid,
> + TPL_CALLBACK,
> + SmmFvbReady,
> + NULL,
> + &SmmFvbRegistration
> + );
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.h
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.h
> new file mode 100644
> index 0000000000..9edb1bcaf0
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.h
> @@ -0,0 +1,232 @@
> +/** @file
> +
> + The internal header file includes the common header files, defines
> + internal structure and functions used by FVB module.
> +
> +Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved. <BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef _SMM_FVB_DXE_H_
> +#define _SMM_FVB_DXE_H_
> +
> +#include <PiDxe.h>
> +
> +#include <Protocol/SmmFirmwareVolumeBlock.h>
> +#include <Protocol/SmmCommunication.h>
> +
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/DevicePathLib.h>
> +
> +#include <Guid/EventGroup.h>
> +#include "FvbSmmCommon.h"
> +
> +#define FVB_DEVICE_SIGNATURE SIGNATURE_32 ('F', 'V', 'B', 'S')
> +#define FVB_DEVICE_FROM_THIS(a) CR (a, EFI_FVB_DEVICE,
> FvbInstance, FVB_DEVICE_SIGNATURE)
> +
> +typedef struct {
> + MEDIA_FW_VOL_DEVICE_PATH FvDevPath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevPath;
> +} FV_PIWG_DEVICE_PATH;
> +
> +typedef struct {
> + MEMMAP_DEVICE_PATH MemMapDevPath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevPath;
> +} FV_MEMMAP_DEVICE_PATH;
> +
> +typedef struct {
> + UINTN Signature;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL FvbInstance;
> + EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL *SmmFvbInstance;
> +} EFI_FVB_DEVICE;
> +
> +/**
> + This function retrieves the attributes and current settings of the block.
> +
> + @param[in] This Indicates the
> EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param[out] Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the
> attributes
> + and current settings are returned. Type
> EFI_FVB_ATTRIBUTES_2
> + is defined in EFI_FIRMWARE_VOLUME_HEADER.
> +
> + @retval EFI_SUCCESS The firmware volume attributes were returned.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbGetAttributes (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + );
> +
> +
> + /**
> + Sets Volume attributes. No polarity translations are done.
> +
> + @param[in] This Calling context.
> + @param[out] Attributes Output buffer which contains attributes.
> +
> + @retval EFI_SUCCESS The function always return successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbSetAttributes (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + );
> +
> +
> +/**
> + Retrieves the physical address of the device.
> +
> + @param[in] This A pointer to
> EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL.
> + @param[out] Address Output buffer containing the address.
> +
> + @retval EFI_SUCCESS The function always return successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbGetPhysicalAddress (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + OUT EFI_PHYSICAL_ADDRESS *Address
> + );
> +
> +
> +/**
> + Retrieve the size of a logical block.
> +
> + @param[in] This Calling context.
> + @param[in] Lba Indicates which block to return the size for.
> + @param[out] BlockSize A pointer to a caller allocated UINTN in which
> + the size of the block is returned.
> + @param[out] NumOfBlocks A pointer to a caller allocated UINTN in which
> the
> + number of consecutive blocks starting with Lba is
> + returned. All blocks in this range have a size of
> + BlockSize.
> +
> + @retval EFI_SUCCESS The function always return successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbGetBlockSize (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + OUT UINTN *BlockSize,
> + OUT UINTN *NumOfBlocks
> + );
> +
> +
> +/**
> + Reads data beginning at Lba:Offset from FV. The Read terminates either
> + when *NumBytes of data have been read, or when a block boundary is
> + reached. *NumBytes is updated to reflect the actual number of bytes
> + written. The write opertion does not include erase. This routine will
> + attempt to write only the specified bytes. If the writes do not stick,
> + it will return an error.
> +
> + @param[in] This Calling context.
> + @param[in] Lba Block in which to begin write.
> + @param[in] Offset Offset in the block at which to begin write
> + @param[in,out] NumBytes On input, indicates the requested write size.
> On
> + output, indicates the actual number of bytes written
> + @param[in] Buffer Buffer containing source data for the write.
> +
> + @retval EFI_SUCCESS The firmware volume was read successfully
> and
> + contents are in Buffer
> + @retval EFI_BAD_BUFFER_SIZE Read attempted across a LBA boundary.
> On output,
> + NumBytes contains the total number of bytes returned
> + in Buffer
> + @retval EFI_ACCESS_DENIED The firmware volume is in the
> ReadDisabled state
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and
> + could not be read
> + @retval EFI_INVALID_PARAMETER NumBytes or Buffer are NULL
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbRead (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + OUT UINT8 *Buffer
> + );
> +
> +
> +/**
> + Writes data beginning at Lba:Offset from FV. The write terminates either
> + when *NumBytes of data have been written, or when a block boundary is
> + reached. *NumBytes is updated to reflect the actual number of bytes
> + written. The write opertion does not include erase. This routine will
> + attempt to write only the specified bytes. If the writes do not stick,
> + it will return an error.
> +
> + @param[in] This Calling context.
> + @param[in] Lba Block in which to begin write.
> + @param[in] Offset Offset in the block at which to begin write.
> + @param[in,out] NumBytes On input, indicates the requested write size.
> On
> + output, indicates the actual number of bytes written
> + @param[in] Buffer Buffer containing source data for the write.
> +
> + @retval EFI_SUCCESS The firmware volume was written successfully
> + @retval EFI_BAD_BUFFER_SIZE Write attempted across a LBA boundary.
> On output,
> + NumBytes contains the total number of bytes
> + actually written.
> + @retval EFI_ACCESS_DENIED The firmware volume is in the
> WriteDisabled state
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and
> + could not be written.
> + @retval EFI_INVALID_PARAMETER NumBytes or Buffer are NULL.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbWrite (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + );
> +
> +
> +/**
> + The EraseBlock() function erases one or more blocks as denoted by the
> + variable argument list. The entire parameter list of blocks must be verified
> + prior to erasing any blocks. If a block is requested that does not exist
> + within the associated firmware volume (it has a larger index than the last
> + block of the firmware volume), the EraseBlock() function must return
> + EFI_INVALID_PARAMETER without modifying the contents of the firmware
> volume.
> +
> + @param[in] This Calling context.
> + @param[in] ... Starting LBA followed by Number of Lba to erase.
> + a -1 to terminate the list.
> +
> + @retval EFI_SUCCESS The erase request was successfully completed.
> + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled
> state
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and
> + could not be written. Firmware device may have been
> + partially erased.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbEraseBlocks (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
> + ...
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.inf
> new file mode 100644
> index 0000000000..aa2b63fe13
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.inf
> @@ -0,0 +1,50 @@
> +## @file
> +# Component description file for Firmware Volume Block module.
> +#
> +# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = FvbSmmDxe
> + FILE_GUID = 9E8AD3F4-383D-4ec3-816E-7A4749371290
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = FvbSmmDxeInitialize
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +[Sources]
> + FvbSmmDxe.c
> + FvbSmmDxe.h
> + FvbSmmCommon.h
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + UefiBootServicesTableLib
> + DebugLib
> + DxeServicesTableLib
> + UefiDriverEntryPoint
> + PcdLib
> +
> +[Protocols]
> + gEfiFirmwareVolumeBlockProtocolGuid ## ALWAYS_PRODUCES
> + gEfiSmmCommunicationProtocolGuid
> + gEfiSmmFirmwareVolumeBlockProtocolGuid
> +
> +[Depex]
> + gEfiSmmCommunicationProtocolGuid
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/GenBiosId
> b/Platform/Intel/Vlv2TbltDevicePkg/GenBiosId
> new file mode 100755
> index
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> z>|bI0M|<AN+~Zl8u{^bz+dVZScT9j(;(+4D)~;o0J=rC&KH{6?nPt at X7G3*Cd1Q
> Il
> zyt<+=qyhMvp1l1w4yfZq*MlBrBN)FuM;7TgLY=M~iF)cspXb>zdte&<OS8D_*v
> t8{
> z;k>o1;Ujgf8)^46WtMyB1d5HcoPYF36ipv>t^FkRPI|IV+RDvySQ{Jr at W@D=$K
> gQX
> zJh`9m?dh4k^~L8|3XP?6T7GJz99605v^*q^jXBTxalFrG<FZfkOwY~Gh4-
> 8l5wRjJ
> z62g~A#1lGS%p$QqJrcuvmmZ2l&2{?X<b~p{UWgZD0twS^Q7E3W=1O(M2K~`
> UP!Ggo
> zp-7)>u7~1 at e!r!(wE1IKSh{?7`*h>hjxAgDj&@zDH-
> qaCT)V0_67wg9l)fUHZXs<j
> zW37>RvLmRctVlFs4K3FP%|tR1kFC=O8@%;;{hF2aO)FQ`*RR%f=xmD*3?(9cV
> M|{c
> zSf;ajx!w`8%&6WLPYlEp=vqAH)mx%bU5X|3gqbuGgJ#ex+xH~>eF(~Dr#Zf at h
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> C*A0
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> TQ+X#nnfL(ffm=V
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> UzxIGz|K8
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> fD
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> |r#|
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> zyzq01q%7m8D9?<QppWj=+<f=AXH0Yd`jdS85WX?vPvPS2uj9KJ=m}uH{7oYB4
> |P0i
> z;`6ple6O9x8!^wJyO8-_F(3KM$aT=maxEyoZ at Q8B-
> JBG!|MAH*KA3>gmouPG0HgSS
> zPW)zWH~M$j`Uv^FVa@#|<R!>!kk=z`Lk=MiBJV@~Hu6E_r;(2$+dBRb^>pwp
> xx=H2
> zx&OQc?8R4H^^Y|y&DPi)Ql<@UZR_-<J-w-
> zm0G!pFWqsy(YwZb^@@g+tX#cJVIjQ9
> zp?=HX3u+}44cjGr;x!Wk!W)ZQrnjZFV}<4KE1<qu%G;ZY;M091D7-{re=;n*!J!!R
> zDQYDYr|=d(2N>Wb%qZnmVIXP=ZzLAMuVwDSZwLUac+hY8h1U!lp at hHRG{
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> z$YZ)3nST$boV-
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> odYr{5G~3XLqVu)3nBm
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> 1Yqh
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> zxF_qZDNKOkU^u#j>#}nt=iJ3Lj9 at Zug#EE#)D-
> ykh}S8rJ6?!a>HXZ|MOvpqM{pS5
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> zz6%or?`4GnmUn(JWun~}ovoI?e?S-;2aPVXFOtOTXj{~uOqxkC+b21-
> 3Kx={cGSn@
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>
> literal 0
> HcmV?d00001
>
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/GenBiosId.exe
> b/Platform/Intel/Vlv2TbltDevicePkg/GenBiosId.exe
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..323b87c444915b173b7f32d54
> 81c67e4471b047b
> GIT binary patch
> literal 384000
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> 8;ig<``RA&^uM4^+Z
> zOpeo1B`vo0Dpzl>ZS5^>siFlMUL;_#jg<D%mRo~QuI^z{jT$A;$UNWg+UJ}(LxR
> 2c
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> zHr9`Lef)-kxv!6(Z!W&Ca>>2-
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> zwBoyQ at vSE79*@$7kYUU%C^FPd$$AH-%P1-
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> zQH)>w=X at KL!!)yS4}4oLfUL*L^6h@{rqRB)*f>|NKK-
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> z1BF at qOJ9j=b8c72utEWAjxVh4I1$j>{fYM2Nme9a&GI*xl?9g>YTgNQKQl(X?5
> SSL
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> `{
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> zi_`=MVG$6XN`!XT2f%mfVVfX)&9^8iS3p=~?jyo3BK$9re7lDa5n<W?A=R3t7kL
> oc
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> z*=L_A!{y3^50~bLXrl?jQH&p9^~F<!v8lEfP^D38?g%hqOi~HngT^2`!s?r%_WZ
> Wu
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> }EJ^SKY3StvRc1KU&
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> UC+nu%0ie
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> zO?tnuIrUhWAyg2gI}*k6U?X^D&;i>>J!wTY!gYu@!!;OZuKU<_P#SnqsD7!P0m
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> zgF-
> `U6s)XzVPmz2asyFd0ZKu`0 at M*SL!+4Lpm<N)W~Ubrv`OkZFA5E*QLwT~xhRf
> +
> zM-
> memjxPNTKVa3d2H~ngom@^re6AbRovhz!MRw}tYA~@zWOHX&J$;kFB}3ce
> &D*ol
> z@%TI%J<W=2-
> *N;|nC<bdGq!XMEAq8H<GT#L)&>sEh9!!dNgG<jRh at 5j9tm#V3OzbA
> zuX_FVEr*NINc^ocw!Ag0s4OMbBkNgxy;KjaZ=F-
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> z+-
> )7=(=jyf^@DndX0Omp#?g#`J(|kGy)8m>$Dt#l31OcFJ)wDzAk<xlp}8(ZbDc+X
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> zcl3mVXg$#CP6}%9+iE^bFiuJ=$LY3q_05x{7K+x2t!TpM4y#1l9VKmZp{Mm%V
> wE_v
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> zu*XzcxRrknX<9uprd8}G3DDeoNPwpCuQ9T9v(6CBPLF11wk=dqgKqYN7 at B97
> qlt<-
> z-QEAcF at i?GG5-BUe~9M$goKrS*s4ik`)h~{tV^d+4F;bgt6-rFpA<}@-
> QoUQp+3lC
> zR$@7usA|)1ZBR6h<xKmnCIp_+y;a8U{IMBQ#M(XCpNQ3Gsn;+<vZIJice{}a5r
> ag)
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> &ZAc5g+)64_YYs!W9tBS_HKzj$kT=pzb|_
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> D=gC
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> ?_%g~
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> 9NQTC#t
> zZE!h}?4nZ?Cu0lpyU(<^KY;xYGN^G at kiYHjA=1|{ZHb0NTY8Ds!^9HkVHW{j#2;
> })
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> zU}y;D&}dwD?{SRAFb77jh?jM*M#^>RF59*ty<&svu*utEj*r!0y;l>$Isi7^)x_%%
> z0sA^A3)c|U;YTWk;jL7M+>Z3tBd*=K$he{IbB|ihULN&?9pn>Z0vwcJg00kvx)n
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> DiO#0EiPL~z`L4N%
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> !;@
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> kKrtYb!e$@^gda*%vw0W&PN*_+hnXsejKJIVKr({
> zKP`*@xt;0^2B{Al|5V(#*gmyXaF+S0HhRql8x}9_r=3Ebqu&p`;ppWTKg7qR^_K
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> G%t*cdj!J0
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> z`u^WbDr#Lv2GYlkGDcG^dB}7Lbr5mQE_Y8zi)%qOJ*(oz57;ML#yQ!RaROSr9H
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> zzQ?bUcW>nPDSn^j`T8s8CK6*`>0gEaP^mwoMgZb_6|YC@(;@bKOtt<Tx^6ak
> zk^>B
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> OyE
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> kq@%V~6R7
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> zfIv+?Iv<6qhDE`_h8+qFP at UX(uD#iK{@}E&g`&@c?=K;1F}5l3OXyN0e5v6nQm
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> iuIQyGTJP$>ms
> zMJa|zVR&wwZErTV3{88ixUf(Y^gC)zAEwrW94~bPAucG5jRYxlPwo)ZWKs>Dt
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> 1S>+pQIXF_Y+f
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> znN&n&T at r%r#=)j|N<_xD`S-<o=BjmQ9w-
> n2fm8OSM*Vl)7%2b0i{>Ua@;jg3gC8i#
> zh)_P1x8I;K(||Ekv%}yko!exAhgW<M4mL7Rk}q}V=Oqv=v?1X^g8XVZ+G%p~)
> >do%
> z;7Fv8GHWopn!m5we6a8?3|yM;Jyu0sVObRW^G5(XNnn}+YTQsXl2&*82w)W
> gv&ef8
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> )gb&ti
> z5?4j7+Z>m??FEKO*nmKf^-Jk-
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> z=`?%Cno`%|zBB^Z3W2FmPh1CamyG~+Nm!`GgiSxo_Su#Zz)lYfm2OO-
> EP0+X0$6oe
> zsAnSw8;u$POdF2SMt)^80xJA^U*Xqto;eu|r^|N)rV78#m;JgH_uvR%cL+=so
> @fp0
> zIE3W35x}kv3q9NyiW+#;2w-
> mu3mxYR9oOP!jR1C3Sm>d?&_kQugb~2{r7pw5h0(sy
> z(XFmX%HcKLY4aADT701uEp9)W9$*EnXIbrz^#vW<?7lWa4!4B`9qkJ`y4Bq}0@
> zhy
> zK}Y(6j%;z4j{r6+EOde|bV9S6IRe;(u+Z_o(DCf29s#WAg;3g!^@WaYasNZg;Y8R
> b
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> Mx~8
> zokDvJFKA|1&{4jiqwsGY0c>1Y=n=lqBU)Vb2w?w%47b`PeWA%_x0jT|3;lt>RJ
> +4`
> zp@(r^)Cgc&=(nyh#uqw<^Q_CkMkC#eDJyZ5FL6|}`{eV1%_gLVHai^9$O_pt
> WD-A$
> zA+voXuzn4SfN4+!i~;!E5UiicAo-v}6f481FK4t9*ZrEgiH;?66JNY`ZelFYZ{Ybt
> zo^Rp#nGeoQyvVx~dA^9}%{=eoIl=R(Ja_T at O`d;An$bLenCFl4{2x632AFs7d?n
> 90
> zo*(9UGS6r6yol#@JcnvlFdnj66OUIl$T2y{XwIWT0VGrh->3w-
> 6V|<cDtLhPDeU;x
> zI(-U!$7so>R?g;v2)26$7}G+|4#6DT)WYhAh4VKkf3lT<B1svnBMi_wxv>q^$u(c`
> zd|?xNsbi3mmOs$yo_TIq`HFYrq at ig;jbKbe+dLB3erafcsfz$c7wH-
> ate4sdOd6WZ
> zD6Q_pAy_YJlJvBu{Zu+$v!FgT?im7?k2Zsf2EOV<2ih=;26vbfNL8U;-9lBZwhejd
> z?%6zL&n5cVK>C)dMCy2;u}h*vGgUxc9<VLjN4EF=J8Ky4unxprf^h6oe&{&^ve
> T^j
> zwDJ8wPRe)YX at 6pq(y~;aI!48{kfRiItUm<3`lRJkC2K2dHLFcy(b@(EqD03#1Va3!
> z-S<)Ae_8LTAthUkJ%-
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> zSn8aDn~v_JelUTY at D6Y*3VLqnu#}M;n?eXT_Y%7i>$xfDCQ0=FL3Sk8Vkr(L{q
> oFK
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> z?VLJVrDG=MuQNcuz4w0n`ySAx`>VR+vV`Vlo8HQ|iiz<J>Ucs+mi5KSd?2!5dqp
> jI
> zi3941+jWJ<O!2<v*!T2fvs>FMLlA}bih&%rWb6{=TeUkW~&d&^>#QyW<b
> N*yrd
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> zR#=HsAc{vT7ea{!iwRmb36?(wil32^&aozUb_X+g!>5I|R<x0!heVYsmeK}BCG
> UKU
> zx7p at e@`jCD-M--
> CPW!l3J?VVr7}eWn*V7QN23y5z*}KXrHEfySL;<iydf)Du%%-g}
> zWM^Ayh<DfjQ7qCE7eQ&2J-
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> z{8#s_rNrpG&q4R|--W`!JTyq$>~8g}pEcKrCCl<nogBF%PmbK2y61Ku(|y9|{-
> L4K
> zYUSo!UXBu_W<JUTZl7Zac+37b(Jb<foxoZiqR<9}Cn8!0mR(O}C?od0_PJjj^YrR{
> zl at zl2F|k`~&M={m1k7}l&ngfxzLa;Ul(tS_trXhmonavzZw=9}9#;jJPn|utI(Til
> zXXi``5bRQwvMu$6U#PKscJr&#dn*IWvymcw3!N|(ey!o?oOsclQ&c~MQb$BN
> !lYIH
> zor2-
> mul|Sel?QA%w}#VBJmmu%>x+#6mTK*ajxz(&xZl`}h_J$(*b~sXI{ie2M=;x5
> z9lQ+cHYr40+yq59%YbWg&7XW at l<G3S_PJjkvvc)cYmBXG3 at Rl0AeN%WFcJk
> k=Nm(s
> zPmFEg?MLs8T6`=YBOLu%UBl3{?r~<R(ZujRMbv0=E`~V1b&LtK^Xm&=SBsU}X
> KC;q
> zX1MU%p0M_ at VNOj4r~HXgh+`1&uq%!Z8jZzLPxLv}cG}r%DZ2Piq$za9(8Yciuv
> 2;&
> ztkqslzExii$k*{MkBwI7d_%Yy5#BR``XVHD8qKU4+4HOYd;G9PGtV9&mj_8^SE
> qZc
> z)Va}(kcS*cboRzUIjlz!-pl3Rw?>wKBMY`~8;0HrSrTj;ZY&pU>Ah7*ueRzycm!fM
> z8W2X7Uq|jeSbl-
> B2J4aJSFOn}ar0;~^J|h{HDczHe4>~Bd41R#SA~?N`2zVtWSg*M
> zK1ZiAF^~#dCg9Xb!+LelCiLkis(g-gS<fEUS|Tg#Va;ihr at b7Zt0IKn<&$e!*o$UY
> z7em6c^()A`fD;gPJF9$A5$EI%W{=l1$i>;i>&rGo5nAQ9-#nN<>KM${FN at k-
> gC#Od
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> zsQ}UmCS}jBkCV>&jHOTa)szN%(^iiog{{D)CbnPjHLcrX5?uc^HJ8?H8<$k)nMAc
> $
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> uST
> z459MOzi66NLPCE?3T^zhk%V=Rpgx?P)rfxt!Il~a5uX<7An+z3?&{bZIQZHoX~~
> Cc
> z8t+1%ZFs6fc#kRW9;Rak{I!NWN+h}jWxV=?Aq|EP??8wmNs<pg#et~|6<$lxc
> %i3~
> z&SToI#(%efyuf@`V|D7(P)o;$rp0aWABglIU!P{z{dMae4gH2&=qqIv{?Ue@!e
> M=b
> zdQxlF9-CfFKHByo_qM!I%?zxGRmB(6&%bZ^M14uWuy_?K8;vjG-
> GEn2agzUf?(!r2
> z*Yj45^<T$$pP8+DnRd0k=#Q2jEdHA`<UnhDh4SGSTh4}wC}rT><%jwr-
> o0{yFXDZi
> zLvEjL!LPXF=pzRxx#?h_wIEL2v7$=+$_C1rk7+~JE9 at 5~9<5sF9C_k(RGT-
> <U~vUa
> zUcLGSjd&}L*5}+fg#k`JTz4){HOKehPBU1%RP&mAQ=hvR$7%ij1|I1-
> ye;eSc<FOr
> z(39!!KF+lE-
> 6`&3pG)(l*^Ohy?3ZN^nentT)TgufL=hMznre>U8dA=x<N39vgss@*
> z!#Y>a9~`xUgJ|2TEnac*;VK<CM-
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> ze`eadlGTwAoo>3r;1cRf(0pau>Uu23g{@(DWVl*;iXOq?c2~f}^!Z3``1THpKaTM
> u
> zezcaAd5UpyUGeB*efj4l3CG?W at TrS(3(8wE)V_P~yu_k=_?&1?_stKwS~LCK
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> zQ at veooVH&0F0Dzc%r?vwYqE!H9;V%|-
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> zexCcn<0Y5T0J8l)z%8-+=~i{XaKkO-LJXK<ms<=P+IL$c9fFObsfk=Gmmk7)>Plv8
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> w(YQ8gU7Zv3z@`{D?_Y4zthSHoj`GDpXbKJvGR}}D<yWbLae$~
> zN(`$We7SRt-
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> z-6LaTf$DUN#sWxRU`gzO;uw9+wmpz*d?4-4RCbj`>_mMHO?B5-
> 7O#*m&J!F~fWft=
> zq0wE>ntxA2lk1p7q(nn=R$JdqNzPVCeygo+R9m0?8?mU+>L~X0YBpT$jy$OK3
> sb13
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> z4ll at b)r~XV!;h(#zk$y_ks49ohB)3hNbR%lRG+m}G3nAT3#XNVwCQ>7muzsSe
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> zU+$Rb(nzK4s(E4)hM`2ELFzV!PxkyY5;pNpPCvW>vhR{W6qR=gl=C{mb3Bf1Pb
> @OY
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> zI9MX`d}I&%VP+<X(_$fUc4#~4<>s*n0+g_1F;}SJ3rdY#Cy_JBqYj%ewA3s>$$O
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>
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h
> new file mode 100644
> index 0000000000..3b0f00198b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h
> @@ -0,0 +1,122 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + AlertStandardFormatTable.h
> +
> +Abstract:
> +
> + ACPI Alert Standard Format Description Table ASF! as described
> + in the ASF2.0 Specification
> +
> +--*/
> +
> +#ifndef _ALERT_STANDARD_FORMAT_TABLE_H
> +#define _ALERT_STANDARD_FORMAT_TABLE_H
> +
> +#include <IndustryStandard/Acpi20.h>
> +
> +//
> +// Ensure proper structure formats.
> +//
> +#pragma pack (1)
> +
> +//
> +// Information Record header that appears at the beginning of each record.
> +//
> +typedef struct {
> + UINT8 Type;
> + UINT8 Reserved;
> + UINT16 RecordLength;
> +} EFI_ACPI_ASF_RECORD_HEADER;
> +
> +//
> +// This structure contains information that identifies the system type
> +// and configuration.
> +//
> +typedef struct {
> + EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
> + UINT8 MinWatchDogResetValue;
> + UINT8 MinPollingInterval;
> + UINT16 SystemID;
> + UINT32 IANAManufactureID;
> + UINT8 FeatureFlags;
> + UINT8 Reserved[3];
> +} EFI_ACPI_ASF_INFO;
> +
> +//
> +// Alert sensors definition.
> +//
> +#define ASF_ALRT_SENSOR_ARRAY_LENGTH 36
> +
> +typedef struct {
> + EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
> + UINT8 AssertionEventBitMask;
> + UINT8 DeassertionEventBitMask;
> + UINT8 NumberOfAlerts;
> + UINT8 ArrayElementLength;
> + UINT8 DeviceArray[ASF_ALRT_SENSOR_ARRAY_LENGTH];
> +} EFI_ACPI_ASF_ALRT;
> +
> +//
> +// Alert Remote Control System Actions.
> +//
> +#define ASF_RCTL_DEVICES_ARRAY_LENGTH 16
> +
> +typedef struct {
> + EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
> + UINT8 NumberOfControls;
> + UINT8 ArrayElementLength;
> + UINT16 RctlReserved;
> + UINT8 ControlArray[ASF_RCTL_DEVICES_ARRAY_LENGTH];
> +} EFI_ACPI_ASF_RCTL;
> +
> +//
> +// Remote Control Capabilities.
> +//
> +typedef struct {
> + EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
> + UINT8 RemoteControlCapabilities[7];
> + UINT8 RMCPCompletionCode;
> + UINT32 RMCPIANA;
> + UINT8 RMCPSpecialCommand;
> + UINT8 RMCPSpecialCommandParameter[2];
> + UINT8 RMCPBootOptions[2];
> + UINT8 RMCPOEMParameters[2];
> +} EFI_ACPI_ASF_RMCP;
> +
> +//
> +// SMBus Devices with fixed addresses.
> +//
> +#define ASF_ADDR_DEVICE_ARRAY_LENGTH 16
> +
> +typedef struct {
> + EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
> + UINT8 SEEPROMAddress;
> + UINT8 NumberOfDevices;
> + UINT8
> FixedSmbusAddresses[ASF_ADDR_DEVICE_ARRAY_LENGTH];
> +} EFI_ACPI_ASF_ADDR;
> +
> +typedef struct {
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + EFI_ACPI_ASF_INFO AsfInfo;
> + EFI_ACPI_ASF_ALRT AsfAlert;
> + EFI_ACPI_ASF_RCTL AsfRctl;
> + EFI_ACPI_ASF_RMCP AsfRmcp;
> + EFI_ACPI_ASF_ADDR AsfAddr;
> +} EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE;
> +
> +//
> +// "ASF!" ASF Description Table Signature.
> +//
> +#define EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE_SIGNATURE 0x21465341
> +
> +#pragma pack ()
> +
> +#endif // _ALERT_STANDARD_FORMAT_TABLE_H
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/ChipsetAccess.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/ChipsetAccess.h
> new file mode 100644
> index 0000000000..31ccfe6d5f
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/ChipsetAccess.h
> @@ -0,0 +1,28 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + ChipsetAccess.h
> +
> +Abstract:
> +
> + Common Include file for Platform Drivers to access the Chipset registers.
> +
> +--*/
> +
> +#ifndef _CHIPSET_ACCESS_H_
> +#define _CHIPSET_ACCESS_H_
> +
> +#include "PchAccess.h"
> +#include "Valleyview.h"
> +#include "VlvAccess.h"
> +#include "VlvCommonDefinitions.h"
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/CommonIncludes.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/CommonIncludes.h
> new file mode 100644
> index 0000000000..eab47b28d9
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/CommonIncludes.h
> @@ -0,0 +1,115 @@
> +/**
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> + at file
> + CommonIncludes.h
> +
> + at brief
> + This file defines common equates.
> +
> +**/
> +#ifndef _COMMON_INCLUDES_H_
> +#define _COMMON_INCLUDES_H_
> +
> +#define V_INTEL_VID 0x8086
> +
> +#ifndef STALL_ONE_MICRO_SECOND
> +#define STALL_ONE_MICRO_SECOND 1
> +#endif
> +#ifndef STALL_ONE_MILLI_SECOND
> +#define STALL_ONE_MILLI_SECOND 1000
> +#endif
> +///
> +/// Min Max
> +///
> +#define V_MIN(a, b) (((a) < (b)) ? (a) : (b))
> +#define V_MAX(a, b) (((a) > (b)) ? (a) : (b))
> +
> +///
> +/// Bit map macro
> +///
> +#ifndef BIT0
> +
> +#define BIT63 0x8000000000000000
> +#define BIT62 0x4000000000000000
> +#define BIT61 0x2000000000000000
> +#define BIT60 0x1000000000000000
> +#define BIT59 0x0800000000000000
> +#define BIT58 0x0400000000000000
> +#define BIT57 0x0200000000000000
> +#define BIT56 0x0100000000000000
> +#define BIT55 0x0080000000000000
> +#define BIT54 0x0040000000000000
> +#define BIT53 0x0020000000000000
> +#define BIT52 0x0010000000000000
> +#define BIT51 0x0008000000000000
> +#define BIT50 0x0004000000000000
> +#define BIT49 0x0002000000000000
> +#define BIT48 0x0001000000000000
> +#define BIT47 0x0000800000000000
> +#define BIT46 0x0000400000000000
> +#define BIT45 0x0000200000000000
> +#define BIT44 0x0000100000000000
> +#define BIT43 0x0000080000000000
> +#define BIT42 0x0000040000000000
> +#define BIT41 0x0000020000000000
> +#define BIT40 0x0000010000000000
> +#define BIT39 0x0000008000000000
> +#define BIT38 0x0000004000000000
> +#define BIT37 0x0000002000000000
> +#define BIT36 0x0000001000000000
> +#define BIT35 0x0000000800000000
> +#define BIT34 0x0000000400000000
> +#define BIT33 0x0000000200000000
> +#define BIT32 0x0000000100000000
> +
> +#define BIT31 0x80000000
> +#define BIT30 0x40000000
> +#define BIT29 0x20000000
> +#define BIT28 0x10000000
> +#define BIT27 0x08000000
> +#define BIT26 0x04000000
> +#define BIT25 0x02000000
> +#define BIT24 0x01000000
> +#define BIT23 0x00800000
> +#define BIT22 0x00400000
> +#define BIT21 0x00200000
> +#define BIT20 0x00100000
> +#define BIT19 0x00080000
> +#define BIT18 0x00040000
> +#define BIT17 0x00020000
> +#define BIT16 0x00010000
> +#define BIT15 0x00008000
> +#define BIT14 0x00004000
> +#define BIT13 0x00002000
> +#define BIT12 0x00001000
> +#define BIT11 0x00000800
> +#define BIT10 0x00000400
> +#define BIT9 0x00000200
> +#define BIT8 0x00000100
> +#define BIT7 0x00000080
> +#define BIT6 0x00000040
> +#define BIT5 0x00000020
> +#define BIT4 0x00000010
> +#define BIT3 0x00000008
> +#define BIT2 0x00000004
> +#define BIT1 0x00000002
> +#define BIT0 0x00000001
> +#endif
> +
> +#define BITS(x) (1 << (x))
> +
> +//
> +// Notes :
> +// 1. Bit position always starts at 0.
> +// 2. Following macros are applicable only for Word alligned integers.
> +//
> +#define BIT(Pos, Value) (1 << (Pos) & (Value))
> +#define BITRANGE(From, Width, Value) (((Value) >> (From)) & ((1 <<
> (Width)) - 1))
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/CpuType.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/CpuType.h
> new file mode 100644
> index 0000000000..c195dee773
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/CpuType.h
> @@ -0,0 +1,59 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + CpuType.h
> +
> +Abstract:
> +
> +--*/
> +
> +#ifndef _CPU_TYPE_H
> +#define _CPU_TYPE_H
> +
> +#pragma pack(1)
> +
> +typedef enum {
> + EnumCpuUarchUnknown = 0,
> + EnumNehalemUarch,
> +} EFI_CPU_UARCH;
> +
> +typedef enum {
> + EnumCpuPlatformUnknown = 0,
> + EnumDesktop,
> + EnumMobile,
> + EnumServer,
> + EnumNetTop
> +} EFI_CPU_PLATFORM;
> +
> +typedef enum {
> + EnumCpuTypeUnknown = 0,
> + EnumAtom,
> + EnumNehalemEx,
> + EnumBloomfield,
> + EnumGainestown,
> + EnumHavendale,
> + EnumLynnfield,
> + EnumAuburndale,
> + EnumClarksfield,
> + EnumPineview,
> + EnumCedarview,
> + EnumValleyview,
> + EnumClarkdale // Havendale 32nm
> +} EFI_CPU_TYPE;
> +
> +typedef enum {
> + EnumCpuFamilyUnknown = 0,
> + EnumFamilyField,
> + EnumFamilyDale
> +} EFI_CPU_FAMILY;
> +
> +#pragma pack()
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/FileHandleLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/FileHandleLib.h
> new file mode 100644
> index 0000000000..5d733a0240
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/FileHandleLib.h
> @@ -0,0 +1,499 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef _FILE_HANDLE_LIBRARY_HEADER_
> +#define _FILE_HANDLE_LIBRARY_HEADER_
> +
> +#include <Protocol/SimpleFileSystem.h>
> +
> +//
> +// The tag for use in identifying UNICODE files.
> +// If the file is UNICODE, the first 16 bits of the file will equal this value.
> +//
> +extern CONST UINT16 gUnicodeFileTag;
> +
> +/**
> + This function retrieves information about the file for the handle
> + specified and stores it in the allocated pool memory.
> +
> + This function allocates a buffer to store the file's information. It is the
> + caller's responsibility to free the buffer.
> +
> + @param[in] FileHandle The file handle of the file for which information
> is
> + being requested.
> +
> + @retval NULL Information could not be retrieved.
> + @retval !NULL The information about the file.
> +**/
> +EFI_FILE_INFO*
> +EFIAPI
> +FileHandleGetInfo (
> + IN EFI_FILE_HANDLE FileHandle
> + );
> +
> +/**
> + This function sets the information about the file for the opened handle
> + specified.
> +
> + @param[in] FileHandle The file handle of the file for which information
> + is being set.
> +
> + @param[in] FileInfo The information to set.
> +
> + @retval EFI_SUCCESS The information was set.
> + @retval EFI_INVALID_PARAMETER A parameter was out of range or invalid.
> + @retval EFI_UNSUPPORTED The FileHandle does not support FileInfo.
> + @retval EFI_NO_MEDIA The device has no medium.
> + @retval EFI_DEVICE_ERROR The device reported an error.
> + @retval EFI_VOLUME_CORRUPTED The file system structures are
> corrupted.
> + @retval EFI_WRITE_PROTECTED The file or medium is write protected.
> + @retval EFI_ACCESS_DENIED The file was opened read only.
> + @retval EFI_VOLUME_FULL The volume is full.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleSetInfo (
> + IN EFI_FILE_HANDLE FileHandle,
> + IN CONST EFI_FILE_INFO *FileInfo
> + );
> +
> +/**
> + This function reads information from an opened file.
> +
> + If FileHandle is not a directory, the function reads the requested number
> of
> + bytes from the file at the file's current position and returns them in Buffer.
> + If the read goes beyond the end of the file, the read length is truncated to
> the
> + end of the file. The file's current position is increased by the number of
> bytes
> + returned. If FileHandle is a directory, the function reads the directory
> entry
> + at the file's current position and returns the entry in Buffer. If the Buffer
> + is not large enough to hold the current directory entry, then
> + EFI_BUFFER_TOO_SMALL is returned and the current file position is not
> updated.
> + BufferSize is set to be the size of the buffer needed to read the entry. On
> + success, the current position is updated to the next directory entry. If
> there
> + are no more directory entries, the read returns a zero-length buffer.
> + EFI_FILE_INFO is the structure returned as the directory entry.
> +
> + @param[in] FileHandle The opened file handle.
> + @param[in, out] BufferSize On input, the size of buffer in bytes. On
> return,
> + the number of bytes written.
> + @param[out] Buffer The buffer to put read data into.
> +
> + @retval EFI_SUCCESS Data was read.
> + @retval EFI_NO_MEDIA The device has no media.
> + @retval EFI_DEVICE_ERROR The device reported an error.
> + @retval EFI_VOLUME_CORRUPTED The file system structures are
> corrupted.
> + @retval EFI_BUFFER_TO_SMALL Buffer is too small. ReadSize contains
> required
> + size.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleRead(
> + IN EFI_FILE_HANDLE FileHandle,
> + IN OUT UINTN *BufferSize,
> + OUT VOID *Buffer
> + );
> +
> +/**
> + Write data to a file.
> +
> + This function writes the specified number of bytes to the file at the current
> + file position. The current file position is advanced the actual number of
> bytes
> + written, which is returned in BufferSize. Partial writes only occur when
> there
> + has been a data error during the write attempt (such as "volume space
> full").
> + The file is automatically grown to hold the data if required. Direct writes to
> + opened directories are not supported.
> +
> + @param[in] FileHandle The opened file for writing.
> + @param[in, out] BufferSize On input, the number of bytes in Buffer. On
> output,
> + the number of bytes written.
> + @param[in] Buffer The buffer containing data to write is stored.
> +
> + @retval EFI_SUCCESS Data was written.
> + @retval EFI_UNSUPPORTED Writes to an open directory are not
> supported.
> + @retval EFI_NO_MEDIA The device has no media.
> + @retval EFI_DEVICE_ERROR The device reported an error.
> + @retval EFI_VOLUME_CORRUPTED The file system structures are
> corrupted.
> + @retval EFI_WRITE_PROTECTED The device is write-protected.
> + @retval EFI_ACCESS_DENIED The file was opened for read only.
> + @retval EFI_VOLUME_FULL The volume is full.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleWrite(
> + IN EFI_FILE_HANDLE FileHandle,
> + IN OUT UINTN *BufferSize,
> + IN VOID *Buffer
> + );
> +
> +/**
> + Close an open file handle.
> +
> + This function closes a specified file handle. All "dirty" cached file data is
> + flushed to the device, and the file is closed. In all cases the handle is
> + closed.
> +
> + @param[in] FileHandle The file handle to close.
> +
> + @retval EFI_SUCCESS The file handle was closed successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleClose (
> + IN EFI_FILE_HANDLE FileHandle
> + );
> +
> +/**
> + Delete a file and close the handle.
> +
> + This function closes and deletes a file. In all cases the file handle is closed.
> + If the file cannot be deleted, the warning code
> EFI_WARN_DELETE_FAILURE is
> + returned, but the handle is still closed.
> +
> + @param[in] FileHandle The file handle to delete.
> +
> + @retval EFI_SUCCESS The file was closed successfully.
> + @retval EFI_WARN_DELETE_FAILURE The handle was closed, but the file
> was not
> + deleted.
> + @retval INVALID_PARAMETER One of the parameters has an invalid
> value.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleDelete (
> + IN EFI_FILE_HANDLE FileHandle
> + );
> +
> +/**
> + Set the current position in a file.
> +
> + This function sets the current file position for the handle to the position
> + supplied. With the exception of moving to position 0xFFFFFFFFFFFFFFFF,
> only
> + absolute positioning is supported, and moving past the end of the file is
> + allowed (a subsequent write would grow the file). Moving to position
> + 0xFFFFFFFFFFFFFFFF causes the current position to be set to the end of
> the file.
> + If FileHandle is a directory, the only position that may be set is zero. This
> + has the effect of starting the read process of the directory entries over
> again.
> +
> + @param[in] FileHandle The file handle on which the position is being
> set.
> + @param[in] Position The byte position from the begining of the file.
> +
> + @retval EFI_SUCCESS The operation completed sucessfully.
> + @retval EFI_UNSUPPORTED The request for non-zero is not valid on
> + directories.
> + @retval INVALID_PARAMETER One of the parameters has an invalid
> value.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleSetPosition (
> + IN EFI_FILE_HANDLE FileHandle,
> + IN UINT64 Position
> + );
> +
> +/**
> + Gets a file's current position.
> +
> + This function retrieves the current file position for the file handle. For
> + directories, the current file position has no meaning outside of the file
> + system driver. As such, the operation is not supported. An error is
> returned
> + if FileHandle is a directory.
> +
> + @param[in] FileHandle The open file handle on which to get the
> position.
> + @param[out] Position The byte position from begining of file.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval INVALID_PARAMETER One of the parameters has an invalid
> value.
> + @retval EFI_UNSUPPORTED The request is not valid on directories.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleGetPosition (
> + IN EFI_FILE_HANDLE FileHandle,
> + OUT UINT64 *Position
> + );
> +
> +/**
> + Flushes data on a file.
> +
> + This function flushes all modified data associated with a file to a device.
> +
> + @param[in] FileHandle The file handle on which to flush data.
> +
> + @retval EFI_SUCCESS The data was flushed.
> + @retval EFI_NO_MEDIA The device has no media.
> + @retval EFI_DEVICE_ERROR The device reported an error.
> + @retval EFI_VOLUME_CORRUPTED The file system structures are
> corrupted.
> + @retval EFI_WRITE_PROTECTED The file or medium is write protected.
> + @retval EFI_ACCESS_DENIED The file was opened for read only.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleFlush (
> + IN EFI_FILE_HANDLE FileHandle
> + );
> +
> +/**
> + Function to determine if a given handle is a directory handle.
> +
> + If DirHandle is NULL, then ASSERT().
> +
> + Open the file information on the DirHandle, and verify that the Attribute
> + includes EFI_FILE_DIRECTORY bit set.
> +
> + @param[in] DirHandle The handle to open the file.
> +
> + @retval EFI_SUCCESS DirHandle is a directory.
> + @retval EFI_INVALID_PARAMETER DirHandle did not have EFI_FILE_INFO
> available.
> + @retval EFI_NOT_FOUND DirHandle is not a directory.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleIsDirectory (
> + IN EFI_FILE_HANDLE DirHandle
> + );
> +
> +/**
> + Retrieve first entry from a directory.
> +
> + This function takes an open directory handle and gets information from
> the
> + first entry in the directory. A buffer is allocated to contain
> + the information and a pointer to the buffer is returned in *Buffer. The
> + caller can use FileHandleFindNextFile() to get subsequent directory entries.
> +
> + The buffer will be freed by FileHandleFindNextFile() when the last
> directory
> + entry is read. Otherwise, the caller must free the buffer, using FreePool,
> + when finished with it.
> +
> + @param[in] DirHandle The file handle of the directory to search.
> + @param[out] Buffer The pointer to pointer to buffer for file's
> information.
> +
> + @retval EFI_SUCCESS Found the first file.
> + @retval EFI_NOT_FOUND Cannot find the directory.
> + @retval EFI_NO_MEDIA The device has no media.
> + @retval EFI_DEVICE_ERROR The device reported an error.
> + @retval EFI_VOLUME_CORRUPTED The file system structures are
> corrupted.
> + @return Others The status of FileHandleGetInfo,
> FileHandleSetPosition,
> + or FileHandleRead.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleFindFirstFile (
> + IN EFI_FILE_HANDLE DirHandle,
> + OUT EFI_FILE_INFO **Buffer
> + );
> +
> +/**
> + Retrieve next entries from a directory.
> +
> + To use this function, the caller must first call the FileHandleFindFirstFile()
> + function to get the first directory entry. Subsequent directory entries are
> + retrieved by using the FileHandleFindNextFile() function. This function can
> + be called several times to get each entry from the directory. If the call of
> + FileHandleFindNextFile() retrieved the last directory entry, the next call of
> + this function will set *NoFile to TRUE and free the buffer.
> +
> + @param[in] DirHandle The file handle of the directory.
> + @param[out] Buffer The pointer to buffer for file's information.
> + @param[out] NoFile The pointer to boolean when last file is found.
> +
> + @retval EFI_SUCCESS Found the next file, or reached last file.
> + @retval EFI_NO_MEDIA The device has no media.
> + @retval EFI_DEVICE_ERROR The device reported an error.
> + @retval EFI_VOLUME_CORRUPTED The file system structures are
> corrupted.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleFindNextFile(
> + IN EFI_FILE_HANDLE DirHandle,
> + OUT EFI_FILE_INFO *Buffer,
> + OUT BOOLEAN *NoFile
> + );
> +
> +/**
> + Retrieve the size of a file.
> +
> + If FileHandle is NULL then ASSERT().
> + If Size is NULL then ASSERT().
> +
> + This function extracts the file size info from the FileHandle's EFI_FILE_INFO
> + data.
> +
> + @param[in] FileHandle The file handle from which size is retrieved.
> + @param[out] Size The pointer to size.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_DEVICE_ERROR Cannot access the file.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleGetSize (
> + IN EFI_FILE_HANDLE FileHandle,
> + OUT UINT64 *Size
> + );
> +
> +/**
> + Set the size of a file.
> +
> + If FileHandle is NULL then ASSERT().
> +
> + This function changes the file size info from the FileHandle's EFI_FILE_INFO
> + data.
> +
> + @param[in] FileHandle The file handle whose size is to be changed.
> + @param[in] Size The new size.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_DEVICE_ERROR Cannot access the file.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleSetSize (
> + IN EFI_FILE_HANDLE FileHandle,
> + IN UINT64 Size
> + );
> +
> +/**
> + Function to get a full filename given a EFI_FILE_HANDLE somewhere lower
> on the
> + directory 'stack'.
> +
> + @param[in] Handle Handle to the Directory or File to create path to.
> + @param[out] FullFileName Pointer to pointer to generated full file
> name. It
> + is the responsibility of the caller to free this memory
> + with a call to FreePool().
> + @retval EFI_SUCCESS The operation was successful and FullFileName
> is valid.
> + @retval EFI_INVALID_PARAMETER Handle was NULL.
> + @retval EFI_INVALID_PARAMETER FullFileName was NULL.
> + @retval EFI_OUT_OF_MEMORY A memory allocation failed.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleGetFileName (
> + IN CONST EFI_FILE_HANDLE Handle,
> + OUT CHAR16 **FullFileName
> + );
> +
> +/**
> + Function to read a single line (up to but not including the \n) from a file.
> +
> + If the position upon start is 0, then the Ascii Boolean will be set. This
> should be
> + maintained and not changed for all operations with the same file.
> +
> + @param[in] Handle FileHandle to read from.
> + @param[in, out] Buffer The pointer to buffer to read into.
> + @param[in, out] Size The pointer to number of bytes in Buffer.
> + @param[in] Truncate If the buffer is large enough, this has no effect.
> + If the buffer is is too small and Truncate is TRUE,
> + the line will be truncated.
> + If the buffer is is too small and Truncate is FALSE,
> + then no read will occur.
> +
> + @param[in, out] Ascii Boolean value for indicating whether the file is
> + Ascii (TRUE) or UCS2 (FALSE).
> +
> + @retval EFI_SUCCESS The operation was successful. The line is
> stored in
> + Buffer.
> + @retval EFI_INVALID_PARAMETER Handle was NULL.
> + @retval EFI_INVALID_PARAMETER Size was NULL.
> + @retval EFI_BUFFER_TOO_SMALL Size was not large enough to store the
> line.
> + Size was updated to the minimum space required.
> + @sa FileHandleRead
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleReadLine(
> + IN EFI_FILE_HANDLE Handle,
> + IN OUT CHAR16 *Buffer,
> + IN OUT UINTN *Size,
> + IN BOOLEAN Truncate,
> + IN OUT BOOLEAN *Ascii
> + );
> +
> +/**
> + Function to read a single line from a file. The \n is not included in the
> returned
> + buffer. The returned buffer must be callee freed.
> +
> + If the position upon start is 0, then the Ascii Boolean will be set. This
> should be
> + maintained and not changed for all operations with the same file.
> +
> + @param[in] Handle FileHandle to read from.
> + @param[in, out] Ascii Boolean value for indicating whether the file is
> + Ascii (TRUE) or UCS2 (FALSE).
> +
> + @return The line of text from the file.
> +
> + @sa FileHandleReadLine
> +**/
> +CHAR16*
> +EFIAPI
> +FileHandleReturnLine(
> + IN EFI_FILE_HANDLE Handle,
> + IN OUT BOOLEAN *Ascii
> + );
> +
> +/**
> + Function to write a line of unicode text to a file.
> +
> + If Handle is NULL, ASSERT.
> +
> + @param[in] Handle FileHandle to write to.
> + @param[in] Buffer Buffer to write, if NULL the function will
> + take no action and return EFI_SUCCESS.
> +
> + @retval EFI_SUCCESS The data was written.
> + @retval other Failure.
> +
> + @sa FileHandleWrite
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandleWriteLine(
> + IN EFI_FILE_HANDLE Handle,
> + IN CHAR16 *Buffer
> + );
> +
> +/**
> + Function to take a formatted argument and print it to a file.
> +
> + @param[in] Handle The file handle for the file to write to.
> + @param[in] Format The format argument (see printlib for the format
> specifier).
> + @param[in] ... The variable arguments for the format.
> +
> + @retval EFI_SUCCESS The operation was successful.
> + @retval other A return value from FileHandleWriteLine.
> +
> + @sa FileHandleWriteLine
> +**/
> +EFI_STATUS
> +EFIAPI
> +FileHandlePrintLine(
> + IN EFI_FILE_HANDLE Handle,
> + IN CONST CHAR16 *Format,
> + ...
> + );
> +
> +/**
> + Function to determine if a FILE_HANDLE is at the end of the file.
> +
> + This will NOT work on directories.
> +
> + If Handle is NULL, then ASSERT().
> +
> + @param[in] Handle The file handle.
> +
> + @retval TRUE The position is at the end of the file.
> + @retval FALSE The position is not at the end of the file.
> +**/
> +BOOLEAN
> +EFIAPI
> +FileHandleEof(
> + IN EFI_FILE_HANDLE Handle
> + );
> +
> +#endif //_FILE_HANDLE_LIBRARY_HEADER_
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h
> new file mode 100644
> index 0000000000..7320bf6cfe
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h
> @@ -0,0 +1,30 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + AcpiTableStorage.h
> +
> +Abstract:
> +
> + GUID for the ACPI Table Storage filename.
> +
> + This GUID is defined in the Tiano ACPI Table Storage EPS.
> +
> +--*/
> +
> +#ifndef _ACPI_TABLE_STORAGE_H_
> +#define _ACPI_TABLE_STORAGE_H_
> +
> +#define EFI_ACPI_TABLE_STORAGE_GUID \
> + { 0x7e374e25, 0x8e01, 0x4fee, {0x87, 0xf2, 0x39, 0xc, 0x23, 0xc6, 0x6, 0xcd} }
> +
> +extern EFI_GUID gEfiAcpiTableStorageGuid;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h
> new file mode 100644
> index 0000000000..f0459545e4
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h
> @@ -0,0 +1,86 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + Asf.h
> +
> +Abstract:
> +
> + Alert Standard Format address variable
> +
> +--*/
> +
> +#ifndef AlertStandardFormat_h_included
> +#define AlertStandardFormat_h_included
> +
> +
> +#pragma pack(1)
> +
> +//
> +// ASF address
> +//
> +//
> +// {3D995FB4-4F05-4073-BE72-A19CFB5DE690}
> +//
> +#define ALERT_STANDARD_FORMAT_VARIABLE_GUID \
> + {0x3d995fb4, 0x4f05, 0x4073, 0xbe, 0x72, 0xa1, 0x9c, 0xfb, 0x5d, 0xe6, 0x90}
> +
> +#define ALERT_STANDARD_FORMAT_VARIABLE_NAME (L"ASF")
> +#define ASCII_ALERT_STANDARD_FORMAT_VARIABLE_NAME ("ASF")
> +
> +extern EFI_GUID gAlertStandardFormatGuid;
> +extern CHAR16 gAlertStandardFormatName[];
> +
> +typedef struct {
> + UINT8 SmbusAddr;
> + struct {
> + UINT32 VendorSpecificId;
> + UINT16 SubsystemDeviceId;
> + UINT16 SubsystemVendorId;
> + UINT16 Interface;
> + UINT16 DeviceId;
> + UINT16 VendorId;
> + UINT8 VendorRevision;
> + UINT8 DeviceCapabilities;
> + } Udid;
> + struct {
> + UINT8 SubCommand;
> + UINT8 Version;
> + UINT32 IanaId;
> + UINT8 SpecialCommand;
> + UINT16 SpecialCommandParam;
> + UINT16 BootOptionsBits;
> + UINT16 OemParam;
> + } AsfBootOptions;
> + struct {
> + UINT8 Bus;
> + UINT8 Device;
> + UINT8 Function;
> + UINT16 VendorId;
> + UINT16 DeviceId;
> + UINT16 IderCmdBar;
> + UINT16 IderCtrlBar;
> + UINT8 IderIrq;
> + UINT16 SolBar;
> + UINT8 SolIrq;
> + } PciInfo;
> + struct {
> + UINT8 IamtProvisioningStatus;
> + BOOLEAN IamtIsProvisioned;
> + } IamtInfo;
> + struct {
> + BOOLEAN FlashUpdatingIsAllowed;
> + } MeInfoForEbu;
> + UINT32 EitBPFAddress;
> +} EFI_ASF_VARIABLE;
> +
> +#pragma pack()
> +
> +#endif
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/BiosId.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/BiosId.h
> new file mode 100644
> index 0000000000..e86fc852fc
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/BiosId.h
> @@ -0,0 +1,30 @@
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + BiosId.h
> +
> +Abstract:
> +
> + GUIDs used for Bios ID.
> +
> +--*/
> +
> +#ifndef _BIOS_ID_H_
> +#define _BIOS_ID_H_
> +
> +
> +#define EFI_BIOS_ID_GUID \
> +{ 0xC3E36D09, 0x8294, 0x4b97, 0xA8, 0x57, 0xD5, 0x28, 0x8F, 0xE3, 0x3E,
> 0x28 }
> +
> +
> +extern EFI_GUID gEfiBiosIdGuid;
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h
> new file mode 100644
> index 0000000000..ae3c2d9aea
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h
> @@ -0,0 +1,214 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + BoardFeatures.h
> +
> +Abstract:
> +
> + EFI Platform Board Features
> +
> +
> +
> +--*/
> +
> +#ifndef BoardFeatures_h_included
> +#define BoardFeatures_h_included
> +
> +#include <Base.h>
> +
> +#pragma pack(1)
> +
> +//
> +// Board Features
> +//
> +#if defined LEGACY_BOARD_FEATURES && LEGACY_BOARD_FEATURES
> +#define B_BOARD_FEATURES_CHIPSET_LAN BIT0
> +#define B_BOARD_FEATURES_LAN_MARVELL BIT1
> +#define B_BOARD_FEATURES_AA_NOT_FOUND BIT2
> +#define B_BOARD_FEATURES_SIO_NO_COM1 BIT3
> +#define B_BOARD_FEATURES_SIO_COM2 BIT4
> +#define B_BOARD_FEATURES_SIO_NO_PARALLEL BIT5
> +#define B_BOARD_FEATURES_CHIPSET_VIDEO BIT6
> +#define B_BOARD_FEATURES_CHIPSET_VIDEO_OPTION0 BIT7
> +#define B_BOARD_FEATURES_VIDEO_SLOT BIT8
> +#define B_BOARD_FEATURES_MINI_CARD BIT9
> +#define B_BOARD_FEATURES_DISCRETE_1394 BIT10
> +#define B_BOARD_FEATURES_LEGACY_FREE BIT11
> +#define B_BOARD_FEATURES_USB_HUB BIT12
> +#define B_BOARD_FEATURES_TPM BIT13
> +#define B_BOARD_FEATURES_VIIV BIT14
> +#define B_BOARD_FEATURES_FORM_FACTOR_MASK
> (BIT15|BIT16|BIT17|BIT18|BIT19)
> +#define B_BOARD_FEATURES_FORM_FACTOR_PBTX BIT15
> +#define B_BOARD_FEATURES_FORM_FACTOR_ATX BIT16
> +#define B_BOARD_FEATURES_FORM_FACTOR_BTX BIT17
> +#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX BIT18
> +#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
> +#define B_BOARD_FEATURES_MEMORY_TYPE_DDR1 BIT20
> +#define B_BOARD_FEATURES_MEMORY_TYPE_DDR2 BIT21
> +#define B_BOARD_FEATURES_MEMORY_SLOT_MASK BIT23 | BIT22
> +#define V_BOARD_FEATURES_1_MEMORY_SLOT 0 // BIT22=0,
> BIT23=0
> +#define V_BOARD_FEATURES_2_MEMORY_SLOT BIT22 // BIT22=1,
> BIT23=0
> +#define V_BOARD_FEATURES_3_MEMORY_SLOT BIT23 // BIT22=0,
> BIT23=1
> +#define V_BOARD_FEATURES_4_MEMORY_SLOT BIT23 | BIT22 //
> BIT22=1, BIT23=1
> +#define B_BOARD_FEATURES_ALT_MEM_CLK_RT BIT24
> +#define B_BOARD_FEATURES_SLEEP_MASK BIT25
> +#define V_BOARD_FEATURES_SLEEP_S1 0 // BIT25=0
> +#define V_BOARD_FEATURES_SLEEP_S3 BIT25 // BIT25=1
> +#define B_BOARD_FEATURES_3JACK_AUDIO_SOLUTION BIT26 //
> 0/1= 5/3 Rear Jacks
> +#define B_BOARD_FEATURES_DISCRETE_SATA BIT27
> +#define B_BOARD_FEATURES_2_SATA BIT28 // 2SATA instead of
> 4(pre Ich8) or 4 SATA instead of 6(Ich8)
> +#define B_BOARD_FEATURES_RVP BIT29 // Board is an RVP board
> +#define B_BOARD_FEATURES_PORT80_LPC BIT30 // Port80 PCI(0) or
> LPC(1)
> +#define B_BOARD_FEATURES_LIMITED_CPU_SUPPORT BIT31 // Limited
> CPU support
> +#define B_BOARD_FEATURES_PMP_SUPPORT BIT32 // Support for
> over-voltaging memory
> +#define B_BOARD_FEATURES_HW_WATCHDOG_TIMER BIT33 // Support
> for the HW-based 555 Watchdog Timer feature
> +#define B_BOARD_FEATURES_NO_QRT BIT34 // disable QRT
> +#define B_BOARD_FEATURES_VERB_TABLE1 BIT35 // Verb table 1
> +#define B_BOARD_FEATURES_VERB_TABLE2 BIT36 // Verb table 2
> +#define B_BOARD_FEATURES_VERB_TABLE3 BIT37 // Verb table 3
> +#define B_BOARD_FEATURES_VERB_TABLE4 BIT38 // Verb table 4
> +#define B_BOARD_FEATURES_VERB_TABLE5 BIT39 // Reserved for
> Verb table 5
> +#define B_BOARD_FEATURES_VERB_TABLE_MASK BIT35 | BIT36 | BIT37
> | BIT38 | BIT39
> +#define B_BOARD_FEATURES_KENTSFIELD_BLOCK BIT40 // Kentsfield
> not supported
> +#define B_BOARD_FEATURES_KENTSFIELD_WARNING BIT41 //
> Kentsfield warning
> +#define B_BOARD_FEATURES_ESATA_PORT0 BIT42 // E-SATA on
> Port0
> +#define B_BOARD_FEATURES_ESATA_PORT1 BIT43 // E-SATA on
> Port1
> +#define B_BOARD_FEATURES_ESATA_PORT2 BIT44 // E-SATA on
> Port2
> +#define B_BOARD_FEATURES_ESATA_PORT3 BIT45 // E-SATA on
> Port3
> +#define B_BOARD_FEATURES_ESATA_PORT4 BIT46 // E-SATA on
> Port4
> +#define B_BOARD_FEATURES_ESATA_PORT5 BIT47 // E-SATA on
> Port5
> +#define B_BOARD_FEATURES_ECIR BIT48 // Enhanced Consumer
> IR
> +#define B_BOARD_FEATURES_PS2WAKEFROMS5 BIT49 // Wake from
> S5 via PS2 keyboard
> +#define B_BOARD_FEATURES_HDAUDIOLINK BIT50 // HD audio link
> support
> +#define B_BOARD_FEATURES_1_PATA BIT51
> +#define B_BOARD_FEATURES_MOBILE BIT52
> +#define B_BOARD_FEATURES_NO_FLOPPY BIT53
> +#define B_BOARD_FEATURES_DISABLE_UNUSED_FSB BIT54
> +
> +//
> +// Bit 55-58 reserved by PSID support. CPU power requirement below are
> preliminary.
> +// They might be changed.
> +// This is not same as 8.6.1 products so be careful.
> +//
> +#define B_BOARD_FEATURES_CPU_POWER_BITNUM 55
> +#define B_BOARD_FEATURES_CPU_POWER_MASK (BIT55 | BIT56 |
> BIT57 | BIT58)
> +#define B_BOARD_FEATURES_CPU_POWER_35W 0 // Theoretically
> doesn't exist.
> +#define B_BOARD_FEATURES_CPU_POWER_40W BIT55 // 0001
> +#define B_BOARD_FEATURES_CPU_POWER_45W BIT56 // 0010
> +#define B_BOARD_FEATURES_CPU_POWER_50W (BIT55 | BIT56) //
> 0011
> +#define B_BOARD_FEATURES_CPU_POWER_65W BIT57 // 0100
> Wolfdale-H/-M
> +#define B_BOARD_FEATURES_CPU_POWER_70W (BIT55 | BIT57) //
> 0101
> +#define B_BOARD_FEATURES_CPU_POWER_75W (BIT56 | BIT57) //
> 0110
> +#define B_BOARD_FEATURES_CPU_POWER_80W (BIT55 | BIT56 | BIT57)
> // 0111
> +#define B_BOARD_FEATURES_CPU_POWER_95W BIT58 // 1000
> Yorkfield
> +#define B_BOARD_FEATURES_CPU_POWER_100W (BIT55 | BIT58) //
> 1001
> +#define B_BOARD_FEATURES_CPU_POWER_105W (BIT56 | BIT58) //
> 1010
> +#define B_BOARD_FEATURES_CPU_POWER_110W (BIT55 | BIT56 | BIT58)
> // 1011
> +#define B_BOARD_FEATURES_CPU_POWER_130W (BIT57 | BIT58) //
> 1100 XE Yorkfield
> +#define B_BOARD_FEATURES_CPU_POWER_135W (BIT55 | BIT57 | BIT58)
> // 1101
> +#define B_BOARD_FEATURES_CPU_POWER_Over135W (BIT56 | BIT57 |
> BIT58) // 1110 Reserved
> +#define B_BOARD_FEATURES_CPU_POWER_140W (BIT55 | BIT56 | BIT57
> | BIT58) // 1111 Reserved
> +#define B_VV_BOARD_FEATURES BIT59
> +#define B_BOARD_FEATURES_IDCC2_SUPPORT BIT60 // Include IDCC2
> support
> +#define B_BOARD_FEATURES_NO_SATA_PORT2_3 BIT61 // No SATA
> Port2&3 Connector, used with B_BOARD_FEATURES_2_SATA flag
> +#define B_BOARD_FEATURES_FORM_FACTOR_MINI_ITX BIT62
> +#define B_BOARD_FEATURES_NPI_QPI_VOLTAGE BIT63
> +
> +#else
> +
> +#define B_BOARD_FEATURES_CHIPSET_LAN BIT0
> +#define B_BOARD_FEATURES_CHIPSET_VIDEO BIT1
> +#define B_BOARD_FEATURES_VIDEO_SLOT BIT2
> +#define B_BOARD_FEATURES_AA_NOT_FOUND BIT3
> +#define B_BOARD_FEATURES_SIO_NO_COM1 BIT4
> +#define B_BOARD_FEATURES_SIO_COM2 BIT5
> +#define B_BOARD_FEATURES_SIO_NO_PARALLEL BIT6
> +#define B_BOARD_FEATURES_NO_FLOPPY BIT7
> +#define B_BOARD_FEATURES_PS2WAKEFROMS5 BIT8 // Wake
> from S5 via PS2 keyboard
> +#define B_BOARD_FEATURES_ECIR BIT9 // Enhanced
> Consumer IR
> +#define B_BOARD_FEATURES_LEGACY_FREE BIT10
> +#define B_BOARD_FEATURES_MINI_CARD BIT11
> +#define B_BOARD_FEATURES_DISCRETE_1394 BIT12
> +#define B_BOARD_FEATURES_USB_HUB BIT13
> +#define B_BOARD_FEATURES_TPM BIT14
> +#define B_BOARD_FEATURES_FORM_FACTOR_MASK
> (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
> +#define B_BOARD_FEATURES_FORM_FACTOR_PBTX BIT15
> +#define B_BOARD_FEATURES_FORM_FACTOR_ATX BIT16
> +#define B_BOARD_FEATURES_FORM_FACTOR_BTX BIT17
> +#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX BIT18
> +#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
> +#define B_BOARD_FEATURES_FORM_FACTOR_MINI_ITX BIT20
> +#define B_BOARD_FEATURES_MEMORY_TYPE_DDR2 BIT21
> +#define B_BOARD_FEATURES_MEMORY_TYPE_DDR3 BIT22
> +#define B_BOARD_FEATURES_MEMORY_SLOT_MASK (BIT24 | BIT23)
> +#define V_BOARD_FEATURES_1_MEMORY_SLOT 0 // BIT23=0,
> BIT24=0
> +#define V_BOARD_FEATURES_2_MEMORY_SLOT BIT23 //
> BIT23=1, BIT24=0
> +#define V_BOARD_FEATURES_3_MEMORY_SLOT BIT24 //
> BIT23=0, BIT24=1
> +#define V_BOARD_FEATURES_4_MEMORY_SLOT (BIT24 | BIT23) //
> BIT23=1, BIT24=1
> +#define B_BOARD_FEATURES_2_C0_MEMORY_SLOT BIT25 // 2
> Channel 0 memory slot
> +#define B_BOARD_FEATURES_SLEEP_MASK BIT26
> +#define V_BOARD_FEATURES_SLEEP_S1 0 // BIT26=0
> +#define V_BOARD_FEATURES_SLEEP_S3 BIT26 // BIT26=1
> +#define B_BOARD_FEATURES_3JACK_AUDIO_SOLUTION BIT27 //
> 0/1= 5/3 Rear Jacks
> +#define B_BOARD_FEATURES_HDAUDIOLINK BIT28 // HD audio
> link support
> +#define B_BOARD_FEATURES_DISCRETE_SATA BIT29
> +#define B_BOARD_FEATURES_2_SATA BIT30 // 2SATA
> instead of 4(pre Ich8) or 4 SATA instead of 6(Ich8)
> +#define B_BOARD_FEATURES_NO_SATA_PORT2_3 BIT31 // No
> SATA Port2&3 Connector, used with B_BOARD_FEATURES_2_SATA flag
> +#define B_BOARD_FEATURES_RVP BIT32 // Board is an RVP
> board
> +#define B_BOARD_FEATURES_ESATA_PORT0 BIT33 // E-SATA
> on Port0
> +#define B_BOARD_FEATURES_ESATA_PORT1 BIT34 // E-SATA
> on Port1
> +#define B_BOARD_FEATURES_ESATA_PORT2 BIT35 // E-SATA
> on Port2
> +#define B_BOARD_FEATURES_ESATA_PORT3 BIT36 // E-SATA
> on Port3
> +#define B_BOARD_FEATURES_ESATA_PORT4 BIT37 // E-SATA
> on Port4
> +#define B_BOARD_FEATURES_ESATA_PORT5 BIT38 // E-SATA
> on Port5
> +#define B_BOARD_FEATURES_IDCC2_SUPPORT BIT39 // Include
> IDCC2 support
> +#define B_BOARD_FEATURES_NPI_QPI_VOLTAGE BIT40
> +#define B_BOARD_FEATURES_LIMITED_CPU_SUPPORT BIT41 //
> Limited CPU support
> +#define B_BOARD_FEATURES_PMP_SUPPORT BIT42 // Support
> for over-voltaging memory
> +#define B_BOARD_FEATURES_HW_WATCHDOG_TIMER BIT43 //
> Support for the HW-based 555 Watchdog Timer feature
> +#define B_BOARD_FEATURES_LVDS BIT44 // Support for
> LVDS
> +#define B_BOARD_FEATURES_VERB_TABLE_MASK
> (BIT45|BIT46|BIT47|BIT48) // Verb table
> +#define B_BOARD_FEATURES_VERB_TABLE1 BIT45 // Verb
> table 1
> +#define B_BOARD_FEATURES_VERB_TABLE2 BIT46 // Verb
> table 2
> +#define B_BOARD_FEATURES_VERB_TABLE3 BIT47 // Verb
> table 3
> +#define B_BOARD_FEATURES_VERB_TABLE4 BIT48 // Verb
> table 4
> +#define B_BOARD_FEATURES_NO_MINIPCIE BIT49 // Mini PCIe
> slot
> +#define B_BOARD_FEATURES_HDMI_SLOT BIT50 // HDMI slot
> +#define B_BOARD_FEATURES_PS2_HIDE BIT51 // PS2 hide
> +#define B_BOARD_FEATURES_DVID_SLOT BIT52 // DVID slot
> +
> +#define B_BOARD_FEATURES_SIO_COM3 BIT53
> +#define B_BOARD_FEATURES_SIO_COM4 BIT54
> +
> +#define B_BOARD_FEATURES_LAN2 BIT55
> +#define B_BOARD_FEATURES_PCIe_SLOT BIT56
> +#endif
> +
> +typedef UINT64 EFI_BOARD_FEATURES;
> +
> +#pragma pack()
> +
> +//
> +// Global ID for the Platform Boot Mode Protocol.
> +//
> +#define EFI_BOARD_FEATURES_GUID \
> + { 0x94b9e8ae, 0x8877, 0x479a, 0x98, 0x42, 0xf5, 0x97, 0x4b, 0x82, 0xce,
> 0xd3 }
> +
> +extern EFI_GUID gEfiBoardFeaturesGuid;
> +
> +#define BOARD_FEATURES_NAME L"BoardFeatures"
> +
> +#define EFI_BOARD_ID_GUID \
> + { 0x6b2dd245, 0x3f2, 0x414a, 0x8c, 0x2, 0x9f, 0xfc, 0x23, 0x52, 0xe3, 0x1e }
> +#define EFI_BOARD_ID_NAME (L"BoardId")
> +
> +#endif
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h
> new file mode 100644
> index 0000000000..e00e582ce1
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h
> @@ -0,0 +1,156 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + EfiVpdData.h
> +
> +Abstract:
> +
> + Constants and declarations that are common accross PEI and DXE.
> +--*/
> +
> +#ifndef _EFI_VPD_DATA_H_
> +#define _EFI_VPD_DATA_H_
> +
> +
> +#pragma pack(1)
> +
> +//
> +// DMI data
> +//
> +typedef struct {
> +
> + CHAR8 DmiGpnvHeader[4]; // $DMI
> + CHAR8 SystemInfoManufacturer[0x20]; // Structure Type 1 String 1
> + CHAR8 SystemInfoProductName[0x20]; // Structure Type 1 String 2
> + CHAR8 SystemInfoVersion[0x18]; // Structure Type 1 String 3
> + CHAR8 SystemInfoSerialNumber[0x20]; // Structure Type 1 String 4
> + CHAR8 BaseBoardManufacturer[0x20]; // Structure Type 2 String 1
> + CHAR8 BaseBoardProductName[0x20]; // Structure Type 2 String 2
> + CHAR8 BaseBoardVersion[0x18]; // Structure Type 2 String 3
> + CHAR8 BaseBoardSerialNumber[0x20]; // Structure Type 2 String 4
> + CHAR8 ChassisManufacturer[0x20]; // Structure Type 3 String 1
> + UINT8 ChassisType; // Enumerated
> + CHAR8 ChassisVersion[0x18]; // Structure Type 3 String 2
> + CHAR8 ChassisSerialNumber[0x20]; // Structure Type 3 String 3
> + CHAR8 ChassisAssetTag[0x20]; // Structure Type 3 String 4
> + UINT8 MfgAccessKeyWorkspace;
> +
> + UINT8 ChecksumFixupPool[0xd]; // Checksum Fix-ups
> + UINT8 SwitchboardData[4]; // 32 switch switchboard
> + UINT8 IntelReserved; // Reserved for Future Use
> +} DMI_DATA;
> +
> +#define DMI_DATA_GUID \
> + { \
> + 0x70e56c5e, 0x280c, 0x44b0, 0xa4, 0x97, 0x09, 0x68, 0x1a, 0xbc, 0x37, 0x5e
> \
> + }
> +
> +#define DMI_DATA_NAME (L"DmiData")
> +#define ASCII_DMI_DATA_NAME ("DmiData")
> +
> +extern EFI_GUID gDmiDataGuid;
> +extern CHAR16 gDmiDataName[];
> +
> +//
> +// UUID - universally unique system id.
> +//
> +#define UUID_VARIABLE_GUID \
> + { \
> + 0xd357c710, 0x0ada, 0x4717, 0x8d, 0xba, 0xc6, 0xad, 0xc7, 0xcd, 0x2b,
> 0x2a \
> + }
> +
> +#define UUID_VARIABLE_NAME (L"UUID")
> +#define ASCII_UUID_VARIABLE_NAME ("UUID")
> +
> +//
> +// UUID data
> +//
> +typedef struct {
> + UINT32 UuidHigh;
> + UINT32 UuidLow;
> +} SYSTEM_1394_UUID;
> +
> +typedef struct {
> + EFI_GUID SystemUuid; // System Unique ID
> + SYSTEM_1394_UUID System1394Uuid; // Onboard 1394 UUID
> +} UUID_DATA;
> +
> +extern EFI_GUID gUuidVariableGuid;
> +extern CHAR16 gUuidVariableName[];
> +
> +//
> +// MB32GUID for Computrace.
> +//
> +
> +#define MB32_GUID \
> + { 0x539D62BA, 0xDE35, 0x453E, 0xBA, 0xB0, 0x85, 0xDB, 0x8D, 0xA2, 0x42,
> 0xF9 }
> +
> +#define MB32_VARIABLE_NAME (L"MB32")
> +#define ASCII_MB32_VARIABLE_NAME ("MB32")
> +
> +extern EFI_GUID gMb32Guid;
> +extern CHAR16 gMb32VariableName[];
> +
> +//
> +// ACPI OSFR Manufacturer String.
> +//
> +// {72234213-0FD7-48a1-A59F-B41BC107FBCD}
> +//
> +#define ACPI_OSFR_MFG_STRING_VARIABLE_GUID \
> + {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}
> +#define ACPI_OSFR_MFG_STRING_VARIABLE_NAME (L"OcurMfg")
> +#define ASCII_ACPI_OSFR_MF_STRING_VARIABLE_NAME ("OcurMfg")
> +
> +extern EFI_GUID gACPIOSFRMfgStringVariableGuid;
> +
> +
> +//
> +// ACPI OSFR Model String.
> +//
> +// {72234213-0FD7-48a1-A59F-B41BC107FBCD}
> +//
> +#define ACPI_OSFR_MODEL_STRING_VARIABLE_GUID \
> + {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}
> +#define ACPI_OSFR_MODEL_STRING_VARIABLE_NAME (L"OcurModel")
> +#define ASCII_ACPI_OSFR_MODEL_STRING_VARIABLE_NAME
> ("OcurModel")
> +
> +extern EFI_GUID gACPIOSFRModelStringVariableGuid;
> +
> +//
> +// ACPI OSFR Reference Data Block.
> +//
> +// {72234213-0FD7-48a1-A59F-B41BC107FBCD}
> +//
> +#define ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_GUID \
> + {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}
> +#define ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME (L"OcurRef")
> +#define ASCII_ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME
> ("OcurRef")
> +extern EFI_GUID gACPIOSFRRefDataBlockVariableGuid;
> +
> +//
> +// Manufacturing mode GUID
> +//
> +#define MfgMode_GUID \
> + { 0xEF14FD78, 0x0793, 0x4e2b, 0xAC, 0x6D, 0x06, 0x28, 0x47, 0xE0, 0x17,
> 0x91 }
> +
> +#define MFGMODE_VARIABLE_NAME (L"MfgMode")
> +#define ASCII_MFGMODE_VARIABLE_NAME ("MfgMode")
> +
> +typedef struct {
> + UINT8 MfgModeData;
> +} MFG_MODE_VAR;
> +
> +extern EFI_GUID gMfgModeVariableGuid;
> +extern CHAR16 gMfgModeVariableName[];
> +
> +#pragma pack()
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h
> new file mode 100644
> index 0000000000..fd524b8ce5
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h
> @@ -0,0 +1,61 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + FirmwareId.h
> +
> +--*/
> +
> +#ifndef _FirmwareId_h_GUID_included
> +#define _FirmwareId_h_GUID_included
> +
> +
> +#pragma pack(1)
> +
> +//
> +// Firmware ID
> +//
> +
> +#define FIRMWARE_ID_MAX_LENGTH 35
> +
> +typedef struct {
> + CHAR8 BiosId[8];
> + CHAR8 Separator1;
> + CHAR8 OemId[3];
> + CHAR8 Separator2;
> + CHAR8 BuildId[4];
> + CHAR8 Separator3;
> + CHAR8 Century[2];
> + CHAR8 Year[2];
> + CHAR8 Separator4;
> + CHAR8 Month[2];
> + CHAR8 Date[2];
> + CHAR8 Separator5;
> + CHAR8 Hour[2];
> + CHAR8 Minute[2];
> + CHAR8 Dummy[3];
> +} FIRMWARE_ID_DATA;
> +
> +#define OLD_FIRMWARE_ID_GUID \
> + {0xefc071ae, 0x41b8, 0x4018, 0xaf, 0xa7, 0x31, 0x4b, 0x18, 0x5e, 0x57, 0x8b}
> +
> +#define FIRMWARE_ID_GUID \
> + {0x5e559c23, 0x1faa, 0x4ae1, 0x8d, 0x4a, 0xc6, 0xcf, 0x02, 0x6c, 0x76, 0x6f}
> +
> +#define FIRMWARE_ID_NAME L"FirmwareId"
> +#define FIRMWARE_ID_NAME_WITH_PASSWORD FIRMWARE_ID_NAME
> L"H#8,^-!t"
> +
> +extern EFI_GUID gFirmwareIdGuid;
> +extern CHAR16 gFirmwareIdName[];
> +
> +#pragma pack()
> +
> +#endif
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h
> new file mode 100644
> index 0000000000..3cd6c843b1
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h
> @@ -0,0 +1,134 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + HwWatchdogTimerHob.h
> +
> +Abstract:
> +
> + GUID used for Watchdog Timer status in the HOB list.
> +
> +--*/
> +
> +#ifndef _EFI_WATCHDOG_TIMER_HOB_GUID_H_
> +#define _EFI_WATCHDOG_TIMER_HOB_GUID_H_
> +
> +#define EFI_WATCHDOG_TIMER_HOB_GUID \
> + { 0x226cd3f, 0x69b5, 0x4150, 0xac, 0xbe, 0xbf, 0xbf, 0x18, 0xe3, 0x3, 0xd5 }
> +
> +#define EFI_WATCHDOG_TIMER_DEFINITION_HOB_GUID \
> + { 0xd29302b0, 0x11ba, 0x4073, 0xa2, 0x27, 0x53, 0x8d, 0x25, 0x42, 0x70,
> 0x9f }
> +
> +typedef enum {
> + HWWD_NONE,
> + HWWD_TIMER_EXPIRED,
> + HWWD_SPONTANEOUS_REBOOT,
> + HWWD_FORCED_TIMEOUT
> +} HW_WATCHDOG_TIMEOUT;
> +
> +typedef struct {
> + HW_WATCHDOG_TIMEOUT TimeoutStatus;
> +} HW_WATCHDOG_INFO;
> +
> +//
> +// Watchdog timer action values.
> +//
> +#define WDT_ACTION_RESET 0x01 // reload/reset timer
> +#define WDT_ACTION_QUERY_CURRENT_VALUE 0x04 // get current
> value // DON'T NEED FOR OVERCLOCK UTILITY
> +#define WDT_ACTION_QUERY_COUNTDOWN_PERIOD 0x05 // get
> countdown period
> +#define WDT_ACTION_SET_COUNTDOWN_PERIOD 0x06 // set
> countdown period
> +#define WDT_ACTION_QUERY_RUNNING_STATE 0x08 // query if
> running
> +#define WDT_ACTION_SET_RUNNING_STATE 0x09 // start timer
> +#define WDT_ACTION_QUERY_STOPPED_STATE 0x0A // query if
> stopped
> +#define WDT_ACTION_SET_STOPPED_STATE 0x0B // stop timer
> +#define WDT_ACTION_QUERY_STATUS 0x20 // is current boot cause
> by wdt timeout?
> +#define WDT_ACTION_SET_STATUS 0x21 // resets wdt status bit
> +
> +//
> +// Watchdog timer instruction values.
> +//
> +#define WDT_INSTR_VALUE_MASK 0x03 // Mask for just the value
> +#define WDT_INSTR_READ_CMP_VALUE 0x00 // Read / compare
> value
> +#define WDT_INSTR_READ_COUNTDOWN 0x01 // read countdown
> value
> +#define WDT_INSTR_WRITE_VALUE 0x02 // Write value
> +#define WDT_INSTR_WRITE_COUNTDOWN 0x03 // write countdown
> value
> +#define WDT_INSTR_PRESERVE_REG 0x80 // preserve reg; used in
> Write Value / Write Countdown
> +#define WDT_INSTR_WRITE_VALUE_PRES (0x02 |
> WDT_INSTR_PRESERVE_REG) // Write value with preserve
> +#define WDT_INSTR_WRITE_COUNTDOWN_PRES (0x03 |
> WDT_INSTR_PRESERVE_REG) // write countdown value with preserve
> +
> +//
> +// The Generic Address Structure is defined in the ACPI Specification and
> should only be
> +// changed to match updated revisions of that specification. The
> GAS_ADDRESS_SPACE and
> +// GAS_ACCESS_SIZE enumerations are also defined by the ACPI
> Specification.
> +//
> +typedef enum {
> + GAS_SYSTEM_MEMORY,
> + GAS_SYSTEM_IO,
> + GAS_PCI_CONFIG_SPACE,
> + GAS_EMBEDDED_CONTROLLER,
> + GAS_SMBUS
> +} GAS_ADDRESS_SPACE;
> +
> +typedef enum {
> + GAS_UNDEFINED,
> + GAS_BYTE_ACCESS,
> + GAS_WORD_ACCESS,
> + GAS_DWORD_ACCESS,
> + GAS_QWORD_ACCESS
> +} GAS_ACCESS_SIZE;
> +
> +#pragma pack(1)
> +
> +typedef struct {
> + UINT8 AddressSpaceId;
> + UINT8 RegisterBitWidth;
> + UINT8 RegisterBitOffset;
> + UINT8 AccessSize;
> + UINT64 Address;
> +} GENERIC_ADDRESS_STRUCTURE;
> +
> +//
> +// GAS_SYSTEM_MEMORY - When used as the AddressSpaceId, the 64-bit
> physical memory address
> +// of the register. 32-bit platforms must have the high DWORD
> set to 0.
> +// GAS_SYSTEM_IO - The 64-bit I/O address of the register. 32-bit
> platforms must have
> +// the high DWORD set to 0.
> +// GAS_PCI_CONFIG_SPACE - PCI Configuration space addresses must be
> confined to devices on PCI
> +// Sepment Group 0, Bus 0. This restriction exists to
> accommodate access
> +// to fixed hardware prior to PCI bus enumeration. The format
> of addresses
> +// are defined as follows:
> +// Highest WORD: Reserved and must be -0-
> +// ... PCI Device number on bus 0
> +// ... PCI Function number
> +// Lowest WORD: Offset in the configuration space header.
> +//
> +
> +typedef struct {
> + UINT8 WdAction;
> + UINT8 Flag;
> + UINT16 Res;
> + GENERIC_ADDRESS_STRUCTURE GenericAddressStructures;
> + UINT32 Value;
> + UINT32 Mask;
> +} WD_INSTRUCTION;
> +
> +typedef struct {
> + UINT32 TimerPeriod;
> + UINT32 MaxTimerCount;
> + UINT32 MinTimerCount;
> + UINT16 InstructionCount;
> + WD_INSTRUCTION ActionDefinitions[1];
> +} WD_HOB_DEFINITION;
> +
> +#pragma pack()
> +
> +extern EFI_GUID gWatchdogTimerHobGuid;
> +extern EFI_GUID gWatchdogTimerDefinitionHobGuid;
> +
> +#endif // _EFI_WATCHDOG_TIMER_HOB_GUID_H_
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/IdccData.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/IdccData.h
> new file mode 100644
> index 0000000000..7e3b965666
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/IdccData.h
> @@ -0,0 +1,104 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + IdccData.h
> +
> +Abstract:
> +
> +--*/
> +
> +#ifndef _IDCCDATAHUB_GUID_H_
> +#define _IDCCDATAHUB_GUID_H_
> +
> +//
> +// This GUID is for the IDCC related data found in the Data Hub.
> +//
> +#define IDCC_DATA_HUB_GUID \
> + { 0x788e1d9f, 0x1eab, 0x47d2, 0xa2, 0xf3, 0x78, 0xca, 0xe8, 0x7d, 0x60,
> 0x12 }
> +
> +extern EFI_GUID gIdccDataHubGuid;
> +
> +#pragma pack(1)
> +
> +typedef struct {
> + UINT32 Type;
> + UINT32 RecordLength;
> +} EFI_IDCC_DATA_HEADER;
> +
> +typedef struct {
> + EFI_IDCC_DATA_HEADER IdccHeader;
> + UINT32 Tcontrol;
> +} EFI_IDCC_TCONTROL;
> +
> +typedef struct {
> + UINT32 EntryCount;
> +} EFI_IDCC_CLOCK_COMMON;
> +
> +typedef struct {
> + UINT8 Polarity;
> + UINT8 Percent;
> + UINT32 FpValue;
> +} EFI_IDCC_TYPE_2_DATA;
> +
> +typedef struct {
> + UINT8 SetupVal;
> + UINT32 FpValue;
> +} EFI_IDCC_TYPE_3_4_DATA;
> +
> +typedef struct {
> + EFI_IDCC_DATA_HEADER IdccHeader;
> + UINT32 ProcessorRatio;
> +} EFI_IDCC_PROCESSOR_RATIO;
> +
> +typedef struct {
> + EFI_IDCC_DATA_HEADER IdccHeader;
> + UINT32 BoardFormFactor;
> +} EFI_IDCC_BOARD_FORM_FACTOR;
> +
> +typedef struct {
> + EFI_IDCC_DATA_HEADER IdccHeader;
> + UINT32 ProcessorInfo;
> +} EFI_IDCC_PROCESSOR_INFO;
> +
> +#define EFI_IDCC_PROCESSOR_UNCON (1 << 0) // Bit 0: UnCon CPU
> +#define EFI_IDCC_PROCESSOR_UNLOCK (1 << 1) // Bit 1: UnLock CPU
> +#define EFI_IDCC_PROCESSOR_CNR (1 << 2) // Bit 2: CNR CPU
> +#define EFI_IDCC_PROCESSOR_KNF (1 << 3) // Bit 3: KNF CPU
> +
> +typedef struct {
> + EFI_IDCC_DATA_HEADER IdccHeader;
> + UINT32 MinFSB;
> + UINT32 MaxFSB;
> + UINT8 StepFSB;
> +} EFI_IDCC_FSB_DATA;
> +
> +#pragma pack()
> +
> +#define EFI_IDCC_POSITIVE 0
> +#define EFI_IDCC_NEGATIVE 1
> +
> +//
> +// Board Form Factor equates.
> +//
> +#define ATX_FORM_FACTOR 0x00
> +#define BTX_FORM_FACTOR 0x01
> +
> +
> +#define EFI_IDCC_TCONTROL_TYPE 1
> +#define EFI_IDCC_FSB_TYPE 2
> +#define EFI_IDCC_PCI_TYPE 3
> +#define EFI_IDCC_PCIE_TYPE 4
> +#define EFI_IDCC_PROC_RATIO_TYPE 5
> +#define EFI_IDCC_BOARD_FORM_FACTOR_TYPE 6
> +#define EFI_IDCC_PROC_INFO_TYPE 7
> +#define EFI_IDCC_FSB_DATA_TYPE 8
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/ItkData.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/ItkData.h
> new file mode 100644
> index 0000000000..e7bd29e6e4
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/ItkData.h
> @@ -0,0 +1,70 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + ItkData.h
> +
> +Abstract:
> +
> +--*/
> +
> +#ifndef _ITKDATAHUB_GUID_H_
> +#define _ITKDATAHUB_GUID_H_
> +
> +//
> +// This GUID is for the ITK related data found in the Data Hub {E7060843-
> A336-4d5b-9598-13402F5D7375}
> +//
> +#define ITK_DATA_HUB_GUID \
> + { 0xe7060843, 0xa336, 0x4d5b, 0x95, 0x98, 0x13, 0x40, 0x2f, 0x5d, 0x73,
> 0x75 }
> +
> +extern EFI_GUID gItkDataHubGuid;
> +
> +//
> +// This GUID is for the ITK related data found in a Variable {3812723D-7E48-
> 4e29-BC27-F5A39AC94EF1}
> +//
> +#define ITK_DATA_VAR_GUID \
> + { 0x3812723d, 0x7e48, 0x4e29, 0xbc, 0x27, 0xf5, 0xa3, 0x9a, 0xc9, 0x4e,
> 0xf1 }
> +
> +extern EFI_GUID gItkDataVarGuid;
> +
> +#define ITK_DATA_VAR_NAME L"ItkDataVar"
> +
> +extern CHAR16 gItkDataVarName[];
> +
> +#define ITK_BIOS_MOD_VAR_NAME L"ItkBiosModVar"
> +
> +extern CHAR16 gItkBiosModVarName[];
> +
> +#pragma pack(1)
> +typedef struct {
> + UINT32 Type;
> + UINT32 RecordLength;
> +} EFI_ITK_DATA_HEADER;
> +
> +typedef struct {
> + EFI_ITK_DATA_HEADER ItkHeader;
> + UINT32 HecetaAddress;
> +} EFI_ITK_HECETA_ADDRESS;
> +
> +typedef struct {
> + UINT16 VarEqName;
> + UINT16 VarEqValue;
> +} EFI_ITK_VAR_EQ_RECORD;
> +
> +typedef struct {
> + EFI_ITK_DATA_HEADER ItkHeader;
> + EFI_ITK_VAR_EQ_RECORD VarEqRecord[0x10000];
> +} EFI_ITK_VAR_EQ;
> +#pragma pack()
> +
> +#define EFI_ITK_HECETA_ADDRESS_TYPE 1
> +#define EFI_ITK_MOBILE_BIOS_TYPE 2
> +#define EFI_ITK_VAR_EQ_TYPE 3
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h
> new file mode 100644
> index 0000000000..0fe759a16e
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h
> @@ -0,0 +1,32 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +Module Name:
> +
> + MemoryConfigData.h
> +
> +Abstract:
> +
> + GUID used for Memory Configuration Data entries in the HOB list.
> +
> +--*/
> +
> +#ifndef _MEMORY_CONFIG_DATA_GUID_H_
> +#define _MEMORY_CONFIG_DATA_GUID_H_
> +
> +#define EFI_MEMORY_CONFIG_DATA_GUID \
> + { \
> + 0x80dbd530, 0xb74c, 0x4f11, 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31
> \
> + }
> +
> +extern EFI_GUID gEfiMemoryConfigDataGuid;
> +extern CHAR16 EfiMemoryConfigVariable[];
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h
> new file mode 100644
> index 0000000000..e7bbcf67c9
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h
> @@ -0,0 +1,85 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + OsSelection.h
> +
> +Abstract:
> +
> + GUID used for LPSS, SCC and LPE configuration data entries in the HOB list.
> +
> +--*/
> +
> +#ifndef _OS_SELECTION_GUID_H_
> +#define _OS_SELECTION_GUID_H_
> +
> +#ifndef ECP_FLAG
> +#include <PiPei.h>
> +
> +#include <Library/HobLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/DebugLib.h>
> +#endif
> +
> +#define ANDROID 1
> +
> +#define EFI_OS_SELECTION_VARIABLE_GUID \
> + { \
> + 0x86843f56, 0x675d, 0x40a5, 0x95, 0x30, 0xbc, 0x85, 0x83, 0x72, 0xf1, 0x03
> \
> + }
> +
> +extern EFI_GUID gOsSelectionVariableGuid;
> +
> +#pragma pack(1)
> +
> +typedef struct {
> + UINT8 LpssPciModeEnabled;
> + //SCC
> + UINT8 LpsseMMCEnabled;
> + UINT8 LpssSdioEnabled;
> + UINT8 LpssSdcardEnabled;
> + UINT8 LpssSdCardSDR25Enabled;
> + UINT8 LpssSdCardDDR50Enabled;
> + UINT8 LpssMipiHsi;
> + UINT8 LpsseMMC45Enabled;
> + UINT8 LpsseMMC45DDR50Enabled;
> + UINT8 LpsseMMC45HS200Enabled;
> + UINT8 LpsseMMC45RetuneTimerValue;
> + UINT8 eMMCBootMode;
> + //LPSS2
> + UINT8 LpssDma1Enabled;
> + UINT8 LpssI2C0Enabled;
> + UINT8 LpssI2C1Enabled;
> + UINT8 LpssI2C2Enabled;
> + UINT8 LpssI2C3Enabled;
> + UINT8 LpssI2C4Enabled;
> + UINT8 LpssI2C5Enabled;
> + UINT8 LpssI2C6Enabled;
> + //LPSS1
> + UINT8 LpssDma0Enabled;
> + UINT8 LpssPwm0Enabled;
> + UINT8 LpssPwm1Enabled;
> + UINT8 LpssHsuart0Enabled;
> + UINT8 LpssHsuart1Enabled;
> + UINT8 LpssSpiEnabled;
> + UINT8 I2CTouchAd;
> +} EFI_PLATFORM_LPSS_DATA;
> +
> +typedef struct _EFI_OS_SELECTION_HOB {
> + UINT8 OsSelection;
> + UINT8 OsSelectionChanged;
> + UINT8 Lpe;
> + UINT8 PchAzalia;
> + EFI_PLATFORM_LPSS_DATA LpssData;
> +} EFI_OS_SELECTION_HOB;
> +
> +#pragma pack()
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h
> new file mode 100644
> index 0000000000..46c45b0303
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h
> @@ -0,0 +1,39 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + PciLanInfo.h
> +
> +Abstract:
> +
> +--*/
> +
> +#ifndef _PCI_LAN_INFO_GUID_H_
> +#define _PCI_LAN_INFO_GUID_H_
> +
> +#pragma pack(1)
> +
> +//
> +// structure used for Pci Lan variable
> +//
> +typedef struct {
> + UINT8 PciBus;
> + UINT8 PciDevice;
> + UINT8 PciFunction;
> +} PCI_LAN_INFO;
> +
> +#pragma pack()
> +
> +#define EFI_PCI_LAN_INFO_GUID \
> + {0xd9a1427, 0xe02a, 0x437d, 0x92, 0x6b, 0xaa, 0x52, 0x1f, 0xd7, 0x22, 0xba};
> +
> +extern EFI_GUID gEfiPciLanInfoGuid;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h
> new file mode 100644
> index 0000000000..f1756662bd
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h
> @@ -0,0 +1,180 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + PlatformCpuInfo.h
> +
> +Abstract:
> +
> + GUID used for Platform CPU Info Data entries in the HOB list.
> +
> +--*/
> +
> +#ifndef _PLATFORM_CPU_INFO_GUID_H_
> +#define _PLATFORM_CPU_INFO_GUID_H_
> +
> +#include "CpuType.h"
> +#include <Library/CpuIA32.h>
> +
> +#define EFI_PLATFORM_CPU_INFO_GUID \
> + {\
> + 0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc
> \
> + }
> +
> +extern EFI_GUID gEfiPlatformCpuInfoGuid;
> +extern CHAR16 EfiPlatformCpuInfoVariable[];
> +
> +//
> +// Tri-state for feature capabilities and enable/disable.
> +// [0] clear=feature isn't capable
> +// [0] set =feature is capable
> +// [1] clear=feature is disabled
> +// [1] set =feature is enabled
> +//
> +#define CPU_FEATURES_CAPABLE BIT0
> +#define CPU_FEATURES_ENABLE BIT1
> +
> +#define MAX_CACHE_DESCRIPTORS 64
> +#define MAXIMUM_CPU_BRAND_STRING_LENGTH 48
> +
> +#pragma pack(1)
> +
> +typedef struct {
> + UINT32 FullCpuId; // [31:0] & 0x0FFF0FFF
> + UINT32 FullFamilyModelId; // [31:0] & 0x0FFF0FF0
> + UINT8 ExtendedFamilyId; // [27:20]
> + UINT8 ExtendedModelId; // [19:16]
> + UINT8 ProcessorType; // [13:11]
> + UINT8 FamilyId; // [11:8]
> + UINT8 Model; // [7:4]
> + UINT8 SteppingId; // [3:0]
> +} EFI_CPU_VERSION_INFO; // CPUID.1.EAX
> +
> +typedef struct {
> + UINT32 L1InstructionCacheSize;
> + UINT32 L1DataCacheSize;
> + UINT32 L2CacheSize;
> + UINT32 L3CacheSize;
> + UINT32 TraceCacheSize;
> + UINT8 CacheDescriptor[MAX_CACHE_DESCRIPTORS];
> +} EFI_CPU_CACHE_INFO; // CPUID.2.EAX
> +
> +typedef struct {
> + UINT8 PhysicalPackages;
> + UINT8 LogicalProcessorsPerPhysicalPackage;
> + UINT8 CoresPerPhysicalPackage;
> + UINT8 ThreadsPerCore;
> +} EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX
> +
> +typedef struct {
> + UINT32 RegEdx; // CPUID.5.EAX
> + UINT8 MaxCState;
> + UINT8 C0SubCStatesMwait; // EDX [3:0]
> + UINT8 C1SubCStatesMwait; // EDX [7:4]
> + UINT8 C2SubCStatesMwait; // EDX [11:8]
> + UINT8 C3SubCStatesMwait; // EDX [15:12]
> + UINT8 C4SubCStatesMwait; // EDX [19:16]
> + UINT8 C5SubCStatesMwait; // EDX [23:20]
> + UINT8 C6SubCStatesMwait; // EDX [27:24]
> + UINT8 C7SubCStatesMwait; // EDX [31:28]
> + UINT8 MonitorMwaitSupport; // ECX [0]
> + UINT8 InterruptsBreakMwait; // ECX [1]
> +} EFI_CPU_CSTATE_INFO; // CPUID.5.EAX
> +
> +typedef struct {
> + UINT8 Turbo; // EAX [1]
> + UINT8 PECI; // EAX [0]
> + UINT8 NumIntThresholds; // EBX [3:0]
> + UINT8 HwCoordinationFeedback; // ECX [0]
> +} EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX
> +
> +//
> +// IMPORTANT: Each CPU feature enabling entry is assumed a tri-state
> variable.
> +// - Keep the respective feature entry variable as default value (0x00)
> +// if the CPU is not capable for the feature.
> +// - Use the specially defined programming convention to update the
> variable
> +// to indicate capable, enable or disable.
> +// ie. F_CAPABLE for feature available
> +// F_ENABLE for feature enable
> +// F_DISABLE for feature disable
> +//
> +typedef struct {
> + EFI_CPUID_REGISTER Regs; // CPUID.1.EAX
> + UINT8 Xapic; // ECX [21]
> + UINT8 SSE4_2; // ECX [20]
> + UINT8 SSE4_1; // ECX [19]
> + UINT8 Dca; // ECX [18]
> + UINT8 SupSSE3; // ECX [9]
> + UINT8 Tm2; // ECX [8]
> + UINT8 Eist; // ECX [7]
> + UINT8 Lt; // ECX [6]
> + UINT8 Vt; // ECX [5]
> + UINT8 Mwait; // ECX [3]
> + UINT8 SSE3; // ECX [0]
> + UINT8 Tcc; // EDX [29]
> + UINT8 Mt; // EDX [28]
> + UINT8 SSE2; // EDX [26]
> + UINT8 SSE; // EDX [25]
> + UINT8 MMX; // EDX [23]
> + EFI_CPUID_REGISTER ExtRegs; // CPUID.80000001.EAX
> + UINT8 ExtLahfSahf64; // ECX [0]
> + UINT8 ExtIntel64; // EDX [29]
> + UINT8 ExtXd; // EDX [20]
> + UINT8 ExtSysCallRet64; // EDX [11]
> + UINT16 Ht; // CPUID.0B.EAX EBX [15:0]
> +} EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX
> +
> +typedef struct {
> + UINT8 PhysicalBits;
> + UINT8 VirtualBits;
> +} EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX
> +
> +typedef struct {
> + UINT8 PlatformID; // MSR 0x17 [52:50]
> + UINT32 MicrocodeRevision; // MSR 0x8B [63:32]
> + UINT8 MaxEfficiencyRatio; // MSR 0xCE [47:40]
> + UINT8 DdrRatioUnlockCap; // MSR 0xCE [30]
> + UINT8 TdcTdpLimitsTurbo; // MSR 0xCE [29]
> + UINT8 RatioLimitsTurbo; // MSR 0xCE [28]
> + UINT8 PreProduction; // MSR 0xCE [27]
> + UINT8 DcuModeSelect; // MSR 0xCE [26]
> + UINT8 MaxNonTurboRatio; // MSR 0xCE [15:8]
> + UINT8 Emrr; // MSR 0xFE [12]
> + UINT8 Smrr; // MSR 0xFE [11]
> + UINT8 VariableMtrrCount; // MSR 0xFE [7:0]
> + UINT16 PState; // MSR 0x198 [15:0]
> + UINT8 TccActivationTemperature; // MSR 0x1A2 [23:16]
> + UINT8 TemperatureControlOffset; // MSR 0x1A2 [15:8]
> + UINT32 PCIeBar; // MSR 0x300 [39:20]
> + UINT8 PCIeBarSizeMB; // MSR 0x300 [3:1]
> +} EFI_MSR_FEATURES;
> +
> +typedef struct {
> + BOOLEAN IsIntelProcessor;
> + UINT8
> BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1];
> + UINT32 CpuidMaxInputValue;
> + UINT32 CpuidMaxExtInputValue;
> + EFI_CPU_UARCH CpuUarch;
> + EFI_CPU_FAMILY CpuFamily;
> + EFI_CPU_PLATFORM CpuPlatform;
> + EFI_CPU_TYPE CpuType;
> + EFI_CPU_VERSION_INFO CpuVersion;
> + EFI_CPU_CACHE_INFO CpuCache;
> + EFI_CPU_FEATURES CpuFeatures;
> + EFI_CPU_CSTATE_INFO CpuCState;
> + EFI_CPU_PACKAGE_INFO CpuPackage;
> + EFI_CPU_POWER_MANAGEMENT CpuPowerManagement;
> + EFI_CPU_ADDRESS_BITS CpuAddress;
> + EFI_MSR_FEATURES Msr;
> +} EFI_PLATFORM_CPU_INFO;
> +
> +#pragma pack()
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h
> new file mode 100644
> index 0000000000..cac31e2a40
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h
> @@ -0,0 +1,433 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +Module Name:
> +
> + PlatformInfo.h
> +
> +Abstract:
> +
> + GUID used for Platform Info Data entries in the HOB list.
> +
> +--*/
> +
> +#ifndef _PLATFORM_INFO_GUID_H_
> +#define _PLATFORM_INFO_GUID_H_
> +
> +#ifndef ECP_FLAG
> +#include <PiPei.h>
> +
> +#include <Library/HobLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/SmbusLib.h>
> +#include <IndustryStandard/SmBus.h>
> +#endif
> +
> +#define PLATFORM_INFO_REVISION = 1 // Revision id for current
> platform information struct.
> +
> +//
> +// Start::BayLake Board Defines
> +//
> +#define BOARD_REVISION_DEFAULT = 0xff
> +#define UNKNOWN_FABID 0x0F
> +#define FAB_ID_MASK 0x0F
> +#define BOARD_ID_2 0x01
> +#define BOARD_ID_1 0x40
> +#define BOARD_ID_0 0x04
> +
> +#define BOARD_ID_DT_CRB 0x0
> +#define BOARD_ID_DT_VLVR 0x1
> +#define BOARD_ID_SVP_VLV 0xC
> +#define BOARD_ID_SVP_EV_VLV 0xD
> +//
> +// End::BayLake Board Defines
> +//
> +
> +//
> +// Start::Alpine Valley Board Defines
> +//
> +#define DC_ID_DDR3L 0x00
> +#define DC_ID_DDR3 0x04
> +#define DC_ID_LPDDR3 0x02
> +#define DC_ID_LPDDR2 0x06
> +#define DC_ID_DDR4 0x01
> +#define DC_ID_DDR3L_ECC 0x05
> +#define DC_ID_NO_MEM 0x07
> +//
> +// End::Alpine Valley Board Defines
> +//
> +
> +#define MAX_FAB_ID_RETRY_COUNT 100
> +#define MAX_FAB_ID_CHECK_COUNT 3
> +
> +#define PLATFORM_INFO_HOB_REVISION 0x1
> +
> +#define EFI_PLATFORM_INFO_GUID \
> + { \
> + 0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \
> + }
> +
> +extern EFI_GUID gEfiPlatformInfoGuid;
> +
> +typedef enum {
> + FlavorUnknown = 0,
> +
> + //
> + // Mobile
> + //
> + FlavorMobile = 1,
> +
> + //
> + // Desktop
> + //
> + FlavorDesktop = 2,
> +
> + //
> + // Tablet
> + //
> + FlavorTablet = 3
> +} PLATFORM_FLAVOR;
> +
> +#pragma pack(1)
> +
> +typedef struct {
> + UINT16 PciResourceIoBase;
> + UINT16 PciResourceIoLimit;
> + UINT32 PciResourceMem32Base;
> + UINT32 PciResourceMem32Limit;
> + UINT64 PciResourceMem64Base;
> + UINT64 PciResourceMem64Limit;
> + UINT64 PciExpressBase;
> + UINT32 PciExpressSize;
> + UINT8 PciHostAddressWidth;
> + UINT8 PciResourceMinSecBus;
> +} EFI_PLATFORM_PCI_DATA;
> +
> +typedef struct {
> + UINT8 CpuAddressWidth;
> + UINT32 CpuFamilyStepping;
> +} EFI_PLATFORM_CPU_DATA;
> +
> +typedef struct {
> + UINT8 SysIoApicEnable;
> + UINT8 SysSioExist;
> +} EFI_PLATFORM_SYS_DATA;
> +
> +typedef struct {
> + UINT32 MemTolm;
> + UINT32 MemMaxTolm;
> + UINT32 MemTsegSize;
> + UINT32 MemTsegBase;
> + UINT32 MemIedSize;
> + UINT32 MemIgdSize;
> + UINT32 MemIgdBase;
> + UINT32 MemIgdGttSize;
> + UINT32 MemIgdGttBase;
> + UINT64 MemMir0;
> + UINT64 MemMir1;
> + UINT32 MemConfigSize;
> + UINT16 MmioSize;
> + UINT8 DdrFreq;
> + UINT8 DdrType;
> + UINT32 MemSize;
> + BOOLEAN EccSupport;
> + UINT8 Reserved[3];
> + UINT16 DimmSize[2];
> +} EFI_PLATFORM_MEM_DATA;
> +
> +
> +typedef struct {
> + UINT32 IgdOpRegionAddress; // IGD OpRegion Starting Address
> + UINT8 IgdBootType; // IGD Boot Display Device
> + UINT8 IgdPanelType; // IGD Panel Type CMOs option
> + UINT8 IgdTvFormat; // IGD TV Format CMOS option
> + UINT8 IgdTvMinor; // IGD TV Minor Format CMOS option
> + UINT8 IgdPanelScaling; // IGD Panel Scaling
> + UINT8 IgdBlcConfig; // IGD BLC Configuration
> + UINT8 IgdBiaConfig; // IGD BIA Configuration
> + UINT8 IgdSscConfig; // IGD SSC Configuration
> + UINT8 IgdDvmtMemSize; // IGD DVMT Memory Size
> + UINT8 IgdFunc1Enable; // IGD Function 1 Enable
> + UINT8 IgdHpllVco; // HPLL VCO
> + UINT8 IgdSciSmiMode; // GMCH SMI/SCI mode (0=SCI)
> + UINT8 IgdPAVP; // IGD PAVP data
> +} EFI_PLATFORM_IGD_DATA;
> +
> +typedef enum {
> + BOARD_ID_AV_SVP = 0x0, // Alpine Valley Board
> + BOARD_ID_BL_RVP = 0x2, // BayLake Board (RVP)
> + BOARD_ID_BL_FFRD8 = 0x3, // FFRD8 b'0011
> + BOARD_ID_BL_FFRD = 0x4, // BayLake Board (FFRD)
> + BOARD_ID_BL_RVP_DDR3L = 0x5, // BayLake Board (RVP DDR3L)
> + BOARD_ID_BL_STHI = 0x7, // PPV- STHI Board
> + BOARD_ID_BB_RVP = 0x20, // Bayley Bay Board
> + BOARD_ID_BS_RVP = 0x30, // Bakersport Board
> + BOARD_ID_CVH = 0x90, // Crestview Hills
> + BOARD_ID_MINNOW2 = 0xA0, // MinnowBorad Max
> + BOARD_ID_MINNOW2_TURBOT = 0xB0 // MinnowBoard Turbot
> +
> +} BOARD_ID_LIST;
> +
> +typedef enum {
> + FAB1 = 0,
> + FAB2 = 1,
> + FAB3 = 2
> +} FAB_ID_LIST;
> +
> +typedef enum {
> + PR0 = 0, // FFRD PR0
> + PR05 = 1, // FFRD PR0.3 and PR 0.5
> + PR1 = 2, // FFRD PR1
> + PR11 = 3 // FFRD PR1.1
> +} FFRD_ID_LIST;
> +
> +
> +//
> +// VLV2 GPIO GROUP OFFSET
> +//
> +#define GPIO_SCORE_OFFSET 0x0000
> +#define GPIO_NCORE_OFFSET 0x1000
> +#define GPIO_SSUS_OFFSET 0x2000
> +
> +//
> +// GPIO Initialization Data Structure for BayLake.
> +// SC = SCORE, SS= SSUS
> +// Note: NC doesn't support GPIO functionality in IO access mode, only
> support in MMIO access mode.
> +//
> +
> +//
> +// IO space
> +//
> +typedef struct{
> + UINT32 Use_Sel_SC0;
> + UINT32 Use_Sel_SC1;
> + UINT32 Use_Sel_SC2;
> + UINT32 Use_Sel_SS;
> +
> + UINT32 Io_Sel_SC0;
> + UINT32 Io_Sel_SC1;
> + UINT32 Io_Sel_SC2;
> + UINT32 Io_Sel_SS;
> +
> + UINT32 GP_Lvl_SC0;
> + UINT32 GP_Lvl_SC1;
> + UINT32 GP_Lvl_SC2;
> + UINT32 GP_Lvl_SS;
> +
> + UINT32 TPE_SC0;
> + UINT32 TPE_SS;
> +
> + UINT32 TNE_SC0;
> + UINT32 TNE_SS;
> +
> + UINT32 TS_SC0;
> + UINT32 TS_SS;
> +
> + UINT32 WE_SS;
> +} CFIO_INIT_STRUCT;
> +
> +
> +
> +//
> +// CFIO PAD configuration Registers
> +//
> +//
> +// Memory space
> +//
> +typedef union {
> + UINT32 dw;
> + struct {
> + UINT32 Func_Pin_Mux:3; // 0:2 Function of CFIO selection
> + UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check
> Width
> + UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate
> + UINT32 Pull_assign:2; // 7:8 Pull assignment
> + UINT32 Pull_strength:2; // 9:10 Pull strength
> + UINT32 Bypass_flop:1; // 11 Bypass flop
> + UINT32 Filter_en:1; // 12 Filter Enable
> + UINT32 Hist_ctrl:2; // 13:14 hysteresis control
> + UINT32 Hist_enb:1; // 15 Hysteresis enable, active low
> + UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or
> output
> + UINT32 Reserved:3; // 22:24 Reserved
> + UINT32 TPE:1; // 25 Trigger Positive Edge Enable
> + UINT32 TNE:1; // 26 Trigger Negative Edge Enable
> + UINT32 Reserved2:3; // 27:29 Reserved
> + UINT32 i1p5sel:1; // 30
> + UINT32 IODEN:1; // 31 : Open Drain enable. Active high
> + } r;
> +} PAD_CONF0;
> +
> +typedef union{
> + UINT32 dw;
> + struct {
> + UINT32 instr:16; // 0:15 Pad (N) strength.
> + UINT32 ipstr:16; // 16:31 Pad (P) strength.
> + }r;
> +} PAD_CONF1;
> +
> +typedef union{
> + UINT32 dw;
> + struct {
> + UINT32 pad_val:1; // 0 These registers are implemented as dual
> read/write with dedicated storage each.
> + UINT32 ioutenb:1; // 1 output enable
> + UINT32 iinenb:1; // 2 input enable
> + UINT32 Reserved:29; // 3:31 Reserved
> + }r;
> +} PAD_VAL;
> +
> +typedef union{
> + UINT32 GPI;
> + struct {
> + UINT32 ihbpen:1; // 0 Pad high by pass enable
> + UINT32 ihbpinen:1; // 1 Pad high by pass input
> + UINT32 instaticen:1; // 2 TBD
> + UINT32 ipstaticen:1; // 3 TBD
> + UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the
> strap pin value on this pad, if exists.
> + UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap
> pin value and it exist for the specific pad, this value will be used.
> + UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing
> + }r;
> +} PAD_DFT;
> +
> +//
> +// GPIO_USAGE value need to matche the PAD_VAL input/output enable
> bits.
> +//
> +typedef enum {
> + Native = 0xFF, // Native, no need to set PAD_VALUE
> + GPI = 2, // GPI, input only in PAD_VALUE
> + GPO = 4, // GPO, output only in PAD_VALUE
> + GPIO = 0, // GPIO, input & output
> + TRISTS = 6, // Tri-State
> + GPIO_NONE
> +} GPIO_USAGE;
> +
> +typedef enum {
> + LO = 0,
> + HI = 1,
> + NA = 0xFF
> +} GPO_D4;
> +
> +typedef enum {
> + F0 = 0,
> + F1 = 1,
> + F2 = 2,
> + F3 = 3,
> + F4 = 4,
> + F5 = 5,
> + F6 = 6,
> + F7 = 7
> +} GPIO_FUNC_NUM;
> +
> +//
> +// Mapping to CONF0 bit 27:24
> +// Note: Assume "Direct Irq En" is not set, unless specially notified.
> +//
> +typedef enum {
> + TRIG_ = 0,
> + TRIG_Edge_High = /*BIT3 |*/ BIT1, // Positive Edge (Rasing)
> + TRIG_Edge_Low = /*BIT3 |*/ BIT2, // Negative Edge (Falling)
> + TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1, // Both Edge
> + TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0, // Level High
> + TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0, // Level Low
> +} INT_TYPE;
> +
> +typedef enum {
> + P_20K_H, // Pull Up 20K
> + P_20K_L, // Pull Down 20K
> + P_10K_H, // Pull Up 10K
> + P_10K_L, // Pull Down 10K
> + P_2K_H, // Pull Up 2K
> + P_2K_L, // Pull Down 2K
> + P_NONE // Pull None
> +} PULL_TYPE;
> +
> +#ifdef EFI_DEBUG
> + #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap,
> int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/
> TRIG_##int_type, P_##pull, offset}
> +#else
> + #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap,
> int_type, pull, offset) { usage, gpod4, func, /*int_cap,*/
> TRIG_##int_type, P_##pull, offset}
> +#endif
> +
> +//
> +// GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.
> +// NC = NCORE, SC = SCORE, SS= SSUS
> +//
> +typedef struct {
> +
> +#ifdef EFI_DEBUG
> + char pad_name[32];// GPIO Pin Name for debug purpose
> +#endif
> +
> + GPIO_USAGE usage; // GPIO pin used as Native mode or
> GPI/GPO/GPIO mode
> + GPO_D4 gpod4; // GPO default value
> + GPIO_FUNC_NUM func; // Function Number (F0~F7)
> + INT_TYPE int_type; // Edge or Level trigger, low or high active
> + PULL_TYPE pull; // Pull Up or Down
> + UINT8 offset; // Equal with (PCONF0 register offset >> 4 bits)
> +} GPIO_CONF_PAD_INIT;
> +
> +//
> +//typedef UINT64 BOARD_FEATURES
> +//
> +typedef struct _EFI_PLATFORM_INFO_HOB {
> + UINT16 PlatformType; // Platform Type
> + UINT8 BoardId; // Board ID
> + UINT8 BoardRev; // Board Revision
> + PLATFORM_FLAVOR PlatformFlavor; // Platform Flavor
> + UINT8 DDRDaughterCardCh0Id;// DDR daughter card channel 0
> id
> + UINT8 DDRDaughterCardCh1Id;// DDR daughter card channel 1
> id
> + UINT8 ECOId; // ECO applied on platform
> + UINT16 IohSku;
> + UINT8 IohRevision;
> + UINT16 IchSku;
> + UINT8 IchRevision;
> + EFI_PLATFORM_PCI_DATA PciData;
> + EFI_PLATFORM_CPU_DATA CpuData;
> + EFI_PLATFORM_MEM_DATA MemData;
> + EFI_PLATFORM_SYS_DATA SysData;
> + EFI_PLATFORM_IGD_DATA IgdData;
> + UINT8 RevisonId; // Structure Revision ID
> + EFI_PHYSICAL_ADDRESS PlatformCfioData;
> + EFI_PHYSICAL_ADDRESS PlatformGpioData_NC;
> + EFI_PHYSICAL_ADDRESS PlatformGpioData_SC;
> + EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS;
> + EFI_PHYSICAL_ADDRESS PlatformGpioData_NC_TRI;
> + EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_TRI;
> + EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_TRI;
> + EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1;
> + EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_PR1_1;
> + EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1_1;
> +
> + UINT8 CfioEnabled;
> + UINT32 SsidSvid;
> + UINT16 AudioSubsystemDeviceId;
> + UINT64 AcpiOemId;
> + UINT64 AcpiOemTableId;
> + UINT16 MemCfgID;
> +} EFI_PLATFORM_INFO_HOB;
> +
> +#pragma pack()
> +
> +EFI_STATUS
> +GetPlatformInfoHob (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
> + );
> +
> +
> +EFI_STATUS
> +InstallPlatformClocksNotify (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +EFI_STATUS
> +InstallPlatformSysCtrlGPIONotify (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h
> new file mode 100644
> index 0000000000..19eee2b729
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h
> @@ -0,0 +1,279 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +Module Name:
> +
> + SensorInfoVariable.h
> +
> +Abstract:
> +
> + GUID used for Sensor Info variable.
> +
> +--*/
> +
> +
> +//
> +// Module: SensorInfoVariable.h
> +//
> +// Description: Provides structure and literal definitions for the
> +// Sensor Information Variable. The BIOS will provide
> +// this variable to runtime applications via the EFI
> +// GetVariable function.
> +//
> +// Notes: 1. When defining and initializing the variable within the
> +// BIOS, the module will define the structure using the
> +// typedef macros in a block. For an ATX board using a
> +// single Heceta 6P, which has 4 temperature sensors, 6
> +// voltage sensors, 4 fan speed sensors and 3 fan speed
> +// controllers, this block would be declared as follows:
> +//
> +// TYPEDEF_TEMP_SENSOR_SECTION(4);
> +// TYPEDEF_VOLT_SENSOR_SECTION(6);
> +// TYPEDEF_FAN_SENSOR_SECTION(4);
> +// TYPEDEF_FAN_CONTROLLER_SENSOR(3);
> +// TYPEDEF_SENSOR_INFO_VAR;
> +//
> +// 2. When crafting code to access the variable, the module
> +// will also need to invoke the typedef macros in a
> +// block but, since it cannot declare a structure for the
> +// overall variable (because array lengths will vary), it
> +// cannot use TYPEDEF_SENSOR_INFO_VAR. The block will
> +// typically be used as follows:
> +//
> +// TYPEDEF_TEMP_SENSOR_SECTION(1);
> +// TYPEDEF_VOLT_SENSOR_SECTION(1);
> +// TYPEDEF_FAN_SENSOR_SECTION(1);
> +// TYPEDEF_FAN_CONTROLLER_SENSOR(1);
> +//
> +// The structure buffer should instead be declared as a
> +// BYTE array. Pointers to the various sections can then
> +// be built using the XXXX_SECTION_LEN macros...
> +//
> +
> +
> +#ifndef _SENSOR_INFO_VAR_GUID_H_
> +#define _SENSOR_INFO_VAR_GUID_H_
> +
> +#define SENSOR_INFO_VAR_GUID \
> + { \
> + 0xE59E7B4D, 0x06DC, 0x44AB, 0xB3, 0x6D, 0x5E, 0xD7, 0x78, 0x9C, 0x53,
> 0x0A \
> + }
> +
> +extern EFI_GUID gEfiSensorInfoVarGuid;
> +extern CHAR16 gEfiSensorInfoVarName[];
> +extern CHAR16 gEfiSensorInfoVarNameWithPassword[];
> +
> +#define SENSOR_INFO_VAR_NAME L"SensorInfoVar"
> +#define SENSOR_INFO_VAR_NAME_WITH_PASSWORD
> SENSOR_INFO_VAR_NAME L"S4k?A^7!"
> +
> +//
> +// Sensor/Controller usage definitions
> +//
> +
> +#define UNKNOWN_OTHER 0
> +
> +//
> +// Temperature Sensors
> +//
> +#define CPU_CORE_TEMPERATURE 1
> +#define CPU_DIE_TEMPERATURE 2
> +#define ICH_TEMPERATURE 3
> +#define MCH_TEMPERATURE 4
> +#define VR_TEMPERATURE 5
> +#define MEMORY_TEMPERATURE 6
> +#define MOTHERBOARD_AMBIENT_TEMPERATURE 7
> +#define SYSTEM_AMBIENT_AIR_TEMPERATURE 8
> +#define CPU_INLET_AIR_TEMPERATURE 9
> +#define SYSTEM_INLET_AIR_TEMPERATURE 10
> +#define SYSTEM_OUTLET_AIR_TEMPERATURE 11
> +#define PSU_HOTSPOT_TEMPERATURE 12
> +#define PSU_INLET_AIR_TEMPERATURE 13
> +#define PSU_OUTLET_AIR_TEMPERATURE 14
> +#define DRIVE_TEMPERATURE 15
> +#define GPU_TEMPERATURE 16
> +#define IOH_TEMPERATURE 17
> +
> +#define LAST_TEMPERATURE 17
> +
> +//
> +// Voltage Sensors
> +//
> +#define PLUS_12_VOLTS 1
> +#define NEG_12_VOLTS 2
> +#define PLUS_5_VOLTS 3
> +#define PLUS_5_VOLT_BACKUP 4
> +#define NEG_5_VOLTS 5
> +#define PLUS_3P3_VOLTS 6
> +#define PLUS_2P5_VOLTS 7
> +#define PLUS_1P5_VOLTS 8
> +#define CPU_1_VCCP_VOLTAGE 9
> +#define CPU_2_VCCP_VOLTAGE 10
> +#define CPU_3_VCCP_VOLTAGE 11
> +#define CPU_4_VCCP_VOLTAGE 12
> +#define PSU_INPUT_VOLTAGE 13
> +#define MCH_VCC_VOLTAGE 14
> +#define PLUS_3P3_VOLT_STANDBY 15
> +#define CPU_VTT_VOLTAGE 16
> +#define PLUS_1P8_VOLTS 17
> +
> +#define LAST_VOLTAGE 17
> +
> +//
> +// Fan Speed Sensors and Controllers.
> +//
> +#define CPU_COOLING_FAN 1
> +#define SYSTEM_COOLING_FAN 2
> +#define MCH_COOLING_FAN 3
> +#define VR_COOLING_FAN 4
> +#define CHASSIS_COOLING_FAN 5
> +#define CHASSIS_INLET_FAN 6
> +#define CHASSIS_OUTLET_FAN 7
> +#define PSU_COOLING_FAN 8
> +#define PSU_INLET_FAN 9
> +#define PSU_OUTLET_FAN 10
> +#define DRIVE_COOLING_FAN 11
> +#define GPU_COOLING_FAN 12
> +#define AUX_COOLING_FAN 13
> +#define IOH_COOLING_FAN 14
> +
> +#define LAST_FAN 14
> +
> +//
> +// Fan Type Definitions
> +//
> +#define FAN_TYPE_UNKNOWN 0
> +#define FAN_3WIRE_PULSE 1
> +#define FAN_3WIRE_VOLTAGE 2
> +#define FAN_4WIRE 3
> +
> +#pragma pack(1)
> +
> +//
> +// TEMP_SENSOR_INFO - Structure providing info for a temperature sensor.
> +//
> +typedef struct _TEMP_SENSOR_INFO
> +{
> + UINT8 byDevice; // Device index
> + UINT8 byIndex; // Physical sensor index
> + UINT8 byUsage; // Usage indicator
> + UINT8 bRelative; // Relative vs. Absolute readings
> +
> +} TEMP_SENSOR_INFO, *P_TEMP_SENSOR_INFO;
> +
> +//
> +// TYPEDEF_TEMP_SENSOR_SECTION - Macro that can be used to typedef
> the
> +// TEMP_SENSOR_SECTION structure, which provides information about all
> +// temperature sensors.
> +//
> +#define TYPEDEF_TEMP_SENSOR_SECTION(count) \
> +typedef struct _TEMP_SENSOR_SECTION \
> +{ \
> + UINT8 byCount; \
> + TEMP_SENSOR_INFO stSensor[count]; \
> + \
> +} TEMP_SENSOR_SECTION, *P_TEMP_SENSOR_SECTION
> +
> +//
> +// VOLT_SENSOR_INFO - Structure providing info for a voltage sensor.
> +//
> +typedef struct _VOLT_SENSOR_INFO
> +{
> + UINT8 byDevice; // Device index
> + UINT8 byIndex; // Physical sensor index
> + UINT8 byUsage; // Usage indicator
> +
> +} VOLT_SENSOR_INFO, *P_VOLT_SENSOR_INFO;
> +
> +//
> +// TYPEDEF_VOLT_SENSOR_SECTION - Macro that can be used to typedef
> the
> +// VOLT_SENSOR_SECTION structure, which provides information about all
> +// voltage sensors.
> +//
> +#define TYPEDEF_VOLT_SENSOR_SECTION(count) \
> +typedef struct _VOLT_SENSOR_SECTION \
> +{ \
> + UINT8 byCount; \
> + VOLT_SENSOR_INFO stSensor[count]; \
> + \
> +} VOLT_SENSOR_SECTION, *P_VOLT_SENSOR_SECTION
> +
> +//
> +// FAN_SENSOR_INFO - Structure providing info for a fan speed sensor.
> +//
> +typedef struct _FAN_SENSOR_INFO
> +{
> + UINT8 byDevice; // Device index
> + UINT8 byIndex; // Physical sensor index
> + UINT8 byUsage; // Usage indicator
> + UINT8 byType; // Fan type
> + UINT8 byController; // Associated Fan Controller
> +
> +} FAN_SENSOR_INFO, *P_FAN_SENSOR_INFO;
> +
> +//
> +// TYPEDEF_FAN_SENSOR_SECTION - Macro that can be used to typedef
> the
> +// FAN_SENSOR_SECTION structure, which provides information about all
> fan
> +// speed sensors.
> +//
> +#define TYPEDEF_FAN_SENSOR_SECTION(count) \
> +typedef struct _FAN_SENSOR_SECTION \
> +{ \
> + UINT8 byCount; \
> + FAN_SENSOR_INFO stSensor[count]; \
> + \
> +} FAN_SENSOR_SECTION, *P_FAN_SENSOR_SECTION
> +
> +//
> +// FAN_CONTROLLER_INFO - Structure providing info for a fan speed
> controller.
> +//
> +#define MAX_ASSOC_FANS 4
> +#define ASSOC_UNUSED 0xFF
> +
> +typedef struct _FAN_CONTROLLER_INFO
> +{
> + UINT8 byDevice; // Device index
> + UINT8 byIndex; // Physical Controller Index
> + UINT8 byUsage; // Usage Indicator
> + UINT8 byFan[MAX_ASSOC_FANS]; // Associated Fan
> Sensors
> +
> +} FAN_CONTROLLER_INFO, *P_FAN_CONTROLLER_INFO;
> +
> +//
> +// TYPEDEF_FAN_CONTROLLER_SECTION - Macro that can be used to
> typedef the
> +// FAN_CONTROLLER_SECTION structure, which provides information about
> all
> +// fan speed controllers.
> +//
> +#define TYPEDEF_FAN_CONTROLLER_SECTION(count) \
> +typedef struct _FAN_CONTROLLER_SECTION \
> +{ \
> + UINT8 byCount; \
> + FAN_CONTROLLER_INFO stController[count]; \
> + \
> +} FAN_CONTROLLER_SECTION, *P_FAN_CONTROLLER_SECTION
> +
> +//
> +// TYPEDEF_SENSOR_INFO_VAR - Macro that can be used to typedef the
> +// SENSOR_INFO_VAR structure, which provides information about all
> sensors
> +// and fan speed controllers. The other TYPEDEF macros must be invoked
> +// before using this one...
> +//
> +#define TYPEDEF_SENSOR_INFO_VAR \
> +typedef struct _SENSOR_INFO_VAR \
> +{ \
> + TEMP_SENSOR_SECTION stTemps; \
> + VOLT_SENSOR_SECTION stVolts; \
> + FAN_SENSOR_SECTION stFans; \
> + FAN_CONTROLLER_SECTION stCtrls; \
> + \
> +} SENSOR_INFO_VAR, *P_SENSOR_INFO_VAR
> +
> +#pragma pack()
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
> new file mode 100644
> index 0000000000..32f121892b
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
> @@ -0,0 +1,1344 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
> +
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +
> +Module Name:
> +
> + SetupVariable.h
> +
> +Abstract:
> +
> + Driver configuration include file
> +
> +
> +**/
> +
> +#ifndef _SETUP_VARIABLE_H
> +#define _SETUP_VARIABLE_H
> +
> +//
> +// ---------------------------------------------------------------------------
> +//
> +// Driver Configuration
> +//
> +// ---------------------------------------------------------------------------
> +//
> +
> +//
> +// {EC87D643-EBA4-4bb5-A1E5-3F3E36B20DA9}
> +//
> +#define SYSTEM_CONFIGURATION_GUID\
> + { \
> + 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9
> \
> + }
> +
> +#define ROOT_SECURITY_GUID\
> + { \
> + 0xd387d688, 0xeba4, 0x45b5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0x37
> \
> + }
> +
> +//
> +// {6936B3BD-4350-46d9-8940-1FA20961AEB1}
> +//
> +#define SYSTEM_ROOT_MAIN_GUID\
> + { \
> + 0x6936b3bd, 0x4350, 0x46d9, 0x89, 0x40, 0x1f, 0xa2, 0x9, 0x61, 0xae, 0xb1
> \
> + }
> +
> +//
> +// {21FEE8DB-0D29-477e-B5A9-96EB343BA99C}
> +//
> +#define ADDITIONAL_SYSTEM_INFO_GUID\
> + { \
> + 0x21fee8db, 0xd29, 0x477e, 0xb5, 0xa9, 0x96, 0xeb, 0x34, 0x3b, 0xa9,
> 0x9c \
> + }
> +
> +#define SETUP_GUID { 0xEC87D643, 0xEBA4, 0x4BB5, 0xA1, 0xE5, 0x3F, 0x3E,
> 0x36, 0xB2, 0x0D, 0xA9 }
> +
> +// {1B838190-4625-4ead-ABC9-CD5E6AF18FE0}
> +#define EFI_HII_EXPORT_DATABASE_GUID { 0x1b838190, 0x4625, 0x4ead,
> 0xab, 0xc9, 0xcd, 0x5e, 0x6a, 0xf1, 0x8f, 0xe0 }
> +
> +#define PASSWORD_MAX_SIZE 20
> +
> +#define MAX_CUSTOM_VID_TABLE_STATES 6
> +//
> +// Overclocking Source Defines
> +//
> +#define OVERCLOCK_SOURCE_BIOS 0
> +#define OVERCLOCK_SOURCE_OS 1
> +
> +#define PCH_PCIE_MAX_ROOT_PORTS 4
> +
> +#pragma pack(1)
> +
> +// NOTE: When you add anything to this structure,
> +// you MUST add it to the very bottom!!!!
> +// You must make sure the structure size is able to divide by 32!
> +typedef struct {
> +
> + //
> + // Floppy
> + //
> + UINT8 Floppy;
> + UINT8 FloppyLockHide;
> +
> + UINT8 FloppyWriteProtect;
> + UINT8 FloppyWriteProtectLockHide;
> +
> + //
> + // System ports
> + //
> + UINT8 Serial;
> + UINT8 SerialLockHide;
> +
> + UINT8 Serial2;
> + UINT8 Serial2LockHide;
> +
> + UINT8 Parallel;
> + UINT8 ParallelLockHide;
> +
> + UINT8 ParallelMode;
> + UINT8 ParallelModeLockHide;
> +
> + UINT8 AllUsb;
> + UINT8 UsbPortsLockHide;
> +
> + UINT8 Usb2;
> + UINT8 Usb2LockHide;
> +
> + UINT8 UsbLegacy;
> + UINT8 UsbLegacyLockHide;
> +
> + UINT8 Audio;
> + UINT8 AudioLockHide;
> +
> + UINT8 Lan;
> + UINT8 LanLockHide;
> +
> + //
> + // Keyboard
> + //
> + UINT8 Numlock;
> + UINT8 NumlockLockHide;
> +
> + //
> + // ECIR
> + //
> + UINT8 ECIR;
> + UINT8 ECIRLockHide;
> +
> + //
> + // Power State
> + //
> + UINT8 PowerState;
> + UINT8 PowerStateLockHide;
> +
> + //
> + // Wake on RTC variables
> + //
> + UINT8 WakeOnRtcS5;
> + UINT8 WakeOnRtcS5LockHide;
> + UINT8 RTCWakeupDate;
> + UINT8 RTCWakeupDateLockHide;
> + UINT8 RTCWakeupTimeHour;
> + UINT8 RTCWakeupHourLockHide;
> + UINT8 RTCWakeupTimeMinute;
> + UINT8 RTCWakeupMinuteLockHide;
> + UINT8 RTCWakeupTimeSecond;
> + UINT8 RTCWakeupSecondLockHide;
> +
> + //
> + // Wake On Lan
> + //
> + UINT8 WakeOnLanS5;
> + UINT8 WakeOnLanS5LockHide;
> +
> + //Spread spectrum
> + UINT8 SpreadSpectrum;
> +
> + //
> + // Boot Order
> + //
> + UINT8 BootOrder[8];
> + UINT8 BootOrderLockHide;
> +
> + //
> + // Hard Drive Boot Order
> + //
> + UINT8 HardDriveBootOrder[8];
> + UINT8 HardDriveBootOrderLockHide;
> +
> + //
> + // CD Drive Boot Order
> + //
> + UINT8 CdDriveBootOrder[4];
> + UINT8 CdDriveBootOrderLockHide;
> +
> + //
> + // FDD Drive Boot Order
> + //
> + UINT8 FddDriveBootOrder[4];
> + UINT8 FddDriveBootOrderLockHide;
> +
> + //
> + // Drive Boot Order
> + //
> + UINT8 DriveBootOrder[16];
> + UINT8 DriveBootOrderLockHide;
> +
> + //
> + // Boot Menu Type
> + //
> + UINT8 BootMenuType;
> + UINT8 BootMenuTypeLockHide;
> +
> + //
> + // Boot from Removable Devices
> + //
> + UINT8 BootFloppy;
> + UINT8 BootFloppyLockHide;
> +
> + //
> + // Boot from Optical Devices
> + //
> + UINT8 BootCd;
> + UINT8 BootCdLockHide;
> +
> + //
> + // Boot from Network
> + //
> + UINT8 BootNetwork;
> + UINT8 BootNetworkLockHide;
> +
> + //
> + // Boot USB
> + //
> + UINT8 BootUsb;
> + UINT8 BootUsbLockHide;
> +
> + //
> + // USB Zip Emulation Type
> + //
> + UINT8 UsbZipEmulation;
> + UINT8 UsbZipEmulationLockHide;
> +
> + //
> + // USB Devices Boot First in Boot Order
> + //
> + UINT8 UsbDevicesBootFirst;
> + UINT8 UsbDevicesBootFirstLockHide;
> +
> + //
> + // USB Boot Device SETUP Emulation
> + //
> + UINT8 UsbSetupDeviceEmulation;
> + UINT8 UsbSetupDeviceEmulationLockHide;
> +
> + //
> + // BIOS INT13 Emulation for USB Mass Devices
> + //
> + UINT8 UsbBIOSINT13DeviceEmulation;
> + UINT8 UsbBIOSINT13DeviceEmulationLockHide;
> +
> + //
> + // BIOS INT13 Emulation Size for USB Mass Devices
> + //
> + UINT16 UsbBIOSINT13DeviceEmulationSize;
> + UINT8 UsbBIOSINT13DeviceEmulationSizeLockHide;
> +
> + //
> + // Dummy place holder to prevent VFR compiler problem.
> + //
> + UINT16 DummyDataForVfrBug; // Don't change or use.
> +
> + //
> + // Language Select
> + //
> + UINT8 LanguageSelect;
> +
> + //
> + // SATA Type (Ide, Ahci, Raid)
> + //
> + UINT8 SataType;
> + UINT8 SataTypeLockHide;
> + UINT8 SataTestMode;
> +
> + //
> + // Fixed Disk Boot Sector (Fdbs)
> + //
> + UINT8 Fdbs;
> + UINT8 FdbsLockHide;
> +
> + //
> + // DisplaySetupPrompt
> + //
> + UINT8 DisplaySetupPrompt;
> + UINT8 DisplaySetupPromptLockHide;
> +
> + //
> + // ASF
> + //
> + UINT8 Asf;
> + UINT8 AsfLockHide;
> +
> + //
> + // Event Logging
> + //
> + UINT8 EventLogging;
> + UINT8 EventLoggingLockHide;
> +
> + //
> + // Clear Event Log
> + //
> + UINT8 ClearEvents;
> + UINT8 ClearEventsLockHide;
> +
> + //
> + // Expansion Card Text
> + //
> + UINT8 ExpansionCardText;
> + UINT8 ExpansionCardTextLockHide;
> +
> + //
> + // Video Adaptor
> + //
> + UINT8 PrimaryVideoAdaptor;
> + UINT8 PrimaryVideoAdaptorLockHide;
> +
> + //
> + // Chassis intrusion
> + //
> + UINT8 IntruderDetection;
> + UINT8 IntruderDetectionLockHide;
> +
> + //
> + // User Access Level
> + //
> + UINT8 UserPasswordLevel;
> + UINT8 UserPasswordLevelLockHide;
> +
> + //
> + // Maximum FSB Automatic/Disable
> + //
> + UINT8 MaxFsb;
> + UINT8 MaxFsbLockHide;
> +
> + //
> + // Hard Disk Pre-delay
> + //
> + UINT8 HddPredelay;
> + UINT8 HddPredelayLockHide;
> +
> + //
> + // S.M.A.R.T. Mode
> + //
> + UINT8 SmartMode;
> + UINT8 SmartModeLockHide;
> +
> + //
> + // ACPI Suspend State
> + //
> + UINT8 AcpiSuspendState;
> + UINT8 AcpiSuspendStateLockHide;
> +
> + //
> + // PCI Latency Timer
> + //
> + UINT8 PciLatency;
> + UINT8 PciLatencyLockHide;
> +
> + //
> + // Fan Control
> + //
> + UINT8 FanControl;
> + UINT8 FanControlLockHide;
> +
> + //
> + // CPU Fan Control
> + //
> + UINT8 CpuFanControl;
> + UINT8 CpuFanControlLockHide;
> +
> + //
> + // Lowest Fan Speed
> + //
> + UINT8 LowestFanSpeed;
> + UINT8 LowestFanSpeedLockHide;
> +
> + //
> + // Processor (CPU)
> + //
> + UINT8 CpuFlavor;
> +
> + UINT8 CpuidMaxValue;
> + UINT8 CpuidMaxValueLockHide;
> +
> + UINT8 ExecuteDisableBit;
> + UINT8 ExecuteDisableBitLockHide;
> +
> + //
> + // EIST or GV3 setup option
> + //
> + UINT8 ProcessorEistEnable;
> + UINT8 ProcessorEistEnableLockHide;
> +
> + //
> + // C1E Enable
> + //
> + UINT8 ProcessorC1eEnable;
> + UINT8 ProcessorC1eEnableLockHide;
> +
> + //
> + // Enabling CPU C-States of processor
> + //
> + UINT8 ProcessorCcxEnable;
> + UINT8 ProcessorCcxEnableLockHide;
> +
> + //
> + // Package C-State Limit
> + //
> + UINT8 PackageCState;
> + UINT8 PackageCStateLockHide;
> +
> + //
> + // Enable/Disable NHM C3(ACPI C2) report to OS
> + //
> + UINT8 OSC2Report;
> + UINT8 OSC2ReportLockHide;
> +
> + //
> + // Enable/Disable NHM C6(ACPI C3) report to OS
> + //
> + UINT8 C6Enable;
> + UINT8 C6EnableLockHide;
> +
> + //
> + // Enable/Disable NHM C7(ACPI C3) report to OS
> + //
> + UINT8 C7Enable;
> + UINT8 C7EnableLockHide;
> +
> + //
> + // EIST/PSD Function select option
> + //
> + UINT8 ProcessorEistPsdFunc;
> + UINT8 ProcessorEistPsdFuncLockHide;
> +
> + //
> + //
> + //
> + UINT8 CPU00;
> + UINT8 CPU01;
> +
> + //
> + //
> + //
> + UINT8 CPU02;
> + UINT8 CPU03;
> +
> + //
> + //
> + //
> + UINT8 CPU04;
> + UINT8 CPU05;
> +
> + //
> + //
> + //
> + UINT8 CPU06;
> + UINT8 CPU07;
> +
> + //
> + //
> + //
> + UINT8 CPU08;
> + UINT8 CPU09;
> +
> + //
> + //
> + //
> + UINT8 CPU10;
> + UINT8 CPU11;
> +
> + //
> + //
> + //
> + UINT8 CPU12;
> + UINT8 CPU13;
> +
> + //
> + //
> + //
> + UINT8 CPU14;
> + UINT8 CPU15;
> +
> + //
> + //
> + //
> + UINT8 CPU16;
> + UINT8 CPU17;
> +
> + //
> + //
> + //
> + UINT8 CPU18;
> + UINT8 CPU19;
> +
> + //
> + //
> + //
> + UINT8 CPU20;
> + UINT8 CPU21;
> +
> + //
> + //
> + //
> + UINT8 CPU22;
> + UINT8 CPU23;
> +
> + //
> + //
> + //
> + UINT8 CPU24;
> + UINT8 CPU25;
> +
> + //
> + //
> + //
> + UINT8 CPU26;
> + UINT8 CPU27;
> +
> + //
> + //
> + //
> + UINT8 CPU28;
> + UINT8 CPU29;
> +
> + //
> + //
> + //
> + UINT8 CPU30;
> + UINT8 CPU31;
> +
> + //
> + //
> + //
> + UINT8 CPU32;
> + UINT8 CPU33;
> +
> + //
> + //
> + //
> + UINT8 CPU34;
> + UINT8 CPU35;
> +
> + //
> + //
> + //
> + UINT8 CPU36;
> + UINT8 CPU37;
> +
> + //
> + //
> + //
> + UINT8 CPU38;
> + UINT8 CPU39;
> +
> + //
> + //
> + //
> + UINT16 CPU40;
> + UINT8 CPU41;
> +
> + //
> + //
> + //
> + UINT8 CPU42;
> + UINT8 CPU43;
> +
> + //
> + //
> + //
> + UINT16 CPU44;
> + UINT8 CPU45;
> +
> + //
> + //
> + //
> + UINT8 CPU46;
> + UINT8 CPU47;
> +
> + //
> + //
> + //
> + UINT8 CPU48;
> + UINT8 CPU49;
> +
> + //
> + //
> + //
> + UINT8 CPU50;
> + UINT8 CPU51;
> +
> + //
> + //
> + //
> + UINT8 CPU52;
> + UINT8 CPU53;
> +
> + //
> + //
> + //
> + UINT8 CPU54;
> + UINT8 CPU55;
> +
> + //
> + //
> + //
> + UINT8 CPU56;
> + UINT8 CPU57;
> +
> + //
> + //
> + //
> + UINT8 CPU58;
> + UINT8 CPU59;
> +
> + //
> + //
> + //
> + UINT8 CPU60;
> + UINT8 CPU61;
> +
> + //
> + //
> + //
> + UINT8 CPU62;
> + UINT8 CPU63;
> +
> + //
> + //
> + //
> + UINT8 CPU64;
> + UINT8 CPU65;
> +
> + //
> + //
> + //
> + UINT8 CPU66;
> + UINT8 CPU67;
> +
> + //
> + //
> + //
> + UINT16 CPU68;
> + UINT8 CPU69;
> +
> + //
> + //
> + //
> + UINT16 CPU70;
> +
> + //
> + //
> + //
> + UINT8 CPU71;
> +
> + //
> + //
> + //
> + UINT8 MEM00;
> + UINT8 MEM01;
> +
> + //
> + //
> + //
> + UINT8 MEM02;
> + UINT8 MEM03;
> +
> + UINT16 MEM04;
> + UINT8 MEM05;
> +
> + UINT8 MEM06;
> + UINT8 MEM07;
> +
> + UINT8 MEM08;
> + UINT8 MEM09;
> +
> + UINT8 MEM10;
> + UINT8 MEM11;
> +
> + UINT8 MEM12;
> + UINT8 MEM13;
> +
> + UINT8 MEM14;
> + UINT8 MEM15;
> +
> + UINT8 MEM16;
> + UINT8 MEM17;
> +
> + UINT16 MEM18;
> + UINT8 MEM19;
> +
> + UINT8 MEM20;
> + UINT8 MEM21;
> +
> + UINT8 MEM22;
> + UINT8 MEM23;
> +
> + UINT8 MEM24;
> + UINT8 MEM25;
> +
> + UINT8 MEM26;
> + UINT8 MEM27;
> +
> + UINT8 MEM28;
> + UINT8 MEM29;
> +
> + UINT8 MEM30;
> + UINT8 MEM31;
> +
> + UINT8 MEM32;
> + UINT8 MEM33;
> +
> + UINT8 MEM34;
> + UINT8 MEM35;
> +
> + //
> + //
> + //
> + UINT8 MEM36;
> + UINT8 MEM37;
> + UINT8 MEM38;
> + UINT8 MEM39;
> +
> + //
> + //
> + //
> + UINT8 MEM40;
> + UINT8 MEM41;
> + UINT8 MEM42;
> + UINT8 MEM43;
> + UINT8 MEM44;
> + UINT8 MEM45;
> + UINT8 MEM46;
> + UINT8 MEM47;
> +
> +
> + //
> + // Port 80 decode 0/1 - PCI/LPC
> + UINT8 Port80Route;
> + UINT8 Port80RouteLockHide;
> +
> + //
> + // ECC Event Logging
> + //
> + UINT8 EccEventLogging;
> + UINT8 EccEventLoggingLockHide;
> +
> + //
> + // TPM Enable/Disable
> + //
> + UINT8 ETpm;
> +
> + //
> + // TPM question 0 = Disabled, 1 = Enabled
> + //
> + UINT8 ETpmClear;
> +
> + //
> + // Secondary SATA Controller question 0 = Disabled, 1 = Enabled
> + //
> + UINT8 ExtSata;
> + UINT8 ExtSataLockHide;
> +
> + //
> + // Mode selection for Secondary SATA Controller (0=IDE, 1=RAID)
> + //
> + UINT8 ExtSataMode;
> + UINT8 ExtSataModeLockHide;
> +
> + //
> + // LT Technology 0/1 -> Disable/Enable
> + //
> + UINT8 LtTechnology;
> + UINT8 LtTechnologyLockHide;
> +
> + //
> + // HPET Support 0/1 -> Disable/Enable
> + //
> + UINT8 Hpet;
> + UINT8 HpetLockHide;
> +
> + //
> + // ICH Function Level Reset enable/disable
> + //
> + UINT8 FlrCapability;
> + UINT8 FlrCapabilityLockHide;
> +
> + // VT-d Option
> + UINT8 VTdSupport;
> + UINT8 VTdSupportLockHide;
> +
> + UINT8 InterruptRemap;
> + UINT8 InterruptRemapLockHide;
> +
> + UINT8 Isoc;
> + UINT8 IsocLockHide;
> +
> + UINT8 CoherencySupport;
> + UINT8 CoherencySupportLockHide;
> +
> + UINT8 ATS;
> + UINT8 ATSLockHide;
> +
> + UINT8 PassThroughDma;
> + UINT8 PassThroughDmaLockHide;
> +
> + //
> + // IGD option
> + //
> + UINT8 GraphicsDriverMemorySize;
> + UINT8 GraphicsDriverMemorySizeLockHide;
> +
> +
> + //
> + // Discrete SATA Type (Ide, Raid, Ahci)
> + //
> + UINT8 ExtSataMode2;
> + UINT8 ExtSataMode2LockHide;
> +
> + UINT8 ProcessorReserve00;
> + UINT8 ProcessorReserve01;
> +
> + //
> + // IGD Aperture Size question
> + //
> + UINT8 IgdApertureSize;
> + UINT8 IgdApertureSizeLockHide;
> +
> + //
> + // Boot Display Device
> + //
> + UINT8 BootDisplayDevice;
> + UINT8 BootDisplayDeviceLockHide;
> +
> +
> + //
> + // System fan speed duty cycle
> + //
> + UINT8 SystemFanDuty;
> + UINT8 SystemFanDutyLockHide;
> +
> +
> + //
> + // S3 state LED indicator
> + //
> + UINT8 S3StateIndicator;
> + UINT8 S3StateIndicatorLockHide;
> +
> + //
> + // S1 state LED indicator
> + //
> + UINT8 S1StateIndicator;
> + UINT8 S1StateIndicatorLockHide;
> +
> + //
> + // PS/2 Wake from S5
> + //
> + UINT8 WakeOnS5Keyboard;
> + UINT8 WakeOnS5KeyboardLockHide;
> +
> +
> + //
> + // SATA Controller question 0 = Disabled, 1 = Enabled
> + //
> + UINT8 Sata;
> + UINT8 SataLockHide;
> +
> + //
> + // PS2 port
> + //
> + UINT8 PS2;
> +
> + //
> + // No VideoBeep
> + //
> + UINT8 NoVideoBeepEnable;
> +
> + //
> + // Integrated Graphics Device
> + //
> + UINT8 Igd;
> +
> + //
> + // Video Device select order
> + //
> + UINT8 VideoSelectOrder[8];
> +
> + // Flash update sleep delay
> + UINT8 FlashSleepDelay;
> + UINT8 FlashSleepDelayLockHide;
> +
> + //
> + // Boot Display Device2
> + //
> + UINT8 BootDisplayDevice2;
> + UINT8 BootDisplayDevice2LockHide;
> +
> + //
> + // Flat Panel
> + //
> + UINT8 EdpInterfaceType;
> + UINT8 EdpInterfaceTypeLockHide;
> +
> + UINT8 LvdsInterfaceType;
> + UINT8 LvdsInterfaceTypeLockHide;
> +
> + UINT8 ColorDepth;
> + UINT8 ColorDepthLockHide;
> +
> + UINT8 EdidConfiguration;
> + UINT8 EdidConfigurationLockHide;
> +
> + UINT8 PwmReserved;
> + UINT8 MaxInverterPWMLockHide;
> +
> + UINT8 PreDefinedEdidConfiguration;
> + UINT8 PreDefinedEdidConfigurationLockHide;
> +
> + UINT16 ScreenBrightnessResponseTime;
> + UINT8 ScreenBrightnessResponseTimeLockHide;
> +
> + UINT8 Serial3;
> + UINT8 Serial3LockHide;
> +
> + UINT8 Serial4;
> + UINT8 Serial4LockHide;
> +
> + UINT8 CurrentSetupProfile;
> + UINT8 CurrentSetupProfileLockHide;
> +
> + //
> + // FSC system Variable
> + //
> + UINT8 CPUFanUsage;
> + UINT8 CPUFanUsageLockHide;
> + UINT16 CPUUnderSpeedthreshold;
> + UINT8 CPUUnderSpeedthresholdLockHide;
> + UINT8 CPUFanControlMode;
> + UINT8 CPUFanControlModeLockHide;
> + UINT16 Voltage12UnderVolts;
> + UINT8 Voltage12UnderVoltsLockHide;
> + UINT16 Voltage12OverVolts;
> + UINT8 Voltage12OverVoltsLockHide;
> + UINT16 Voltage5UnderVolts;
> + UINT8 Voltage5UnderVoltsLockHide;
> + UINT16 Voltage5OverVolts;
> + UINT8 Voltage5OverVoltsLockHide;
> + UINT16 Voltage3p3UnderVolts;
> + UINT8 Voltage3p3UnderVoltsLockHide;
> + UINT16 Voltage3p3OverVolts;
> + UINT8 Voltage3p3OverVoltsLockHide;
> + UINT16 Voltage2p5UnderVolts;
> + UINT8 Voltage2p5UnderVoltsLockHide;
> + UINT16 Voltage2p5OverVolts;
> + UINT8 Voltage2p5OverVoltsLockHide;
> + UINT16 VoltageVccpUnderVolts;
> + UINT8 VoltageVccpUnderVoltsLockHide;
> + UINT16 VoltageVccpOverVolts;
> + UINT8 VoltageVccpOverVoltsLockHide;
> + UINT16 Voltage5BackupUnderVolts;
> + UINT8 Voltage5BackupUnderVoltsLockHide;
> + UINT16 Voltage5BackupOverVolts;
> + UINT8 Voltage5BackupOverVoltsLockHide;
> + UINT16 VS3p3StbyUnderVolt;
> + UINT8 VS3p3StbyUnderVoltLockHide;
> + UINT16 VS3p3StbyOverVolt;
> + UINT8 VS3p3StbyOverVoltLockHide;
> + UINT8 CPUFanMinDutyCycle;
> + UINT8 CPUFanMinDutyCycleLockHide;
> + UINT8 CPUFanMaxDutyCycle;
> + UINT8 CPUFanMaxDutyCycleLockHide;
> + UINT8 CPUFanOnDutyCycle;
> + UINT8 CPUFanOnDutyCycleLockHide;
> + UINT16 CpuOverTemp;
> + UINT8 CpuOverTempLockHide;
> + UINT16 CpuControlTemp;
> + UINT8 CpuControlTempLockHide;
> + UINT16 CpuAllOnTemp;
> + UINT8 CpuAllOnTempLockHide;
> + UINT8 CpuResponsiveness;
> + UINT8 CpuResponsivenessLockHide;
> + UINT8 CpuDamping;
> + UINT8 CpuDampingLockHide;
> + UINT16 PchOverTemp;
> + UINT8 PchOverTempLockHide;
> + UINT16 PchControlTemp;
> + UINT8 PchControlTempLockHide;
> + UINT16 PchAllOnTemp;
> + UINT8 PchAllOnTempLockHide;
> + UINT8 PchResponsiveness;
> + UINT8 PchResponsivenessLockHide;
> + UINT8 PchDamping;
> + UINT8 PchDampingLockHide;
> + UINT16 MemoryOverTemp;
> + UINT8 MemoryOverTempLockHide;
> + UINT16 MemoryControlTemp;
> + UINT8 MemoryControlTempLockHide;
> + UINT16 MemoryAllOnTemp;
> + UINT8 MemoryAllOnTempLockHide;
> + UINT8 MemoryResponsiveness;
> + UINT8 MemoryResponsivenessLockHide;
> + UINT8 MemoryDamping;
> + UINT8 MemoryDampingLockHide;
> + UINT16 VROverTemp;
> + UINT8 VROverTempLockHide;
> + UINT16 VRControlTemp;
> + UINT8 VRControlTempLockHide;
> + UINT16 VRAllOnTemp;
> + UINT8 VRAllOnTempLockHide;
> + UINT8 VRResponsiveness;
> + UINT8 VRResponsivenessLockHide;
> + UINT8 VRDamping;
> + UINT8 VRDampingLockHide;
> +
> + UINT8 LvdsBrightnessSteps;
> + UINT8 LvdsBrightnessStepsLockHide;
> + UINT8 EdpDataRate;
> + UINT8 EdpDataRateLockHide;
> + UINT16 LvdsPowerOnToBacklightEnableDelayTime;
> + UINT8 LvdsPowerOnToBacklightEnableDelayTimeLockHide;
> + UINT16 LvdsPowerOnDelayTime;
> + UINT8 LvdsPowerOnDelayTimeLockHide;
> + UINT16 LvdsBacklightOffToPowerDownDelayTime;
> + UINT8 LvdsBacklightOffToPowerDownDelayTimeLockHide;
> + UINT16 LvdsPowerDownDelayTime;
> + UINT8 LvdsPowerDownDelayTimeLockHide;
> + UINT16 LvdsPowerCycleDelayTime;
> + UINT8 LvdsPowerCycleDelayTimeLockHide;
> +
> + UINT8 IgdFlatPanel;
> + UINT8 IgdFlatPanelLockHide;
> + UINT8 Lan2;
> + UINT8 Lan2LockHide;
> +
> + UINT8 SwapMode;
> + UINT8 SwapModeLockHide;
> +
> + UINT8 Sata0HotPlugCap;
> + UINT8 Sata0HotPlugCapLockHide;
> + UINT8 Sata1HotPlugCap;
> + UINT8 Sata1HotPlugCapLockHide;
> +
> + UINT8 UsbCharging;
> + UINT8 UsbChargingLockHide;
> +
> + UINT8 Cstates;
> + UINT8 EnableC4;
> + UINT8 EnableC6;
> +
> + UINT8 FastBoot;
> + UINT8 EfiNetworkSupport;
> + UINT8 PxeRom;
> +
> + //Add for PpmPlatformPlicy
> + UINT8 PPM00;
> + UINT8 PPM01;
> + UINT8 PPM02;
> + UINT8 PPM03;
> + UINT8 PPM04;
> + UINT8 PPM05;
> + UINT8 PPM06;
> + UINT8 PPM07;
> + UINT8 PPM08;
> + UINT8 PPM09;
> + UINT8 PPM10;
> + UINT8 QuietBoot;
> + UINT8 LegacyUSBBooting;
> +
> + UINT8 PwmReserved02;
> + //
> + // Thermal Policy Values
> + //
> + UINT8 EnableDigitalThermalSensor;
> + UINT8 PassiveThermalTripPoint;
> + UINT8 PassiveTc1Value;
> + UINT8 PassiveTc2Value;
> + UINT8 PassiveTspValue;
> + UINT8 DisableActiveTripPoints;
> + UINT8 CriticalThermalTripPoint;
> + UINT8 IchPciExp[4];
> + UINT8 DeepStandby;
> + UINT8 AlsEnable;
> + UINT8 IgdLcdIBia;
> + UINT8 LogBootTime;
> +
> +
> + UINT8 PcieRootPortIOApic[4];
> + UINT8 IffsEnable;
> + UINT8 IffsOnS3RtcWake;
> + UINT8 IffsS3WakeTimerMin;
> + UINT8 IffsOnS3CritBattWake;
> + UINT8 IffsCritBattWakeThreshold;
> + UINT8 ScramblerSupport;
> + UINT8 SecureBoot;
> + UINT8 SecureBootCustomMode;
> + UINT8 SecureBootUserPhysicalPresent;
> + UINT8 CoreFreMultipSelect;
> + UINT8 MaxCState;
> + UINT8 PanelScaling;
> + UINT8 IgdLcdIGmchBlc;
> + UINT8 GfxBoost;
> + UINT8 IgdThermal;
> + UINT8 SEC00;
> + UINT8 fTPM;
> + UINT8 SEC02;
> + UINT8 SEC03;
> + UINT8 MeasuredBootEnable;
> + UINT8 UseProductKey;
> + //Image Signal Processor PCI Device Configuration
> + //
> + UINT8 ISPDevSel;
> + UINT8 ISPEn;
> + // Passwords
> + UINT16 UserPassword[PASSWORD_MAX_SIZE];
> + UINT16 AdminPassword[PASSWORD_MAX_SIZE];
> + UINT8 Tdt;
> + UINT8 Recovery;
> + UINT8 Suspend;
> + UINT8 TdtState;
> + UINT8 TdtEnrolled;
> + UINT8 PBAEnable;
> +
> + UINT8 HpetBootTime;
> + UINT8 UsbDebug;
> + UINT8 Lpe;
> + //
> + // LPSS Configuration
> + //
> + UINT8 LpssPciModeEnabled;
> + //Scc
> + UINT8 LpsseMMCEnabled;
> + UINT8 LpssSdioEnabled;
> + UINT8 LpssSdcardEnabled;
> + UINT8 LpssSdCardSDR25Enabled;
> + UINT8 LpssSdCardDDR50Enabled;
> + UINT8 LpssMipiHsi;
> + UINT8 LpsseMMC45Enabled;
> + UINT8 LpsseMMC45DDR50Enabled;
> + UINT8 LpsseMMC45HS200Enabled;
> + UINT8 LpsseMMC45RetuneTimerValue;
> + UINT8 eMMCBootMode;
> +
> + //LPSS2
> + UINT8 LpssDma1Enabled;
> + UINT8 LpssI2C0Enabled;
> + UINT8 LpssI2C1Enabled;
> + UINT8 LpssI2C2Enabled;
> + UINT8 LpssI2C3Enabled;
> + UINT8 LpssI2C4Enabled;
> + UINT8 LpssI2C5Enabled;
> + UINT8 LpssI2C6Enabled;
> + //LPSS1
> + UINT8 LpssDma0Enabled;
> + UINT8 LpssPwm0Enabled;
> + UINT8 LpssPwm1Enabled;
> + UINT8 LpssHsuart0Enabled;
> + UINT8 LpssHsuart1Enabled;
> + UINT8 LpssSpiEnabled;
> + UINT8 I2CTouchAd;
> +
> + UINT8 GTTSize;
> + //
> + // DVMT5.0 Graphic memory setting
> + //
> + UINT8 IgdDvmt50PreAlloc;
> + UINT8 IgdDvmt50TotalAlloc;
> + UINT8 IgdTurboEnabled;
> +
> + //
> + // Usb Config
> + //
> + UINT8 UsbAutoMode; // PCH controller Auto mode
> + UINT8 UsbXhciSupport;
> + UINT8 Hsic0;
> + UINT8 PchUsb30Mode;
> + UINT8 PchUsb30Streams;
> + UINT8 PchUsb20;
> + UINT8 PchUsbPerPortCtl;
> + UINT8 PchUsbPort[8];
> + UINT8 PchUsbRmh;
> + UINT8 PchUsbOtg;
> + UINT8 PchUsbVbusOn; //OTG VBUS control
> + UINT8 PchFSAOn; //FSA control
> + UINT8 EhciPllCfgEnable;
> +
> +
> + //Gbe
> + UINT8 PcieRootPortSpeed[PCH_PCIE_MAX_ROOT_PORTS];
> + UINT8 SlpLanLowDc;
> +
> + UINT8 ISCT00;
> + UINT8 ISCT01;
> + UINT8 ISCT02;
> + UINT8 ISCT03;
> + UINT8 ISCT04;
> + UINT8 ISCT05;
> + UINT8 ISCT06;
> + UINT8 ISCT07;
> + //
> + // Azalia Configuration
> + //
> + UINT8 PchAzalia;
> + UINT8 AzaliaVCiEnable;
> + UINT8 AzaliaDs;
> + UINT8 AzaliaPme;
> + UINT8 HdmiCodec;
> +
> + UINT8 UartInterface;
> + UINT8 PcuUart1;
> + //UINT8 PcuUart2;//for A0
> + UINT8 StateAfterG3;
> + UINT8 EnableClockSpreadSpec;
> + UINT8 GraphicReserve00;
> + UINT8 GOPEnable;
> + UINT8 GOPBrightnessLevel; //Gop Brightness level
> + UINT8 PavpMode;
> + UINT8 SEC04;
> + UINT8 SEC05;
> + UINT8 SEC06;
> + UINT8 SEC07;
> +
> + UINT8 HdmiCodecPortB;
> + UINT8 HdmiCodecPortC;
> + UINT8 HdmiCodecPortD;
> + UINT8 LidStatus;
> + UINT8 Reserved00;
> + UINT8 Reserved01;
> + UINT16 Reserved02;
> + UINT16 Reserved03;
> + UINT16 Reserved04;
> + UINT16 Reserved05;
> + UINT16 Reserved06;
> + UINT16 Reserved07;
> + UINT16 Reserved08;
> + UINT16 Reserved09;
> + UINT16 Reserved0A;
> + UINT16 Reserved0B;
> + UINT16 Reserved0C;
> + UINT16 Reserved0D;
> + UINT8 Reserved0E;
> + UINT8 Reserved0F;
> + UINT32 Reserved10;
> + UINT32 Reserved11;
> + UINT32 Reserved12;
> + UINT32 Reserved13;
> + UINT32 Reserved14;
> + UINT8 Reserved15;
> + UINT8 Reserved16;
> + UINT8 Reserved17;
> + UINT8 Reserved18;
> + UINT8 Reserved19;
> + UINT8 Reserved1A;
> + UINT8 Reserved1B;
> + UINT8 Reserved1C;
> + UINT8 Reserved1D;
> + UINT8 Reserved1E;
> + UINT8 Reserved1F;
> + UINT8 Reserved20;
> + UINT8 PmicEnable;
> + UINT8 IdleReserve;
> + UINT8 TSEGSizeSel;
> + UINT8 ACPIMemDbg;
> + UINT8 ExISupport;
> + UINT8 BatteryChargingSolution; //0-non ULPMC 1-ULPMC
> + UINT8 PnpSettings;
> + UINT8 CfioPnpSettings;
> + UINT8 PchEhciDebug;
> + UINT8 CRIDSettings;
> + UINT8 ULPMCFWLock;
> + UINT8 SpiRwProtect;
> + UINT8 GraphicReserve02;
> + UINT8 PDMConfig;
> + UINT16 LmMemSize;
> + UINT8 PunitBIOSConfig;
> + UINT8 LpssSdioMode;
> + UINT8 ENDBG2;
> + UINT8 WittEnable;
> + UINT8 UtsEnable;
> + UINT8 TristateLpc;
> + UINT8 GraphicReserve05;
> + UINT8 UsbXhciLpmSupport;
> + UINT8 EnableAESNI;
> + UINT8 SecureErase;
> +
> + UINT8 MmioSize;
> +
> +
> + UINT8 SAR1;
> +
> + UINT8 DisableCodec262;
> + UINT8 ReservedO;
> + UINT8 PcieDynamicGating; // Need PMC enable it first from PMC
> 0x3_12 MCU 318.
> +
> + UINT8 MipiDsi;
> +
> + //Added flow control item for UART1 and UART2
> + UINT8 LpssHsuart0FlowControlEnabled;
> + UINT8 LpssHsuart1FlowControlEnabled;
> +
> + UINT8 SdCardRemovable; // ACPI reporting MMC/SD media as:
> removable/non-removable
> + UINT8 GpioWakeCapability;
> + UINT8 RtcBattery;
> + UINT8 LpeAudioReportedByDSDT;
> +
> + UINT8 Uart1Int3511Com; // Report UART1 as COM with _HID INT3511
> + CHAR16 SystemUuid[37];
> +
> +} SYSTEM_CONFIGURATION;
> +#pragma pack()
> +
> +#ifndef PLATFORM_SETUP_VARIABLE_NAME
> +#define PLATFORM_SETUP_VARIABLE_NAME L"Setup"
> +#endif
> +
> +#pragma pack(1)
> +typedef struct{
> + // Passwords
> + UINT16 UserPassword[PASSWORD_MAX_SIZE];
> + UINT16 AdminPassword[PASSWORD_MAX_SIZE];
> + UINT16 DummyDataForVfrBug; // Don't change or use
> +
> +} SYSTEM_PASSWORDS;
> +#pragma pack()
> +
> +//
> +// #defines for Drive Presence
> +//
> +#define EFI_HDD_PRESENT 0x01
> +#define EFI_HDD_NOT_PRESENT 0x00
> +#define EFI_CD_PRESENT 0x02
> +#define EFI_CD_NOT_PRESENT 0x00
> +
> +#define EFI_HDD_WARNING_ON 0x01
> +#define EFI_CD_WARNING_ON 0x02
> +#define EFI_SMART_WARNING_ON 0x04
> +#define EFI_HDD_WARNING_OFF 0x00
> +#define EFI_CD_WARNING_OFF 0x00
> +#define EFI_SMART_WARNING_OFF 0x00
> +
> +#ifndef VFRCOMPILE
> +extern EFI_GUID gEfiSetupVariableGuid;
> +#endif
> +
> +#define SETUP_DATA SYSTEM_CONFIGURATION
> +
> +#endif // #ifndef _SETUP_VARIABLE
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Hpet.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Hpet.h
> new file mode 100644
> index 0000000000..e448ee9796
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Hpet.h
> @@ -0,0 +1,40 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + Mseg.h
> +
> +Abstract:
> +
> + This file describes the contents of the ACPI HEPT Table.
> +
> +--*/
> +
> +#ifndef _HPET_H
> +#define _HPET_H
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/Acpi10.h>
> +#include <IndustryStandard/Acpi20.h>
> +#include <IndustryStandard/Acpi30.h>
> +#include <IndustryStandard/HighPrecisionEventTimerTable.h>
> +
> +//
> +// HPET Definitions
> +//
> +#define EFI_ACPI_HPET_TABLE_REVISION 0x1
> +#define MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS 0x80
> //approx 1ms
> +
> +#define HPET_BASE_ADDRESS 0xFED00000
> +#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A001
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h
> new file mode 100644
> index 0000000000..484b358264
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h
> @@ -0,0 +1,104 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + BiosIdLib.h
> +
> +Abstract:
> +
> + BIOS ID library definitions.
> +
> + This library provides functions to get BIOS ID, VERSION, DATE and TIME
> +
> +--*/
> +
> +#ifndef _BIOS_ID_LIB_H_
> +#define _BIOS_ID_LIB_H_
> +
> +//
> +// BIOS ID string format:
> +//
> +//
> $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE
> )$(VERSION_MINOR).YYMMDDHHMM
> +//
> +// Example: "TRFTCRB1.86C.0008.D03.0506081529"
> +//
> +#pragma pack(1)
> +
> +typedef struct {
> + CHAR16 BoardId[7]; // "TRFTCRB"
> + CHAR16 BoardRev; // "1"
> + CHAR16 Dot1; // "."
> + CHAR16 OemId[3]; // "86C"
> + CHAR16 Dot2; // "."
> + CHAR16 VersionMajor[4]; // "0008"
> + CHAR16 Dot3; // "."
> + CHAR16 BuildType; // "D"
> + CHAR16 VersionMinor[2]; // "03"
> + CHAR16 Dot4; // "."
> + CHAR16 TimeStamp[10]; // "YYMMDDHHMM"
> + CHAR16 NullTerminator; // 0x0000
> +} BIOS_ID_STRING;
> +
> +#define MEM_IFWIVER_START 0x7E0000
> +#define MEM_IFWIVER_LENGTH 0x1000
> +
> +typedef struct _MANIFEST_OEM_DATA{
> + UINT32 Signature;
> + unsigned char FillNull[0x39];
> + UINT32 IFWIVersionLen;
> + unsigned char IFWIVersion[32];
> +}MANIFEST_OEM_DATA;
> +
> +//
> +// A signature precedes the BIOS ID string in the FV to enable search by
> external tools.
> +//
> +typedef struct {
> + UINT8 Signature[8]; // "$IBIOSI$"
> + BIOS_ID_STRING BiosIdString; // "TRFTCRB1.86C.0008.D03.0506081529"
> +} BIOS_ID_IMAGE;
> +
> +#pragma pack()
> +
> +/**
> + This function returns BIOS ID by searching HOB or FV.
> +
> + @param[in] BiosIdImage The BIOS ID got from HOB or FV
> +
> + @retval EFI_SUCCESS All parameters were valid and BIOS ID has
> been got.
> + @retval EFI_NOT_FOUND BiosId image is not found, and no
> parameter will be modified.
> + @retval EFI_INVALID_PARAMETER The parameter is NULL.
> +
> +**/
> +EFI_STATUS
> +GetBiosId (
> + OUT BIOS_ID_IMAGE *BiosIdImage
> + );
> +
> +/**
> + This function returns the Version & Release Date and Time by getting and
> converting
> + BIOS ID.
> +
> + @param[in] BiosVersion The Bios Version out of the conversion.
> + @param[in] BiosReleaseDate The Bios Release Date out of the
> conversion.
> + @param[in] BiosReleaseTime The Bios Release Time out of the
> conversion.
> +
> + @retval EFI_SUCCESS BIOS Version & Release Date and Time have
> been got successfully.
> + @retval EFI_NOT_FOUND BiosId image is not found, and no
> parameter will be modified.
> + @retval EFI_INVALID_PARAMETER All the parameters are NULL.
> +
> +**/
> +EFI_STATUS
> +GetBiosVersionDateTime (
> + OUT CHAR16 *BiosVersion, OPTIONAL
> + OUT CHAR16 *BiosReleaseDate, OPTIONAL
> + OUT CHAR16 *BiosReleaseTime OPTIONAL
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/CpuIA32.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/CpuIA32.h
> new file mode 100644
> index 0000000000..78c78319ce
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/CpuIA32.h
> @@ -0,0 +1,345 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + CpuIA32.h
> +
> +Abstract:
> +
> +--*/
> +
> +#ifndef _CPU_IA32_H
> +#define _CPU_IA32_H
> +
> +typedef struct {
> + UINT32 RegEax;
> + UINT32 RegEbx;
> + UINT32 RegEcx;
> + UINT32 RegEdx;
> +} EFI_CPUID_REGISTER;
> +
> +typedef struct {
> + UINT32 HeaderVersion;
> + UINT32 UpdateRevision;
> + UINT32 Date;
> + UINT32 ProcessorId;
> + UINT32 Checksum;
> + UINT32 LoaderRevision;
> + UINT32 ProcessorFlags;
> + UINT32 DataSize;
> + UINT32 TotalSize;
> + UINT8 Reserved[12];
> +} EFI_CPU_MICROCODE_HEADER;
> +
> +typedef struct {
> + UINT32 ExtendedSignatureCount;
> + UINT32 ExtendedTableChecksum;
> + UINT8 Reserved[12];
> +} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;
> +
> +typedef struct {
> + UINT32 ProcessorSignature;
> + UINT32 ProcessorFlag;
> + UINT32 ProcessorChecksum;
> +} EFI_CPU_MICROCODE_EXTENDED_TABLE;
> +
> +typedef struct {
> + UINT32 Stepping : 4;
> + UINT32 Model : 4;
> + UINT32 Family : 4;
> + UINT32 Type : 2;
> + UINT32 Reserved1 : 2;
> + UINT32 ExtendedModel : 4;
> + UINT32 ExtendedFamily : 8;
> + UINT32 Reserved2 : 4;
> +} EFI_CPU_VERSION;
> +
> +#define EFI_CPUID_SIGNATURE 0x0
> +#define EFI_CPUID_VERSION_INFO 0x1
> +#define EFI_CPUID_CACHE_INFO 0x2
> +#define EFI_CPUID_SERIAL_NUMBER 0x3
> +#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000
> +#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001
> +#define EFI_CPUID_BRAND_STRING1 0x80000002
> +#define EFI_CPUID_BRAND_STRING2 0x80000003
> +#define EFI_CPUID_BRAND_STRING3 0x80000004
> +
> +#define EFI_MSR_IA32_PLATFORM_ID 0x17
> +#define EFI_MSR_IA32_APIC_BASE 0x1B
> +#define EFI_MSR_EBC_HARD_POWERON 0x2A
> +#define EFI_MSR_EBC_SOFT_POWERON 0x2B
> +#define BINIT_DRIVER_DISABLE 0x40
> +#define INTERNAL_MCERR_DISABLE 0x20
> +#define INITIATOR_MCERR_DISABLE 0x10
> +#define EFI_MSR_EBC_FREQUENCY_ID 0x2C
> +#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79
> +#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B
> +#define EFI_MSR_PSB_CLOCK_STATUS 0xCD
> +#define EFI_APIC_GLOBAL_ENABLE 0x800
> +#define EFI_MSR_IA32_MISC_ENABLE 0x1A0
> +#define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000
> +#define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008
> +#define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004
> +#define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002
> +#define FAST_STRING_ENABLE_BIT 0x00000001
> +
> +#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200
> +#define EFI_CACHE_VARIABLE_MTRR_END 0x20F
> +#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF
> +#define EFI_CACHE_MTRR_VALID 0x800
> +#define EFI_CACHE_FIXED_MTRR_VALID 0x400
> +#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
> +#define EFI_MSR_VALID_MASK 0xFFFFFFFFF
> +#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000
> +#define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF
> +
> +#define EFI_IA32_MTRR_FIX64K_00000 0x250
> +#define EFI_IA32_MTRR_FIX16K_80000 0x258
> +#define EFI_IA32_MTRR_FIX16K_A0000 0x259
> +#define EFI_IA32_MTRR_FIX4K_C0000 0x268
> +#define EFI_IA32_MTRR_FIX4K_C8000 0x269
> +#define EFI_IA32_MTRR_FIX4K_D0000 0x26A
> +#define EFI_IA32_MTRR_FIX4K_D8000 0x26B
> +#define EFI_IA32_MTRR_FIX4K_E0000 0x26C
> +#define EFI_IA32_MTRR_FIX4K_E8000 0x26D
> +#define EFI_IA32_MTRR_FIX4K_F0000 0x26E
> +#define EFI_IA32_MTRR_FIX4K_F8000 0x26F
> +
> +#define EFI_IA32_MCG_CAP 0x179
> +#define EFI_IA32_MCG_CTL 0x17B
> +#define EFI_IA32_MC0_CTL 0x400
> +#define EFI_IA32_MC0_STATUS 0x401
> +
> +#define EFI_IA32_PERF_STATUS 0x198
> +#define EFI_IA32_PERF_CTL 0x199
> +
> +#define EFI_CACHE_UNCACHEABLE 0
> +#define EFI_CACHE_WRITECOMBINING 1
> +#define EFI_CACHE_WRITETHROUGH 4
> +#define EFI_CACHE_WRITEPROTECTED 5
> +#define EFI_CACHE_WRITEBACK 6
> +
> +//
> +// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number
> +//
> +#define EfiMakeCpuVersion(f, m, s) \
> + (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))
> +
> +/**
> + Halt the Cpu
> +
> + @param[in] None
> +
> + @retval None
> +
> +**/
> +VOID
> +EFIAPI
> +EfiHalt (
> + VOID
> + );
> +
> +/**
> + Write back and invalidate the Cpu cache
> +
> + @param[in] None
> +
> + @retval None
> +
> +**/
> +VOID
> +EFIAPI
> +EfiWbinvd (
> + VOID
> + );
> +
> +/**
> + Invalidate the Cpu cache
> +
> + @param[in] None
> +
> + @retval None
> +
> +**/
> +VOID
> +EFIAPI
> +EfiInvd (
> + VOID
> + );
> +
> +/**
> + Get the Cpu info by execute the CPUID instruction
> +
> + @param[in] RegisterInEax The input value to put into register EAX
> + @param[in] Regs The Output value
> +
> + @retval None
> +
> +**/
> +VOID
> +EFIAPI
> +EfiCpuid (
> + IN UINT32 RegisterInEax,
> + OUT EFI_CPUID_REGISTER *Regs
> + );
> +
> +/**
> + When RegisterInEax != 4, the functionality is the same as EfiCpuid.
> + When RegisterInEax == 4, the function return the deterministic cache
> + parameters by excuting the CPUID instruction.
> +
> + @param[in] RegisterInEax The input value to put into register EAX.
> + @param[in] CacheLevel The deterministic cache level.
> + @param[in] Regs The Output value.
> +
> + @retval None
> +
> +**/
> +VOID
> +EFIAPI
> +EfiCpuidExt (
> + IN UINT32 RegisterInEax,
> + IN UINT32 CacheLevel,
> + OUT EFI_CPUID_REGISTER *Regs
> + );
> +
> +/**
> + Read Cpu MSR
> +
> + @param[in] Index The index value to select the register
> +
> + @retval Return the read data
> +
> +**/
> +UINT64
> +EFIAPI
> +EfiReadMsr (
> + IN UINT32 Index
> + );
> +
> +/**
> + Write Cpu MSR
> +
> + @param[in] Index The index value to select the register
> + @param[in] Value The value to write to the selected register
> +
> + @retval None
> +
> +**/
> +VOID
> +EFIAPI
> +EfiWriteMsr (
> + IN UINT32 Index,
> + IN UINT64 Value
> + );
> +
> +/**
> + Read Time stamp
> +
> + @param[in] None
> +
> + @retval Return the read data
> +
> +**/
> +UINT64
> +EFIAPI
> +EfiReadTsc (
> + VOID
> + );
> +
> +/**
> + Writing back and invalidate the cache,then diable it
> +
> + @param[in] None
> +
> + @retval None
> +
> +**/
> +VOID
> +EFIAPI
> +EfiDisableCache (
> + VOID
> + );
> +
> +/**
> + Invalidate the cache,then Enable it
> +
> + @param[in] None
> +
> + @retval None
> +
> +**/
> +VOID
> +EFIAPI
> +EfiEnableCache (
> + VOID
> + );
> +
> +/**
> + Get Eflags
> +
> + @param[in] None
> +
> + @retval Return the Eflags value
> +
> +**/
> +UINT32
> +EFIAPI
> +EfiGetEflags (
> + VOID
> + );
> +
> +/**
> + Disable Interrupts
> +
> + @param[in] None
> +
> + @retval None
> +
> +**/
> +VOID
> +EFIAPI
> +EfiDisableInterrupts (
> + VOID
> + );
> +
> +/**
> + Enable Interrupts
> +
> + @param[in] None
> +
> + @retval None
> +
> +**/
> +VOID
> +EFIAPI
> +EfiEnableInterrupts (
> + VOID
> + );
> +
> +/**
> + Extract CPU detail version infomation
> +
> + @param[in] FamilyId FamilyId, including ExtendedFamilyId
> + @param[in] Model Model, including ExtendedModel
> + @param[in] SteppingId SteppingId
> + @param[in] Processor Processor
> +
> +**/
> +VOID
> +EFIAPI
> +EfiCpuVersion (
> + IN UINT16 *FamilyId, OPTIONAL
> + IN UINT8 *Model, OPTIONAL
> + IN UINT8 *SteppingId, OPTIONAL
> + IN UINT8 *Processor OPTIONAL
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h
> new file mode 100644
> index 0000000000..915f8b39d9
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h
> @@ -0,0 +1,196 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + EfiRegTableLib.h
> +
> +Abstract:
> +
> + Definitions and macros for building register tables for chipset
> + initialization..
> +
> + Components linking this lib must include CpuIo, PciRootBridgeIo, and
> + BootScriptSave protocols in their DPX.
> +
> +
> +
> +--*/
> +
> +#ifndef EFI_REG_TABLE_H
> +#define EFI_REG_TABLE_H
> +
> +
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Protocol/CpuIo.h>
> +#include <Protocol/BootScriptSave.h>
> +#include <Framework/BootScript.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +
> +
> +#define OPCODE_BASE(OpCode) ((UINT8)((OpCode) & 0xFF))
> +#define OPCODE_FLAGS(OpCode) ((UINT8)(((OpCode) >> 8) & 0xFF))
> +#define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16))
> +
> +//
> +// RegTable Base OpCodes
> +//
> +#define OP_TERMINATE_TABLE 0
> +#define OP_MEM_WRITE 1
> +#define OP_MEM_READ_MODIFY_WRITE 2
> +#define OP_IO_WRITE 3
> +#define OP_IO_READ_MODIFY_WRITE 4
> +#define OP_PCI_WRITE 5
> +#define OP_PCI_READ_MODIFY_WRITE 6
> +#define OP_STALL 7
> +
> +//
> +// RegTable OpCode Flags
> +//
> +#define OPCODE_FLAG_S3SAVE 1
> +
> +
> +#define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0,
> (UINT32) 0 }
> +
> +
> +//
> +// REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of
> the OpCode
> +// as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values
> +//
> +typedef struct {
> + UINT32 OpCode;
> + UINT32 PciAddress;
> + UINT32 Data;
> +} EFI_REG_TABLE_PCI_WRITE;
> +
> +#define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag) \
> + { \
> + (UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
> + (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \
> + (UINT32) (Data), \
> + (UINT32) (0) \
> + }
> +
> +typedef struct {
> + UINT32 OpCode;
> + UINT32 MemAddress;
> + UINT32 Data;
> +} EFI_REG_TABLE_MEM_WRITE;
> +
> +typedef struct {
> + UINT32 OpCode;
> + UINT32 PciAddress;
> + UINT32 OrMask;
> + UINT32 AndMask;
> +} EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;
> +
> +#define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask,
> AndMask, S3Flag) \
> + { \
> + (UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) <<
> 16)), \
> + (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \
> + (UINT32) (OrMask), \
> + (UINT32) (AndMask) \
> + }
> +
> +typedef struct {
> + UINT32 OpCode;
> + UINT32 MemAddress;
> + UINT32 OrMask;
> + UINT32 AndMask;
> +} EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;
> +
> +#define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask,
> S3Flag) \
> + { \
> + (UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width)
> << 16)), \
> + (UINT32) (Address), \
> + (UINT32) (OrMask), \
> + (UINT32) (AndMask) \
> + }
> +
> +typedef struct {
> + UINT32 OpCode;
> + UINT32 Field2;
> + UINT32 Field3;
> + UINT32 Field4;
> +} EFI_REG_TABLE_GENERIC;
> +
> +typedef union {
> + EFI_REG_TABLE_GENERIC Generic;
> + EFI_REG_TABLE_PCI_WRITE PciWrite;
> + EFI_REG_TABLE_PCI_READ_MODIFY_WRITE PciReadModifyWrite;
> + EFI_REG_TABLE_MEM_READ_MODIFY_WRITE MemReadModifyWrite;
> +} EFI_REG_TABLE;
> +
> +/**
> + Processes register table assuming which may contain PCI, IO, MEM, and
> STALL
> + entries.
> +
> + No parameter checking is done so the caller must be careful about omitting
> + values for PciRootBridgeIo or CpuIo parameters. If the regtable does
> + not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
> + NULL). If the regtable does not contain any IO or Mem entries, it is safe to
> + omit the CpuIo (supply NULL).
> +
> + The RegTableEntry parameter is not checked, but is required.
> +
> + gBS is assumed to have been defined and is used when processing stalls.
> +
> + The function processes each entry sequentially until an
> OP_TERMINATE_TABLE
> + entry is encountered.
> +
> + @param[in] RegTableEntry A pointer to the register table to process
> +
> + @param[in] PciRootBridgeIo A pointer to the instance of PciRootBridgeIo
> that is used
> + when processing PCI table entries
> +
> + @param[in] CpuIo A pointer to the instance of CpuIo that is used
> when processing IO and
> + MEM table entries
> +
> + @retval Nothing.
> +
> +**/
> +VOID
> +ProcessRegTablePci (
> + EFI_REG_TABLE * RegTableEntry,
> + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo,
> + EFI_CPU_IO_PROTOCOL * CpuIo
> + );
> +
> +/**
> + Processes register table assuming which may contain IO, MEM, and STALL
> + entries, but must NOT contain any PCI entries. Any PCI entries cause an
> + ASSERT in a DEBUG build and are skipped in a free build.
> +
> + No parameter checking is done. Both RegTableEntry and CpuIo
> parameters are
> + required.
> +
> + gBS is assumed to have been defined and is used when processing stalls.
> +
> + The function processes each entry sequentially until an
> OP_TERMINATE_TABLE
> + entry is encountered.
> +
> + @param[in] RegTableEntry - A pointer to the register table to process
> +
> + @param[in] CpuIo - A pointer to the instance of CpuIo that is used when
> processing IO and
> + MEM table entries
> +
> + @retval Nothing.
> +
> +**/
> +VOID
> +ProcessRegTableCpu (
> + EFI_REG_TABLE * RegTableEntry,
> + EFI_CPU_IO_PROTOCOL * CpuIo
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/Esrt.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/Esrt.h
> new file mode 100644
> index 0000000000..a92a27cade
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/Esrt.h
> @@ -0,0 +1,74 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + Esrt.h
> +
> +Abstract:
> +
> +--*/
> +
> +#ifndef _DFU_ESRT_H_
> +#define _DFU_ESRT_H_
> +
> +typedef struct {
> + EFI_GUID FwClass;
> + UINT32 FwType;
> + UINT32 FwVersion;
> + UINT32 FwLstCompatVersion;
> + UINT32 CapsuleFlags;
> + UINT32 LastAttemptVersion;
> + UINT32 LastAttemptStatus;
> +} FW_RES_ENTRY;
> +
> +typedef struct {
> + UINT32 NumEntries;
> + FW_RES_ENTRY FwEntries[256];
> +} FW_RES_ENTRY_LIST;
> +
> +
> +typedef struct {
> + UINT32 FwResourceCount;
> + UINT32 FwResourceMax;
> + UINT64 FwResourceVersion;
> +} EFI_SYSTEM_RESOURCE_TABLE;
> +
> +
> +typedef
> +EFI_STATUS
> +(EFIAPI *ESRT_POPULATE_TABLE) (
> +);
> +
> +typedef
> +EFI_STATUS
> +(EFIAPI *ESRT_UPDATE_TABLE_ENTRY_BY_GUID) (
> + IN EFI_GUID FwEntryGuid,
> + IN FW_RES_ENTRY *FwEntry
> +);
> +
> +typedef
> +EFI_STATUS
> +(EFIAPI *ESRT_GET_FW_ENTRY_BY_GUID) (
> + IN EFI_GUID FwEntryGuid,
> + OUT FW_RES_ENTRY *FwEntry
> +);
> +
> +
> +#pragma pack()
> +
> +typedef struct _ESRT_OPERATION_PROTOCOL {
> + ESRT_POPULATE_TABLE
> EsrtPopulateTable;
> + ESRT_UPDATE_TABLE_ENTRY_BY_GUID
> EsrtUpdateTableEntryByGuid;
> + ESRT_GET_FW_ENTRY_BY_GUID
> EsrtGetFwEntryByGuid;
> +} ESRT_OPERATION_PROTOCOL;
> +
> +extern EFI_GUID gEfiEsrtOperationProtocolGuid;
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/Fd.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/Fd.h
> new file mode 100644
> index 0000000000..a54ac11162
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/Fd.h
> @@ -0,0 +1,264 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +Module Name:
> +
> + Fd.h
> +
> +Abstract:
> +
> + EFI Intel82802AB/82802AC Firmware Hub.
> +
> +
> +--*/
> +
> +
> +//
> +// Supported SPI devices
> +//
> +
> +//
> +// MFG and Device code
> +//
> +#define SST_25LF040A 0x0044BF
> +#define SST_25LF040 0x0040BF
> +#define SST_25LF080A 0x0080BF
> +#define SST_25VF080B 0x008EBF
> +#define SST_25VF016B 0x0041BF
> +#define SST_25VF032B 0x004ABF
> +
> +#define PMC_25LV040 0x007E9D
> +
> +#define ATMEL_26DF041 0x00441F
> +#define Atmel_AT26F004 0x00041F
> +#define Atmel_AT26DF081A 0x01451F
> +#define Atmel_AT25DF161 0x02461F
> +#define Atmel_AT26DF161 0x00461F
> +#define Atmel_AT25DF641 0x00481F
> +#define Atmel_AT26DF321 0x00471F
> +
> +#define Macronix_MX25L8005 0x1420C2
> +#define Macronix_MX25L1605A 0x1520C2
> +#define Macronix_MX25L3205D 0x1620C2
> +
> +#define STMicro_M25PE80 0x148020
> +
> +#define Winbond_W25X40 0x1330EF
> +#define Winbond_W25X80 0x1430EF
> +#define Winbond_W25Q80 0x1440EF
> +
> +#define Winbond_W25X16 0x1540EF // W25Q16
> +#define Winbond_W25X32 0x1630EF
> +
> +//
> +// NOTE: Assuming that 8Mbit flash will only contain a 4Mbit binary.
> +// Treating 4Mbit and 8Mbit devices the same.
> +//
> +
> +//
> +// BIOS Base Address
> +//
> +#define BIOS_BASE_ADDRESS_4M 0xFFF80000
> +#define BIOS_BASE_ADDRESS_8M 0xFFF00000
> +#define BIOS_BASE_ADDRESS_16M 0xFFE00000
> +
> +//
> +// block and sector sizes
> +//
> +#define SECTOR_SIZE_256BYTE 0x100 // 256byte page size
> +#define SECTOR_SIZE_4KB 0x1000 // 4kBytes sector size
> +#define BLOCK_SIZE_32KB 0x00008000 // 32Kbytes block size
> +#define MAX_FLASH_SIZE 0x00400000 // 32Mbit (Note that this can also
> be used for the 4Mbit & 8Mbit)
> +
> +//
> +// Flash commands
> +//
> +#define SPI_SST25LF_COMMAND_WRITE 0x02
> +#define SPI_SST25LF_COMMAND_READ 0x03
> +#define SPI_SST25LF_COMMAND_ERASE 0x20
> +#define SPI_SST25LF_COMMAND_WRITE_DISABLE 0x04
> +#define SPI_SST25LF_COMMAND_READ_STATUS 0x05
> +#define SPI_SST25LF_COMMAND_WRITE_ENABLE 0x06
> +#define SPI_SST25LF_COMMAND_READ_ID 0xAB
> +#define SPI_SST25LF_COMMAND_WRITE_S_EN 0x50
> +#define SPI_SST25LF_COMMAND_WRITE_S 0x01
> +
> +#define SPI_PMC25LV_COMMAND_WRITE 0x02
> +#define SPI_PMC25LV_COMMAND_READ 0x03
> +#define SPI_PMC25LV_COMMAND_ERASE 0xD7
> +#define SPI_PMC25LV_COMMAND_WRITE_DISABLE 0x04
> +#define SPI_PMC25LV_COMMAND_READ_STATUS 0x05
> +#define SPI_PMC25LV_COMMAND_WRITE_ENABLE 0x06
> +#define SPI_PMC25LV_COMMAND_READ_ID 0xAB
> +#define SPI_PMC25LV_COMMAND_WRITE_S_EN 0x06
> +#define SPI_PMC25LV_COMMAND_WRITE_S 0x01
> +
> +#define SPI_AT26DF_COMMAND_WRITE 0x02
> +#define SPI_AT26DF_COMMAND_READ 0x03
> +#define SPI_AT26DF_COMMAND_ERASE 0x20
> +#define SPI_AT26DF_COMMAND_WRITE_DISABLE 0x00
> +#define SPI_AT26DF_COMMAND_READ_STATUS 0x05
> +#define SPI_AT26DF_COMMAND_WRITE_ENABLE 0x00
> +#define SPI_AT26DF_COMMAND_READ_ID 0x9F
> +#define SPI_AT26DF_COMMAND_WRITE_S_EN 0x00
> +#define SPI_AT26DF_COMMAND_WRITE_S 0x00
> +
> +#define SPI_AT26F_COMMAND_WRITE 0x02
> +#define SPI_AT26F_COMMAND_READ 0x03
> +#define SPI_AT26F_COMMAND_ERASE 0x20
> +#define SPI_AT26F_COMMAND_WRITE_DISABLE 0x04
> +#define SPI_AT26F_COMMAND_READ_STATUS 0x05
> +#define SPI_AT26F_COMMAND_WRITE_ENABLE 0x06
> +#define SPI_AT26F_COMMAND_JEDEC_ID 0x9F
> +#define SPI_AT26F_COMMAND_WRITE_S_EN 0x00
> +#define SPI_AT26F_COMMAND_WRITE_S 0x01
> +#define SPI_AT26F_COMMAND_WRITE_UNPROTECT 0x39
> +
> +#define SPI_SST25VF_COMMAND_WRITE 0x02
> +#define SPI_SST25VF_COMMAND_READ 0x03
> +#define SPI_SST25VF_COMMAND_ERASE 0x20
> +#define SPI_SST25VF_COMMAND_WRITE_DISABLE 0x04
> +#define SPI_SST25VF_COMMAND_READ_STATUS 0x05
> +#define SPI_SST25VF_COMMAND_WRITE_ENABLE 0x06
> +#define SPI_SST25VF_COMMAND_READ_ID 0xAB
> +#define SPI_SST25VF_COMMAND_JEDEC_ID 0x9F
> +#define SPI_SST25VF_COMMAND_WRITE_S_EN 0x50
> +#define SPI_SST25VF_COMMAND_WRITE_S 0x01
> +
> +#define SPI_STM25PE_COMMAND_WRITE 0x02
> +#define SPI_STM25PE_COMMAND_READ 0x03
> +#define SPI_STM25PE_COMMAND_ERASE 0xDB
> +#define SPI_STM25PE_COMMAND_WRITE_DISABLE 0x04
> +#define SPI_STM25PE_COMMAND_READ_STATUS 0x05
> +#define SPI_STM25PE_COMMAND_WRITE_ENABLE 0x06
> +#define SPI_STM25PE_COMMAND_JEDEC_ID 0x9F
> +
> +#define SPI_WinbondW25X_COMMAND_WRITE_S 0x01
> +#define SPI_WinbondW25X_COMMAND_WRITE 0x02
> +#define SPI_WinbondW25X_COMMAND_READ 0x03
> +#define SPI_WinbondW25X_COMMAND_READ_STATUS 0x05
> +#define SPI_WinbondW25X_COMMAND_ERASE_S 0x20
> +#define SPI_WinbondW25X_COMMAND_WRITE_ENABLE 0x06
> +#define SPI_WinbondW25X_COMMAND_JEDEC_ID 0x9F
> +
> +//
> +// SPI default opcode slots
> +//
> +#define SPI_OPCODE_WRITE_INDEX 0
> +#define SPI_OPCODE_READ_INDEX 1
> +#define SPI_OPCODE_ERASE_INDEX 2
> +#define SPI_OPCODE_READ_S_INDEX 3
> +#define SPI_OPCODE_READ_ID_INDEX 4
> +#define SPI_OPCODE_WRITE_S_INDEX 6
> +#define SPI_OPCODE_WRITE_UNPROTECT_INDEX 7
> +
> +#define SPI_PREFIX_WRITE_S_EN 1
> +#define SPI_PREFIX_WRITE_EN 0
> +
> +//
> +// Atmel AT26F00x
> +//
> +#define B_AT26F_STS_REG_SPRL 0x80
> +#define B_AT26F_STS_REG_SWP 0x0C
> +
> +//
> +// Block lock bit definitions:
> +//
> +#define READ_LOCK 0x04
> +#define LOCK_DOWN 0x02
> +#define WRITE_LOCK 0x01
> +#define FULL_ACCESS 0x00
> +
> +//
> +// Function Prototypes
> +//
> +EFI_STATUS
> +FlashGetNextBlock (
> + IN UINTN* Key,
> + OUT EFI_PHYSICAL_ADDRESS* BlockAddress,
> + OUT UINTN* BlockSize
> + );
> +
> +EFI_STATUS
> +FlashGetSize (
> + OUT UINTN* Size
> + );
> +
> +EFI_STATUS
> +FlashGetUniformBlockSize (
> + OUT UINTN* Size
> + );
> +
> +EFI_STATUS
> +FlashEraseWithNoTopSwapping (
> + IN UINT8 *BaseAddress,
> + IN UINTN NumBytes
> + );
> +
> +EFI_STATUS
> +FlashErase (
> + IN UINT8 *BaseAddress,
> + IN UINTN NumBytes
> + );
> +
> +EFI_STATUS
> +FlashWriteWithNoTopSwapping (
> + IN UINT8* DstBufferPtr,
> + IN UINT8* SrcBufferPtr,
> + IN UINTN NumBytes
> + );
> +
> +EFI_STATUS
> +FlashWrite (
> + IN UINT8 *DstBufferPtr,
> + IN UINT8 *SrcBufferPtr,
> + IN UINTN NumBytes
> + );
> +
> +EFI_STATUS
> +FlashReadWithNoTopSwapping (
> + IN UINT8 *BaseAddress,
> + IN UINT8 *DstBufferPtr,
> + IN UINTN NumBytes
> + );
> +
> +EFI_STATUS
> +FlashRead (
> + IN UINT8 *BaseAddress,
> + IN UINT8 *DstBufferPtr,
> + IN UINTN NumBytes
> + );
> +
> +EFI_STATUS
> +FlashLockWithNoTopSwapping (
> + IN UINT8* BaseAddress,
> + IN UINTN NumBytes,
> + IN UINT8 LockState
> + );
> +
> +EFI_STATUS
> +FlashLock(
> + IN UINT8 *BaseAddress,
> + IN UINTN NumBytes,
> + IN UINT8 LockState
> + );
> +
> +EFI_STATUS
> +CheckIfErased(
> + IN UINT8 *DstBufferPtr,
> + IN UINTN NumBytes
> + );
> +
> +EFI_STATUS
> +CheckIfFlashIsReadyForWrite (
> + IN UINT8 *DstBufferPtr,
> + IN UINT8 *SrcBufferPtr,
> + IN UINTN NumBytes
> + );
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h
> new file mode 100644
> index 0000000000..43c5e88586
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h
> @@ -0,0 +1,122 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> + Flash device library class header file.
> +
> + Flash Device Library common type, MACRO and API definition. The basic
> idea for
> + this library is to provide API to abstract the different between flash
> + technology (SPI, FWH etc..), flash controller (SPI host controller on
> + ICH, MMIO type access for FWH), flash chip (programming command,
> method
> + of status checking). This library class can be consumed by drivers or
> applications
> + such as Firmware Volume Block driver, Flash Update application. These
> driver
> + can be written in a generic manner so that they are more easy to be
> + ported to other platforms.
> +
> + This library can be build on a set of APIs which can touch flash controller,
> flash
> + chip directly for a platform with simple flash device configuration.
> +
> + For a platform with complex flash device configuration, this library can be
> built
> + on the Flash Device Operate Library. Please see the header file for that
> library
> + class for detailed usage.
> +
> +**/
> +
> +#ifndef __FLASHDEVICE_LIB_H__
> +#define __FLASHDEVICE_LIB_H__
> +
> +/**
> + Read NumBytes bytes of data from the address specified by
> + PAddress into Buffer.
> +
> + @param[in] PAddress The starting physical address of the read.
> + @param[in,out] NumBytes On input, the number of bytes to read. On
> output, the number
> + of bytes actually read.
> + @param[out] Buffer The destination data buffer for the read.
> +
> + @retval EFI_SUCCESS. Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibFvbFlashDeviceRead (
> + IN UINTN PAddress,
> + IN OUT UINTN *NumBytes,
> + OUT UINT8 *Buffer
> + );
> +
> +/**
> + Write NumBytes bytes of data from Buffer to the address specified by
> + PAddresss.
> +
> + @param[in] PAddress The starting physical address of the write.
> + @param[in,out] NumBytes On input, the number of bytes to write. On
> output,
> + the actual number of bytes written.
> + @param[in] Buffer The source data buffer for the write.
> +
> + @retval EFI_SUCCESS. Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibFvbFlashDeviceWrite (
> + IN UINTN PAddress,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + );
> +
> +/**
> + Erase the block staring at PAddress.
> +
> + @param[in] PAddress The starting physical address of the region to be
> erased.
> + @param[in] LbaLength The length of the region to be erased. This
> parameter is necessary
> + as the physical block size on a flash device could be different
> than
> + the logical block size of Firmware Volume Block protocol. Erase
> on
> + flash chip is always performed block by block. Therefore, the
> ERASE
> + operation to a logical block is converted a number of ERASE
> operation
> + (or a partial erase) on the hardware.
> +
> + @retval EFI_SUCCESS. Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibFvbFlashDeviceBlockErase (
> + IN UINTN PAddress,
> + IN UINTN LbaLength
> +);
> +
> +/**
> + Lock or unlock the block staring at PAddress.
> +
> + @param[in] PAddress The starting physical address of region to be
> (un)locked.
> + @param[in] LbaLength The length of the region to be (un)locked. This
> parameter is necessary
> + as the physical block size on a flash device could be different
> than
> + the logical block size of Firmware Volume Block protocol.
> (Un)Lock on
> + flash chip is always performed block by block. Therefore, the
> (Un)Lock
> + operation to a logical block is converted a number of (Un)Lock
> operation
> + (or a partial erase) on the hardware.
> + @param[in] Lock TRUE to lock. FALSE to unlock.
> +
> + @retval EFI_SUCCESS. Opertion is successful.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibFvbFlashDeviceBlockLock (
> + IN UINTN PAddress,
> + IN UINTN LbaLength,
> + IN BOOLEAN Lock
> +);
> +
> +#endif
> +
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2CLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2CLib.h
> new file mode 100644
> index 0000000000..672c2b45f9
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2CLib.h
> @@ -0,0 +1,58 @@
> +/** @file
> + Interface Definitions for I2C Lib.
> +
> + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +--*/
> +
> +#include <Uefi.h>
> +#include <Library/IoLib.h>
> +
> +#ifndef I2C_LIB_HEADER_H
> +#define I2C_LIB_HEADER_H
> +
> +
> +/**
> + Reads a Byte from I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be read
> + @param Offset Offset from which the data has to be read
> + @param ReadBytes Number of bytes to be read
> + @param *ReadBuffer Address to which the value read has to be
> stored
> +
> + @return EFI_SUCCESS If the byte value has been successfully read
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS
> +ByteReadI2C(
> + IN UINT8 BusNo,
> + IN UINT8 SlaveAddress,
> + IN UINT8 Offset,
> + IN UINTN ReadBytes,
> + OUT UINT8 *ReadBuffer
> + );
> +
> +/**
> + Writes a Byte to I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be written
> + @param Offset Offset from which the data has to be written
> + @param WriteBytes Number of bytes to be written
> + @param *Byte Address to which the value written is stored
> +
> + @return EFI_SUCCESS If the byte value has been successfully read
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS ByteWriteI2C(
> + IN UINT8 BusNo,
> + IN UINT8 SlaveAddress,
> + IN UINT8 Offset,
> + IN UINTN WriteBytes,
> + IN UINT8 *WriteBuffer
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h
> new file mode 100644
> index 0000000000..7eea7e1d29
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h
> @@ -0,0 +1,23 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef __MMIO_CONFIG_LIB_H__
> +#define __MMIO_CONFIG_LIB_H__
> +
> +#include <Protocol/MmioDevice.h>
> +
> +///
> +/// Declare the memory mapped I/O devices assocaited with the
> +/// board.
> +///
> +extern CONST EFI_MMIO_DEVICE_PROTOCOL gMmioDeviceList [ ];
> +extern CONST UINTN gMmioDeviceCount;
> +
> +#endif // __MMIO_CONFIG_LIB_H__
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h
> new file mode 100644
> index 0000000000..9975faeac8
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h
> @@ -0,0 +1,26 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef _I2C_PORT_H
> +#define _I2C_PORT_H
> +
> +//
> +// Types
> +//
> +
> +//
> +// Context passed from platform (board) layer to the I2C port driver.
> +//
> +typedef struct {
> + EFI_PHYSICAL_ADDRESS BaseAddress;
> + UINT32 InputFrequencyHertz;
> +} I2C_PIO_PLATFORM_CONTEXT;
> +
> +#endif // _I2C_PORT_A0_H
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h
> new file mode 100644
> index 0000000000..06dab3016b
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h
> @@ -0,0 +1,50 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +--*/
> +
> +#ifndef _FSA_LIB_H
> +#define _FSA_LIB_H
> +#include <Uefi.h>
> +#include <Uefi/UefiSpec.h>
> +
> +#define FSA_REG_DEVID 0x1
> +#define FSA_REG_CTRL 0x2
> +#define FSA_REG_INTR 0x3
> +#define FSA_REG_INTR_MSK 0x5
> +#define FSA_REG_RESISTOR_CODE 0x7
> +#define FSA_REG_TIMING_SET 0x8
> +#define FSA_REG_STATUS 0x9
> +#define FSA_REG_DEV_TYPE 0xA
> +#define FSA_REG_DAC_SAR 0xB
> +#define FSA_REG_MANUAL_SW 0x13
> +#define FSA_REG_MANUAL_CHG_CTRL 0x14
> +
> +extern
> +EFI_STATUS
> +EFIAPI
> +FsaUsbDeviceMode (
> + VOID
> +);
> +
> +
> +extern
> +EFI_STATUS
> +EFIAPI
> +DisableFsaTimerHandler (
> + VOID
> +);
> +
> +extern
> +EFI_STATUS
> +EFIAPI
> +FSAInit (
> + IN UINT32 FFRDVer
> +);
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h
> new file mode 100644
> index 0000000000..c3235afa90
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h
> @@ -0,0 +1,23 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +--*/
> +
> +#ifndef _PLATFORM_FSP_LIB_H
> +#define _PLATFORM_FSP_LIB_H
> +#include <Base.h>
> +#include <Uefi.h>
> +
> +extern
> +EFI_STATUS
> +PlatformHobCreateFromFsp (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + VOID *HobList
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H
> new file mode 100644
> index 0000000000..335660cd4c
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H
> @@ -0,0 +1,239 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +**/
> +
> +#ifndef _SPIFlash_H_
> +#define _SPIFlash_H_
> +
> +#include <Protocol/Spi.h>
> +
> +//EFI_STATUS SpiFlashLock(BOOLEAN Lock);
> +//EFI_STATUS SpiFlashInit(void);
> +
> +typedef enum {
> + EnumSpiFlashW25Q64,
> + EnumSpiFlashAT25DF321A,
> + EnumSpiFlashAT26DF321,
> + EnumSpiFlashAT25DF641,
> + EnumSpiFlashW25Q16,
> + EnumSpiFlashW25Q32,
> + EnumSpiFlashW25X32,
> + EnumSpiFlashW25X64,
> + EnumSpiFlashW25Q128,
> + EnumSpiFlashMX25L16,
> + EnumSpiFlashMX25L32,
> + EnumSpiFlashMX25L64,
> + EnumSpiFlashMX25L128,
> + EnumSpiFlashMX25U6435F,
> + EnumSpiFlashSST25VF016B,
> + EnumSpiFlashSST25VF064C,
> + EnumSpiFlashN25Q064,
> + EnumSpiFlashM25PX16,
> + EnumSpiFlashN25Q032,
> + EnumSpiFlashM25PX32,
> + EnumSpiFlashM25PX64,
> + EnumSpiFlashN25Q128,
> + EnumSpiFlashEN25Q16,
> + EnumSpiFlashEN25Q32,
> + EnumSpiFlashEN25Q64,
> + EnumSpiFlashEN25Q128,
> + EnumSpiFlashA25L016,
> + EnumSpiFlashMax
> +} SPI_FLASH_TYPES_SUPPORTED;
> +
> +//
> +// Serial Flash VendorId and DeviceId
> +//
> +#define SF_VENDOR_ID_ATMEL 0x1F
> +#define SF_DEVICE_ID0_AT26DF321 0x47
> +#define SF_DEVICE_ID1_AT26DF321 0x00
> +#define SF_DEVICE_ID0_AT25DF321A 0x47
> +#define SF_DEVICE_ID1_AT25DF321A 0x01
> +#define SF_DEVICE_ID0_AT25DF641 0x48
> +#define SF_DEVICE_ID1_AT25DF641 0x00
> +
> +#define SF_VENDOR_ID_WINBOND 0xEF
> +#define SF_DEVICE_ID0_W25XXX 0x30
> +#define SF_DEVICE_ID1_W25X32 0x16
> +#define SF_DEVICE_ID1_W25X64 0x17
> +#define SF_DEVICE_ID0_W25QXX 0x40
> +#define SF_DEVICE_ID1_W25Q16 0x15
> +#define SF_DEVICE_ID1_W25Q32 0x16
> +#define SF_DEVICE_ID1_W25Q64 0x17
> +#define SF_DEVICE_ID1_W25Q128 0x18
> +
> +#define SF_VENDOR_ID_MACRONIX 0xC2
> +#define SF_DEVICE_ID0_MX25LXX 0x20
> +#define SF_DEVICE_ID1_MX25L16 0x15
> +#define SF_DEVICE_ID1_MX25L32 0x16
> +#define SF_DEVICE_ID1_MX25L64 0x17
> +#define SF_DEVICE_ID1_MX25L128 0x18
> +#define SF_DEVICE_ID0_MX25UXX 0x25
> +#define SF_DEVICE_ID1_MX25U6435F 0x37
> +
> +#define SF_VENDOR_ID_NUMONYX 0x20
> +#define SF_DEVICE_ID0_N25Q064 0xBB
> +#define SF_DEVICE_ID1_N25Q064 0x17
> +#define SF_DEVICE_ID0_M25PXXX 0x71
> +#define SF_DEVICE_ID0_N25QXXX 0xBA
> +#define SF_DEVICE_ID1_M25PX16 0x15
> +#define SF_DEVICE_ID1_N25Q032 0x16
> +#define SF_DEVICE_ID1_M25PX32 0x16
> +#define SF_DEVICE_ID1_M25PX64 0x17
> +#define SF_DEVICE_ID1_N25Q128 0x18
> +
> +#define SF_VENDOR_ID_SST 0xBF
> +#define SF_DEVICE_ID0_SST25VF0XXX 0x25
> +#define SF_DEVICE_ID1_SST25VF016B 0x41
> +#define SF_DEVICE_ID1_SST25VF064C 0x4B
> +
> +#define SF_VENDOR_ID_EON 0x1C
> +#define SF_DEVICE_ID0_EN25QXX 0x30
> +#define SF_DEVICE_ID1_EN25Q16 0x15
> +#define SF_DEVICE_ID1_EN25Q32 0x16
> +#define SF_DEVICE_ID1_EN25Q64 0x17
> +#define SF_DEVICE_ID1_EN25Q128 0x18
> +
> +#define SF_VENDOR_ID_AMIC 0x37
> +#define SF_DEVICE_ID0_A25L016 0x30
> +#define SF_DEVICE_ID1_A25L016 0x15
> +
> +#define ATMEL_AT26DF321_SIZE 0x00400000
> +#define ATMEL_AT25DF321A_SIZE 0x00400000
> +#define ATMEL_AT25DF641_SIZE 0x00800000
> +#define WINBOND_W25X32_SIZE 0x00400000
> +#define WINBOND_W25X64_SIZE 0x00800000
> +#define WINBOND_W25Q16_SIZE 0x00200000
> +#define WINBOND_W25Q32_SIZE 0x00400000
> +#define WINBOND_W25Q64_SIZE 0x00800000
> +#define WINBOND_W25Q128_SIZE 0x01000000
> +#define SST_SST25VF016B_SIZE 0x00200000
> +#define SST_SST25VF064C_SIZE 0x00800000
> +#define MACRONIX_MX25L16_SIZE 0x00200000
> +#define MACRONIX_MX25L32_SIZE 0x00400000
> +#define MACRONIX_MX25L64_SIZE 0x00800000
> +#define MACRONIX_MX25U64_SIZE 0x00800000
> +#define MACRONIX_MX25L128_SIZE 0x01000000
> +#define NUMONYX_M25PX16_SIZE 0x00400000
> +#define NUMONYX_N25Q032_SIZE 0x00400000
> +#define NUMONYX_M25PX32_SIZE 0x00400000
> +#define NUMONYX_M25PX64_SIZE 0x00800000
> +#define NUMONYX_N25Q064_SIZE 0x00800000
> +#define NUMONYX_N25Q128_SIZE 0x01000000
> +#define EON_EN25Q16_SIZE 0x00200000
> +#define EON_EN25Q32_SIZE 0x00400000
> +#define EON_EN25Q64_SIZE 0x00800000
> +#define EON_EN25Q128_SIZE 0x01000000
> +#define AMIC_A25L16_SIZE 0x00200000
> +
> +#define SF_VENDOR_ID_SST 0xBF
> +#define SF_DEVICE_ID0_25LF080A 0x25
> +#define SF_DEVICE_ID1_25LF080A 0x8E
> +#define SF_DEVICE_ID0_25VF016B 0x25
> +#define SF_DEVICE_ID1_25VF016B 0x41
> +
> +#define SF_VENDOR_ID_ATMEL 0x1F
> +#define SF_DEVICE_ID0_AT26DF321 0x47
> +#define SF_DEVICE_ID1_AT26DF321 0x00
> +
> +#define SF_VENDOR_ID_STM 0x20
> +#define SF_DEVICE_ID0_M25P32 0x20
> +#define SF_DEVICE_ID1_M25P32 0x16
> +
> +#define SF_VENDOR_ID_WINBOND 0xEF
> +#define SF_DEVICE_ID0_W25XXX 0x30
> +
> +#define SF_DEVICE_ID1_W25X80 0x14
> +#define SF_DEVICE_ID1_W25X16 0x15
> +#define SF_DEVICE_ID1_W25X32 0x16
> +#define SF_DEVICE_ID1_W25X64 0x17
> +
> +#define SF_VENDOR_ID_MX 0xC2
> +#define SF_DEVICE_ID0_25L1605A 0x20
> +#define SF_DEVICE_ID1_25L1605A 0x15
> +
> +#define SF_VENDOR_ID_NUMONYX 0x20
> +#define SF_DEVICE_ID0_M25PX16 0x71
> +#define SF_DEVICE_ID1_M25PX16 0x15
> +
> +#define SST_25LF080A_SIZE 0x00100000
> +#define SST_25LF016B_SIZE 0x00200000
> +#define ATMEL_AT26DF321_SIZE 0x00400000
> +#define STM_M25P32_SIZE 0x00400000
> +#define WINBOND_W25X80_SIZE 0x00100000
> +#define WINBOND_W25X16_SIZE 0x00200000
> +#define WINBOND_W25X32_SIZE 0x00400000
> +#define WINBOND_W25X64_SIZE 0x00800000
> +#define MX_25L1605A_SIZE 0x00200000
> +
> +//
> +// Physical Sector Size on the Serial Flash device
> +//
> +#define SF_SECTOR_SIZE 0x1000
> +#define SF_BLOCK_SIZE 0x8000
> +
> +//
> +// Serial Flash Status Register definitions
> +//
> +#define SF_SR_BUSY 0x01 // Indicates if internal write operation is in
> progress
> +#define SF_SR_WEL 0x02 // Indicates if device is memory write
> enabled
> +#define SF_SR_BP0 0x04 // Block protection bit 0
> +#define SF_SR_BP1 0x08 // Block protection bit 1
> +#define SF_SR_BP2 0x10 // Block protection bit 2
> +#define SF_SR_BP3 0x20 // Block protection bit 3
> +#define SF_SR_WPE 0x3C // Enable write protection on all blocks
> +#define SF_SR_AAI 0x40 // Auto Address Increment Programming
> status
> +#define SF_SR_BPL 0x80 // Block protection lock-down
> +
> +//
> +// Operation Instruction definitions for the Serial Flash Device
> +//
> +#define SF_INST_WRSR 0x01 // Write Status Register
> +#define SF_INST_PROG 0x02 // Byte Program
> +#define SF_INST_READ 0x03 // Read
> +#define SF_INST_WRDI 0x04 // Write Disable
> +#define SF_INST_RDSR 0x05 // Read Status Register
> +#define SF_INST_WREN 0x06 // Write Enable
> +#define SF_INST_HS_READ 0x0B // High-speed Read
> +#define SF_INST_SERASE 0x20 // Sector Erase (4KB)
> +#define SF_INST_BERASE 0x52 // Block Erase (32KB)
> +#define SF_INST_64KB_ERASE 0xD8 // Block Erase (64KB)
> +#define SF_INST_EWSR 0x50 // Enable Write Status Register
> +#define SF_INST_READ_ID 0xAB // Read ID
> +#define SF_INST_JEDEC_READ_ID 0x9F // JEDEC Read ID
> +#define SF_INST_DOFR 0x3B // Dual Output Fast Read
> +#define SF_INST_SFDP 0x5A // Serial Flash Discovery Parameters
> +
> +#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
> +#define SECTOR_SIZE_64KB 0x10000 // Common 64kBytes sector size
> +#define BLOCK_SIZE_64KB 0x00010000 // Common 64kBytes block size
> +#define MAX_FWH_SIZE 0x00100000 // 8Mbit (Note that this can also
> be used for the 4Mbit )
> +
> +//
> +// Prefix Opcode Index on the host SPI controller
> +//
> +typedef enum {
> + SPI_WREN, // Prefix Opcode 0: Write Enable
> + SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register
> +} PREFIX_OPCODE_INDEX;
> +
> +//
> +// Opcode Menu Index on the host SPI controller
> +//
> +typedef enum {
> + SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address
> + SPI_READ, // Opcode 1: READ, Read cycle with address
> + SPI_RDSR, // Opcode 2: Read Status Register, No address
> + SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters,
> No address
> + SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address
> + SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address
> + SPI_PROG, // Opcode 6: Byte Program, Write cycle with address
> + SPI_WRSR, // Opcode 7: Write Status Register, No address
> +} SPI_OPCODE_INDEX;
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h
> new file mode 100644
> index 0000000000..49baffdcc5
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h
> @@ -0,0 +1,40 @@
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + SmmStallLib.h
> +
> +Abstract:
> +
> + This library provides SMM functions for Stall.
> + These can be used to save size and simplify code.
> + All contents must be runtime and SMM safe.
> +
> +--*/
> +
> +#ifndef _SMM_STALL_LIB_H_
> +#define _SMM_STALL_LIB_H_
> +#include "PiDxe.h"
> +#include "Pi/PiSmmCis.h"
> +extern EFI_SMM_SYSTEM_TABLE2 *mSmst;
> +
> +/**
> + Delay for at least the request number of microseconds
> +
> + @param[in] Microseconds Number of microseconds to delay.
> +
> + @retval None
> +
> +**/
> +VOID
> +SmmStall (
> + IN UINTN Microseconds
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h
> new file mode 100644
> index 0000000000..c52417f00f
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h
> @@ -0,0 +1,181 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef __BASE_USBDEVICEMODE_LIB_H__
> +#define __BASE_USBDEVICEMODE_LIB_H__
> +
> +#pragma pack(1)
> +typedef struct {
> + UINT8 bLength;
> + UINT8 bDescriptorType;
> + UINT8 bMaxBurst;
> + UINT8 bmAttributes;
> + UINT16 wBytesPerInterval;
> +} endpointCompanionDescriptor;
> +#pragma pack()
> +
> +#pragma pack(1)
> +typedef struct {
> + UINT8 bLength;
> + UINT8 bDescriptorType;
> + UINT8 bEndpointAddress;
> + UINT8 bmAttributes;
> + UINT16 wMaxPacketSize;
> + UINT8 bInterval;
> +} endpointDescriptor;
> +#pragma pack()
> +
> +typedef struct {
> + endpointDescriptor *pEpDesc;
> + endpointCompanionDescriptor *pEpCompDesc;
> +} USB_DEV_EP_INFO; //usbdEpInfo;
> +
> +typedef struct {
> + VOID *pBuf;
> + UINT32 dataLen;
> +} USBD_IO_INFO;
> +
> +typedef struct {
> + USBD_IO_INFO ioInfo;
> + USB_DEV_EP_INFO epInfo;
> +} USBD_IO_REQ;
> +
> +UINTN
> +EFIAPI
> +usbdInitDCI (
> + VOID
> + );
> +
> +BOOLEAN
> +EFIAPI
> +fbInit (
> + OUT VOID *pParams
> + );
> +
> +BOOLEAN
> +EFIAPI
> +fbDeinit (
> + VOID
> + );
> +
> +BOOLEAN
> +EFIAPI
> +fbStart (
> + VOID
> + );
> +
> +BOOLEAN
> +EFIAPI
> +fbStop (
> + VOID
> + );
> +
> +BOOLEAN
> +EFIAPI
> +usbdSetMmioBar (
> + UINT32 mmioBar
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciDeinit (
> + VOID *pUdciHndl,
> + UINT32 flags
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciIsr (
> + VOID *pUdciHndl
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciConnect (
> + VOID *pUdciHndl
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciDisconnect (
> + VOID *pUdciHndl
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciSetAddress (
> + VOID *pUdciHndl,
> + UINT8 address
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciInitEp (
> + VOID *pUdciHndl,
> + USB_DEV_EP_INFO *pEpInfo
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciEnableEp (
> + VOID *pUdciHndl,
> + USB_DEV_EP_INFO *pEpInfo
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciDisableEp (
> + VOID *pUdciHndl,
> + USB_DEV_EP_INFO *pEpInfo
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciStallEp (
> + VOID *pUdciHndl,
> + USB_DEV_EP_INFO *pEpInfo
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciClearStallEp (
> + VOID *pUdciHndl,
> + USB_DEV_EP_INFO *pEpInfo
> + );
> +
> +
> +BOOLEAN
> +EFIAPI
> +udciEp0TxStatus (
> + VOID *pUdciHndl
> + );
> +
> +
> +BOOLEAN
> +EFIAPI
> +udciEpTxData (
> + VOID *pUdciHndl,
> + USBD_IO_REQ *pIoReq
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciEpRxData (
> + VOID *pUdciHndl,
> + USBD_IO_REQ *pIoReq
> + );
> +
> +BOOLEAN
> +EFIAPI
> +udciRegisterCallbacks (
> + VOID *pUdciHndl
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Mcfg.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Mcfg.h
> new file mode 100644
> index 0000000000..2751a27d2d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Mcfg.h
> @@ -0,0 +1,69 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + Mcfg.h
> +
> +Abstract:
> +
> + ACPI Memory mapped configuration space base address Description Table
> + implementation, based on PCI Firmware Specification Revision 3.0 final
> draft,
> + downloadable at http://www.pcisig.com/home
> +
> +**/
> +
> +#ifndef _MCFG_H_
> +#define _MCFG_H_
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/Acpi20.h>
> +#include "McfgTable.h"
> +#include "Platform.h"
> +
> +//
> +// "MCFG" Static Resource Affinity Table
> +//
> +#define
> EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABL
> E_SIGNATURE 0x4746434D
> +
> +//
> +// MCFG Definitions, see specification for details.
> +//
> +#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001
> +
> +//
> +// Define the number of each table type.
> +// This is where the table layout is modified.
> +//
> +#define
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRE
> SS_STRUCTURE_COUNT 1
> +
> +//
> +// MCFG Table definition. The table must be defined in a platform
> +// specific manner.
> +//
> +//
> +// Ensure proper structure formats
> +//
> +#pragma pack(1)
> +
> +typedef struct {
> +
> EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HE
> ADER Header;
> +
> +#if
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRE
> SS_STRUCTURE_COUNT > 0
> +
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRE
> SS_STRUCTURE Segment[
> +
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRE
> SS_STRUCTURE_COUNT];
> +#endif
> +
> +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE;
> +
> +#pragma pack()
> +
> +#endif // _MCFG_H_
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/McfgTable.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/McfgTable.h
> new file mode 100644
> index 0000000000..dc9dc49e74
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/McfgTable.h
> @@ -0,0 +1,65 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + McfgTable.h
> +
> +Abstract:
> +
> + ACPI Memory mapped configuration space base address Description Table
> + definition, based on PCI Firmware Specification Revision 3.0 final draft,
> + downloadable at http://www.pcisig.com/home
> +
> +**/
> +
> +#ifndef _MCFG_TABLE_H_
> +#define _MCFG_TABLE_H_
> +
> +//
> +// Include files
> +//
> +#include <PiDxe.h>
> +
> +//
> +// Ensure proper structure formats
> +//
> +#pragma pack(1)
> +
> +//
> +// MCFG Revision (defined in spec)
> +//
> +#define
> EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_RE
> VISION 0x01
> +
> +//
> +// MCFG Structure Definitions
> +//
> +//
> +// Memory Mapped Enhanced Configuration Base Address Allocation
> +// Structure Definition
> +//
> +typedef struct {
> + UINT64 BaseAddress;
> + UINT16 PciSegmentGroupNumber;
> + UINT8 StartBusNumber;
> + UINT8 EndBusNumber;
> + UINT32 Reserved;
> +}
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRE
> SS_STRUCTURE;
> +
> +//
> +// MCFG Table header definition. The rest of the table
> +// must be defined in a platform specific manner.
> +//
> +typedef struct {
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + UINT64 Reserved;
> +}
> EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HE
> ADER;
> +
> +#pragma pack()
> +
> +#endif // _MCFG_TABLE_H
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Platform.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Platform.h
> new file mode 100644
> index 0000000000..4d1932febd
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Platform.h
> @@ -0,0 +1,133 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + Platform.h
> +
> +Abstract:
> +
> + Pinetrail platform specific information.
> +
> +**/
> +
> +#ifndef _PLATFORM_H
> +#define _PLATFORM_H
> +
> +#include "ChipsetAccess.h"
> +#include "PlatformBaseAddresses.h"
> +
> +
> +//
> +// Number of P & T states supported.
> +//
> +#define NPTM_P_STATES_SUPPORTED 16
> +#define NPTM_T_STATES_SUPPORTED 8
> +
> +//
> +// I/O APIC IDs, the code uses math to generate the numbers
> +// instead of using these defines.
> +//
> +#define ICH_IOAPIC (1 << 0)
> +#define ICH_IOAPIC_ID 0x08
> +
> +//
> +// Possible SMBus addresses that will be present.
> +//
> +#define SMBUS_ADDR_CH_A_1 0xA0
> +#define SMBUS_ADDR_CH_A_2 0xA2
> +#define SMBUS_ADDR_CH_B_1 0xA4
> +#define SMBUS_ADDR_CH_B_2 0xA6
> +#define SMBUS_ADDR_CH_C_1 0xA8
> +#define SMBUS_ADDR_CH_C_2 0xAA
> +#define SMBUS_ADDR_CH_D_1 0xAC
> +#define SMBUS_ADDR_CH_D_2 0xAE
> +#define SMBUS_ADDR_HOST_CLK_BUFFER 0xDC
> +#define SMBUS_ADDR_ICH_SLAVE 0x44
> +#define SMBUS_ADDR_HECETA 0x5C
> +#define SMBUS_ADDR_SMBARP 0xC2
> +#define SMBUS_ADDR_82573E 0xC6
> +#define SMBUS_ADDR_CLKCHIP 0xD2
> +#define SMBUS_ADDR_BRD_REV 0x4E
> +#define SMBUS_ADDR_DB803 0x82
> +
> +//
> +// SMBus addresses that used on this platform.
> +//
> +#define PLATFORM_SMBUS_RSVD_ADDRESSES { \
> + SMBUS_ADDR_CH_A_1, \
> + SMBUS_ADDR_CH_A_2, \
> + SMBUS_ADDR_HOST_CLK_BUFFER, \
> + SMBUS_ADDR_ICH_SLAVE, \
> + SMBUS_ADDR_SMBARP, \
> + SMBUS_ADDR_CLKCHIP, \
> + SMBUS_ADDR_BRD_REV, \
> + SMBUS_ADDR_DB803 \
> + }
> +
> +//
> +// Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES.
> +//
> +#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8
> +
> +//
> +// CMOS usage
> +//
> +#define CMOS_CPU_BSP_SELECT 0x10
> +#define CMOS_CPU_UP_MODE 0x11
> +#define CMOS_CPU_RATIO_OFFSET 0x12
> +#define CMOS_CPU_CORE_HT_OFFSET 0x13
> +#define CMOS_EFI_DEBUG 0x14
> +#define CMOS_CPU_BIST_OFFSET 0x15
> +#define CMOS_CPU_VMX_OFFSET 0x16
> +#define CMOS_ICH_PORT80_OFFSET 0x17
> +#define CMOS_PLATFORM_DESIGNATOR 0x18 // Second bank CMOS
> location of Platform ID.
> +#define CMOS_VALIDATION_TEST_BYTE 0x19 // BIT0 - Validation
> mailbox for UPonDP.
> +#define CMOS_SERIAL_BAUD_RATE 0x1A // 0=115200; 1=57600;
> 2=38400; 3=19200; 4=9600
> +#define CMOS_DCU_MODE_OFFSET 0x1B
> +#define CMOS_VR11_SET_OFFSET 0x1C
> +#define CMOS_SBSP_TO_AP_COMM 0x20 // SEC code use ONLY!!!
> +#define CMOS_RESET_TYPE_BY_OS 0x52
> +#define TCG_CMOS_MOR_AREA_OFFSET 0x65 // Also Change in
> Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &
> +#define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E
> +#define ACPI_TPM_REQUEST 0x75
> +#define ACPI_TPM_LAST_REQUEST 0x76
> +#define CMOS_BOOT_FLAG_ADDRESS 0x7E
> +
> +//
> +// GPIO Index Data Structure.
> +//
> +typedef struct {
> + UINT8 Register;
> + UINT32 Value;
> +} ICH_GPIO_DEV;
> +
> +//
> +// CPU Equates
> +//
> +#define MAX_THREAD 2
> +#define MAX_CORE 1
> +#define MAX_DIE 2
> +#define MAX_CPU_SOCKET 1
> +#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE *
> MAX_DIE * MAX_CPU_SOCKET)
> +
> +#define MEM64_LEN 0x00100000000
> +#define RES_MEM64_36_BASE 0x01000000000 - MEM64_LEN //
> 2^36
> +#define RES_MEM64_36_LIMIT 0x01000000000 - 1 // 2^36
> +#define RES_MEM64_39_BASE 0x08000000000 - MEM64_LEN //
> 2^39
> +#define RES_MEM64_39_LIMIT 0x08000000000 - 1 // 2^39
> +#define RES_MEM64_40_BASE 0x10000000000 - MEM64_LEN //
> 2^40
> +#define RES_MEM64_40_LIMIT 0x10000000000 - 1 // 2^40
> +
> +#define PLATFORM_MAX_BUS_NUM 0x3f
> +#define V_DEFAULT_SUBSYSTEM_DEVICE_ID 0x574d
> +#define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b
> +#define V_DEFAULT_SUBSYSTEM_VENDOR_ID 0x8086
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/PlatformBootMode.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/PlatformBootMode.h
> new file mode 100644
> index 0000000000..812077ce14
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/PlatformBootMode.h
> @@ -0,0 +1,35 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + PlatformBootMode.h
> +
> +Abstract:
> +
> + EFI Platform Boot Mode
> +
> +Revision History
> +
> +--*/
> +
> +#ifndef _EFI_PLATFORM_BOOT_MODE_H_
> +#define _EFI_PLATFORM_BOOT_MODE_H_
> +
> +//
> +// Global ID for the Platform Boot Mode Protocol.
> +//
> +#define MANUFACTURE_SETUP_NAME L"MfgDefault"
> +#define SAFE_SETUP_NAME L"SetupDefault"
> +#define OEM_DEFAULTS_SETUP_NAME L"OemDefault"
> +#define CUSTOM_DEFAULTS_SETUP_NAME L"CustomDefault"
> +
> +#endif
> +
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/PlatformDefinitions.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/PlatformDefinitions.h
> new file mode 100644
> index 0000000000..a64cda0799
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/PlatformDefinitions.h
> @@ -0,0 +1,43 @@
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + PlatformDefinitions.h
> +
> +Abstract:
> +
> + This header file provides platform specific definitions used by other
> modules
> + for platform specific initialization.
> +
> + THIS FILE SHOULD ONLY CONTAIN #defines BECAUSE IT IS CONSUMED BY
> NON-C MODULES
> + (ASL and VFR)
> +
> + This file should not contain addition or other operations that an ASL
> compiler or
> + VFR compiler does not understand.
> +
> +--*/
> +
> +#ifndef _PLATFORM_DEFINITIONS_H_
> +#define _PLATFORM_DEFINITIONS_H_
> +
> +
> +//
> +// Platform Base Address definitions
> +//
> +#define PCIEX_BASE_ADDRESS EDKII_GLUE_PciExpressBaseAddress //
> Pci Express Configuration Space Base Address
> +
> +#define PCIEX_LENGTH PLATFORM_PCIEXPRESS_LENGTH
> +
> +#define THERMAL_BASE_ADDRESS 0xFED08000
> +
> +#ifndef MCH_BASE_ADDRESS
> +#define MCH_BASE_ADDRESS 0xFED10000 // MCH Register Base
> Address
> +#endif
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h
> new file mode 100644
> index 0000000000..353c80b629
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h
> @@ -0,0 +1,42 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + BaseMemoryTest.h
> +
> +Abstract:
> +
> + Pei memory test PPI as defined in Tiano
> +
> + Used to Pei memory test in PEI
> +
> +--*/
> +
> +#ifndef _BASE_MEMORY_TEST_H_
> +#define _BASE_MEMORY_TEST_H_
> +
> +typedef struct _PEI_MFG_MEMORY_TEST_PPI
> PEI_MFG_MEMORY_TEST_PPI;
> +
> +typedef
> +EFI_STATUS
> +(EFIAPI *PEI_MFG_MEMORY_TEST) (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN PEI_MFG_MEMORY_TEST_PPI * This,
> + IN UINT32 BeginAddress,
> + IN UINT32 MemoryLength
> + );
> +
> +typedef struct _PEI_MFG_MEMORY_TEST_PPI {
> + PEI_MFG_MEMORY_TEST MfgMemoryTest;
> +}PEI_MFG_MEMORY_TEST_PPI;
> +
> +
> +extern EFI_GUID gPeiMfgMemoryTestPpiGuid;
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h
> new file mode 100644
> index 0000000000..1c9b2b9ea1
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h
> @@ -0,0 +1,131 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + Speaker.h
> +
> +Abstract:
> +
> + EFI Speaker Interface Protocol
> +
> +
> +
> +--*/
> +
> +#ifndef _PEI_SHA256_HASH_H
> +#define _PEI_SHA256_HASH_H
> +
> +//
> +// Global ID Speaker Interface
> +//
> +#define PEI_SHA256_HASH_PPI_GUID \
> + { \
> + 0x950e191b, 0x8524, 0x4f51, 0x80, 0xa1, 0x5c, 0x4f, 0x1b, 0x3, 0xf3, 0x5c
> \
> + }
> +
> +typedef struct _PEI_SHA256_HASH_PPI PEI_SHA256_HASH_PPI;
> +
> +/**
> + @return The size, in bytes, of the context buffer required for hash
> operations.
> +
> +**/
> +typedef
> +UINTN
> +(EFIAPI *HASH_GET_CONTEXT_SIZE)(
> + VOID
> + );
> +
> +/**
> + Initializes user-supplied memory pointed by HashContext as hash context
> for
> + subsequent use.
> +
> + If HashContext is NULL, then ASSERT().
> +
> + @param[in, out] HashContext Pointer to Context being initialized.
> +
> + @retval TRUE HASH context initialization succeeded.
> + @retval FALSE HASH context initialization failed.
> +
> +**/
> +typedef
> +BOOLEAN
> +(EFIAPI *HASH_INIT)(
> + IN OUT VOID *HashContext
> + );
> +
> +/**
> + Performs digest on a data buffer of the specified length. This function can
> + be called multiple times to compute the digest of long or discontinuous
> data streams.
> +
> + If HashContext is NULL, then ASSERT().
> +
> + @param[in, out] HashContext Pointer to the MD5 context.
> + @param[in] Data Pointer to the buffer containing the data to be
> hashed.
> + @param[in] DataLength Length of Data buffer in bytes.
> +
> + @retval TRUE HASH data digest succeeded.
> + @retval FALSE Invalid HASH context. After HashFinal function has been
> called, the
> + HASH context cannot be reused.
> +
> +**/
> +typedef
> +BOOLEAN
> +(EFIAPI *HASH_UPDATE)(
> + IN OUT VOID *HashContext,
> + IN CONST VOID *Data,
> + IN UINTN DataLength
> + );
> +
> +/**
> + Completes hash computation and retrieves the digest value into the
> specified
> + memory. After this function has been called, the context cannot be used
> again.
> +
> + If HashContext is NULL, then ASSERT().
> + If HashValue is NULL, then ASSERT().
> +
> + @param[in, out] HashContext Pointer to the MD5 context
> + @param[out] HashValue Pointer to a buffer that receives the HASH
> digest
> + value.
> +
> + @retval TRUE HASH digest computation succeeded.
> + @retval FALSE HASH digest computation failed.
> +
> +**/
> +typedef
> +BOOLEAN
> +(EFIAPI *HASH_FINAL)(
> + IN OUT VOID *HashContext,
> + OUT UINT8 *HashValue
> + );
> +
> +//
> +// Ppi definition
> +//
> +typedef struct _PEI_SHA256_HASH_PPI {
> + //
> + // Pointer to Hash GetContentSize function
> + //
> + HASH_GET_CONTEXT_SIZE GetContextSize;
> + //
> + // Pointer to Hash Init function
> + //
> + HASH_INIT HashInit;
> + //
> + // Pointer to Hash Update function
> + //
> + HASH_UPDATE HashUpdate;
> + //
> + // Pointer to Hash Final function
> + //
> + HASH_FINAL HashFinal;
> +
> +} PEI_SHA256_HASH_PPI;
> +
> +extern EFI_GUID gPeiSha256HashPpiGuid;
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/Speaker.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/Speaker.h
> new file mode 100644
> index 0000000000..b8c817e4ca
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/Speaker.h
> @@ -0,0 +1,65 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + Speaker.h
> +
> +Abstract:
> +
> + EFI Speaker Interface Protocol
> +
> +
> +
> +--*/
> +
> +#ifndef _PEI_SPEAKER_IF_H
> +#define _PEI_SPEAKER_IF_H
> +
> +//
> +// Global ID Speaker Interface
> +//
> +#define PEI_SPEAKER_INTERFACE_PPI_GUID \
> + { \
> + 0x30ac275e, 0xbb30, 0x4b84, 0xa1, 0xcd, 0x0a, 0xf1, 0x32, 0x2c, 0x89, 0xc0
> \
> + }
> +
> +typedef struct _PEI_SPEAKER_IF_PPI PEI_SPEAKER_IF_PPI;
> +
> +//
> +// Beep Code
> +//
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_SPEAKER_GENERATE_BEEP) (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINTN NumberOfBeep,
> + IN UINTN BeepDuration,
> + IN UINTN TimeInterval
> + );
> +
> +//
> +// Set Frequency
> +//
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_SPEAKER_SET_FREQUENCY) (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINT16 Frequency
> + );
> +
> +//
> +// Protocol definition
> +//
> +typedef struct _PEI_SPEAKER_IF_PPI {
> + EFI_SPEAKER_SET_FREQUENCY SetSpeakerToneFrequency;
> + EFI_SPEAKER_GENERATE_BEEP GenerateBeep;
> +} PEI_SPEAKER_IF_PPI;
> +
> +extern EFI_GUID gPeiSpeakerInterfacePpiGuid;
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/UsbController.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/UsbController.h
> new file mode 100644
> index 0000000000..5448566116
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Ppi/UsbController.h
> @@ -0,0 +1,85 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> + Define APIs to retrieve USB Host Controller Info such as controller type and
> + I/O Port Base Address.
> +
> +
> +**/
> +
> +#ifndef _PEI_USB_CONTROLLER_PPI_H_
> +#define _PEI_USB_CONTROLLER_PPI_H_
> +
> +//
> +// Global ID for the PEI_USB_CONTROLLER_PPI.
> +//
> +#define PEI_USB_CONTROLLER_PPI_GUID \
> + { \
> + 0x3bc1f6de, 0x693e, 0x4547,{ 0xa3, 0x0, 0x21, 0x82, 0x3c, 0xa4, 0x20, 0xb2}
> \
> + }
> +
> +//
> +// Forward declaration for the PEI_USB_CONTROLLER_PPI.
> +//
> +typedef struct _PEI_USB_CONTROLLER_PPI PEI_USB_CONTROLLER_PPI;
> +
> +//
> +// This bit is used in the ControllerType return parameter of
> GetUsbController()
> +// to identify the USB Host Controller type as UHCI
> +//
> +#define PEI_UHCI_CONTROLLER 0x01
> +
> +//
> +// This bit is used in the ControllerType return parameter of
> GetUsbController()
> +// to identify the USB Host Controller type as OHCI
> +//
> +#define PEI_OHCI_CONTROLLER 0x02
> +
> +//
> +// This bit is used in the ControllerType return parameter of
> GetUsbController()
> +// to identify the USB Host Controller type as EHCI
> +//
> +#define PEI_EHCI_CONTROLLER 0x03
> +
> +/**
> + Retrieve USB Host Controller Info such as controller type and I/O Base
> Address.
> +
> + @param[in] PeiServices The pointer to the PEI Services Table.
> + @param[in] This The pointer to this instance of the
> PEI_USB_CONTROLLER_PPI.
> + @param[in] ControllerId The ID of the USB controller.
> + @param[out] ControllerType On output, returns the type of the USB
> controller.
> + @param[out] BaseAddress On output, returns the base address of
> UHCI's I/O ports
> + if UHCI is enabled or the base address of EHCI's MMIO
> + if EHCI is enabled.
> +
> + @retval EFI_SUCCESS USB controller attributes were returned
> successfully.
> + @retval EFI_INVALID_PARAMETER ControllerId is greater than the
> maximum number
> + of USB controller supported by this platform.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *PEI_GET_USB_CONTROLLER)(
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN PEI_USB_CONTROLLER_PPI *This,
> + IN UINT8 UsbControllerId,
> + OUT UINTN *ControllerType,
> + OUT UINTN *BaseAddress
> + );
> +
> +//
> +// This PPI contains a single service to retrieve the USB Host Controller type
> +// and the base address of the I/O ports used to access the USB Host
> Controller.
> +//
> +struct _PEI_USB_CONTROLLER_PPI {
> + PEI_GET_USB_CONTROLLER GetUsbController;
> +};
> +
> +extern EFI_GUID gPeiUsbControllerPpiGuid;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformIn
> fo.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformIn
> fo.h
> new file mode 100644
> index 0000000000..daf5d22d71
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformIn
> fo.h
> @@ -0,0 +1,126 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + CK505ClockPlatformInfo.h
> +
> +Abstract:
> +
> + Protocol to communicate product clock routing information.
> +
> +GUID Info:
> + {3C485EA4-449A-46ce-BB08-2A336EA96B4E}
> + 0x3c485ea4, 0x449a, 0x46ce, 0xbb, 0x8, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e);
> +
> +**/
> +
> +#ifndef _CLOCK_PLATFORM_INFO_H_
> +#define _CLOCK_PLATFORM_INFO_H_
> +
> +
> +#define EFI_CK505_CLOCK_PLATFORM_INFO_GUID \
> + {0x3c485ea4, 0x449a, 0x46ce, 0xbb, 0x8, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e}
> +
> +//
> +// Structure to hold register modifications
> +//
> +typedef enum {
> + None = 0x00000000,
> + nICS9LP505_1 = 0x00000001,
> + nICS9LP505_2 = 0x00000002,
> + nIDTCV163 = 0x00000004,
> + nIDTCV174 = 0x00000008,
> + nSLG505YC56 = 0x00000010,
> + nSLG505YC64 = 0x00000020,
> + nCY28505 = 0x00000040,
> + nCY28505_2 = 0x00000080,
> + nCY28505LF = 0x00000100,
> + nPI6C505_OLD = 0x00000200,
> + nPI6C505_RevD = 0x00000400,
> + nGENERIC_505 = 0x00000800,
> + nSLG505YC264 = 0x00001000,
> + nIDTCV183 = 0x00002000,
> + nSLG505YC256 = 0x00004000,
> + nIDTCV184 = 0x00008000,
> + nIDTCV190 = 0x00010000,
> + All = 0xFFFFFFFF
> +} EFI_CLOCKS_SUPPORTED;
> +
> +typedef enum {
> + Disabled,
> + Enabled,
> + EnabledWithoutSwitch,
> + EnabledWithSwitch
> +} EFI_SIGNAL_STATE;
> +
> +typedef enum {
> + SrcClk11,
> + SrcClk10,
> + SrcClk9,
> + SrcClk8,
> + SrcClk7,
> + SrcClk6,
> + SrcClk5,
> + SrcClk4,
> + SrcClk3,
> + SrcClk2,
> + SrcClk1,
> + SrcClk0,
> + CpuClk1,
> + CpuClk0,
> + Ref0,
> + Dot96,
> + Usb48,
> + PciClkF5,
> + PciClk4,
> + PciClk3,
> + PciClk2,
> + PciClk1,
> + PciClk0,
> + SaveClockConfiguration,
> + MePresent,
> + Cr_A,
> + Cr_B,
> + Cr_C,
> + Cr_D,
> + Cr_E,
> + Cr_F,
> + Cr_G,
> + Cr_H,
> + Clk_None // Dummy entry for dynamic detection
> +} EFI_CLOCK_SIGNAL_NAME;
> +
> +typedef struct {
> + EFI_CLOCK_SIGNAL_NAME Signal;
> + EFI_SIGNAL_STATE State;
> + EFI_CLOCKS_SUPPORTED Supported;
> +} EFI_STATIC_SIGNALS;
> +
> +typedef struct {
> + BOOLEAN BehindBridge;
> + UINT16 BridgeBus;
> + UINT16 BridgeDev;
> + UINT16 BridgeFunction;
> + UINT16 TargetDevice;
> + EFI_CLOCK_SIGNAL_NAME Signal;
> +} EFI_DYNAMIC_SIGNALS;
> +
> +
> +typedef struct {
> + EFI_STATIC_SIGNALS *StaticClockTable;
> + UINTN StaticClockTableCount;
> + EFI_STATIC_SIGNALS *SxClockTable;
> + UINTN SxClockTableCount;
> + EFI_STATIC_SIGNALS *DynamicDisabledClocksTable;
> + UINTN DynamicDisabledClocksTableCount;
> +} EFI_CLOCK_PLATFORM_INFO;
> +
> +extern EFI_GUID gEfiCk505ClockPlatformInfoGuid;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.
> h
> new file mode 100644
> index 0000000000..9b74180845
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.
> h
> @@ -0,0 +1,76 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +Module Name:
> +
> + EnhancedSpeedstep.h
> +
> +Abstract:
> +
> + Enhanced Speedstep protocol
> +
> + The Enhanced Speedstep Protocol support.
> +
> +**/
> +
> +#ifndef _ENHANCED_SPEEDSTEP_H_
> +#define _ENHANCED_SPEEDSTEP_H_
> +
> +#define ENHANCED_SPEEDSTEP_PROTOCOL_GUID \
> + { \
> + 0x91a1ddcf, 0x5374, 0x4939, 0x89, 0x51, 0xd7, 0x29, 0x3f, 0x1a, 0x78, 0x6f
> \
> + }
> +
> +typedef struct _ENHANCED_SPEEDSTEP_PROTOCOL
> ENHANCED_SPEEDSTEP_PROTOCOL;
> +
> +typedef struct {
> + UINT8 Version; // EIST State format
> + UINT8 Size; // Size of element
> + UINT32 RatioStep; // Step
> + UINT32 MinRatio; // Calculated min ratio
> + UINT32 MaxRatio; // Calculated max ratio
> + UINT32 MinCoreFreq; // Calculated min freq
> + UINT32 MaxCoreFreq; // Calculated max freq
> + UINT32 MinPower; // Calculated min power
> + UINT32 MaxPower; // Calculated max power
> + UINT32 NumStates; // Number of states
> +} EIST_INFORMATION;
> +
> +typedef struct {
> + UINT32 CoreFrequency;
> + UINT32 Power;
> + UINT32 TransitionLatency;
> + UINT32 BusMasterLatency;
> + UINT32 Control;
> + UINT32 Status;
> +} EFI_ACPI_CPU_PSS_STATE;
> +
> +typedef
> +EFI_STATUS
> +(EFIAPI *GET_EIST_TABLE) (
> + IN ENHANCED_SPEEDSTEP_PROTOCOL *This,
> + OUT EIST_INFORMATION **EistInformation,
> + OUT VOID **PssStates
> + );
> +
> +struct _ENHANCED_SPEEDSTEP_PROTOCOL {
> + UINT32 ProcApicId;
> + GET_EIST_TABLE GetEistTable;
> +};
> +
> +//
> +// There will be an instance of this protocol for every processor
> +// in the system. ProcNumber is used to manage all the different
> +// processors in the system and passed into the MP protocol
> +// to run code streams on application processors
> +//
> +extern EFI_GUID gEnhancedSpeedstepProtocolGuid;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h
> new file mode 100644
> index 0000000000..e2683b2e5b
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h
> @@ -0,0 +1,475 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +
> +
> +Module Name:
> +
> + GlobalNvsArea.h
> +
> +Abstract:
> +
> + Definition of the global NVS area protocol. This protocol
> + publishes the address and format of a global ACPI NVS buffer used as a
> communications
> + buffer between SMM code and ASL code.
> + The format is derived from the ACPI reference code, version 0.95.
> +
> + Note: Data structures defined in this protocol are not naturally aligned.
> +
> +**/
> +
> +
> +#ifndef _GLOBAL_NVS_AREA_H_
> +#define _GLOBAL_NVS_AREA_H_
> +
> +//
> +// Includes
> +//
> +#define GLOBAL_NVS_DEVICE_ENABLE 1
> +#define GLOBAL_NVS_DEVICE_DISABLE 0
> +
> +//
> +// Forward reference for pure ANSI compatibility
> +//
> +
> +//EFI_FORWARD_DECLARATION (EFI_GLOBAL_NVS_AREA_PROTOCOL);
> +
> +//
> +// Global NVS Area Protocol GUID
> +//
> +#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
> +{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
> +
> +//
> +// Revision id - Added TPM related fields
> +//
> +#define GLOBAL_NVS_AREA_RIVISION_1 1
> +
> +//
> +// Extern the GUID for protocol users.
> +//
> +extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
> +
> +//
> +// Global NVS Area definition
> +//
> +#pragma pack (1)
> +typedef struct {
> + //
> + // Miscellaneous Dynamic Values, the definitions below need to be
> matched
> + // GNVS definitions in Platform.ASL
> + //
> + UINT16 OperatingSystem; // 00
> + UINT8 SmiFunction; // 02 SMI function call via IO Trap
> + UINT8 SmiParameter0; // 03
> + UINT8 SmiParameter1; // 04
> + UINT8 SciFunction; // 05 SCI function call via _L00
> + UINT8 SciParameter0; // 06
> + UINT8 SciParameter1; // 07
> + UINT8 GlobalLock; // 08 Global lock function call
> + UINT8 LockParameter0; // 09
> + UINT8 LockParameter1; // 10
> + UINT32 Port80DebugValue; // 11
> + UINT8 LidState; // 15 Open = 1
> + UINT8 PowerState; // 16 AC = 1
> + UINT8 DebugState; // 17
> +
> +
> + //
> + // Thermal Policy Values
> + //
> + UINT8 EnableThermalOffset; // 18 ThermalOffset for KSC
> + UINT8 Reserved1; // 19
> + UINT8 Reserved2; // 20
> + UINT8 PassiveThermalTripPoint; // 21
> + UINT8 PassiveTc1Value; // 22
> + UINT8 PassiveTc2Value; // 23
> + UINT8 PassiveTspValue; // 24
> + UINT8 CriticalThermalTripPoint; // 25
> + UINT8 EnableDigitalThermalSensor; // 26
> + UINT8 BspDigitalThermalSensorTemperature; // 27 Temperature
> of BSP
> + UINT8 ApDigitalThermalSensorTemperature; // 28 Temperature of
> AP
> + UINT8 DigitalThermalSensorSmiFunction; // 29 SMI function call
> via DTS IO Trap
> +
> + //
> + // Battery Support Values
> + //
> + UINT8 NumberOfBatteries; // 30
> + UINT8 BatteryCapacity0; // 31 Battery 0 Stored Capacity
> + UINT8 BatteryCapacity1; // 32 Battery 1 Stored Capacity
> + UINT8 BatteryCapacity2; // 33 Battery 2 Stored Capacity
> + UINT8 BatteryStatus0; // 34 Battery 0 Stored Status
> + UINT8 BatteryStatus1; // 35 Battery 1 Stored Status
> + UINT8 BatteryStatus2; // 36 Battery 2 Stored Status
> +
> + // NOTE: Do NOT Change the Offset of Revision Field
> + UINT8 Revision; // 37 Revision of the structure
> EFI_GLOBAL_NVS_AREA
> + UINT8 Reserved3[2]; // 38:39
> +
> + //
> + // Processor Configuration Values
> + //
> + UINT8 ApicEnable; // 40 APIC Enabled by SBIOS (APIC Enabled = 1)
> + UINT8 LogicalProcessorCount; // 41 Processor Count Enabled (MP
> Enabled != 0)
> + UINT8 CurentPdcState0; // 42 PDC settings, Processor 0
> + UINT8 CurentPdcState1; // 43 PDC settings, Processor 1
> + UINT8 MaximumPpcState; // 44 Maximum PPC state
> + UINT32 PpmFlags; // 45:48 PPM configuration flags, same as
> CFGD
> + UINT8 Reserved4[1]; // 49
> +
> + //
> + // SIO Configuration Values
> + //
> + UINT8 DockedSioPresent; // 50 Dock SIO Present
> + UINT8 DockComA; // 51 COM A Port
> + UINT8 DockComB; // 52 COM B Port
> + UINT8 LptP; // 53 LPT Port
> + UINT8 DockFdc; // 54 FDC Port
> + UINT8 OnboardCom; // 55 Onboard COM Port
> + UINT8 OnboardComCir; // 56 Onboard COM CIR Port
> +
> + UINT8 WPCN381U; // 57
> + UINT8 NPCE791x; // 58
> + UINT8 Reserved5[1]; // 59
> +
> + //
> + // Internal Graphics Device Values
> + //
> + UINT8 IgdState; // 60 IGD State (Primary Display = 1)
> + UINT8 DisplayToggleList; // 61 Display Toggle List Selection
> + UINT8 CurrentDeviceList; // 62 Current Attached Device List
> + UINT8 PreviousDeviceList; // 63 Previous Attached Device List
> + UINT16 CurrentDisplayState; // 64 Current Display State
> + UINT16 NextDisplayState; // 66 Next Display State
> + UINT16 SetDisplayState; // 68 Set Display State
> + UINT8 NumberOfValidDeviceId; // 70 Number of Valid Device IDs
> + UINT32 DeviceId1; // 71 Device ID 1
> + UINT32 DeviceId2; // 75 Device ID 2
> + UINT32 DeviceId3; // 79 Device ID 3
> + UINT32 DeviceId4; // 83 Device ID 4
> + UINT32 DeviceId5; // 87 Device ID 5
> +
> + UINT32 AKsv0; // 91:94 First four bytes of AKSV (manufacturing
> mode)
> + UINT8 AKsv1; // 95 Fifth byte of AKSV (manufacturing mode
> +
> + UINT8 Reserved6[7]; // 96:102
> +
> + //
> + // Backlight Control Values
> + //
> + UINT8 BacklightControlSupport; // 103 Backlight Control Support
> + UINT8 BrightnessPercentage; // 104 Brightness Level Percentage
> +
> + //
> + // Ambient Light Sensor Values
> + //
> + UINT8 AlsEnable; // 105 Ambient Light Sensor Enable
> + UINT8 AlsAdjustmentFactor; // 106 Ambient Light Adjusment Factor
> + UINT8 LuxLowValue; // 107 LUX Low Value
> + UINT8 LuxHighValue; // 108 LUX High Value
> +
> + UINT8 Reserved7[1]; // 109
> +
> + //
> + // Extended Mobile Access Values
> + //
> + UINT8 EmaEnable; // 110 EMA Enable
> + UINT16 EmaPointer; // 111 EMA Pointer
> + UINT16 EmaLength; // 113 EMA Length
> +
> + UINT8 Reserved8[1]; // 115
> +
> + //
> + // Mobile East Fork Values
> + //
> + UINT8 MefEnable; // 116 Mobile East Fork Enable
> +
> + //
> + // PCIe Dock Status
> + //
> + UINT8 PcieDockStatus; // 117 PCIe Dock Status
> +
> + UINT8 Reserved9[2]; // 118:119
> +
> + //
> + // TPM Registers
> + //
> + UINT8 TpmPresent; // 120 TPM Present
> + UINT8 TpmEnable; // 121 TPM Enable
> +
> + UINT8 MorData; // 122 Memory Overwrite Request Data
> + UINT8 TcgParamter; // 123 Used for save the Mor and/or physical
> presence parameter
> + UINT32 PPResponse; // 124 Physical Presence request operation
> response
> + UINT8 PPRequest; // 128 Physical Presence request operation
> + UINT8 LastPPRequest; // 129 Last Physical Presence request
> operation
> +
> + //
> + // SATA Values
> + //
> + UINT8 GtfTaskFileBufferPort0[7]; // 130 GTF Task File Buffer for Port 0
> + UINT8 GtfTaskFileBufferPort2[7]; // 137 GTF Task File Buffer for Port 2
> + UINT8 IdeMode; // 144 IDE Mode (Compatible\Enhanced)
> + UINT8 GtfTaskFileBufferPort1[7]; // 145:151 GTF Task File Buffer for
> Port 1
> +
> + UINT8 Reserved111[10]; // 152:161
> + UINT64 BootTimeLogAddress; // 162:169 Boot Time Log Table
> Address
> +
> + UINT32 IgdOpRegionAddress; // 170 IGD OpRegion Starting
> Address
> + UINT8 IgdBootType; // 174 IGD Boot Type CMOS option
> + UINT8 IgdPanelType; // 175 IGD Panel Type CMOs option
> + UINT8 IgdTvFormat; // 176 IGD TV Format CMOS option
> + UINT8 IgdTvMinor; // 177 IGD TV Minor Format CMOS option
> + UINT8 IgdPanelScaling; // 178 IGD Panel Scaling
> + UINT8 IgdBlcConfig; // 179 IGD BLC Configuration
> + UINT8 IgdBiaConfig; // 180 IGD BIA Configuration
> + UINT8 IgdSscConfig; // 181 IGD SSC Configuration
> + UINT8 Igd409; // 182 IGD 0409 Modified Settings Flag
> + UINT8 Igd509; // 183 IGD 0509 Modified Settings Flag
> + UINT8 Igd609; // 184 IGD 0609 Modified Settings Flag
> + UINT8 Igd709; // 185 IGD 0709 Modified Settings Flag
> + UINT8 IgdPowerConservation; // 186 IGD Power Conservation
> Feature Flag
> + UINT8 IgdDvmtMemSize; // 187 IGD DVMT Memory Size
> + UINT8 IgdFunc1Enable; // 188 IGD Function 1 Enable
> + UINT8 IgdHpllVco; // 189 HPLL VCO
> + UINT32 NextStateDid1; // 190 Next state DID1 for _DGS
> + UINT32 NextStateDid2; // 194 Next state DID2 for _DGS
> + UINT32 NextStateDid3; // 198 Next state DID3 for _DGS
> + UINT32 NextStateDid4; // 202 Next state DID4 for _DGS
> + UINT32 NextStateDid5; // 206 Next state DID5 for _DGS
> + UINT32 NextStateDid6; // 210 Next state DID6 for _DGS
> + UINT32 NextStateDid7; // 214 Next state DID7 for _DGS
> + UINT32 NextStateDid8; // 218 Next state DID8 for _DGS
> + UINT8 IgdSciSmiMode; // 222 GMCH SMI/SCI mode (0=SCI)
> + UINT8 IgdPAVP; // 223 IGD PAVP data
> + UINT8 IgdSelfRefresh; // 224 IGD Self Refresh
> + UINT8 PcieOSCControl; // 225 PCIE OSC Control
> + UINT8 NativePCIESupport; // 226 Native PCI Express Support
> +
> + //
> + // USB Sideband Deferring Support
> + //
> + UINT8 HostAlertVector; // 227 GPE vector used for HOST_ALERT
> + UINT8 HostAlertPio; // 228 PIO of USB device used for
> HOST_ALERT
> +
> + UINT8 Reserved112[27]; // 229
> + UINT32 NvIgOpRegionAddress; // 256 NVIG support
> + UINT32 NvHmOpRegionAddress; // 260 NVHM support
> + UINT32 ApXmOpRegionAddress; // 264 AMDA support
> + UINT32 DeviceId6; // 268 Device ID 6
> + UINT32 DeviceId7; // 272 Device ID 7
> + UINT32 DeviceId8; // 276 Device ID 8
> + UINT32 EndpointBaseAddress; // 280 PEG Endpoint PCIe Base
> Address
> + UINT32 CapStrPresence; // 284 PEG Endpoint Capability Structure
> Presence
> + UINT32 EndpointPcieCapBaseAddress; // 288 PEG Endpoint PCIe
> Capability Structure Base Address
> + UINT32 EndpointVcCapBaseAddress; // 292 PEG Endpoint Virtual
> Channel Capability Structure Base Address
> + UINT32 XPcieCfgBaseAddress; // 296 Any Device's PCIe Config
> Space Base Address
> + UINT32 OccupiedBuses1; // 300 Occupied Buses from 0 to 31
> + UINT32 OccupiedBuses2; // 304 Occupied Buses from 32 to 63
> + UINT32 OccupiedBuses3; // 308 Occupied Buses from 64 to 95
> + UINT32 OccupiedBuses4; // 312 Occupied Buses from 96 to 127
> + UINT32 OccupiedBuses5; // 316 Occupied Buses from 128 to 159
> + UINT32 OccupiedBuses6; // 320 Occupied Buses from 160 to 191
> + UINT32 OccupiedBuses7; // 324 Occupied Buses from 192 to 223
> + UINT32 OccupiedBuses8; // 328 Occupied Buses from 224 to 255
> + UINT8 UartSelection; // 332 UART Interface Selection 0: Internal;
> 1: SIO
> + UINT8 PcuUart1Enable; // 333 PCU UART 1 Enabled
> + UINT8 PcuUart2Enable; // 334 PCU UART 2 Enabled
> +
> + UINT32 LPEBar0; // 335~338 LPE Bar0
> + UINT32 LPEBar1; // 339~342 LPE Bar1
> +
> + UINT32 LPEBar2; // 343~346 LPE Bar2
> + UINT8 AcSetup; // 347 For Ac Powered Config option - IST
> applet
> + UINT8 BatterySetup; // 348 For Battery Powered Config option -
> IST applet
> + UINT8 PlatformFlavor; // 349 0:unknown 1: Mobile; 2: desktop
> + UINT8 Reserved113[1]; // 350
> +
> + UINT8 IsctReserve; // 351 ISCT / AOAC Configuration
> + UINT8 XhciMode; // 352 xHCI mode
> + UINT8 PmicEnable; // 353 PMIC enable
> +
> + UINT8 LpeEnable; // 354 LPE enable
> + UINT32 ISPAddr; // 355 ISP Base address
> + UINT8 ISPDevSel; // 359 ISP device enabled selection 0:
> Disabled; 1: PCI Device 2; 2: PCI Device 3
> +
> + //
> + // Lpss controllers
> + //
> + UINT32 PCIBottomAddress; //360 ((4+8+6)*4+2)*4=296
> + UINT32 PCITopAddress; //364
> +
> + UINT32 LDMA1Addr; // 368
> + UINT32 LDMA1Len; // 372
> + UINT32 LDMA11Addr; // 376
> + UINT32 LDMA11Len; // 380
> + UINT32 PWM1Addr; // 384 PWM1
> + UINT32 PWM1Len; // 388
> + UINT32 PWM11Addr; // 392
> + UINT32 PWM11Len; // 396
> + UINT32 PWM2Addr; // 400 PWM2
> + UINT32 PWM2Len; // 404
> + UINT32 PWM21Addr; // 408
> + UINT32 PWM21Len; // 412
> + UINT32 UART1Addr; // 416 UART1
> + UINT32 UART1Len; // 420
> + UINT32 UART11Addr; // 424 UART1
> + UINT32 UART11Len; // 428
> + UINT32 UART2Addr; // 432 UART2
> + UINT32 UART2Len; // 436
> + UINT32 UART21Addr; // 440 UART2
> + UINT32 UART21Len; // 444
> + UINT32 SPIAddr; // 448 SPI
> + UINT32 SPILen; // 452
> + UINT32 SPI1Addr; // 456
> + UINT32 SPI1Len; // 460
> +
> + UINT32 LDMA2Addr; // 464
> + UINT32 LDMA2Len; // 468
> + UINT32 LDMA21Addr; // 472
> + UINT32 LDMA21Len; // 476
> + UINT32 I2C1Addr; // 480 I2C1
> + UINT32 I2C1Len; // 484
> + UINT32 I2C11Addr; // 488 I2C1
> + UINT32 I2C11Len; // 492
> + UINT32 I2C2Addr; // 496 I2C2
> + UINT32 I2C2Len; // 500
> + UINT32 I2C21Addr; // 504 I2C2
> + UINT32 I2C21Len; // 508
> + UINT32 I2C3Addr; // 512 I2C3
> + UINT32 I2C3Len; // 516
> + UINT32 I2C31Addr; // 520 I2C3
> + UINT32 I2C31Len; // 524
> + UINT32 I2C4Addr; // 528 I2C4
> + UINT32 I2C4Len; // 532
> + UINT32 I2C41Addr; // 536 I2C4
> + UINT32 I2C41Len; // 540
> + UINT32 I2C5Addr; // 544 I2C5
> + UINT32 I2C5Len; // 548
> + UINT32 I2C51Addr; // 552 I2C5
> + UINT32 I2C51Len; // 556
> + UINT32 I2C6Addr; // 560 I2C6
> + UINT32 I2C6Len; // 564
> + UINT32 I2C61Addr; // 566 I2C6
> + UINT32 I2C61Len; // 570
> + UINT32 I2C7Addr; // 574 I2C7
> + UINT32 I2C7Len; // 578
> + UINT32 I2C71Addr; // 582 I2C7
> + UINT32 I2C71Len; // 586
> +
> + //
> + // Scc controllers
> + //
> + UINT32 eMMCAddr; // 590 EMMC
> + UINT32 eMMCLen; // 594
> + UINT32 eMMC1Addr; // 598
> + UINT32 eMMC1Len; // 602
> + UINT32 SDIOAddr; // 606 SDIO
> + UINT32 SDIOLen; // 610
> + UINT32 SDIO1Addr; // 614
> + UINT32 SDIO1Len; // 618
> + UINT32 SDCardAddr; // 622 SDCard
> + UINT32 SDCardLen; // 626
> + UINT32 SDCard1Addr; // 630
> + UINT32 SDCard1Len; // 636
> + UINT32 MipiHsiAddr; // 640 MIPI-HSI
> + UINT32 MipiHsiLen; // 644
> + UINT32 MipiHsi1Addr; // 648
> + UINT32 MipiHsi1Len; // 652
> +
> + UINT8 SdCardRemovable; // 656 reserve offset upto 658
> + UINT8 HideLPSSDevices; // 657 Hide unsupported LPSS devices
> when in ACPI mode
> + UINT8 ReservedO; // 658 OS Selection
> + UINT8 Reserved00; // 659
> + UINT8 Reserved01; // 660
> + UINT8 Reserved02; // 661
> + UINT8 Reserved03; // 662
> + UINT8 Reserved04; // 663
> + UINT8 Reserved05; // 664
> + UINT8 Reserved06; // 665
> + UINT8 Reserved07; // 666
> + UINT8 Reserved08; // 667
> + UINT8 Reserved09; // 668
> + UINT8 Reserved0A; // 669
> + UINT32 Reserved0B; // 670
> + UINT32 Reserved0C; // 674
> + UINT32 Reserved0D; // 678
> + UINT32 Reserved0E; // 682
> + UINT32 Reserved0F; // 686
> + UINT32 Reserved10; // 690
> + UINT32 Reserved11; // 694
> + UINT32 Reserved12; // 698
> + UINT32 Reserved13; // 702
> + UINT32 Reserved14; // 706
> + UINT32 Reserved15; // 710
> + UINT32 Reserved16; // 714
> + UINT8 Reserved17;
> + UINT32 Reserved18;
> + UINT32 Reserved19;
> + UINT32 Reserved1A;
> + UINT32 Reserved1B;
> + UINT32 Reserved1C;
> + UINT8 Reserved1D;
> + UINT32 Reserved1E;
> + UINT32 Reserved1F;
> + UINT32 Reserved20;
> + UINT32 Reserved21;
> + UINT32 Reserved22;
> + UINT8 Reserved23;
> + UINT8 BatteryChargingSolution; // 761 0-non ULPMC 1-ULPMC
> +
> + //
> + //101 bytes
> + //
> + UINT8 NFCnSelect; // 762 NFCx Select 1: NFC1 2:NFC2
> + UINT8 LpssSccMode; // 763 EMMC device 0-ACPI mode, 1-
> PCI mode
> +
> + UINT32 TPMAddress; // 764
> + UINT32 TPMLength; // 768
> +
> + UINT8 I2CTouchAddress; // 772 I2C touch address, 0x4B:RVP
> 0x4A:FFRD
> + UINT8 IdleReserve; // 773 0 - disabled 1 - enabled
> + UINT8 SDIOMode; // 774 3 - Default 2 - DDR50
> + UINT8 emmcVersion; // 775 0 - 4.41 1 - 4.5
> + UINT32 BmBound; // 776 BM Bound
> + UINT8 FsaStatus; // 780 0 - Fsa is off, 1- Fsa is on
> +
> + //
> + // Board Id
> + // This field is for the ASL code to know whether this board is Baylake or
> Bayley Bay etc
> + //
> + UINT8 BoardID; // 781
> + UINT8 FabID; // 782
> + UINT8 OtgMode; // 783 0- OTG disable 1- OTG PCI mode
> + UINT8 Stepping; // 784 Stepping
> + UINT8 WittEnable; // 785 WITT eanble 0 - disable 1 - enable
> +
> + UINT8 SocStepping; // 786 Soc Stepping infomation
> + UINT8 AmbientTripPointChange; // 787 DPTF: Controls whether
> _ATI changes other participant's trip point(enabled/disabled)
> + UINT8 UtsEnable; // 788 Uart Test eanble 0 - disable 1 -
> enable
> + UINT8 DptfReserve; // 789
> +
> + UINT8 SarEnable; // 790
> + UINT8 PssDeveice; // 791 PSS Deveice: 0 - None, 1 - Monzax
> 2K, 2 - Monzax 8K
> + UINT8 EDPV; // 792 Check for eDP display device
> + UINT32 DIDX; // 793 Device ID for eDP device
> + UINT8 MicrosoftIoT; // (794)JP1 pins are for Microsoft IoT
> project.
> + UINT8 RtcBattery; // (795) The Flag of RTC Battery Present.
> + UINT8 LpeAudioReportedByDSDT; // (796)
> +} EFI_GLOBAL_NVS_AREA;
> +#pragma pack ()
> +
> +//
> +// Global NVS Area Protocol
> +//
> +typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
> + EFI_GLOBAL_NVS_AREA *Area;
> +} EFI_GLOBAL_NVS_AREA_PROTOCOL;
> +
> +#endif
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h
> new file mode 100644
> index 0000000000..71fe6275ee
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h
> @@ -0,0 +1,235 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + HwWatchdogTimer.h
> +
> +Abstract:
> +
> +
> +--*/
> +
> +#ifndef __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__
> +#define __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__
> +
> +#define EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_GUID \
> + { 0xd5b06d16, 0x2ea1, 0x4def, 0x98, 0xd0, 0xa0, 0x5d, 0x40, 0x72, 0x84,
> 0x17 }
> +
> +#define EFI_WATCHDOG_TIMER_NOT_SUPPORTED_PROTOCOL_GUID \
> + { 0xe9e156ac, 0x3203, 0x4572, 0xac, 0xdf, 0x84, 0x4f, 0xdc, 0xdb, 0x6, 0xbf }
> +
> +
> +#include <Guid/HwWatchdogTimerHob.h>
> +
> +//
> +// General Purpose Constants
> +//
> +#define ICH_INSTAFLUSH_GPIO BIT16 // BIT 16 in GPIO Level 2 is GPIO 48.
> +#define B_INSTAFLUSH BIT4
> +
> +//
> +// Other Watchdog timer values
> +//
> +#define WDT_COUNTDOWN_VALUE 0x14
> +#define BDS_WDT_COUNTDOWN_VALUE 0x35
> +
> +//
> +// Prototypes for the Watchdog Timer Driver Protocol
> +//
> +
> +/**
> + This service begins the Watchdog Timer countdown. If the countdown
> completes prior to
> + Stop Timer or Restart Timer the system will reset.
> +
> + @param[in] None
> +
> + @retval EFI_SUCCESS Operation completed successfully
> + @retval EFI_DEVICE_ERROR The command was unsuccessful
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_WATCHDOG_START_TIMER) (
> + VOID
> + );
> +
> +/**
> + This service resets the Watchdog Timer countdown and should only be
> called after the
> + Start Timer function.
> +
> + @param[in] None
> +
> + @retval EFI_SUCCESS Operation completed successfully
> + @retval EFI_DEVICE_ERROR The command was unsuccessful
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *PEI_WATCHDOG_RESET_TIMER) (
> + VOID
> + );
> +
> +/**
> + This service restarts the Watchdog Timer countdown and should only be
> called after the
> + Start Timer function.
> +
> + @param[in] None
> +
> + @retval EFI_SUCCESS Operation completed successfully
> + @retval EFI_DEVICE_ERROR The command was unsuccessful
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_WATCHDOG_RESTART_TIMER) (
> + VOID
> + );
> +
> +/**
> + This service disables the Watchdog Timer countdown.
> +
> + @param[in] None
> +
> + @retval EFI_SUCCESS Operation completed successfully
> + @retval EFI_DEVICE_ERROR The command was unsuccessful
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_WATCHDOG_STOP_TIMER) (
> + VOID
> + );
> +
> +/**
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_WATCHDOG_CHECK_TIMEOUT) (
> + OUT HW_WATCHDOG_TIMEOUT *WatchdogTimeout
> + );
> +
> +
> +
> +/**
> + This service forces a reboot of the system due to a reset of the
> POWERGOOD_PS,
> + POWERGOOD_CLK, and the BSEL Override
> +
> + Arguments:
> + None
> +
> + Returns:
> + This function should not return!
> +
> + EFI_DEVICE_ERROR - The command was unsuccessful and a reboot did
> not occur
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_WATCHDOG_FORCE_REBOOT) (
> + IN BOOLEAN ForceTimeout,
> + IN UINT8 ResetType
> + );
> +
> +/**
> + This service notifies the Watchdog Timer of the fact that a known reset is
> occuring.
> +
> + @param[in] AllowReset TRUE if a Reset is currently expected
> + FALSE if a Reset is not currently expected
> +
> + This function should not return!
> +
> + EFI_DEVICE_ERROR - The command was unsuccessful and a reboot did
> not occur
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_WATCHDOG_KNOWN_RESET) (
> + IN BOOLEAN AllowReset
> + );
> +
> +/**
> + This service reads the current Watchdog Timer countdown reload value.
> +
> + @param[in] CountdownValue pointer to UINT32 to return the value of
> the reload register.
> +
> + @retval EFI_SUCCESS Operation completed successfully
> + @retval EFI_DEVICE_ERROR The command was unsuccessful
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_GET_TIMER_COUNT_DOWN_PERIOD)(
> + OUT UINT32 *CountdownValue
> + );
> +
> +/**
> + This service reads the current Watchdog Timer countdown reload value.
> +
> + @param[in] CountdownValue Value to set the reload register.
> +
> + @retval EFI_SUCCESS Operation completed successfully
> + @retval EFI_DEVICE_ERROR The command was unsuccessful
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_SET_TIMER_COUNT_DOWN_PERIOD)(
> + OUT UINT32 CountdownValue
> + );
> +
> +/**
> + This service clears the state that indicates the Watchdog Timer fired.
> +
> + @retval EFI_SUCCESS - Operation completed successfully
> + @retval EFI_DEVICE_ERROR - The command was unsuccessful
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *PEI_WATCHDOG_CLEAR_TIMER_STATE) (
> + );
> +
> +/**
> + This service disables the Watchdog Timer countdown. It also closes the
> recurring restart event
> + if the event exists.
> +
> + @param[in] Stall TRUE = Stop the timer countdown
> + FALSE = Start the timer countdown
> +
> + @retval EFI_SUCCESS Operation completed successfully
> + @retval EFI_DEVICE_ERROR The command was unsuccessful
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_STALL_WATCHDOG_COUNTDOWN) (
> + IN BOOLEAN Stall
> + );
> +
> +
> +typedef struct _EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL {
> + EFI_WATCHDOG_START_TIMER StartWatchdogTimer;
> + PEI_WATCHDOG_RESET_TIMER ResetWatchdogTimeout;
> + EFI_WATCHDOG_RESTART_TIMER RestartWatchdogTimer;
> + EFI_WATCHDOG_STOP_TIMER StopWatchdogTimer;
> + EFI_WATCHDOG_CHECK_TIMEOUT CheckWatchdogTimeout;
> + EFI_WATCHDOG_FORCE_REBOOT ForceReboot;
> + EFI_WATCHDOG_KNOWN_RESET AllowKnownReset;
> + EFI_GET_TIMER_COUNT_DOWN_PERIOD GetCountdownPeriod;
> + EFI_SET_TIMER_COUNT_DOWN_PERIOD SetCountdownPeriod;
> + PEI_WATCHDOG_CLEAR_TIMER_STATE ClearTimerState;
> + EFI_STALL_WATCHDOG_COUNTDOWN StallWatchdogCountdown;
> +} EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL;
> +
> +extern EFI_GUID gEfiWatchdogTimerDriverProtocolGuid;
> +extern EFI_GUID gEfiWatchdogTimerNotSupportedProtocolGuid;
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h
> new file mode 100644
> index 0000000000..9ec5e1473b
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h
> @@ -0,0 +1,107 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +**/
> +
> +#ifndef __I2C_ACPI_H__
> +#define __I2C_ACPI_H__
> +
> +#include <Protocol/DevicePath.h>
> +
> +//
> +// I2C ACPI protocol
> +//
> +typedef struct _EFI_I2C_ACPI_PROTOCOL EFI_I2C_ACPI_PROTOCOL;
> +
> +//
> +// I2C device description
> +//
> +// This structure provides the platform specific information which
> +// describes an I2C device.
> +//
> +typedef struct {
> + //
> + // Hardware revision - ACPI _HRV value
> + //
> + UINT32 HardwareRevision;
> +
> + //
> + // Device path node for the I2C device.
> + //
> + CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> +
> + //
> + // I2C bus configuration for the I2C device.
> + //
> + UINT32 I2cBusConfiguration;
> +
> + //
> + // Number of slave addresses for the I2C device.
> + //
> + UINT32 SlaveAddressCount;
> +
> + //
> + // Address of the array of slave addresses for the I2C device.
> + //
> + CONST UINT32 *SlaveAddressArray;
> +}EFI_I2C_DEVICE;
> +
> +
> +/**
> + Enumerate the I2C devices
> +
> + This routine must be called at or below TPL_NOTIFY.
> +
> + This function walks the platform specific data to enumerates the
> + I2C devices on an I2C bus.
> +
> + @param[in] This Address of an EFI_I2C_ENUM_PROTOCOL
> + structure.
> + @param[in, out] Device Buffer containing the address of an
> + EFI_I2C_DEVICE structure. Enumeration
> + is started by setting the initial
> + EFI_I2C_DEVICE structure address to NULL.
> + The buffer receives an EFI_I2C_DEVICE
> + structure address for the next I2C device.
> +
> + @retval EFI_SUCCESS The platform data for the next device
> + on the I2C bus was returned successfully.
> + @retval EFI_INVALID_PARAMETER NextDevice was NULL
> + @retval EFI_NO_MAPPING PreviousDevice does not point to a valid
> + EFI_I2C_DEVICE structure.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_I2C_ACPI_ENUMERATE) (
> + IN CONST EFI_I2C_ACPI_PROTOCOL *This,
> + IN OUT CONST EFI_I2C_DEVICE **Device
> + );
> +
> +//
> +// I2C device description
> +//
> +// This structure provides the platform specific information which
> +// describes an I2C device.
> +//
> +struct _EFI_I2C_ACPI_PROTOCOL {
> + //
> + // Walk the platform's list of I2C devices on the bus. This
> + // routine returns the next I2C device in the platform's list
> + // for this I2C bus.
> + //
> + EFI_I2C_ACPI_ENUMERATE Enumerate;
> +};
> +
> +//
> +// Variable containing the GUID for the I2C device enumeration protocol
> +//
> +extern EFI_GUID gEfiI2cAcpiProtocolGuid;
> +
> +#endif // __I2C_ACPI_H__
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h
> new file mode 100644
> index 0000000000..b321a026b2
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h
> @@ -0,0 +1,164 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef __I2C_BUS_H__
> +#define __I2C_BUS_H__
> +
> +#include <Protocol/I2cHostMcg.h>
> +
> +//
> +// I2C bus protocol
> +//
> +typedef struct _EFI_I2C_BUS_PROTOCOL EFI_I2C_BUS_PROTOCOL;
> +
> +
> +/**
> + Perform an I2C operation on the device
> +
> + This routine must be called at or below TPL_NOTIFY. For synchronous
> + requests this routine must be called at or below TPL_CALLBACK.
> +
> + N.B. The typical consumers of this API are the third party I2C
> + drivers. Extreme care must be taken by other consumers of this
> + API to prevent confusing the third party I2C drivers due to a
> + state change at the I2C device which the third party I2C drivers
> + did not initiate. I2C platform drivers may use this API within
> + these guidelines.
> +
> + This routine queues an operation to the I2C controller for execution
> + on the I2C bus.
> +
> + As an upper layer driver writer, the following need to be provided
> + to the platform vendor:
> +
> + 1. ACPI CID value or string - this is used to connect the upper layer
> + driver to the device.
> + 2. Slave address array guidance when the I2C device uses more than one
> + slave address. This is used to access the blocks of hardware within
> + the I2C device.
> +
> + @param[in] This Address of an EFI_I2C_BUS_PROTOCOL
> + structure
> + @param[in] SlaveAddressIndex Index into an array of slave addresses for
> + the I2C device. The values in the array are
> + specified by the board designer, with the
> + I2C device driver writer providing the slave
> + address order.
> +
> + For devices that have a single slave address,
> + this value must be zero. If the I2C device
> + uses more than one slave address then the third
> + party (upper level) I2C driver writer needs to
> + specify the order of entries in the slave address
> + array.
> +
> + \ref ThirdPartyI2cDrivers "Third Party I2C Drivers"
> + section in I2cMaster.h.
> + @param[in] Event Event to set for asynchronous operations,
> + NULL for synchronous operations
> + @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET
> + structure describing the I2C operation
> + @param[out] I2cStatus Optional buffer to receive the I2C operation
> + completion status
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_ABORTED The request did not complete because the
> driver
> + was shutdown.
> + @retval EFI_ACCESS_DENIED Invalid SlaveAddressIndex value
> + @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size
> is too large.
> + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the
> operation.
> + This could indicate the slave device is not present.
> + @retval EFI_INVALID_PARAMETER RequestPacket is NULL
> + @retval EFI_INVALID_PARAMETER TPL is too high
> + @retval EFI_NO_RESPONSE The I2C device is not responding to the
> + slave address. EFI_DEVICE_ERROR may also be
> + returned if the controller can not distinguish
> + when the NACK occurred.
> + @retval EFI_NOT_FOUND I2C slave address exceeds maximum
> address
> + @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for
> + the event and then read status pointed to by
> + the request packet.
> + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation
> + @retval EFI_TIMEOUT The transaction did not complete within an
> internally
> + specified timeout period.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_I2C_BUS_START_REQUEST) (
> + IN CONST EFI_I2C_BUS_PROTOCOL *This,
> + IN UINTN SlaveAddressIndex,
> + IN EFI_EVENT Event OPTIONAL,
> + IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,
> + OUT EFI_STATUS *I2cStatus OPTIONAL
> + );
> +
> +//
> +// The I2C bus protocol enables access to a specific device on the I2C bus.
> +//
> +// Each I2C device is described as an ACPI node (HID, UID and CID) within
> the
> +// platform layer. The I2C bus protocol enumerates the I2C devices in the
> +// platform and creates a unique handle and device path for each I2C device.
> +//
> +// I2C slave addressing is abstracted to validate addresses and limit
> operation
> +// to the specified I2C device. The third party providing the I2C device
> support
> +// provides an ordered list of slave addresses for the I2C device to the team
> +// building the platform layer. The platform team must preserve the order
> of the
> +// supplied list. SlaveAddressCount is the number of entries in this list or
> +// array within the platform layer. The third party device support
> references
> +// a slave address using an index into the list or array in the range of zero
> +// to SlaveAddressCount - 1.
> +//
> +struct _EFI_I2C_BUS_PROTOCOL {
> + //
> + // Start an I2C operation on the bus
> + //
> + EFI_I2C_BUS_START_REQUEST StartRequest;
> +
> + //
> + // The maximum number of slave addresses for the I2C device. The caller
> may
> + // validate this value as a check on the platform layer's configuration. Slave
> + // address selection uses an index value in the range of zero to
> SlaveAddressCount - 1.
> + //
> + UINTN SlaveAddressCount;
> +
> + //
> + // Hardware revision - Matches the ACPI _HRV value
> + //
> + // The HardwareRevision value allows a single driver to support multiple
> hardware
> + // revisions and implement the necessary workarounds for limitations
> within the
> + // hardware.
> + //
> + UINT32 HardwareRevision;
> +
> + //
> + // The maximum number of bytes the I2C host controller
> + // is able to receive from the I2C bus.
> + //
> + UINT32 MaximumReceiveBytes;
> +
> + //
> + // The maximum number of bytes the I2C host controller
> + // is able to send on the I2C bus.
> + //
> + UINT32 MaximumTransmitBytes;
> +
> + //
> + // The maximum number of bytes in the I2C bus transaction.
> + //
> + UINT32 MaximumTotalBytes;
> +};
> +
> +//
> +// GUID for the I2C bus protocol
> +//
> +extern EFI_GUID gEfiI2cBusProtocolGuid;
> +
> +#endif // __I2C_BUS_H__
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h
> new file mode 100644
> index 0000000000..1cfca218bd
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h
> @@ -0,0 +1,163 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef __I2C_BUS_H__
> +#define __I2C_BUS_H__
> +
> +#include <Protocol/I2cHostMcg.h>
> +
> +//
> +// I2C bus protocol
> +//
> +typedef struct _EFI_I2C_BUS_PROTOCOL EFI_I2C_BUS_PROTOCOL;
> +
> +/**
> + Perform an I2C operation on the device
> +
> + This routine must be called at or below TPL_NOTIFY. For synchronous
> + requests this routine must be called at or below TPL_CALLBACK.
> +
> + N.B. The typical consumers of this API are the third party I2C
> + drivers. Extreme care must be taken by other consumers of this
> + API to prevent confusing the third party I2C drivers due to a
> + state change at the I2C device which the third party I2C drivers
> + did not initiate. I2C platform drivers may use this API within
> + these guidelines.
> +
> + This routine queues an operation to the I2C controller for execution
> + on the I2C bus.
> +
> + As an upper layer driver writer, the following need to be provided
> + to the platform vendor:
> +
> + 1. ACPI CID value or string - this is used to connect the upper layer
> + driver to the device.
> + 2. Slave address array guidance when the I2C device uses more than one
> + slave address. This is used to access the blocks of hardware within
> + the I2C device.
> +
> + @param[in] This Address of an EFI_I2C_BUS_PROTOCOL
> + structure
> + @param[in] SlaveAddressIndex Index into an array of slave addresses for
> + the I2C device. The values in the array are
> + specified by the board designer, with the
> + I2C device driver writer providing the slave
> + address order.
> +
> + For devices that have a single slave address,
> + this value must be zero. If the I2C device
> + uses more than one slave address then the third
> + party (upper level) I2C driver writer needs to
> + specify the order of entries in the slave address
> + array.
> +
> + \ref ThirdPartyI2cDrivers "Third Party I2C Drivers"
> + section in I2cMaster.h.
> + @param[in] Event Event to set for asynchronous operations,
> + NULL for synchronous operations
> + @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET
> + structure describing the I2C operation
> + @param[out] I2cStatus Optional buffer to receive the I2C operation
> + completion status
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_ABORTED The request did not complete because the
> driver
> + was shutdown.
> + @retval EFI_ACCESS_DENIED Invalid SlaveAddressIndex value
> + @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size
> is too large.
> + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the
> operation.
> + This could indicate the slave device is not present.
> + @retval EFI_INVALID_PARAMETER RequestPacket is NULL
> + @retval EFI_INVALID_PARAMETER TPL is too high
> + @retval EFI_NO_RESPONSE The I2C device is not responding to the
> + slave address. EFI_DEVICE_ERROR may also be
> + returned if the controller can not distinguish
> + when the NACK occurred.
> + @retval EFI_NOT_FOUND I2C slave address exceeds maximum
> address
> + @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for
> + the event and then read status pointed to by
> + the request packet.
> + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation
> + @retval EFI_TIMEOUT The transaction did not complete within an
> internally
> + specified timeout period.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_I2C_BUS_START_REQUEST) (
> + IN CONST EFI_I2C_BUS_PROTOCOL *This,
> + IN UINTN SlaveAddressIndex,
> + IN EFI_EVENT Event OPTIONAL,
> + IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,
> + OUT EFI_STATUS *I2cStatus OPTIONAL
> + );
> +
> +//
> +// The I2C bus protocol enables access to a specific device on the I2C bus.
> +//
> +// Each I2C device is described as an ACPI node (HID, UID and CID) within
> the
> +// platform layer. The I2C bus protocol enumerates the I2C devices in the
> +// platform and creates a unique handle and device path for each I2C device.
> +//
> +// I2C slave addressing is abstracted to validate addresses and limit
> operation
> +// to the specified I2C device. The third party providing the I2C device
> support
> +// provides an ordered list of slave addresses for the I2C device to the team
> +// building the platform layer. The platform team must preserve the order
> of the
> +// supplied list. SlaveAddressCount is the number of entries in this list or
> +// array within the platform layer. The third party device support
> references
> +// a slave address using an index into the list or array in the range of zero
> +// to SlaveAddressCount - 1.
> +//
> +struct _EFI_I2C_BUS_PROTOCOL {
> + //
> + // Start an I2C operation on the bus
> + //
> + EFI_I2C_BUS_START_REQUEST StartRequest;
> +
> + //
> + // The maximum number of slave addresses for the I2C device. The caller
> may
> + // validate this value as a check on the platform layer's configuration. Slave
> + // address selection uses an index value in the range of zero to
> SlaveAddressCount - 1.
> + //
> + UINTN SlaveAddressCount;
> +
> + //
> + // Hardware revision - Matches the ACPI _HRV value
> + //
> + // The HardwareRevision value allows a single driver to support multiple
> hardware
> + // revisions and implement the necessary workarounds for limitations
> within the
> + // hardware.
> + //
> + UINT32 HardwareRevision;
> +
> + //
> + // The maximum number of bytes the I2C host controller
> + // is able to receive from the I2C bus.
> + ///
> + UINT32 MaximumReceiveBytes;
> +
> + //
> + // The maximum number of bytes the I2C host controller
> + // is able to send on the I2C bus.
> + //
> + UINT32 MaximumTransmitBytes;
> +
> + //
> + // The maximum number of bytes in the I2C bus transaction.
> + //
> + UINT32 MaximumTotalBytes;
> +};
> +
> +//
> +// GUID for the I2C bus protocol
> +//
> +extern EFI_GUID gEfiI2cBusProtocolGuid;
> +
> +#endif // __I2C_BUS_H__
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h
> new file mode 100644
> index 0000000000..1d94ee4106
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h
> @@ -0,0 +1,138 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef __I2C_HOST_H__
> +#define __I2C_HOST_H__
> +
> +#include <Protocol/I2cMasterMcg.h>
> +
> +/**
> + Declare the forward references
> +
> +**/
> +typedef struct _EFI_I2C_HOST_PROTOCOL EFI_I2C_HOST_PROTOCOL;
> +typedef struct _EFI_I2C_HOST_CALLBACKS EFI_I2C_HOST_CALLBACKS;
> +
> +
> +/**
> + Queue an I2C operation for execution on the I2C controller.
> +
> + This routine must be called at or below TPL_NOTIFY. For synchronous
> + requests this routine must be called at or below TPL_CALLBACK.
> +
> + N.B. The typical consumers of this API are the I2C bus driver and
> + on rare occasions the I2C test application. Extreme care must be
> + taken by other consumers of this API to prevent confusing the
> + third party I2C drivers due to a state change at the I2C device
> + which the third party I2C drivers did not initiate. I2C platform
> + drivers may use this API within these guidelines.
> +
> + This layer uses the concept of I2C bus configurations to describe
> + the I2C bus. An I2C bus configuration is defined as a unique
> + setting of the multiplexers and switches in the I2C bus which
> + enable access to one or more I2C devices. When using a switch
> + to divide a bus, due to speed differences, the I2C platform layer
> + would define an I2C bus configuration for the I2C devices on each
> + side of the switch. When using a multiplexer, the I2C platform
> + layer defines an I2C bus configuration for each of the selector
> + values required to control the multiplexer. See Figure 1 in the
> + <a
> href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I<sup
> >2</sup>C
> + Specification</a> for a complex I2C bus configuration.
> +
> + The I2C host driver processes all operations in FIFO order. Prior to
> + performing the operation, the I2C host driver calls the I2C platform
> + driver to reconfigure the switches and multiplexers in the I2C bus
> + enabling access to the specified I2C device. The I2C platform driver
> + also selects the maximum bus speed for the device. After the I2C bus
> + is configured, the I2C host driver calls the I2C port driver to
> + initialize the I2C controller and start the I2C operation.
> +
> + @param[in] This Address of an EFI_I2C_HOST_PROTOCOL instance.
> + @param[in] I2cBusConfiguration I2C bus configuration to access the I2C
> + device.
> + @param[in] SlaveAddress Address of the device on the I2C bus.
> + @param[in] Event Event to set for asynchronous operations,
> + NULL for synchronous operations
> + @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET
> + structure describing the I2C operation
> + @param[out] I2cStatus Optional buffer to receive the I2C operation
> + completion status
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_ABORTED The request did not complete because the
> driver
> + was shutdown.
> + @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size
> is too large.
> + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the
> operation.
> + This could indicate the slave device is not present.
> + @retval EFI_INVALID_PARAMETER RequestPacket is NULL
> + @retval EFI_INVALID_PARAMETER TPL is too high
> + @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value
> + @retval EFI_NO_RESPONSE The I2C device is not responding to the
> + slave address. EFI_DEVICE_ERROR may also be
> + returned if the controller cannot distinguish
> + when the NACK occurred.
> + @retval EFI_NOT_FOUND I2C slave address exceeds maximum
> address
> + @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for
> + the event and then read status pointed to by
> + the request packet.
> + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation
> + @retval EFI_TIMEOUT The transaction did not complete within an
> internally
> + specified timeout period.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_I2C_HOST_QUEUE_REQUEST) (
> + IN CONST EFI_I2C_HOST_PROTOCOL *This,
> + IN UINTN I2cBusConfiguration,
> + IN UINTN SlaveAddress,
> + IN EFI_EVENT Event OPTIONAL,
> + IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,
> + OUT EFI_STATUS *I2cStatus OPTIONAL
> + );
> +
> +///
> +/// Host access to the I2C bus.
> +///
> +struct _EFI_I2C_HOST_PROTOCOL {
> + ///
> + /// Queue an operation for execution on the I2C bus
> + ///
> + EFI_I2C_HOST_QUEUE_REQUEST QueueRequest;
> +
> + ///
> + /// The maximum number of I2C bus configurations
> + ///
> + UINTN I2cBusConfigurationCount;
> +
> + ///
> + /// The maximum number of bytes the I2C host controller
> + /// is able to receive from the I2C bus.
> + ///
> + UINT32 MaximumReceiveBytes;
> +
> + ///
> + /// The maximum number of bytes the I2C host controller
> + /// is able to send on the I2C bus.
> + ///
> + UINT32 MaximumTransmitBytes;
> +
> + ///
> + /// The maximum number of bytes in the I2C bus transaction.
> + ///
> + UINT32 MaximumTotalBytes;
> +};
> +
> +///
> +/// GUID for the EFI_I2C_HOST_PROTOCOL
> +///
> +extern EFI_GUID gEfiI2cHostProtocolGuid;
> +
> +#endif // __I2C_HOST_H__
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h
> new file mode 100644
> index 0000000000..5ca47b2c7f
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h
> @@ -0,0 +1,519 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> + \section I2cDriverStack I2C Driver Stack
> +
> + The following is a representation of the I<sup>2</sup>C (I2C)
> + driver stack and an I2C bus layout.
> +
> + <code><pre>
> + +-----------------+
> + | Application |
> + +-----------------+
> + |
> + | Third Party or UEFI
> + |
> + V
> + +--------+ +-----------------+
> + | Slave | | Third Party |
> + | Driver | | I2C Device |
> + | | | Driver |
> + +--------+ +-----------------+
> + | |
> + | BUS |
> + | |
> + | V
> + | +-----------------+
> + | | I2C Bus Driver |------------------.
> + | +-----------------+ |
> + | | |
> + | HOST | BUS |
> + | | CONFIGURATION |
> +SLAVE | V MANAGEMENT | ACPI
> + | +-----------------+ |
> + | | I2C Host Driver |----------. |
> + | +-----------------+ | |
> + | | | |
> + | MASTER | V V
> + | | +-------=-------------+
> + | V | I2C Platform Driver |
> + | +-----------------+ +---------------------+
> + `------>| I2C Port Driver | | |
> + +-----------------+ | |
> + | | |
> + Software | | |
> + --------------------------------------------------
> + Hardware | | |
> + | | |
> + V | |
> + +-----------------+ | |
> + | I2C Controller | | |
> + +-----------------+ | |
> + | | |
> + ----------------------- | |
> + I2C Bus | | |
> + | +------------+ | |
> + +----| High speed | | |
> + | | I2C device | | |
> + | | 0x01 | | |
> + | +------------+ | |
> + | | |
> + +---------+ 0 | |
> + | Switch |<------------------` |
> + +---------+ 1 |
> + | |
> + | +------------+ |
> + +----| Fast speed | |
> + | | I2C device | |
> + | | 0x02 | |
> + | +------------+ |
> + | |
> + +-------------+ |
> + | Multiplexer |<-----------------------`
> + +-------------+
> + 0 | | 1
> + | |
> + | |
> + | | +-------------+
> + | +----| Third Party |
> + | | | I2C Device |
> + | | | 0x03, 0x04 |
> + | | +-------------+
> + | |
> + |
> + | +-------------+
> + +------------| Third Party |
> + | | I2C Device |
> + | | 0x03, 0x04 |
> + | +-------------+
> + |
> + </pre></code>
> +
> + The platform hardware designer chooses the bus layout based upon
> + the platform, I2C chip and software requirements. The design uses
> + switches to truncate the bus to enable higher speed operation for a
> + subset of devices which are placed closer to the controller. When the
> + switch is on, the extended bus must operate at a lower speed. The
> + design uses multiplexer to create separate address spaces enabling
> + the use of multiple devices which would otherwise have conflicting
> + addresses. See the
> + <a
> href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I<sup
> >2</sup>C
> + Specification</a> for more details.
> +
> + N.B. Some operating systems may prohibit the changing of switches
> + and multiplexers in the I2C bus. In this case the platform hardware
> + and software designers must select a single I2C bus configuration
> + consisting of constant input values for the switches and multiplexers.
> + The platform software designer must then ensure that this I2C bus
> + configuration is enabled prior to passing control to the operating
> + system.
> +
> + The platform hardware designer needs to provide the platform software
> + designer the following data for each I2C bus:
> +
> + 1. Which controller controls this bus
> +
> + 2. A list of logic blocks contained in one or more I2C devices:
> +
> + a. I2C device which contains this logic block
> +
> + b. Logic block slave address
> +
> + c. Logic block name
> +
> + 3. For each configuration of the switches and multiplexer
> +
> + a. What is the maximum speed of operation
> +
> + b. What devices are accessible
> +
> + 4. The settings for the switches and multiplexers when control is
> + given to the operating system.
> +
> + \section ThirdPartyI2cDrivers Third Party I2C Drivers
> +
> + This layer is I2C chip specific but platform and host controller
> + independent.
> +
> + Third party I2C driver writers, typically silicon vendors, need
> + to provide:
> +
> + 1. The device path node data that is used to select their
> + driver.
> +
> + 2. The order for the blocks of logic that get referenced
> + by the entries in the slave address array.
> +
> + 3. The hardware version of the I2C device, this value is passed
> + to the third party I2C driver to enable it to perform work
> + arounds for the specific hardware version. This value should
> + match the value in the ACPI _HRV tag.
> +
> + The third party I2C driver uses relative addressing to abstract
> + the platform specific details of the I2C device. Using an
> + example I2C device containing an accelerometer and a magnetometer
> + which consumes two slave addresses, one for each logic block. The
> + third party I2C driver writer may choose to write two drivers, one
> + for each block of logic, in which case each driver refers to the
> + single I2C slave address using the relative value of zero (0).
> + However if the third party I2C driver writer chooses to write a
> + single driver which consumes multiple slave addresses then the
> + third party I2C driver writer needs to convey the order of the
> + I2C slave address entries in the slave address array to the
> + platform software designer. For the example:
> +
> + 0: Accelerometer
> +
> + 1: Magnetometer
> +
> + The platform hardware designer picks the actual slave addresses
> + from the I2C device's data sheet and provides this information
> + to the platform software designer. The platform software designer
> + then places the slave addresses into the slave address array in the
> + order specified by the third party I2C driver writer. The third
> + party driver I2C writer then indirectly references this array by
> + specifying the index value as the relative slave address. The
> + relative value always starts at zero (0) and its maximum value is
> + the number of entries in slave address array minus one.
> +
> + The slave address is specified as a 32-bit integer to allow room
> + for future slave address expansion. Only the port driver knows
> + the maximum slave address value. All other drivers and
> + applications must look for the EFI_NOT_FOUND status for the
> + indication that the maximum slave address was exceeded.
> +
> + \section I2cBusDriver I2C Bus Driver
> +
> + This layer is platform, host controller, and I2C chip independent.
> +
> + The I2C bus driver creates a handle for each of the I2C devices
> + described within the platform driver. The I2C controller's device
> + path is extended with the device path node provided by the platform
> + driver and attached to the handle. The third party I2C device driver
> + uses the device path to determine if it may connect. For ACPI nodes,
> + the third party I2C driver should use the CID or CidString value.
> +
> + The I2C bus driver validates the relative address for the I2C device
> + and then converts the relative value to an actual I2C slave address.
> + The request is then passed to the I2C host driver.
> +
> + \section I2cHostDriver I2C Host Driver
> +
> + This layer is platform, host controller, and I2C chip independent.
> +
> + N.B. For proper operation of the I2C bus, only the I2C bus driver
> + and the I2C test application should connect to the I2C host driver
> + via the EFI_I2C_HOST_DRIVER_PROTOCOL.
> +
> + The I2C host driver may access any device on the I2C bus. The I2C
> + host driver has the following responsibilities:
> +
> + 1. Limits the number of requests to the I2C port driver to one.
> + The I2C host driver holds on to additional requests until the
> + I2C port driver is available to process the request. The I2C
> + requests are issued in FIFO order to the I2C port driver.
> +
> + 2. Enable the proper I2C bus configuration before starting the
> + I2C request on the I2C port driver
> +
> + I2C devices are addressed as the tuple: BusConfiguration:SlaveAddress.
> + I2C bus configuration zero (0) is the portion of the I2C bus that
> + connects to the host controller. The bus configuration specifies
> + the control values for the switches and multiplexers in the I2C bus.
> + After the switches and multiplexers are properly configured, the I2C
> + controller uses the slave address to access the requested I2C device.
> +
> + Since the I2C driver stack supports asynchronous operations this
> + layer maintains a queue of I2C requests until the I2C controller
> + is available them. When a request reaches the head of the queue
> + the necessary bus configuration is enabled and then the request
> + is sent to the I2C port driver.
> +
> + \section I2cPortDriver I2C Port Driver
> +
> + This layer is I2C controller specific but platform independent.
> +
> + This layer manipulates the I2C controller to perform an operation
> + on the I2C bus. This layer does not configure the I2C bus so it
> + is up to the caller to ensure that the I2C bus is in the proper
> + configuration before issuing the I2C request.
> +
> + This layer typically needs the following information:
> +
> + 1. Host controller address
> + 2. Controller's input clock frequency
> +
> + Depending upon the I2C controller, more data may be necessary.
> + This layer may use any method to get these values: hard coded
> + values, PCD values, or may choose to communicate with the platform
> + layer using an undefined mechanism to get these values.
> +
> + If the I2C port driver requires data from the platform driver then
> + the I2C port driver writer needs to provide the platform interface
> + details to the platform software designer.
> +
> + \section I2cPlatformDriver I2C Platform Driver
> +
> + When enabling access to I2C devices within UEFI, this driver
> + installs the EFI_I2C_ACPI_PROTOCOL to provide the I2C device
> + descriptions to the I2C bus driver using the EFI_I2C_DEVICE
> + structure. These descriptions include the bus configuration
> + number required for the I2C device, the slave address array
> + and the device path.
> +
> + The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol is optional.
> + This protocol needs to be specified under the following conditions:
> +
> + 1. The I2C bus must operate at a frequency greater than 100 KHz
> + 2. The I2C bus contains switches or multiplexers.
> +
> + The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol enables the
> + I2C host driver to call into the I2C platform driver to enable
> + a specific I2C bus configuration and set its maximum clock speed.
> +
> + The platform software designer collects the data requirements
> + from third party I2C driver writers, the I2C controller
> + driver writer, the EFI_I2C_ACPI_PROTOCOL and
> + EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL. The
> platform
> + software designer gets the necessary data from the platform
> + hardware designer. The platform software designer then builds
> + the data structures and implements the necessary routines to
> + construct the I2C platform driver.
> +
> + \section I2cSwitches Switches and Multiplexers
> +
> + There are some I2C switches and I2C multiplexers where the control
> + is done via I2C commands. When the control inputs come via the
> + same I2C bus that is being configured then the platform driver must
> + use the EFI_I2C_MASTER_PROTOCOL that is passed to the platform
> + driver. While the I2C host driver makes the call to the I2C
> + platform driver to configure the bus, the host driver keeps the
> + I2C port driver idle, to allow the I2C platform driver preform
> + the necessary configuration operations.
> +
> + If however the configuration control is done via and I2C device
> + connected to a different I2C bus (host controller), then it is
> + possible for the platform software designer may choose between
> + the following:
> +
> + 1. Call into a third party I2C driver to manipulate the I2C
> + bus control device.
> + 2. Call into the EFI_I2C_BUS_PROTOCOL if no third party I2C
> + driver exists for the I2C bus control device
> + 3. Call into the EFI_I2C_HOST_PROTOCOL if the platform does
> + not expose the I2C bus control device.
> +
> +**/
> +
> +#ifndef __I2C_MASTER_H__
> +#define __I2C_MASTER_H__
> +
> +/**
> + Declare the forward references
> +
> +**/
> +typedef struct _EFI_I2C_MASTER_PROTOCOL
> EFI_I2C_MASTER_PROTOCOL; ///< I2C master protocol
> +
> +///
> +/// I2C device operation
> +///
> +/// This structure provides the information necessary for an operation
> +/// on an I2C device
> +///
> +typedef struct {
> + ///
> + /// Number of bytes to send to the I2C device
> + ///
> + UINT32 WriteBytes;
> +
> + ///
> + /// Number of bytes to read, set to zero for write only operations
> + ///
> + UINT32 ReadBytes;
> +
> + ///
> + /// Address of the buffer containing the data to send to the I2C device.
> + /// The WriteBuffer must be at least WriteBytes in length.
> + ///
> + UINT8 *WriteBuffer;
> +
> + ///
> + /// Address of the buffer to receive data from the I2C device. Use NULL
> + /// for write only operations. The ReadBuffer must be at least ReadBytes
> + /// in length.
> + ///
> + UINT8 *ReadBuffer;
> +
> + ///
> + /// Timeout for the I2C operation in 100 ns units
> + ///
> + UINT32 Timeout;
> +} EFI_I2C_REQUEST_PACKET;
> +
> +
> +/**
> + Set the I2C controller bus clock frequency.
> +
> + This routine must be called at or below TPL_NOTIFY.
> +
> + The software and controller do a best case effort of using the specified
> + frequency for the I2C bus. If the frequency does not match exactly then
> + the controller will use a slightly lower frequency to avoid
> + exceeding the operating conditions for any of the I2C devices on the bus.
> + For example if 400 KHz was specified and the controller's divide network
> + only supports 402 KHz or 398 KHz then the controller would be set to 398
> + KHz. However if the desired frequency is 400 KHz and the controller only
> + supports 1 MHz and 100 KHz then this routine would return
> EFI_UNSUPPORTED.
> +
> + @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
> + structure
> + @param[in] BusClockHertz New I2C bus clock frequency in Hertz
> +
> + @retval EFI_SUCCESS The bus frequency was set successfully.
> + @retval EFI_UNSUPPORTED The controller does not support this
> frequency.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_I2C_MASTER_BUS_FREQUENCY_SET) (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This,
> + IN UINTN BusClockHertz
> + );
> +
> +/**
> + Reset the I2C controller and configure it for use
> +
> + This routine must be called at or below TPL_NOTIFY.
> +
> + The I2C controller is reset and the I2C bus frequency is set to 100 KHz.
> +
> + @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
> + structure
> +
> +**/
> +typedef
> +VOID
> +(EFIAPI *EFI_I2C_MASTER_RESET) (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This
> + );
> +
> +/**
> + Start an I2C operation on the host controller
> +
> + This routine must be called at or below TPL_NOTIFY. For synchronous
> + requests this routine must be called at or below TPL_CALLBACK.
> +
> + This function initiates an I2C operation on the controller.
> +
> + The operation is performed by selecting the I2C device with its slave
> + address and then sending all write data to the I2C device. If read data
> + is requested, a restart is sent followed by the slave address and then
> + the read data is clocked into the I2C controller and placed in the read
> + buffer. When the operation completes, the status value is returned and
> + then the event is set.
> +
> + N.B. The typical consumer of this API is the I2C host driver.
> + Extreme care must be taken by other consumers of this API to
> + prevent confusing the third party I2C drivers due to a state
> + change at the I2C device which the third party I2C drivers did
> + not initiate. I2C platform drivers may use this API within
> + these guidelines.
> +
> + N.B. This API supports only one operation, no queuing support
> + exists at this layer. This API assumes that the I2C bus is in
> + the correct configuration for the I2C request.
> +
> + @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
> + structure
> + @param[in] SlaveAddress Address of the device on the I2C bus.
> + @param[in] Event Event to set for asynchronous operations,
> + NULL for synchronous operations
> + @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET
> + structure describing the I2C operation
> + @param[out] I2cStatus Optional buffer to receive the I2C operation
> + completion status
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_ABORTED The request did not complete because the
> driver
> + was shutdown.
> + @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size
> is too large.
> + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the
> operation.
> + This could indicate the slave device is not present.
> + @retval EFI_INVALID_PARAMETER RequestPacket is NULL
> + @retval EFI_INVALID_PARAMETER TPL is too high
> + @retval EFI_NOT_FOUND SlaveAddress exceeds maximum address
> + @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for
> + the event and then read status pointed to by
> + the request packet.
> + @retval EFI_NO_RESPONSE The I2C device is not responding to the
> + slave address. EFI_DEVICE_ERROR may also be
> + returned if the controller cannot distinguish
> + when the NACK occurred.
> + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation
> + @retval EFI_TIMEOUT The transaction did not complete within an
> internally
> + specified timeout period.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_I2C_MASTER_START_REQUEST) (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This,
> + IN UINTN SlaveAddress,
> + IN EFI_EVENT Event OPTIONAL,
> + IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,
> + OUT EFI_STATUS *I2cStatus OPTIONAL
> + );
> +
> +///
> +/// I2C master mode protocol
> +///
> +/// This protocol manipulates the I2C host controller to perform transactions
> as a
> +/// master on the I2C bus using the current state of any switches or
> multiplexers
> +/// in the I2C bus.
> +///
> +struct _EFI_I2C_MASTER_PROTOCOL {
> + ///
> + /// Set the clock frequency for the I2C bus
> + ///
> + EFI_I2C_MASTER_BUS_FREQUENCY_SET BusFrequencySet;
> +
> + ///
> + /// Reset the I2C host controller
> + ///
> + EFI_I2C_MASTER_RESET Reset;
> +
> + ///
> + /// Start an I2C transaction in master mode on the host controller
> + ///
> + EFI_I2C_MASTER_START_REQUEST StartRequest;
> +
> + ///
> + /// The maximum number of bytes the I2C host controller
> + /// is able to receive from the I2C bus.
> + ///
> + UINT32 MaximumReceiveBytes;
> +
> + ///
> + /// The maximum number of bytes the I2C host controller
> + /// is able to send on the I2C bus.
> + ///
> + UINT32 MaximumTransmitBytes;
> +
> + ///
> + /// The maximum number of bytes in the I2C bus transaction.
> + ///
> + UINT32 MaximumTotalBytes;
> +};
> +
> +///
> +/// GUID for the EFI_I2C_MASTER_PROTOCOL
> +///
> +extern EFI_GUID gEfiI2cMasterProtocolGuid;
> +
> +#endif // __I2C_MASTER_H__
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h
> new file mode 100644
> index 0000000000..64cb2b7398
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h
> @@ -0,0 +1,194 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +**/
> +
> +#ifndef __I2C_SLAVE_H__
> +#define __I2C_SLAVE_H__
> +
> +#include <Protocol/I2cHostMcg.h>
> +
> +/**
> + Declare the forward references
> +
> +**/
> +typedef struct _EFI_I2C_SLAVE_PROTOCOL EFI_I2C_SLAVE_PROTOCOL;
> ///< I2C slave protocol
> +
> +/**
> + The I2C controller received a data byte from the
> + I2C msster.
> +
> + @param[in] Context The value passed to the slave enable routine.
> + @param[in] NumberOfBytes Number of data bytes received
> + @param[in] Data Buffer containing the received data bytes
> +
> + @retval EFI_SUCCESS ACK the data byte
> + @retval EFI_UNSUPPORTED NACK the data byte
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_I2C_SLAVE_RECEIVE_DATA) (
> + IN VOID *Context,
> + IN UINTN NumberOfBytes,
> + IN CONST UINT8 *Data
> + );
> +
> +/**
> + The I2C controller received the start bit from the
> + I2C master.
> +
> + @param[in] Context The value passed to the slave enable routine.
> +
> +**/
> +typedef
> +VOID
> +(EFIAPI *EFI_I2C_SLAVE_RECEIVE_START) (
> + IN VOID *Context,
> + IN UINTN BytesSent,
> + IN EFI_STATUS Status
> + );
> +
> +/**
> + The I2C controller received the stop bit from the
> + I2C master.
> +
> + @param[in] Context The value passed to the slave enable routine.
> + @param[in] BytesSent Number of bytes successfully ACKed by the
> + I2C master. This is a hint, not all I2C
> + controllers support the ability to return
> + the number of bytes sent. When it is not
> + possible, the port driver returns zero.
> + @param[in] Status <ul>
> + <li>EFI_SUCCESS - All of the data was successfully sent</li>
> + <li>EFI_ABORTED - The controller was reset</li>
> + <li>EFI_DEVICE_ERROR - A NACK was received when sending
> the data.</li>
> + <li>EFI_END_OF_FILE - The stop bit was received before all
> of
> + the data was sent.</li>
> + </ul>
> +
> +**/
> +typedef
> +VOID
> +(EFIAPI *EFI_I2C_SLAVE_RECEIVE_STOP) (
> + IN VOID *Context,
> + IN UINTN BytesSent,
> + IN EFI_STATUS Status
> + );
> +
> +/**
> + Enable or disable I2C slave operation.
> +
> + The ReceiveData callback allows the port driver to return data
> + to the driver or application handling slave mode operations. This
> + is data that a remote master has sent to the local I2C controller.
> + The data may be returned one byte at a time if the controller supports
> + the ability to ACK/NACK on each receive byte. If not, a block of
> + data may be returned by the I2C port driver and the ACK/NACK status
> + is used only as a hint for the port driver.
> +
> + The slave mode driver or application should buffer the data until
> + either ReceiveStart or ReceiveStop is called. At that time all of
> + the data is received and the command may be processed.
> +
> + ReceiveStart is called when the I2C master is expecting a response.
> + After processing the command, but before sending the response the
> + slave driver or application should mark the command as processed to
> + avoid processing it a second time when ReceiveStop is called. The
> + slave driver or application then calls SendData to send to queue the
> + response data for transmission. The data must remain valid in the
> + WriteBuffer until ReceiveStop is called.
> +
> + ReceiveStop is called when the stop bit is received on the I2C bus.
> + The slave driver or application starts processing the command if an
> + command data is pending in the slave driver's or application's buffer.
> + The BytesSent value is a hint to the slave driver or application as
> + to how much data was returned to the I2C master. If the controller
> + does not provide this level of support then this value is set to zero.
> +
> + @param[in] This Address of an EFI_I2C_SLAVE_PROTOCOL
> + structure
> + @param[in] SlaveAddress Slave address for the I2C controller
> + @param[in] Context Address of a context structure for use when
> + calling ReceiveData or ReceiveStop
> + @param[in] ReceiveData Called by the I2C port driver as data bytes
> + are received from the master. Response status
> + indicates if the byte is ACKed or NACKed. When
> + data is passed back a byte at a time, the port
> + driver must hold the clock until this callback
> + returns.
> + @param[in] ReceiveStart Called when the I2C controller receives a start
> bit.
> + @param[in] ReceiveStop Called after all of the data bytes are
> + received.
> +
> + @retval EFI_SUCCESS Slave operation is enabled on the controller.
> + @retval EFI_UNSUPPORTED The controller does not support this
> frequency.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_I2C_SLAVE_ENABLE) (
> + IN CONST EFI_I2C_SLAVE_PROTOCOL *This,
> + IN UINT32 SlaveAddress,
> + IN VOID *Context,
> + IN EFI_I2C_SLAVE_RECEIVE_DATA ReceiveData,
> + IN EFI_I2C_SLAVE_RECEIVE_START ReceiveStart,
> + IN EFI_I2C_SLAVE_RECEIVE_STOP ReceiveStop
> + );
> +
> +/**
> + Send data to the I2C master.
> +
> + Port drivers may implement this as a blocking or non-blocking call.
> + The data in the write buffer must remain valid until ReceiveStop or
> + ReceiveStart is called indicating that the I2C master has terminated
> + the transfer.
> +
> + @param[in] This Address of an EFI_I2C_SLAVE_PROTOCOL
> + structure
> + @param[in] WriteBytes Number of bytes to write
> + @param[in] WriteBuffer Buffer containing the data to send
> +
> + @retval EFI_SUCCESS Data waiting for master access.
> + @retval EFI_INVALID_PARAMETER WriteBuffer is NULL or WriteBytes
> + is zero.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_I2C_SLAVE_SEND) (
> + IN CONST EFI_I2C_SLAVE_PROTOCOL *This,
> + IN UINTN WriteBytes,
> + IN CONST UINT8 *WriteBuffer
> + );
> +
> +///
> +/// I2C slave protocol
> +///
> +/// The port driver publishes this protocol when slave mode is
> +/// supported by the controller.
> +///
> +struct _EFI_I2C_SLAVE_PROTOCOL {
> + ///
> + /// Enable or disable I2C slave operation
> + ///
> + EFI_I2C_SLAVE_ENABLE SlaveEnable;
> +
> + ///
> + /// Send data to the I2C master
> + ///
> + EFI_I2C_SLAVE_SEND SendData;
> +};
> +
> +///
> +/// GUID for the EFI_I2C_SLAVE_PROTOCOL
> +///
> +extern EFI_GUID gEfiI2cSlaveProtocolGuid;
> +
> +#endif // __I2C_SLAVE_H__
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h
> new file mode 100644
> index 0000000000..62d026f133
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h
> @@ -0,0 +1,92 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + LpcWpc83667Policy.h
> +
> +Abstract:
> +
> + Protocol used for WPC83627 Policy definition.
> +-------------------------------------------------------------------------------
> + Rev Date<MM/DD/YYYY> Name Description
> + -------------------------------------------------------------------------------
> + R01 < 4/22/2011> LB Update driver for Sio83627UGH support.
> + -------------------------------------------------------------------------------
> +**/
> +
> +#ifndef _WPC83627_POLICY_PROTOCOL_H_
> +#define _WPC83627_POLICY_PROTOCOL_H_
> +
> +EFI_FORWARD_DECLARATION (EFI_WPC83627_POLICY_PROTOCOL);
> +
> +#define EFI_WPC83627_POLICY_PROTOCOL_GUID \
> + { \
> + 0xd3ecc567, 0x9fd5, 0x44c1, 0x86, 0xcf, 0x5d, 0xa7, 0xa2, 0x4f, 0x4b, 0x5d
> \
> + }
> +
> +#define EFI_WPC83627_COM1_ENABLE 0x01
> +#define EFI_WPC83627_COM2_ENABLE 0x01
> +
> +#define EFI_WPC83627_COM3_ENABLE 0x01
> +#define EFI_WPC83627_COM4_ENABLE 0x01
> +
> +#define EFI_WPC83627_LPT1_ENABLE 0x01
> +#define EFI_WPC83627_LPT1_ENABLE 0x01
> +#define EFI_WPC83627_FDD_ENABLE 0x01
> +#define EFI_WPC83627_FDD_WRITE_ENABLE 0x01
> +#define EFI_WPC83627_PS2_KBC_ENABLE 0x01
> +#define EFI_WPC83627_ECIR_ENABLE 0x01
> +
> +#define EFI_WPC83627_COM1_DISABLE 0x00
> +#define EFI_WPC83627_COM2_DISABLE 0x00
> +
> +#define EFI_WPC83627_COM3_DISABLE 0x00
> +#define EFI_WPC83627_COM4_DISABLE 0x00
> +
> +#define EFI_WPC83627_LPT1_DISABLE 0x00
> +#define EFI_WPC83627_FDD_DISABLE 0x00
> +#define EFI_WPC83627_FDD_WRITE_PROTECT 0x00
> +#define EFI_WPC83627_PS2_KBC_DISABLE 0x00
> +#define EFI_WPC83627_ECIR_DISABLE 0x00
> +#define EFI_WPC83627_RESERVED_DEFAULT 0x00
> +
> +typedef struct {
> + UINT16 Com1 :1; // 0 = Disable, 1 = Enable
> + UINT16 Lpt1 :1; // 0 = Disable, 1 = Enable
> + UINT16 Floppy :1; // 0 = Disable, 1 = Enable
> + UINT16 FloppyWriteProtect :1; // 0 = Write Protect, 1 = Write Enable
> + UINT16 Port80 :1; // 0 = Disable, 1 = Enable
> + UINT16 CIR :1; // CIR enable or disable
> + UINT16 Ps2Keyboard :1; // 0 = Disable, 1 = Enable
> + UINT16 Ps2Mouse :1; // 0 = Disable, 1 = Enable
> + UINT16 Com2 :1; // 0 = Disable, 1 = Enable
> +
> + UINT16 Com3 :1; // 0 = Disable, 1 = Enable
> + UINT16 Com4 :1; // 0 = Disable, 1 = Enable
> +
> + UINT16 Dac :1; // 0 = Disable, 1 = Enable
> + UINT16 Rsvd :6;
> +} EFI_WPC83627_DEVICE_ENABLES;
> +
> +typedef enum {
> + LptModeOutput,
> + LptModeBiDirectional,
> + LptModeEpp,
> + LptModeEcp
> +} EFI_LPT_MODE;
> +
> +typedef struct _EFI_WPC83627_POLICY_PROTOCOL {
> + EFI_WPC83627_DEVICE_ENABLES DeviceEnables;
> + EFI_LPT_MODE LptMode;
> +} EFI_WPC83627_POLICY_PROTOCOL;
> +
> +extern EFI_GUID gEfiLpcWpc83627PolicyProtocolGuid;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h
> new file mode 100644
> index 0000000000..1b2459e54a
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h
> @@ -0,0 +1,55 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + LpcWpce791Policy.h
> +
> +Abstract:
> +
> + Protocol used for WPCE791 Policy definition.
> +
> +**/
> +
> +#ifndef _WPCE791_POLICY_PROTOCOL_H_
> +#define _WPCE791_POLICY_PROTOCOL_H_
> +
> +
> +#define EFI_WPCE791_POLICY_PROTOCOL_GUID \
> + { \
> + 0xab2bee2f, 0xc1a6, 0x4399, 0x85, 0x3d, 0xc0, 0x7c, 0x77, 0x4f, 0xfd, 0xd \
> + }
> +
> +#define EFI_WPCE791_PS2_KEYBOARD_ENABLE 0x01
> +#define EFI_WPCE791_PS2_KEYBOARD_DISABLE 0x00
> +
> +#define EFI_WPCE791_PS2_MOUSE_ENABLE 0x01
> +#define EFI_WPCE791_PS2_MOUSE_DISABLE 0x00
> +
> +typedef struct {
> + UINT16 Com1 :1; // 0 = Disable, 1 = Enable
> + UINT16 Lpt1 :1; // 0 = Disable, 1 = Enable
> + UINT16 Floppy :1; // 0 = Disable, 1 = Enable
> + UINT16 FloppyWriteProtect :1; // 0 = Write Protect, 1 = Write Enable
> + UINT16 Port80 :1; // 0 = Disable, 1 = Enable
> + UINT16 CIR :1; // CIR enable or disable
> + UINT16 Ps2Keyboard :1; // 0 = Disable, 1 = Enable
> + UINT16 Ps2Mouse :1; // 0 = Disable, 1 = Enable
> + UINT16 Com2 :1; // 0 = Disable, 1 = Enable
> + UINT16 Dac :1; // 0 = Disable, 1 = Enable
> + UINT16 Rsvd :6;
> +} EFI_WPCE791_DEVICE_ENABLES;
> +
> +typedef struct _EFI_WPCE791_POLICY_PROTOCOL {
> + EFI_WPCE791_DEVICE_ENABLES DeviceEnables;
> +} EFI_WPCE791_POLICY_PROTOCOL;
> +
> +extern EFI_GUID gEfiLpcWpce791PolicyProtocolGuid;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h
> new file mode 100644
> index 0000000000..3c0eb5201a
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h
> @@ -0,0 +1,84 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef __MMIO_DEVICE_H__
> +#define __MMIO_DEVICE_H__
> +
> +//
> +// Protocol to define for the MMIO device
> +//
> +typedef struct {
> + //
> + // Address of a GUID
> + //
> + EFI_GUID *Guid;
> +
> + //
> + // Context for the protocol
> + //
> + VOID *Context;
> +} EFI_MMIO_DEVICE_PROTOCOL_ITEM;
> +
> +
> +typedef struct _EFI_MMIO_DEVICE_PROTOCOL
> EFI_MMIO_DEVICE_PROTOCOL;
> +
> +//
> +// The MMIO device protocol defines a memory mapped I/O device
> +// for use by the system.
> +//
> +struct _EFI_MMIO_DEVICE_PROTOCOL {
> + //
> + // Pointer to an ACPI_EXTENDED_HID_DEVICE_PATH structure
> + // containing HID/HidStr and CID/CidStr values.
> + //
> + // See the note below associated with the UnitIdentification
> + // field.
> + //
> + CONST ACPI_EXTENDED_HID_DEVICE_PATH *AcpiPath;
> +
> + //
> + // Allow the use of a shared template for the AcpiPath.
> + //
> + // If this value is non-zero UID value then the AcpiPath must
> + // be a template which contains only the HID/HidStr and CID/CidStr
> + // values. The UID/UidStr values in the AcpiPath must be zero!
> + //
> + // If this value is zero then the AcpiPath is not shared and
> + // must contain either a non-zero UID value or a UidStr value.
> + //
> + UINT32 UnitIdentification;
> +
> + //
> + // Hardware revision - ACPI _HRV value
> + //
> + UINT32 HardwareRevision;
> +
> + //
> + // Pointer to a data structure containing the controller
> + // resources and configuration. At a minimum this points
> + // to an EFI_PHYSICAL_ADDRESS for the base address of the
> + // MMIO device.
> + //
> + CONST VOID *DriverResources;
> +
> + //
> + // Number of protocols in the array
> + //
> + UINTN ProtocolCount;
> +
> + //
> + // List of protocols to define
> + //
> + CONST EFI_MMIO_DEVICE_PROTOCOL_ITEM *ProtocolArray;
> +};
> +
> +extern EFI_GUID gEfiMmioDeviceProtocolGuid;
> +
> +#endif // __MMIO_DEVICE_H__
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/Observable.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/Observable.h
> new file mode 100644
> index 0000000000..bc5571e6d5
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/Observable.h
> @@ -0,0 +1,186 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + Observable.h
> +
> +Abstract:
> +
> + Interface and GUID definitions for Observable protocol.
> +
> +**/
> +
> +#ifndef _OBSERVABLE_PROTOCOL_H_
> +#define _OBSERVABLE_PROTOCOL_H_
> +
> +//
> +// GUID Definitions
> +//
> +#define OBSERVABLE_PROTOCOL_GUID \
> + { \
> + 0xe227c522, 0xd5fe, 0x4a53, 0x87, 0xb1, 0x0f, 0xbe, 0x57, 0x0f, 0x98, 0xe9
> \
> + }
> +
> +extern EFI_GUID gObservableProtocolGuid;
> +
> +typedef struct _OBS_OBSERVABLE_PROTOCOL
> OBS_OBSERVABLE_PROTOCOL;
> +
> +//
> +// Interface Definitions
> +//
> +
> +/**
> + Remove all observables.
> +
> + Remove all observable guids and all interfaces subscribed to them.
> +
> + @param VOID No Parameters.
> +
> + @return EFI_SUCCESS Successfully removed all observables and
> subscribed interfaces.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *OBS_REMOVE_ALL_OBSERVABLES) (
> + VOID
> + );
> +
> +/**
> + Interface for notification functions.
> +
> + Functions that are to be used as callbacks must inherit this interface in
> order to be used properly.
> +
> + @param VOID* Data Parameter context to be passed to the notification
> function.
> +
> + @return EFI_STATUS Varies depending on implementation.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *OBS_CALLBACK) (
> + IN OUT VOID* Data
> + );
> +
> +/**
> + Subscribe an interface with an observable guid.
> +
> + Use this to register a callback function with a guid. The function provided
> by CallbackInterface will be executed
> + whenever the appropriate observable instance specified by
> ReferenceGuid calls Publish.
> +
> + @param EFI_GUID ReferenceGuid The observable guid that
> the callback interface will subscribe to.
> + OBS_NOTIFY_INTERFACE CallbackInterface A pointer to the
> function that is subscribing to the observable.
> +
> + @return EFI_SUCCESS Successfully subscribed the interface to the
> observable guid.
> + EFI_NOT_FOUND No match could be found between the provided
> guid and existing observables.
> + EFI_OUT_OF_RESOURCES Could not subscribe to this observer due to
> resource limitations.
> + EFI_INVALID_PARAMETER Interface is already subscribed to this
> observer.
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *OBS_SUBSCRIBE) (
> + IN EFI_GUID ReferenceGuid,
> + IN OBS_CALLBACK CallbackInterface
> + );
> +
> +/**
> + Unsubscribe an interface with an observable guid.
> +
> + Use this to remove an interface from the callback list associated with an
> observable guid.
> +
> + @param EFI_GUID ReferenceGuid The observable guid to
> unsubscribe the interface from.
> + OBS_NOTIFY_INTERFACE NotifyCallback A pointer to the interface
> that is being unsubscribed.
> +
> + @return EFI_SUCCESS Successfully unsubscribed the interface from
> the observable guid.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *OBS_UNSUBSCRIBE) (
> + IN EFI_GUID ReferenceGuid,
> + IN OBS_CALLBACK CallbackInterface
> + );
> +
> +/**
> + Notify observing functions.
> +
> + Use this to notify all functions who are subscribed to the guid specified by
> ReferenceGuid.
> +
> + @param EFI_GUID ReferenceGuid The observable guid that
> contains the the list of interfaces to be notified.
> + VOID* Data Parameter context to be passed to the
> notification function.
> +
> + @return EFI_SUCCESS Successfully notified all observers listening to
> this guid.
> + EFI_NOT_FOUND No match could be found between the provided
> guid and existing observables.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *OBS_PUBLISH) (
> + IN EFI_GUID ReferenceGuid,
> + IN OUT VOID* Data
> + );
> +
> +/**
> + Creates a new observable.
> +
> + Create a new observable that can be observed with the use of Subscribe
> function.
> +
> + @param EFI_GUID ReferenceGuid The observable guid to add.
> +
> + @return EFI_SUCCESS Successfully added observable.
> + EFI_INVALID_PARAMETER Observable already exists.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *OBS_ADD_OBSERVABLE) (
> + IN EFI_GUID ReferenceGuid
> + );
> +
> +/**
> + Remove an observable.
> +
> + Remove an observable so that it can no longer be subscribed to. In
> addition, unsubscribe any functions
> + that are subscribed to this guid.
> +
> + @param EFI_GUID ReferenceGuid The observable guid to remove.
> +
> + @return EFI_SUCCESS Successfully removed observable.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *OBS_REMOVE_OBSERVABLE) (
> + IN EFI_GUID ReferenceGuid
> + );
> +
> +//
> +// Protocol Definitions
> +//
> +typedef struct _OBS_LEAF {
> + OBS_CALLBACK Observer;
> + struct _OBS_LEAF* Next;
> +} OBS_LEAF;
> +
> +typedef struct _OBS_TREE {
> + EFI_GUID ObservableGuid;
> + OBS_LEAF* Leaf;
> + struct _OBS_TREE* Next;
> +} OBS_TREE;
> +
> +struct _OBS_OBSERVABLE_PROTOCOL {
> + OBS_ADD_OBSERVABLE AddObservable;
> + OBS_REMOVE_OBSERVABLE RemoveObservable;
> + OBS_SUBSCRIBE Subscribe;
> + OBS_UNSUBSCRIBE Unsubscribe;
> + OBS_PUBLISH Publish;
> + OBS_REMOVE_ALL_OBSERVABLES RemoveAllObservables;
> +} ;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h
> new file mode 100644
> index 0000000000..ef2ad3d558
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h
> @@ -0,0 +1,68 @@
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +--*/
> +
> +/** @file
> +**/
> +
> +#ifndef _PLATFORM_GOP_POLICY_PROTOCOL_H_
> +#define _PLATFORM_GOP_POLICY_PROTOCOL_H_
> +
> +#define EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID \
> + { 0xec2e931b, 0x3281, 0x48a5, 0x81, 0x7, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d }
> +
> +#define EFI_BMP_IMAGE_GUID \
> + { 0x878AC2CC, 0x5343, 0x46F2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56,
> 0xBA }
> +
> +#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01 0x01
> +#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_02 x0222
> +
> +#pragma pack(1)
> +
> +typedef enum {
> + LidClosed,
> + LidOpen,
> + LidStatusMax
> +} LID_STATUS;
> +
> +typedef enum {
> + Docked,
> + UnDocked,
> + DockStatusMax
> +} DOCK_STATUS;
> +
> +typedef
> +EFI_STATUS
> +(EFIAPI *GET_PLATFORM_LID_STATUS) (
> + OUT LID_STATUS *CurrentLidStatus
> +);
> +
> +typedef
> +EFI_STATUS
> +(EFIAPI *GET_VBT_DATA) (
> + OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
> + OUT UINT32 *VbtSize
> +);
> +
> +#pragma pack()
> +
> +typedef struct _PLATFORM_GOP_POLICY_PROTOCOL {
> + UINT32 Revision;
> + GET_PLATFORM_LID_STATUS GetPlatformLidStatus;
> + GET_VBT_DATA GetVbtData;
> +} PLATFORM_GOP_POLICY_PROTOCOL;
> +
> +//
> +// Extern the GUID for protocol users.
> +//
> +extern EFI_GUID gPlatformGOPPolicyGuid;
> +
> +extern EFI_GUID gBmpImageGuid;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h
> new file mode 100644
> index 0000000000..a8b6900d16
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h
> @@ -0,0 +1,43 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + PlatformIdeInit.h
> +
> +Abstract:
> +
> + EFI Platform Ide Init Protocol
> +
> +Revision History
> +
> +**/
> +
> +#ifndef _EFI_PLATFORM_IDE_INIT_H_
> +#define _EFI_PLATFORM_IDE_INIT_H_
> +
> +//
> +// Global ID for the IDE Platform Protocol
> +//
> +#define EFI_PLATFORM_IDE_INIT_PROTOCOL_GUID \
> + { 0x377c66a3, 0x8fe7, 0x4ee8, 0x85, 0xb8, 0xf1, 0xa2, 0x82, 0x56, 0x9e,
> 0x3b };
> +
> +EFI_FORWARD_DECLARATION (EFI_PLATFORM_IDE_INIT_PROTOCOL);
> +
> +
> +//
> +// Interface structure for the Platform IDE Init Protocol
> +//
> +typedef struct _EFI_PLATFORM_IDE_INIT_PROTOCOL {
> + BOOLEAN SmartMode;
> +} EFI_PLATFORM_IDE_INIT_PROTOCOL;
> +
> +extern EFI_GUID gEfiPlatformIdeInitProtocolGuid;
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h
> new file mode 100644
> index 0000000000..6892106a36
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h
> @@ -0,0 +1,79 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + SetupMode.h
> +
> +Abstract:
> +
> + EFI Setup Mode
> +
> +Revision History
> +
> +**/
> +
> +#ifndef _EFI_SETUP_MODE_H_
> +#define _EFI_SETUP_MODE_H_
> +
> +//
> +// Global ID for the Setup Mode
> +//
> +#define EFI_PLATFORM_BOOT_MODE_GUID \
> + { 0xce845704, 0x1683, 0x4d38, 0xa4, 0xf9, 0x7d, 0xb, 0x50, 0x77, 0x57, 0x93 }
> +
> +#define EFI_NORMAL_SETUP_GUID \
> + { 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd,
> 0xa9 }
> +
> +#define EFI_NORMAL_SETUP_RESET_NAME L"Reset"
> +
> +enum {
> + //
> + // This means: "whatever reset defaults in setup does"
> + //
> + SetupDataResetNormal = 0,
> +
> + //
> + // This means: "the defaults built into the BIOS"
> + //
> + SetupDataResetStandard = 1,
> +
> + //
> + // This means: "the manufacturing mode defaults"
> + //
> + SetupDataResetManufacturing = 2,
> +
> + //
> + // This means: "the oem defaults"
> + //
> + SetupDataResetOem = 3,
> +};
> +
> +//
> +// PlatformBootMode types
> +//
> +#define PLATFORM_NORMAL_MODE 0x01
> +#define PLATFORM_SAFE_MODE 0x02
> +#define PLATFORM_RECOVERY_MODE 0x04
> +#define PLATFORM_MANUFACTURING_MODE 0x08
> +#define PLATFORM_BACK_TO_BIOS_MODE 0x10
> +
> +extern EFI_GUID gEfiPlatformBootModeGuid;
> +extern EFI_GUID gEfiNormalSetupGuid;
> +extern CHAR16 gEfiNormalSetupName[];
> +extern CHAR16 gEfiInSetupName[];
> +extern CHAR16 gEfiSystemPasswordName[];
> +
> +typedef struct {
> + EFI_GUID SetupGuid;
> + CHAR16 SetupName[0x20]; // Maximum "Setup" Name
> + UINT32 PlatformBootMode;
> +} EFI_PLATFORM_SETUP_ID;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.
> h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.
> h
> new file mode 100644
> index 0000000000..ac051d1759
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.
> h
> @@ -0,0 +1,47 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + SmbiosSlotPopulation.h
> +
> +Abstract:
> +
> + EFI SMBIOS slot structure control code.
> +
> +GUID:
> + {EF7BF7D6-F8FF-4a76-8247-C0D0D1CC49C0}
> + 0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0
> +
> +Revision History
> +
> +**/
> +
> +#ifndef _EFI_SMBIOS_SLOT_POPULATION_H_
> +#define _EFI_SMBIOS_SLOT_POPULATION_H_
> +
> +//
> +// Slot Population Protocol GUID
> +//
> +#define EFI_SMBIOS_SLOT_POPULATION_GUID \
> + { 0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 }
> +
> +typedef struct {
> + UINT16 SmbiosSlotId; // SMBIOS Slot ID
> + BOOLEAN InUse; // Does the slot have a card in it
> + BOOLEAN Disabled; // Should the slot information be in SMBIOS
> +} EFI_SMBIOS_SLOT_ENTRY;
> +
> +typedef struct {
> + UINT32 NumberOfEntries;
> + EFI_SMBIOS_SLOT_ENTRY *SlotEntries;
> +} EFI_SMBIOS_SLOT_POPULATION_INFO;
> +
> +extern EFI_GUID gEfiSmbiosSlotPopulationGuid;
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/Speaker.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/Speaker.h
> new file mode 100644
> index 0000000000..9bffcad24e
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/Speaker.h
> @@ -0,0 +1,65 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + Speaker.h
> +
> +Abstract:
> +
> + EFI Speaker Interface Protocol
> +
> +Revision History
> +
> +**/
> +
> +#ifndef _EFI_SPEAKER_H
> +#define _EFI_SPEAKER_H
> +
> +//
> +// Global Id for Speaker Interface
> +//
> +#define EFI_SPEAKER_INTERFACE_PROTOCOL_GUID \
> + { \
> + 0x400b4476, 0x3081, 0x11d6, 0x87, 0xed, 0x00, 0x06, 0x29, 0x45, 0xc3,
> 0xb9 \
> + }
> +
> +typedef struct _EFI_SPEAKER_IF_PROTOCOL EFI_SPEAKER_IF_PROTOCOL;
> +
> +//
> +// Beep Code
> +//
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_GENERATE_BEEP) (
> + IN EFI_SPEAKER_IF_PROTOCOL * This,
> + IN UINTN NumberOfBeep,
> + IN UINTN BeepDuration,
> + IN UINTN TimeInterval
> + );
> +
> +//
> +// Set Frequency
> +//
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_SPEAKER_SET_FREQUENCY) (
> + IN EFI_SPEAKER_IF_PROTOCOL * This,
> + IN UINT16 Frequency
> + );
> +
> +//
> +// Protocol definition
> +//
> +struct _EFI_SPEAKER_IF_PROTOCOL {
> + EFI_SPEAKER_SET_FREQUENCY SetSpeakerToneFrequency;
> + EFI_GENERATE_BEEP GenerateBeep;
> +} ;
> +
> +extern EFI_GUID gEfiSpeakerInterfaceProtocolGuid;
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h
> new file mode 100644
> index 0000000000..bda47c359d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h
> @@ -0,0 +1,67 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + TcoReset.h
> +
> +Abstract:
> +
> + Protocol to communicate with ICH TCO.
> +
> +GUID Info:
> + {A6A79162-E325-4c30-BCC3-59373064EFB3}
> + 0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3);
> +
> +
> +--*/
> +
> +#ifndef _TCO_RESET_H_
> +#define _TCO_RESET_H_
> +
> +
> +#define EFI_TCO_RESET_PROTOCOL_GUID \
> + {0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3}
> +
> +typedef struct _EFI_TCO_RESET_PROTOCOL EFI_TCO_RESET_PROTOCOL;
> +
> +/**
> + Enables the TCO timer to reset the system in case of a system hang. This is
> + used when writing the clock registers.
> +
> + @param[in] RcrbGcsSaveValue This is the value of the RCRB GCS register
> before it is
> + changed by this procedure. This will be used to restore
> + the settings of this register in PpiDisableTcoReset.
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET) (
> + IN UINT32 *RcrbGcsSaveValue
> + );
> +
> +/**
> + Disables the TCO timer. This is used after writing the clock registers.
> +
> + @param[in] RcrbGcsRestoreValue Value saved in PpiEnableTcoReset so
> that it can
> + restored.
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET) (
> + OUT UINT32 RcrbGcsRestoreValue
> + );
> +
> +typedef struct _EFI_TCO_RESET_PROTOCOL {
> + EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET EnableTcoReset;
> + EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET DisableTcoReset;
> +} EFI_TCO_RESET_PROTOCOL;
> +
> +extern EFI_GUID gEfiTcoResetProtocolGuid;
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h
> new file mode 100644
> index 0000000000..415e53daf2
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h
> @@ -0,0 +1,136 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + Tpm.h
> +
> +Abstract:
> +
> +
> +--*/
> +
> +#ifndef __EFI_TPM_MP_DRIVER_PROTOCOL_H__
> +#define __EFI_TPM_MP_DRIVER_PROTOCOL_H__
> +
> +
> +#define EFI_TPM_MP_DRIVER_PROTOCOL_GUID \
> + { 0xde161cfe, 0x1e60, 0x42a1, 0x8c, 0xc3, 0xee, 0x7e, 0xf0, 0x73, 0x52,
> 0x12 }
> +
> +
> +EFI_FORWARD_DECLARATION (EFI_TPM_MP_DRIVER_PROTOCOL);
> +
> +#define TPM_DRIVER_STATUS 0
> +#define TPM_DEVICE_STATUS 1
> +
> +#define TPM_DRIVER_OK 0
> +#define TPM_DRIVER_FAILED 1
> +#define TPM_DRIVER_NOT_OPENED 2
> +#define TPM_DEVICE_OK 0
> +#define TPM_DEVICE_UNRECOVERABLE 1
> +#define TPM_DEVICE_RECOVERABLE 2
> +#define TPM_DEVICE_NOT_FOUND 3
> +
> +//
> +// Prototypes for the TPM MP Driver Protocol
> +//
> +
> +/**
> + This service Open the TPM interface
> +
> + @param[in] This A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL.
> +
> + @retval EFI_SUCCESS Operation completed successfully
> + @retval EFI_DEVICE_ERROR The command was unsuccessful
> + @retval EFI_NOT_FOUND The component was not running
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_TPM_MP_INIT) (
> + IN EFI_TPM_MP_DRIVER_PROTOCOL *This
> + );
> +
> +/**
> + This service close the TPM interface and deactivate TPM
> +
> + @param[in] This A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL.
> +
> + @retval EFI_SUCCESS Operation completed successfully
> + @retval EFI_DEVICE_ERROR The command was unsuccessful
> + @retval EFI_NOT_FOUND The component was not running
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_TPM_MP_CLOSE) (
> + IN EFI_TPM_MP_DRIVER_PROTOCOL *This
> + );
> +
> +/**
> + This service get the current status infomation of TPM
> +
> + @param[in] This A pointer to the
> EFI_TPM_MP_DRIVER_PROTOCOL.
> + @param[in] ReqStatusType Requested type of status information,
> driver or device.
> + @param[in] Status Pointer to the returned status.
> +
> + @retval EFI_SUCCESS Operation completed successfully
> + @retval EFI_DEVICE_ERROR The command was unsuccessful
> + @retval EFI_INVALID_PARAMETER One or more of the parameters are
> incorrect
> + @retval EFI_BUFFER_TOO_SMALL The receive buffer is too small
> + @retval EFI_NOT_FOUND The component was not running
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_TPM_MP_GET_STATUS_INFO) (
> + IN EFI_TPM_MP_DRIVER_PROTOCOL *This,
> + IN UINT32 ReqStatusType,
> + OUT UINT32 *Status
> + );
> +
> +/**
> + This service transmit data to the TPM and get response from TPM
> +
> + @param[in] This A pointer to the
> EFI_TPM_MP_DRIVER_PROTOCOL.
> + @param[in] TransmitBuf Pointer to a buffer containing TPM
> transmit data.
> + @param[in] TransmitBufLen Sizeof TPM input buffer in bytes.
> + @param[in] ReceiveBuf Pointer to a buffer containing TPM
> receive data.
> + @param[in] ReceiveBufLen On input, size of TPM receive buffer in
> bytes.
> + On output, number of bytes written.
> +
> + @retval EFI_SUCCESS Operation completed successfully
> + @retval EFI_DEVICE_ERROR The command was unsuccessful
> + @retval EFI_INVALID_PARAMETER One or more of the parameters are
> incorrect
> + @retval EFI_BUFFER_TOO_SMALL The receive buffer is too small
> + @retval EFI_NOT_FOUND The component was not running
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_TPM_MP_TRANSMIT) (
> + IN EFI_TPM_MP_DRIVER_PROTOCOL *This,
> + IN UINT8 *TransmitBuffer,
> + IN UINT32 TransmitBufferLen,
> + OUT UINT8 *ReceiveBuf,
> + IN OUT UINT32 *ReceiveBufLen
> + );
> +
> +
> +
> +typedef struct _EFI_TPM_MP_DRIVER_PROTOCOL {
> + EFI_TPM_MP_INIT Init;
> + EFI_TPM_MP_CLOSE Close;
> + EFI_TPM_MP_GET_STATUS_INFO GetStatusInfo;
> + EFI_TPM_MP_TRANSMIT Transmit;
> +} EFI_TPM_MP_DRIVER_PROTOCOL;
> +
> +extern EFI_GUID gEfiTpmMpDriverProtocolGuid;
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h
> new file mode 100644
> index 0000000000..16e9f9c6bc
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h
> @@ -0,0 +1,126 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> + UsbPolicy.h
> +
> +Abstract:
> +
> +--*/
> +
> +#ifndef _USB_POLICY_H_
> +#define _USB_POLICY_H_
> +
> +EFI_FORWARD_DECLARATION (EFI_USB_POLICY_PROTOCOL);
> +
> +#define USB_POLICY_GUID \
> + {\
> + 0xf617b358, 0x12cf, 0x414a, 0xa0, 0x69, 0x60, 0x67, 0x7b, 0xda, 0x13,
> 0xb4\
> + }
> +
> +#define TIANO_CODE_BASE 0x00
> +#define ICBD_CODE_BASE 0x01
> +
> +#define ATUO_TYPE 0x00
> +#define USB_FDD_TYPE 0x01
> +#define HDD_TYPE 0x02
> +#define ZIP_TYPE 0x03
> +#define CDROM_TYPE 0x04
> +#define SIZE_TYPE 0x05
> +
> +#define ZIP_FDD 0x80
> +
> +#define FDD_EMULATION 0x00
> +#define HDD_EMULATION 0x01
> +
> +#define HIGH_SPEED 0x00
> +#define FULL_SPEED 0x01
> +#define SUPER_SPEED 0x02
> +
> +#define LEGACY_KB_EN 0x01
> +#define LEGACY_KB_DIS 0x00
> +#define LEGACY_MS_EN 0x01
> +#define LEGACY_MS_DIS 0x00
> +#define LEGACY_USB_EN 0x00
> +#define LEGACY_USB_DIS 0x01
> +#define LEGACY_FREE_SUPP 0x01
> +#define LEGACY_FREE_UN_SUPP 0x00
> +#define LEGACY_PERIOD_SUPP 0x01
> +#define LEGACY_PERIOD_UN_SUPP 0x00
> +
> +#define LEGACY_USB_TIME_TUE_ENABLE 0x01
> +#define LEGACY_USB_TIME_TUE_DISABLE 0x00
> +#define USB_HAVE_HUB_INTERNEL 0x01
> +#define USB_NOT_HAVE_HUB_INTERNEL 0x00
> +
> +#define USB_POLICY_PROTOCOL_REVISION_1 1
> +#define USB_POLICY_PROTOCOL_REVISION_2 2
> +
> +#ifndef __GNUC__
> +#pragma warning ( disable : 4306 )
> +#pragma warning ( disable : 4054 )
> +#endif
> +
> +#define GET_USB_CFG (UsbCfg);\
> + do{\
> + UINT16 *pSegOfEbda;\
> + UINT32 mToEbda;\
> + pSegOfEbda = (UINT16 *)(UINTN)0x40E;\
> + mToEbda = (UINT32)(((UINTN)(*pSegOfEbda) << 4) + 0x80);\
> + UsbCfg = (USB_CFG *)(UINTN)mToEbda;\
> + }while(0);
> +
> +#pragma pack(1)
> +typedef struct {
> + UINT8 HasUSBKeyboard:1;
> + UINT8 HasUSBMouse:1;
> + UINT8 LegacyFreeSupport:1;
> + UINT8 UsbOperationMode:1;
> + UINT8 LegacyKBEnable:1;
> + UINT8 LegacyMSEnable:1;
> + UINT8 USBPeriodSupport:1;
> + UINT8 Reserved:1;
> +} USB_DEVICE_INFOR;
> +
> +typedef struct {
> + UINT8 Codebase;
> + UINT8 USBHDDForceType;
> + UINT8 Configurated;
> + UINT8 LpcAcpiBase;
> + UINT8 AcpiTimerReg;
> + UINT8 Reserved1[0x01];
> + UINT8 LegacyUsbEnable;
> + USB_DEVICE_INFOR UsbDeviceInfor;
> + UINT16 UsbEmulationSize;
> + UINT8 Reserved2[0x06];
> +} USB_CFG;
> +#pragma pack()
> +
> +typedef struct _EFI_USB_POLICY_PROTOCOL{
> + UINT8 Version;
> + UINT8 UsbMassStorageEmulationType; // 1: FDD_Type; 2: HDD_Type;
> other:Auto_Type*
> + UINT8 UsbOperationMode; // 0: High_Speed; 1: Full_Speed;
> + UINT8 LegacyKBEnable; // 0: Disabled; 1: Enabled*
> + UINT8 LegacyMSEnable; // 0: Disabled; 1: Enabled*
> + UINT8 USBPeriodSupport; // 0; Unsupport; 1: Support
> + UINT8 LegacyUsbEnable; // 1: Disabled; 0: Enabled*
> + UINT8 LegacyFreeSupport; // 0: Unsupport; 1: Support
> + UINT8 CodeBase;
> + UINT8 LpcAcpiBase; // 40h(default)
> + UINT8 AcpiTimerReg;
> + UINT8 UsbTimeTue;
> + UINT8 InternelHubExist; // 1: Host have internel hub on board; 0:
> No internel hub on board
> + UINT8 EnumWaitPortStableStall; // Value for wait port stable when
> enum a new dev.
> + UINT16 UsbEmulationSize; // Mbytes.
> + UINT8 UsbZipEmulationType;
> + UINT8 Reserved[3]; // Reserved fields for future expansion w/o
> protocol change
> +} EFI_USB_POLICY_PROTOCOL;
> +
> +extern EFI_GUID gUsbPolicyGuid;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h
> new file mode 100644
> index 0000000000..5c0ffa3027
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h
> @@ -0,0 +1,102 @@
> +/**
> + Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +Module Name:
> +
> + VlvPlatformPolicy.h
> +
> +Abstract:
> +
> + Interface definition details between MCH and platform drivers during DXE
> phase.
> +
> +--*/
> +
> +#ifndef _VLV_PLATFORM_POLICY_H_
> +#define _VLV_PLATFORM_POLICY_H_
> +
> +//
> +// VLV Policy provided by platform for DXE phase {5BAB88BA-E0E2-4674-
> B6AD-B812F6881CD6}
> +//
> +#define DXE_VLV_PLATFORM_POLICY_GUID \
> + {0x5bab88ba, 0xe0e2, 0x4674, 0xb6, 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c,
> 0xd6}
> +
> +//
> +// Extern the GUID for protocol users.
> +//
> +extern EFI_GUID gDxeVlvPlatformPolicyGuid;
> +
> +//
> +// Protocol revision number
> +// Any backwards compatible changes to this protocol will result in an
> update in the revision number
> +// Major changes will require publication of a new protocol
> +//
> +#define DXE_VLV_PLATFORM_POLICY_PROTOCOL_REVISION 0
> +
> +
> +typedef struct {
> + UINT8 PFITStatus;
> + UINT8 IgdTheramlSupport;
> + UINT8 ALSEnabled;
> + UINT8 LidStatus;
> +} IGD_PANEL_FEATURES;
> +
> +typedef struct {
> + UINT8 Reserved00;
> + UINT8 Reserved01;
> + UINT16 Reserved02;
> + UINT16 Reserved03;
> + UINT16 Reserved04;
> + UINT16 Reserved05;
> + UINT16 Reserved06;
> + UINT16 Reserved07;
> + UINT16 Reserved08;
> + UINT16 Reserved09;
> + UINT16 Reserved0A;
> + UINT16 Reserved0B;
> + UINT16 Reserved0C;
> + UINT16 Reserved0D;
> + UINT8 Reserved0E;
> + UINT8 Reserved0F;
> + UINT32 Reserved10;
> + UINT32 Reserved11;
> + UINT32 Reserved12;
> + UINT32 Reserved13;
> + UINT32 Reserved14;
> + UINT8 Reserved15;
> + UINT8 Reserved16;
> +} DPTF_SETTINGS;
> +
> +//
> +// MCH DXE Platform Policiy
> ==================================================
> +//
> +
> +#define NO_AUDIO 0
> +#define HD_AUDIO 1
> +#define LPE_AUDIO 2
> +
> +typedef struct _DXE_VLV_PLATFORM_POLICY_PROTOCOL {
> + UINT8 Revision;
> + IGD_PANEL_FEATURES IgdPanelFeatures;
> + DPTF_SETTINGS Reserved;
> + UINT8 GraphicReserve00;
> + UINT8 GraphicsPerfAnalyzers;
> + UINT8 PwmReserved00;
> + UINT8 PwmReserved01;
> + UINT8 PmSupport;
> + UINT8 GraphicReserve01;
> + UINT8 GfxPause;
> + UINT8 GraphicsFreqReq;
> + UINT8 GraphicReserve03;
> + UINT8 GraphicReserve02;
> + UINT8 GraphicReserve04;
> + UINT8 PavpMode;
> + UINT8 GraphicReserve05;
> + UINT8 UlClockGating;
> + UINT8 IdleReserve;
> + UINT8 AudioTypeSupport;
> + UINT8 GraphicReserve06;
> +} DXE_VLV_PLATFORM_POLICY_PROTOCOL;
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Include/SetupMode.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Include/SetupMode.h
> new file mode 100644
> index 0000000000..53abd1d3a6
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Include/SetupMode.h
> @@ -0,0 +1,85 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + SetupMode.h
> +
> +Abstract:
> +
> + EFI Setup Mode
> +
> +
> +
> +--*/
> +
> +#ifndef _EFI_SETUP_MODE_H_
> +#define _EFI_SETUP_MODE_H_
> +
> +//
> +// Global ID for the Setup Mode
> +//
> +#define EFI_PLATFORM_BOOT_MODE_GUID \
> + { 0xce845704, 0x1683, 0x4d38, 0xa4, 0xf9, 0x7d, 0xb, 0x50, 0x77, 0x57, 0x93 }
> +
> +#define EFI_NORMAL_SETUP_GUID \
> + { 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd,
> 0xa9 }
> +
> +#define EFI_NORMAL_SETUP_RESET_NAME L"Reset"
> +
> +enum {
> + //
> + // This means: "whatever reset defaults in setup does"
> + //
> + SetupDataResetNormal = 0,
> +
> + //
> + // This means: "the defaults built into the BIOS"
> + //
> + SetupDataResetStandard = 1,
> +
> + //
> + // This means: "the manufacturing mode defaults"
> + //
> + SetupDataResetManufacturing = 2,
> +
> + //
> + // This means: "the oem defaults"
> + //
> + SetupDataResetOem = 3,
> +};
> +
> +//
> +// PlatformBootMode types
> +//
> +#define PLATFORM_NORMAL_MODE 0x01
> +#define PLATFORM_SAFE_MODE 0x02
> +#define PLATFORM_RECOVERY_MODE 0x04
> +#define PLATFORM_MANUFACTURING_MODE 0x08
> +#define PLATFORM_BACK_TO_BIOS_MODE 0x10
> +
> +extern EFI_GUID gEfiPlatformBootModeGuid;
> +
> +#define NORMAL_SETUP_NAME L"Setup"
> +#define IN_SETUP_NAME L"InSetup"
> +#define SYSTEM_PASSWORD_NAME L"SystemPassword"
> +#define BOOT_TIME_NAME L"BootTime"
> +
> +extern EFI_GUID gEfiNormalSetupGuid;
> +extern CHAR16 gEfiNormalSetupName[];
> +extern CHAR16 gEfiInSetupName[];
> +extern CHAR16 gEfiSystemPasswordName[];
> +
> +typedef struct {
> + EFI_GUID SetupGuid;
> + CHAR16 SetupName[0x20]; // Maximum "Setup" Name
> + UINT32 PlatformBootMode;
> +} EFI_PLATFORM_SETUP_ID;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/IntelGopDepex/IntelGopDriver.depex
> b/Platform/Intel/Vlv2TbltDevicePkg/IntelGopDepex/IntelGopDriver.depex
> new file mode 100644
> index 0000000000..011f929f0a
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/IntelGopDepex/IntelGopDriver.depex
> @@ -0,0 +1 @@
> +�.�2�H�
ߊ��<]
> \ No newline at end of file
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.c
> new file mode 100644
> index 0000000000..3f0e20c7a8
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.c
> @@ -0,0 +1,337 @@
> +/*++
> +
> +Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + BiosIdLib.c
> +
> +Abstract:
> +
> + Boot service DXE BIOS ID library implementation.
> +
> + These functions in this file can be called during DXE and cannot be called
> during runtime
> + or in SMM which should use a RT or SMM library.
> +
> +--*/
> +
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +
> +#include <Library/BiosIdLib.h>
> +#include <Guid/BiosId.h>
> +#include <Protocol/FirmwareVolume2.h>
> +#include <Protocol/LoadedImage.h>
> +
> +
> +EFI_STATUS
> +GetImageFromFv (
> + IN EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv,
> + IN EFI_GUID *NameGuid,
> + IN EFI_SECTION_TYPE SectionType,
> + OUT VOID **Buffer,
> + OUT UINTN *Size
> + )
> +{
> + EFI_STATUS Status;
> + EFI_FV_FILETYPE FileType;
> + EFI_FV_FILE_ATTRIBUTES Attributes;
> + UINT32 AuthenticationStatus;
> +
> + //
> + // Read desired section content in NameGuid file
> + //
> + *Buffer = NULL;
> + *Size = 0;
> + Status = Fv->ReadSection (
> + Fv,
> + NameGuid,
> + SectionType,
> + 0,
> + Buffer,
> + Size,
> + &AuthenticationStatus
> + );
> +
> + if (EFI_ERROR (Status) && (SectionType == EFI_SECTION_TE)) {
> + //
> + // Try reading PE32 section, since the TE section does not exist
> + //
> + *Buffer = NULL;
> + *Size = 0;
> + Status = Fv->ReadSection (
> + Fv,
> + NameGuid,
> + EFI_SECTION_PE32,
> + 0,
> + Buffer,
> + Size,
> + &AuthenticationStatus
> + );
> + }
> +
> + if (EFI_ERROR (Status) &&
> + ((SectionType == EFI_SECTION_TE) || (SectionType ==
> EFI_SECTION_PE32))) {
> + //
> + // Try reading raw file, since the desired section does not exist
> + //
> + *Buffer = NULL;
> + *Size = 0;
> + Status = Fv->ReadFile (
> + Fv,
> + NameGuid,
> + Buffer,
> + Size,
> + &FileType,
> + &Attributes,
> + &AuthenticationStatus
> + );
> + }
> +
> + return Status;
> +}
> +
> +
> +EFI_STATUS
> +GetImageEx (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_GUID *NameGuid,
> + IN EFI_SECTION_TYPE SectionType,
> + OUT VOID **Buffer,
> + OUT UINTN *Size,
> + BOOLEAN WithinImageFv
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE *HandleBuffer;
> + UINTN HandleCount;
> + UINTN Index;
> + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
> +
> + EFI_FIRMWARE_VOLUME2_PROTOCOL *ImageFv;
> + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
> +
> +
> + if (ImageHandle == NULL && WithinImageFv) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Status = EFI_NOT_FOUND;
> + ImageFv = NULL;
> + if (ImageHandle != NULL) {
> + Status = gBS->HandleProtocol (
> + ImageHandle,
> + &gEfiLoadedImageProtocolGuid,
> + (VOID **) &LoadedImage
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + Status = gBS->HandleProtocol (
> + LoadedImage->DeviceHandle,
> + &gEfiFirmwareVolume2ProtocolGuid,
> + (VOID **) &ImageFv
> + );
> + if (!EFI_ERROR (Status)) {
> + Status = GetImageFromFv (ImageFv, NameGuid, SectionType, Buffer,
> Size);
> + }
> + }
> +
> + if (Status == EFI_SUCCESS || WithinImageFv) {
> + return Status;
> + }
> +
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiFirmwareVolume2ProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Find desired image in all Fvs
> + //
> + for (Index = 0; Index < HandleCount; ++Index) {
> + Status = gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gEfiFirmwareVolume2ProtocolGuid,
> + (VOID**)&Fv
> + );
> +
> + if (EFI_ERROR (Status)) {
> + gBS->FreePool(HandleBuffer);
> + return Status;
> + }
> +
> + if (ImageFv != NULL && Fv == ImageFv) {
> + continue;
> + }
> +
> + Status = GetImageFromFv (Fv, NameGuid, SectionType, Buffer, Size);
> +
> + if (!EFI_ERROR (Status)) {
> + break;
> + }
> + }
> + gBS->FreePool(HandleBuffer);
> +
> + //
> + // Not found image
> + //
> + if (Index == HandleCount) {
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function returns BIOS ID by searching HOB or FV.
> +
> + @param BiosIdImage The BIOS ID got from HOB or FV.
> +
> + @retval EFI_SUCCESS All parameters were valid and BIOS ID has been
> got.
> + @retval EFI_NOT_FOUND BiosId image is not found, and no
> parameter will be modified.
> + @retval EFI_INVALID_PARAMETER The parameter is NULL.
> +
> +**/
> +EFI_STATUS
> +GetBiosId (
> + OUT BIOS_ID_IMAGE *BiosIdImage
> + )
> +
> +{
> + EFI_STATUS Status;
> + VOID *Address = NULL;
> + UINTN Size = 0;
> +
> + DEBUG ((EFI_D_INFO, "Get BIOS ID from FV\n"));
> +
> + Status = GetImageEx (
> + NULL,
> + &gEfiBiosIdGuid,
> + EFI_SECTION_RAW,
> + &Address,
> + &Size,
> + FALSE
> + );
> +
> + if (Status == EFI_SUCCESS) {
> + //
> + // BiosId image is present in FV
> + //
> + if (Address != NULL) {
> + Size = sizeof (BIOS_ID_IMAGE);
> + gBS->CopyMem (
> + (void *) BiosIdImage,
> + Address,
> + Size
> + );
> + //
> + // GetImage () allocated buffer for Address, now clear it.
> + //
> + gBS->FreePool (Address);
> +
> + DEBUG ((EFI_D_INFO, "Get BIOS ID from FV successfully\n"));
> + DEBUG ((EFI_D_INFO, "BIOS ID: %s\n", (CHAR16 *) (&(BiosIdImage-
> >BiosIdString))));
> +
> + return EFI_SUCCESS;
> + }
> + }
> + return EFI_NOT_FOUND;
> +}
> +
> +/**
> + This function returns the Version & Release Date and Time by getting and
> converting
> + BIOS ID.
> +
> + @param BiosVersion The Bios Version out of the conversion.
> + @param BiosReleaseDate The Bios Release Date out of the conversion.
> + @param BiosReleaseTime - The Bios Release Time out of the conversion.
> +
> + @retval EFI_SUCCESS - BIOS Version & Release Date and Time have been
> got successfully.
> + @retval EFI_NOT_FOUND - BiosId image is not found, and no parameter
> will be modified.
> + @retval EFI_INVALID_PARAMETER - All the parameters are NULL.
> +
> +**/
> +EFI_STATUS
> +GetBiosVersionDateTime (
> + OUT CHAR16 *BiosVersion, OPTIONAL
> + OUT CHAR16 *BiosReleaseDate, OPTIONAL
> + OUT CHAR16 *BiosReleaseTime OPTIONAL
> + )
> +{
> + EFI_STATUS Status;
> + BIOS_ID_IMAGE BiosIdImage;
> +
> + if ((BiosVersion == NULL) && (BiosReleaseDate == NULL) &&
> (BiosReleaseTime == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Status = GetBiosId (&BiosIdImage);
> + if (EFI_ERROR (Status)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + if (BiosVersion != NULL) {
> + //
> + // Fill the BiosVersion data from the BIOS ID.
> + //
> + StrCpy (BiosVersion, (CHAR16 *) (&(BiosIdImage.BiosIdString)));
> + }
> +
> + if (BiosReleaseDate != NULL) {
> + //
> + // Fill the build timestamp date from the BIOS ID in the "MM/DD/YY"
> format.
> + //
> + BiosReleaseDate[0] = BiosIdImage.BiosIdString.TimeStamp[2];
> + BiosReleaseDate[1] = BiosIdImage.BiosIdString.TimeStamp[3];
> + BiosReleaseDate[2] = (CHAR16) ((UINT8) ('/'));
> +
> + BiosReleaseDate[3] = BiosIdImage.BiosIdString.TimeStamp[4];
> + BiosReleaseDate[4] = BiosIdImage.BiosIdString.TimeStamp[5];
> + BiosReleaseDate[5] = (CHAR16) ((UINT8) ('/'));
> +
> + //
> + // Add 20 for SMBIOS table
> + // Current Linux kernel will misjudge 09 as year 0, so using 2009 for
> SMBIOS table
> + //
> + BiosReleaseDate[6] = '2';
> + BiosReleaseDate[7] = '0';
> + BiosReleaseDate[8] = BiosIdImage.BiosIdString.TimeStamp[0];
> + BiosReleaseDate[9] = BiosIdImage.BiosIdString.TimeStamp[1];
> +
> + BiosReleaseDate[10] = (CHAR16) ((UINT8) ('\0'));
> + }
> +
> + if (BiosReleaseTime != NULL) {
> +
> + //
> + // Fill the build timestamp time from the BIOS ID in the "HH:MM" format.
> + //
> +
> + BiosReleaseTime[0] = BiosIdImage.BiosIdString.TimeStamp[6];
> + BiosReleaseTime[1] = BiosIdImage.BiosIdString.TimeStamp[7];
> + BiosReleaseTime[2] = (CHAR16) ((UINT8) (':'));
> +
> + BiosReleaseTime[3] = BiosIdImage.BiosIdString.TimeStamp[8];
> + BiosReleaseTime[4] = BiosIdImage.BiosIdString.TimeStamp[9];
> +
> + BiosReleaseTime[5] = (CHAR16) ((UINT8) ('\0'));
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.inf
> new file mode 100644
> index 0000000000..3e53680d08
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.inf
> @@ -0,0 +1,50 @@
> +#/*++
> +#
> +# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +
> +#
> +# Module Name:
> +#
> +# BiosIdLib.inf
> +#
> +# Abstract:
> +#
> +# Component description file for BIOS ID library
> +#
> +#--*/
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = BiosIdLib
> + FILE_GUID = 98546145-64F1-4d2e-814F-6BF963DB7930
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = BiosIdLib
> + PI_SPECIFICATION_VERSION = 0x0001000A
> +
> +[Sources]
> + BiosIdLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + HobLib
> +
> +[Guids]
> + gEfiBiosIdGuid
> +
> +[Protocols]
> + gEfiLoadedImageProtocolGuid
> + gEfiFirmwareVolume2ProtocolGuid
> +
> +[Depex]
> + gEfiLoadedImageProtocolGuid AND
> + gEfiFirmwareVolume2ProtocolGuid
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf
> new file mode 100644
> index 0000000000..c9f0a434ac
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf
> @@ -0,0 +1,41 @@
> +#
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +# Module Name:
> +#
> +# CpuIA32Lib.inf
> +#
> +# Abstract:
> +#
> +# Component description file for the Cpu IA32 library.
> +#
> +#--*/
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = CpuIA32Lib
> + FILE_GUID = 98546178-64F1-4d2e-814F-6BF963DB7930
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = CpuIA32Lib
> + PI_SPECIFICATION_VERSION = 0x0001000A
> +
> +[Sources]
> + EfiCpuVersion.c
> +
> +[Sources.IA32]
> + IA32/CpuIA32.c
> +
> +[Sources.X64]
> + X64/Cpu.asm
> + X64/Cpu.S
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/EfiCpuVersion.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/EfiCpuVersion.c
> new file mode 100644
> index 0000000000..935f11e871
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/EfiCpuVersion.c
> @@ -0,0 +1,70 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + EfiCpuVersion.c
> +
> +Abstract:
> +
> + Provide cpu version extract considering extended family & model ID.
> +--*/
> +
> +#include <Library/CpuIA32.h>
> +
> +/**
> + Extract CPU detail version infomation
> +
> + @param FamilyId FamilyId, including ExtendedFamilyId
> + @param Model Model, including ExtendedModel
> + @param SteppingId SteppingId
> + @param Processor Processor
> +
> +**/
> +VOID
> +EFIAPI
> +EfiCpuVersion (
> + IN OUT UINT16 *FamilyId, OPTIONAL
> + IN OUT UINT8 *Model, OPTIONAL
> + IN OUT UINT8 *SteppingId, OPTIONAL
> + IN OUT UINT8 *Processor OPTIONAL
> + )
> +
> +{
> + EFI_CPUID_REGISTER Register;
> + UINT8 TempFamilyId;
> +
> + EfiCpuid (EFI_CPUID_VERSION_INFO, &Register);
> +
> + if (SteppingId != NULL) {
> + *SteppingId = (UINT8) (Register.RegEax & 0xF);
> + }
> +
> + if (Processor != NULL) {
> + *Processor = (UINT8) ((Register.RegEax >> 12) & 0x3);
> + }
> +
> + if (Model != NULL || FamilyId != NULL) {
> + TempFamilyId = (UINT8) ((Register.RegEax >> 8) & 0xF);
> +
> + if (Model != NULL) {
> + *Model = (UINT8) ((Register.RegEax >> 4) & 0xF);
> + if (TempFamilyId == 0x6 || TempFamilyId == 0xF) {
> + *Model = (UINT8) (*Model | ((Register.RegEax >> 12) & 0xF0));
> + }
> + }
> +
> + if (FamilyId != NULL) {
> + *FamilyId = TempFamilyId;
> + if (TempFamilyId == 0xF) {
> + *FamilyId = (UINT8 ) (*FamilyId + (UINT16) ((Register.RegEax >> 20) &
> 0xFF));
> + }
> + }
> + }
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S
> new file mode 100644
> index 0000000000..ba1bd448c0
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S
> @@ -0,0 +1,223 @@
> +#
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#Module Name:
> +#
> +# CpuIA32.c
> +#
> +#Abstract:
> +#
> +#--*/
> +
> +##include "CpuIA32.h"
> +#include "EfiBind.h"
> +
> +#---------------------------------------------------------------------------
> + .586p:
> + #.MODEL flat,C
> + .code:
> +
> +#---------------------------------------------------------------------------
> +
> +.globl ASM_PFX(EfiHalt)
> +.globl ASM_PFX(EfiWbinvd)
> +.globl ASM_PFX(EfiInvd)
> +.globl ASM_PFX(EfiCpuid)
> +.globl ASM_PFX(EfiReadMsr)
> +.globl ASM_PFX(EfiWriteMsr)
> +.globl ASM_PFX(EfiReadTsc)
> +.globl ASM_PFX(EfiDisableCache)
> +.globl ASM_PFX(EfiEnableCache)
> +.globl ASM_PFX(EfiGetEflags)
> +.globl ASM_PFX(EfiDisableInterrupts)
> +.globl ASM_PFX(EfiEnableInterrupts)
> +.globl ASM_PFX(EfiCpuidExt)
> +
> +
> +#VOID
> +#EfiHalt (
> +# VOID
> +#)
> +ASM_PFX(EfiHalt):
> + hlt
> + ret
> +#EfiHalt ENDP
> +
> +#VOID
> +#EfiWbinvd (
> +# VOID
> +#)
> +ASM_PFX(EfiWbinvd):
> + wbinvd
> + ret
> +#EfiWbinvd ENDP
> +
> +#VOID
> +#EfiInvd (
> +# VOID
> +#)
> +ASM_PFX(EfiInvd):
> + invd
> + ret
> +#EfiInvd ENDP
> +
> +#VOID
> +#EfiCpuid (IN UINT32 RegisterInEax,
> +# OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
> +ASM_PFX(EfiCpuid):
> + pushl %ebp
> + movl %esp, %ebp
> + pushl %ebx
> + pushl %esi
> + pushl %edi
> + pushal
> +
> + movl 8(%ebp), %eax #RegisterInEax
> + cpuid
> + cmpl $0, 0xC(%ebp) # Reg
> + je L1
> + movl 0xC(%ebp), %edi # Reg
> +
> + movl %eax, (%edi) # Reg->RegEax
> + movl %ebx, 4(%edi) # Reg->RegEbx
> + movl %ecx, 8(%edi) # Reg->RegEcx
> + movl %edx, 0xC(%edi) # Reg->RegEdx
> +
> +L1:
> + popal
> + popl %edi
> + popl %esi
> + popl %ebx
> + popl %ebp
> +
> + ret
> +#EfiCpuid ENDP
> +
> +
> +#UINT64
> +#EfiReadMsr (
> +# IN UINT32 Index
> +# );
> +ASM_PFX(EfiReadMsr):
> + movl 4(%esp), %ecx # Index
> + rdmsr
> + ret
> +#EfiReadMsr ENDP
> +
> +#VOID
> +#EfiWriteMsr (
> +# IN UINT32 Index,
> +# IN UINT64 Value
> +# );
> +ASM_PFX(EfiWriteMsr):
> + movl 4(%esp), %ecx # Index
> + movl 8(%esp), %eax # DWORD PTR Value[0]
> + movl 0xC(%esp), %edx # DWORD PTR Value[4]
> + wrmsr
> + ret
> +#EfiWriteMsr ENDP
> +
> +#UINT64
> +#EfiReadTsc (
> +# VOID
> +# )
> +ASM_PFX(EfiReadTsc):
> + rdtsc
> + ret
> +#EfiReadTsc ENDP
> +
> +#VOID
> +#EfiDisableCache (
> +# VOID
> +#)
> +ASM_PFX(EfiDisableCache):
> + movl %cr0, %eax
> + bswapl %eax
> + andb $0x60, %al
> + cmpb $0x60, %al
> + je L2
> + movl %cr0, %eax
> + orl $0x60000000, %eax
> + movl %eax, %cr0
> + wbinvd
> +L2:
> + ret
> +#EfiDisableCache ENDP
> +
> +#VOID
> +#EfiEnableCache (
> +# VOID
> +# )
> +ASM_PFX(EfiEnableCache):
> + wbinvd
> + movl %cr0, %eax
> + andl $0x9fffffff, %eax
> + movl %eax, %cr0
> + ret
> +#EfiEnableCache ENDP
> +
> +#UINT32
> +#EfiGetEflags (
> +# VOID
> +# )
> +ASM_PFX(EfiGetEflags):
> + pushfl
> + popl %eax
> + ret
> +#EfiGetEflags ENDP
> +
> +#VOID
> +#EfiDisableInterrupts (
> +# VOID
> +# )
> +ASM_PFX(EfiDisableInterrupts):
> + cli
> + ret
> +#EfiDisableInterrupts ENDP
> +
> +#VOID
> +#EfiEnableInterrupts (
> +# VOID
> +# )
> +ASM_PFX(EfiEnableInterrupts):
> + sti
> + ret
> +#EfiEnableInterrupts ENDP
> +
> +#VOID
> +#EfiCpuidExt (
> +# IN UINT32 RegisterInEax,
> +# IN UINT32 CacheLevel,
> +# OUT EFI_CPUID_REGISTER *Regs
> +# )
> +ASM_PFX(EfiCpuidExt):
> + push %ebx
> + push %edi
> + push %esi
> + pushal
> +
> + movl 0x30(%esp), %eax # RegisterInEax
> + movl 0x34(%esp), %ecx # CacheLevel
> + cpuid
> + movl 0x38(%esp), %edi # DWORD PTR Regs
> +
> + movl %eax, (%edi) # Reg->RegEax
> + movl %ebx, 4(%edi) # Reg->RegEbx
> + movl %ecx, 8(%edi) # Reg->RegEcx
> + movl %edx, 0xC(%edi) # Reg->RegEdx
> +
> + popal
> + pop %esi
> + pop %edi
> + pop %ebx
> + ret
> +#EfiCpuidExt ENDP
> +
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.asm
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.asm
> new file mode 100644
> index 0000000000..3fdf16f8ee
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.asm
> @@ -0,0 +1,206 @@
> +;
> +; This file contains an 'Intel Sample Driver' and is
> +; licensed for Intel CPUs and chipsets under the terms of your
> +; license agreement with Intel or your vendor. This file may
> +; be modified by the user, subject to additional terms of the
> +; license agreement
> +;
> +;
> +; Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +;
>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +;
>
> +;
> +
> +;Module Name:
> +;
> +; CpuIA32.c
> +;
> +;Abstract:
> +;
> +;--*/
> +
> +;#include "CpuIA32.h"
> +
> +;---------------------------------------------------------------------------
> + .586p
> + .model flat,C
> + .code
> +
> +;---------------------------------------------------------------------------
> +;VOID
> +;EfiHalt (
> +; VOID
> +;)
> +EfiHalt PROC C PUBLIC
> + hlt
> + ret
> +EfiHalt ENDP
> +
> +;VOID
> +;EfiWbinvd (
> +; VOID
> +;)
> +EfiWbinvd PROC C PUBLIC
> + wbinvd
> + ret
> +EfiWbinvd ENDP
> +
> +;VOID
> +;EfiInvd (
> +; VOID
> +;)
> +EfiInvd PROC C PUBLIC
> + invd
> + ret
> +EfiInvd ENDP
> +
> +;VOID
> +;EfiCpuid (IN UINT32 RegisterInEax,
> +; OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
> +EfiCpuid PROC C PUBLIC
> + push ebp
> + mov ebp, esp
> + push ebx
> + push esi
> + push edi
> + pushad
> +
> + mov eax, dword ptr[ebp + 8] ;egisterInEax
> + cpuid
> + cmp dword ptr[ebp + 0Ch], 0 ; Reg
> + je @F
> + mov edi,dword ptr [ebp+0Ch] ; Reg
> +
> + mov dword ptr [edi],eax ; Reg->RegEax
> + mov dword ptr [edi+4],ebx ; Reg->RegEbx
> + mov dword ptr [edi+8],ecx ; Reg->RegEcx
> + mov dword ptr [edi+0Ch],edx ; Reg->RegEdx
> +
> +@@:
> + popad
> + pop edi
> + pop esi
> + pop ebx
> + pop ebp
> +
> + ret
> +EfiCpuid ENDP
> +
> +
> +;UINT64
> +;EfiReadMsr (
> +; IN UINT32 Index
> +; );
> +EfiReadMsr PROC C PUBLIC
> + mov ecx, dword ptr [esp + 4]; Index
> + rdmsr
> + ret
> +EfiReadMsr ENDP
> +
> +;VOID
> +;EfiWriteMsr (
> +; IN UINT32 Index,
> +; IN UINT64 Value
> +; );
> +EfiWriteMsr PROC C PUBLIC
> + mov ecx, dword ptr [esp+4]; Index
> + mov eax, dword ptr [esp+8]; DWORD PTR Value[0]
> + mov edx, dword ptr [esp+0Ch]; DWORD PTR Value[4]
> + wrmsr
> + ret
> +EfiWriteMsr ENDP
> +
> +;UINT64
> +;EfiReadTsc (
> +; VOID
> +; )
> +EfiReadTsc PROC C PUBLIC
> + rdtsc
> + ret
> +EfiReadTsc ENDP
> +
> +;VOID
> +;EfiDisableCache (
> +; VOID
> +;)
> +EfiDisableCache PROC C PUBLIC
> + mov eax, cr0
> + bswap eax
> + and al, 60h
> + cmp al, 60h
> + je @F
> + mov eax, cr0
> + or eax, 060000000h
> + mov cr0, eax
> + wbinvd
> +@@:
> + ret
> +EfiDisableCache ENDP
> +
> +;VOID
> +;EfiEnableCache (
> +; VOID
> +; )
> +EfiEnableCache PROC C PUBLIC
> + wbinvd
> + mov eax, cr0
> + and eax, 09fffffffh
> + mov cr0, eax
> + ret
> +EfiEnableCache ENDP
> +
> +;UINT32
> +;EfiGetEflags (
> +; VOID
> +; )
> +EfiGetEflags PROC C PUBLIC
> + pushfd
> + pop eax
> + ret
> +EfiGetEflags ENDP
> +
> +;VOID
> +;EfiDisableInterrupts (
> +; VOID
> +; )
> +EfiDisableInterrupts PROC C PUBLIC
> + cli
> + ret
> +EfiDisableInterrupts ENDP
> +
> +;VOID
> +;EfiEnableInterrupts (
> +; VOID
> +; )
> +EfiEnableInterrupts PROC C PUBLIC
> + sti
> + ret
> +EfiEnableInterrupts ENDP
> +
> +;VOID
> +;EfiCpuidExt (
> +; IN UINT32 RegisterInEax,
> +; IN UINT32 CacheLevel,
> +; OUT EFI_CPUID_REGISTER *Regs
> +; )
> +EfiCpuidExt PROC C PUBLIC USES ebx edi esi
> + pushad
> +
> + mov eax, dword ptr [esp + 30h] ; RegisterInEax
> + mov ecx, dword ptr [esp + 34h] ; CacheLevel
> + cpuid
> + mov edi, dword ptr [esp + 38h] ; DWORD PTR Regs
> +
> + mov dword ptr [edi], eax ; Reg->RegEax
> + mov dword ptr [edi + 4], ebx ; Reg->RegEbx
> + mov dword ptr [edi + 8], ecx ; Reg->RegEcx
> + mov dword ptr [edi + 0Ch], edx ; Reg->RegEdx
> +
> + popad
> + ret
> +EfiCpuidExt ENDP
> +
> + END
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.c
> new file mode 100644
> index 0000000000..cb8de2f9c7
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.c
> @@ -0,0 +1,177 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + CpuIA32.c
> +
> +Abstract:
> +
> +--*/
> +
> +#include <Library/CpuIA32.h>
> +
> +VOID
> +EfiHalt (VOID)
> +{
> + __asm {
> + hlt
> + }
> +}
> +
> +VOID
> +EfiWbinvd (VOID)
> +{
> + __asm {
> + wbinvd
> + }
> +}
> +
> +VOID
> +EfiInvd (VOID)
> +{
> + __asm {
> + invd
> + }
> +}
> +
> +VOID
> +EfiCpuid (IN UINT32 RegisterInEax,
> + OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
> +{
> + __asm {
> + pushad
> +
> + mov eax, RegisterInEax
> + cpuid
> + cmp Reg, 0
> + je _Exit
> + mov edi, DWORD PTR Reg
> +
> + mov DWORD PTR [edi].RegEax, eax ; Reg->RegEax
> + mov DWORD PTR [edi].RegEbx, ebx ; Reg->RegEbx
> + mov DWORD PTR [edi].RegEcx, ecx ; Reg->RegEcx
> + mov DWORD PTR [edi].RegEdx, edx ; Reg->RegEdx
> +
> +_Exit:
> + popad
> + }
> +}
> +
> +UINT64
> +EfiReadMsr (IN UINT32 Index)
> +{
> + __asm {
> + mov ecx, Index
> + rdmsr
> + }
> +}
> +
> +VOID
> +EfiWriteMsr (
> + IN UINT32 Index,
> + IN UINT64 Value
> + )
> +{
> + __asm {
> + mov ecx, Index
> + mov eax, DWORD PTR Value[0]
> + mov edx, DWORD PTR Value[4]
> + wrmsr
> + }
> +}
> +
> +UINT64
> +EfiReadTsc (VOID)
> +{
> + __asm {
> + rdtsc
> + }
> +}
> +
> +VOID
> +EfiDisableCache (VOID)
> +{
> + __asm {
> + mov eax, cr0
> + bswap eax
> + and al, 60h
> + cmp al, 60h
> + je Exit
> + mov eax, cr0
> + or eax, 060000000h
> + mov cr0, eax
> + wbinvd
> +Exit:
> + }
> +}
> +
> +VOID
> +EfiEnableCache (VOID)
> +{
> + __asm {
> + wbinvd
> + mov eax, cr0
> + and eax, 09fffffffh
> + mov cr0, eax
> + }
> +}
> +
> +UINT32
> +EfiGetEflags (
> + VOID
> + )
> +{
> + __asm {
> + pushfd
> + pop eax
> + }
> +}
> +
> +VOID
> +EfiDisableInterrupts (VOID)
> +{
> + __asm {
> + cli
> + }
> +}
> +
> +VOID
> +EfiEnableInterrupts (
> + VOID
> + )
> +{
> + __asm {
> + sti
> + }
> +}
> +
> +VOID
> +EfiCpuidExt (
> + IN UINT32 RegisterInEax,
> + IN UINT32 CacheLevel,
> + OUT EFI_CPUID_REGISTER *Regs
> + )
> +{
> + __asm {
> + pushad
> +
> + mov eax, RegisterInEax
> + mov ecx, CacheLevel
> + cpuid
> + mov edi, DWORD PTR Regs
> +
> + mov DWORD PTR [edi].RegEax, eax ; Reg->RegEax
> + mov DWORD PTR [edi].RegEbx, ebx ; Reg->RegEbx
> + mov DWORD PTR [edi].RegEcx, ecx ; Reg->RegEcx
> + mov DWORD PTR [edi].RegEdx, edx ; Reg->RegEdx
> +
> + popad
> + }
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.S
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.S
> new file mode 100644
> index 0000000000..3a8d6e6bc5
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.S
> @@ -0,0 +1,207 @@
> +#
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#* Module Name:
> +#*
> +#* Cpu.asm
> +#*
> +#* Abstract:
> +#*
> +#------------------------------------------------------------------------------
> +##include <EfiBind.h>
> +
> +.globl ASM_PFX(EfiHalt)
> +.globl ASM_PFX(EfiWbinvd)
> +.globl ASM_PFX(EfiInvd)
> +.globl ASM_PFX(EfiCpuid)
> +.globl ASM_PFX(EfiReadTsc)
> +.globl ASM_PFX(EfiDisableCache)
> +.globl ASM_PFX(EfiEnableCache)
> +.globl ASM_PFX(EfiReadMsr)
> +.globl ASM_PFX(EfiWriteMsr)
> +.globl ASM_PFX(EfiGetEflags)
> +.globl ASM_PFX(EfiDisableInterrupts)
> +.globl ASM_PFX(EfiEnableInterrupts)
> +.globl ASM_PFX(EfiCpuidExt)
> +
> +.text
> +
> +
> +#------------------------------------------------------------------------------
> +# VOID
> +# EfiHalt (
> +# VOID
> +# )
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiHalt):
> + hlt
> + retq
> +
> +
> +#------------------------------------------------------------------------------
> +# VOID
> +# EfiWbinvd (
> +# VOID
> +# )
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiWbinvd):
> + wbinvd
> + retq
> +
> +
> +#------------------------------------------------------------------------------
> +# VOID
> +# EfiInvd (
> +# VOID
> +# )
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiInvd):
> + invd
> + retq
> +
> +#------------------------------------------------------------------------------
> +# VOID
> +# EfiCpuid (
> +# IN UINT32 RegisterInEax, // rcx
> +# OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx
> +# )
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiCpuid):
> + push %rbx
> + mov %rdx,%r8
> + mov %rcx,%rax
> + cpuid
> + cmp $0x0,%r8
> + je _Exit
> + mov %eax,(%r8)
> + mov %ebx,0x4(%r8)
> + mov %ecx,0x8(%r8)
> + mov %edx,0xc(%r8)
> +_Exit:
> + pop %rbx
> + retq
> +
> +#------------------------------------------------------------------------------
> +# UINT64
> +# EfiReadMsr (
> +# IN UINT32 Index, // rcx
> +# )
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiReadMsr):
> + rdmsr
> + shl $0x20,%rdx
> + or %rdx,%rax
> + retq
> +
> +#------------------------------------------------------------------------------
> +# VOID
> +# EfiWriteMsr (
> +# IN UINT32 Index, // rcx
> +# IN UINT64 Value // rdx
> +# )
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiWriteMsr):
> + mov %rdx,%rax
> + sar $0x20,%rdx
> + wrmsr
> + retq
> +
> +#------------------------------------------------------------------------------
> +# UINT64
> +# EfiReadTsc (
> +# VOID
> +# );
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiReadTsc):
> + rdtsc
> + shl $0x20,%rax
> + shrd $0x20,%rdx,%rax
> + retq
> +
> +#------------------------------------------------------------------------------
> +# VOID
> +# EfiDisableCache (
> +# VOID
> +# );
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiDisableCache):
> +# added a check to see if cache is already disabled. If it is, then skip.
> + mov %cr0,%rax
> + and $0x60000000,%rax
> + cmp $0x0,%rax
> + jne 1f
> + mov %cr0,%rax
> + or $0x60000000,%rax
> + mov %rax,%cr0
> + wbinvd
> +1:
> + retq
> +
> +#------------------------------------------------------------------------------
> +# VOID
> +# EfiEnableCache (
> +# VOID
> +# );
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiEnableCache):
> + wbinvd
> + mov %cr0,%rax
> + and $0xffffffff9fffffff,%rax
> + mov %rax,%cr0
> + retq
> +
> +#------------------------------------------------------------------------------
> +# UINTN
> +# EfiGetEflags (
> +# VOID
> +# );
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiGetEflags):
> + pushfq
> + pop %rax
> + retq
> +
> +#------------------------------------------------------------------------------
> +# VOID
> +# EfiDisableInterrupts (
> +# VOID
> +# );
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiDisableInterrupts):
> + cli
> + ret
> +
> +#------------------------------------------------------------------------------
> +# VOID
> +# EfiEnableInterrupts (
> +# VOID
> +# );
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiEnableInterrupts):
> + sti
> + ret
> +#------------------------------------------------------------------------------
> +# VOID
> +# EfiCpuidExt (
> +# IN UINT32 RegisterInEax,
> +# IN UINT32 CacheLevel,
> +# OUT EFI_CPUID_REGISTER *Regs
> +# )
> +#------------------------------------------------------------------------------
> +ASM_PFX(EfiCpuidExt):
> + push %rbx
> + mov %rcx,%rax
> + mov %rdx,%rcx
> + cpuid
> + mov %eax,(%r8)
> + mov %ebx,0x4(%r8)
> + mov %ecx,0x8(%r8)
> + mov %edx,0xc(%r8)
> + pop %rbx
> + retq
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.asm
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.asm
> new file mode 100644
> index 0000000000..44aae7de64
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.asm
> @@ -0,0 +1,222 @@
> +
> +TITLE Cpu.asm: Assembly code for the x64 resources
> +
> +;
> +; This file contains an 'Intel Sample Driver' and is
> +; licensed for Intel CPUs and chipsets under the terms of your
> +; license agreement with Intel or your vendor. This file may
> +; be modified by the user, subject to additional terms of the
> +; license agreement
> +;
> +;
> +; Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +;
>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +;
>
> +;
> +;
> +;
> +;
> +;* Module Name:
> +;*
> +;* Cpu.asm
> +;*
> +;* Abstract:
> +;*
> +;------------------------------------------------------------------------------
> +
> +text SEGMENT
> +
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EfiHalt (
> +; VOID
> +; )
> +;------------------------------------------------------------------------------
> +EfiHalt PROC PUBLIC
> + hlt
> + ret
> +EfiHalt ENDP
> +
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EfiWbinvd (
> +; VOID
> +; )
> +;------------------------------------------------------------------------------
> +EfiWbinvd PROC PUBLIC
> + wbinvd
> + ret
> +EfiWbinvd ENDP
> +
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EfiInvd (
> +; VOID
> +; )
> +;------------------------------------------------------------------------------
> +EfiInvd PROC PUBLIC
> + invd
> + ret
> +EfiInvd ENDP
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EfiCpuid (
> +; IN UINT32 RegisterInEax, // rcx
> +; OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx
> +; )
> +;------------------------------------------------------------------------------
> +EfiCpuid PROC PUBLIC
> + push rbx
> +
> + mov r8, rdx ; r8 = *Reg
> + mov rax, rcx ; RegisterInEax
> + cpuid
> + cmp r8, 0
> + je _Exit
> + mov [r8 + 0], eax ; Reg->RegEax
> + mov [r8 + 4], ebx ; Reg->RegEbx
> + mov [r8 + 8], ecx ; Reg->RegEcx
> + mov [r8 + 12], edx ; Reg->RegEdx
> +
> +_Exit:
> + pop rbx
> + ret
> +EfiCpuid ENDP
> +
> +;------------------------------------------------------------------------------
> +; UINT64
> +; EfiReadMsr (
> +; IN UINT32 Index, // rcx
> +; )
> +;------------------------------------------------------------------------------
> +EfiReadMsr PROC PUBLIC
> + rdmsr
> + sal rdx, 32 ; edx:eax -> rax
> + or rax, rdx ; rax = edx:eax
> + ret
> +EfiReadMsr ENDP
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EfiWriteMsr (
> +; IN UINT32 Index, // rcx
> +; IN UINT64 Value // rdx
> +; )
> +;------------------------------------------------------------------------------
> +EfiWriteMsr PROC PUBLIC
> + mov rax, rdx ; rdx = Value
> + sar rdx, 32 ; convert rdx to edx upper 32-bits
> + wrmsr ; wrmsr[ecx] result = edx:eax
> + ret
> +EfiWriteMsr ENDP
> +
> +
> +;------------------------------------------------------------------------------
> +; UINT64
> +; EfiReadTsc (
> +; VOID
> +; );
> +;------------------------------------------------------------------------------
> +EfiReadTsc PROC PUBLIC
> + rdtsc
> + shl rax, 32
> + shrd rax, rdx, 32
> + ret
> +EfiReadTsc ENDP
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EfiDisableCache (
> +; VOID
> +; );
> +;------------------------------------------------------------------------------
> +EfiDisableCache PROC PUBLIC
> +; added a check to see if cache is already disabled. If it is, then skip.
> + mov rax, cr0
> + and rax, 060000000h
> + cmp rax, 0
> + jne @f
> + mov rax, cr0
> + or rax, 060000000h
> + mov cr0, rax
> + wbinvd
> +@@:
> + ret
> +EfiDisableCache ENDP
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EfiEnableCache (
> +; VOID
> +; );
> +;------------------------------------------------------------------------------
> +EfiEnableCache PROC PUBLIC
> + wbinvd
> + mov rax, cr0
> + and rax, 09fffffffh
> + mov cr0, rax
> + ret
> +EfiEnableCache ENDP
> +
> +;------------------------------------------------------------------------------
> +; UINTN
> +; EfiGetEflags (
> +; VOID
> +; );
> +;------------------------------------------------------------------------------
> +EfiGetEflags PROC PUBLIC
> + pushfq
> + pop rax
> + ret
> +EfiGetEflags ENDP
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EfiDisableInterrupts (
> +; VOID
> +; );
> +;------------------------------------------------------------------------------
> +EfiDisableInterrupts PROC PUBLIC
> + cli
> + ret
> +EfiDisableInterrupts ENDP
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EfiEnableInterrupts (
> +; VOID
> +; );
> +;------------------------------------------------------------------------------
> +EfiEnableInterrupts PROC PUBLIC
> + sti
> + ret
> +EfiEnableInterrupts ENDP
> +;------------------------------------------------------------------------------
> +; VOID
> +; EfiCpuidExt (
> +; IN UINT32 RegisterInEax,
> +; IN UINT32 CacheLevel,
> +; OUT EFI_CPUID_REGISTER *Regs
> +; )
> +;------------------------------------------------------------------------------
> +EfiCpuidExt PROC PUBLIC
> + push rbx
> + mov rax, rcx ; rax = RegisterInEax
> + mov rcx, rdx ; rcx = CacheLevel
> +
> + cpuid
> + mov [r8 + 0 ], eax ; Reg->RegEax
> + mov [r8 + 4 ], ebx ; Reg->RegEbx
> + mov [r8 + 8 ], ecx ; Reg->RegEcx
> + mov [r8 + 12], edx ; Reg->RegEdx
> +
> + pop rbx
> + ret
> +EfiCpuidExt ENDP
> +END
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c
> new file mode 100644
> index 0000000000..b7d896d9fd
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c
> @@ -0,0 +1,282 @@
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + EfiRegTableLib.c
> +
> +Abstract:
> +
> + Lib function for table driven register initialization.
> +
> +Revision History
> +
> +--*/
> +
> +#include <Library/EfiRegTableLib.h>
> +#include <Library/S3BootScriptLib.h>
> +
> +//
> +// Local Functions
> +//
> +
> +/**
> + Local worker function to process PCI_WRITE table entries. Performs write
> and
> + may also call BootScriptSave protocol if indicated in the Entry flags
> +
> + @param Entry A pointer to the PCI_WRITE entry to process
> +
> + @param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that
> is used
> + when processing the entry.
> +
> + @retval Nothing.
> +
> +**/
> +STATIC
> +VOID
> +PciWrite (
> + EFI_REG_TABLE_PCI_WRITE *Entry,
> + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = PciRootBridgeIo->Pci.Write (
> + PciRootBridgeIo,
> + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)
> (OPCODE_EXTRA_DATA (Entry->OpCode)),
> + (UINT64) Entry->PciAddress,
> + 1,
> + &Entry->Data
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
> + Status = S3BootScriptSavePciCfgWrite (
> + (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry-
> >OpCode)),
> + (UINT64) Entry->PciAddress,
> + 1,
> + &Entry->Data
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +}
> +
> +/**
> + Local worker function to process PCI_READ_MODIFY_WRITE table entries.
> + Performs RMW write and may also call BootScriptSave protocol if indicated
> in
> + the Entry flags.
> +
> + @param Entry A pointer to the PCI_READ_MODIFY_WRITE entry to
> process.
> +
> + @param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that
> is used
> + when processing the entry.
> +
> + @retval Nothing.
> +
> +**/
> +STATIC
> +VOID
> +PciReadModifyWrite (
> + EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *Entry,
> + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 TempData;
> +
> + Status = PciRootBridgeIo->Pci.Read (
> + PciRootBridgeIo,
> + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)
> (OPCODE_EXTRA_DATA (Entry->OpCode)),
> + (UINT64) Entry->PciAddress,
> + 1,
> + &TempData
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Entry->OrMask &= Entry->AndMask;
> + TempData &= ~Entry->AndMask;
> + TempData |= Entry->OrMask;
> +
> + Status = PciRootBridgeIo->Pci.Write (
> + PciRootBridgeIo,
> + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)
> (OPCODE_EXTRA_DATA (Entry->OpCode)),
> + (UINT64) Entry->PciAddress,
> + 1,
> + &TempData
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
> + Status = S3BootScriptSavePciCfgReadWrite (
> + (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry-
> >OpCode)),
> + (UINT64) Entry->PciAddress,
> + &Entry->OrMask,
> + &Entry->AndMask
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +}
> +
> +/**
> + Local worker function to process MEM_READ_MODIFY_WRITE table
> entries.
> + Performs RMW write and may also call BootScriptSave protocol if indicated
> in
> + the Entry flags.
> +
> + @param Entry A pointer to the MEM_READ_MODIFY_WRITE entry to
> process.
> +
> + @param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that
> is used
> + when processing the entry.
> +
> + @retval Nothing.
> +
> +**/
> +STATIC
> +VOID
> +MemReadModifyWrite (
> + EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *Entry,
> + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 TempData;
> +
> + Status = PciRootBridgeIo->Mem.Read (
> + PciRootBridgeIo,
> + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)
> (OPCODE_EXTRA_DATA (Entry->OpCode)),
> + (UINT64) Entry->MemAddress,
> + 1,
> + &TempData
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Entry->OrMask &= Entry->AndMask;
> + TempData &= ~Entry->AndMask;
> + TempData |= Entry->OrMask;
> +
> + Status = PciRootBridgeIo->Mem.Write (
> + PciRootBridgeIo,
> + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)
> (OPCODE_EXTRA_DATA (Entry->OpCode)),
> + (UINT64) Entry->MemAddress,
> + 1,
> + &TempData
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
> + Status = S3BootScriptSaveMemReadWrite (
> + (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry-
> >OpCode)),
> + Entry->MemAddress,
> + &Entry->OrMask,
> + &Entry->AndMask
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +}
> +
> +//
> +// Exported functions
> +//
> +
> +/**
> + Processes register table assuming which may contain PCI, IO, MEM, and
> STALL
> + entries.
> +
> + No parameter checking is done so the caller must be careful about omitting
> + values for PciRootBridgeIo or CpuIo parameters. If the regtable does
> + not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
> + NULL). If the regtable does not contain any IO or Mem entries, it is safe to
> + omit the CpuIo (supply NULL).
> +
> + The RegTableEntry parameter is not checked, but is required.
> +
> + gBS is assumed to have been defined and is used when processing stalls.
> +
> + The function processes each entry sequentially until an
> OP_TERMINATE_TABLE
> + entry is encountered.
> +
> + @param RegTableEntry A pointer to the register table to process
> +
> + @param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that
> is used
> + when processing PCI table entries
> +
> + @param CpuIo A pointer to the instance of CpuIo that is used when
> processing IO and
> + MEM table entries
> +
> + @retval Nothing.
> +
> +**/
> +VOID
> +ProcessRegTablePci (
> + EFI_REG_TABLE *RegTableEntry,
> + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
> + EFI_CPU_IO_PROTOCOL *CpuIo
> + )
> +{
> + while (OPCODE_BASE (RegTableEntry->Generic.OpCode) !=
> OP_TERMINATE_TABLE) {
> + switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {
> + case OP_PCI_WRITE:
> + PciWrite ((EFI_REG_TABLE_PCI_WRITE *) RegTableEntry,
> PciRootBridgeIo);
> + break;
> +
> + case OP_PCI_READ_MODIFY_WRITE:
> + PciReadModifyWrite ((EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *)
> RegTableEntry, PciRootBridgeIo);
> + break;
> +
> + case OP_MEM_READ_MODIFY_WRITE:
> + MemReadModifyWrite ((EFI_REG_TABLE_MEM_READ_MODIFY_WRITE
> *) RegTableEntry, PciRootBridgeIo);
> + break;
> +
> + default:
> + DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode
> (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));
> + ASSERT (0);
> + break;
> + }
> +
> + RegTableEntry++;
> + }
> +}
> +
> +/**
> + Processes register table assuming which may contain IO, MEM, and STALL
> + entries, but must NOT contain any PCI entries. Any PCI entries cause an
> + ASSERT in a DEBUG build and are skipped in a free build.
> +
> + No parameter checking is done. Both RegTableEntry and CpuIo
> parameters are
> + required.
> +
> + gBS is assumed to have been defined and is used when processing stalls.
> +
> + The function processes each entry sequentially until an
> OP_TERMINATE_TABLE
> + entry is encountered.
> +
> + @param RegTableEntry A pointer to the register table to process
> +
> + @param CpuIo A pointer to the instance of CpuIo that is used when
> processing IO and
> + MEM table entries
> +
> + @retval Nothing.
> +
> +**/
> +VOID
> +ProcessRegTableCpu (
> + EFI_REG_TABLE *RegTableEntry,
> + EFI_CPU_IO_PROTOCOL *CpuIo
> + )
> +{
> + while (OPCODE_BASE (RegTableEntry->Generic.OpCode) !=
> OP_TERMINATE_TABLE) {
> + switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {
> + default:
> + DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode
> (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));
> + ASSERT (0);
> + break;
> + }
> +
> + RegTableEntry++;
> + }
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.in
> f
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.in
> f
> new file mode 100644
> index 0000000000..9cb8841d65
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.in
> f
> @@ -0,0 +1,47 @@
> +#
> +#
> +#/*++
> +#
> +# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +
> +#
> +# Module Name:
> +#
> +# EfiRegTableLib.inf
> +#
> +# Abstract:
> +#
> +# Component description file.
> +#
> +#--*/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = EfiRegTableLib
> + FILE_GUID = 98546145-64F1-4d2e-814F-6BF963DB7930
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = EfiRegTableLib
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + EfiRegTableLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> +
> +
> +[LibraryClasses]
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.c
> new file mode 100644
> index 0000000000..558763fa98
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.c
> @@ -0,0 +1,461 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +**/
> +
> +#include <PiDxe.h>
> +
> +#include <Library/FlashDeviceLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/UefiRuntimeLib.h>
> +#include <Protocol/SmmBase2.h>
> +#include <Guid/EventGroup.h>
> +#include "SpiChipDefinitions.h"
> +
> +UINTN FlashDeviceBase = FLASH_DEVICE_BASE_ADDRESS;
> +
> +EFI_SPI_PROTOCOL *mSpiProtocol = NULL;
> +
> +EFI_STATUS
> +SpiFlashErase (
> + UINT8 *BaseAddress,
> + UINTN NumBytes
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + UINT32 SectorSize;
> + UINT32 SpiAddress;
> +
> + SpiAddress = (UINT32)(UINTN)(BaseAddress) - (UINT32)FlashDeviceBase;
> + SectorSize = SECTOR_SIZE_4KB;
> + while ( (NumBytes > 0) && (NumBytes <= MAX_FWH_SIZE) ) {
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_SERASE,
> + SPI_WREN,
> + FALSE,
> + TRUE,
> + FALSE,
> + (UINT32) SpiAddress,
> + 0,
> + NULL,
> + EnumSpiRegionBios
> + );
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + SpiAddress += SectorSize;
> + NumBytes -= SectorSize;
> + }
> +
> + return Status;
> +}
> +
> +
> +EFI_STATUS
> +SpiFlashBlockErase (
> + UINT8 *BaseAddress,
> + UINTN NumBytes
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + UINT32 SectorSize;
> + UINT32 SpiAddress;
> +
> + SpiAddress = (UINT32)(UINTN)(BaseAddress) - (UINT32)FlashDeviceBase;
> + SectorSize = SECTOR_SIZE_4KB;
> + while ( (NumBytes > 0) && (NumBytes <= MAX_FWH_SIZE) ) {
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_SERASE,
> + SPI_WREN,
> + FALSE,
> + TRUE,
> + FALSE,
> + (UINT32) SpiAddress,
> + 0,
> + NULL,
> + EnumSpiRegionBios
> + );
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + SpiAddress += SectorSize;
> + NumBytes -= SectorSize;
> + }
> +
> + return Status;
> +}
> +
> +
> +static
> +EFI_STATUS
> +SpiFlashWrite (
> + UINT8 *DstBufferPtr,
> + UINT8 *Byte,
> + IN UINTN Length
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 NumBytes = (UINT32)Length;
> + UINT8* pBuf8 = Byte;
> + UINT32 SpiAddress;
> +
> + SpiAddress = (UINT32)(UINTN)(DstBufferPtr) - (UINT32)FlashDeviceBase;
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_PROG,
> + SPI_WREN,
> + TRUE,
> + TRUE,
> + TRUE,
> + (UINT32)SpiAddress,
> + NumBytes,
> + pBuf8,
> + EnumSpiRegionBios
> + );
> + return Status;
> +}
> +
> +/**
> + Read the Serial Flash Status Registers.
> +
> + @param SpiStatus Pointer to a caller-allocated UINT8. On successful
> return, it contains the
> + status data read from the Serial Flash Status Register.
> +
> +
> + @retval EFI_SUCCESS Operation success, status is returned in SpiStatus.
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and the operation failed.
> +
> +**/
> +EFI_STATUS
> +ReadStatusRegister (
> + UINT8 *SpiStatus
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_RDSR,
> + SPI_WREN,
> + TRUE,
> + FALSE,
> + FALSE,
> + 0,
> + 1,
> + SpiStatus,
> + EnumSpiRegionBios
> + );
> + return Status;
> +}
> +
> +EFI_STATUS
> +SpiFlashLock (
> + IN UINT8 *BaseAddress,
> + IN UINTN NumBytes,
> + IN BOOLEAN Lock
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 SpiData;
> + UINT8 SpiStatus;
> +
> + if (Lock) {
> + SpiData = SF_SR_WPE;
> + } else {
> + SpiData = 0;
> + }
> +
> + //
> + // Always disable block protection to workaround tool issue.
> + // Feature may be re-enabled in a future bios.
> + //
> + SpiData = 0;
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_WRSR,
> + SPI_EWSR,
> + TRUE,
> + TRUE,
> + TRUE,
> + 0,
> + 1,
> + &SpiData,
> + EnumSpiRegionBios
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + Status = ReadStatusRegister (&SpiStatus);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if ((SpiStatus & SpiData) != SpiData) {
> + Status = EFI_DEVICE_ERROR;
> + }
> +
> + return Status;
> +}
> +
> +
> +/**
> + Read NumBytes bytes of data from the address specified by
> + PAddress into Buffer.
> +
> + @param[in] PAddress The starting physical address of the read.
> + @param[in,out] NumBytes On input, the number of bytes to read. On
> output, the number
> + of bytes actually read.
> + @param[out] Buffer The destination data buffer for the read.
> +
> + @retval EFI_SUCCESS. Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibFvbFlashDeviceRead (
> + IN UINTN PAddress,
> + IN OUT UINTN *NumBytes,
> + OUT UINT8 *Buffer
> + )
> +{
> + CopyMem(Buffer, (VOID*)PAddress, *NumBytes);
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Write NumBytes bytes of data from Buffer to the address specified by
> + PAddresss.
> +
> + @param[in] PAddress The starting physical address of the write.
> + @param[in,out] NumBytes On input, the number of bytes to write.
> On output,
> + the actual number of bytes written.
> + @param[in] Buffer The source data buffer for the write.
> +
> + @retval EFI_SUCCESS. Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibFvbFlashDeviceWrite (
> + IN UINTN PAddress,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> +EFI_STATUS Status;
> + Status = SpiFlashWrite((UINT8 *)PAddress, Buffer, *NumBytes);
> + return Status;
> +}
> +
> +
> +/**
> + Erase the block staring at PAddress.
> +
> + @param[in] PAddress The starting physical address of the block to be
> erased.
> + This library assume that caller garantee that the PAddress
> + is at the starting address of this block.
> + @param[in] LbaLength The length of the logical block to be erased.
> +
> + @retval EFI_SUCCESS. Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibFvbFlashDeviceBlockErase (
> + IN UINTN PAddress,
> + IN UINTN LbaLength
> + )
> +{
> + EFI_STATUS Status;
> + Status = SpiFlashBlockErase((UINT8 *)PAddress, LbaLength);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Lock or unlock the block staring at PAddress.
> +
> + @param[in] PAddress The starting physical address of region to be
> (un)locked.
> + @param[in] LbaLength The length of the logical block to be erased.
> + @param[in] Lock TRUE to lock. FALSE to unlock.
> +
> + @retval EFI_SUCCESS. Opertion is successful.
> + @retval EFI_DEVICE_ERROR If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibFvbFlashDeviceBlockLock (
> + IN UINTN PAddress,
> + IN UINTN LbaLength,
> + IN BOOLEAN Lock
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = SpiFlashLock((UINT8*)PAddress, LbaLength, Lock);
> + return Status;
> +}
> +
> +VOID
> +EFIAPI
> +LibFvbFlashDeviceVirtualAddressChangeNotifyEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + gRT->ConvertPointer (0, (VOID **) &mSpiProtocol);
> + gRT->ConvertPointer (0, (VOID **) &FlashDeviceBase);
> +}
> +
> +
> +/**
> + The library constructuor.
> +
> + The function does the necessary initialization work for this library
> + instance. Please put all initialization works in it.
> +
> + @param[in] ImageHandle The firmware allocated handle for the UEFI
> image.
> + @param[in] SystemTable A pointer to the EFI system table.
> +
> + @retval EFI_SUCCESS The function always return EFI_SUCCESS for
> now.
> + It will ASSERT on error for debug version.
> + @retval EFI_ERROR Please reference LocateProtocol for error code
> details.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibFvbFlashDeviceSupportInit (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_EVENT Event;
> + UINT8 SfId[3];
> + UINT8 FlashIndex;
> + UINT8 SpiReadError;
> + UINT8 SpiNotMatchError;
> + EFI_SMM_BASE2_PROTOCOL *SmmBase;
> + BOOLEAN InSmm;
> +
> + SpiReadError = 0x00;
> + SpiNotMatchError = 0x00;
> +
> + InSmm = FALSE;
> + Status = gBS->LocateProtocol (
> + &gEfiSmmBase2ProtocolGuid,
> + NULL,
> + (void **)&SmmBase
> + );
> + if (!EFI_ERROR(Status)) {
> + Status = SmmBase->InSmm(SmmBase, &InSmm);
> + if (EFI_ERROR(Status)) {
> + InSmm = FALSE;
> + }
> + }
> +
> + if (!InSmm) {
> + Status = gBS->LocateProtocol (
> + &gEfiSpiProtocolGuid,
> + NULL,
> + (VOID **)&mSpiProtocol
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gBS->CreateEventEx (
> + EVT_NOTIFY_SIGNAL,
> + TPL_NOTIFY,
> + LibFvbFlashDeviceVirtualAddressChangeNotifyEvent,
> + NULL,
> + &gEfiEventVirtualAddressChangeGuid,
> + &Event
> + );
> + ASSERT_EFI_ERROR (Status);
> + } else {
> + Status = gBS->LocateProtocol (
> + &gEfiSmmSpiProtocolGuid,
> + NULL,
> + (VOID **)&mSpiProtocol
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> +
> + for (FlashIndex = EnumSpiFlashW25Q64; FlashIndex < EnumSpiFlashMax;
> FlashIndex++) {
> + Status = mSpiProtocol->Init (mSpiProtocol, &(mInitTable[FlashIndex]));
> + if (!EFI_ERROR (Status)) {
> + //
> + // Read Vendor/Device IDs to check if the driver supports the Serial Flash
> device.
> + //
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_READ_ID,
> + SPI_WREN,
> + TRUE,
> + FALSE,
> + FALSE,
> + 0,
> + 3,
> + SfId,
> + EnumSpiRegionAll
> + );
> + if (!EFI_ERROR (Status)) {
> + if ((SfId[0] == mInitTable[FlashIndex].VendorId) &&
> + (SfId[1] == mInitTable[FlashIndex].DeviceId0) &&
> + (SfId[2] == mInitTable[FlashIndex].DeviceId1)) {
> + //
> + // Found a matching SPI device, FlashIndex now contains flash device.
> + //
> + DEBUG ((DEBUG_ERROR, "OK - Found SPI Flash Type in SPI Flash
> Driver, Device Type ID 0 = 0x%02x!\n", mInitTable[FlashIndex].DeviceId0));
> + DEBUG ((DEBUG_ERROR, "Device Type ID 1 = 0x%02x!\n",
> mInitTable[FlashIndex].DeviceId1));
> +
> + if (mInitTable[FlashIndex].BiosStartOffset == (UINTN) (-1)) {
> + DEBUG ((DEBUG_ERROR, "ERROR - The size of BIOS image is bigger
> than SPI Flash device!\n"));
> + CpuDeadLoop ();
> + }
> + break;
> + } else {
> + SpiNotMatchError++;
> + }
> + } else {
> + SpiReadError++;
> + }
> + }
> + }
> +
> + DEBUG ((DEBUG_ERROR, "SPI flash chip VID = 0x%X, DID0 = 0x%X, DID1 =
> 0x%X\n", SfId[0], SfId[1], SfId[2]));
> +
> + if (FlashIndex < EnumSpiFlashMax) {
> + return EFI_SUCCESS;
> + } else {
> + if (SpiReadError != 0) {
> + DEBUG ((DEBUG_ERROR, "ERROR - SPI Read ID execution failed! Error
> Count = %d\n", SpiReadError));
> + }
> + else {
> + if (SpiNotMatchError != 0) {
> + DEBUG ((DEBUG_ERROR, "ERROR - No supported SPI flash chip found!
> Error Count = %d\n", SpiNotMatchError));
> + DEBUG ((DEBUG_ERROR, "SPI flash chip VID = 0x%X, DID0 = 0x%X, DID1
> = 0x%X\n", SfId[0], SfId[1], SfId[2]));
> + }
> + }
> + return EFI_UNSUPPORTED;
> + }
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.in
> f
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.i
> nf
> new file mode 100644
> index 0000000000..4ef48cc12b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.i
> nf
> @@ -0,0 +1,44 @@
> +#
> +#
> +# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = FlashDeviceLib
> + FILE_GUID = E38A1C3C-928C-4bf7-B6C1-7F0EF163FAA5
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = FlashDeviceLib | DXE_SMM_DRIVER
> DXE_RUNTIME_DRIVER
> + CONSTRUCTOR = LibFvbFlashDeviceSupportInit
> +
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +[Sources]
> + FlashDeviceLib.c
> +
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> +
> +[Protocols]
> + gEfiSpiProtocolGuid
> + gEfiSmmSpiProtocolGuid
> + gEfiSmmBase2ProtocolGuid
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibD
> xe.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibD
> xe.c
> new file mode 100644
> index 0000000000..cf4677ed88
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibD
> xe.c
> @@ -0,0 +1,56 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +**/
> +
> +#include <PiDxe.h>
> +
> +#include <Library/FlashDeviceLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include "SpiChipDefinitions.h"
> +
> +extern UINTN FlashDeviceBase;
> +
> +extern EFI_SPI_PROTOCOL *mSpiProtocol;
> +
> +/**
> + The library constructuor.
> +
> + The function does the necessary initialization work for this library
> + instance. Please put all initialization works in it.
> +
> + @param[in] ImageHandle The firmware allocated handle for the UEFI
> image.
> + @param[in] SystemTable A pointer to the EFI system table.
> +
> + @retval EFI_SUCCESS The function always return EFI_SUCCESS for
> now.
> + It will ASSERT on error for debug version.
> + @retval EFI_ERROR Please reference LocateProtocol for error code
> details.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibFvbFlashDeviceSupportInit (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + Status = gBS->LocateProtocol (
> + &gEfiSpiProtocolGuid,
> + NULL,
> + (VOID **)&mSpiProtocol
> + );
> + ASSERT_EFI_ERROR (Status);
> + // There is no need to call Init, because Runtime or SMM FVB already does
> that.
> + DEBUG((EFI_D_ERROR, "LibFvbFlashDeviceSupportInit - no init\n"));
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibD
> xe.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibD
> xe.inf
> new file mode 100644
> index 0000000000..2237e95781
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibD
> xe.inf
> @@ -0,0 +1,43 @@
> +#
> +#
> +# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = FlashDeviceLibDxe
> + FILE_GUID = F0D7222F-FD43-4A5D-B8BF-A259C87AE3B2
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = FlashDeviceLib | DXE_DRIVER
> + CONSTRUCTOR = LibFvbFlashDeviceSupportInit
> +
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +[Sources]
> + FlashDeviceLib.c
> + FlashDeviceLibDxe.c
> +
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> +
> +[Protocols]
> + gEfiSpiProtocolGuid
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibD
> xeRuntimeSmm.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibD
> xeRuntimeSmm.c
> new file mode 100644
> index 0000000000..df395fbc03
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLibD
> xeRuntimeSmm.c
> @@ -0,0 +1,173 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +**/
> +
> +#include <PiDxe.h>
> +
> +#include <Library/FlashDeviceLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/UefiRuntimeLib.h>
> +#include <Protocol/SmmBase2.h>
> +#include <Guid/EventGroup.h>
> +#include "SpiChipDefinitions.h"
> +
> +extern UINTN FlashDeviceBase;
> +
> +extern EFI_SPI_PROTOCOL *mSpiProtocol;
> +
> +VOID
> +EFIAPI
> +LibFvbFlashDeviceVirtualAddressChangeNotifyEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + gRT->ConvertPointer (0, (VOID **) &mSpiProtocol);
> + gRT->ConvertPointer (0, (VOID **) &FlashDeviceBase);
> +}
> +
> +
> +/**
> + The library constructuor.
> +
> + The function does the necessary initialization work for this library
> + instance. Please put all initialization works in it.
> +
> + @param[in] ImageHandle The firmware allocated handle for the UEFI
> image.
> + @param[in] SystemTable A pointer to the EFI system table.
> +
> + @retval EFI_SUCCESS The function always return EFI_SUCCESS for
> now.
> + It will ASSERT on error for debug version.
> + @retval EFI_ERROR Please reference LocateProtocol for error code
> details.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibFvbFlashDeviceSupportInit (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_EVENT Event;
> + UINT8 SfId[3];
> + UINT8 FlashIndex;
> + UINT8 SpiReadError;
> + UINT8 SpiNotMatchError;
> + EFI_SMM_BASE2_PROTOCOL *SmmBase;
> + BOOLEAN InSmm;
> +
> + SpiReadError = 0x00;
> + SpiNotMatchError = 0x00;
> +
> + InSmm = FALSE;
> + Status = gBS->LocateProtocol (
> + &gEfiSmmBase2ProtocolGuid,
> + NULL,
> + (void **)&SmmBase
> + );
> + if (!EFI_ERROR(Status)) {
> + Status = SmmBase->InSmm(SmmBase, &InSmm);
> + if (EFI_ERROR(Status)) {
> + InSmm = FALSE;
> + }
> + }
> +
> + if (!InSmm) {
> + Status = gBS->LocateProtocol (
> + &gEfiSpiProtocolGuid,
> + NULL,
> + (VOID **)&mSpiProtocol
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gBS->CreateEventEx (
> + EVT_NOTIFY_SIGNAL,
> + TPL_NOTIFY,
> + LibFvbFlashDeviceVirtualAddressChangeNotifyEvent,
> + NULL,
> + &gEfiEventVirtualAddressChangeGuid,
> + &Event
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + } else {
> + Status = gBS->LocateProtocol (
> + &gEfiSmmSpiProtocolGuid,
> + NULL,
> + (VOID **)&mSpiProtocol
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> +
> + for (FlashIndex = EnumSpiFlashW25Q64; FlashIndex < EnumSpiFlashMax;
> FlashIndex++) {
> + Status = mSpiProtocol->Init (mSpiProtocol, &(mInitTable[FlashIndex]));
> + if (!EFI_ERROR (Status)) {
> + //
> + // Read Vendor/Device IDs to check if the driver supports the Serial Flash
> device.
> + //
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_READ_ID,
> + SPI_WREN,
> + TRUE,
> + FALSE,
> + FALSE,
> + 0,
> + 3,
> + SfId,
> + EnumSpiRegionAll
> + );
> + if (!EFI_ERROR (Status)) {
> + if ((SfId[0] == mInitTable[FlashIndex].VendorId) &&
> + (SfId[1] == mInitTable[FlashIndex].DeviceId0) &&
> + (SfId[2] == mInitTable[FlashIndex].DeviceId1)) {
> + //
> + // Found a matching SPI device, FlashIndex now contains flash device.
> + //
> + DEBUG ((EFI_D_ERROR, "OK - Found SPI Flash Type in SPI Flash Driver,
> Device Type ID 0 = 0x%02x!\n", mInitTable[FlashIndex].DeviceId0));
> + DEBUG ((EFI_D_ERROR, "Device Type ID 1 = 0x%02x!\n",
> mInitTable[FlashIndex].DeviceId1));
> +
> + if (mInitTable[FlashIndex].BiosStartOffset == (UINTN) (-1)) {
> + DEBUG ((EFI_D_ERROR, "ERROR - The size of BIOS image is bigger
> than SPI Flash device!\n"));
> + CpuDeadLoop ();
> + }
> + break;
> + } else {
> + SpiNotMatchError++;
> + }
> + } else {
> + SpiReadError++;
> + }
> + }
> + }
> +
> + DEBUG ((EFI_D_ERROR, "SPI flash chip VID = 0x%X, DID0 = 0x%X, DID1 =
> 0x%X\n", SfId[0], SfId[1], SfId[2]));
> +
> + if (FlashIndex < EnumSpiFlashMax) {
> + return EFI_SUCCESS;
> + } else {
> + if (SpiReadError != 0) {
> + DEBUG ((EFI_D_ERROR, "ERROR - SPI Read ID execution failed! Error
> Count = %d\n", SpiReadError));
> + }
> + else {
> + if (SpiNotMatchError != 0) {
> + DEBUG ((EFI_D_ERROR, "ERROR - No supported SPI flash chip found!
> Error Count = %d\n", SpiNotMatchError));
> + DEBUG ((EFI_D_ERROR, "SPI flash chip VID = 0x%X, DID0 = 0x%X, DID1 =
> 0x%X\n", SfId[0], SfId[1], SfId[2]));
> + }
> + }
> + return EFI_UNSUPPORTED;
> + }
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitio
> ns.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitio
> ns.h
> new file mode 100644
> index 0000000000..c20ee6e372
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitio
> ns.h
> @@ -0,0 +1,835 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +**/
> +
> +#include <Library/SpiFlash.H>
> +
> +#define FLASH_SIZE 0x400000
> +#define FLASH_DEVICE_BASE_ADDRESS (0xFFFFFFFF-FLASH_SIZE+1)
> +
> +//
> +// Serial Flash device initialization data table provided to the
> +// Intel(R) SPI Host Controller Compatibility Interface.
> +//
> +SPI_INIT_TABLE mInitTable[] = {
> + {
> + SF_VENDOR_ID_WINBOND, // VendorId
> + SF_DEVICE_ID0_W25QXX, // DeviceId 0
> + SF_DEVICE_ID1_W25Q64, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read
> ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2:
> Read Status Register
> + {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz,
> EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash
> Discovery Parameters
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((WINBOND_W25Q64_SIZE >= FLASH_SIZE) ? WINBOND_W25Q64_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_ATMEL, // VendorId
> + SF_DEVICE_ID0_AT25DF321A, // DeviceId 0
> + SF_DEVICE_ID1_AT25DF321A, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR).
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read
> ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2:
> Read Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (32KB)
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((ATMEL_AT25DF321A_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF321A_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_ATMEL, // VendorId
> + SF_DEVICE_ID0_AT26DF321, // DeviceId 0
> + SF_DEVICE_ID1_AT26DF321, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR).
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read
> ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2:
> Read Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (32KB)
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((ATMEL_AT26DF321_SIZE >= FLASH_SIZE) ? ATMEL_AT26DF321_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_ATMEL, // VendorId
> + SF_DEVICE_ID0_AT25DF641, // DeviceId 0
> + SF_DEVICE_ID1_AT25DF641, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR).
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read
> ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2:
> Read Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (32KB)
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((ATMEL_AT25DF641_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF641_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_WINBOND, // VendorId
> + SF_DEVICE_ID0_W25QXX, // DeviceId 0
> + SF_DEVICE_ID1_W25Q16, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read
> ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2:
> Read Status Register
> + {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz,
> EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash
> Discovery Parameters
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((WINBOND_W25Q16_SIZE >= FLASH_SIZE) ? WINBOND_W25Q16_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_WINBOND, // VendorId
> + SF_DEVICE_ID0_W25QXX, // DeviceId 0
> + SF_DEVICE_ID1_W25Q32, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register.
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read
> ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2:
> Read Status Register
> + {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz,
> EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash
> Discovery Parameters
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((WINBOND_W25Q32_SIZE >= FLASH_SIZE) ? WINBOND_W25Q32_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_WINBOND, // VendorId
> + SF_DEVICE_ID0_W25XXX, // DeviceId 0
> + SF_DEVICE_ID1_W25X32, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read
> ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2:
> Read Status Register
> + {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz,
> EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash
> Discovery Parameters
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((WINBOND_W25X32_SIZE >= FLASH_SIZE) ? WINBOND_W25X32_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_WINBOND, // VendorId
> + SF_DEVICE_ID0_W25XXX, // DeviceId 0
> + SF_DEVICE_ID1_W25X64, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz,
> EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash
> Discovery Parameters
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((WINBOND_W25X64_SIZE >= FLASH_SIZE) ? WINBOND_W25X64_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_WINBOND, // VendorId
> + SF_DEVICE_ID0_W25QXX, // DeviceId 0
> + SF_DEVICE_ID1_W25Q128, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read
> ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2:
> Read Status Register
> + {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz,
> EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash
> Discovery Parameters
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((WINBOND_W25Q128_SIZE >= FLASH_SIZE) ? WINBOND_W25Q128_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_MACRONIX, // VendorId
> + SF_DEVICE_ID0_MX25LXX, // DeviceId 0
> + SF_DEVICE_ID1_MX25L16, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR).
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz,
> EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash
> Discovery Parameters
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((MACRONIX_MX25L16_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L16_SIZE
> - FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_MACRONIX, // VendorId
> + SF_DEVICE_ID0_MX25LXX, // DeviceId 0
> + SF_DEVICE_ID1_MX25L32, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR).
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz,
> EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash
> Discovery Parameters
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((MACRONIX_MX25L32_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L32_SIZE
> - FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_MACRONIX, // VendorId
> + SF_DEVICE_ID0_MX25LXX, // DeviceId 0
> + SF_DEVICE_ID1_MX25L64, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR)
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz,
> EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash
> Discovery Parameters
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((MACRONIX_MX25L64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L64_SIZE
> - FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_MACRONIX, // VendorId
> + SF_DEVICE_ID0_MX25LXX, // DeviceId 0
> + SF_DEVICE_ID1_MX25L128, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR)
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz,
> EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash
> Discovery Parameters
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((MACRONIX_MX25L128_SIZE >= FLASH_SIZE) ?
> MACRONIX_MX25L128_SIZE - FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_MACRONIX, // VendorId
> + SF_DEVICE_ID0_MX25UXX, // DeviceId 0
> + SF_DEVICE_ID1_MX25U6435F, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Write Enable
> (this part doesn't support EWSR)
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId },
> // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ,
> EnumSpiCycle33MHz, EnumSpiOperationReadData },
> // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, //
> Opcode 2: Read Status Register
> + {EnumSpiOpcodeRead, SF_INST_SFDP,
> EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},
> // Opcode 3: Serial Flash Discovery Parameters
> + {EnumSpiOpcodeWrite, SF_INST_SERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, //
> Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, //
> Opcode 5: Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG,
> EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
> // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, //
> Opcode 7: Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((MACRONIX_MX25U64_SIZE >= FLASH_SIZE) ?
> MACRONIX_MX25U64_SIZE - FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_SST, // VendorId
> + SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
> + SF_DEVICE_ID1_SST25VF016B,// DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read
> ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2:
> Read Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (32KB)
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((SST_SST25VF016B_SIZE >= FLASH_SIZE) ? SST_SST25VF016B_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_SST, // VendorId
> + SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
> + SF_DEVICE_ID1_SST25VF064C,// DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read
> ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2:
> Read Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (32KB)
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((SST_SST25VF064C_SIZE >= FLASH_SIZE) ? SST_SST25VF064C_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + //
> + // Minnow2 SPI type
> + //
> + SF_VENDOR_ID_NUMONYX, // VendorId
> + SF_DEVICE_ID0_N25Q064, // DeviceId 0
> + SF_DEVICE_ID1_N25Q064, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR)
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle20MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle20MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle20MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle20MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle20MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle20MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle20MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE
> - FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_NUMONYX, // VendorId
> + SF_DEVICE_ID0_M25PXXX, // DeviceId 0
> + SF_DEVICE_ID1_M25PX16, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR).
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((NUMONYX_M25PX16_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX16_SIZE
> - FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_NUMONYX, // VendorId
> + SF_DEVICE_ID0_N25QXXX, // DeviceId 0
> + SF_DEVICE_ID1_N25Q032, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR).
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read
> ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2:
> Read Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((NUMONYX_N25Q032_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q032_SIZE
> - FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_NUMONYX, // VendorId
> + SF_DEVICE_ID0_M25PXXX, // DeviceId 0
> + SF_DEVICE_ID1_M25PX32, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR).
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((NUMONYX_M25PX32_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX32_SIZE
> - FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_NUMONYX, // VendorId
> + SF_DEVICE_ID0_M25PXXX, // DeviceId 0
> + SF_DEVICE_ID1_M25PX64, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR)
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((NUMONYX_M25PX64_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX64_SIZE
> - FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_NUMONYX, // VendorId
> + SF_DEVICE_ID0_N25QXXX, // DeviceId 0
> + SF_DEVICE_ID1_N25Q128, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR)
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((NUMONYX_N25Q128_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q128_SIZE
> - FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_EON, // VendorId
> + SF_DEVICE_ID0_EN25QXX, // DeviceId 0
> + SF_DEVICE_ID1_EN25Q16, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR)
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((EON_EN25Q16_SIZE >= FLASH_SIZE) ? EON_EN25Q16_SIZE - FLASH_SIZE :
> (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_EON, // VendorId
> + SF_DEVICE_ID0_EN25QXX, // DeviceId 0
> + SF_DEVICE_ID1_EN25Q32, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR)
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((EON_EN25Q32_SIZE >= FLASH_SIZE) ? EON_EN25Q32_SIZE - FLASH_SIZE :
> (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_EON, // VendorId
> + SF_DEVICE_ID0_EN25QXX, // DeviceId 0
> + SF_DEVICE_ID1_EN25Q64, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR).
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((EON_EN25Q64_SIZE >= FLASH_SIZE) ? EON_EN25Q64_SIZE - FLASH_SIZE :
> (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_EON, // VendorId
> + SF_DEVICE_ID0_EN25QXX, // DeviceId 0
> + SF_DEVICE_ID1_EN25Q128, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR)
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((EON_EN25Q128_SIZE >= FLASH_SIZE) ? EON_EN25Q128_SIZE -
> FLASH_SIZE : (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + },
> + {
> + SF_VENDOR_ID_AMIC, // VendorId
> + SF_DEVICE_ID0_A25L016, // DeviceId 0
> + SF_DEVICE_ID1_A25L016, // DeviceId 1
> + {
> + SF_INST_WREN, // Prefix Opcode 0: Write Enable
> + SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't
> support EWSR)
> + },
> + {
> + {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID,
> EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
> + {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz,
> EnumSpiOperationReadData }, // Opcode 1: Read
> + {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR,
> EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read
> Status Register
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI,
> EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3:
> Write Disable
> + {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz,
> EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
> + {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE,
> EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5:
> Block Erase (64KB
> + {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz,
> EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
> + {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,
> EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7:
> Write Status Register
> + },
> +
> + //
> + // The offset of the start of the BIOS image in flash. This value is platform
> specific
> + // and depends on the system flash map. If BIOS size is bigger than flash
> return -1.
> + //
> + ((AMIC_A25L16_SIZE >= FLASH_SIZE) ? AMIC_A25L16_SIZE - FLASH_SIZE :
> (UINTN) (-1)),
> +
> + //
> + // The size of the BIOS image in flash. This value is platform specific and
> depends on the system flash map.
> + //
> + FLASH_SIZE
> + }
> +};
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c
> new file mode 100644
> index 0000000000..85f066a9e3
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c
> @@ -0,0 +1,46 @@
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + I2CLib.c
> +
> +
> +
> +--*/
> +#ifdef ECP_FLAG
> +#include "EdkIIGlueDxe.h"
> +#else
> +#include <Library/DebugLib.h>
> +#include <Library/TimerLib.h>
> +#endif
> +#include <PchRegs/PchRegsPcu.h>
> +#include <PchRegs.h>
> +#include <PlatformBaseAddresses.h>
> +#include <PchRegs/PchRegsLpss.h>
> +#ifdef ECP_FLAG
> +#include "I2CLib.h"
> +#else
> +#include <Library/I2CLib.h>
> +#endif
> +#include <Protocol/GlobalNvsArea.h>
> +#ifndef ECP_FLAG
> +#include <Library/UefiBootServicesTableLib.h>
> +#endif
> +
> +EFI_STATUS ByteReadI2C(
> + IN UINT8 BusNo,
> + IN UINT8 SlaveAddress,
> + IN UINT8 Offset,
> + IN UINTN ReadBytes,
> + OUT UINT8 *ReadBuffer
> + )
> +{
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
> new file mode 100644
> index 0000000000..d669a4eaf8
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
> @@ -0,0 +1,39 @@
> +## @file
> +# Null instance of Debug Agent Library with empty functions.
> +#
> +# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = I2CLib
> + FILE_GUID = 7f62bf44-2ba7-4c2d-9d4a-91c8906ff053
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = I2CLib
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources.common]
> + I2CLib.c
> +
> +[LibraryClasses]
> + BaseLib
> + IoLib
> + TimerLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[Protocols]
> + gEfiGlobalNvsAreaProtocolGuid
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLib.c
> new file mode 100644
> index 0000000000..104c2ded43
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLib.c
> @@ -0,0 +1,735 @@
> +/** @file
> + Functions for accessing I2C registers.
> +
> + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +--*/
> +
> +#include <Library/DebugLib.h>
> +#include <Library/TimerLib.h>
> +#include <PchRegs/PchRegsPcu.h>
> +#include <PchRegs.h>
> +#include <PlatformBaseAddresses.h>
> +#include <PchRegs/PchRegsLpss.h>
> +#include <Library/I2CLib.h>
> +#include <Protocol/GlobalNvsArea.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <I2CRegs.h>
> +
> +#define GLOBAL_NVS_OFFSET(Field)
> (UINTN)((CHAR8*)&((EFI_GLOBAL_NVS_AREA*)0)->Field - (CHAR8*)0)
> +
> +#define PCIEX_BASE_ADDRESS 0xE0000000
> +#define PCI_EXPRESS_BASE_ADDRESS ((VOID *) (UINTN)
> PCIEX_BASE_ADDRESS)
> +#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
> + ((UINTN)PCI_EXPRESS_BASE_ADDRESS + \
> + (UINTN)(Bus << 20) + \
> + (UINTN)(Device << 15) + \
> + (UINTN)(Function << 12) + \
> + (UINTN)(Register) \
> + )
> +#define PCI_D31F0_REG_BASE PCIEX_BASE_ADDRESS + (UINT32) (31
> << 15)
> +
> +typedef struct _LPSS_PCI_DEVICE_INFO {
> + UINTN Segment;
> + UINTN BusNum;
> + UINTN DeviceNum;
> + UINTN FunctionNum;
> + UINTN Bar0;
> + UINTN Bar1;
> +} LPSS_PCI_DEVICE_INFO;
> +
> +LPSS_PCI_DEVICE_INFO mLpssPciDeviceList[] = {
> + {0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1,
> PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC, 0xFE900000, 0xFE908000},
> + {0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
> PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0, 0xFE910000, 0xFE918000},
> + {0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
> PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1, 0xFE920000, 0xFE928000},
> + {0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
> PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2, 0xFE930000, 0xFE938000},
> + {0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
> PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3, 0xFE940000, 0xFE948000},
> + {0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
> PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4, 0xFE950000, 0xFE958000},
> + {0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
> PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5, 0xFE960000, 0xFE968000},
> + {0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
> PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6, 0xFE970000, 0xFE978000}
> +};
> +
> +#define LPSS_PCI_DEVICE_NUMBER
> sizeof(mLpssPciDeviceList)/sizeof(LPSS_PCI_DEVICE_INFO)
> +
> +STATIC UINTN mI2CBaseAddress = 0;
> +STATIC UINT16 mI2CSlaveAddress = 0;
> +
> +UINT16 mI2cMode=B_IC_RESTART_EN | B_IC_SLAVE_DISABLE |
> B_MASTER_MODE ;
> +
> +UINTN mI2cNvsBaseAddress[] = {
> + GLOBAL_NVS_OFFSET(LDMA2Addr),
> + GLOBAL_NVS_OFFSET(I2C1Addr),
> + GLOBAL_NVS_OFFSET(I2C2Addr),
> + GLOBAL_NVS_OFFSET(I2C3Addr),
> + GLOBAL_NVS_OFFSET(I2C4Addr),
> + GLOBAL_NVS_OFFSET(I2C5Addr),
> + GLOBAL_NVS_OFFSET(I2C6Addr),
> + GLOBAL_NVS_OFFSET(I2C7Addr)
> + };
> +
> +/**
> + This function get I2Cx controller base address (BAR0).
> +
> + @param I2cControllerIndex Bus Number of I2C controller.
> +
> + @return I2C BAR.
> +**/
> +UINTN
> +GetI2cBarAddr(
> + IN UINT8 I2cControllerIndex
> + )
> +{
> + EFI_STATUS Status;
> + EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
> + UINTN AcpiBaseAddr;
> + UINTN PciMmBase=0;
> +
> + ASSERT(gBS!=NULL);
> +
> + Status = gBS->LocateProtocol (
> + &gEfiGlobalNvsAreaProtocolGuid,
> + NULL,
> + &GlobalNvsArea
> + );
> +
> + //
> + // PCI mode from PEI ( Global NVS is not ready).
> + //
> + if (EFI_ERROR(Status)) {
> + DEBUG ((EFI_D_INFO, "GetI2cBarAddr()
> gEfiGlobalNvsAreaProtocolGuid:%r\n", Status));
> + //
> + // Global NVS is not ready.
> + //
> + return 0;
> + }
> +
> + AcpiBaseAddr = *(UINTN*)((CHAR8*)GlobalNvsArea->Area +
> mI2cNvsBaseAddress[I2cControllerIndex + 1]);
> +
> + //
> + //PCI mode from DXE (global NVS protocal) to LPSS OnReadytoBoot(swith
> to ACPI).
> + //
> + if(AcpiBaseAddr==0) {
> + PciMmBase = MmPciAddress (
> + mLpssPciDeviceList[I2cControllerIndex + 1].Segment,
> + mLpssPciDeviceList[I2cControllerIndex + 1].BusNum,
> + mLpssPciDeviceList[I2cControllerIndex + 1].DeviceNum,
> + mLpssPciDeviceList[I2cControllerIndex + 1].FunctionNum,
> + 0
> + );
> + DEBUG((EFI_D_ERROR, "\nGetI2cBarAddr() I2C Device %x %x %x
> PciMmBase:%x\n", \
> + mLpssPciDeviceList[I2cControllerIndex + 1].BusNum, \
> + mLpssPciDeviceList[I2cControllerIndex + 1].DeviceNum, \
> + mLpssPciDeviceList[I2cControllerIndex + 1].FunctionNum,
> PciMmBase));
> +
> + if (MmioRead32 (PciMmBase) != 0xFFFFFFFF) {
> + if((MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_STSCMD)&
> B_PCH_LPSS_I2C_STSCMD_MSE)) {
> + //
> + // Get the address allocted.
> + //
> + mLpssPciDeviceList[I2cControllerIndex + 1].Bar0=MmioRead32
> (PciMmBase+R_PCH_LPSS_I2C_BAR);
> + mLpssPciDeviceList[I2cControllerIndex + 1].Bar1=MmioRead32
> (PciMmBase+R_PCH_LPSS_I2C_BAR1);
> + }
> + }
> + AcpiBaseAddr =mLpssPciDeviceList[I2cControllerIndex+1].Bar0;
> + }
> +
> + //
> + // ACPI mode from BDS: LPSS OnReadytoBoot
> + //
> + else {
> + DEBUG ((EFI_D_INFO, "GetI2cBarAddr() NVS Varialable is updated by this
> LIB or LPSS \n"));
> + }
> +
> + DEBUG ((EFI_D_INFO, "GetI2cBarAddr() I2cControllerIndex+1 0x%x
> AcpiBaseAddr:0x%x \n", (I2cControllerIndex + 1), AcpiBaseAddr));
> + return AcpiBaseAddr;
> +}
> +
> +
> +/**
> + This function enables I2C controllers.
> +
> + @param I2cControllerIndex Bus Number of I2C controllers.
> +
> + @return Result of the I2C initialization.
> +**/
> +EFI_STATUS
> +ProgramPciLpssI2C (
> + IN UINT8 I2cControllerIndex
> + )
> +{
> + UINT32 PmcBase;
> + UINTN PciMmBase=0;
> + EFI_STATUS Status;
> + EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
> +
> + UINT32 PmcFunctionDsiable[]= {
> + B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1,
> + B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2,
> + B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3,
> + B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4,
> + B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5,
> + B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6,
> + B_PCH_PMC_FUNC_DIS_LPSS2_FUNC7
> + };
> +
> + DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() Start\n"));
> +
> + //
> + // Set the VLV Function Disable Register to ZERO
> + //
> + PmcBase = MmioRead32 (PCI_D31F0_REG_BASE + R_PCH_LPC_PMC_BASE)
> & B_PCH_LPC_PMC_BASE_BAR;
> +
> if(MmioRead32(PmcBase+R_PCH_PMC_FUNC_DIS)&PmcFunctionDsiable[I2
> cControllerIndex]) {
> + DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() End:I2C[%x] is
> disabled\n",I2cControllerIndex));
> + return EFI_NOT_READY;
> + }
> +
> + DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C()------------
> I2cControllerIndex=%x,PMC=%x\n",I2cControllerIndex,MmioRead32(PmcBa
> se+R_PCH_PMC_FUNC_DIS)));
> +
> + {
> + PciMmBase = MmPciAddress (
> + mLpssPciDeviceList[I2cControllerIndex+1].Segment,
> + mLpssPciDeviceList[I2cControllerIndex+1].BusNum,
> + mLpssPciDeviceList[I2cControllerIndex+1].DeviceNum,
> + mLpssPciDeviceList[I2cControllerIndex+1].FunctionNum,
> + 0
> + );
> +
> + DEBUG((EFI_D_ERROR, "Program Pci Lpss I2C Device %x %x %x
> PciMmBase:%x\n", \
> + mLpssPciDeviceList[I2cControllerIndex+1].BusNum, \
> + mLpssPciDeviceList[I2cControllerIndex+1].DeviceNum, \
> + mLpssPciDeviceList[I2cControllerIndex+1].FunctionNum, PciMmBase));
> +
> + if (MmioRead32 (PciMmBase) != 0xFFFFFFFF) {
> + if((MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_STSCMD)&
> B_PCH_LPSS_I2C_STSCMD_MSE)) {
> + //
> + // Get the address allocted.
> + //
> + mLpssPciDeviceList[I2cControllerIndex+1].Bar0=MmioRead32
> (PciMmBase+R_PCH_LPSS_I2C_BAR);
> + mLpssPciDeviceList[I2cControllerIndex+1].Bar1=MmioRead32
> (PciMmBase+R_PCH_LPSS_I2C_BAR1);
> + DEBUG((EFI_D_ERROR, "ProgramPciLpssI2C() bar0:0x%x
> bar1:0x%x\n",mLpssPciDeviceList[I2cControllerIndex+1].Bar0,
> mLpssPciDeviceList[I2cControllerIndex+1].Bar1));
> + } else {
> +
> + //
> + // Program BAR 0
> + //
> + ASSERT (((mLpssPciDeviceList[I2cControllerIndex+1].Bar0 &
> B_PCH_LPSS_I2C_BAR_BA) ==
> mLpssPciDeviceList[I2cControllerIndex+1].Bar0) &&
> (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 != 0));
> + MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR), (UINT32)
> (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 &
> B_PCH_LPSS_I2C_BAR_BA));
> +
> + //
> + // Program BAR 1
> + //
> + ASSERT (((mLpssPciDeviceList[I2cControllerIndex+1].Bar1 &
> B_PCH_LPSS_I2C_BAR1_BA) ==
> mLpssPciDeviceList[I2cControllerIndex+1].Bar1) &&
> (mLpssPciDeviceList[I2cControllerIndex+1].Bar1 != 0));
> + MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR1),
> (UINT32) (mLpssPciDeviceList[I2cControllerIndex+1].Bar1 &
> B_PCH_LPSS_I2C_BAR1_BA));
> +
> + //
> + // Bus Master Enable & Memory Space Enable
> + //
> + MmioOr32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_STSCMD),
> (UINT32) (B_PCH_LPSS_I2C_STSCMD_BME |
> B_PCH_LPSS_I2C_STSCMD_MSE));
> + ASSERT (MmioRead32
> (mLpssPciDeviceList[I2cControllerIndex+1].Bar0) != 0xFFFFFFFF);
> + }
> +
> + //
> + // Release Resets
> + //
> + MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 +
> R_PCH_LPIO_I2C_MEM_RESETS,(B_PCH_LPIO_I2C_MEM_RESETS_FUNC |
> B_PCH_LPIO_I2C_MEM_RESETS_APB));
> +
> + //
> + // Activate Clocks
> + //
> + MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 +
> R_PCH_LPSS_I2C_MEM_PCP,0x80020003);//No use for A0
> +
> + DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() Programmed()\n"));
> + }
> +
> + //
> + // BDS: already switched to ACPI mode
> + //
> + else {
> + ASSERT(gBS!=NULL);
> + Status = gBS->LocateProtocol (
> + &gEfiGlobalNvsAreaProtocolGuid,
> + NULL,
> + &GlobalNvsArea
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG ((EFI_D_INFO, "GetI2cBarAddr()
> gEfiGlobalNvsAreaProtocolGuid:%r\n", Status));
> + //
> + // gEfiGlobalNvsAreaProtocolGuid is not ready.
> + //
> + return 0;
> + }
> + mLpssPciDeviceList[I2cControllerIndex + 1].Bar0 =
> *(UINTN*)((CHAR8*)GlobalNvsArea->Area +
> mI2cNvsBaseAddress[I2cControllerIndex + 1]);
> + DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C(): is switched to ACPI 0x:%x
> \n",mLpssPciDeviceList[I2cControllerIndex + 1].Bar0));
> + }
> + }
> +
> + DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() End\n"));
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Disable I2C Bus.
> +
> + @param VOID.
> +
> + @return Result of the I2C disabling.
> +**/
> +RETURN_STATUS
> +I2cDisable (
> + VOID
> + )
> +{
> + //
> + // 0.1 seconds
> + //
> + UINT32 NumTries = 10000;
> +
> + MmioWrite32 ( mI2CBaseAddress + R_IC_ENABLE, 0 );
> + while ( 0 != ( MmioRead32 ( mI2CBaseAddress + R_IC_ENABLE_STATUS) &
> 1)) {
> + MicroSecondDelay (10);
> + NumTries --;
> + if(0 == NumTries) {
> + return RETURN_NOT_READY;
> + }
> + }
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Enable I2C Bus.
> +
> + @param VOID.
> +
> + @return Result of the I2C disabling.
> +**/
> +RETURN_STATUS
> +I2cEnable (
> + VOID
> + )
> +{
> + //
> + // 0.1 seconds
> + //
> + UINT32 NumTries = 10000;
> +
> + MmioWrite32 (mI2CBaseAddress + R_IC_ENABLE, 1);
> +
> + while (0 == (MmioRead32 (mI2CBaseAddress + R_IC_ENABLE_STATUS) &
> 1)) {
> + MicroSecondDelay (10);
> + NumTries --;
> + if(0 == NumTries){
> + return RETURN_NOT_READY;
> + }
> + }
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Enable I2C Bus.
> +
> + @param VOID.
> +
> + @return Result of the I2C enabling.
> +**/
> +RETURN_STATUS
> +I2cBusFrequencySet (
> + IN UINTN BusClockHertz
> + )
> +{
> + DEBUG((EFI_D_INFO,"InputFreq BusClockHertz: %d\r\n",BusClockHertz));
> +
> + //
> + // Set the 100 KHz clock divider according to SV result and I2C spec
> + //
> + MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_HCNT, (UINT16)0x214 );
> + MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_LCNT, (UINT16)0x272 );
> +
> + //
> + // Set the 400 KHz clock divider according to SV result and I2C spec
> + //
> + MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_HCNT, (UINT16)0x50 );
> + MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_LCNT, (UINT16)0xAD );
> +
> + switch ( BusClockHertz ) {
> + case 100 * 1000:
> + MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD,
> (UINT16)0x40);//100K
> + mI2cMode = V_SPEED_STANDARD;
> + break;
> + case 400 * 1000:
> + MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD,
> (UINT16)0x32);//400K
> + mI2cMode = V_SPEED_FAST;
> + break;
> + default:
> + MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD,
> (UINT16)0x09);//3.4M
> + mI2cMode = V_SPEED_HIGH;
> + }
> +
> + //
> + // Select the frequency counter,
> + // Enable restart condition,
> + // Enable master FSM, disable slave FSM.
> + //
> + mI2cMode |= B_IC_RESTART_EN | B_IC_SLAVE_DISABLE |
> B_MASTER_MODE;
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Initializes the host controller to execute I2C commands.
> +
> + @param I2cControllerIndex Index of I2C controller in LPSS device. 0
> represents I2C0, which is PCI function 1 of LPSS device.
> +
> + @return EFI_SUCCESS Opcode initialization on the I2C host controller
> completed.
> + @return EFI_DEVICE_ERROR Device error, operation failed.
> +**/
> +EFI_STATUS
> +I2CInit (
> + IN UINT8 I2cControllerIndex,
> + IN UINT16 SlaveAddress
> + )
> +{
> + EFI_STATUS Status=RETURN_SUCCESS;
> + UINT32 NumTries = 0;
> + UINTN GnvsI2cBarAddr=0;
> +
> + //
> + // Verify the parameters
> + //
> + if ((1023 < SlaveAddress) || (6 < I2cControllerIndex)) {
> + Status = RETURN_INVALID_PARAMETER;
> + DEBUG((EFI_D_INFO,"I2CInit Exit with
> RETURN_INVALID_PARAMETER\r\n"));
> + return Status;
> + }
> + MmioWrite32 ( mI2CBaseAddress + R_IC_TAR, (UINT16)SlaveAddress );
> + mI2CSlaveAddress = SlaveAddress;
> +
> + //
> + // 1.PEI: program and init ( before pci enumeration).
> + // 2.DXE:update address and re-init ( after pci enumeration).
> + // 3.BDS:update ACPI address and re-init ( after acpi mode is enabled).
> + //
> + if(mI2CBaseAddress == mLpssPciDeviceList[I2cControllerIndex + 1].Bar0) {
> +
> + //
> + // I2CInit is already called.
> + //
> + GnvsI2cBarAddr=GetI2cBarAddr(I2cControllerIndex);
> +
> + if((GnvsI2cBarAddr == 0)||(GnvsI2cBarAddr == mI2CBaseAddress)) {
> + DEBUG((EFI_D_INFO,"I2CInit Exit with mI2CBaseAddress:%x ==
> [%x].Bar0\r\n",mI2CBaseAddress,I2cControllerIndex+1));
> + return RETURN_SUCCESS;
> + }
> + }
> +
> + Status=ProgramPciLpssI2C(I2cControllerIndex);
> + if(Status!=EFI_SUCCESS) {
> + return Status;
> + }
> +
> +
> + mI2CBaseAddress = (UINT32) mLpssPciDeviceList[I2cControllerIndex +
> 1].Bar0;
> + DEBUG ((EFI_D_ERROR, "mI2CBaseAddress = 0x%x
> \n",mI2CBaseAddress));
> +
> + //
> + // 1 seconds.
> + //
> + NumTries = 10000;
> + while ((1 == ( MmioRead32 ( mI2CBaseAddress + R_IC_STATUS) &
> STAT_MST_ACTIVITY ))) {
> + MicroSecondDelay(10);
> + NumTries --;
> + if(0 == NumTries) {
> + DEBUG((EFI_D_INFO, "Try timeout\r\n"));
> + return RETURN_DEVICE_ERROR;
> + }
> + }
> +
> + Status = I2cDisable();
> + DEBUG((EFI_D_INFO, "I2cDisable Status = %r\r\n", Status));
> + I2cBusFrequencySet(400 * 1000);
> +
> + MmioWrite32(mI2CBaseAddress + R_IC_INTR_MASK, 0x0);
> + if (0x7f < SlaveAddress )
> + SlaveAddress = ( SlaveAddress & 0x3ff ) | IC_TAR_10BITADDR_MASTER;
> + MmioWrite32 ( mI2CBaseAddress + R_IC_TAR, (UINT16)SlaveAddress );
> + MmioWrite32 ( mI2CBaseAddress + R_IC_RX_TL, 0);
> + MmioWrite32 ( mI2CBaseAddress + R_IC_TX_TL, 0 );
> + MmioWrite32 ( mI2CBaseAddress + R_IC_CON, mI2cMode);
> + Status = I2cEnable();
> +
> + DEBUG((EFI_D_INFO, "I2cEnable Status = %r\r\n", Status));
> + MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT );
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Reads a Byte from I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has
> been connected
> + @param SlaveAddress Device Address from which the byte value has to
> be read
> + @param Offset Offset from which the data has to be read
> + @param *Byte Address to which the value read has to be stored
> + @param Start Whether a RESTART is issued before the byte is sent
> or received
> + @param End Whether STOP is generated after a data byte is sent
> or received
> +
> + @return EFI_SUCCESS IF the byte value has been successfully read
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS
> +ByteReadI2CBasic(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINTN ReadBytes,
> + OUT UINT8 *ReadBuffer,
> + IN UINT8 Start,
> + IN UINT8 End
> + )
> +{
> +
> + EFI_STATUS Status;
> + UINT32 I2cStatus;
> + UINT16 ReceiveData;
> + UINT8 *ReceiveDataEnd;
> + UINT8 *ReceiveRequest;
> + UINT16 RawIntrStat;
> + UINT32 Count=0;
> +
> + Status = EFI_SUCCESS;
> +
> + ReceiveDataEnd = &ReadBuffer [ReadBytes];
> + if( ReadBytes ) {
> +
> + ReceiveRequest = ReadBuffer;
> + DEBUG((EFI_D_INFO,"Read: ---------------%d bytes to
> RX\r\n",ReceiveDataEnd - ReceiveRequest));
> +
> + while ((ReceiveDataEnd > ReceiveRequest) || (ReceiveDataEnd >
> ReadBuffer)) {
> +
> + //
> + // Check for NACK
> + //
> + RawIntrStat = (UINT16)MmioRead32 (mI2CBaseAddress +
> R_IC_RawIntrStat);
> + if ( 0 != ( RawIntrStat & I2C_INTR_TX_ABRT )) {
> + MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT );
> + Status = RETURN_DEVICE_ERROR;
> + DEBUG((EFI_D_INFO,"TX ABRT ,%d bytes hasn't been
> transferred\r\n",ReceiveDataEnd - ReceiveRequest));
> + break;
> + }
> +
> + //
> + // Determine if another byte was received
> + //
> + I2cStatus = (UINT16)MmioRead32 (mI2CBaseAddress + R_IC_STATUS);
> + if (0 != ( I2cStatus & STAT_RFNE )) {
> + ReceiveData = (UINT16)MmioRead32 ( mI2CBaseAddress +
> R_IC_DATA_CMD );
> + *ReadBuffer++ = (UINT8)ReceiveData;
> + DEBUG((EFI_D_INFO,"MmioRead32 ,1 byte 0x:%x is
> received\r\n",ReceiveData));
> + }
> +
> + if(ReceiveDataEnd == ReceiveRequest) {
> + MicroSecondDelay ( FIFO_WRITE_DELAY );
> + DEBUG((EFI_D_INFO,"ReceiveDataEnd==ReceiveRequest------------
> %x\r\n",I2cStatus & STAT_RFNE));
> + Count++;
> + if(Count<1024) {
> + //
> + // To avoid sys hung without ul-pmc device on RVP,
> + // waiting the last request to get data and make (ReceiveDataEnd >
> ReadBuffer) =TRUE.
> + //
> + continue;
> + } else {
> + break;
> + }
> + }
> +
> + //
> + // Wait until a read request will fit.
> + //
> + if (0 == (I2cStatus & STAT_TFNF)) {
> + DEBUG((EFI_D_INFO,"Wait until a read request will fit\r\n"));
> + MicroSecondDelay (10);
> + continue;
> + }
> +
> + //
> + // Issue the next read request.
> + //
> + if(End && Start) {
> + MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD,
> B_READ_CMD|B_CMD_RESTART|B_CMD_STOP);
> + } else if (!End && Start) {
> + MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD,
> B_READ_CMD|B_CMD_RESTART);
> + } else if (End && !Start) {
> + MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD,
> B_READ_CMD|B_CMD_STOP);
> + } else if (!End && !Start) {
> + MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD);
> + }
> + MicroSecondDelay (FIFO_WRITE_DELAY);
> +
> + ReceiveRequest += 1;
> + }
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Writes a Byte to I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be written
> + @param Offset Offset from which the data has to be read
> + @param *Byte Address to which the value written is stored
> + @param Start Whether a RESTART is issued before the byte is sent
> or received
> + @param End Whether STOP is generated after a data byte is sent
> or received
> +
> + @return EFI_SUCCESS IF the byte value has been successfully written
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS ByteWriteI2CBasic(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINTN WriteBytes,
> + IN UINT8 *WriteBuffer,
> + IN UINT8 Start,
> + IN UINT8 End
> + )
> +{
> +
> + EFI_STATUS Status;
> + UINT32 I2cStatus;
> + UINT8 *TransmitEnd;
> + UINT16 RawIntrStat;
> + UINT32 Count=0;
> +
> + Status = EFI_SUCCESS;
> +
> + Status=I2CInit(I2cControllerIndex, SlaveAddress);
> + if(Status!=EFI_SUCCESS)
> + return Status;
> +
> + TransmitEnd = &WriteBuffer[WriteBytes];
> + if( WriteBytes ) {
> + DEBUG((EFI_D_INFO,"Write: --------------%d bytes to TX\r\n",TransmitEnd
> - WriteBuffer));
> + while (TransmitEnd > WriteBuffer) {
> + I2cStatus = MmioRead32 (mI2CBaseAddress + R_IC_STATUS);
> + RawIntrStat = (UINT16)MmioRead32 (mI2CBaseAddress +
> R_IC_RawIntrStat);
> + if (0 != ( RawIntrStat & I2C_INTR_TX_ABRT)) {
> + MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT);
> + Status = RETURN_DEVICE_ERROR;
> + DEBUG((EFI_D_ERROR,"TX ABRT TransmitEnd:0x%x
> WriteBuffer:0x%x\r\n", TransmitEnd, WriteBuffer));
> + break;
> + }
> + if (0 == (I2cStatus & STAT_TFNF)) {
> + //
> + // If TX not full , will send cmd or continue to wait
> + //
> + MicroSecondDelay (FIFO_WRITE_DELAY);
> + continue;
> + }
> +
> + if(End && Start) {
> + MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD,
> (*WriteBuffer++)|B_CMD_RESTART|B_CMD_STOP);
> + } else if (!End && Start) {
> + MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD,
> (*WriteBuffer++)|B_CMD_RESTART);
> + } else if (End && !Start) {
> + MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD,
> (*WriteBuffer++)|B_CMD_STOP);
> + } else if (!End && !Start ) {
> + MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD,
> (*WriteBuffer++));
> + }
> +
> + //
> + // Add a small delay to work around some odd behavior being seen.
> Without this delay bytes get dropped.
> + //
> + MicroSecondDelay ( FIFO_WRITE_DELAY );//wait after send cmd
> +
> + //
> + // Time out
> + //
> + while(1) {
> + RawIntrStat = MmioRead16 ( mI2CBaseAddress + R_IC_RawIntrStat );
> + if (0 != ( RawIntrStat & I2C_INTR_TX_ABRT)) {
> + MmioRead16 (mI2CBaseAddress + R_IC_CLR_TX_ABRT);
> + Status = RETURN_DEVICE_ERROR;
> + DEBUG((EFI_D_ERROR,"TX ABRT TransmitEnd:0x%x
> WriteBuffer:0x%x\r\n", TransmitEnd, WriteBuffer));
> + }
> + if(0 == MmioRead16(mI2CBaseAddress + R_IC_TXFLR)) break;
> +
> + MicroSecondDelay (FIFO_WRITE_DELAY);
> + Count++;
> + if(Count<1024) {
> + //
> + // to avoid sys hung without ul-pmc device on RVP.
> + // Waiting the last request to get data and make (ReceiveDataEnd >
> ReadBuffer) =TRUE.
> + //
> + continue;
> + } else {
> + break;
> + }
> + }//while( 1 )
> + }
> +
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Reads a Byte from I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be read
> + @param Offset Offset from which the data has to be read
> + @param ReadBytes Number of bytes to be read
> + @param *ReadBuffer Address to which the value read has to be
> stored
> +
> + @return EFI_SUCCESS IF the byte value has been successfully read
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS ByteReadI2C(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINT8 Offset,
> + IN UINTN ReadBytes,
> + OUT UINT8 *ReadBuffer
> + )
> +{
> + EFI_STATUS Status;
> +
> + DEBUG ((EFI_D_INFO, "ByteReadI2C:---offset:0x%x\n",Offset));
> + Status = ByteWriteI2CBasic(I2cControllerIndex,
> SlaveAddress,1,&Offset,TRUE,FALSE);
> + Status = ByteReadI2CBasic(I2cControllerIndex,
> SlaveAddress,ReadBytes,ReadBuffer,TRUE,TRUE);
> +
> + return Status;
> +}
> +
> +/**
> + Writes a Byte to I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be written
> + @param Offset Offset from which the data has to be written
> + @param WriteBytes Number of bytes to be written
> + @param *Byte Address to which the value written is stored
> +
> + @return EFI_SUCCESS IF the byte value has been successfully read
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS ByteWriteI2C(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINT8 Offset,
> + IN UINTN WriteBytes,
> + IN UINT8 *WriteBuffer
> + )
> +{
> + EFI_STATUS Status;
> +
> + DEBUG ((EFI_D_INFO, "ByteWriteI2C:---
> offset/bytes/buf:0x%x,0x%x,0x%x,0x%x\n",Offset,WriteBytes,WriteBuffer,
> *WriteBuffer));
> + Status = ByteWriteI2CBasic(I2cControllerIndex,
> SlaveAddress,1,&Offset,TRUE,FALSE);
> + Status = ByteWriteI2CBasic(I2cControllerIndex,
> SlaveAddress,WriteBytes,WriteBuffer,FALSE,TRUE);
> +
> + return Status;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLibDxe.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLibDxe.inf
> new file mode 100644
> index 0000000000..cd10f1de93
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CLibDxe.inf
> @@ -0,0 +1,39 @@
> +## @file
> +# Instance of I2C Library.
> +#
> +# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = I2CLib
> + FILE_GUID = 7f62bf44-2ba7-4c2d-9d4a-91c8906ff053
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = I2CLib|DXE_DRIVER DXE_RUNTIME_DRIVER
> UEFI_DRIVER UEFI_APPLICATION
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources.common]
> + I2CLib.c
> +
> +[LibraryClasses]
> + BaseLib
> + IoLib
> + TimerLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[Protocols]
> + gEfiGlobalNvsAreaProtocolGuid
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CRegs.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CRegs.h
> new file mode 100644
> index 0000000000..57455162f6
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CRegs.h
> @@ -0,0 +1,126 @@
> +/** @file
> + Register Definitions for I2C Driver/PEIM.
> +
> + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +--*/
> +
> +#ifndef I2C_REGS_H
> +#define I2C_REGS_H
> +
> +//
> +// FIFO write delay value.
> +//
> +#define FIFO_WRITE_DELAY 2
> +
> +//
> +// MMIO Register Definitions.
> +//
> +#define R_IC_CON ( 0x00) // I2C Control
> +#define B_IC_RESTART_EN BIT5
> +#define B_IC_SLAVE_DISABLE BIT6
> +#define V_SPEED_STANDARD 0x02
> +#define V_SPEED_FAST 0x04
> +#define V_SPEED_HIGH 0x06
> +#define B_MASTER_MODE BIT0
> +
> +#define R_IC_TAR ( 0x04) // I2C Target Address
> +#define IC_TAR_10BITADDR_MASTER BIT12
> +
> +#define R_IC_SAR ( 0x08) // I2C Slave Address
> +#define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code
> Address
> +#define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and
> Command
> +
> +#define B_READ_CMD BIT8 // 1 = read, 0 = write
> +#define B_CMD_STOP BIT9 // 1 = STOP
> +#define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
> +
> +#define V_WRITE_CMD_MASK ( 0xFF)
> +
> +#define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock
> SCL High Count
> +#define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock
> SCL Low Count
> +#define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL
> High Count
> +#define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL
> Low Count
> +#define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL
> High Count
> +#define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL
> Low Count
> +#define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status
> +#define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask
> +#define I2C_INTR_GEN_CALL BIT11 // General call received
> +#define I2C_INTR_START_DET BIT10
> +#define I2C_INTR_STOP_DET BIT9
> +#define I2C_INTR_ACTIVITY BIT8
> +#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
> +#define I2C_INTR_TX_EMPTY BIT4
> +#define I2C_INTR_TX_OVER BIT3
> +#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over
> threshold
> +#define I2C_INTR_RX_OVER BIT1
> +#define I2C_INTR_RX_UNDER BIT0
> +#define R_IC_RawIntrStat ( 0x34) // I2C Raw Interrupt Status
> +#define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold
> +#define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold
> +#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual
> Interrupts
> +#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER
> Interrupt
> +#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt
> +#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt
> +#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
> +#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
> +#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt
> +#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
> +#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt
> +#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET
> interrupt
> +#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt
> +#define R_IC_ENABLE ( 0x6C) // I2C Enable
> +#define R_IC_STATUS ( 0x70) // I2C Status
> +
> +#define R_IC_SDA_HOLD ( 0x7C) // I2C
> IC_DEFAULT_SDA_HOLD//16bits
> +
> +#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.
> +#define STAT_RFF BIT4 // RX FIFO is completely full
> +#define STAT_RFNE BIT3 // RX FIFO is not empty
> +#define STAT_TFE BIT2 // TX FIFO is completely empty
> +#define STAT_TFNF BIT1 // TX FIFO is not full
> +
> +#define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register
> +#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
> +#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort
> Status Register
> +#define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate
> SLV_DATA_NACK Register
> +#define R_IC_DMA_CR ( 0x88) // DMA Control Register
> +#define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level
> +#define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level
> +#define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register
> +#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call
> Register
> +#define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status
> Register
> +#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter
> Register
> +#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
> +#define R_IC_COMP_TYPE ( 0xFC) // Component Type
> +
> +#define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD
> +#define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4
> +#define I2C_FS_SCL_HCNT_VALUE_100M 0x54
> +#define I2C_FS_SCL_LCNT_VALUE_100M 0x9a
> +#define I2C_HS_SCL_HCNT_VALUE_100M 0x7
> +#define I2C_HS_SCL_LCNT_VALUE_100M 0xE
> +
> +#define IC_TAR_10BITADDR_MASTER BIT12
> +#define FIFO_SIZE 32
> +#define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status
> +#define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask
> +#define I2C_INTR_GEN_CALL BIT11 // General call received
> +#define I2C_INTR_START_DET BIT10
> +#define I2C_INTR_STOP_DET BIT9
> +#define I2C_INTR_ACTIVITY BIT8
> +#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
> +#define I2C_INTR_TX_EMPTY BIT4
> +#define I2C_INTR_TX_OVER BIT3
> +#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over
> threshold
> +#define I2C_INTR_RX_OVER BIT1
> +#define I2C_INTR_RX_UNDER BIT0
> +
> +#define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset
> +#define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock
> Domain Reset
> +#define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain
> Reset
> +#define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock
> Parameters
> +
> +#endif
> \ No newline at end of file
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CAccess.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CAccess.h
> new file mode 100644
> index 0000000000..bf6ef4c747
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CAccess.h
> @@ -0,0 +1,44 @@
> +/** @file
> + Misc Registers Definition.
> +
> + Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +--*/
> +
> +#ifndef _I2C_ACCESS_H_
> +#define _I2C_ACCESS_H_
> +
> +#include "I2CIoLibPei.h"
> +
> +#define DEFAULT_PCI_BUS_NUMBER_PCH 0
> +
> +#define PCI_DEVICE_NUMBER_PCH_LPC 31
> +#define PCI_FUNCTION_NUMBER_PCH_LPC 0
> +
> +#define R_PCH_LPC_ACPI_BASE 0x40 // ABASE, 16bit
> +#define R_PCH_LPC_ACPI_BASEADR 0x400 // ABASE, 16bit
> +#define B_PCH_LPC_ACPI_BASE_EN BIT1 // Enable Bit
> +#define B_PCH_LPC_ACPI_BASE_BAR 0x0000FF80 // Base
> Address, 128 Bytes
> +#define V_PCH_ACPI_PM1_TMR_MAX_VAL 0x1000000 // The
> timer is 24 bit overflow
> +#define B_PCH_ACPI_PM1_TMR_VAL 0xFFFFFF // The timer
> value mask
> +
> +#define R_PCH_ACPI_PM1_TMR 0x08 // Power
> Management 1 Timer
> +#define V_PCH_ACPI_PM1_TMR_FREQUENCY 3579545 // Timer
> Frequency
> +
> +
> +#define PchLpcPciCfg8(Register) I2CLibPeiMmioRead8 (MmPciAddress (0,
> DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0,
> Register))
> +
> +#define PCIEX_BASE_ADDRESS 0xE0000000
> +#define PCI_EXPRESS_BASE_ADDRESS ((VOID *) (UINTN)
> PCIEX_BASE_ADDRESS)
> +
> +#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
> + ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
> + (UINTN)(Bus << 20) + \
> + (UINTN)(Device << 15) + \
> + (UINTN)(Function << 12) + \
> + (UINTN)(Register) \
> + )
> +#endif
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.c
> new file mode 100644
> index 0000000000..d5f8dfd012
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.c
> @@ -0,0 +1,46 @@
> +/** @file
> + MicroSecondDelay implementation of ACPI Timer.
> +
> + Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +--*/
> +
> +#include "PiPei.h"
> +#include "I2CAccess.h"
> +#include "I2CDelayPei.h"
> +#include <Library/DebugLib.h>
> +#include <Library/PeiServicesTablePointerLib.h>
> +#include <Ppi/Stall.h>
> +
> +/**
> + Stalls the CPU for at least the given number of microseconds.
> + Stalls the CPU for the number of microseconds specified by MicroSeconds.
> +
> + @param MicroSeconds The minimum number of microseconds to delay.
> +
> + @return EFI_STATUS
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +MicroSecondDelay (
> + IN UINTN MicroSeconds
> + )
> +{
> +
> + EFI_PEI_STALL_PPI *StallPpi;
> + EFI_STATUS Status;
> + CONST EFI_PEI_SERVICES **PeiServices;
> +
> + PeiServices = GetPeiServicesTablePointer();
> +
> +
> + Status = (**PeiServices).LocatePpi (PeiServices, &gEfiPeiStallPpiGuid, 0,
> NULL, &StallPpi);
> + ASSERT(!EFI_ERROR(Status));
> +
> + StallPpi->Stall (PeiServices, StallPpi, MicroSeconds);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.h
> new file mode 100644
> index 0000000000..604f1f67c5
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CDelayPei.h
> @@ -0,0 +1,30 @@
> +/** @file
> + MicroSecondDelay implementation of ACPI Timer.
> +
> + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __I2C_DELAY_PEI__
> +
> +#define __I2C_DELAY_PEI__
> +#include "PiPei.h"
> +
> +/**
> + Stalls the CPU for at least the given number of microseconds.
> +
> + Stalls the CPU for the number of microseconds specified by MicroSeconds.
> +
> + @param MicroSeconds The minimum number of microseconds to delay.
> +
> + @return MicroSeconds
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +MicroSecondDelay (
> + IN UINTN MicroSeconds
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.c
> new file mode 100644
> index 0000000000..6a37dbec1d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.c
> @@ -0,0 +1,178 @@
> +/** @file
> + Functions for access I2C MMIO register.
> +
> + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PeiServicesTablePointerLib.h>
> +
> +/**
> + Reads an 8-bit MMIO register.
> +
> + Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 8-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +I2CLibPeiMmioRead8 (
> + IN UINTN Address
> + )
> +{
> + UINT8 Value;
> +
> + Value = *(volatile UINT8*)Address;
> + return Value;
> +}
> +
> +/**
> + Reads a 16-bit MMIO register.
> +
> + Reads the 16-bit MMIO register specified by Address. The 16-bit read value
> is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 16-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +I2CLibPeiMmioRead16 (
> + IN UINTN Address
> + )
> +{
> + UINT16 Value;
> +
> + ASSERT ((Address & 1) == 0);
> + Value = *(volatile UINT16*)Address;
> + return Value;
> +}
> +
> +/**
> + Writes a 16-bit MMIO register.
> +
> + Writes the 16-bit MMIO register specified by Address with the value
> specified
> + by Value and returns Value. This function must guarantee that all MMIO
> read
> + and write operations are serialized.
> +
> + If 16-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +I2CLibPeiMmioWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + )
> +{
> + ASSERT ((Address & 1) == 0);
> + *(volatile UINT16*)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads a 32-bit MMIO register.
> +
> + Reads the 32-bit MMIO register specified by Address. The 32-bit read value
> is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +I2CLibPeiMmioRead32 (
> + IN UINTN Address
> + )
> +{
> + UINT32 Value;
> +
> + ASSERT ((Address & 3) == 0);
> + Value = *(volatile UINT32*)Address;
> +
> + return Value;
> +}
> +
> +/**
> + Writes a 32-bit MMIO register.
> +
> + Writes the 32-bit MMIO register specified by Address with the value
> specified
> + by Value and returns Value. This function must guarantee that all MMIO
> read
> + and write operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +I2CLibPeiMmioWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + ASSERT ((Address & 3) == 0);
> + *(volatile UINT32*)Address = Value;
> + return Value;
> +}
> +
> +/**
> + OR a 32-bit MMIO register.
> +
> + OR the 32-bit MMIO register specified by Address with the value specified
> + by Value and returns Value. This function must guarantee that all MMIO
> read
> + and write operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write OR.
> + @param Value The value to OR to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +I2CLibPeiMmioOr32 (
> + IN UINTN Address,
> + IN UINT32 OrData
> + )
> +{
> + return I2CLibPeiMmioWrite32 (Address, I2CLibPeiMmioRead32(Address) |
> OrData);
> +}
> +
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.h
> new file mode 100644
> index 0000000000..b68bc1ed09
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CIoLibPei.h
> @@ -0,0 +1,153 @@
> +/** @file
> + Functions for access I2C MMIO register.
> +
> + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __I2C_IOLIB_PEI__
> +
> +#define __I2C_IOLIB_PEI__
> +#include <PiPei.h>
> +
> +
> +/**
> + Reads an 8-bit MMIO register.
> +
> + Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 8-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +
> +UINT8
> +EFIAPI
> +I2CLibPeiMmioRead8 (
> + IN UINTN Address
> + );
> +
> +
> +/**
> + Reads a 16-bit MMIO register.
> +
> + Reads the 16-bit MMIO register specified by Address. The 16-bit read value
> is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 16-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +I2CLibPeiMmioRead16 (
> + IN UINTN Address
> + );
> +
> +
> +/**
> + Writes a 16-bit MMIO register.
> +
> + Writes the 16-bit MMIO register specified by Address with the value
> specified
> + by Value and returns Value. This function must guarantee that all MMIO
> read
> + and write operations are serialized.
> +
> + If 16-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +I2CLibPeiMmioWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + );
> +
> +
> +/**
> + Reads a 32-bit MMIO register.
> +
> + Reads the 32-bit MMIO register specified by Address. The 32-bit read value
> is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +I2CLibPeiMmioRead32 (
> + IN UINTN Address
> + );
> +
> +
> +/**
> + Writes a 32-bit MMIO register.
> +
> + Writes the 32-bit MMIO register specified by Address with the value
> specified
> + by Value and returns Value. This function must guarantee that all MMIO
> read
> + and write operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +I2CLibPeiMmioWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
> +
> +/**
> + OR a 32-bit MMIO register.
> +
> + OR the 32-bit MMIO register specified by Address with the value specified
> + by Value and returns Value. This function must guarantee that all MMIO
> read
> + and write operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The MMIO register to write OR.
> + @param Value The value to OR to the MMIO register.
> +
> + @return Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +I2CLibPeiMmioOr32 (
> + IN UINTN Address,
> + IN UINT32 OrData
> + );
> +
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.c
> new file mode 100644
> index 0000000000..dd5cceb70d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.c
> @@ -0,0 +1,638 @@
> +/** @file
> + I2C PEI Lib Instance.
> +
> + Copyright (c) 1999- 2015, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "I2CDelayPei.h"
> +#include "I2CIoLibPei.h"
> +#include "I2CAccess.h"
> +#include "I2CLibPei.h"
> +#include <PlatformBaseAddresses.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/PeiServicesTablePointerLib.h>
> +#include <Library/HobLib.h>
> +#include <PchRegs/PchRegsPcu.h>
> +#include <PchRegs/PchRegsLpss.h>
> +
> +#define LPSS_PCI_DEVICE_NUMBER 8
> +
> +#define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset
> +#define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock
> Domain Reset
> +#define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain
> Reset
> +#define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock
> Parameters
> +
> +#define PEI_TEPM_LPSS_DMA_BAR 0xFE900000
> +#define PEI_TEPM_LPSS_I2C0_BAR 0xFE910000
> +#define PCI_CONFIG_SPACE_SIZE 0x10000
> +
> +EFI_GUID mI2CPeiInitGuid = {
> + 0x96DED71A, 0xB9E7, 0x4EAD, 0x96, 0x2C, 0x01, 0x69, 0x3C, 0xED, 0x2A,
> 0x64
> +};
> +
> +
> +UINT16 I2CGPIO[]= {
> + //
> + // 19.1.6 I2C0
> + // I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210
> + // I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200
> + //
> + 0x0210,
> + 0x0200,
> +
> + //
> + // 19.1.7 I2C1
> + // I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0
> + // I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0
> + //
> + 0x01F0,
> + 0x01E0,
> +
> + //
> + // 19.1.8 I2C2
> + // I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0
> + // I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0
> + //
> + 0x01D0,
> + 0x01B0,
> +
> + //
> + // 19.1.9 I2C3
> + // I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190
> + // I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0
> + //
> + 0x0190,
> + 0x01C0,
> +
> + //
> + // 19.1.10 I2C4
> + // I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0
> + // I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170
> + //
> + 0x01A0,
> + 0x0170,
> +
> + //
> + // 19.1.11 I2C5
> + // I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150
> + // I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140
> + //
> + 0x0150,
> + 0x0140,
> +
> + //
> + // 19.1.12 I2C6
> + // I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180
> + // I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160
> + //
> + 0x0180,
> + 0x0160
> +};
> +
> +/**
> + Constructor of this library.
> +
> + @param VOID
> +
> + @return EFI_SUCCESS
> +**/
> +EFI_STATUS
> +EFIAPI
> +IntelI2CPeiLibConstructor (
> + IN EFI_PEI_FILE_HANDLE FileHandle,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + UINTN Index;
> +
> + for (Index = 0; Index < sizeof(I2CGPIO)/sizeof(UINT16); Index ++) {
> + I2CLibPeiMmioWrite32(IO_BASE_ADDRESS+I2CGPIO[Index], 0x2003CC81);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Programe all I2C controllers on LPSS.
> +
> + I2C0 is function 1 of LPSS. I2C1 is function 2 of LPSS, etc..
> +
> + @param VOID
> +
> + @return EFI_SUCCESS
> +**/
> +EFI_STATUS
> +ProgramPciLpssI2C (
> + VOID
> + )
> +{
> + UINT32 PmcBase;
> + UINT32 DevID;
> + UINTN PciMmBase=0;
> + UINTN Index;
> + UINTN Bar0;
> + UINTN Bar1;
> + DEBUG ((EFI_D_INFO, "Pei ProgramPciLpssI2C() Start\n"));
> +
> + //
> + // Set the VLV Function Disable Register to ZERO
> + //
> + PmcBase = I2CLibPeiMmioRead32(PciD31F0RegBase +
> R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR;
> +
> + if(I2CLibPeiMmioRead32(PmcBase + R_PCH_PMC_FUNC_DIS)&
> + (B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1 |
> B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2
> + | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3 |
> B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4 |
> B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5
> + | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6 |
> B_PCH_PMC_FUNC_DIS_LPSS2_FUNC7)) {
> + I2CLibPeiMmioWrite32(
> + PmcBase+R_PCH_PMC_FUNC_DIS,
> + I2CLibPeiMmioRead32(PmcBase + R_PCH_PMC_FUNC_DIS)& \
> + ~(B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1 |
> B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2 \
> + | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3 |
> B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4 \
> + | B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5 |
> B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6|B_PCH_PMC_FUNC_DIS_LPSS2_FU
> NC7)
> + );
> + DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() enable all I2C controllers\n"));
> + }
> +
> + for(Index = 0; Index < LPSS_PCI_DEVICE_NUMBER; Index ++) {
> +
> + PciMmBase = MmPciAddress (
> + 0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
> + Index,
> + 0
> + );
> + DevID = I2CLibPeiMmioRead32(PciMmBase);
> +
> + Bar0 = PEI_TEPM_LPSS_DMA_BAR + (Index * PCI_CONFIG_SPACE_SIZE);
> + Bar1 = Bar0 + 0x8000;
> +
> + DEBUG((EFI_D_ERROR, "Program Pci Lpss I2C Device Function=%x
> DevID=%08x\n", Index, DevID));
> +
> + //
> + // Check if device present
> + //
> + if (DevID != 0xFFFFFFFF) {
> + if(!(I2CLibPeiMmioRead32 (PciMmBase + R_PCH_LPSS_I2C_STSCMD) &
> B_PCH_LPSS_I2C_STSCMD_MSE)) {
> + //
> + // Program BAR 0
> + //
> + I2CLibPeiMmioWrite32((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR),
> (UINT32)(Bar0 & B_PCH_LPSS_I2C_BAR_BA));
> +
> + DEBUG ((EFI_D_ERROR, "I2CBaseAddress1 = 0x%x
> \n",I2CLibPeiMmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR)));
> +
> + //
> + // Program BAR 1
> + //
> + I2CLibPeiMmioWrite32 ((UINTN)(PciMmBase + R_PCH_LPSS_I2C_BAR1),
> (UINT32)(Bar1 & B_PCH_LPSS_I2C_BAR1_BA));
> + DEBUG ((EFI_D_ERROR, "I2CBaseAddress1 = 0x%x
> \n",I2CLibPeiMmioRead32(PciMmBase+R_PCH_LPSS_I2C_BAR1)));
> +
> + //
> + // Bus Master Enable & Memory Space Enable
> + //
> + I2CLibPeiMmioWrite32((UINTN) (PciMmBase +
> R_PCH_LPSS_I2C_STSCMD), (UINT32)(B_PCH_LPSS_I2C_STSCMD_BME |
> B_PCH_LPSS_I2C_STSCMD_MSE));
> + }
> +
> + //
> + // Release Resets
> + //
> + I2CLibPeiMmioWrite32 (Bar0 + R_PCH_LPIO_I2C_MEM_RESETS,
> (B_PCH_LPIO_I2C_MEM_RESETS_FUNC |
> B_PCH_LPIO_I2C_MEM_RESETS_APB));
> +
> + //
> + // Activate Clocks
> + //
> + I2CLibPeiMmioWrite32 (Bar0 + R_PCH_LPSS_I2C_MEM_PCP,
> 0x80020003);//No use for A0
> +
> + DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() Programmed()\n"));
> + }
> +
> + }
> +
> + DEBUG ((EFI_D_INFO, "Pei ProgramPciLpssI2C() End\n"));
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Disable I2C Bus.
> +
> + @param I2cControllerIndex Index of I2C controller.
> +
> + @return EFI_SUCCESS
> +**/
> +EFI_STATUS
> +I2cDisable (
> + IN UINT8 I2cControllerIndex
> + )
> +{
> + UINTN I2CBaseAddress;
> + UINT32 NumTries = 10000; // 0.1 seconds
> +
> + I2CBaseAddress = (UINT32) PEI_TEPM_LPSS_I2C0_BAR +
> I2cControllerIndex * PCI_CONFIG_SPACE_SIZE;
> +
> + I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_ENABLE, 0);
> + while (0 != ( I2CLibPeiMmioRead16 (I2CBaseAddress +
> R_IC_ENABLE_STATUS ) & 1)) {
> + MicroSecondDelay (10);
> + NumTries --;
> + if(0 == NumTries) return EFI_NOT_READY;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Enable I2C Bus.
> +
> + @param I2cControllerIndex Index of I2C controller.
> +
> + @return EFI_SUCCESS
> +**/
> +EFI_STATUS
> +I2cEnable (
> + IN UINT8 I2cControllerIndex
> + )
> +{
> + UINTN I2CBaseAddress;
> + UINT32 NumTries = 10000; // 0.1 seconds
> +
> + I2CBaseAddress = (UINT32) PEI_TEPM_LPSS_I2C0_BAR+
> I2cControllerIndex * PCI_CONFIG_SPACE_SIZE;
> + I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_ENABLE, 1);
> + while (0 == ( I2CLibPeiMmioRead16 ( I2CBaseAddress +
> R_IC_ENABLE_STATUS ) & 1)) {
> + MicroSecondDelay (10);
> + NumTries --;
> + if(0 == NumTries) return EFI_NOT_READY;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Set the I2C controller bus clock frequency.
> +
> + @param[in] This Address of the library's I2C context structure
> + @param[in] PlatformData Address of the platform configuration data
> + @param[in] BusClockHertz New I2C bus clock frequency in Hertz
> +
> + @retval RETURN_SUCCESS The bus frequency was set successfully.
> + @retval RETURN_UNSUPPORTED The controller does not support this
> frequency.
> +
> +**/
> +EFI_STATUS
> +I2cBusFrequencySet (
> + IN UINTN I2CBaseAddress,
> + IN UINTN BusClockHertz,
> + IN UINT16 *I2cMode
> + )
> +{
> + DEBUG((EFI_D_INFO,"InputFreq BusClockHertz: %d\r\n",BusClockHertz));
> +
> + *I2cMode = B_IC_RESTART_EN | B_IC_SLAVE_DISABLE |
> B_MASTER_MODE;
> +
> + //
> + // Set the 100 KHz clock divider
> + //
> + // From Table 10 of the I2C specification
> + //
> + // High: 4.00 uS
> + // Low: 4.70 uS
> + //
> + I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_SS_SCL_HCNT,
> (UINT16)0x214 );
> + I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_SS_SCL_LCNT,
> (UINT16)0x272 );
> +
> + //
> + // Set the 400 KHz clock divider
> + //
> + // From Table 10 of the I2C specification
> + //
> + // High: 0.60 uS
> + // Low: 1.30 uS
> + //
> + I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_FS_SCL_HCNT,
> (UINT16)0x50 );
> + I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_FS_SCL_LCNT,
> (UINT16)0xAD );
> +
> + switch ( BusClockHertz ) {
> + case 100 * 1000:
> + I2CLibPeiMmioWrite32 ( I2CBaseAddress + R_IC_SDA_HOLD,
> (UINT16)0x40);//100K
> + *I2cMode |= V_SPEED_STANDARD;
> + break;
> + case 400 * 1000:
> + I2CLibPeiMmioWrite32 ( I2CBaseAddress + R_IC_SDA_HOLD,
> (UINT16)0x32);//400K
> + *I2cMode |= V_SPEED_FAST;
> + break;
> + default:
> + I2CLibPeiMmioWrite32 ( I2CBaseAddress + R_IC_SDA_HOLD,
> (UINT16)0x09);//3.4M
> + *I2cMode |= V_SPEED_HIGH;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Initializes the host controller to execute I2C commands.
> +
> + @param I2cControllerIndex Index of I2C controller in LPSS device. 0
> represents I2C0, which is PCI function 1 of LPSS device.
> +
> + @return EFI_SUCCESS Opcode initialization on the I2C host controller
> completed.
> + @return EFI_DEVICE_ERROR Device error, operation failed.
> +**/
> +EFI_STATUS
> +I2CInit (
> + UINT8 I2cControllerIndex,
> + UINT16 SlaveAddress
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 NumTries = 0;
> + UINTN I2CBaseAddress;
> + UINT16 I2cMode;
> + UINTN PciMmBase=0;
> +
> +
> + PciMmBase = MmPciAddress (
> + 0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
> + (I2cControllerIndex + 1),
> + 0
> + );
> +
> + I2CBaseAddress = I2CLibPeiMmioRead32
> (PciMmBase+R_PCH_LPSS_I2C_BAR);
> +
> + //
> + // Verify the parameters
> + //
> + if (1023 < SlaveAddress ) {
> + Status = EFI_INVALID_PARAMETER;
> + DEBUG((EFI_D_INFO,"I2cStartRequest Exit with Status %r\r\n", Status));
> + return Status;
> + }
> +
> + if(I2CBaseAddress == (PEI_TEPM_LPSS_I2C0_BAR + I2cControllerIndex *
> PCI_CONFIG_SPACE_SIZE)) {
> + return EFI_SUCCESS;
> + }
> + ProgramPciLpssI2C();
> +
> + I2CBaseAddress = (UINT32) (PEI_TEPM_LPSS_I2C0_BAR +
> I2cControllerIndex * PCI_CONFIG_SPACE_SIZE);
> + DEBUG ((EFI_D_ERROR, "I2CBaseAddress = 0x%x \n",I2CBaseAddress));
> + NumTries = 10000; // 1 seconds
> + while ((1 == ( I2CLibPeiMmioRead32 ( I2CBaseAddress + R_IC_STATUS) &
> STAT_MST_ACTIVITY ))) {
> + MicroSecondDelay(10);
> + NumTries --;
> + if(0 == NumTries)
> + return EFI_DEVICE_ERROR;
> + }
> +
> + Status = I2cDisable (I2cControllerIndex);
> + DEBUG((EFI_D_INFO, "I2cDisable Status = %r\r\n", Status));
> +
> + I2cBusFrequencySet(I2CBaseAddress, 400 * 1000, &I2cMode);//Set
> I2cMode
> +
> + I2CLibPeiMmioWrite16(I2CBaseAddress + R_IC_INTR_MASK, 0x0);
> + if (0x7F < SlaveAddress) {
> + SlaveAddress = (SlaveAddress & 0x3ff ) | IC_TAR_10BITADDR_MASTER;
> + }
> + I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_TAR, (UINT16)
> SlaveAddress );
> + I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_RX_TL, 0);
> + I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_TX_TL, 0 );
> + I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_CON, I2cMode);
> +
> + Status = I2cEnable(I2cControllerIndex);
> + DEBUG((EFI_D_INFO, "I2cEnable Status = %r\r\n", Status));
> + I2CLibPeiMmioRead16 ( I2CBaseAddress + R_IC_CLR_TX_ABRT );
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Reads a Byte from I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be read
> + @param Offset Offset from which the data has to be read
> + @param *Byte Address to which the value read has to be stored
> +
> + @return EFI_SUCCESS If the byte value has been successfully read
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS ByteReadI2CBasic(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINTN ReadBytes,
> + OUT UINT8 *ReadBuffer,
> + IN UINT8 Start,
> + IN UINT8 End
> + )
> +{
> +
> + EFI_STATUS Status;
> + UINT32 I2cStatus;
> + UINT16 ReceiveData;
> + UINT8 *ReceiveDataEnd;
> + UINT8 *ReceiveRequest;
> + UINT16 RawIntrStat;
> + UINTN I2CBaseAddress;
> +
> + I2CBaseAddress = (UINT32)(PEI_TEPM_LPSS_I2C0_BAR +
> I2cControllerIndex * PCI_CONFIG_SPACE_SIZE);
> +
> + Status = EFI_SUCCESS;
> +
> + I2CInit(I2cControllerIndex, SlaveAddress);
> +
> + ReceiveDataEnd = &ReadBuffer [ReadBytes];
> + if(ReadBytes) {
> + ReceiveRequest = ReadBuffer;
> + DEBUG((EFI_D_INFO,"Read: ---------------%d bytes to
> RX\r\n",ReceiveDataEnd - ReceiveRequest));
> +
> + while ((ReceiveDataEnd > ReceiveRequest) || (ReceiveDataEnd >
> ReadBuffer)) {
> + //
> + // Check for NACK
> + //
> + RawIntrStat = I2CLibPeiMmioRead16 (I2CBaseAddress +
> R_IC_RawIntrStat );
> + if ( 0 != (RawIntrStat & I2C_INTR_TX_ABRT )) {
> + I2CLibPeiMmioRead16 ( I2CBaseAddress + R_IC_CLR_TX_ABRT );
> + Status = RETURN_DEVICE_ERROR;
> + DEBUG((EFI_D_INFO,"TX ABRT ,%d bytes hasn't been
> transferred\r\n",ReceiveDataEnd - ReceiveRequest));
> + break;
> + }
> +
> + //
> + // Determine if another byte was received
> + //
> + I2cStatus = I2CLibPeiMmioRead16 ( I2CBaseAddress + R_IC_STATUS );
> + if ( 0 != ( I2cStatus & STAT_RFNE )) {
> + ReceiveData = I2CLibPeiMmioRead16 ( I2CBaseAddress +
> R_IC_DATA_CMD );
> + *ReadBuffer++ = (UINT8)ReceiveData;
> + DEBUG((EFI_D_INFO,"MmioRead32 ,1 byte 0x:%x is
> received\r\n",ReceiveData));
> + }
> +
> + if(ReceiveDataEnd==ReceiveRequest) {
> + //
> + // Waiting the last request to get data and make (ReceiveDataEnd >
> ReadBuffer) =TRUE.
> + //
> + continue;
> + }
> +
> + //
> + // Wait until a read request will fit
> + //
> + if ( 0 == ( I2cStatus & STAT_TFNF )) {
> + MicroSecondDelay ( 10 );
> + continue;
> + }
> +
> + //
> + // Issue the next read request
> + //
> + if(End && Start ) {
> + I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_DATA_CMD,
> B_READ_CMD|B_CMD_RESTART|B_CMD_STOP);
> + } else if (!End && Start ) {
> + I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_DATA_CMD,
> B_READ_CMD|B_CMD_RESTART);
> + } else if (End && !Start ) {
> + I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_DATA_CMD,
> B_READ_CMD|B_CMD_STOP);
> + } else if (!End && !Start ) {
> + I2CLibPeiMmioWrite16 ( I2CBaseAddress + R_IC_DATA_CMD,
> B_READ_CMD);
> + }
> + ReceiveRequest += 1;
> + }
> +
> + }
> + return Status;
> +
> +}
> +
> +/**
> + Writes a Byte to I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be written
> + @param Offset Offset from which the data has to be read
> + @param *Byte Address to which the value written is stored
> +
> + @return EFI_SUCCESS IF the byte value has been successfully written
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS
> +ByteWriteI2CBasic(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINTN WriteBytes,
> + IN UINT8 *WriteBuffer,
> + IN UINT8 Start,
> + IN UINT8 End
> + )
> +{
> +
> + EFI_STATUS Status;
> + UINT32 I2cStatus;
> + UINT8 *TransmitEnd;
> + UINT16 RawIntrStat;
> + UINTN I2CBaseAddress;
> +
> + I2CBaseAddress = (UINT32)PEI_TEPM_LPSS_I2C0_BAR+ I2cControllerIndex
> * PCI_CONFIG_SPACE_SIZE;
> +
> + Status = EFI_SUCCESS;
> +
> + I2CInit(I2cControllerIndex, SlaveAddress);
> +
> + TransmitEnd = &WriteBuffer [WriteBytes];
> + if( WriteBytes ) {
> +
> + DEBUG((EFI_D_INFO,"Write: --------------%d bytes to TX\r\n",
> TransmitEnd - WriteBuffer));
> +
> + while ( TransmitEnd > WriteBuffer) {
> + I2cStatus = I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_STATUS);
> + RawIntrStat = I2CLibPeiMmioRead16 (I2CBaseAddress +
> R_IC_RawIntrStat);
> + if ( 0 != (RawIntrStat & I2C_INTR_TX_ABRT)) {
> + I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_CLR_TX_ABRT);
> + Status = RETURN_DEVICE_ERROR;
> + DEBUG((EFI_D_ERROR,"TX ABRT TransmitEnd:0x%x
> WriteBuffer:0x%x\r\n", TransmitEnd, WriteBuffer));
> + break;
> + }
> + if (0 == ( I2cStatus & STAT_TFNF)) {
> + continue;
> + }
> + if(End && Start) {
> + I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD,
> (*WriteBuffer++) | B_CMD_RESTART | B_CMD_STOP);
> + } else if (!End && Start ) {
> + I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD,
> (*WriteBuffer++) | B_CMD_RESTART);
> + } else if (End && !Start ) {
> + I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD,
> (*WriteBuffer++) | B_CMD_STOP);
> + } else if (!End && !Start ) {
> + I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD,
> (*WriteBuffer++));
> + }
> +
> + // Add a small delay to work around some odd behavior being seen.
> Without this delay bytes get dropped.
> + MicroSecondDelay ( FIFO_WRITE_DELAY );
> + }
> +
> + }
> +
> + if(EFI_ERROR(Status)) {
> + DEBUG((EFI_D_INFO,"I2cStartRequest Exit with Status %r\r\n",Status));
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Reads a Byte from I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be read
> + @param Offset Offset from which the data has to be read
> + @param ReadBytes Number of bytes to be read
> + @param *ReadBuffer Address to which the value read has to be
> stored
> +
> + @return EFI_SUCCESS IF the byte value has been successfully read
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS
> +ByteReadI2C(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINT8 Offset,
> + IN UINTN ReadBytes,
> + OUT UINT8 *ReadBuffer
> + )
> +{
> + EFI_STATUS Status;
> +
> + DEBUG ((EFI_D_ERROR, "ByteReadI2C:---offset:0x%x\n",Offset));
> + Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress, 1,
> &Offset,TRUE,FALSE);
> + Status = ByteReadI2CBasic(I2cControllerIndex, SlaveAddress, ReadBytes,
> ReadBuffer, TRUE, TRUE);
> +
> + return Status;
> +}
> +
> +/**
> + Writes a Byte to I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be written
> + @param Offset Offset from which the data has to be written
> + @param WriteBytes Number of bytes to be written
> + @param *Byte Address to which the value written is stored
> +
> + @return EFI_SUCCESS IF the byte value has been successfully read
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS ByteWriteI2C(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINT8 Offset,
> + IN UINTN WriteBytes,
> + IN UINT8 *WriteBuffer
> + )
> +{
> + EFI_STATUS Status;
> +
> + DEBUG ((EFI_D_ERROR, "ByteWriteI2C:---
> offset/bytes/buf:0x%x,0x%x,0x%x,0x%x\n",Offset,WriteBytes,WriteBuffer,
> *WriteBuffer));
> + Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress, 1, &Offset,
> TRUE, FALSE);
> + Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress, WriteBytes,
> WriteBuffer, FALSE, TRUE);
> +
> + return Status;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.h
> new file mode 100644
> index 0000000000..47536aebf7
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.h
> @@ -0,0 +1,280 @@
> +/** @file
> + I2C PEI Lib Instance.
> +
> + Copyright (c) 1999- 2015, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef I2C_PEI_REGS_H
> +#define I2C_PEI_REGS_H
> +
> +#include "PiPei.h"
> +
> +#define R_PCH_LPC_PMC_BASE 0x44
> +#define B_PCH_LPC_PMC_BASE_BAR 0xFFFFFE00
> +#define R_PCH_PMC_FUNC_DIS 0x34 // Function Disable
> Register
> +#define PCIEX_BASE_ADDRESS 0xE0000000
> +#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32)
> (31 << 15)
> +#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC7 BIT7 // LPSS SPI
> Disable
> +#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC6 BIT6 // LPSS HSUART
> #2 Disable
> +#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC5 BIT5 // LPSS HSUART
> #1 Disable
> +#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC4 BIT4 // LPSS I2S
> Disable
> +#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC3 BIT3 // LPSS PCM
> Disable
> +#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC2 BIT2 // LPSS I2C #2
> Disable
> +#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC1 BIT1 // LPSS I2C #1
> Disable
> +#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC0 BIT0 // LPSS DMA
> Disable
> +
> +
> +#define DEFAULT_PCI_BUS_NUMBER_PCH 0
> +
> +#define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command
> +#define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA
> +#define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA
> +#define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List
> +#define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
> +#define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt
> Disable
> +#define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable
> +#define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable
> +#define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space
> Enable
> +
> +#define R_PCH_LPSS_I2C_BAR 0x10 // BAR
> +#define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address
> +#define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator
> +#define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable
> +#define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
> +#define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space
> +
> +#define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1
> +#define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address
> +#define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator
> +#define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable
> +#define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
> +#define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space
> +
> +#define NUM_RETRIES 0xFFFF
> +
> +//
> +// LPIO I2C Module Memory Space Registers
> +//
> +#define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset
> +#define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock
> Domain Reset
> +#define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain
> Reset
> +
> +#define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock
> Parameters
> +
> +#define bit(a) 1 << (a)
> +
> +//
> +// MMIO Register Definitions
> +//
> +
> +#define I2C0_REG_SPACE_ADDR_BASE 0xFF138000 //01K
> +
> +#define R_IC_CON ( 0x00) // I2C Control
> +#define B_IC_RESTART_EN BIT5
> +#define B_IC_SLAVE_DISABLE BIT6
> +#define V_SPEED_STANDARD 0x02
> +#define V_SPEED_FAST 0x04
> +#define V_SPEED_HIGH 0x06
> +#define B_MASTER_MODE BIT0
> +
> +#define R_IC_TAR ( 0x04) // I2C Target Address
> +#define IC_TAR_10BITADDR_MASTER BIT12
> +
> +#define R_IC_SAR ( 0x08) // I2C Slave Address
> +#define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code
> Address
> +#define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and
> Command
> +
> +#define B_READ_CMD BIT8 // 1 = read, 0 = write
> +#define B_CMD_STOP BIT9 // 1 = STOP
> +#define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
> +
> +#define V_WRITE_CMD_MASK ( 0xFF)
> +
> +#define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock
> SCL High Count
> +#define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock
> SCL Low Count
> +#define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL
> High Count
> +#define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL
> Low Count
> +#define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL
> High Count
> +#define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL
> Low Count
> +#define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status
> +#define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask
> +#define I2C_INTR_GEN_CALL BIT11 // General call received
> +#define I2C_INTR_START_DET BIT10
> +#define I2C_INTR_STOP_DET BIT9
> +#define I2C_INTR_ACTIVITY BIT8
> +#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
> +#define I2C_INTR_TX_EMPTY BIT4
> +#define I2C_INTR_TX_OVER BIT3
> +#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over
> threshold
> +#define I2C_INTR_RX_OVER BIT1
> +#define I2C_INTR_RX_UNDER BIT0
> +#define R_IC_RawIntrStat ( 0x34) // I2C Raw Interrupt Status
> +#define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold
> +#define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold
> +#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual
> Interrupts
> +#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER
> Interrupt
> +#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt
> +#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt
> +#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
> +#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
> +#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt
> +#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
> +#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt
> +#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET
> interrupt
> +#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt
> +#define R_IC_ENABLE ( 0x6C) // I2C Enable
> +#define R_IC_STATUS ( 0x70) // I2C Status
> +
> +#define R_IC_SDA_HOLD ( 0x7C) // I2C
> IC_DEFAULT_SDA_HOLD//16bits
> +
> +#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.
> +#define STAT_RFF BIT4 // RX FIFO is completely full
> +#define STAT_RFNE BIT3 // RX FIFO is not empty
> +#define STAT_TFE BIT2 // TX FIFO is completely empty
> +#define STAT_TFNF BIT1 // TX FIFO is not full
> +
> +#define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register
> +#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
> +#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort
> Status Register
> +#define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate
> SLV_DATA_NACK Register
> +#define R_IC_DMA_CR ( 0x88) // DMA Control Register
> +#define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level
> +#define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level
> +#define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register
> +#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call
> Register
> +#define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status
> Register
> +#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter
> Register
> +#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
> +#define R_IC_COMP_TYPE ( 0xFC) // Component Type
> +
> +#define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD
> +#define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4
> +#define I2C_FS_SCL_HCNT_VALUE_100M 0x54
> +#define I2C_FS_SCL_LCNT_VALUE_100M 0x9a
> +#define I2C_HS_SCL_HCNT_VALUE_100M 0x7
> +#define I2C_HS_SCL_LCNT_VALUE_100M 0xE
> +
> +//
> +// FIFO write workaround value.
> +//
> +#define FIFO_WRITE_DELAY 2
> +#define IC_TAR_10BITADDR_MASTER BIT12
> +#define FIFO_SIZE 32
> +#define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status
> +#define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask
> +#define I2C_INTR_GEN_CALL BIT11 // General call received
> +#define I2C_INTR_START_DET BIT10
> +#define I2C_INTR_STOP_DET BIT9
> +#define I2C_INTR_ACTIVITY BIT8
> +#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
> +#define I2C_INTR_TX_EMPTY BIT4
> +#define I2C_INTR_TX_OVER BIT3
> +#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over
> threshold
> +#define I2C_INTR_RX_OVER BIT1
> +#define I2C_INTR_RX_UNDER BIT0
> +
> +/**
> + Programe all I2C controllers on LPSS.
> +
> + I2C0 is function 1 of LPSS. I2C1 is function 2 of LPSS, etc..
> +
> + @param VOID
> +
> + @return EFI_SUCCESS
> +**/
> +EFI_STATUS
> +ProgramPciLpssI2C (
> + VOID
> + );
> +
> +/**
> + Reads a Byte from I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be read
> + @param Offset Offset from which the data has to be read
> + @param *Byte Address to which the value read has to be stored
> + @param Start Whether a RESTART is issued before the byte is sent
> or received
> + @param End Whether STOP is generated after a data byte is sent
> or received
> +
> + @return EFI_SUCCESS If the byte value has been successfully read
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS
> +ByteReadI2CBasic(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINTN ReadBytes,
> + OUT UINT8 *ReadBuffer,
> + IN UINT8 Start,
> + IN UINT8 End
> + );
> +
> +/**
> + Writes a Byte to I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be written
> + @param Offset Offset from which the data has to be read
> + @param *Byte Address to which the value written is stored
> + @param Start Whether a RESTART is issued before the byte is sent
> or received
> + @param End Whether STOP is generated after a data byte is sent
> or received
> +
> + @return EFI_SUCCESS IF the byte value has been successfully written
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS
> +ByteWriteI2CBasic(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINTN WriteBytes,
> + IN UINT8 *WriteBuffer,
> + IN UINT8 Start,
> + IN UINT8 End
> + );
> +
> +/**
> + Reads a Byte from I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be read
> + @param Offset Offset from which the data has to be read
> + @param ReadBytes Number of bytes to be read
> + @param *ReadBuffer Address to which the value read has to be
> stored
> +
> + @return EFI_SUCCESS IF the byte value has been successfully read
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS
> +ByteReadI2C(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINT8 Offset,
> + IN UINTN ReadBytes,
> + OUT UINT8 *ReadBuffer
> + );
> +
> +/**
> + Writes a Byte to I2C Device.
> +
> + @param I2cControllerIndex I2C Bus no to which the I2C device has been
> connected
> + @param SlaveAddress Device Address from which the byte value has
> to be written
> + @param Offset Offset from which the data has to be written
> + @param WriteBytes Number of bytes to be written
> + @param *Byte Address to which the value written is stored
> +
> + @return EFI_SUCCESS IF the byte value has been successfully read
> + @return EFI_DEVICE_ERROR Operation Failed, Device Error
> +**/
> +EFI_STATUS
> +ByteWriteI2C(
> + IN UINT8 I2cControllerIndex,
> + IN UINT8 SlaveAddress,
> + IN UINT8 Offset,
> + IN UINTN WriteBytes,
> + IN UINT8 *WriteBuffer
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.inf
> new file mode 100644
> index 0000000000..a78212a0e7
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/I2CLibPei/I2CLibPei.inf
> @@ -0,0 +1,40 @@
> +## @file
> +# Instance of I2C Library.
> +#
> +# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = I2CLibPei
> + FILE_GUID = 8EF61509-890B-4FF2-B352-1C0E9CDDEC8B
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = LockBoxLib|PEIM
> + CONSTRUCTOR = IntelI2CPeiLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources.common]
> + I2CLibPei.c
> + I2CIoLibPei.c
> +
> +[LibraryClasses]
> + TimerLib
> +
> +[PPIs]
> + gEfiPeiStallPpiGuid
> +
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/CommonH
> eader.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/Common
> Header.h
> new file mode 100644
> index 0000000000..794c9178f1
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/Common
> Header.h
> @@ -0,0 +1,27 @@
> +/**@file
> + Common header file shared by all source files.
> +
> + This file includes package header files, library classes and protocol, PPI &
> GUID definitions.
> +
> + Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef __COMMON_HEADER_H_
> +#define __COMMON_HEADER_H_
> +
> +
> +#include <Base.h>
> +#include <PchAccess.h>
> +
> +#include <Library/TimerLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PciLib.h>
> +#include <Library/PcdLib.h>
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchA
> cpiTimerLib.c
> new file mode 100644
> index 0000000000..af44c6bd27
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchA
> cpiTimerLib.c
> @@ -0,0 +1,255 @@
> +/** @file
> + ICH9 ACPI Timer implements one instance of Timer Library.
> +
> +Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include "CommonHeader.h"
> +
> +/**
> + The constructor function enables ACPI IO space.
> +
> + If ACPI I/O space not enabled, this function will enable it.
> + It will always return RETURN_SUCCESS.
> +
> + @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +IntelPchAcpiTimerLibConstructor (
> + VOID
> + )
> +{
> + if ((PchLpcPciCfg8(R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_EN)
> == 0) {
> + //
> + // If ACPI I/O space is not enabled, program ACPI I/O base address and
> enable it.
> + //
> + MmioWrite16 (
> + MmPciAddress (
> + 0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_ACPI_BASE
> + ),
> + ((PcdGet16 (PcdPchAcpiIoPortBaseAddress) &
> B_PCH_LPC_ACPI_BASE_BAR) | B_PCH_LPC_ACPI_BASE_EN)
> + );
> + }
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Internal function to read the current tick counter of ACPI.
> +
> + Internal function to read the current tick counter of ACPI.
> +
> + @return The tick counter read.
> +
> +**/
> +STATIC
> +UINT32
> +InternalAcpiGetTimerTick (
> + VOID
> + )
> +{
> + return IoRead32 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) +
> R_PCH_ACPI_PM1_TMR);
> +}
> +
> +/**
> + Stalls the CPU for at least the given number of ticks.
> +
> + Stalls the CPU for at least the given number of ticks. It's invoked by
> + MicroSecondDelay() and NanoSecondDelay().
> +
> + @param Delay A period of time to delay in ticks.
> +
> +**/
> +STATIC
> +VOID
> +InternalAcpiDelay (
> + IN UINT32 Delay
> + )
> +{
> + UINT32 Ticks;
> + UINT32 Times;
> +
> + Times = Delay >> 22;
> + Delay &= BIT22 - 1;
> + do {
> + //
> + // The target timer count is calculated here
> + //
> + Ticks = InternalAcpiGetTimerTick () + Delay;
> + Delay = BIT22;
> + //
> + // Wait until time out
> + // Delay >= 2^23 could not be handled by this function
> + // Timer wrap-arounds are handled correctly by this function
> + //
> + while (((Ticks - InternalAcpiGetTimerTick ()) & BIT23) == 0) {
> + CpuPause ();
> + }
> + } while (Times-- > 0);
> +}
> +
> +/**
> + Stalls the CPU for at least the given number of microseconds.
> +
> + Stalls the CPU for the number of microseconds specified by MicroSeconds.
> +
> + @param MicroSeconds The minimum number of microseconds to delay.
> +
> + @return MicroSeconds
> +
> +**/
> +UINTN
> +EFIAPI
> +MicroSecondDelay (
> + IN UINTN MicroSeconds
> + )
> +{
> + InternalAcpiDelay (
> + (UINT32)DivU64x32 (
> + MultU64x32 (
> + MicroSeconds,
> + V_PCH_ACPI_PM1_TMR_FREQUENCY
> + ),
> + 1000000u
> + )
> + );
> + return MicroSeconds;
> +}
> +
> +/**
> + Stalls the CPU for at least the given number of nanoseconds.
> +
> + Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
> +
> + @param NanoSeconds The minimum number of nanoseconds to delay.
> +
> + @return NanoSeconds
> +
> +**/
> +UINTN
> +EFIAPI
> +NanoSecondDelay (
> + IN UINTN NanoSeconds
> + )
> +{
> + InternalAcpiDelay (
> + (UINT32)DivU64x32 (
> + MultU64x32 (
> + NanoSeconds,
> + V_PCH_ACPI_PM1_TMR_FREQUENCY
> + ),
> + 1000000000u
> + )
> + );
> + return NanoSeconds;
> +}
> +
> +/**
> + Retrieves the current value of a 64-bit free running performance counter.
> +
> + Retrieves the current value of a 64-bit free running performance counter.
> The
> + counter can either count up by 1 or count down by 1. If the physical
> + performance counter counts by a larger increment, then the counter
> values
> + must be translated. The properties of the counter can be retrieved from
> + GetPerformanceCounterProperties().
> +
> + @return The current value of the free running performance counter.
> +
> +**/
> +UINT64
> +EFIAPI
> +GetPerformanceCounter (
> + VOID
> + )
> +{
> + return (UINT64)InternalAcpiGetTimerTick ();
> +}
> +
> +/**
> + Retrieves the 64-bit frequency in Hz and the range of performance counter
> + values.
> +
> + If StartValue is not NULL, then the value that the performance counter
> starts
> + with immediately after is it rolls over is returned in StartValue. If
> + EndValue is not NULL, then the value that the performance counter end
> with
> + immediately before it rolls over is returned in EndValue. The 64-bit
> + frequency of the performance counter in Hz is always returned. If
> StartValue
> + is less than EndValue, then the performance counter counts up. If
> StartValue
> + is greater than EndValue, then the performance counter counts down. For
> + example, a 64-bit free running counter that counts up would have a
> StartValue
> + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running
> counter
> + that counts down would have a StartValue of 0xFFFFFF and an EndValue of
> 0.
> +
> + @param StartValue The value the performance counter starts with when
> it
> + rolls over.
> + @param EndValue The value that the performance counter ends with
> before
> + it rolls over.
> +
> + @return The frequency in Hz.
> +
> +**/
> +UINT64
> +EFIAPI
> +GetPerformanceCounterProperties (
> + OUT UINT64 *StartValue, OPTIONAL
> + OUT UINT64 *EndValue OPTIONAL
> + )
> +{
> + if (StartValue != NULL) {
> + *StartValue = 0;
> + }
> +
> + if (EndValue != NULL) {
> + *EndValue = V_PCH_ACPI_PM1_TMR_MAX_VAL - 1;
> + }
> +
> + return V_PCH_ACPI_PM1_TMR_FREQUENCY;
> +}
> +
> +/**
> + Converts elapsed ticks of performance counter to time in nanoseconds.
> +
> + This function converts the elapsed ticks of running performance counter to
> + time value in unit of nanoseconds.
> +
> + @param Ticks The number of elapsed ticks of running performance
> counter.
> +
> + @return The elapsed time in nanoseconds.
> +
> +**/
> +UINT64
> +EFIAPI
> +GetTimeInNanoSecond (
> + IN UINT64 Ticks
> + )
> +{
> + UINT64 NanoSeconds;
> + UINT32 Remainder;
> +
> + //
> + // Ticks
> + // Time = --------- x 1,000,000,000
> + // Frequency
> + //
> + NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks,
> V_PCH_ACPI_PM1_TMR_FREQUENCY, &Remainder), 1000000000u);
> +
> + //
> + // Frequency < 0x100000000, so Remainder < 0x100000000, then
> (Remainder * 1,000,000,000)
> + // will not overflow 64-bit.
> + //
> + NanoSeconds += DivU64x32 (MultU64x32 ((UINT64) Remainder,
> 1000000000u), V_PCH_ACPI_PM1_TMR_FREQUENCY);
> +
> + return NanoSeconds;
> +}
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchA
> cpiTimerLib.inf
> new file mode 100644
> index 0000000000..f30d70e01f
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchA
> cpiTimerLib.inf
> @@ -0,0 +1,51 @@
> +#/** @file
> +# Intel ICH9 Acpi Timer Instance
> +#
> +# ICH9 Acpi timer implements one instance of Timer Library. Acpi timer
> cannot be programmed,
> +# so it could be used by any types of drivers, including SMM drivers and
> Runtime drivers.
> +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = IntelPchAcpiTimerLib
> + FILE_GUID = 0C0AC8C1-E368-4d20-85FE-23EFB3DB094E
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = TimerLib
> + EDK_RELEASE_VERSION = 0x00020000
> + EFI_SPECIFICATION_VERSION = 0x00020000
> +
> + CONSTRUCTOR = IntelPchAcpiTimerLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources.common]
> + IntelPchAcpiTimerLib.c
> + CommonHeader.h
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + PcdLib
> + PciLib
> + IoLib
> + BaseLib
> +
> +[Pcd.common]
> + gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens
> /BoardClkGens.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens
> /BoardClkGens.c
> new file mode 100644
> index 0000000000..919032c2df
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens
> /BoardClkGens.c
> @@ -0,0 +1,430 @@
> +/** @file
> + Clock generator setting for multiplatform.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <BoardClkGens.h>
> +#include <Guid/SetupVariable.h>
> +#include <Ppi/ReadOnlyVariable2.h>
> +#include <Library/BaseMemoryLib.h>
> +
> +#ifndef __GNUC__
> +#pragma optimize( "", off )
> +#endif
> +
> +#define CLKGEN_EN 1
> +#define EFI_DEBUG 1
> +
> +CLOCK_GENERATOR_DETAILS mSupportedClockGeneratorTable[] =
> +{
> + { ClockGeneratorCk410, CK410_GENERATOR_ID ,
> CK410_GENERATOR_SPREAD_SPECTRUM_BYTE,
> CK410_GENERATOR_SPREAD_SPECTRUM_BIT },
> + { ClockGeneratorCk505, CK505_GENERATOR_ID ,
> CK505_GENERATOR_SPREAD_SPECTRUM_BYTE,
> CK505_GENERATOR_SPREAD_SPECTRUM_BIT }
> +};
> +
> +/**
> + Configure the clock generator using the SMBUS PPI services.
> +
> + This function performs a block write, and dumps debug information.
> +
> + @param PeiServices General purpose services available to every
> PEIM.
> + @param ClockType Clock generator's model name.
> + @param ClockAddress SMBUS address of clock generator.
> + @param ConfigurationTableLength Length of configuration table.
> + @param ConfigurationTable Pointer of configuration table.
> +
> + @retval EFI_SUCCESS - Operation success.
> +
> +**/
> +EFI_STATUS
> +ConfigureClockGenerator (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_SMBUS_PPI *SmbusPpi,
> + IN CLOCK_GENERATOR_TYPE ClockType,
> + IN UINT8 ClockAddress,
> + IN UINTN ConfigurationTableLength,
> + IN OUT UINT8 *ConfigurationTable
> + )
> +{
> +
> + EFI_STATUS Status;
> + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
> + UINT8 Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH];
> + UINTN Length;
> + EFI_SMBUS_DEVICE_COMMAND Command;
> +#if CLKGEN_CONFIG_EXTRA
> + UINT8 j;
> +#endif
> +
> + //
> + // Verify input arguments
> + //
> + ASSERT (ConfigurationTableLength >= 6);
> + ASSERT (ConfigurationTableLength <=
> MAX_CLOCK_GENERATOR_BUFFER_LENGTH);
> + ASSERT (ClockType < ClockGeneratorMax);
> + ASSERT (ConfigurationTable != NULL);
> +
> + //
> + // Read the clock generator
> + //
> + SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
> + Length = sizeof (Buffer);
> + Command = 0;
> + Status = SmbusPpi->Execute (
> + PeiServices,
> + SmbusPpi,
> + SlaveAddress,
> + Command,
> + EfiSmbusReadBlock,
> + FALSE,
> + &Length,
> + Buffer
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> +#ifdef EFI_DEBUG
> + {
> + UINT8 i;
> + for (i = 0; i < sizeof (Buffer); i++) {
> + DEBUG((EFI_D_ERROR, "CK505 default Clock Generator Byte %d: %x\n",
> i, Buffer[i]));
> + }
> +#if CLKGEN_EN
> + for (i = 0; i < ConfigurationTableLength; i++) {
> + DEBUG((EFI_D_ERROR, "BIOS structure Clock Generator Byte %d: %x\n",
> i, ConfigurationTable[i]));
> + }
> +#endif
> + }
> +#endif
> +
> + DEBUG((EFI_D_ERROR, "Expected Clock Generator ID is %x,
> expecting %x\n",
> mSupportedClockGeneratorTable[ClockType].ClockId,(Buffer[7]&0xF)));
> +
> + //
> + // Program clock generator
> + //
> + Command = 0;
> +#if CLKGEN_EN
> +#if CLKGEN_CONFIG_EXTRA
> + for (j = 0; j < ConfigurationTableLength; j++) {
> + Buffer[j] = ConfigurationTable[j];
> + }
> +
> + Buffer[30] = 0x00;
> +
> + Status = SmbusPpi->Execute (
> + PeiServices,
> + SmbusPpi,
> + SlaveAddress,
> + Command,
> + EfiSmbusWriteBlock,
> + FALSE,
> + &Length,
> + Buffer
> + );
> +#else
> + Status = SmbusPpi->Execute (
> + PeiServices,
> + SmbusPpi,
> + SlaveAddress,
> + Command,
> + EfiSmbusWriteBlock,
> + FALSE,
> + &ConfigurationTableLength,
> + ConfigurationTable
> + );
> +#endif // CLKGEN_CONFIG_EXTRA
> +#else
> + ConfigurationTable[4] = (ConfigurationTable[4] & 0x3) | (Buffer[4] &
> 0xFC);
> + Command = 4;
> + Length = 1;
> + Status = SmbusPpi->Execute (
> + PeiServices,
> + SmbusPpi,
> + SlaveAddress,
> + Command,
> + EfiSmbusWriteBlock,
> + FALSE,
> + &Length,
> + &ConfigurationTable[4]
> + );
> +#endif //CLKGEN_EN
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Dump contents after write
> + //
> + #ifdef EFI_DEBUG
> + {
> + UINT8 i;
> + SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
> + Length = sizeof (Buffer);
> + Command = 0;
> + Status = SmbusPpi->Execute (
> + PeiServices,
> + SmbusPpi,
> + SlaveAddress,
> + Command,
> + EfiSmbusReadBlock,
> + FALSE,
> + &Length,
> + Buffer
> + );
> +
> + for (i = 0; i < ConfigurationTableLength; i++) {
> + DEBUG((EFI_D_ERROR, "Clock Generator Byte %d: %x\n", i, Buffer[i]));
> + }
> + }
> + #endif
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Configure the clock generator using the SMBUS PPI services.
> +
> + This function performs a block write, and dumps debug information.
> +
> + @param PeiServices General purpose services available to every
> PEIM.
> + @param ClockType Clock generator's model name.
> + @param ClockAddress SMBUS address of clock generator.
> + @param ConfigurationTableLength Length of configuration table.
> + @param ConfigurationTable Pointer of configuration table.
> +
> +
> + @retval EFI_SUCCESS Operation success.
> +
> +**/
> +UINT8
> +ReadClockGeneratorID (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_SMBUS_PPI *SmbusPpi,
> + IN UINT8 ClockAddress
> + )
> +{
> + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
> + UINT8 Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH];
> + UINTN Length;
> + EFI_SMBUS_DEVICE_COMMAND Command;
> +
> + //
> + // Read the clock generator
> + //
> + SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
> + Length = sizeof (Buffer);
> + Command = 0;
> + SmbusPpi->Execute (
> + PeiServices,
> + SmbusPpi,
> + SlaveAddress,
> + Command,
> + EfiSmbusReadBlock,
> + FALSE,
> + &Length,
> + Buffer
> + );
> +
> + //
> + // Sanity check that the requested clock type is present in our supported
> clocks table
> + //
> + DEBUG((EFI_D_ERROR, "Expected Clock Generator ID is 0x%x\n",
> Buffer[7]));
> +
> + return (Buffer[7]);
> +}
> +
> +/**
> + Configure the clock generator to enable free-running operation. This
> keeps
> + the clocks from being stopped when the system enters C3 or C4.
> +
> + @param None
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +
> +**/
> +EFI_STATUS
> +ConfigurePlatformClocks (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *SmbusPpi
> + )
> +{
> + //
> + // Comment it out for now
> + // Not supported by Hybrid model.
> + //
> + EFI_STATUS Status;
> + UINT8 *ConfigurationTable;
> +
> + CLOCK_GENERATOR_TYPE ClockType = ClockGeneratorCk505;
> + UINT8 ConfigurationTable_Desktop[] =
> CLOCK_GENERATOR_SETTINGS_DESKTOP;
> + UINT8 ConfigurationTable_Mobile[] =
> CLOCK_GENERATOR_SETTINGS_MOBILE;
> + UINT8 ConfigurationTable_Tablet[] =
> CLOCK_GENERATOR_SEETINGS_TABLET;
> +
> + EFI_PLATFORM_INFO_HOB *PlatformInfoHob;
> + BOOLEAN EnableSpreadSpectrum;
> + SYSTEM_CONFIGURATION SystemConfiguration;
> +
> + UINTN Length;
> + EFI_SMBUS_DEVICE_COMMAND Command;
> + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
> + UINT8 Data;
> +
> + UINT8 ClockAddress = CLOCK_GENERATOR_ADDRESS;
> + UINTN VariableSize;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
> +
> + //
> + // Obtain Platform Info from HOB.
> + //
> + Status = GetPlatformInfoHob ((CONST EFI_PEI_SERVICES **) PeiServices,
> &PlatformInfoHob);
> + ASSERT_EFI_ERROR (Status);
> +
> + DEBUG((EFI_D_ERROR, "PlatformInfo protocol is working in
> ConfigurePlatformClocks()...%x\n",PlatformInfoHob->PlatformFlavor));
> +
> + //
> + // Locate SMBUS PPI
> + //
> + Status = (**PeiServices).LocatePpi (
> + (CONST EFI_PEI_SERVICES **) PeiServices,
> + &gEfiPeiSmbusPpiGuid,
> + 0,
> + NULL,
> + &SmbusPpi
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Data = 0;
> + SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
> + Length = 1;
> + Command = 0x87; //Control Register 7 Vendor ID Check
> + Status = ((EFI_PEI_SMBUS_PPI *) SmbusPpi)->Execute (
> + PeiServices,
> + SmbusPpi,
> + SlaveAddress,
> + Command,
> + EfiSmbusReadByte,
> + FALSE,
> + &Length,
> + &Data
> + );
> +
> + if (EFI_ERROR (Status) || ((Data & 0x0F) != CK505_GENERATOR_ID)) {
> + DEBUG((EFI_D_ERROR, "Clock Generator CK505 Not Present, vendor ID
> on board is %x\n",(Data & 0x0F)));
> + return EFI_SUCCESS;
> +}
> +
> + EnableSpreadSpectrum = FALSE;
> + VariableSize = sizeof (SYSTEM_CONFIGURATION);
> + ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
> +
> + Status = (*PeiServices)->LocatePpi (
> + (CONST EFI_PEI_SERVICES **) PeiServices,
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (VOID **) &Variable
> + );
> + //
> + // Use normal setup default from NVRAM variable,
> + // the Platform Mode (manufacturing/safe/normal) is handle in
> PeiGetVariable.
> + //
> + VariableSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = Variable->GetVariable (Variable,
> + L"Setup",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VariableSize,
> + &SystemConfiguration);
> + if (EFI_ERROR (Status) || VariableSize != sizeof(SYSTEM_CONFIGURATION))
> {
> + //The setup variable is corrupted
> + VariableSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = Variable->GetVariable(Variable,
> + L"SetupRecovery",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VariableSize,
> + &SystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> + if(!EFI_ERROR (Status)){
> + EnableSpreadSpectrum = SystemConfiguration.EnableClockSpreadSpec;
> + }
> +
> + //
> + // Perform platform-specific intialization dependent upon Board ID:
> + //
> + DEBUG((EFI_D_ERROR, "board id is %x, platform id
> is %x\n",PlatformInfoHob->BoardId,PlatformInfoHob->PlatformFlavor));
> +
> +
> + switch (PlatformInfoHob->BoardId) {
> + case BOARD_ID_MINNOW2:
> + case BOARD_ID_MINNOW2_TURBOT:
> + default:
> + switch(PlatformInfoHob->PlatformFlavor) {
> + case FlavorTablet:
> + ConfigurationTable = ConfigurationTable_Tablet;
> + Length = sizeof (ConfigurationTable_Tablet);
> + break;
> + case FlavorMobile:
> + ConfigurationTable = ConfigurationTable_Mobile;
> + Length = sizeof (ConfigurationTable_Mobile);
> + break;
> + case FlavorDesktop:
> + default:
> + ConfigurationTable = ConfigurationTable_Desktop;
> + Length = sizeof (ConfigurationTable_Desktop);
> + break;
> + }
> + break;
> + }
> +
> + //
> + // Perform common clock initialization:
> + //
> + // Program Spread Spectrum function.
> + //
> + if (EnableSpreadSpectrum)
> + {
> +
> ConfigurationTable[mSupportedClockGeneratorTable[ClockType].SpreadSpe
> ctrumByteOffset] |=
> mSupportedClockGeneratorTable[ClockType].SpreadSpectrumBitOffset;
> + } else {
> +
> ConfigurationTable[mSupportedClockGeneratorTable[ClockType].SpreadSpe
> ctrumByteOffset] &=
> ~(mSupportedClockGeneratorTable[ClockType].SpreadSpectrumBitOffset);
> + }
> +
> +
> +#if CLKGEN_EN
> + Status = ConfigureClockGenerator (PeiServices, SmbusPpi, ClockType,
> ClockAddress, Length, ConfigurationTable);
> + ASSERT_EFI_ERROR (Status);
> +#endif // CLKGEN_EN
> + return EFI_SUCCESS;
> +}
> +
> +static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK|
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> + &gEfiPeiSmbusPpiGuid,
> + ConfigurePlatformClocks
> + }
> +};
> +
> +EFI_STATUS
> +InstallPlatformClocksNotify (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> +
> + DEBUG ((EFI_D_INFO, "InstallPlatformClocksNotify()...\n"));
> +
> + Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
> + ASSERT_EFI_ERROR (Status);
> + return EFI_SUCCESS;
> +
> +}
> +
> +#ifndef __GNUC__
> +#pragma optimize( "", on )
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens
> /BoardClkGens.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens
> /BoardClkGens.h
> new file mode 100644
> index 0000000000..e153933d72
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens
> /BoardClkGens.h
> @@ -0,0 +1,255 @@
> +/**@file
> + Clock generator setting for multiplatform.
> +
> + This file includes package header files, library classes.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +**/
> +
> +#ifndef _BOARD_CLK_GEN_H_
> +#define _BOARD_CLK_GEN_H_
> +
> +#include <PiPei.h>
> +#include <Library/HobLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/SmbusLib.h>
> +#include <Ppi/Smbus.h>
> +#include <IndustryStandard/SmBus.h>
> +#include <Guid/PlatformInfo.h>
> +
> +
> +#define CLOCK_GENERATOR_ADDRESS 0xd2
> +
> +#define CLOCK_GENERATOR_SEETINGS_TABLET {0xB1, 0x82, 0xFF, 0xBF,
> 0xFF, 0x80}
> +#define CLOCK_GENERATOR_SETTINGS_MOBILE {0xB1, 0x82, 0xFF, 0xBF,
> 0xFF, 0x80}
> +#define CLOCK_GENERATOR_SETTINGS_DESKTOP {0xB1, 0x82, 0xFF, 0xBF,
> 0xFF, 0x80}
> +
> +typedef enum {
> + ClockGeneratorCk410,
> + ClockGeneratorCk505,
> + ClockGeneratorMax
> +} CLOCK_GENERATOR_TYPE;
> +
> +typedef struct {
> + CLOCK_GENERATOR_TYPE ClockType;
> + UINT8 ClockId;
> + UINT8 SpreadSpectrumByteOffset;
> + UINT8 SpreadSpectrumBitOffset;
> +} CLOCK_GENERATOR_DETAILS;
> +
> +#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20
> +
> +//
> +// CK410 Definitions
> +//
> +#define CK410_GENERATOR_ID 0x65
> +#define CK410_GENERATOR_SPREAD_SPECTRUM_BYTE 1
> +#define CK410_GENERATOR_SPREAD_SPECTRUM_BIT BIT0
> +#define CK410_GENERATOR_CLOCK_FREERUN_BYTE 4
> +#define CK410_GENERATOR_CLOCK_FREERUN_BIT (BIT0 | BIT1 | BIT2)
> +
> +//
> +// CK505 Definitions
> +//
> +#define VF_CK505_GENERATOR_ID 0x5
> +#define CK505_GENERATOR_ID 0x5 // Confirmed readout is 5
> +#define CK505_GENERATOR_SPREAD_SPECTRUM_BYTE 4
> +#define CK505_GENERATOR_SPREAD_SPECTRUM_BIT (BIT0 | BIT1)
> +#define CK505_GENERATOR_PERCENT_SPREAD_BYTE 1
> +#define CK505_GENERATOR_PERCENT_MASK ~(0xE)
> +#define CK505_GENERATOR_PERCENT_250_VALUE 0xC
> +#define CK505_GENERATOR_PERCENT_050_VALUE 0x4
> +#define CK505_GENERATOR_PERCENT_000_VALUE 0x2
> +
> +//
> +// IDT Definitions
> +//
> +#define IDT_GENERATOR_ID_REVA 0x1 //IDT Rev A
> +#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BYTE 0
> +#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BIT BIT0
> +#define IDTRevA_GENERATOR_PERCENT_SPREAD_BYTE 5
> +#define IDTRevA_GENERATOR_PERCENT_250_VALUE 0xF
> +#define IDTRevA_GENERATOR_PERCENT_050_VALUE 0x3
> +#define IDTRevA_GENERATOR_PERCENT_000_VALUE 0xE
> +#define IDTRevA_GENERATOR_PERCENT_MASK ~(0xF)
> +
> +#define IDT_GENERATOR_ID_REVB 0x11 //IDT RevB
> +#define IDT_GENERATOR_ID_REVD 0x21 //IDT RevD
> +
> +//
> +// CLOCK CONTROLLER
> +// SmBus address to read DIMM SPD
> +//
> +#define SMBUS_BASE_ADDRESS 0xEFA0
> +#define SMBUS_BUS_DEV_FUNC 0x1F0300
> +#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 4
> +#define SMBUS_ADDR_CH_A_1 0xA0
> +#define SMBUS_ADDR_CH_A_2 0xA2
> +#define SMBUS_ADDR_CH_B_1 0xA4
> +#define SMBUS_ADDR_CH_B_2 0xA6
> +
> +//
> +// Bits for FWH_DEC_EN1�Firmware Hub Decode Enable Register (LPC
> I/F�D31:F0)
> +//
> +#define B_ICH_LPC_FWH_BIOS_DEC_F0 0x4000
> +#define B_ICH_LPC_FWH_BIOS_DEC_E0 0x1000
> +#define B_ICH_LPC_FWH_BIOS_DEC_E8 0x2000
> +#define B_ICH_LPC_FWH_BIOS_LEG_F 0x0080
> +#define B_ICH_LPC_FWH_BIOS_LEG_E 0x0040
> +
> +
> +//
> +// An arbitrary maximum length for clock generator buffers
> +//
> +#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20
> +
> +//
> +// SmBus Bus Device Function and Register Definitions
> +//
> +#define SMBUS_BUS_NUM 0
> +#define SMBUS_DEV_NUM 31
> +#define SMBUS_FUNC_NUM 3
> +#define SMBUS_BUS_DEV_FUNC_NUM \
> + SB_PCI_CFG_ADDRESS(SMBUS_BUS_NUM, SMBUS_DEV_NUM,
> SMBUS_FUNC_NUM, 0)
> +
> +//
> +//ICH7: SMBus I/O Space Equates;
> +//
> +#define BIT_SLAVE_ADDR BIT00
> +#define BIT_COMMAND BIT01
> +#define BIT_DATA BIT02
> +#define BIT_COUNT BIT03
> +#define BIT_WORD BIT04
> +#define BIT_CONTROL BIT05
> +#define BIT_PEC BIT06
> +#define BIT_READ BIT07
> +#define SMBUS_IO_READ_BIT BIT00
> +
> +
> +#define SMB_CMD_QUICK 0x00
> +#define SMB_CMD_BYTE 0x04
> +#define SMB_CMD_BYTE_DATA 0x08
> +#define SMB_CMD_WORD_DATA 0x0C
> +#define SMB_CMD_PROCESS_CALL 0x10
> +#define SMB_CMD_BLOCK 0x14
> +#define SMB_CMD_I2C_READ 0x18
> +#define SMB_CMD_RESERVED 0x1c
> +
> +#define HST_STS_BYTE_DONE 0x80
> +#define SMB_HST_STS 0x000
> +#define SMB_HST_CNT 0x002
> +#define SMB_HST_CMD 0x003
> +#define SMB_HST_ADD 0x004
> +#define SMB_HST_DAT_0 0x005
> +#define SMB_HST_DAT_1 0x006
> +#define SMB_HST_BLK_DAT 0x007
> +#define SMB_PEC 0x008
> +#define SMB_RCV_SLVA 0x009
> +#define SMB_SLV_DAT 0x00A
> +#define SMB_AUX_STS 0x00C
> +#define SMB_AUX_CTL 0x00D
> +#define SMB_SMLINK_PIN_CTL 0x00E
> +#define SMB_SMBUS_PIN_CTL 0x00F
> +#define SMB_SLV_STS 0x010
> +#define SMB_SLV_CMD 0x011
> +#define SMB_NTFY_DADDR 0x014
> +#define SMB_NTFY_DLOW 0x016
> +#define SMB_NTFY_DHIGH 0x017
> +
> +//
> +// PCI Register Definitions - use SmbusPolicyPpi->PciAddress + offset listed
> below
> +//
> +#define R_COMMAND 0x04 // PCI Command Register, 16bit
> +#define B_IOSE 0x01 // RW
> +#define R_BASE_ADDRESS 0x20 // PCI BAR for SMBus I/O
> +#define B_BASE_ADDRESS 0xFFE0 // RW
> +#define R_HOST_CONFIGURATION 0x40 // SMBus Host
> Configuration Register
> +#define B_HST_EN 0x01 // RW
> +#define B_SMB_SMI_EN 0x02 // RW
> +#define B_I2C_EN 0x04 // RW
> +//
> +// I/O Register Definitions - use SmbusPolicyPpi->BaseAddress + offset
> listed below
> +//
> +#define HOST_STATUS_REGISTER 0x00 // Host Status Register R/W
> +#define HST_STS_HOST_BUSY 0x01 // RO
> +#define HST_STS_INTR 0x02 // R/WC
> +#define HST_STS_DEV_ERR 0x04 // R/WC
> +#define HST_STS_BUS_ERR 0x08 // R/WC
> +#define HST_STS_FAILED 0x10 // R/WC
> +#define SMBUS_B_SMBALERT_STS 0x20 // R/WC
> +#define HST_STS_INUSE 0x40 // R/WC
> +#define SMBUS_B_BYTE_DONE_STS 0x80 // R/WC
> +#define SMBUS_B_HSTS_ALL 0xFF // R/WC
> +#define HOST_CONTROL_REGISTER 0x02 // Host Control Register
> R/W
> +#define HST_CNT_INTREN 0x01 // RW
> +#define HST_CNT_KILL 0x02 // RW
> +#define SMBUS_B_SMB_CMD 0x1C // RW
> +#define SMBUS_V_SMB_CMD_QUICK 0x00
> +#define SMBUS_V_SMB_CMD_BYTE 0x04
> +#define SMBUS_V_SMB_CMD_BYTE_DATA 0x08
> +#define SMBUS_V_SMB_CMD_WORD_DATA 0x0C
> +#define SMBUS_V_SMB_CMD_PROCESS_CALL 0x10
> +#define SMBUS_V_SMB_CMD_BLOCK 0x14
> +#define SMBUS_V_SMB_CMD_IIC_READ 0x18
> +#define SMBUS_B_LAST_BYTE 0x20 // WO
> +#define HST_CNT_START 0x40 // WO
> +#define HST_CNT_PEC_EN 0x80 // RW
> +#define HOST_COMMAND_REGISTER 0x03 // Host Command
> Register R/W
> +#define XMIT_SLAVE_ADDRESS_REGISTER 0x04 // Transmit Slave
> Address Register R/W
> +#define SMBUS_B_RW_SEL 0x01 // RW
> +#define SMBUS_B_ADDRESS 0xFE // RW
> +#define HOST_DATA_0_REGISTER 0x05 // Data 0 Register R/W
> +#define HOST_DATA_1_REGISTER 0x06 // Data 1 Register R/W
> +#define HOST_BLOCK_DATA_BYTE_REGISTER 0x07 // Host Block Data
> Register R/W
> +#define SMBUS_R_PEC 0x08 // Packet Error Check Data Register
> R/W
> +#define SMBUS_R_RSA 0x09 // Receive Slave Address Register
> R/W
> +#define SMBUS_B_SLAVE_ADDR 0x7F // RW
> +#define SMBUS_R_SD 0x0A // Receive Slave Data Register R/W
> +#define SMBUS_R_AUXS 0x0C // Auxiliary Status Register R/WC
> +#define SMBUS_B_CRCE 0x01 //R/WC
> +#define AUXILIARY_CONTROL_REGISTER 0x0D // Auxiliary Control
> Register R/W
> +#define SMBUS_B_AAC 0x01 //R/W
> +#define SMBUS_B_E32B 0x02 //R/W
> +#define SMBUS_R_SMLC 0x0E // SMLINK Pin Control Register R/W
> +#define SMBUS_B_SMLINK0_CUR_STS 0x01 // RO
> +#define SMBUS_B_SMLINK1_CUR_STS 0x02 // RO
> +#define SMBUS_B_SMLINK_CLK_CTL 0x04 // RW
> +#define SMBUS_R_SMBC 0x0F // SMBus Pin Control Register R/W
> +#define SMBUS_B_SMBCLK_CUR_STS 0x01 // RO
> +#define SMBUS_B_SMBDATA_CUR_STS 0x02 // RO
> +#define SMBUS_B_SMBCLK_CTL 0x04 // RW
> +#define SMBUS_R_SSTS 0x10 // Slave Status Register R/WC
> +#define SMBUS_B_HOST_NOTIFY_STS 0x01 // R/WC
> +#define SMBUS_R_SCMD 0x11 // Slave Command Register R/W
> +#define SMBUS_B_HOST_NOTIFY_INTREN 0x01 // R/W
> +#define SMBUS_B_HOST_NOTIFY_WKEN 0x02 // R/W
> +#define SMBUS_B_SMBALERT_DIS 0x04 // R/W
> +#define SMBUS_R_NDA 0x14 // Notify Device Address Register
> RO
> +#define SMBUS_B_DEVICE_ADDRESS 0xFE // RO
> +#define SMBUS_R_NDLB 0x16 // Notify Data Low Byte Register RO
> +#define SMBUS_R_NDHB 0x17 // Notify Data High Byte Register
> RO
> +#define BUS_TRIES 3 // How many times to retry on Bus Errors
> +#define SMBUS_NUM_RESERVED 21 // Number of device addresses
> that are
> + // reserved by the SMBus spec.
> +#define SMBUS_ADDRESS_ARP 0xC2 >> 1
> +#define SMBUS_DATA_PREPARE_TO_ARP 0x01
> +#define SMBUS_DATA_RESET_DEVICE 0x02
> +#define SMBUS_DATA_GET_UDID_GENERAL 0x03
> +#define SMBUS_DATA_ASSIGN_ADDRESS 0x04
> +#define SMBUS_GET_UDID_LENGTH 17 // 16 byte UDID + 1 byte address
> +
> +
> +EFI_STATUS
> +ConfigurePlatformClocks (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *SmbusPpi
> + );
> +
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/B
> oardGpios.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/B
> oardGpios.c
> new file mode 100644
> index 0000000000..5790d045fc
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/B
> oardGpios.c
> @@ -0,0 +1,531 @@
> +/** @file
> + Gpio setting for multiplatform..
> +
> + Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <BoardGpios.h>
> +#include <Guid/SetupVariable.h>
> +
> +//
> +//AlpineValley platform ocde begin
> +//
> +#define AV_SC_REG_GPIOS_MUXES_SEL0 0x48
> +#define AV_SC_REG_GPIOS_MUXES_SEL1 0x4C
> +#define AV_SC_REG_GPIOS_MUXES_SEL2 0x50
> +#define AV_SC_REG_GPIOS_MUXES_EN0 0x54
> +#define AV_SC_REG_GPIOS_MUXES_EN1 0x58
> +#define AV_SC_REG_GPIOS_MUXES_EN2 0x5C
> +//
> +//AlpineValley platform code end
> +//
> +
> +EFI_GUID gPeiSmbusPpiGuid = EFI_PEI_SMBUS_PPI_GUID;
> +
> +/**
> + @param None
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +
> +**/
> +EFI_STATUS
> +ConfigurePlatformSysCtrlGpio (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *SmbusPpi
> + )
> +{
> + //
> + //AlpineValley platform code begin
> + //
> + // Initialize GPIO Settings:
> + //
> + UINT32 Status;
> + EFI_PLATFORM_INFO_HOB *PlatformInfoHob;
> +
> + DEBUG ((EFI_D_INFO, "ConfigurePlatformSysCtrlGpio()...\n"));
> +
> + //
> + // Obtain Platform Info from HOB.
> + //
> + Status = GetPlatformInfoHob ((const EFI_PEI_SERVICES **)PeiServices,
> &PlatformInfoHob);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // The GPIO settings are dependent upon the platform. Obtain the Board
> ID through
> + // the EC to determine the current platform.
> + //
> + DEBUG ((EFI_D_INFO, "Platform Flavor | Board ID = 0x%X | 0x%X\n",
> PlatformInfoHob->PlatformFlavor, PlatformInfoHob->BoardId));
> +
> +
> +
> + Status = (**PeiServices).LocatePpi (
> + (const EFI_PEI_SERVICES **)PeiServices,
> + &gPeiSmbusPpiGuid,
> + 0,
> + NULL,
> + (void **)&SmbusPpi
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Select/modify the GPIO initialization data based on the Board ID.
> + //
> + switch (PlatformInfoHob->BoardId)
> + {
> + default:
> + Status = EFI_SUCCESS;
> +
> + //
> + // Do nothing for other RVP boards.
> + //
> + break;
> + }
> + return Status;
> +}
> +
> +static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK|
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> + &gEfiPeiSmbusPpiGuid,
> + ConfigurePlatformSysCtrlGpio
> + }
> +};
> +
> +EFI_STATUS
> +InstallPlatformSysCtrlGPIONotify (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> +
> + DEBUG ((EFI_D_INFO, "InstallPlatformSysCtrlGPIONotify()...\n"));
> +
> + Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
> + ASSERT_EFI_ERROR (Status);
> + return EFI_SUCCESS;
> +
> +}
> +
> +#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3
> Enable
> +
> +/**
> + Returns the Correct GPIO table for Mobile/Desktop respectively.
> + Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get
> correctly.
> +
> + @param PeiServices General purpose services available to every
> PEIM.
> + @param PlatformInfoHob PlatformInfoHob pointer with
> PlatformFlavor specified.
> + @param BoardId BoardId ID as determined through the EC.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> + @retval EFI_DEVICE_ERROR KSC fails to respond.
> +
> +**/
> +EFI_STATUS
> +MultiPlatformGpioTableInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;
> + UINTN VarSize;
> + SYSTEM_CONFIGURATION SystemConfiguration;
> +
> + DEBUG ((EFI_D_INFO, "MultiPlatformGpioTableInit()...\n"));
> +
> + //
> + // Select/modify the GPIO initialization data based on the Board ID.
> + //
> + switch (PlatformInfoHob->BoardId) {
> +
> + case BOARD_ID_MINNOW2: // Minnow2
> + case BOARD_ID_MINNOW2_TURBOT:
> + Status = (**PeiServices).LocatePpi (
> + PeiServices,
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (void **)&PeiReadOnlyVarPpi
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + VarSize = sizeof (SYSTEM_CONFIGURATION);
> + Status = PeiReadOnlyVarPpi->GetVariable (
> + PeiReadOnlyVarPpi,
> + PLATFORM_SETUP_VARIABLE_NAME,
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> +
> + if (SystemConfiguration.GpioWakeCapability == 1) {
> + PlatformInfoHob->PlatformCfioData =
> (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData2;
> + }
> + else {
> + PlatformInfoHob->PlatformCfioData =
> (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData;
> + }
> +
> + PlatformInfoHob->PlatformGpioData_NC =
> (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_NC[0];
> + PlatformInfoHob->PlatformGpioData_SC =
> (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SC[0];
> + PlatformInfoHob->PlatformGpioData_SUS =
> (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SUS[0];
> + break;
> +
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +UINT32
> +GPIORead32 (
> + IN UINT32 mmio_conf
> + )
> +{
> + UINT32 conf_val;
> + UINT32 i;
> + conf_val = MmioRead32(mmio_conf);
> + for(i=0;i<5;i++){
> + if(conf_val == 0xffffffff)
> + conf_val = MmioRead32(mmio_conf);
> + else
> + break;
> + }
> +
> + return conf_val;
> +}
> +
> +/**
> +
> + Set GPIO CONF0 and PAD_VAL registers for NC/SC/SUS GPIO clusters
> +
> + @param Gpio_Mmio_Offset GPIO_SCORE_OFFSET or
> GPIO_NCORE_OFFSET or GPIO_SSUS_OFFSET.
> + @param Gpio_Pin_Num Pin numbers to config for each GPIO
> clusters.
> + @param Gpio_Conf_Data GPIO_CONF_PAD_INIT data array for each
> GPIO clusters.
> +
> +**/
> +VOID
> +InternalGpioConfig (
> + IN UINT32 Gpio_Mmio_Offset,
> + IN UINT32 Gpio_Pin_Num,
> + GPIO_CONF_PAD_INIT* Gpio_Conf_Data
> + )
> +{
> + UINT32 index;
> + UINT32 mmio_conf0;
> + UINT32 mmio_padval;
> + PAD_CONF0 conf0_val;
> + PAD_VAL pad_val;
> +
> + //
> + // GPIO WELL -- Memory base registers
> + //
> +
> + // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
> + // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
> + //
> + for(index=0; index < Gpio_Pin_Num; index++)
> + {
> + //
> + // Calculate the MMIO Address for specific GPIO pin CONF0 register
> pointed by index.
> + //
> + mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset +
> R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
> + mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset +
> R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
> +
> +#ifdef EFI_DEBUG
> + DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
> +
> +#endif
> + DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull
> Up/Down = %d, MMIO Base = 0x%08x, ",
> + Gpio_Conf_Data[index].usage,
> + Gpio_Conf_Data[index].func,
> + Gpio_Conf_Data[index].int_type,
> + Gpio_Conf_Data[index].pull,
> + mmio_conf0));
> +
> + //
> + // Step 1: PadVal Programming.
> + //
> + pad_val.dw = GPIORead32(mmio_padval);
> +
> + //
> + // Config PAD_VAL only for GPIO (Non-Native) Pin
> + //
> + if(Native != Gpio_Conf_Data[index].usage)
> + {
> + pad_val.dw &= ~0x6; // Clear bits 1:2
> + pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2
> according to PadVal
> +
> + //
> + // set GPO default value
> + //
> + if(Gpio_Conf_Data[index].usage == GPO &&
> Gpio_Conf_Data[index].gpod4 != NA)
> + {
> + pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
> + }
> + }
> +
> +
> + DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
> +
> + MmioWrite32(mmio_padval, pad_val.dw);
> +
> + //
> + // Step 2: CONF0 Programming
> + // Read GPIO default CONF0 value, which is assumed to be default value
> after reset.
> + //
> + conf0_val.dw = GPIORead32(mmio_conf0);
> +
> + //
> + // Set Function #
> + //
> + conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
> +
> + if(GPO == Gpio_Conf_Data[index].usage)
> + {
> + //
> + // If used as GPO, then internal pull need to be disabled.
> + //
> + conf0_val.r.Pull_assign = 0; // Non-pull
> + }
> + else
> + {
> + //
> + // Set PullUp / PullDown
> + //
> + if(P_20K_H == Gpio_Conf_Data[index].pull)
> + {
> + conf0_val.r.Pull_assign = 0x1; // PullUp
> + conf0_val.r.Pull_strength = 0x2;// 20K
> + }
> + else if(P_20K_L == Gpio_Conf_Data[index].pull)
> + {
> + conf0_val.r.Pull_assign = 0x2; // PullDown
> + conf0_val.r.Pull_strength = 0x2;// 20K
> + }
> + else if(P_10K_H == Gpio_Conf_Data[index].pull)
> + {
> + conf0_val.r.Pull_assign = 0x1; // PullUp
> + conf0_val.r.Pull_strength = 0x1;// 10K
> + }
> + else if(P_10K_L == Gpio_Conf_Data[index].pull)
> + {
> + conf0_val.r.Pull_assign = 0x2; // PullDown
> + conf0_val.r.Pull_strength = 0x1;// 10K
> + }
> + else if(P_2K_H == Gpio_Conf_Data[index].pull)
> + {
> + conf0_val.r.Pull_assign = 0x1; // PullUp
> + conf0_val.r.Pull_strength = 0x0;// 2K
> + }
> + else if(P_2K_L == Gpio_Conf_Data[index].pull)
> + {
> + conf0_val.r.Pull_assign = 0x2; // PullDown
> + conf0_val.r.Pull_strength = 0x0;// 2K
> + }
> + else if(P_NONE == Gpio_Conf_Data[index].pull)
> + {
> + conf0_val.r.Pull_assign = 0; // Non-pull
> + }
> + else
> + {
> + ASSERT(FALSE); // Invalid value
> + }
> + }
> +
> +
> + //
> + // Set INT Trigger Type
> + //
> + conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
> +
> + //
> + // Set INT Trigger Type
> + //
> + if(TRIG_ == Gpio_Conf_Data[index].int_type)
> + {
> + //
> + // Interrupt not capable, clear bits 27:24
> + //
> + }
> + else
> + {
> + conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
> + }
> +
> + DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
> +
> + //
> + // Write back the targeted GPIO config value according to platform (board)
> GPIO setting.
> + //
> + MmioWrite32 (mmio_conf0, conf0_val.dw);
> + }
> +
> + //
> + // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
> + // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
> + //
> +}
> +
> +/**
> + Returns the Correct GPIO table for Mobile/Desktop respectively.
> + Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get
> correctly.
> +
> + @param PeiServices General purpose services available to every
> PEIM.
> + @param PlatformInfoHob PlatformInfoHob pointer with
> PlatformFlavor specified.
> + @param BoardId BoardId ID as determined through the EC.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> + @retval EFI_DEVICE_ERROR KSC fails to respond.
> +
> +**/
> +EFI_STATUS
> +MultiPlatformGpioProgram (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + )
> +{
> +#if !_SIMIC_
> + CFIO_INIT_STRUCT* PlatformCfioDataPtr;
> +
> + PlatformCfioDataPtr = (CFIO_INIT_STRUCT *) (UINTN) PlatformInfoHob-
> >PlatformCfioData;
> + DEBUG ((EFI_D_INFO, "MultiPlatformGpioProgram()...\n"));
> +
> + //
> + // SCORE GPIO WELL -- IO base registers
> + //
> +
> + //
> + // GPIO_USE_SEL Register -> 1 = GPIO 0 = Native
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,
> PlatformCfioDataPtr->Use_Sel_SC0);
> +
> + //
> + // Set GP_LVL Register
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL ,
> PlatformCfioDataPtr->GP_Lvl_SC0);
> +
> + //
> + // GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL,
> PlatformCfioDataPtr->Io_Sel_SC0);
> +
> + //
> + // GPIO Triger Positive Edge Enable Register
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TPE,
> PlatformCfioDataPtr->TPE_SC0);
> +
> + //
> + // GPIO Trigger Negative Edge Enable Register
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TNE,
> PlatformCfioDataPtr->TNE_SC0);
> +
> + //
> + // GPIO Trigger Status
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TS,
> PlatformCfioDataPtr->TS_SC0);
> +
> + //
> + // GPIO_USE_SEL2 Register -> 1 = GPIO 0 = Native
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL2,
> PlatformCfioDataPtr->Use_Sel_SC1);
> +
> + //
> + // Set GP_LVL2 Register
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2,
> PlatformCfioDataPtr->GP_Lvl_SC1);
> +
> + //
> + // GP_IO_SEL2 Register -> 1 = Input 0 = Output. If Native Mode don't care
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL2,
> PlatformCfioDataPtr->Io_Sel_SC1);
> +
> + //
> + // GPIO_USE_SEL3 Register -> 1 = GPIO 0 = Native
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL3,
> PlatformCfioDataPtr->Use_Sel_SC2);
> +
> + //
> + // Set GP_LVL3 Register
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL3,
> PlatformCfioDataPtr->GP_Lvl_SC2);
> +
> + //
> + // GP_IO_SEL3 Register -> 1 = Input 0 = Output if Native Mode don't care
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL3,
> PlatformCfioDataPtr->Io_Sel_SC2);
> +
> + //
> + // SUS GPIO WELL -- IO base registers
> + //
> +
> + //
> + // GPIO_USE_SEL Register -> 1 = GPIO 0 = Native
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_USE_SEL,
> PlatformCfioDataPtr->Use_Sel_SS);
> +
> + //
> + // Set GP_LVL Register
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_LVL ,
> PlatformCfioDataPtr->GP_Lvl_SS);
> +
> + //
> + // GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care.
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_IO_SEL,
> PlatformCfioDataPtr->Io_Sel_SS);
> +
> + //
> + // GPIO Triger Positive Edge Enable Register.
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TPE,
> PlatformCfioDataPtr->TPE_SS);
> +
> + //
> + // GPIO Trigger Negative Edge Enable Register.
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TNE,
> PlatformCfioDataPtr->TNE_SS);
> +
> + //
> + // GPIO Trigger Status.
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TS,
> PlatformCfioDataPtr->TS_SS);
> +
> + //
> + // GPIO Wake Enable.
> + //
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_WAKE_EN,
> PlatformCfioDataPtr->WE_SS);
> +
> + //
> + // Config SC/NC/SUS GPIO Pins
> + //
> + switch (PlatformInfoHob->BoardId) {
> + case BOARD_ID_MINNOW2:
> + case BOARD_ID_MINNOW2_TURBOT:
> + DEBUG ((EFI_D_INFO, "Start to config Minnow2 GPIO pins\n"));
> + InternalGpioConfig(GPIO_SCORE_OFFSET,
> sizeof(mMinnow2_GpioInitData_SC)/sizeof(mMinnow2_GpioInitData_SC[0]
> ), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob-
> >PlatformGpioData_SC);
> + InternalGpioConfig(GPIO_NCORE_OFFSET,
> sizeof(mMinnow2_GpioInitData_NC)/sizeof(mMinnow2_GpioInitData_NC[0
> ]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob-
> >PlatformGpioData_NC);
> + InternalGpioConfig(GPIO_SSUS_OFFSET,
> sizeof(mMinnow2_GpioInitData_SUS)/sizeof(mMinnow2_GpioInitData_SUS
> [0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob-
> >PlatformGpioData_SUS);
> + break;
> + default:
> +
> + break;
> + }
> +
> + //
> + // configure the CFIO Pnp settings
> + //
> + if (PlatformInfoHob->CfioEnabled) {
> + if (PlatformInfoHob->BoardId == BOARD_ID_MINNOW2 ||
> PlatformInfoHob->BoardId == BOARD_ID_MINNOW2_TURBOT){
> + InternalGpioConfig(GPIO_SCORE_OFFSET,
> sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI)/sizeof(mNB_BB_FAB3_GpioIni
> tData_SC_TRI[0]), (GPIO_CONF_PAD_INIT *) (UINTN)PlatformInfoHob-
> >PlatformGpioData_SC_TRI);
> + }
> + }
> +#else
> + DEBUG ((EFI_D_INFO, "Skip MultiPlatformGpioProgram()...for SIMICS or
> HYB model\n"));
> +#endif
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/B
> oardGpios.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/B
> oardGpios.h
> new file mode 100644
> index 0000000000..0e19819b22
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/B
> oardGpios.h
> @@ -0,0 +1,324 @@
> +/**@file
> + Gpio setting for multiplatform.
> +
> + This file includes package header files, library classes.
> +
> + Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +**/
> +
> +#ifndef _BOARDGPIOS_H_
> +#define _BOARDGPIOS_H_
> +
> +#include <PiPei.h>
> +#include "PchAccess.h"
> +#include "PlatformBaseAddresses.h"
> +#include <../MultiPlatformLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/HobLib.h>
> +#include <Guid/PlatformInfo.h>
> +#include <Ppi/Smbus.h>
> +#include <Ppi/ReadOnlyVariable2.h>
> +#include <Guid/SetupVariable.h>
> +
> +
> +GPIO_CONF_PAD_INIT mNB_BB_FAB3_GpioInitData_SC_TRI[] =
> +{
> +// Pad Name GPIO Number Used As GPO Default Function#
> INT Capable Interrupt Type PULL H/L MMIO Offset
> +GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48
> " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
> +GPIO_INIT_ITEM("PLT_CLK0 GPIOC_96
> " ,TRISTS ,NA ,F0 , , ,NONE ,0x6a),
> +GPIO_INIT_ITEM("PLT_CLK3 GPIOC_99
> " ,TRISTS ,NA ,F0 , , ,NONE ,0x68),
> +};
> +
> +//
> +// Minnow2
> +//
> +#define MINNOW2_GPIO_USE_SEL_VAL_0_31 0x00000000
> +#define MINNOW2_GPIO_USE_SEL_VAL_32_63 0x00000000
> +#define MINNOW2_GPIO_USE_SEL_VAL_64_70 0x00000000
> +#define MINNOW2_GPIO_USE_SEL_VAL_64_70 0x00000000
> +#define MINNOW2_GPIO_USE_SEL_VAL_SUS 0x00000000
> +#define MINNOW2_GPIO_USE_SEL_VAL_SUS2 0x00000001
> +
> +
> +#define MINNOW2_GPIO_IO_SEL_VAL_0_31 0x00000000
> +#define MINNOW2_GPIO_IO_SEL_VAL_32_63 0x00000000
> +#define MINNOW2_GPIO_IO_SEL_VAL_64_70 0x00000000
> +#define MINNOW2_GPIO_IO_SEL_VAL_SUS 0x00000000
> +#define MINNOW2_GPIO_IO_SEL_VAL_SUS2 0x00000001
> +
> +
> +#define MINNOW2_GPIO_LVL_VAL_0_31 0x00000000
> +#define MINNOW2_GPIO_LVL_VAL_32_63 0x00000000
> +#define MINNOW2_GPIO_LVL_VAL_64_70 0x00000000
> +#define MINNOW2_GPIO_LVL_VAL_SUS 0x00000000
> +#define MINNOW2_GPIO_LVL_VAL_SUS2 0x00000001
> +
> +#define MINNOW2_GPIO_TPE_VAL_0_31 0x00000000
> +#define MINNOW2_GPIO_TPE_VAL_SUS 0x00000000
> +#define MINNOW2_GPIO_TPE_VAL_SUS2 0x00000001
> +
> +#define MINNOW2_GPIO_TNE_VAL_0_31 0x00000000
> +#define MINNOW2_GPIO_TNE_VAL_SUS 0x00000000
> +#define MINNOW2_GPIO_TNE_VAL_SUS2 0x00000001
> +
> +#define MINNOW2_GPIO_TS_VAL_0_31 0x00000000
> +#define MINNOW2_GPIO_TS_VAL_SUS 0x00000000
> +#define MINNOW2_GPIO_TS_VAL_SUS2 0x00000001
> +
> +static CFIO_INIT_STRUCT mMinnow2CfioInitData =
> +{
> + MINNOW2_GPIO_USE_SEL_VAL_0_31,
> + MINNOW2_GPIO_USE_SEL_VAL_32_63,
> + MINNOW2_GPIO_USE_SEL_VAL_64_70,
> + MINNOW2_GPIO_USE_SEL_VAL_SUS,
> +
> + MINNOW2_GPIO_IO_SEL_VAL_0_31,
> + MINNOW2_GPIO_IO_SEL_VAL_32_63,
> + MINNOW2_GPIO_IO_SEL_VAL_64_70,
> + MINNOW2_GPIO_IO_SEL_VAL_SUS,
> +
> + MINNOW2_GPIO_LVL_VAL_0_31,
> + MINNOW2_GPIO_LVL_VAL_32_63,
> + MINNOW2_GPIO_LVL_VAL_64_70,
> + MINNOW2_GPIO_LVL_VAL_SUS,
> +
> + MINNOW2_GPIO_TPE_VAL_0_31,
> + MINNOW2_GPIO_TPE_VAL_SUS,
> + MINNOW2_GPIO_TNE_VAL_0_31,
> + MINNOW2_GPIO_TNE_VAL_SUS,
> +
> + MINNOW2_GPIO_TS_VAL_0_31,
> + MINNOW2_GPIO_TS_VAL_SUS
> +};
> +
> +static CFIO_INIT_STRUCT mMinnow2CfioInitData2 =
> +{
> + MINNOW2_GPIO_USE_SEL_VAL_0_31,
> + MINNOW2_GPIO_USE_SEL_VAL_32_63,
> + MINNOW2_GPIO_USE_SEL_VAL_64_70,
> + MINNOW2_GPIO_USE_SEL_VAL_SUS2,
> +
> + MINNOW2_GPIO_IO_SEL_VAL_0_31,
> + MINNOW2_GPIO_IO_SEL_VAL_32_63,
> + MINNOW2_GPIO_IO_SEL_VAL_64_70,
> + MINNOW2_GPIO_IO_SEL_VAL_SUS2,
> +
> + MINNOW2_GPIO_LVL_VAL_0_31,
> + MINNOW2_GPIO_LVL_VAL_32_63,
> + MINNOW2_GPIO_LVL_VAL_64_70,
> + MINNOW2_GPIO_LVL_VAL_SUS2,
> +
> + MINNOW2_GPIO_TPE_VAL_0_31,
> + MINNOW2_GPIO_TPE_VAL_SUS2,
> + MINNOW2_GPIO_TNE_VAL_0_31,
> + MINNOW2_GPIO_TNE_VAL_SUS2,
> +
> + MINNOW2_GPIO_TS_VAL_0_31,
> + MINNOW2_GPIO_TS_VAL_SUS2
> +};
> +
> +static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_NC[] =
> +{
> +// Pad Name GPIO Number Used As GPO Default Function#
> INT Capable Interrupt Type PULL H/L MMIO Offset
> +GPIO_INIT_ITEM("HV_DDI0_HPD GPIONC_0
> " ,Native ,NA ,F2 , , ,NONE ,0x13),
> +GPIO_INIT_ITEM("HV_DDI0_DDC_SDA GPIONC_1
> " ,Native ,NA ,F2 , , ,NONE ,0x12),
> +GPIO_INIT_ITEM("HV_DDI0_DDC_SCL GPIONC_2
> " ,Native ,NA ,F2 , , ,NONE ,0x11),
> +GPIO_INIT_ITEM("PANEL0_VDDEN GPIONC_3
> " ,GPIO ,NA ,F0 , , ,NONE ,0x14),
> +GPIO_INIT_ITEM("PANEL0_BKLTEN GPIONC_4
> " ,GPIO ,NA ,F0 , , ,NONE ,0x15),
> +GPIO_INIT_ITEM("PANEL0_BKLTCTL GPIONC_5
> " ,GPIO ,NA ,F0 , , ,NONE ,0x16),
> +GPIO_INIT_ITEM("HV_DDI1_HPD GPIONC_6
> " ,Native ,NA ,F2 , , ,NONE ,0x18),
> +GPIO_INIT_ITEM("HV_DDI1_DDC_SDA GPIONC_7
> " ,Native ,NA ,F2 , , ,NONE ,0x19),
> +GPIO_INIT_ITEM("HV_DDI1_DDC_SCL GPIONC_8
> " ,Native ,NA ,F2 , , ,NONE ,0x17),
> +GPIO_INIT_ITEM("PANEL1_VDDEN GPIONC_9
> " ,GPIO ,NA ,F0 , , ,NONE ,0x10),
> +GPIO_INIT_ITEM("PANEL1_BKLTEN
> GPIONC_10" ,GPIO ,NA ,F0 , , ,NONE ,0x0e),
> +GPIO_INIT_ITEM("PANEL1_BKLTCTL
> GPIONC_11" ,GPIO ,NA ,F0 , , ,NONE ,0x0f),
> +GPIO_INIT_ITEM("GP_INTD_DSI_TE1
> GPIONC_12" ,GPO ,NA ,F0 , , ,NONE ,0x0c),
> +GPIO_INIT_ITEM("HV_DDI2_DDC_SDA
> GPIONC_13" ,GPI ,NA ,F0 , , ,10K_L ,0x1a),
> +GPIO_INIT_ITEM("HV_DDI2_DDC_SCL
> GPIONC_14" ,GPIO ,NA ,F0 , , ,NONE ,0x1b),
> +GPIO_INIT_ITEM("GP_CAMERASB00
> GPIONC_15" ,GPIO ,NA ,F0 , , ,NONE ,0x01),
> +GPIO_INIT_ITEM("GP_CAMERASB01
> GPIONC_16" ,GPIO ,NA ,F0 , , ,NONE ,0x04),
> +GPIO_INIT_ITEM("GP_CAMERASB02
> GPIONC_17" ,GPIO ,NA ,F0 , , ,NONE ,0x08),
> +GPIO_INIT_ITEM("GP_CAMERASB03
> GPIONC_18" ,GPIO ,NA ,F0 , , ,NONE ,0x0b),
> +GPIO_INIT_ITEM("GP_CAMERASB04
> GPIONC_19" ,GPIO ,NA ,F0 , , ,NONE ,0x00),
> +GPIO_INIT_ITEM("GP_CAMERASB05
> GPIONC_20" ,GPIO ,NA ,F0 , , ,NONE ,0x03),
> +GPIO_INIT_ITEM("GP_CAMERASB06
> GPIONC_21" ,GPIO ,NA ,F0 , , ,NONE ,0x06),
> +GPIO_INIT_ITEM("GP_CAMERASB07
> GPIONC_22" ,GPIO ,NA ,F0 , , ,NONE ,0x0a),
> +GPIO_INIT_ITEM("GP_CAMERASB08
> GPIONC_23" ,GPIO ,NA ,F0 , , ,NONE ,0x0d),
> +GPIO_INIT_ITEM("GP_CAMERASB09
> GPIONC_24" ,GPIO ,NA ,F0 , , ,NONE ,0x02),
> +GPIO_INIT_ITEM("GP_CAMERASB10
> GPIONC_25" ,GPIO ,NA ,F0 , , ,NONE ,0x05),
> +GPIO_INIT_ITEM("GP_CAMERASB11
> GPIONC_26" ,GPIO ,NA ,F0 , , ,NONE ,0x09),
> +};
> +
> +
> +static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_SC[] = {
> +// Pad Name GPIO Number Used As GPO Default Function#
> INT Capable Interrupt Type PULL H/L MMIO Offset
> +GPIO_INIT_ITEM("SATA_GP0 GPIOC_0
> " ,Native ,NA ,F1 , , ,NONE ,0x55),
> +GPIO_INIT_ITEM("SATA_GP1 GPIOC_1
> " ,Native ,NA ,F1 , , ,NONE ,0x59),
> +GPIO_INIT_ITEM("SATA_LEDN GPIOC_2
> " ,Native ,NA ,F1 , , ,NONE ,0x5d),
> +GPIO_INIT_ITEM("PCIE_CLKREQ0B GPIOC_3
> " ,Native ,NA ,F1 , , ,10K_H ,0x60),
> +GPIO_INIT_ITEM("PCIE_CLKREQ1B GPIOC_4
> " ,Native ,NA ,F1 , , ,10K_H ,0x63),
> +GPIO_INIT_ITEM("PCIE_CLKREQ2B GPIOC_5
> " ,Native ,NA ,F1 , , ,10K_H ,0x66),
> +GPIO_INIT_ITEM("PCIE_CLKREQ3B GPIOC_6
> " ,GPIO ,NA ,F0 , , ,NONE ,0x62),
> +GPIO_INIT_ITEM("SDMMC3_WP GPIOC_7
> " ,Native ,NA ,F2 , , ,NONE ,0x65),
> +GPIO_INIT_ITEM("HDA_RSTB GPIOC_8
> " ,GPIO ,NA ,F0 , , ,NONE ,0x22),
> +GPIO_INIT_ITEM("HDA_SYNC GPIOC_9
> " ,GPIO ,NA ,F0 , , ,NONE ,0x25),
> +GPIO_INIT_ITEM("HDA_CLK GPIOC_10
> " ,GPIO ,NA ,F0 , , ,NONE ,0x24),
> +GPIO_INIT_ITEM("HDA_SDO GPIOC_11
> " ,GPIO ,NA ,F0 , , ,NONE ,0x26),
> +GPIO_INIT_ITEM("HDA_SDI0 GPIOC_12
> " ,GPIO ,NA ,F0 , , ,NONE ,0x27),
> +GPIO_INIT_ITEM("HDA_SDI1 GPIOC_13
> " ,GPIO ,NA ,F0 , , ,NONE ,0x23),
> +GPIO_INIT_ITEM("HDA_DOCKRSTB GPIOC_14
> " ,GPIO ,NA ,F0 , , ,NONE ,0x28),
> +GPIO_INIT_ITEM("HDA_DOCKENB GPIOC_15
> " ,GPIO ,NA ,F0 , , ,NONE ,0x54),
> +GPIO_INIT_ITEM("SDMMC1_CLK GPIOC_16
> " ,GPIO ,NA ,F0 , , ,NONE ,0x3e),
> +GPIO_INIT_ITEM("SDMMC1_D0 GPIOC_17
> " ,GPIO ,NA ,F0 , , ,NONE ,0x3d),
> +GPIO_INIT_ITEM("SDMMC1_D1 GPIOC_18
> " ,GPIO ,NA ,F0 , , ,NONE ,0x40),
> +GPIO_INIT_ITEM("SDMMC1_D2 GPIOC_19
> " ,GPIO ,NA ,F0 , , ,NONE ,0x3b),
> +GPIO_INIT_ITEM("SDMMC1_D3_CD_B GPIOC_20
> " ,GPIO ,NA ,F0 , , ,NONE ,0x36),
> +GPIO_INIT_ITEM("MMC1_D4_SD_WE GPIOC_21
> " ,GPIO ,NA ,F0 , , ,NONE ,0x38),
> +GPIO_INIT_ITEM("MMC1_D5 GPIOC_22
> " ,GPIO ,NA ,F0 , , ,NONE ,0x3c),
> +GPIO_INIT_ITEM("MMC1_D6 GPIOC_23
> " ,GPIO ,NA ,F0 , , ,NONE ,0x37),
> +GPIO_INIT_ITEM("MMC1_D7 GPIOC_24
> " ,GPIO ,NA ,F0 , , ,NONE ,0x3f),
> +GPIO_INIT_ITEM("SDMMC1_CMD GPIOC_25
> " ,GPIO ,NA ,F0 , , ,NONE ,0x39),
> +GPIO_INIT_ITEM("MMC1_RESET_B GPIOC_26
> " ,GPIO ,NA ,F0 , , ,NONE ,0x33),
> +GPIO_INIT_ITEM("SDMMC2_CLK GPIOC_27
> " ,GPIO ,NA ,F0 , , ,NONE ,0x32),
> +GPIO_INIT_ITEM("SDMMC2_D0 GPIOC_28
> " ,GPIO ,NA ,F0 , , ,NONE ,0x35),
> +GPIO_INIT_ITEM("SDMMC2_D1 GPIOC_29
> " ,GPIO ,NA ,F0 , , ,NONE ,0x2f),
> +GPIO_INIT_ITEM("SDMMC2_D2 GPIOC_30
> " ,GPIO ,NA ,F0 , , ,NONE ,0x34),
> +GPIO_INIT_ITEM("SDMMC2_D3_CD_B GPIOC_31
> " ,GPIO ,NA ,F0 , , ,NONE ,0x31),
> +GPIO_INIT_ITEM("SDMMC2_CMD GPIOC_32
> " ,GPIO ,NA ,F0 , , ,NONE ,0x30),
> +//
> +//Just for test, We make the setting that all is same with Bayleybay.
> +//
> +GPIO_INIT_ITEM("SDMMC3_CLK GPIOC_33
> " ,Native ,NA ,F1 , , ,NONE ,0x2b),
> +GPIO_INIT_ITEM("SDMMC3_D0 GPIOC_34
> " ,Native ,NA ,F1 , , ,NONE ,0x2e),
> +GPIO_INIT_ITEM("SDMMC3_D1 GPIOC_35
> " ,Native ,NA ,F1 ,YES , ,NONE ,0x29),
> +GPIO_INIT_ITEM("SDMMC3_D2 GPIOC_36
> " ,Native ,NA ,F1 , , ,NONE ,0x2d),
> +GPIO_INIT_ITEM("SDMMC3_D3 GPIOC_37
> " ,Native ,NA ,F1 , , ,NONE ,0x2a),
> +GPIO_INIT_ITEM("SDMMC3_CD_B GPIOC_38
> " ,Native ,NA ,F1 ,YES ,Edge_Both ,NONE ,0x3a),
> +GPIO_INIT_ITEM("SDMMC3_CMD GPIOC_39
> " ,Native ,NA ,F1 , , ,NONE ,0x2c),
> +GPIO_INIT_ITEM("SDMMC3_1P8_EN GPIOC_40
> " ,Native ,NA ,F1 , , ,NONE ,0x5f),
> +GPIO_INIT_ITEM("SDMMC3_PWR_EN_B GPIOC_41
> " ,Native ,NA ,F1 , , ,NONE ,0x69),
> +GPIO_INIT_ITEM("LPC_AD0 GPIOC_42
> " ,GPIO ,NA ,F0 , , ,NONE ,0x46),
> +GPIO_INIT_ITEM("LPC_AD1 GPIOC_43
> " ,GPIO ,NA ,F0 , , ,NONE ,0x44),
> +GPIO_INIT_ITEM("LPC_AD2 GPIOC_44
> " ,GPIO ,NA ,F0 , , ,NONE ,0x43),
> +GPIO_INIT_ITEM("LPC_AD3 GPIOC_45
> " ,GPIO ,NA ,F0 , , ,NONE ,0x42),
> +GPIO_INIT_ITEM("LPC_FRAMEB GPIOC_46
> " ,GPIO ,NA ,F0 , , ,NONE ,0x45),
> +GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47
> " ,GPIO ,NA ,F0 , , ,NONE ,0x47),
> +GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48
> " ,GPIO ,NA ,F0 , , ,NONE ,0x41),
> +GPIO_INIT_ITEM("LPC_CLKRUNB GPIOC_49
> " ,GPIO ,NA ,F0 , , ,NONE ,0x48),
> +GPIO_INIT_ITEM("ILB_SERIRQ GPIOC_50
> " ,GPIO ,NA ,F0 , , ,NONE ,0x56),
> +GPIO_INIT_ITEM("SMB_DATA GPIOC_51
> " ,Native ,NA ,F1 , , ,NONE ,0x5a),
> +GPIO_INIT_ITEM("SMB_CLK GPIOC_52
> " ,Native ,NA ,F1 , , ,NONE ,0x58),
> +GPIO_INIT_ITEM("SMB_ALERTB GPIOC_53
> " ,Native ,NA ,F1 , , ,10K_H ,0x5c),
> +GPIO_INIT_ITEM("SPKR GPIOC_54
> " ,GPI ,NA ,F0 , , ,20K_H ,0x67),
> +GPIO_INIT_ITEM("MHSI_ACDATA GPIOC_55
> " ,GPIO ,NA ,F0 , , ,NONE ,0x4d),
> +GPIO_INIT_ITEM("MHSI_ACFLAG GPIOC_56
> " ,GPI ,NA ,F0 , , ,20K_H ,0x4f),
> +GPIO_INIT_ITEM("MHSI_ACWAKE GPIOC_58
> " ,GPIO ,NA ,F0 , , ,NONE ,0x4e),
> +GPIO_INIT_ITEM("MHSI_CADATA GPIOC_59
> " ,GPIO ,NA ,F0 , , ,NONE ,0x51),
> +GPIO_INIT_ITEM("MHSI_CAFLAG GPIOC_60
> " ,GPO ,HI ,F0 , , ,20K_H ,0x50),
> +GPIO_INIT_ITEM("GP_SSP_2_CLK GPIOC_62
> " ,GPI ,NA ,F0 , , ,20K_H ,0x0d),
> +GPIO_INIT_ITEM("GP_SSP_2_FS GPIOC_63
> " ,GPI ,NA ,F0 , , ,20K_H ,0x0c),
> +GPIO_INIT_ITEM("GP_SSP_2_RXD GPIOC_64
> " ,GPI ,NA ,F0 , , ,20K_H ,0x0f),
> +GPIO_INIT_ITEM("GP_SSP_2_TXD GPIOC_65
> " ,GPI ,NA ,F0 , , ,20K_H ,0x0e),
> +GPIO_INIT_ITEM("SPI1_CS0_B GPIOC_66
> " ,Native ,NA ,F1 , , ,20K_H ,0x11),
> +GPIO_INIT_ITEM("SPI1_MISO GPIOC_67
> " ,Native ,NA ,F1 , , ,20K_H ,0x12),
> +GPIO_INIT_ITEM("SPI1_MOSI GPIOC_68
> " ,Native ,NA ,F1 , , ,20K_H ,0x13),
> +GPIO_INIT_ITEM("SPI1_CLK GPIOC_69
> " ,Native ,NA ,F1 , , ,20K_H ,0x10),
> +GPIO_INIT_ITEM("UART1_RXD GPIOC_70
> " ,Native ,NA ,F1 , , ,20K_H ,0x02),
> +GPIO_INIT_ITEM("UART1_TXD GPIOC_71
> " ,Native ,NA ,F1 , , ,20K_H ,0x01),
> +GPIO_INIT_ITEM("UART1_RTS_B GPIOC_72
> " ,GPI ,NA ,F0 , , ,20K_H ,0x00),
> +GPIO_INIT_ITEM("UART1_CTS_B GPIOC_73
> " ,GPI ,NA ,F0 , , ,20K_H ,0x04),
> +GPIO_INIT_ITEM("UART2_RXD GPIOC_74
> " ,Native ,NA ,F1 , , ,20K_H ,0x06),
> +GPIO_INIT_ITEM("UART2_TXD GPIOC_75
> " ,Native ,NA ,F1 , , ,20K_H ,0x07),
> +GPIO_INIT_ITEM("UART2_RTS_B GPIOC_76
> " ,GPIO ,NA ,F0 , , ,NONE ,0x09),
> +GPIO_INIT_ITEM("UART2_CTS_B GPIOC_77
> " ,Native ,NA ,F1 , , ,20K_H ,0x08),
> +GPIO_INIT_ITEM("I2C0_SDA GPIOC_78
> " ,GPIO ,NA ,F0 , , ,NONE ,0x21),
> +GPIO_INIT_ITEM("I2C0_SCL GPIOC_79
> " ,GPIO ,NA ,F0 , , ,NONE ,0x20),
> +GPIO_INIT_ITEM("I2C1_SDA GPIOC_80
> " ,Native ,NA ,F1 , , ,NONE ,0x1f),
> +GPIO_INIT_ITEM("I2C1_SCL GPIOC_81
> " ,Native ,NA ,F1 , , ,NONE ,0x1e),
> +GPIO_INIT_ITEM("I2C2_SDA GPIOC_82
> " ,GPIO ,NA ,F0 , , ,NONE ,0x1d),
> +GPIO_INIT_ITEM("I2C2_SCL GPIOC_83
> " ,GPIO ,NA ,F0 , , ,NONE ,0x1b),
> +GPIO_INIT_ITEM("I2C3_SDA GPIOC_84
> " ,GPIO ,NA ,F0 , , ,NONE ,0x19),
> +GPIO_INIT_ITEM("I2C3_SCL GPIOC_85
> " ,GPIO ,NA ,F0 , , ,NONE ,0x1c),
> +GPIO_INIT_ITEM("I2C4_SDA GPIOC_86
> " ,Native ,NA ,F1 , , ,20K_H ,0x1a),
> +GPIO_INIT_ITEM("I2C4_SCL GPIOC_87
> " ,GPIO ,NA ,F0 , , ,NONE ,0x17),
> +GPIO_INIT_ITEM("I2C5_SDA GPIOC_88
> " ,Native ,NA ,F1 , , ,20K_H ,0x15),
> +GPIO_INIT_ITEM("I2C5_SCL GPIOC_89
> " ,Native ,NA ,F1 , , ,20K_H ,0x14),
> +GPIO_INIT_ITEM("I2C6_SDA GPIOC_90
> " ,Native ,NA ,F1 , , ,20K_H ,0x18),
> +GPIO_INIT_ITEM("I2C6_SCL GPIOC_91
> " ,Native ,NA ,F1 , , ,20K_H ,0x16),
> +GPIO_INIT_ITEM("I2C_NFC_SDA GPIOC_92
> " ,GPIO ,NA ,F1 , , ,NONE ,0x05),
> +GPIO_INIT_ITEM("I2C_NFC_SCL GPIOC_93
> " ,GPO ,LO ,F1 , , ,NONE ,0x03),
> +GPIO_INIT_ITEM("PWM0 GPIOC_94
> " ,Native ,NA ,F1 , , ,20K_L ,0x0a),
> +GPIO_INIT_ITEM("PWM1 GPIOC_95
> " ,Native ,NA ,F1 , , ,20K_L ,0x0b),
> +GPIO_INIT_ITEM("PLT_CLK0 GPIOC_96
> " ,GPIO ,NA ,F0 , , ,NONE ,0x6a),
> +GPIO_INIT_ITEM("PLT_CLK1 GPIOC_97
> " ,GPIO ,NA ,F0 , , ,NONE ,0x57),
> +GPIO_INIT_ITEM("PLT_CLK2 GPIOC_98
> " ,GPIO ,NA ,F0 , , ,NONE ,0x5b),
> +GPIO_INIT_ITEM("PLT_CLK3 GPIOC_99
> " ,GPIO ,NA ,F0 , , ,NONE ,0x68),
> +GPIO_INIT_ITEM("PLT_CLK4
> GPIOC_100" ,GPIO ,NA ,F0 , , ,NONE ,0x61),
> +GPIO_INIT_ITEM("PLT_CLK5
> GPIOC_101" ,GPIO ,NA ,F0 , , ,NONE ,0x64),
> +};
> +
> +static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_SUS[] = {
> +// Pad Name GPIO Number Used As GPIO Default Function#
> INT Capable Interrupt Type PULL H/L MMIO Offset
> +GPIO_INIT_ITEM("GPIO_SUS0
> GPIO_SUS0" ,GPI ,NA ,F0 , , ,20K_H ,0x1d),
> +GPIO_INIT_ITEM("GPIO_SUS1
> GPIO_SUS1" ,GPI ,NA ,F0 , , ,20K_H ,0x21),
> +GPIO_INIT_ITEM("GPIO_SUS2
> GPIO_SUS2" ,GPI ,NA ,F0 , , ,20K_H ,0x1e),
> +GPIO_INIT_ITEM("GPIO_SUS3
> GPIO_SUS3" ,Native ,NA ,F6 ,YES ,Level_Low ,2K_H ,0
> x1f),
> +GPIO_INIT_ITEM("GPIO_SUS4
> GPIO_SUS4" ,GPIO ,NA ,F0 , , ,NONE ,0x20),
> +GPIO_INIT_ITEM("GPIO_SUS5
> GPIO_SUS5" ,GPI ,NA ,F0 , , ,NONE ,0x22),
> +GPIO_INIT_ITEM("GPIO_SUS6
> GPIO_SUS6" ,GPI ,NA ,F0 , , ,NONE ,0x24),
> +GPIO_INIT_ITEM("GPIO_SUS7
> GPIO_SUS7" ,GPI ,NA ,F0 , , ,NONE ,0x23),
> +GPIO_INIT_ITEM("SEC_GPIO_SUS8
> GPIO_SUS8" ,GPO ,HI ,F0 , , ,20K_H ,0x26),
> +GPIO_INIT_ITEM("SEC_GPIO_SUS9
> GPIO_SUS9" ,GPO ,HI ,F0 , , ,20K_H ,0x25),
> +GPIO_INIT_ITEM("SEC_GPIO_SUS10
> GPIO_SUS10" ,GPO ,HI ,F0 , , ,NONE ,0x12),
> +GPIO_INIT_ITEM("SUSPWRDNACK GPIOS_11
> " ,Native ,NA ,F0 , , ,10K_H ,0x07),
> +GPIO_INIT_ITEM("PMU_SUSCLK GPIOS_12
> " ,Native ,NA ,F0 , , ,NONE ,0x0b),
> +GPIO_INIT_ITEM("PMU_SLP_S0IX_B GPIOS_13
> " ,Native ,NA ,F0 , , ,NONE ,0x14),
> +GPIO_INIT_ITEM("PMU_SLP_LAN_B GPIOS_14
> " ,GPO ,LO ,F1 , , ,10K_H ,0x11),
> +GPIO_INIT_ITEM("PMU_WAKE_B GPIOS_15
> " ,Native ,NA ,F0 , , ,20K_H ,0x01),
> +GPIO_INIT_ITEM("PMU_PWRBTN_B GPIOS_16
> " ,Native ,NA ,F0 , , ,20K_H ,0x08),
> +GPIO_INIT_ITEM("PMU_WAKE_LAN_B GPIOS_17
> " ,GPIO ,NA ,F1 , , ,NONE ,0x0a),
> +GPIO_INIT_ITEM("SUS_STAT_B GPIOS_18
> " ,GPO ,NA ,F1 , , ,NONE ,0x13),
> +GPIO_INIT_ITEM("USB_OC0_B GPIOS_19
> " ,Native ,NA ,F0 , , ,10K_H ,0x0c),
> +GPIO_INIT_ITEM("USB_OC1_B GPIOS_20
> " ,Native ,NA ,F0 , , ,10K_H ,0x00),
> +GPIO_INIT_ITEM("SPI_CS1_B GPIOS_21
> " ,Native ,NA ,F0 , , ,NONE ,0x02),
> +GPIO_INIT_ITEM("GPIO_DFX0 GPIOS_22
> " ,GPIO ,NA ,F0 , , ,NONE ,0x17),
> +GPIO_INIT_ITEM("GPIO_DFX1 GPIOS_23
> " ,GPIO ,NA ,F0 , , ,NONE ,0x27),
> +GPIO_INIT_ITEM("GPIO_DFX2 GPIOS_24
> " ,GPIO ,NA ,F0 , , ,NONE ,0x1c),
> +GPIO_INIT_ITEM("GPIO_DFX3 GPIOS_25
> " ,GPIO ,NA ,F0 , , ,NONE ,0x1b),
> +GPIO_INIT_ITEM("GPIO_DFX4 GPIOS_26
> " ,GPIO ,NA ,F0 , , ,NONE ,0x16),
> +GPIO_INIT_ITEM("GPIO_DFX5 GPIOS_27
> " ,GPI ,NA ,F0 , , ,20K_H ,0x15),
> +GPIO_INIT_ITEM("GPIO_DFX6 GPIOS_28
> " ,GPI ,NA ,F0 , , ,20K_H ,0x18),
> +GPIO_INIT_ITEM("GPIO_DFX7 GPIOS_29
> " ,GPI ,NA ,F0 , , ,20K_H ,0x19),
> +GPIO_INIT_ITEM("GPIO_DFX8 GPIOS_30
> " ,GPI ,NA ,F0 , , ,20K_H ,0x1a),
> +GPIO_INIT_ITEM("USB_ULPI_0_CLK GPIOS_31
> " ,GPIO ,NA ,F0 , , ,NONE ,0x33),
> +GPIO_INIT_ITEM("USB_ULPI_0_DATA0 GPIOS_32
> " ,GPIO ,NA ,F0 , , ,NONE ,0x38),
> +GPIO_INIT_ITEM("USB_ULPI_0_DATA1 GPIOS_33
> " ,GPIO ,NA ,F0 , , ,NONE ,0x36),
> +GPIO_INIT_ITEM("USB_ULPI_0_DATA2 GPIOS_34
> " ,GPIO ,NA ,F0 , , ,NONE ,0x31),
> +GPIO_INIT_ITEM("USB_ULPI_0_DATA3 GPIOS_35
> " ,GPIO ,NA ,F0 , , ,NONE ,0x37),
> +GPIO_INIT_ITEM("USB_ULPI_0_DATA4 GPIOS_36
> " ,GPIO ,NA ,F0 , , ,NONE ,0x30),
> +GPIO_INIT_ITEM("USB_ULPI_0_DATA5 GPIOS_37
> " ,GPIO ,NA ,F0 , , ,NONE ,0x39),
> +GPIO_INIT_ITEM("USB_ULPI_0_DATA6 GPIOS_38
> " ,GPIO ,NA ,F0 , , ,NONE ,0x32),
> +GPIO_INIT_ITEM("USB_ULPI_0_DATA7 GPIOS_39
> " ,GPIO ,NA ,F0 , , ,NONE ,0x3a),
> +GPIO_INIT_ITEM("USB_ULPI_0_DIR GPIOS_40
> " ,GPIO ,NA ,F0 , , ,NONE ,0x34),
> +GPIO_INIT_ITEM("USB_ULPI_0_NXT GPIOS_41
> " ,GPIO ,NA ,F0 , , ,NONE ,0x35),
> +GPIO_INIT_ITEM("USB_ULPI_0_STP GPIOS_42
> " ,GPIO ,NA ,F0 , , ,NONE ,0x3b),
> +GPIO_INIT_ITEM("USB_ULPI_0_REFCLK GPIOS_43
> " ,GPIO ,NA ,F0 , , ,NONE ,0x28),
> +};
> +
> +EFI_STATUS
> +MultiPlatformGpioTableInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + );
> +
> +EFI_STATUS
> +MultiPlatformGpioProgram (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers
> /BoardJumpers.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers
> /BoardJumpers.c
> new file mode 100644
> index 0000000000..67f5e24ede
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers
> /BoardJumpers.c
> @@ -0,0 +1,30 @@
> +/** @file
> + Jumper setting for multiplatform.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <BoardJumpers.h>
> +
> +BOOLEAN
> +IsRecoveryJumper (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> +)
> +{
> + return FALSE;
> +}
> +
> +BOOLEAN
> +IsManufacturingMode(
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> +)
> +{
> + return FALSE;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers
> /BoardJumpers.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers
> /BoardJumpers.h
> new file mode 100644
> index 0000000000..7c1fc88909
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers
> /BoardJumpers.h
> @@ -0,0 +1,30 @@
> +/**@file
> + Jumper setting for multiplatform.
> +
> + This file includes package header files, library classes.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +**/
> +
> +#ifndef _BOARDJUMPERS_H_
> +#define _BOARDJUMPERS_H_
> +
> +#include <PiPei.h>
> +#include "PchAccess.h"
> +#include "PlatformBaseAddresses.h"
> +
> +#include <Library/IoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Guid/PlatformInfo.h>
> +
> +BOOLEAN
> +IsRecoveryJumper (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> +);
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/
> BoardOemIds.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/
> BoardOemIds.c
> new file mode 100644
> index 0000000000..bb3f4c0a33
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/
> BoardOemIds.c
> @@ -0,0 +1,43 @@
> +/** @file
> + ACPI oem ids setting for multiplatform.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <BoardOemIds.h>
> +
> +//
> +// Global module data
> +//
> +EFI_STATUS
> +InitializeBoardOemId (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + )
> +{
> + UINT64 OemId;
> + UINT64 OemTableId;
> +
> + //
> + // Set OEM ID according to Board ID.
> + //
> + switch (PlatformInfoHob->BoardId) {
> +
> + case BOARD_ID_MINNOW2:
> + case BOARD_ID_MINNOW2_TURBOT:
> + default:
> + OemId = EFI_ACPI_OEM_ID_DEFAULT;
> + OemTableId = EFI_ACPI_OEM_TABLE_ID_DEFAULT;
> + break;
> + }
> +
> + PlatformInfoHob->AcpiOemId = OemId;
> + PlatformInfoHob->AcpiOemTableId = OemTableId;
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/
> BoardOemIds.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/
> BoardOemIds.h
> new file mode 100644
> index 0000000000..3598a21a61
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/
> BoardOemIds.h
> @@ -0,0 +1,29 @@
> +/**@file
> + ACPI oem ids setting for multiplatform.
> +
> + This file includes package header files, library classes.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +**/
> +
> +#include <Guid/PlatformInfo.h>
> +#include <Library/BaseMemoryLib.h>
> +
> +#define EFI_ACPI_OEM_ID_DEFAULT SIGNATURE_64('I', 'N', 'T', 'E', 'L', ' ', '
> ', ' ') // max 6 chars
> +#define EFI_ACPI_OEM_ID1 SIGNATURE_64('I', 'N', 'T', 'E', 'L', '1', ' ', ' ')
> // max 6 chars
> +#define EFI_ACPI_OEM_ID2 SIGNATURE_64('I', 'N', 'T', 'E', 'L', '2', ' ', ' ')
> // max 6 chars
> +
> +#define EFI_ACPI_OEM_TABLE_ID_DEFAULT SIGNATURE_64('E', 'D', 'K', '2',
> ' ', ' ', ' ', ' ')
> +#define EFI_ACPI_OEM_TABLE_ID1 SIGNATURE_64('E', 'D', 'K', '2', '_',
> '1', ' ', ' ')
> +#define EFI_ACPI_OEM_TABLE_ID2 SIGNATURE_64('E', 'D', 'K', '2', '_',
> '2', ' ', ' ')
> +
> +
> +EFI_STATUS
> +InitializeBoardOemId (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + );
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/
> BoardSsidSvid.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid
> /BoardSsidSvid.c
> new file mode 100644
> index 0000000000..77764945c3
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid
> /BoardSsidSvid.c
> @@ -0,0 +1,38 @@
> +/** @file
> + Subsystem IDs setting for multiplatform.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <BoardSsidSvid.h>
> +
> +//
> +// Global module data
> +//
> +EFI_STATUS
> +InitializeBoardSsidSvid (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + )
> +{
> + UINT32 SsidSvidValue = 0;
> +
> + //
> + // Set OEM ID according to Board ID.
> + //
> + switch (PlatformInfoHob->BoardId) {
> + case BOARD_ID_MINNOW2:
> + case BOARD_ID_MINNOW2_TURBOT:
> + default:
> + SsidSvidValue =
> SUBSYSTEM_SVID_SSID;//SUBSYSTEM_SVID_SSID_DEFAULT;
> + break;
> + }
> + PlatformInfoHob->SsidSvid = SsidSvidValue;
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/
> BoardSsidSvid.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid
> /BoardSsidSvid.h
> new file mode 100644
> index 0000000000..6a9995c34c
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid
> /BoardSsidSvid.h
> @@ -0,0 +1,35 @@
> +/**@file
> + Subsystem IDs setting for multiplatform.
> +
> + This file includes package header files, library classes.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +**/
> +
> +#include <Guid/PlatformInfo.h>
> +#include <Library/BaseMemoryLib.h>
> +
> +//
> +// Default Vendor ID and Subsystem ID
> +//
> +#define SUBSYSTEM_VENDOR_ID1 0x8086
> +#define SUBSYSTEM_DEVICE_ID1 0x1999
> +#define SUBSYSTEM_SVID_SSID1 (SUBSYSTEM_VENDOR_ID1 +
> (SUBSYSTEM_DEVICE_ID1 << 16))
> +
> +#define SUBSYSTEM_VENDOR_ID2 0x8086
> +#define SUBSYSTEM_DEVICE_ID2 0x1888
> +#define SUBSYSTEM_SVID_SSID2 (SUBSYSTEM_VENDOR_ID2 +
> (SUBSYSTEM_DEVICE_ID2 << 16))
> +
> +#define SUBSYSTEM_VENDOR_ID 0x8086
> +#define SUBSYSTEM_DEVICE_ID 0x1234
> +#define SUBSYSTEM_SVID_SSID (SUBSYSTEM_VENDOR_ID +
> (SUBSYSTEM_DEVICE_ID << 16))
> +
> +EFI_STATUS
> +InitializeBoardSsidSvid (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + );
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformL
> ib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatform
> Lib.c
> new file mode 100644
> index 0000000000..d24e90c7f4
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatform
> Lib.c
> @@ -0,0 +1,120 @@
> +/** @file
> + Multiplatform initialization.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <MultiPlatformLib.h>
> +
> +/**
> + Platform Type detection. Because the PEI globle variable
> + is in the flash, it could not change directly.So use
> + 2 PPIs to distinguish the platform type.
> +
> + @param FfsHeader Pointer to Firmware File System file header.
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval EFI_SUCCESS Memory initialization completed successfully.
> + @retval Others All other error conditions encountered result in an
> ASSERT.
> +
> +**/
> +EFI_STATUS
> +MultiPlatformInfoInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + )
> +{
> + UINT32 PcieLength;
> +
> +
> + PlatformInfoHob->IohSku = MmPci16(0, MC_BUS, MC_DEV, MC_FUN,
> PCI_DEVICE_ID_OFFSET);
> +
> + PlatformInfoHob->IohRevision = MmPci8(0, MC_BUS, MC_DEV, MC_FUN,
> PCI_REVISION_ID_OFFSET);
> +
> + //
> + // Update ICH Type
> + //
> + //
> + // Device ID
> + //
> + PlatformInfoHob->IchSku = PchLpcPciCfg16(PCI_DEVICE_ID_OFFSET);
> +
> + PlatformInfoHob->IchRevision = PchLpcPciCfg8(PCI_REVISION_ID_OFFSET);
> +
> + //
> + //64MB
> + //
> + PcieLength = 0x04000000;
> +
> + //
> + // Don't support BASE above 4GB currently.
> + //
> + PlatformInfoHob->PciData.PciExpressSize = PcieLength;
> + PlatformInfoHob->PciData.PciExpressBase = PcdGet64
> (PcdPciExpressBaseAddress);
> +
> + PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32)
> (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);
> + PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32)
> (PlatformInfoHob->PciData.PciExpressBase -1);
> +
> + PlatformInfoHob->PciData.PciResourceMem64Base =
> RES_MEM64_36_BASE;
> + PlatformInfoHob->PciData.PciResourceMem64Limit =
> RES_MEM64_36_LIMIT;
> + PlatformInfoHob->CpuData.CpuAddressWidth = 36;
> +
> + PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob-
> >PciData.PciResourceMem64Base;
> + PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob-
> >PciData.PciResourceMem64Limit + 1;
> +
> + PlatformInfoHob->PciData.PciResourceMinSecBus = 1; //can be changed
> by SystemConfiguration->PciMinSecondaryBus;
> +
> + //
> + // Set MemMaxTolm to the lowest address between PCIe Base and PCI32
> Base.
> + //
> + if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob-
> >PciData.PciResourceMem32Base ) {
> + PlatformInfoHob->MemData.MemMaxTolm = (UINT32)
> PlatformInfoHob->PciData.PciResourceMem32Base;
> + } else {
> + PlatformInfoHob->MemData.MemMaxTolm = (UINT32)
> PlatformInfoHob->PciData.PciExpressBase;
> + }
> + PlatformInfoHob->MemData.MemTolm = PlatformInfoHob-
> >MemData.MemMaxTolm;
> +
> + //
> + // Platform PCI MMIO Size in unit of 1MB.
> + //
> + PlatformInfoHob->MemData.MmioSize = 0x1000 -
> (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);
> +
> + //
> + // Enable ICH IOAPIC
> + //
> + PlatformInfoHob->SysData.SysIoApicEnable = ICH_IOAPIC;
> +
> + DEBUG ((EFI_D_ERROR, "PlatformFlavor is %x
> (%x=tablet,%x=mobile,%x=desktop)\n",
> + PlatformInfoHob->PlatformFlavor,
> + FlavorTablet,
> + FlavorMobile,
> + FlavorDesktop));
> +
> + //
> + // Get Platform Info and fill the Hob.
> + //
> + PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;
> +
> + //
> + // Get GPIO table
> + //
> + MultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);
> +
> + //
> + // Program GPIO
> + //
> + MultiPlatformGpioProgram (PeiServices, PlatformInfoHob);
> +
> + //
> + // Update OemId
> + //
> + InitializeBoardOemId (PeiServices, PlatformInfoHob);
> + InitializeBoardSsidSvid (PeiServices, PlatformInfoHob);
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformL
> ib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatform
> Lib.h
> new file mode 100644
> index 0000000000..807ca20acb
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatform
> Lib.h
> @@ -0,0 +1,89 @@
> +/**@file
> + Multiplatform initialization header file.
> +
> + This file includes package header files, library classes.
> +
> + Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +**/
> +
> +#ifndef _MULTIPLATFORM_LIB_H_
> +#define _MULTIPLATFORM_LIB_H_
> +
> +
> +#define LEN_64M 0x4000000
> +
> +//
> +// Default PCI32 resource size
> +//
> +#define RES_MEM32_MIN_LEN 0x38000000
> +
> +#define RES_IO_BASE 0x0D00
> +#define RES_IO_LIMIT 0xFFFF
> +
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <FrameworkPei.h>
> +
> +#include "PlatformBaseAddresses.h"
> +#include "PchAccess.h"
> +#include "SetupMode.h"
> +#include "PlatformBootMode.h"
> +#include "Platform.h"
> +
> +#include <Ppi/Stall.h>
> +#include <Guid/SetupVariable.h>
> +#include <Ppi/AtaController.h>
> +#include <Ppi/FindFv.h>
> +#include <Ppi/BootInRecoveryMode.h>
> +#include <Ppi/ReadOnlyVariable2.h>
> +#include <Ppi/Capsule.h>
> +#include <Guid/EfiVpdData.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/BaseLib.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Ppi/Speaker.h>
> +#include <Guid/FirmwareFileSystem.h>
> +#include <Guid/MemoryTypeInformation.h>
> +#include <Ppi/Cache.h>
> +#include <Ppi/Reset.h>
> +#include <Ppi/EndOfPeiPhase.h>
> +#include <Ppi/MemoryDiscovered.h>
> +#include <Guid/GlobalVariable.h>
> +#include <Ppi/RecoveryModule.h>
> +#include <Ppi/DeviceRecoveryModule.h>
> +#include <Guid/Capsule.h>
> +#include <Guid/RecoveryDevice.h>
> +#include <Ppi/MasterBootMode.h>
> +#include <Guid/PlatformInfo.h>
> +
> +#include <BoardOemIds/BoardOemIds.h>
> +#include <BoardSsidSvid/BoardSsidSvid.h>
> +
> +
> +EFI_STATUS
> +GetPlatformInfoHob (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
> + );
> +
> +EFI_STATUS
> +MultiPlatformGpioTableInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + );
> +
> +EFI_STATUS
> +MultiPlatformGpioProgram (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformL
> ib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatform
> Lib.inf
> new file mode 100644
> index 0000000000..758e47ca70
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatform
> Lib.inf
> @@ -0,0 +1,77 @@
> +#
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#
> +#
> +# Module Name:
> +#
> +# MultiPlatform.inf
> +#
> +# Abstract:
> +#
> +#
> +--*/
> +
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = MultiPlatformLib
> + FILE_GUID = AB83A52B-B44A-462c-B099-444CC0ED274D
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = MultiPlatformLib
> + PI_SPECIFICATION_VERSION = 0x0001000A
> +
> +[sources]
> + MultiPlatformLib.c
> + MultiPlatformLib.h
> + PlatformInfoHob.c
> +#GPIO
> + BoardGpios/BoardGpios.c
> + BoardGpios/BoardGpios.h
> +
> +#ClkGen
> + BoardClkGens/BoardClkGens.c
> + BoardClkGens/BoardClkGens.h
> +
> +#Jumper
> + BoardJumpers/BoardJumpers.c
> + BoardJumpers/BoardJumpers.h
> +
> +#OemId
> + BoardOemIds/BoardOemIds.c
> + BoardOemIds/BoardOemIds.h
> +
> +#SSIDSVID
> + BoardSsidSvid/BoardSsidSvid.c
> + BoardSsidSvid/BoardSsidSvid.h
> +[Guids]
> +
> + gEfiPlatformInfoGuid # ALWAYS_CONSUMED
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + Vlv2SocBinPkg/Vlv2SocBinPkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + HobLib
> + IoLib
> +# PeiKscLib
> +
> +[Ppis]
> + gEfiPeiReadOnlyVariable2PpiGuid
> +
> +[Pcd.common]
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> +
> +[Guids]
> + gEfiSetupVariableGuid
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/PlatformInfoH
> ob.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/PlatformInfoH
> ob.c
> new file mode 100644
> index 0000000000..efa3619a76
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/MultiPlatformLib/PlatformInfoH
> ob.c
> @@ -0,0 +1,54 @@
> +/** @file
> + Platform Hob access interface for multiplatform.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <MultiPlatformLib.h>
> +
> +/**
> + Returns the Platform Info of the platform from the HOB.
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param PlatformInfoHob Pointer to the PLATFORM_INFO_HOB Pointer
> +
> + @retval EFI_SUCCESS The function completed successfully.
> + @retval EFI_NOT_FOUND PlatformInfoHob data doesn't exist, use
> default instead.
> +
> +**/
> +EFI_STATUS
> +GetPlatformInfoHob (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
> + )
> +{
> + EFI_PEI_HOB_POINTERS GuidHob;
> +
> + //
> + // Find the PlatformInfo HOB
> + //
> + GuidHob.Raw = GetHobList ();
> + if (GuidHob.Raw == NULL) {
> + return EFI_NOT_FOUND;
> + }
> +
> + if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid,
> GuidHob.Raw)) != NULL) {
> + *PlatformInfoHob = GET_GUID_HOB_DATA (GuidHob.Guid);
> + }
> +
> + //
> + // PlatformInfo PEIM should provide this HOB data, if not ASSERT and
> return error.
> + //
> + ASSERT (*PlatformInfoHob != NULL);
> + if (!(*PlatformInfoHob)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.i
> nf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.i
> nf
> new file mode 100644
> index 0000000000..6b5cc2861c
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.i
> nf
> @@ -0,0 +1,50 @@
> +#
> +#
> +#/*++
> +#
> +# Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +# Module Name:
> +#
> +# PeiDxePchPlatformLib.inf
> +#
> +# Abstract:
> +#
> +# Component description file for PEI/DXE PCH Platform Lib
> +#
> +#--*/
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PchPlatformLib
> + FILE_GUID = 32F89CBC-305D-4bdd-8B2C-9C65592E66AC
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PchPlatformLib
> +
> +[sources.common]
> + PchPlatformLibrary.h
> + PchPlatformLibrary.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + PciLib
> + IoLib
> + DebugLib
> +
> +
> +[Pcd.common]
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> +
> +
> +[Protocols]
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibr
> ary.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibr
> ary.c
> new file mode 100644
> index 0000000000..c31fd754cb
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibr
> ary.c
> @@ -0,0 +1,131 @@
> +/**
> +
> +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> + @file
> + PchPlatformLib.c
> +
> + @brief
> + PCH Platform Lib implementation.
> +
> +**/
> +
> +#include "PchPlatformLibrary.h"
> +
> +//
> +// Silicon Steppings
> +//
> +/**
> + Return Pch stepping type
> +
> + @param[in] None
> +
> + @retval PCH_STEPPING Pch stepping type
> +
> +**/
> +PCH_STEPPING
> +EFIAPI
> +PchStepping (
> + VOID
> + )
> +{
> + UINT8 RevId;
> +
> + RevId = MmioRead8 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_RID_CC)
> + );
> +
> + switch (RevId) {
> + case V_PCH_LPC_RID_0:
> + case V_PCH_LPC_RID_1:
> + return PchA0;
> + break;
> +
> + case V_PCH_LPC_RID_2:
> + case V_PCH_LPC_RID_3:
> + return PchA1;
> + break;
> +
> + case V_PCH_LPC_RID_4:
> + case V_PCH_LPC_RID_5:
> + return PchB0;
> + break;
> +
> + case V_PCH_LPC_RID_6:
> + case V_PCH_LPC_RID_7:
> + return PchB1;
> + break;
> +
> + case V_PCH_LPC_RID_8:
> + case V_PCH_LPC_RID_9:
> + return PchB2;
> + break;
> +
> + case V_PCH_LPC_RID_A:
> + case V_PCH_LPC_RID_B:
> + return PchB3;
> + break;
> +
> + case V_PCH_LPC_RID_C:
> + case V_PCH_LPC_RID_D:
> + return PchC0;
> + break;
> +
> + case V_PCH_LPC_RID_E:
> + case V_PCH_LPC_RID_F:
> + return PchD0;
> + break;
> +
> + default:
> + return PchSteppingMax;
> + break;
> +
> + }
> +}
> +
> +/**
> + Determine if PCH is supported
> +
> + @param[in] None
> +
> + @retval TRUE PCH is supported
> + @retval FALSE PCH is not supported
> +
> +**/
> +BOOLEAN
> +IsPchSupported (
> + VOID
> + )
> +{
> + UINT32 Identifiers;
> + UINT16 PcuVendorId;
> + UINT16 PcuDeviceId;
> +
> + Identifiers = MmioRead32 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_REG_ID)
> + );
> +
> + PcuDeviceId = (UINT16) ((Identifiers & B_PCH_LPC_DEVICE_ID) >> 16);
> + PcuVendorId = (UINT16) (Identifiers & B_PCH_LPC_VENDOR_ID);
> +
> + //
> + // Verify that this is a supported chipset
> + //
> + if (PcuVendorId != (UINT16) V_PCH_LPC_VENDOR_ID
> || !IS_PCH_VLV_LPC_DEVICE_ID (PcuDeviceId)) {
> + DEBUG ((EFI_D_ERROR, "VLV SC code doesn't support the PcuDeviceId:
> 0x%04x!\n", PcuDeviceId));
> + return FALSE;
> + }
> + return TRUE;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibr
> ary.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibr
> ary.h
> new file mode 100644
> index 0000000000..da1f77f680
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibr
> ary.h
> @@ -0,0 +1,35 @@
> +/**
> +**/
> +/**
> +
> +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> + @file
> + PchPlatformLibrary.h
> +
> + @brief
> + Header file for PCH Platform Lib implementation.
> +
> +**/
> +
> +#ifndef _PCH_PLATFORM_LIBRARY_IMPLEMENTATION_H_
> +#define _PCH_PLATFORM_LIBRARY_IMPLEMENTATION_H_
> +
> +#include "PchAccess.h"
> +#ifdef ECP_FLAG
> +#include "EdkIIGlueBase.h"
> +#include "Library/EdkIIGlueMemoryAllocationLib.h"
> +#else
> +#include "Library/PciLib.h"
> +#include "Library/IoLib.h"
> +#include "Library/DebugLib.h"
> +#include "Library/PcdLib.h"
> +
> +#include "PchCommonDefinitions.h"
> +#endif
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PchSmmLib/CommonHeader.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchSmmLib/CommonHeader.h
> new file mode 100644
> index 0000000000..e0a1f3a0f7
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchSmmLib/CommonHeader.h
> @@ -0,0 +1,32 @@
> +/**@file
> + Common header file shared by all source files.
> +
> + This file includes package header files, library classes and protocol, PPI &
> GUID definitions.
> +
> + Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +**/
> +
> +#ifndef __COMMON_HEADER_H_
> +#define __COMMON_HEADER_H_
> +
> +
> +#include <Base.h>
> +
> +#include <Library/TimerLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +#define R_PCH_ACPI_SMI_EN 0x30
> +#define B_PCH_ACPI_APMC_EN 0x00000020
> +#define B_PCH_ACPI_EOS 0x00000002
> +#define B_PCH_ACPI_GBL_SMI_EN 0x00000001
> +#define R_PCH_ACPI_SMI_STS 0x34
> +#define B_PCH_ACPI_APM_STS 0x00000020
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.c
> new file mode 100644
> index 0000000000..2b0aacaccf
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.c
> @@ -0,0 +1,157 @@
> +/** @file
> + PCH Smm Library Services that implements both S/W SMI generation and
> detection.
> +
> + Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +
> +/**
> + Triggers a run time or boot time SMI.
> +
> + This function triggers a software SMM interrupt and set the APMC status
> with an 8-bit Data.
> +
> + @param Data The value to set the APMC status.
> +
> +**/
> +VOID
> +InternalTriggerSmi (
> + IN UINT8 Data
> + )
> +{
> + ASSERT(FALSE);
> +}
> +
> +
> +/**
> + Triggers an SMI at boot time.
> +
> + This function triggers a software SMM interrupt at boot time.
> +
> +**/
> +VOID
> +EFIAPI
> +TriggerBootServiceSoftwareSmi (
> + VOID
> + )
> +{
> + ASSERT(FALSE);
> +}
> +
> +
> +/**
> + Triggers an SMI at run time.
> +
> + This function triggers a software SMM interrupt at run time.
> +
> +**/
> +VOID
> +EFIAPI
> +TriggerRuntimeSoftwareSmi (
> + VOID
> + )
> +{
> + ASSERT(FALSE);
> +}
> +
> +
> +/**
> + Gets the software SMI data.
> +
> + This function tests if a software SMM interrupt happens. If a software SMI
> happens,
> + it retrieves the SMM data and returns it as a non-negative value;
> otherwise a negative
> + value is returned.
> +
> + @return Data The data retrieved from SMM data port in case of a
> software SMI;
> + otherwise a negative value.
> +
> +**/
> +INTN
> +InternalGetSwSmiData (
> + VOID
> + )
> +{
> + ASSERT(FALSE);
> + return -1;
> +}
> +
> +
> +/**
> + Test if a boot time software SMI happened.
> +
> + This function tests if a software SMM interrupt happened. If a software
> SMM interrupt happened and
> + it was triggered at boot time, it returns TRUE. Otherwise, it returns FALSE.
> +
> + @retval TRUE A software SMI triggered at boot time happened.
> + @retval FLASE No software SMI happened or the software SMI was
> triggered at run time.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +IsBootServiceSoftwareSmi (
> + VOID
> + )
> +{
> + ASSERT(FALSE);
> + return FALSE;
> +}
> +
> +
> +/**
> + Test if a run time software SMI happened.
> +
> + This function tests if a software SMM interrupt happened. If a software
> SMM interrupt happened and
> + it was triggered at run time, it returns TRUE. Otherwise, it returns FALSE.
> +
> + @retval TRUE A software SMI triggered at run time happened.
> + @retval FLASE No software SMI happened or the software SMI was
> triggered at boot time.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +IsRuntimeSoftwareSmi (
> + VOID
> + )
> +{
> + ASSERT(FALSE);
> + return FALSE;
> +}
> +
> +
> +/**
> +
> + Clear APM SMI Status Bit; Set the EOS bit.
> +
> +**/
> +VOID
> +EFIAPI
> +ClearSmi (
> + VOID
> + )
> +{
> +
> + UINT16 PmBase;
> +
> + //
> + // Get PMBase
> + //
> + PmBase = PcdGet16 (PcdPchAcpiIoPortBaseAddress);
> +
> + //
> + // Clear the APM SMI Status Bit
> + //
> + IoWrite16 (PmBase + R_PCH_ACPI_SMI_STS, B_PCH_ACPI_APM_STS);
> +
> + //
> + // Set the EOS Bit
> + //
> + IoOr32 (PmBase + R_PCH_ACPI_SMI_EN, B_PCH_ACPI_EOS);
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.inf
> new file mode 100644
> index 0000000000..9d4823d488
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.inf
> @@ -0,0 +1,46 @@
> +## @file
> +# Component description file for Intel Ich7 SMM Library.
> +#
> +# ICH SMM Library that layers on top of the I/O Library to directly
> +# access SMM power management registers.
> +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PchSmmLib
> + FILE_GUID = A6A16CCB-91B0-42f4-B4F3-D17D7A5662E6
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SmmLib
> +
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + PchSmmLib.c
> +
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + PcdLib
> + IoLib
> +
> +[Pcd]
> + gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
> new file mode 100644
> index 0000000000..4d5997d6e9
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
> @@ -0,0 +1,3098 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +Module Name:
> +
> + BdsPlatform.c
> +
> +Abstract:
> +
> + This file include all platform action which can be customized
> + by IBV/OEM.
> +
> +--*/
> +
> +#include "BdsPlatform.h"
> +#include "SetupMode.h"
> +#include <Guid/SetupVariable.h>
> +#include <Library/TcgPhysicalPresenceLib.h>
> +#include <Library/Tcg2PhysicalPresenceLib.h>
> +#include <Protocol/I2cMasterMcg.h>
> +#include <TianoApi.h>
> +#include <PlatformBaseAddresses.h>
> +#include <Protocol/GlobalNvsArea.h>
> +#include <Library/DxeServicesTableLib.h>
> +#include <Protocol/BlockIo.h>
> +#include <PchRegs/PchRegsPcu.h>
> +#include <Library/S3BootScriptLib.h>
> +#include "PchAccess.h"
> +#include "PchRegs/PchRegsSata.h"
> +#include <Library/SerialPortLib.h>
> +#include <Library/DebugLib.h>
> +
> +#include <Library/GenericBdsLib/InternalBdsLib.h>
> +#include <Library/GenericBdsLib/String.h>
> +#include <Library/NetLib.h>
> +
> +#include <Library/CapsuleLib.h>
> +#include <Protocol/EsrtManagement.h>
> +
> +EFI_GUID *ConnectDriverTable[] = {
> + &gEfiMmioDeviceProtocolGuid,
> + &gEfiI2cMasterProtocolGuid,
> + &gEfiI2cHostProtocolGuid
> +};
> +
> +#define SHELL_ENVIRONMENT_INTERFACE_PROTOCOL \
> + { \
> + 0x47c7b221, 0xc42a, 0x11d2, 0x8e, 0x57, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b
> \
> + }
> +VOID *mShellImageCallbackReg = NULL;
> +
> +
> +
> +EFI_USER_PROFILE_HANDLE mCurrentUser = NULL;
> +EFI_EVENT mHotKeyTimerEvent = NULL;
> +EFI_EVENT mHitHotkeyEvent = NULL;
> +EFI_EVENT mUsbKeyboardConnectEvent = NULL;
> +BOOLEAN mHotKeyPressed = FALSE;
> +VOID *mHitHotkeyRegistration;
> +#define KEYBOARD_TIMER_INTERVAL 20000 // 0.02s
> +
> +VOID
> +ConnectUSBController (
> + VOID
> + );
> +
> +EFI_STATUS
> +PlatformBdsConnectSimpleConsole (
> + IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole
> +);
> +
> +VOID
> +BootIntoFirmwareInterface(
> + VOID
> + );
> +
> +VOID
> +EFIAPI
> +PlatformBdsInitHotKeyEvent (
> + VOID
> + );
> +
> +VOID
> +EFIAPI
> +DisableAhciCtlr (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + UINT32 PmcDisableAddress;
> + UINT8 SataStorageAmount;
> + UINT32 SataBase;
> + UINT16 SataPortStatus;
> +
> +
> + DEBUG ((EFI_D_INFO, "Disable AHCI event is signalled\n"));
> + SataStorageAmount = 0;
> + SataBase = *(UINT32*) Context;
> +
> + //
> + // BayTrail-M EDS chapter 16 ---- PCI IO Register Offset 92 (SATA Port
> Control and Status)
> + //
> + SataPortStatus = MmioRead16 (SataBase + R_PCH_SATA_PCS);
> +
> + //
> + // Bit 8 EN: Port 0 Present
> + //
> + if ((SataPortStatus & 0x100) == 0x100) {
> + SataStorageAmount++;
> + }
> +
> + //
> + // Bit 9 EN: Port 1 Present
> + //
> + if ((SataPortStatus & 0x200) == 0x200) {
> + SataStorageAmount++;
> + }
> +
> + //
> + // Disable SATA controller when it sets to AHCI mode without carrying any
> devices
> + // in order to prevent AHCI yellow bang under Win device manager.
> + //
> + if (SataStorageAmount == 0) {
> + PmcDisableAddress = (MmioRead32 ((PCH_PCI_EXPRESS_BASE_ADDRESS
> + (UINT32) (31 << 15)) + R_PCH_LPC_PMC_BASE) &
> B_PCH_LPC_PMC_BASE_BAR) + R_PCH_PMC_FUNC_DIS;
> + MmioOr32 (PmcDisableAddress, B_PCH_PMC_FUNC_DIS_SATA);
> + S3BootScriptSaveMemWrite (
> + EfiBootScriptWidthUint32,
> + (UINTN) PmcDisableAddress,
> + 1,
> + (VOID *) (UINTN) PmcDisableAddress
> + );
> + }
> +}
> +
> +VOID
> +InstallReadyToLock (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE Handle;
> + EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
> + EFI_ACPI_S3_SAVE_PROTOCOL *AcpiS3Save;
> +
> + //
> + // Install DxeSmmReadyToLock protocol prior to the processing of boot
> options
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiSmmAccess2ProtocolGuid,
> + NULL,
> + (VOID **) &SmmAccess
> + );
> + if (!EFI_ERROR (Status)) {
> +
> + //
> + // Prepare S3 information, this MUST be done before
> DxeSmmReadyToLock
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiAcpiS3SaveProtocolGuid,
> + NULL,
> + (VOID **)&AcpiS3Save
> + );
> + if (!EFI_ERROR (Status)) {
> + AcpiS3Save->S3Save (AcpiS3Save, NULL);
> + }
> +
> + Handle = NULL;
> + Status = gBS->InstallProtocolInterface (
> + &Handle,
> + &gExitPmAuthProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Signal EndOfDxe PI Event
> + //
> + EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);
> +
> + Handle = NULL;
> + Status = gBS->InstallProtocolInterface (
> + &Handle,
> + &gEfiDxeSmmReadyToLockProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + return ;
> +}
> +
> +VOID
> +EFIAPI
> +ShellImageCallback (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + BdsSetConsoleMode (TRUE);
> + DEBUG ((EFI_D_INFO, "BdsEntry ShellImageCallback \n"));
> +}
> +
> +//
> +// BDS Platform Functions
> +//
> +/**
> + Platform Bds init. Include the platform firmware vendor, revision
> + and so crc check.
> +
> + @param VOID
> +
> + @retval None.
> +
> +**/
> +VOID
> +EFIAPI
> +PlatformBdsInit (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + EFI_EVENT ShellImageEvent;
> + EFI_GUID ShellEnvProtocol =
> SHELL_ENVIRONMENT_INTERFACE_PROTOCOL;
> +
> + #ifdef __GNUC__
> + SerialPortWrite((UINT8 *)">>>>BdsEntry[GCC]\r\n", 19);
> + #else
> + SerialPortWrite((UINT8 *)">>>>BdsEntry\r\n", 14);
> + #endif
> + BdsLibSaveMemoryTypeInformation ();
> +
> + //
> + // Before user authentication, the user identification devices need be
> connected
> + // from the platform customized device paths
> + //
> + PlatformBdsConnectAuthDevice ();
> +
> + //
> + // As console is not ready, the auto logon user will be identified.
> + //
> + BdsLibUserIdentify (&mCurrentUser);
> +
> + //
> + // Change Gop mode when boot into Shell
> + //
> + if (mShellImageCallbackReg == NULL) {
> + Status = gBS->CreateEvent (
> + EFI_EVENT_NOTIFY_SIGNAL,
> + EFI_TPL_CALLBACK,
> + ShellImageCallback,
> + NULL,
> + &ShellImageEvent
> + );
> + if (!EFI_ERROR (Status)) {
> + Status = gBS->RegisterProtocolNotify (
> + &ShellEnvProtocol,
> + ShellImageEvent,
> + &mShellImageCallbackReg
> + );
> +
> + DEBUG ((EFI_D_INFO, "BdsEntry ShellImageCallback \n"));
> + }
> + }
> +}
> +
> +EFI_STATUS
> +GetGopDevicePath (
> + IN EFI_DEVICE_PATH_PROTOCOL *PciDevicePath,
> + OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath
> + )
> +{
> + UINTN Index;
> + EFI_STATUS Status;
> + EFI_HANDLE PciDeviceHandle;
> + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *TempPciDevicePath;
> + UINTN GopHandleCount;
> + EFI_HANDLE *GopHandleBuffer;
> +
> + UINTN VarSize;
> + SYSTEM_CONFIGURATION mSystemConfiguration;
> +
> + if (PciDevicePath == NULL || GopDevicePath == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Initialize the GopDevicePath to be PciDevicePath
> + //
> + *GopDevicePath = PciDevicePath;
> + TempPciDevicePath = PciDevicePath;
> +
> + Status = gBS->LocateDevicePath (
> + &gEfiDevicePathProtocolGuid,
> + &TempPciDevicePath,
> + &PciDeviceHandle
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Try to connect this handle, so that GOP driver could start on this
> + // device and create child handles with GraphicsOutput Protocol installed
> + // on them, then we get device paths of these child handles and select
> + // them as possible console device.
> + //
> +
> + //
> + // Select display devices
> + //
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"Setup",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + if(mSystemConfiguration.BootDisplayDevice != 0x0)
> + {
> + ACPI_ADR_DEVICE_PATH AcpiAdr;
> + EFI_DEVICE_PATH_PROTOCOL *MyDevicePath = NULL;
> +
> + AcpiAdr.Header.Type = ACPI_DEVICE_PATH;
> + AcpiAdr.Header.SubType = ACPI_ADR_DP;
> +
> + switch (mSystemConfiguration.BootDisplayDevice) {
> + case 1:
> + AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0,
> ACPI_ADR_DISPLAY_TYPE_VGA, PORT_CRT, 0); //CRT Device
> + break;
> + case 2:
> + AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0,
> ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL, PORT_B_HDMI, 0); //HDMI
> Device Port B
> + break;
> + case 3:
> + AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0,
> ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL, PORT_B_DP, 0); //DP PortB
> + break;
> + case 4:
> + AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0,
> ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL, PORT_C_DP, 0); //DP PortC
> + break;
> + case 5:
> + AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0,
> ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL, PORT_C_DP, 0); //eDP Port
> C
> + break;
> + case 6:
> + AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0,
> ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL, PORT_MIPI_A, 0); //DSI Port
> A
> + break;
> + case 7:
> + AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0,
> ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL, PORT_MIPI_C, 0); //DSI Port
> C
> + break;
> + default:
> + AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0,
> ACPI_ADR_DISPLAY_TYPE_VGA, PORT_CRT, 0);
> + break;
> + }
> +
> + SetDevicePathNodeLength (&AcpiAdr.Header, sizeof
> (ACPI_ADR_DEVICE_PATH));
> +
> + MyDevicePath = AppendDevicePathNode(MyDevicePath,
> (EFI_DEVICE_PATH_PROTOCOL*)&AcpiAdr);
> +
> + gBS->ConnectController (
> + PciDeviceHandle,
> + NULL,
> + MyDevicePath,
> + FALSE
> + );
> +
> + FreePool(MyDevicePath);
> + }
> + else
> + {
> + gBS->ConnectController (
> + PciDeviceHandle,
> + NULL,
> + NULL,
> + FALSE
> + );
> + }
> +
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiGraphicsOutputProtocolGuid,
> + NULL,
> + &GopHandleCount,
> + &GopHandleBuffer
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Add all the child handles as possible Console Device
> + //
> + for (Index = 0; Index < GopHandleCount; Index++) {
> + Status = gBS->HandleProtocol (
> + GopHandleBuffer[Index],
> + &gEfiDevicePathProtocolGuid,
> + (VOID**)&TempDevicePath
> + );
> + if (EFI_ERROR (Status)) {
> + continue;
> + }
> + if (CompareMem (
> + PciDevicePath,
> + TempDevicePath,
> + GetDevicePathSize (PciDevicePath) - END_DEVICE_PATH_LENGTH
> + ) == 0) {
> + //
> + // In current implementation, we only enable one of the child handles
> + // as console device, i.e. sotre one of the child handle's device
> + // path to variable "ConOut"
> + // In future, we could select all child handles to be console device
> + //
> + *GopDevicePath = TempDevicePath;
> + }
> + }
> + gBS->FreePool (GopHandleBuffer);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +
> + Search out all the platform pci or agp video device. The function may will
> + find multiple video device, and return all enabled device path.
> +
> + @param PlugInPciVgaDevicePath Return the platform plug in pci video
> device
> + path if the system have plug in pci video device.
> + @param OnboardPciVgaDevicePath Return the platform active agp video
> device path
> + if the system have plug in agp video device or on
> + chip agp device.
> +
> + @retval EFI_SUCCSS Get all platform active video device path.
> + @retval EFI_STATUS Return the status of gBS->LocateDevicePath (),
> + gBS->ConnectController (),
> + and gBS->LocateHandleBuffer ().
> +
> +**/
> +EFI_STATUS
> +GetPlugInPciVgaDevicePath (
> + IN OUT EFI_DEVICE_PATH_PROTOCOL **PlugInPciVgaDevicePath,
> + IN OUT EFI_DEVICE_PATH_PROTOCOL **OnboardPciVgaDevicePath
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE RootHandle;
> + UINTN HandleCount;
> + EFI_HANDLE *HandleBuffer;
> + UINTN Index;
> + UINTN Index1;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + BOOLEAN PlugInPciVga;
> + EFI_PCI_IO_PROTOCOL *PciIo;
> + PCI_TYPE00 Pci;
> +
> + DevicePath = NULL;
> + PlugInPciVga = TRUE;
> + HandleCount = 0;
> + HandleBuffer = NULL;
> +
> + //
> + // Make all the PCI_IO protocols on PCI Seg 0 show up
> + //
> + BdsLibConnectDevicePath (gPlatformRootBridges[0]);
> +
> + Status = gBS->LocateDevicePath (
> + &gEfiDevicePathProtocolGuid,
> + &gPlatformRootBridges[0],
> + &RootHandle
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + Status = gBS->ConnectController (
> + RootHandle,
> + NULL,
> + NULL,
> + FALSE
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Start to check all the pci io to find all possible VGA device
> + //
> + HandleCount = 0;
> + HandleBuffer = NULL;
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiPciIoProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + for (Index = 0; Index < HandleCount; Index++) {
> + Status = gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gEfiPciIoProtocolGuid,
> + (VOID**)&PciIo
> + );
> + if (!EFI_ERROR (Status)) {
> +
> + //
> + // Check for all VGA device
> + //
> + Status = PciIo->Pci.Read (
> + PciIo,
> + EfiPciIoWidthUint32,
> + 0,
> + sizeof (Pci) / sizeof (UINT32),
> + &Pci
> + );
> + if (EFI_ERROR (Status)) {
> + continue;
> + }
> +
> + //
> + // Here we decide which VGA device to enable in PCI bus
> + //
> + // The first plugin PCI VGA card device will be present as PCI VGA
> + // The onchip AGP or AGP card will be present as AGP VGA
> + //
> + if (!IS_PCI_VGA (&Pci)) {
> + continue;
> + }
> +
> + //
> + // Set the device as the possible console out device,
> + //
> + // Below code will make every VGA device to be one
> + // of the possibe console out device
> + //
> + PlugInPciVga = TRUE;
> + gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gEfiDevicePathProtocolGuid,
> + (VOID**)&DevicePath
> + );
> +
> + Index1 = 0;
> +
> + while (gPlatformAllPossiblePciVgaConsole[Index1] != NULL) {
> + if (CompareMem (
> + DevicePath,
> + gPlatformAllPossiblePciVgaConsole[Index1],
> + GetDevicePathSize (gPlatformAllPossiblePciVgaConsole[Index1])
> + ) == 0) {
> +
> + //
> + // This device is an AGP device
> + //
> + *OnboardPciVgaDevicePath = DevicePath;
> + PlugInPciVga = FALSE;
> + break;
> + }
> +
> + Index1 ++;
> + }
> +
> + if (PlugInPciVga) {
> + *PlugInPciVgaDevicePath = DevicePath;
> + }
> + }
> + }
> +
> + FreePool (HandleBuffer);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +
> + Find the platform active vga, and base on the policy to enable the vga as
> + the console out device. The policy is driven by one setup variable "VBIOS".
> +
> + None.
> +
> + @param EFI_UNSUPPORTED There is no active vga device
> +
> + @retval EFI_STATUS Return the status of BdsLibGetVariableAndSize
> ()
> +
> +**/
> +EFI_STATUS
> +PlatformBdsForceActiveVga (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + EFI_DEVICE_PATH_PROTOCOL *PlugInPciVgaDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *OnboardPciVgaDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePathFirst;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePathSecond;
> + EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;
> + UINTN VarSize;
> + SYSTEM_CONFIGURATION mSystemConfiguration;
> +
> + Status = EFI_SUCCESS;
> + PlugInPciVgaDevicePath = NULL;
> + OnboardPciVgaDevicePath = NULL;
> +
> + //
> + // Check the policy which is the first enabled VGA
> + //
> + GetPlugInPciVgaDevicePath (&PlugInPciVgaDevicePath,
> &OnboardPciVgaDevicePath);
> +
> + if (PlugInPciVgaDevicePath == NULL && OnboardPciVgaDevicePath ==
> NULL) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"Setup",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> +
> + if ((PlugInPciVgaDevicePath == NULL && OnboardPciVgaDevicePath !=
> NULL) ) {
> + DEBUG ((EFI_D_ERROR,"Update onboard PCI VGA ...\n"));
> + DevicePathFirst = OnboardPciVgaDevicePath;
> + DevicePathSecond = PlugInPciVgaDevicePath;
> + goto UpdateConOut;
> + }
> + if(OnboardPciVgaDevicePath != NULL &&
> mSystemConfiguration.PrimaryVideoAdaptor == 0) {
> + DEBUG ((EFI_D_ERROR,"Update onboard PCI VGA When set
> primary!!!...\n"));
> + DevicePathFirst = OnboardPciVgaDevicePath;
> + DevicePathSecond = PlugInPciVgaDevicePath;
> + goto UpdateConOut;
> + }
> +
> + DEBUG ((EFI_D_ERROR,"Update plug in PCI VGA ...\n"));
> + DevicePathFirst = PlugInPciVgaDevicePath;
> + DevicePathSecond = OnboardPciVgaDevicePath;
> +
> +UpdateConOut:
> + GetGopDevicePath (DevicePathFirst, &GopDevicePath);
> + DevicePathFirst = GopDevicePath;
> +
> + Status = BdsLibUpdateConsoleVariable (
> + L"ConOut",
> + DevicePathFirst,
> + DevicePathSecond
> + );
> +
> + return Status;
> +}
> +
> +VOID
> +UpdateConsoleResolution(
> + VOID
> + )
> +{
> + UINT32 HorizontalResolution;
> + UINT32 VerticalResolution;
> + SYSTEM_CONFIGURATION SystemConfiguration;
> + UINTN VarSize;
> + EFI_STATUS Status;
> +
> +
> + HorizontalResolution = PcdGet32 (PcdSetupVideoHorizontalResolution);
> + VerticalResolution = PcdGet32 (PcdSetupVideoVerticalResolution);
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"Setup",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + switch (SystemConfiguration.IgdFlatPanel) {
> +
> + case 0:
> + //
> + // Use the detault PCD values.
> + //
> + break;
> +
> + case 1:
> + HorizontalResolution = 640;
> + VerticalResolution = 480;
> + break;
> +
> + case 2:
> + HorizontalResolution = 800;
> + VerticalResolution = 600;
> + break;
> +
> + case 3:
> + HorizontalResolution = 1024;
> + VerticalResolution = 768;
> + break;
> +
> + case 4:
> + HorizontalResolution = 1280;
> + VerticalResolution = 1024;
> + break;
> +
> + case 5:
> + HorizontalResolution = 1366;
> + VerticalResolution = 768;
> + break;
> +
> + case 6:
> + HorizontalResolution = 1680;
> + VerticalResolution = 1050;
> + break;
> +
> + case 7:
> + HorizontalResolution = 1920;
> + VerticalResolution = 1200;
> + break;
> +
> + case 8:
> + HorizontalResolution = 1280;
> + VerticalResolution = 800;
> + break;
> + }
> +
> + PcdSet32 (PcdSetupVideoHorizontalResolution, HorizontalResolution);
> + PcdSet32 (PcdSetupVideoVerticalResolution, VerticalResolution);
> + DEBUG ((EFI_D_ERROR, "HorizontalResolution = %x; VerticalResolution
> = %x", HorizontalResolution, VerticalResolution));
> +
> + return;
> +}
> +
> +/**
> + Connect the predefined platform default console device. Always try to find
> + and enable the vga device if have.
> +
> + @param PlatformConsole Predefined platform default console device
> array.
> +
> + @retval EFI_SUCCESS Success connect at least one ConIn and ConOut
> + device, there must have one ConOut device is
> + active vga device.
> +
> + @retval EFI_STATUS Return the status of
> + BdsLibConnectAllDefaultConsoles ()
> +
> +**/
> +EFI_STATUS
> +PlatformBdsConnectConsole (
> + IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole
> +)
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> + EFI_DEVICE_PATH_PROTOCOL *VarConout;
> + EFI_DEVICE_PATH_PROTOCOL *VarConin;
> + UINTN DevicePathSize;
> +
> + UpdateConsoleResolution();
> +
> + Index = 0;
> + Status = EFI_SUCCESS;
> + DevicePathSize = 0;
> + VarConout = BdsLibGetVariableAndSize (
> + L"ConOut",
> + &gEfiGlobalVariableGuid,
> + &DevicePathSize
> + );
> + VarConin = BdsLibGetVariableAndSize (
> + L"ConIn",
> + &gEfiGlobalVariableGuid,
> + &DevicePathSize
> + );
> + if (VarConout == NULL || VarConin == NULL) {
> + //
> + // Have chance to connect the platform default console,
> + // the platform default console is the minimum device group
> + // the platform should support
> + //
> + while (PlatformConsole[Index].DevicePath != NULL) {
> +
> + //
> + // Update the console variable with the connect type
> + //
> + if ((PlatformConsole[Index].ConnectType & CONSOLE_IN) ==
> CONSOLE_IN) {
> + BdsLibUpdateConsoleVariable (L"ConIn",
> PlatformConsole[Index].DevicePath, NULL);
> + }
> +
> + if ((PlatformConsole[Index].ConnectType & CONSOLE_OUT) ==
> CONSOLE_OUT) {
> + BdsLibUpdateConsoleVariable (L"ConOut",
> PlatformConsole[Index].DevicePath, NULL);
> + }
> +
> + if ((PlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR)
> {
> + BdsLibUpdateConsoleVariable (L"ErrOut",
> PlatformConsole[Index].DevicePath, NULL);
> + }
> +
> + Index ++;
> + }
> + }
> +
> + //
> + // Make sure we have at least one active VGA, and have the right
> + // active VGA in console variable
> + //
> + Status = PlatformBdsForceActiveVga ();
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + DEBUG ((EFI_D_INFO, "DISPLAY INIT DONE\n"));
> +
> + //
> + // Connect the all the default console with current console variable
> + //
> + Status = BdsLibConnectAllDefaultConsoles ();
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Connect with predefined platform connect sequence,
> + the OEM/IBV can customize with their own connect sequence.
> +
> + @param None.
> +
> + @retval None.
> +
> +**/
> +VOID
> +PlatformBdsConnectSequence (
> + VOID
> + )
> +{
> + UINTN Index;
> +
> + Index = 0;
> +
> + //
> + // Here we can get the customized platform connect sequence
> + // Notes: we can connect with new variable which record the
> + // last time boots connect device path sequence
> + //
> + while (gPlatformConnectSequence[Index] != NULL) {
> +
> + //
> + // Build the platform boot option
> + //
> + BdsLibConnectDevicePath (gPlatformConnectSequence[Index]);
> + Index ++;
> + }
> +
> + //
> + // Just use the simple policy to connect all devices
> + // There should be no difference between debug tip and release tip, or it
> will be extremely hard to debug.
> + //
> + // There is case that IdeController driver will write boot script in driver
> model Start() function. It will be rejected by boot script save.
> + // It is only found when DEBUG disabled, because we are using
> BdsLibConnectAll() when DEBUG enabled.
> + //
> + // So we use BdsLibConnectAll() here to make sure IdeController.Start() is
> invoked before InstallReadyToLock().
> + // We may also consider to connect SataController only later if needed.
> + //
> + BdsLibConnectAll ();
> +}
> +
> +/**
> +
> + Load the predefined driver option, OEM/IBV can customize this
> + to load their own drivers
> +
> + @param BdsDriverLists The header of the driver option link list.
> +
> + @retval None.
> +
> +**/
> +VOID
> +PlatformBdsGetDriverOption (
> + IN OUT LIST_ENTRY *BdsDriverLists
> + )
> +{
> + UINTN Index;
> +
> + Index = 0;
> +
> + //
> + // Here we can get the customized platform driver option
> + //
> + while (gPlatformDriverOption[Index] != NULL) {
> +
> + //
> + // Build the platform boot option
> + //
> + BdsLibRegisterNewOption (BdsDriverLists, gPlatformDriverOption[Index],
> NULL, L"DriverOrder");
> + Index ++;
> + }
> +
> +}
> +
> +/**
> + This function is used for some critical time if the the system
> + have no any boot option, and there is no time out for user to add
> + the new boot option. This can also treat as the platform default
> + boot option.
> +
> + @param BdsBootOptionList The header of the boot option link list.
> +
> + @retval None.
> +
> +**/
> +VOID
> +PlatformBdsPredictBootOption (
> + IN OUT LIST_ENTRY *BdsBootOptionList
> + )
> +{
> + UINTN Index;
> +
> + Index = 0;
> +
> + //
> + // Here give chance to get platform boot option data
> + //
> + while (gPlatformBootOption[Index] != NULL) {
> +
> + //
> + // Build the platform boot option
> + //
> + BdsLibRegisterNewOption (BdsBootOptionList,
> gPlatformBootOption[Index], NULL, L"BootOrder");
> + Index ++;
> + }
> +}
> +
> +/**
> + Perform the platform diagnostic, such like test memory. OEM/IBV also
> + can customize this fuction to support specific platform diagnostic.
> +
> + @param MemoryTestLevel The memory test intensive level
> + @param QuietBoot Indicate if need to enable the quiet boot
> + @param BaseMemoryTest A pointer to BdsMemoryTest()
> +
> + @retval None.
> +
> +**/
> +VOID
> +PlatformBdsDiagnostics (
> + IN EXTENDMEM_COVERAGE_LEVEL MemoryTestLevel,
> + IN BOOLEAN QuietBoot,
> + IN BASEM_MEMORY_TEST BaseMemoryTest
> + )
> +{
> + EFI_STATUS Status;
> +
> + //
> + // Here we can decide if we need to show
> + // the diagnostics screen
> + // Notes: this quiet boot code should be remove
> + // from the graphic lib
> + //
> + if (QuietBoot) {
> + EnableQuietBoot (PcdGetPtr(PcdLogoFile));
> +
> + //
> + // Perform system diagnostic
> + //
> + Status = BaseMemoryTest (MemoryTestLevel);
> + if (EFI_ERROR (Status)) {
> + DisableQuietBoot ();
> + }
> +
> + return;
> + }
> +
> + //
> + // Perform system diagnostic
> + //
> + Status = BaseMemoryTest (MemoryTestLevel);
> +}
> +
> +
> +/**
> + For EFI boot option, BDS separate them as six types:
> + 1. Network - The boot option points to the SimpleNetworkProtocol device.
> + Bds will try to automatically create this type boot option when
> enumerate.
> + 2. Shell - The boot option points to internal flash shell.
> + Bds will try to automatically create this type boot option when
> enumerate.
> + 3. Removable BlockIo - The boot option only points to the removable
> media
> + device, like USB flash disk, DVD, Floppy etc.
> + These device should contain a *removable* blockIo
> + protocol in their device handle.
> + Bds will try to automatically create this type boot option
> + when enumerate.
> + 4. Fixed BlockIo - The boot option only points to a Fixed blockIo device,
> + like HardDisk.
> + These device should contain a *fixed* blockIo
> + protocol in their device handle.
> + BDS will skip fixed blockIo devices, and NOT
> + automatically create boot option for them. But BDS
> + will help to delete those fixed blockIo boot option,
> + whose description rule conflict with other auto-created
> + boot options.
> + 5. Non-BlockIo Simplefile - The boot option points to a device whose
> handle
> + has SimpleFileSystem Protocol, but has no blockio
> + protocol. These devices do not offer blockIo
> + protocol, but BDS still can get the
> + \EFI\BOOT\boot{machinename}.EFI by SimpleFileSystem
> + Protocol.
> + 6. File - The boot option points to a file. These boot options are usually
> + created by user manually or OS loader. BDS will not delete or modify
> + these boot options.
> +
> + This function will enumerate all possible boot device in the system, and
> + automatically create boot options for Network, Shell, Removable BlockIo,
> + and Non-BlockIo Simplefile devices.
> + It will only execute once of every boot.
> +
> + @param BdsBootOptionList The header of the link list which indexed all
> + current boot options
> +
> + @retval EFI_SUCCESS Finished all the boot device enumerate and
> create
> + the boot option base on that boot device
> +
> + @retval EFI_OUT_OF_RESOURCES Failed to enumerate the boot device
> and create the boot option list
> +**/
> +EFI_STATUS
> +EFIAPI
> +PlatformBdsLibEnumerateAllBootOption (
> + IN OUT LIST_ENTRY *BdsBootOptionList
> + )
> +{
> + EFI_STATUS Status;
> + UINT16 FloppyNumber;
> + UINT16 HarddriveNumber;
> + UINT16 CdromNumber;
> + UINT16 UsbNumber;
> + UINT16 MiscNumber;
> + UINT16 ScsiNumber;
> + UINT16 NonBlockNumber;
> + UINTN NumberBlockIoHandles;
> + EFI_HANDLE *BlockIoHandles;
> + EFI_BLOCK_IO_PROTOCOL *BlkIo;
> + BOOLEAN Removable[2];
> + UINTN RemovableIndex;
> + UINTN Index;
> + UINTN NumOfLoadFileHandles;
> + EFI_HANDLE *LoadFileHandles;
> + UINTN FvHandleCount;
> + EFI_HANDLE *FvHandleBuffer;
> + EFI_FV_FILETYPE Type;
> + UINTN Size;
> + EFI_FV_FILE_ATTRIBUTES Attributes;
> + UINT32 AuthenticationStatus;
> + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + UINTN DevicePathType;
> + CHAR16 Buffer[40];
> + EFI_HANDLE *FileSystemHandles;
> + UINTN NumberFileSystemHandles;
> + BOOLEAN NeedDelete;
> + EFI_IMAGE_DOS_HEADER DosHeader;
> + CHAR8 *PlatLang;
> + CHAR8 *LastLang;
> + EFI_IMAGE_OPTIONAL_HEADER_UNION HdrData;
> + EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
> + CHAR16 *MacStr;
> + CHAR16 *IPverStr;
> + EFI_HANDLE *NetworkHandles;
> + UINTN BufferSize;
> +
> + FloppyNumber = 0;
> + HarddriveNumber = 0;
> + CdromNumber = 0;
> + UsbNumber = 0;
> + MiscNumber = 0;
> + ScsiNumber = 0;
> + PlatLang = NULL;
> + LastLang = NULL;
> + ZeroMem (Buffer, sizeof (Buffer));
> +
> + //
> + // If the boot device enumerate happened, just get the boot
> + // device from the boot order variable
> + //
> + if (mEnumBootDevice) {
> + GetVariable2 (LAST_ENUM_LANGUAGE_VARIABLE_NAME,
> &gLastEnumLangGuid, (VOID**)&LastLang, NULL);
> + GetEfiGlobalVariable2 (L"PlatformLang", (VOID**)&PlatLang, NULL);
> + ASSERT (PlatLang != NULL);
> + if ((LastLang != NULL) && (AsciiStrCmp (LastLang, PlatLang) == 0)) {
> + Status = BdsLibBuildOptionFromVar (BdsBootOptionList, L"BootOrder");
> + FreePool (LastLang);
> + FreePool (PlatLang);
> + return Status;
> + } else {
> + Status = gRT->SetVariable (
> + LAST_ENUM_LANGUAGE_VARIABLE_NAME,
> + &gLastEnumLangGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + AsciiStrSize (PlatLang),
> + PlatLang
> + );
> + //
> + // Failure to set the variable only impacts the performance next time
> enumerating the boot options.
> + //
> +
> + if (LastLang != NULL) {
> + FreePool (LastLang);
> + }
> + FreePool (PlatLang);
> + }
> + }
> +
> + //
> + // Notes: this dirty code is to get the legacy boot option from the
> + // BBS table and create to variable as the EFI boot option, it should
> + // be removed after the CSM can provide legacy boot option directly
> + //
> + REFRESH_LEGACY_BOOT_OPTIONS;
> +
> + //
> + // Delete invalid boot option
> + //
> + BdsDeleteAllInvalidEfiBootOption ();
> +
> + //
> + // Parse removable media followed by fixed media.
> + // The Removable[] array is used by the for-loop below to create
> removable media boot options
> + // at first, and then to create fixed media boot options.
> + //
> + Removable[0] = FALSE;
> + Removable[1] = TRUE;
> +
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiBlockIoProtocolGuid,
> + NULL,
> + &NumberBlockIoHandles,
> + &BlockIoHandles
> + );
> +
> + for (RemovableIndex = 0; RemovableIndex < 2; RemovableIndex++) {
> + for (Index = 0; Index < NumberBlockIoHandles; Index++) {
> + Status = gBS->HandleProtocol (
> + BlockIoHandles[Index],
> + &gEfiBlockIoProtocolGuid,
> + (VOID **) &BlkIo
> + );
> + //
> + // skip the logical partition
> + //
> + if (EFI_ERROR (Status) || BlkIo->Media->LogicalPartition) {
> + continue;
> + }
> +
> + //
> + // firstly fixed block io then the removable block io
> + //
> + if (BlkIo->Media->RemovableMedia == Removable[RemovableIndex]) {
> + continue;
> + }
> + DevicePath = DevicePathFromHandle (BlockIoHandles[Index]);
> + DevicePathType = BdsGetBootTypeFromDevicePath (DevicePath);
> +
> + switch (DevicePathType) {
> + case BDS_EFI_ACPI_FLOPPY_BOOT:
> + if (FloppyNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_FLOPPY)), FloppyNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_FLOPPY)));
> + }
> + BdsLibBuildOptionFromHandle (BlockIoHandles[Index],
> BdsBootOptionList, Buffer);
> + FloppyNumber++;
> + break;
> +
> + //
> + // Assume a removable SATA device should be the DVD/CD device, a
> fixed SATA device should be the Hard Drive device.
> + //
> + case BDS_EFI_MESSAGE_ATAPI_BOOT:
> + case BDS_EFI_MESSAGE_SATA_BOOT:
> + if (BlkIo->Media->RemovableMedia) {
> + if (CdromNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_CD_DVD)), CdromNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_CD_DVD)));
> + }
> + CdromNumber++;
> + } else {
> + if (HarddriveNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_HARDDRIVE)), HarddriveNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_HARDDRIVE)));
> + }
> + HarddriveNumber++;
> + }
> + DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Buffer: %S\n", Buffer));
> + BdsLibBuildOptionFromHandle (BlockIoHandles[Index],
> BdsBootOptionList, Buffer);
> + break;
> +
> + case BDS_EFI_MESSAGE_USB_DEVICE_BOOT:
> + if (UsbNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_USB)), UsbNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_USB)));
> + }
> + BdsLibBuildOptionFromHandle (BlockIoHandles[Index],
> BdsBootOptionList, Buffer);
> + UsbNumber++;
> + break;
> +
> + case BDS_EFI_MESSAGE_SCSI_BOOT:
> + if (ScsiNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_SCSI)), ScsiNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_SCSI)));
> + }
> + BdsLibBuildOptionFromHandle (BlockIoHandles[Index],
> BdsBootOptionList, Buffer);
> + ScsiNumber++;
> + break;
> +
> + case BDS_EFI_MESSAGE_MISC_BOOT:
> + default:
> + if (MiscNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_MISC)), MiscNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_MISC)));
> + }
> + BdsLibBuildOptionFromHandle (BlockIoHandles[Index],
> BdsBootOptionList, Buffer);
> + MiscNumber++;
> + break;
> + }
> + }
> + }
> +
> + if (NumberBlockIoHandles != 0) {
> + FreePool (BlockIoHandles);
> + }
> +
> + //
> + // If there is simple file protocol which does not consume block Io protocol,
> create a boot option for it here.
> + //
> + NonBlockNumber = 0;
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiSimpleFileSystemProtocolGuid,
> + NULL,
> + &NumberFileSystemHandles,
> + &FileSystemHandles
> + );
> + for (Index = 0; Index < NumberFileSystemHandles; Index++) {
> + Status = gBS->HandleProtocol (
> + FileSystemHandles[Index],
> + &gEfiBlockIoProtocolGuid,
> + (VOID **) &BlkIo
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Skip if the file system handle supports a BlkIo protocol,
> + //
> + continue;
> + }
> +
> + //
> + // Do the removable Media thing. \EFI\BOOT\boot{machinename}.EFI
> + // machinename is ia32, ia64, x64, ...
> + //
> + Hdr.Union = &HdrData;
> + NeedDelete = TRUE;
> + Status = BdsLibGetImageHeader (
> + FileSystemHandles[Index],
> + EFI_REMOVABLE_MEDIA_FILE_NAME,
> + &DosHeader,
> + Hdr
> + );
> + if (!EFI_ERROR (Status) &&
> + EFI_IMAGE_MACHINE_TYPE_SUPPORTED (Hdr.Pe32-
> >FileHeader.Machine) &&
> + Hdr.Pe32->OptionalHeader.Subsystem ==
> EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION) {
> + NeedDelete = FALSE;
> + }
> +
> + if (NeedDelete) {
> + //
> + // No such file or the file is not a EFI application, delete this boot option
> + //
> + BdsLibDeleteOptionFromHandle (FileSystemHandles[Index]);
> + } else {
> + if (NonBlockNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_NON_BLOCK)), NonBlockNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_NON_BLOCK)));
> + }
> + BdsLibBuildOptionFromHandle (FileSystemHandles[Index],
> BdsBootOptionList, Buffer);
> + NonBlockNumber++;
> + }
> + }
> +
> + if (NumberFileSystemHandles != 0) {
> + FreePool (FileSystemHandles);
> + }
> +
> + //
> + // Check if we have on flash shell
> + //
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiFirmwareVolume2ProtocolGuid,
> + NULL,
> + &FvHandleCount,
> + &FvHandleBuffer
> + );
> + for (Index = 0; Index < FvHandleCount; Index++) {
> + gBS->HandleProtocol (
> + FvHandleBuffer[Index],
> + &gEfiFirmwareVolume2ProtocolGuid,
> + (VOID **) &Fv
> + );
> +
> + Status = Fv->ReadFile (
> + Fv,
> + &gUefiShellFileGuid,
> + NULL,
> + &Size,
> + &Type,
> + &Attributes,
> + &AuthenticationStatus
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + // Skip if no shell file in the FV
> + //
> + continue;
> + }
> + //
> + // Build the shell boot option
> + //
> + BdsLibBuildOptionFromShell (FvHandleBuffer[Index], BdsBootOptionList);
> + }
> +
> + if (FvHandleCount != 0) {
> + FreePool (FvHandleBuffer);
> + }
> +
> + //
> + // Parse Network Boot Device
> + //
> + NumOfLoadFileHandles = 0;
> + //
> + // Search Load File protocol for PXE boot option.
> + //
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiLoadFileProtocolGuid,
> + NULL,
> + &NumOfLoadFileHandles,
> + &LoadFileHandles
> + );
> +
> + for (Index = 0; Index < NumOfLoadFileHandles; Index++) {
> +
> +//
> +//Locate EFI_DEVICE_PATH_PROTOCOL to dynamically get IPv4/IPv6
> protocol information.
> +//
> +
> + Status = gBS->HandleProtocol (
> + LoadFileHandles[Index],
> + &gEfiDevicePathProtocolGuid,
> + (VOID **) &DevicePath
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> +
> + while (!IsDevicePathEnd (DevicePath)) {
> + if ((DevicePath->Type == MESSAGING_DEVICE_PATH) &&
> + (DevicePath->SubType == MSG_IPv4_DP)) {
> +
> + //
> + //Get handle infomation
> + //
> + BufferSize = 0;
> + NetworkHandles = NULL;
> + Status = gBS->LocateHandle (
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + NetworkHandles
> + );
> +
> + if (Status == EFI_BUFFER_TOO_SMALL) {
> + NetworkHandles = AllocateZeroPool(BufferSize);
> + if (NetworkHandles == NULL) {
> + return (EFI_OUT_OF_RESOURCES);
> + }
> + Status = gBS->LocateHandle(
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + NetworkHandles
> + );
> + }
> +
> + //
> + //Get the MAC string
> + //
> + Status = NetLibGetMacString (
> + *NetworkHandles,
> + NULL,
> + &MacStr
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + IPverStr = L" IPv4";
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s%s%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_NETWORK)),MacStr,IPverStr);
> + break;
> + }
> + if((DevicePath->Type == MESSAGING_DEVICE_PATH) &&
> + (DevicePath->SubType == MSG_IPv6_DP)) {
> +
> + //
> + //Get handle infomation
> + //
> + BufferSize = 0;
> + NetworkHandles = NULL;
> + Status = gBS->LocateHandle (
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + NetworkHandles
> + );
> +
> + if (Status == EFI_BUFFER_TOO_SMALL) {
> + NetworkHandles = AllocateZeroPool(BufferSize);
> + if (NetworkHandles == NULL) {
> + return (EFI_OUT_OF_RESOURCES);
> + }
> + Status = gBS->LocateHandle(
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + NetworkHandles
> + );
> + }
> +
> + //
> + //Get the MAC string
> + //
> + Status = NetLibGetMacString (
> + *NetworkHandles,
> + NULL,
> + &MacStr
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + IPverStr = L" IPv6";
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s%s%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_NETWORK)),MacStr,IPverStr);
> + break;
> + }
> + DevicePath = NextDevicePathNode (DevicePath);
> + }
> +
> + BdsLibBuildOptionFromHandle (LoadFileHandles[Index],
> BdsBootOptionList, Buffer);
> + }
> +
> + if (NumOfLoadFileHandles != 0) {
> + FreePool (LoadFileHandles);
> + }
> +
> + //
> + // Check if we have on flash shell
> + //
> + /* gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiFirmwareVolume2ProtocolGuid,
> + NULL,
> + &FvHandleCount,
> + &FvHandleBuffer
> + );
> + for (Index = 0; Index < FvHandleCount; Index++) {
> + gBS->HandleProtocol (
> + FvHandleBuffer[Index],
> + &gEfiFirmwareVolume2ProtocolGuid,
> + (VOID **) &Fv
> + );
> +
> + Status = Fv->ReadFile (
> + Fv,
> + &gUefiShellFileGuid,
> + NULL,
> + &Size,
> + &Type,
> + &Attributes,
> + &AuthenticationStatus
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + // Skip if no shell file in the FV
> + //
> + continue;
> + }
> + //
> + // Build the shell boot option
> + //
> + BdsLibBuildOptionFromShell (FvHandleBuffer[Index], BdsBootOptionList);
> + }
> +
> + if (FvHandleCount != 0) {
> + FreePool (FvHandleBuffer);
> + } */
> +
> + //
> + // Make sure every boot only have one time
> + // boot device enumerate
> + //
> + Status = BdsLibBuildOptionFromVar (BdsBootOptionList, L"BootOrder");
> + mEnumBootDevice = TRUE;
> +
> + return Status;
> +}
> +
> +
> +
> +/**
> +
> + The function will execute with as the platform policy, current policy
> + is driven by boot mode. IBV/OEM can customize this code for their specific
> + policy action.
> +
> + @param DriverOptionList - The header of the driver option link list
> + @param BootOptionList - The header of the boot option link list
> + @param ProcessCapsules - A pointer to ProcessCapsules()
> + @param BaseMemoryTest - A pointer to BaseMemoryTest()
> +
> + @retval None.
> +
> +**/
> +VOID
> +EFIAPI
> +PlatformBdsPolicyBehavior (
> + IN OUT LIST_ENTRY *DriverOptionList,
> + IN OUT LIST_ENTRY *BootOptionList,
> + IN PROCESS_CAPSULES BdsProcessCapsules,
> + IN BASEM_MEMORY_TEST BaseMemoryTest
> + )
> +{
> + EFI_STATUS Status;
> + UINT16 Timeout;
> + EFI_BOOT_MODE BootMode;
> + BOOLEAN DeferredImageExist;
> + UINTN Index;
> + SYSTEM_CONFIGURATION SystemConfiguration;
> + UINTN VarSize;
> + PLATFORM_PCI_DEVICE_PATH *EmmcBootDevPath;
> + EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
> + EFI_HANDLE FvProtocolHandle;
> + UINTN HandleCount;
> + EFI_HANDLE *HandleBuffer;
> + UINTN Index1;
> + UINTN SataPciRegBase = 0;
> + UINT16 SataModeSelect = 0;
> + VOID *RegistrationExitPmAuth = NULL;
> + EFI_EVENT Event;
> + BOOLEAN IsFirstBoot;
> + UINT16 *BootOrder;
> + UINTN BootOrderSize;
> + ESRT_MANAGEMENT_PROTOCOL *EsrtManagement;
> +
> + Timeout = PcdGet16 (PcdPlatformBootTimeOut);
> + if (Timeout > 10 ) {
> + //we think the Timeout variable is corrupted
> + Timeout = 10;
> + }
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> +
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + //
> + // Load the driver option as the driver option list
> + //
> + PlatformBdsGetDriverOption (DriverOptionList);
> +
> + //
> + // Get current Boot Mode
> + //
> + BootMode = GetBootModeHob();
> +
> + //
> + // No deferred images exist by default
> + //
> + DeferredImageExist = FALSE;
> + if ((BootMode != BOOT_WITH_MINIMAL_CONFIGURATION) &&
> (PcdGet32(PcdFlashFvShellSize) > 0)){
> + gDS->ProcessFirmwareVolume (
> + (VOID *)(UINTN)PcdGet32(PcdFlashFvShellBase),
> + PcdGet32(PcdFlashFvShellSize),
> + &FvProtocolHandle
> + );
> + }
> +
> + if (SystemConfiguration.FastBoot == 1) {
> + BootOrder = BdsLibGetVariableAndSize (
> + L"BootOrder",
> + &gEfiGlobalVariableGuid,
> + &BootOrderSize
> + );
> + if ((BootOrder != NULL) && (BootMode != BOOT_ON_FLASH_UPDATE)) {
> + //
> + // BootOrder exist, it means system has boot before. We can do fast
> boot.
> + //
> + BootMode = BOOT_WITH_MINIMAL_CONFIGURATION;
> + }
> + }
> +
> +
> + //
> + // Use eMMC to boot OS and turn on AHCI, when SATA HDD is
> diconnected,
> + // SATA AHCI CTLR device will show yellow bang, implement this solution
> to solve it.
> + //
> + SataPciRegBase = MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_SATA,
> 0, 0);
> + SataModeSelect = MmioRead16 (SataPciRegBase + R_PCH_SATA_MAP) &
> B_PCH_SATA_MAP_SMS_MASK;
> + Status = EFI_SUCCESS;
> + if (SataModeSelect != V_PCH_SATA_MAP_SMS_IDE) {
> + Status = gBS->CreateEvent (
> + EVT_NOTIFY_SIGNAL,
> + TPL_CALLBACK,
> + DisableAhciCtlr,
> + &SataPciRegBase,
> + &Event
> + );
> + if (!EFI_ERROR (Status)) {
> + Status = gBS->RegisterProtocolNotify (
> + &gExitPmAuthProtocolGuid,
> + Event,
> + &RegistrationExitPmAuth
> + );
> + }
> + }
> +
> + Status = gBS->LocateProtocol(&gEsrtManagementProtocolGuid, NULL,
> (VOID **)&EsrtManagement);
> + if (EFI_ERROR(Status)) {
> + EsrtManagement = NULL;
> + }
> +
> + DEBUG ((DEBUG_INFO, "BDS: BootMode=%02x\n", BootMode));
> +
> + switch (BootMode) {
> +
> + case BOOT_WITH_MINIMAL_CONFIGURATION:
> + PlatformBdsInitHotKeyEvent ();
> + PlatformBdsConnectSimpleConsole (gPlatformSimpleConsole);
> +
> +
> + //
> + // Check to see if it's needed to dispatch more DXE drivers.
> + //
> + for (Index = 0; Index < sizeof(ConnectDriverTable)/sizeof(EFI_GUID *);
> Index++) {
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + ConnectDriverTable[Index],
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> + if (!EFI_ERROR (Status)) {
> + for (Index1 = 0; Index1 < HandleCount; Index1++) {
> + gBS->ConnectController (
> + HandleBuffer[Index1],
> + NULL,
> + NULL,
> + TRUE
> + );
> + }
> + }
> +
> + if (HandleBuffer != NULL) {
> + FreePool (HandleBuffer);
> + }
> +
> + gDS->Dispatch ();
> + }
> +
> + //
> + // Locate the Global NVS Protocol.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiGlobalNvsAreaProtocolGuid,
> + NULL,
> + (void **)&GlobalNvsArea
> + );
> + if (GlobalNvsArea->Area->emmcVersion == 0){
> + EmmcBootDevPath = (PLATFORM_PCI_DEVICE_PATH
> *)gPlatformSimpleBootOption[0];
> + EmmcBootDevPath->PciDevice.Device = 0x10;
> + }
> +
> + //
> + // Connect boot device here to give time to read keyboard.
> + //
> + BdsLibConnectDevicePath (gPlatformSimpleBootOption[0]);
> +
> + //
> + // This is a workround for dectecting hotkey from USB keyboard.
> + //
> + gBS->Stall(KEYBOARD_TIMER_INTERVAL);
> +
> + if (mHotKeyTimerEvent != NULL) {
> + gBS->SetTimer (
> + mHotKeyTimerEvent,
> + TimerCancel,
> + 0
> + );
> + gBS->CloseEvent (mHotKeyTimerEvent);
> + mHotKeyTimerEvent = NULL;
> + }
> + if (mHotKeyPressed) {
> + //
> + // Skip show progress count down
> + //
> + Timeout = 0xFFFF;
> + goto FULL_CONFIGURATION;
> + }
> +
> + EnableQuietBoot (PcdGetPtr(PcdLogoFile));
> + if (!SystemConfiguration.QuietBoot) {
> + PlatformBdsDiagnostics (IGNORE, FALSE, BaseMemoryTest);
> + }
> +
> +
> + #ifdef TPM_ENABLED
> + TcgPhysicalPresenceLibProcessRequest();
> + #endif
> + #ifdef FTPM_ENABLE
> + Tcg2PhysicalPresenceLibProcessRequest(NULL);
> + #endif
> +
> + if (EsrtManagement != NULL) {
> + EsrtManagement->LockEsrtRepository();
> + }
> +
> + //
> + // Close boot script and install ready to lock
> + //
> + InstallReadyToLock ();
> +
> + //
> + // Give one chance to enter the setup if we
> + // select Gummiboot "Reboot Into Firmware Interface" and Fast Boot is
> enabled.
> + //
> + BootIntoFirmwareInterface();
> + break;
> +
> + case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:
> +
> + //
> + // In no-configuration boot mode, we can connect the
> + // console directly.
> + //
> + BdsLibConnectAllDefaultConsoles ();
> + PlatformBdsDiagnostics (IGNORE, TRUE, BaseMemoryTest);
> +
> + //
> + // Perform some platform specific connect sequence
> + //
> + PlatformBdsConnectSequence ();
> +
> + //
> + // As console is ready, perform user identification again.
> + //
> + if (mCurrentUser == NULL) {
> + PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);
> + if (DeferredImageExist) {
> + //
> + // After user authentication, the deferred drivers was loaded again.
> + // Here, need to ensure the deferred images are connected.
> + //
> + BdsLibConnectAllDefaultConsoles ();
> + PlatformBdsConnectSequence ();
> + }
> + }
> +
> + if (EsrtManagement != NULL) {
> + EsrtManagement->LockEsrtRepository();
> + }
> +
> + //
> + // Close boot script and install ready to lock
> + //
> + InstallReadyToLock ();
> +
> + //
> + // Notes: current time out = 0 can not enter the
> + // front page
> + //
> + PlatformBdsEnterFrontPageWithHotKey (Timeout, FALSE);
> +
> + //
> + // Check the boot option with the boot option list
> + //
> + BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder");
> + break;
> +
> + case BOOT_ON_FLASH_UPDATE:
> +
> + //
> + // Boot with the specific configuration
> + //
> + PlatformBdsConnectConsole (gPlatformConsole);
> + PlatformBdsDiagnostics (EXTENSIVE, TRUE, BaseMemoryTest);
> +
> + DEBUG((DEBUG_INFO, "ProcessCapsules Before EndOfDxe......\n"));
> + ProcessCapsules ();
> + DEBUG((DEBUG_INFO, "ProcessCapsules Done\n"));
> +
> + //
> + // Close boot script and install ready to lock
> + //
> + InstallReadyToLock ();
> +
> + BdsLibConnectAll ();
> +
> + //
> + // Perform user identification
> + //
> + if (mCurrentUser == NULL) {
> + PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);
> + if (DeferredImageExist) {
> + //
> + // After user authentication, the deferred drivers was loaded again.
> + // Here, need to ensure the deferred images are connected.
> + //
> + BdsLibConnectAll ();
> + }
> + }
> +
> + if (EsrtManagement != NULL) {
> + EsrtManagement->SyncEsrtFmp();
> + }
> +
> + DEBUG((DEBUG_INFO, "ProcessCapsules After ConnectAll......\n"));
> + ProcessCapsules();
> + DEBUG((DEBUG_INFO, "ProcessCapsules Done\n"));
> + break;
> +
> + case BOOT_IN_RECOVERY_MODE:
> +
> + //
> + // In recovery mode, just connect platform console
> + // and show up the front page
> + //
> + PlatformBdsConnectConsole (gPlatformConsole);
> + PlatformBdsDiagnostics (EXTENSIVE, FALSE, BaseMemoryTest);
> + BdsLibConnectAll ();
> +
> + //
> + // Perform user identification
> + //
> + if (mCurrentUser == NULL) {
> + PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);
> + if (DeferredImageExist) {
> + //
> + // After user authentication, the deferred drivers was loaded again.
> + // Here, need to ensure the deferred drivers are connected.
> + //
> + BdsLibConnectAll ();
> + }
> + }
> +
> + //
> + // Close boot script and install ready to lock
> + //
> + InstallReadyToLock ();
> +
> + //
> + // In recovery boot mode, we still enter to the
> + // frong page now
> + //
> + PlatformBdsEnterFrontPageWithHotKey (Timeout, FALSE);
> + break;
> +
> +FULL_CONFIGURATION:
> + case BOOT_WITH_FULL_CONFIGURATION:
> + case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:
> + case BOOT_WITH_DEFAULT_SETTINGS:
> + default:
> +
> + //
> + // Connect platform console
> + //
> + Status = PlatformBdsConnectConsole (gPlatformConsole);
> + if (EFI_ERROR (Status)) {
> +
> + //
> + // Here OEM/IBV can customize with defined action
> + //
> + PlatformBdsNoConsoleAction ();
> + }
> +
> + //
> + // Chenyunh[TODO]: This is Workgroud to show the fs for uSDcard,
> + // Need to root cause this issue.
> + //
> + DEBUG ((DEBUG_ERROR, "Start to reconnect all driver.\n"));
> + BdsLibDisconnectAllEfi();
> + BdsLibConnectAll ();
> + DEBUG ((DEBUG_ERROR, "End to reconnect all driver.\n"));
> +
> + //
> + // Perform some platform specific connect sequence
> + //
> + PlatformBdsConnectSequence ();
> + EnableQuietBoot (PcdGetPtr(PcdLogoFile));
> + if (!SystemConfiguration.QuietBoot) {
> + PlatformBdsDiagnostics (IGNORE, FALSE, BaseMemoryTest);
> + }
> +
> + //
> + // Do a pre-delay so Hard Disk can spin up and see more logo.
> + //
> + gBS->Stall(SystemConfiguration.HddPredelay * 1000000);
> +
> + //
> + // Perform user identification
> + //
> + if (mCurrentUser == NULL) {
> + PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);
> + if (DeferredImageExist) {
> + //
> + // After user authentication, the deferred drivers was loaded again.
> + // Here, need to ensure the deferred drivers are connected.
> + //
> + Status = PlatformBdsConnectConsole (gPlatformConsole);
> + if (EFI_ERROR (Status)) {
> + PlatformBdsNoConsoleAction ();
> + }
> + PlatformBdsConnectSequence ();
> + }
> + }
> + #ifdef TPM_ENABLED
> + TcgPhysicalPresenceLibProcessRequest();
> + #endif
> + #ifdef FTPM_ENABLE
> + Tcg2PhysicalPresenceLibProcessRequest(NULL);
> + #endif
> +
> + if (EsrtManagement != NULL) {
> + EsrtManagement->SyncEsrtFmp();
> + }
> + //
> + // Close boot script and install ready to lock
> + //
> + InstallReadyToLock ();
> +
> + //
> + // Here we have enough time to do the enumeration of boot device
> + //
> + PlatformBdsLibEnumerateAllBootOption (BootOptionList);
> +
> + //
> + // Give one chance to enter the setup if we
> + // have the time out
> + //
> + PlatformBdsEnterFrontPageWithHotKey (Timeout, FALSE);
> +
> + //
> + // Give one chance to enter the setup if we
> + // select Gummiboot "Reboot Into Firmware Interface"
> + //
> + BootIntoFirmwareInterface();
> +
> + //
> + // In default boot mode, always find all boot
> + // option and do enumerate all the default boot option
> + //
> + if (Timeout == 0) {
> + BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder");
> + if (IsListEmpty(BootOptionList)) {
> + PlatformBdsPredictBootOption (BootOptionList);
> + }
> +
> + return;
> + }
> +
> +
> + break;
> + }
> +
> +
> + IsFirstBoot = PcdGetBool(PcdBootState);
> + if (IsFirstBoot) {
> + PcdSetBool(PcdBootState, FALSE);
> + }
> + return;
> +
> +}
> +
> +/**
> + Hook point after a boot attempt succeeds. We don't expect a boot option
> to
> + return, so the UEFI 2.0 specification defines that you will default to an
> + interactive mode and stop processing the BootOrder list in this case. This
> + is alos a platform implementation and can be customized by IBV/OEM.
> +
> + @param Option Pointer to Boot Option that succeeded to boot.
> +
> + @retval None.
> +
> +**/
> +VOID
> +EFIAPI
> +PlatformBdsBootSuccess (
> + IN BDS_COMMON_OPTION *Option
> + )
> +{
> + CHAR16 *TmpStr;
> +
> + //
> + // If Boot returned with EFI_SUCCESS and there is not in the boot device
> + // select loop then we need to pop up a UI and wait for user input.
> + //
> + TmpStr = Option->StatusString;
> + if (TmpStr != NULL) {
> + BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r",
> NULL);
> + FreePool(TmpStr);
> + }
> +}
> +
> +/**
> + Hook point after a boot attempt fails.
> +
> + @param Option - Pointer to Boot Option that failed to boot.
> + @param Status - Status returned from failed boot.
> + @param ExitData - Exit data returned from failed boot.
> + @param ExitDataSize - Exit data size returned from failed boot.
> +
> + @retval None.
> +
> +**/
> +VOID
> +EFIAPI
> +PlatformBdsBootFail (
> + IN BDS_COMMON_OPTION *Option,
> + IN EFI_STATUS Status,
> + IN CHAR16 *ExitData,
> + IN UINTN ExitDataSize
> + )
> +{
> + CHAR16 *TmpStr;
> + EFI_HANDLE FvProtocolHandle;
> +
> + //
> + // If Boot returned with failed status then we need to pop up a UI and wait
> + // for user input.
> + //
> + TmpStr = Option->StatusString;
> + if (TmpStr != NULL) {
> + BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r",
> NULL);
> + FreePool(TmpStr);
> + }
> + if (PcdGet32(PcdFlashFvShellSize) > 0){
> + gDS->ProcessFirmwareVolume (
> + (VOID *)(UINTN)PcdGet32(PcdFlashFvShellBase),
> + PcdGet32(PcdFlashFvShellSize),
> + &FvProtocolHandle
> + );
> + }
> + PlatformBdsConnectSequence ();
> +}
> +
> +/**
> + This function is remained for IBV/OEM to do some platform action,
> + if there no console device can be connected.
> +
> + @param None.
> +
> + @retval EFI_SUCCESS Direct return success now.
> +
> +**/
> +EFI_STATUS
> +PlatformBdsNoConsoleAction (
> + VOID
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function locks the block
> +
> + @param Base The base address flash region to be locked.
> +
> +**/
> +VOID
> +BdsLockFv (
> + IN EFI_PHYSICAL_ADDRESS Base
> + )
> +{
> + EFI_FV_BLOCK_MAP_ENTRY *BlockMap;
> + EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
> + EFI_PHYSICAL_ADDRESS BaseAddress;
> + UINT32 BlockLength;
> + UINTN Index;
> +
> + BaseAddress = Base - 0x400000 + 2;
> + FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) ((UINTN) (Base));
> + BlockMap = &(FvHeader->BlockMap[0]);
> +
> + while ((BlockMap->NumBlocks != 0) && (BlockMap->Length != 0)) {
> + BlockLength = BlockMap->Length;
> + for (Index = 0; Index < BlockMap->NumBlocks; Index++) {
> + MmioOr8 ((UINTN) BaseAddress, 0x03);
> + BaseAddress += BlockLength;
> + }
> + BlockMap++;
> + }
> +}
> +
> +VOID
> +EFIAPI
> +PlatformBdsLockNonUpdatableFlash (
> + VOID
> + )
> +{
> + EFI_PHYSICAL_ADDRESS Base;
> +
> + Base = (EFI_PHYSICAL_ADDRESS) PcdGet32 (PcdFlashFvMainBase);
> + if (Base > 0) {
> + BdsLockFv (Base);
> + }
> +
> + Base = (EFI_PHYSICAL_ADDRESS) PcdGet32 (PcdFlashFvRecoveryBase);
> + if (Base > 0) {
> + BdsLockFv (Base);
> + }
> +}
> +
> +/**
> + Lock the ConsoleIn device in system table. All key
> + presses will be ignored until the Password is typed in. The only way to
> + disable the password is to type it in to a ConIn device.
> +
> + @param Password Password used to lock ConIn device.
> +
> + @retval EFI_SUCCESS lock the Console In Spliter virtual handle
> successfully.
> + @retval EFI_UNSUPPORTED Password not found
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LockKeyboards (
> + IN CHAR16 *Password
> + )
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Connect the predefined platform default authentication devices.
> +
> + This function connects the predefined device path for authentication
> device,
> + and if the predefined device path has child device path, the child handle
> will
> + be connected too. But the child handle of the child will not be connected.
> +
> +**/
> +VOID
> +EFIAPI
> +PlatformBdsConnectAuthDevice (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> + UINTN HandleIndex;
> + UINTN HandleCount;
> + EFI_HANDLE *HandleBuffer;
> + EFI_DEVICE_PATH_PROTOCOL *ChildDevicePath;
> + EFI_USER_MANAGER_PROTOCOL *Manager;
> +
> + Status = gBS->LocateProtocol (
> + &gEfiUserManagerProtocolGuid,
> + NULL,
> + (VOID **) &Manager
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + // As user manager protocol is not installed, the authentication devices
> + // should not be connected.
> + //
> + return ;
> + }
> +
> + Index = 0;
> + while (gUserAuthenticationDevice[Index] != NULL) {
> + //
> + // Connect the platform customized device paths
> + //
> + BdsLibConnectDevicePath (gUserAuthenticationDevice[Index]);
> + Index++;
> + }
> +
> + //
> + // Find and connect the child device paths of the platform customized
> device paths
> + //
> + HandleBuffer = NULL;
> + for (Index = 0; gUserAuthenticationDevice[Index] != NULL; Index++) {
> + HandleCount = 0;
> + Status = gBS->LocateHandleBuffer (
> + AllHandles,
> + NULL,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> + ASSERT (!EFI_ERROR (Status));
> +
> + //
> + // Find and connect the child device paths of
> gUserIdentificationDevice[Index]
> + //
> + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {
> + ChildDevicePath = NULL;
> + Status = gBS->HandleProtocol (
> + HandleBuffer[HandleIndex],
> + &gEfiDevicePathProtocolGuid,
> + (VOID **) &ChildDevicePath
> + );
> + if (EFI_ERROR (Status) || ChildDevicePath == NULL) {
> + continue;
> + }
> +
> + if (CompareMem (
> + ChildDevicePath,
> + gUserAuthenticationDevice[Index],
> + (GetDevicePathSize (gUserAuthenticationDevice[Index]) - sizeof
> (EFI_DEVICE_PATH_PROTOCOL))
> + ) != 0) {
> + continue;
> + }
> + gBS->ConnectController (
> + HandleBuffer[HandleIndex],
> + NULL,
> + NULL,
> + TRUE
> + );
> + }
> + }
> +
> + if (HandleBuffer != NULL) {
> + FreePool (HandleBuffer);
> + }
> +}
> +
> +/**
> + This function is to identify a user, and return whether deferred images
> exist.
> +
> + @param[out] User Point to user profile handle.
> + @param[out] DeferredImageExist On return, points to TRUE if the
> deferred image
> + exist or FALSE if it did not exist.
> +
> +**/
> +VOID
> +EFIAPI
> +PlatformBdsUserIdentify (
> + OUT EFI_USER_PROFILE_HANDLE *User,
> + OUT BOOLEAN *DeferredImageExist
> + )
> +{
> + EFI_STATUS Status;
> + EFI_DEFERRED_IMAGE_LOAD_PROTOCOL *DeferredImage;
> + UINTN HandleCount;
> + EFI_HANDLE *HandleBuf;
> + UINTN Index;
> + UINTN DriverIndex;
> + EFI_DEVICE_PATH_PROTOCOL *ImageDevicePath;
> + VOID *DriverImage;
> + UINTN ImageSize;
> + BOOLEAN BootOption;
> +
> + //
> + // Perform user identification
> + //
> + do {
> + Status = BdsLibUserIdentify (User);
> + } while (EFI_ERROR (Status));
> +
> + //
> + // After user authentication now, try to find whether deferred image
> exists
> + //
> + HandleCount = 0;
> + HandleBuf = NULL;
> + *DeferredImageExist = FALSE;
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiDeferredImageLoadProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuf
> + );
> + if (EFI_ERROR (Status)) {
> + return ;
> + }
> +
> + for (Index = 0; Index < HandleCount; Index++) {
> + Status = gBS->HandleProtocol (
> + HandleBuf[Index],
> + &gEfiDeferredImageLoadProtocolGuid,
> + (VOID **) &DeferredImage
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Find whether deferred image exists in this instance.
> + //
> + DriverIndex = 0;
> + Status = DeferredImage->GetImageInfo(
> + DeferredImage,
> + DriverIndex,
> + &ImageDevicePath,
> + (VOID **) &DriverImage,
> + &ImageSize,
> + &BootOption
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // The deferred image is found.
> + //
> + FreePool (HandleBuf);
> + *DeferredImageExist = TRUE;
> + return ;
> + }
> + }
> + }
> +
> + FreePool (HandleBuf);
> +}
> +
> +UINTN gHotKey = 0;
> +
> +
> +EFI_STATUS
> +ShowProgressHotKey (
> + IN UINT16 TimeoutDefault
> + )
> +{
> + CHAR16 *TmpStr;
> + UINT16 TimeoutRemain;
> + EFI_STATUS Status;
> + EFI_INPUT_KEY Key;
> + EFI_GRAPHICS_OUTPUT_BLT_PIXEL Foreground;
> + EFI_GRAPHICS_OUTPUT_BLT_PIXEL Background;
> + EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color;
> + UINT32 GpioValue;
> + CHAR16 *TmpStr1;
> + CHAR16 *TmpStr2;
> + CHAR16 *TmpStr3;
> + UINTN TmpStrSize;
> + VOID *Buffer;
> + UINTN Size;
> +
> + if (TimeoutDefault == 0) {
> + return EFI_TIMEOUT;
> + }
> +
> + gST->ConOut->SetAttribute(gST->ConOut, EFI_TEXT_ATTR
> (EFI_LIGHTGRAY, EFI_BLACK));
> +
> + if (DebugAssertEnabled())
> + {
> + DEBUG ((EFI_D_INFO, "\n\nStart showing progress bar... Press any key to
> stop it, or press <F2> or <DEL> to enter setup page! ...Zzz....\n"));
> + }
> + else
> + {
> + #ifdef __GNUC__
> + SerialPortWrite((UINT8 *)"\n\n>>>>Start boot option, Press <F2> or <DEL>
> to enter setup page(5 Sec)[GCC]", 76);
> + #else
> + SerialPortWrite((UINT8 *)"\n\n>>>>Start boot option, Press <F2> or <DEL>
> to enter setup page(5 Sec)", 71);
> + #endif
> + }
> + SetMem (&Foreground, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);
> + SetMem (&Background, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0);
> + SetMem (&Color, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);
> +
> + TmpStr2 = NULL;
> + TmpStr3 = NULL;
> +
> + //
> + // Check if the platform is using test key.
> + //
> + Status = GetSectionFromAnyFv(
> + PcdGetPtr(PcdEdkiiRsa2048Sha256TestPublicKeyFileGuid),
> + EFI_SECTION_RAW,
> + 0,
> + &Buffer,
> + &Size
> + );
> + if (!EFI_ERROR(Status)) {
> + if ((Size == PcdGetSize(PcdRsa2048Sha256PublicKeyBuffer)) &&
> + (CompareMem(Buffer, PcdGetPtr(PcdRsa2048Sha256PublicKeyBuffer),
> Size) == 0)) {
> + TmpStr2 = L"WARNING: Recovery Test Key is used.\r\n";
> + if (DebugAssertEnabled()) {
> + DEBUG ((DEBUG_INFO, "\n\nWARNING: Recovery Test Key is
> used.\n"));
> + } else {
> + SerialPortWrite((UINT8 *)"\n\nWARNING: Recovery Test Key is used.",
> sizeof("\n\nWARNING: Recovery Test Key is used."));
> + }
> + PcdSetBoolS(PcdTestKeyUsed, TRUE);
> + }
> + FreePool(Buffer);
> + }
> + Status = GetSectionFromAnyFv(
> + PcdGetPtr(PcdEdkiiPkcs7TestPublicKeyFileGuid),
> + EFI_SECTION_RAW,
> + 0,
> + &Buffer,
> + &Size
> + );
> + if (!EFI_ERROR(Status)) {
> + if ((Size == PcdGetSize(PcdPkcs7CertBuffer)) &&
> + (CompareMem(Buffer, PcdGetPtr(PcdPkcs7CertBuffer), Size) == 0)) {
> + TmpStr3 = L"WARNING: Capsule Test Key is used.\r\n";
> + if (DebugAssertEnabled()) {
> + DEBUG ((DEBUG_INFO, "\n\nWARNING: Capsule Test Key is
> used.\r\n"));
> + } else {
> + SerialPortWrite((UINT8 *)"\n\nWARNING: Capsule Test Key is used.",
> sizeof("\n\nWARNING: Capsule Test Key is used."));
> + }
> + PcdSetBoolS(PcdTestKeyUsed, TRUE);
> + }
> + FreePool(Buffer);
> + }
> +
> + //
> + // Clear the progress status bar first
> + //
> + TmpStr1 = L"Start boot option, Press <F2> or <DEL> to enter setup
> page.\r\n";
> + TmpStrSize = StrSize(TmpStr1);
> + if (TmpStr2 != NULL) {
> + TmpStrSize += StrSize(TmpStr2);
> + }
> + if (TmpStr3 != NULL) {
> + TmpStrSize += StrSize(TmpStr3);
> + }
> + TmpStr = AllocatePool (TmpStrSize);
> + if (TmpStr == NULL) {
> + TmpStr = TmpStr1;
> + } else {
> + StrCpyS(TmpStr, TmpStrSize/sizeof(CHAR16), TmpStr1);
> + if (TmpStr2 != NULL) {
> + StrCatS(TmpStr, TmpStrSize/sizeof(CHAR16), TmpStr2);
> + }
> + if (TmpStr3 != NULL) {
> + StrCatS(TmpStr, TmpStrSize/sizeof(CHAR16), TmpStr3);
> + }
> + }
> + PlatformBdsShowProgress (Foreground, Background, TmpStr, Color, 0, 0);
> +
> + TimeoutRemain = TimeoutDefault;
> + while (TimeoutRemain != 0) {
> + if (DebugAssertEnabled())
> + {
> + DEBUG ((EFI_D_INFO, "Showing progress bar...Remaining %d second!\n",
> TimeoutRemain));
> + }
> + else
> + {
> + SerialPortWrite ((UINT8 *)".", 1);
> + }
> + Status = WaitForSingleEvent (gST->ConIn->WaitForKey, ONE_SECOND);
> + if (Status != EFI_TIMEOUT) {
> + break;
> + }
> + TimeoutRemain--;
> +
> + //
> + // Show progress
> + //
> + if (TmpStr != NULL) {
> + PlatformBdsShowProgress (
> + Foreground,
> + Background,
> + TmpStr,
> + Color,
> + ((TimeoutDefault - TimeoutRemain) * 100 / TimeoutDefault),
> + 0
> + );
> + }
> + }
> +
> + //
> + // Timeout expired
> + //
> + if (TimeoutRemain == 0) {
> + if (DebugAssertEnabled())
> + {
> + }
> + else
> + {
> + SerialPortWrite ((UINT8 *)"\r\n", 2);
> + }
> + return EFI_TIMEOUT;
> + }
> +
> + //
> + // User pressed some key
> + //
> + Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Check Volume Up Key to enter Setup
> + //
> + GpioValue = MmioRead32 (IO_BASE_ADDRESS + 0x0668); // The value of
> GPIOC_5
> + if (((GpioValue & BIT0) == 0) && (Key.ScanCode == SCAN_UP)) {
> + gHotKey = 0;
> + return EFI_SUCCESS;
> + }
> +
> + if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {
> + //
> + // User pressed enter, equivalent to select "continue"
> + //
> + return EFI_TIMEOUT;
> + }
> +
> + //
> + //F2 -- Front Page
> + //F5 -- Device Manager
> + //F7 -- Boot Manager
> + // do not use F8. generally people assume it is windows safe mode key.
> + //F9 -- Boot order
> + //
> + DEBUG ((EFI_D_INFO, "[Key Pressed]: ScanCode 0x%x\n", Key.ScanCode));
> + switch(Key.ScanCode) {
> + case SCAN_F2:
> + gHotKey = 0;
> + break;
> +
> + case SCAN_DELETE:
> + gHotKey = 0;
> + break;
> +
> + case SCAN_F5:
> + gHotKey = FRONT_PAGE_KEY_DEVICE_MANAGER;
> + break;
> +
> + case SCAN_F7:
> + gHotKey = FRONT_PAGE_KEY_BOOT_MANAGER;
> + break;
> +
> + case SCAN_F9:
> + gHotKey = FRONT_PAGE_KEY_BOOT_MAINTAIN;
> + break;
> +
> + default:
> + //set gHotKey to continue so that flow will not go into CallFrontPage
> + gHotKey = FRONT_PAGE_KEY_CONTINUE;
> + return EFI_TIMEOUT;
> + break;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +
> +/**
> + This function is the main entry of the platform setup entry.
> + The function will present the main menu of the system setup,
> + this is the platform reference part and can be customize.
> +
> +
> + @param TimeoutDefault The fault time out value before the system
> + continue to boot.
> + @param ConnectAllHappened The indicater to check if the connect all
> have
> + already happened.
> +
> +**/
> +VOID
> +PlatformBdsEnterFrontPageWithHotKey (
> + IN UINT16 TimeoutDefault,
> + IN BOOLEAN ConnectAllHappened
> + )
> +{
> + EFI_STATUS Status;
> +
> + EFI_STATUS LogoStatus;
> + EFI_BOOT_LOGO_PROTOCOL *BootLogo;
> + EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;
> + EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *SimpleTextOut;
> + UINTN BootTextColumn;
> + UINTN BootTextRow;
> +
> + GraphicsOutput = NULL;
> + SimpleTextOut = NULL;
> +
> + PERF_START (NULL, "BdsTimeOut", "BDS", 0);
> +
> + //
> + // Indicate if we need connect all in the platform setup
> + //
> + if (ConnectAllHappened) {
> + gConnectAllHappened = TRUE;
> + }
> +
> + if (!mModeInitialized) {
> + //
> + // After the console is ready, get current video resolution
> + // and text mode before launching setup at first time.
> + //
> + Status = gBS->HandleProtocol (
> + gST->ConsoleOutHandle,
> + &gEfiGraphicsOutputProtocolGuid,
> + (VOID**)&GraphicsOutput
> + );
> + if (EFI_ERROR (Status)) {
> + GraphicsOutput = NULL;
> + }
> +
> + Status = gBS->HandleProtocol (
> + gST->ConsoleOutHandle,
> + &gEfiSimpleTextOutProtocolGuid,
> + (VOID**)&SimpleTextOut
> + );
> + if (EFI_ERROR (Status)) {
> + SimpleTextOut = NULL;
> + }
> +
> + if (GraphicsOutput != NULL) {
> + //
> + // Get current video resolution and text mode.
> + //
> + mBootHorizontalResolution = GraphicsOutput->Mode->Info-
> >HorizontalResolution;
> + mBootVerticalResolution = GraphicsOutput->Mode->Info-
> >VerticalResolution;
> + }
> +
> + if (SimpleTextOut != NULL) {
> + Status = SimpleTextOut->QueryMode (
> + SimpleTextOut,
> + SimpleTextOut->Mode->Mode,
> + &BootTextColumn,
> + &BootTextRow
> + );
> + mBootTextModeColumn = (UINT32)BootTextColumn;
> + mBootTextModeRow = (UINT32)BootTextRow;
> + }
> +
> + //
> + // Get user defined text mode for setup.
> + //
> + mSetupHorizontalResolution = PcdGet32
> (PcdSetupVideoHorizontalResolution);
> + mSetupVerticalResolution = PcdGet32
> (PcdSetupVideoVerticalResolution);
> + mSetupTextModeColumn = PcdGet32 (PcdSetupConOutColumn);
> + mSetupTextModeRow = PcdGet32 (PcdSetupConOutRow);
> +
> + mModeInitialized = TRUE;
> + }
> +
> + if (TimeoutDefault != 0xffff) {
> + Status = ShowProgressHotKey (TimeoutDefault);
> +
> + //
> + // Ensure screen is clear when switch Console from Graphics mode to
> Text mode
> + //
> + gST->ConOut->EnableCursor (gST->ConOut, TRUE);
> + gST->ConOut->ClearScreen (gST->ConOut);
> +
> + //
> + // Boot Logo is corrupted, report it using Boot Logo protocol.
> + //
> + LogoStatus = gBS->LocateProtocol (&gEfiBootLogoProtocolGuid, NULL,
> (VOID **) &BootLogo);
> + if (!EFI_ERROR (LogoStatus) && (BootLogo != NULL)) {
> + BootLogo->SetBootLogo (BootLogo, NULL, 0, 0, 0, 0);
> + }
> +
> + if (EFI_ERROR (Status)) {
> + //
> + // Timeout or user press enter to continue
> + //
> + goto Exit;
> + }
> + }
> +
> + //
> + // Install BM HiiPackages.
> + // Keep BootMaint HiiPackage, so that it can be covered by global setting.
> + //
> + InitBMPackage ();
> + do {
> +
> + BdsSetConsoleMode (TRUE);
> +
> + InitializeFrontPage (FALSE);
> +
> + //
> + // Update Front Page strings
> + //
> + UpdateFrontPageStrings ();
> +
> + Status = EFI_SUCCESS;
> + gCallbackKey = 0;
> + if (gHotKey == 0) {
> + Status = CallFrontPage ();
> + } else {
> + gCallbackKey = gHotKey;
> + gHotKey = 0;
> + }
> +
> + //
> + // If gCallbackKey is greater than 1 and less or equal to 5,
> + // it will launch configuration utilities.
> + // 2 = set language
> + // 3 = boot manager
> + // 4 = device manager
> + // 5 = boot maintenance manager
> + //
> + if (gCallbackKey != 0) {
> + REPORT_STATUS_CODE (
> + EFI_PROGRESS_CODE,
> + (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_PC_USER_SETUP)
> + );
> + }
> +
> + //
> + // Based on the key that was set, we can determine what to do
> + //
> + switch (gCallbackKey) {
> + //
> + // The first 4 entries in the Front Page are to be GUARANTEED to remain
> constant so IHV's can
> + // describe to their customers in documentation how to find their setup
> information (namely
> + // under the device manager and specific buckets)
> + //
> + // These entries consist of the Continue, Select language, Boot Manager,
> and Device Manager
> + //
> + case FRONT_PAGE_KEY_CONTINUE:
> +
> + //
> + // User hit continue
> + //
> + break;
> +
> + case FRONT_PAGE_KEY_LANGUAGE:
> +
> + //
> + // User made a language setting change - display front page again
> + //
> + break;
> +
> + case FRONT_PAGE_KEY_BOOT_MANAGER:
> + //
> + // Remove the installed BootMaint HiiPackages when exit.
> + //
> + FreeBMPackage ();
> +
> + //
> + // User chose to run the Boot Manager
> + //
> + CallBootManager ();
> +
> + //
> + // Reinstall BootMaint HiiPackages after exiting from Boot Manager.
> + //
> + InitBMPackage ();
> + break;
> +
> + case FRONT_PAGE_KEY_DEVICE_MANAGER:
> +
> + //
> + // Display the Device Manager
> + //
> + do {
> + CallDeviceManager ();
> + } while (gCallbackKey == FRONT_PAGE_KEY_DEVICE_MANAGER);
> + break;
> +
> + case FRONT_PAGE_KEY_BOOT_MAINTAIN:
> +
> + //
> + // Display the Boot Maintenance Manager
> + //
> + BdsStartBootMaint ();
> + break;
> + }
> +
> + } while (((UINTN)gCallbackKey) != FRONT_PAGE_KEY_CONTINUE);
> +
> + //
> + //Will leave browser, check any reset required change is applied? if yes,
> reset system
> + //
> + SetupResetReminder ();
> + //
> + // Remove the installed BootMaint HiiPackages when exit.
> + //
> + FreeBMPackage ();
> +
> +Exit:
> + //
> + // Automatically load current entry
> + // Note: The following lines of code only execute when Auto boot
> + // takes affect
> + //
> + PERF_END (NULL, "BdsTimeOut", "BDS", 0);
> +}
> +
> +
> +VOID
> +BootIntoFirmwareInterface(
> +VOID
> +)
> +{
> + EFI_STATUS Status;
> + UINTN DataSize;
> + UINT16 Timeout;
> + UINT64 OsIndication;
> +
> +
> + OsIndication = 0;
> + DataSize = sizeof(UINT64);
> + Status = gRT->GetVariable (
> + L"OsIndications",
> + &gEfiGlobalVariableGuid,
> + NULL,
> + &DataSize,
> + &OsIndication
> + );
> +
> + DEBUG ((EFI_D_INFO, "OSIndication Variable Value %d\n", OsIndication));
> + //
> + //Goto FrontPage directly when bit
> EFI_OS_INDICATIONS_BOOT_TO_FW_UI in OSIndication Variable is setted.
> + //
> + if (!EFI_ERROR(Status) && (OsIndication != 0)) {
>
> + Timeout = 0xffff;
> + PlatformBdsEnterFrontPage (Timeout, FALSE);
> + }
> +}
> +
> +
> +EFI_STATUS
> +PlatformBdsConnectSimpleConsole (
> + IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole
> +)
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> + EFI_DEVICE_PATH_PROTOCOL *VarConout;
> + EFI_DEVICE_PATH_PROTOCOL *VarConin;
> + UINTN DevicePathSize;
> +
> +
> + Index = 0;
> + Status = EFI_SUCCESS;
> + DevicePathSize = 0;
> + VarConout = BdsLibGetVariableAndSize (
> + L"ConOut",
> + &gEfiGlobalVariableGuid,
> + &DevicePathSize
> + );
> + VarConin = BdsLibGetVariableAndSize (
> + L"ConIn",
> + &gEfiGlobalVariableGuid,
> + &DevicePathSize
> + );
> + if (VarConout == NULL || VarConin == NULL) {
> + //
> + // Have chance to connect the platform default console,
> + // the platform default console is the minimum device group
> + // the platform should support
> + //
> + while (PlatformConsole[Index].DevicePath != NULL) {
> +
> + //
> + // Update the console variable with the connect type
> + //
> + if ((PlatformConsole[Index].ConnectType & CONSOLE_IN) ==
> CONSOLE_IN) {
> + BdsLibUpdateConsoleVariable (L"ConIn",
> PlatformConsole[Index].DevicePath, NULL);
> + }
> +
> + if ((PlatformConsole[Index].ConnectType & CONSOLE_OUT) ==
> CONSOLE_OUT) {
> + BdsLibUpdateConsoleVariable (L"ConOut",
> PlatformConsole[Index].DevicePath, NULL);
> + }
> +
> + if ((PlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR)
> {
> + BdsLibUpdateConsoleVariable (L"ErrOut",
> PlatformConsole[Index].DevicePath, NULL);
> + }
> +
> + Index ++;
> + }
> + }
> +
> + //
> + // Connect ConIn first to give keyboard time to parse hot key event.
> + //
> + Status = BdsLibConnectConsoleVariable (L"ConIn");
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Make sure we have at least one active VGA, and have the right
> + // active VGA in console variable
> + //
> + Status = PlatformBdsForceActiveVga ();
> +
> + //
> + // It seems impossible not to have any ConOut device on platform,
> + // so we check the status here.
> + //
> + Status = BdsLibConnectConsoleVariable (L"ConOut");
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Timer handler to convert the key from USB.
> +
> + @param Event Indicates the event that invoke this function.
> + @param Context Indicates the calling context.
> +**/
> +VOID
> +EFIAPI
> +HotKeyTimerHandler (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> + EFI_INPUT_KEY Key;
> +
> + Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
> + if (EFI_ERROR (Status)) {
> + return;
> + }
> +
> + switch(Key.ScanCode) {
> + case SCAN_F2:
> + gHotKey = 0;
> + mHotKeyPressed = TRUE;
> + break;
> +
> + case SCAN_F5:
> + gHotKey = FRONT_PAGE_KEY_DEVICE_MANAGER;
> + mHotKeyPressed = TRUE;
> + break;
> +
> + case SCAN_F7:
> + gHotKey = FRONT_PAGE_KEY_BOOT_MANAGER;
> + mHotKeyPressed = TRUE;
> + break;
> +
> + case SCAN_F9:
> + gHotKey = FRONT_PAGE_KEY_BOOT_MAINTAIN;
> + mHotKeyPressed = TRUE;
> + break;
> + }
> +
> + if (mHotKeyPressed) {
> + gBS->SetTimer (
> + mHotKeyTimerEvent,
> + TimerCancel,
> + 0
> + );
> + gBS->CloseEvent (mHotKeyTimerEvent);
> + mHotKeyTimerEvent = NULL;
> + }
> +
> + return;
> +}
> +
> +
> +/**
> + Callback function for SimpleTextInEx protocol install events
> +
> + @param Event the event that is signaled.
> + @param Context not used here.
> +
> +**/
> +VOID
> +EFIAPI
> +HitHotkeyEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = gBS->CloseEvent(mHitHotkeyEvent);
> + if (EFI_ERROR (Status)) {
> + return;
> + }
> + Status = gBS->CreateEvent (
> + EVT_TIMER | EVT_NOTIFY_SIGNAL,
> + TPL_NOTIFY,
> + HotKeyTimerHandler,
> + NULL,
> + &mHotKeyTimerEvent
> + );
> + if (EFI_ERROR (Status)) {
> + return;
> + }
> + Status = gBS->SetTimer (
> + mHotKeyTimerEvent,
> + TimerPeriodic,
> + KEYBOARD_TIMER_INTERVAL
> + );
> + if (EFI_ERROR (Status)) {
> + return;
> + }
> +
> + return;
> +}
> +
> +
> +VOID
> +EFIAPI
> +PlatformBdsInitHotKeyEvent (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> +
> + //
> + // Register Protocol notify for Hotkey service
> + //
> + Status = gBS->CreateEvent (
> + EVT_NOTIFY_SIGNAL,
> + TPL_CALLBACK,
> + HitHotkeyEvent,
> + NULL,
> + &mHitHotkeyEvent
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Register for protocol notifications on this event
> + //
> + Status = gBS->RegisterProtocolNotify (
> + &gEfiSimpleTextInputExProtocolGuid,
> + mHitHotkeyEvent,
> + &mHitHotkeyRegistration
> + );
> + ASSERT_EFI_ERROR (Status);
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.h
> new file mode 100644
> index 0000000000..b5bb519747
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.h
> @@ -0,0 +1,516 @@
> +/*++
> +
> + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + BdsPlatform.h
> +
> +Abstract:
> +
> + Head file for BDS Platform specific code
> +
> +--*/
> +
> +#ifndef _BDS_PLATFORM_H
> +#define _BDS_PLATFORM_H
> +
> +#include <FrameworkDxe.h>
> +
> +#include <Protocol/FirmwareVolume2.h>
> +#include <Protocol/DevicePath.h>
> +#include <Protocol/SimpleNetwork.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include <Protocol/LoadFile.h>
> +#include <Protocol/LegacyBios.h>
> +#include <Protocol/PciIo.h>
> +#include <Protocol/SmmAccess2.h>
> +#include <Protocol/DxeSmmReadyToLock.h>
> +#include <Protocol/UserManager.h>
> +#include <Protocol/DeferredImageLoad.h>
> +#include <Protocol/AcpiS3Save.h>
> +#include <Protocol/ExitPmAuth.h>
> +#include <Protocol/MmioDevice.h>
> +#include <Protocol/I2cBusMcg.h>
> +#include <Protocol/I2cHostMcg.h>
> +#include <Guid/CapsuleVendor.h>
> +#include <Guid/MemoryTypeInformation.h>
> +#include <Guid/GlobalVariable.h>
> +#include <Guid/DebugAgentGuid.h>
> +
> +
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/GenericBdsLib.h>
> +#include <Library/PlatformBdsLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/PerformanceLib.h>
> +#include <Library/ReportStatusCodeLib.h>
> +
> +#include <IndustryStandard/Pci.h>
> +
> +extern EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges [];
> +extern BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole [];
> +extern EFI_DEVICE_PATH_PROTOCOL *gPlatformAllPossiblePciVgaConsole
> [];
> +extern EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence [];
> +extern EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption [];
> +extern EFI_DEVICE_PATH_PROTOCOL *gPlatformBootOption [];
> +extern EFI_DEVICE_PATH_PROTOCOL *gUserAuthenticationDevice[];
> +extern BDS_CONSOLE_CONNECT_ENTRY gPlatformSimpleConsole [];
> +extern EFI_DEVICE_PATH_PROTOCOL *gPlatformSimpleBootOption [];
> +
> +extern BOOLEAN mEnumBootDevice;
> +
> +
> +//
> +// the short form device path for Usb keyboard
> +//
> +#define CLASS_HID 3
> +#define SUBCLASS_BOOT 1
> +#define PROTOCOL_KEYBOARD 1
> +
> +#define PCI_DEVICE_PATH_NODE(Func, Dev) \
> + { \
> + HARDWARE_DEVICE_PATH, \
> + HW_PCI_DP, \
> + { \
> + (UINT8) (sizeof (PCI_DEVICE_PATH)), \
> + (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \
> + }, \
> + (Func), \
> + (Dev) \
> + }
> +
> +#define PNPID_DEVICE_PATH_NODE(PnpId) \
> + { \
> + { \
> + ACPI_DEVICE_PATH, \
> + ACPI_DP, \
> + { \
> + (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
> + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
> + } \
> + }, \
> + EISA_PNP_ID((PnpId)), \
> + 0 \
> + }
> +
> +#define gUart(BaudRate, DataBits, Parity, StopBits) \
> + { \
> + { \
> + MESSAGING_DEVICE_PATH, \
> + MSG_UART_DP, \
> + { \
> + (UINT8) (sizeof (UART_DEVICE_PATH)), \
> + (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \
> + } \
> + }, \
> + 0, \
> + (BaudRate), \
> + (DataBits), \
> + (Parity), \
> + (StopBits) \
> + }
> +
> +#define gPcAnsiTerminal \
> + { \
> + { \
> + MESSAGING_DEVICE_PATH, \
> + MSG_VENDOR_DP, \
> + { \
> + (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
> + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
> + } \
> + }, \
> + DEVICE_PATH_MESSAGING_PC_ANSI \
> + }
> +
> +#define gUsbKeyboardMouse \
> + { \
> + { \
> + MESSAGING_DEVICE_PATH, \
> + MSG_USB_CLASS_DP, \
> + (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)), \
> + (UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8) \
> + }, \
> + 0xffff, \
> + 0xffff, \
> + CLASS_HID, \
> + SUBCLASS_BOOT, \
> + PROTOCOL_KEYBOARD \
> + }
> +
> +#define gEndEntire \
> + { \
> + END_DEVICE_PATH_TYPE, \
> + END_ENTIRE_DEVICE_PATH_SUBTYPE, \
> + { \
> + END_DEVICE_PATH_LENGTH, \
> + 0 \
> + } \
> + }
> +
> +#define gPciRootBridge \
> + PNPID_DEVICE_PATH_NODE(0x0A03)
> +
> +#define gPnpPs2Keyboard \
> + PNPID_DEVICE_PATH_NODE(0x0303)
> +
> +#define gPnp16550ComPort \
> + PNPID_DEVICE_PATH_NODE(0x0501)
> +
> +#define gPciePort0Bridge \
> + PCI_DEVICE_PATH_NODE(0, 0x1C)
> +
> +#define gPciePort1Bridge \
> + PCI_DEVICE_PATH_NODE(1, 0x1C)
> +
> +#define gPciePort2Bridge \
> + PCI_DEVICE_PATH_NODE(2, 0x1C)
> +
> +#define gPciePort3Bridge \
> + PCI_DEVICE_PATH_NODE(3, 0x1C)
> +
> +#define gPciIsaBridge \
> + PCI_DEVICE_PATH_NODE(0, 0x1f)
> +
> +//
> +// Platform Root Bridge
> +//
> +typedef struct {
> + ACPI_HID_DEVICE_PATH PciRootBridge;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;
> +
> +//
> +// Below is the platform console device path
> +//
> +typedef struct {
> + ACPI_HID_DEVICE_PATH PciRootBridge;
> + PCI_DEVICE_PATH IsaBridge;
> + ACPI_HID_DEVICE_PATH Keyboard;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} PLATFORM_ISA_KEYBOARD_DEVICE_PATH;
> +
> +typedef struct {
> + VENDOR_DEVICE_PATH VendorDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} HII_VENDOR_DEVICE_PATH;
> +
> +typedef struct {
> + USB_CLASS_DEVICE_PATH UsbClass;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} USB_CLASS_FORMAT_DEVICE_PATH;
> +
> +typedef struct {
> + ACPI_HID_DEVICE_PATH PciRootBridge;
> + PCI_DEVICE_PATH OnboardVga;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} PLATFORM_ONBOARD_VGA_DEVICE_PATH;
> +
> +typedef struct {
> + ACPI_HID_DEVICE_PATH PciRootBridge;
> + PCI_DEVICE_PATH AgpBridge;
> + PCI_DEVICE_PATH AgpDevice;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} PLATFORM_OFFBOARD_VGA_DEVICE_PATH;
> +
> +typedef struct {
> + ACPI_HID_DEVICE_PATH PciRootBridge;
> + PCI_DEVICE_PATH IsaBridge;
> + ACPI_HID_DEVICE_PATH IsaSerial;
> + UART_DEVICE_PATH Uart;
> + VENDOR_DEVICE_PATH TerminalType;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} PLATFORM_ISA_SERIAL_DEVICE_PATH;
> +
> +//
> +// Below is the boot option device path
> +//
> +typedef struct {
> + BBS_BBS_DEVICE_PATH LegacyHD;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} LEGACY_HD_DEVICE_PATH;
> +
> +//
> +// Below is the platform IDE device path
> +//
> +typedef struct {
> + ACPI_HID_DEVICE_PATH PciRootBridge;
> + PCI_DEVICE_PATH IsaBridge;
> + ATAPI_DEVICE_PATH Ide;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} PLATFORM_IDE_DEVICE_PATH;
> +
> +//
> +// Floppy device path definition
> +//
> +typedef struct {
> + ACPI_HID_DEVICE_PATH PciRootBridge;
> + PCI_DEVICE_PATH IsaBridge;
> + ACPI_HID_DEVICE_PATH Floppy;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} PLATFORM_FLOPPY_DEVICE_PATH;
> +
> +//
> +// Below is the platform USB controller device path for
> +// USB disk as user authentication device.
> +//
> +typedef struct {
> + ACPI_HID_DEVICE_PATH PciRootBridge;
> + PCI_DEVICE_PATH PciDevice;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} PLATFORM_USB_DEVICE_PATH;
> +
> +//
> +// Debug Agent UART Console device path definition
> +//
> +typedef struct {
> + VENDOR_DEVICE_PATH VendorHardware;
> + UART_DEVICE_PATH Uart;
> + VENDOR_DEVICE_PATH TerminalType;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} VENDOR_UART_DEVICE_PATH;
> +
> +//
> +// Below is the platform PCI device path
> +//
> +typedef struct {
> + ACPI_HID_DEVICE_PATH PciRootBridge;
> + PCI_DEVICE_PATH PciDevice;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} PLATFORM_PCI_DEVICE_PATH;
> +
> +typedef enum {
> + PMIC_Equal = 0, // = 0
> + PMIC_Greater_Than, // > 1
> + PMIC_Smaller_Than, // < 2
> + PMIC_Greater_Equal, // >= 3
> + PMIC_Smaller_Equal, // <= 4
> + PMIC_Any // don't care 5
> +} PMIC_Condition_list;
> +
> +typedef enum {
> + PMIC_White_List = 0, //White list
> + PMIC_Black_List = 1 //Black list
> +} PMIC_Compliance_mode;
> +
> +typedef struct {
> + UINT8 Cond_Choice; // PMIC_Condition_list
> + UINT8 Cond_Number; // the number
> +}PMIC_Condition_Item;
> +
> +typedef struct {
> + PMIC_Condition_Item
> PMIC_BoardID;
> + PMIC_Condition_Item PMIC_FabID;
> + PMIC_Condition_Item
> Soc_Stepping;//define PMIC type, 1:Dialog , 2:Rohm
> + PMIC_Condition_Item
> PMIC_VendID;
> + PMIC_Condition_Item PMIC_RevID;
> + PMIC_Compliance_mode mode; //if 1,
> blacklist; if 0, white list.
> +} PMIC_Compliance_Item;
> +
> +//
> +// Platform BDS Functions
> +//
> +VOID
> +PlatformBdsGetDriverOption (
> + IN LIST_ENTRY *BdsDriverLists
> + );
> +
> +VOID
> +PlatformBdsPredictBootOption (
> + IN LIST_ENTRY *BdsBootOptionList
> + );
> +
> +EFI_STATUS
> +PlatformBdsShowProgress (
> + EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
> + EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
> + CHAR16 *Title,
> + EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
> + UINTN Progress,
> + UINTN PreviousValue
> + );
> +
> +VOID
> +PlatformBdsConnectSequence (
> + VOID
> + );
> +
> +EFI_STATUS
> +PlatformBdsConnectConsole (
> + IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole
> + );
> +
> +EFI_STATUS
> +PlatformBdsNoConsoleAction (
> + VOID
> + );
> +
> +VOID
> +PlatformBdsEnterFrontPage (
> + IN UINT16 TimeoutDefault,
> + IN BOOLEAN ConnectAllHappened
> + );
> +
> +VOID
> +EFIAPI
> +PlatformBdsUserIdentify (
> + OUT EFI_USER_PROFILE_HANDLE *User,
> + OUT BOOLEAN *DeferredImage
> + );
> +
> +VOID
> +EFIAPI
> +PlatformBdsConnectAuthDevice (
> + VOID
> + );
> +
> +VOID
> +PlatformBdsEnterFrontPageWithHotKey (
> + IN UINT16 TimeoutDefault,
> + IN BOOLEAN ConnectAllHappened
> + );
> +
> + EFI_STATUS
> + ShowProgress (
> + IN UINT16 TimeoutDefault
> + );
> +
> + EFI_STATUS
> + InitializeFrontPage (
> + IN BOOLEAN InitializeHiiData
> + );
> +
> + VOID
> + UpdateFrontPageStrings (
> + VOID
> + );
> +
> +
> + EFI_STATUS
> + InitBMPackage (
> + VOID
> + );
> +
> +
> + VOID
> + FreeBMPackage (
> + VOID
> + );
> +
> +
> + EFI_STATUS
> + CallFrontPage (
> + VOID
> + );
> +
> +
> + VOID
> + CallBootManager (
> + VOID
> + );
> +
> +VOID
> +CallDeviceManager (
> + VOID
> + );
> +
> +VOID
> +BdsStartBootMaint (
> + VOID
> + );
> +
> +CHAR16 *
> +GetStringById (
> + IN EFI_STRING_ID Id
> + );
> +
> +EFI_STATUS
> +WaitForSingleEvent (
> + IN EFI_EVENT Event,
> + IN UINT64 Timeout OPTIONAL
> + );
> +
> +EFI_STATUS
> +BdsLibDeleteOptionFromHandle (
> + IN EFI_HANDLE Handle
> + );
> +
> +EFI_STATUS
> +BdsDeleteAllInvalidEfiBootOption (
> + VOID
> + );
> +
> +
> +#define ONE_SECOND 10000000
> +#define FRONT_PAGE_KEY_CONTINUE 0x1000
> +#define FRONT_PAGE_KEY_LANGUAGE 0x1234
> +#define FRONT_PAGE_KEY_BOOT_MANAGER 0x1064
> +#define FRONT_PAGE_KEY_DEVICE_MANAGER 0x8567
> +#define FRONT_PAGE_KEY_BOOT_MAINTAIN 0x9876
> +
> +#define PORT_A_DVO 0 // ; DVO A
> +#define PORT_B_DVO 1 // ; DVO B
> +#define PORT_C_DVO 2 // ; DVO C
> +#define PORT_D_DVO 3 // ; DVO D
> +#define PORT_LVDS 4 // ; Integrated LVDS port
> +#define PORT_ANALOG_TV 5 // ; Integrated TV port
> +#define PORT_CRT 6 // ; integrated Analog port
> +#define PORT_B_DP 7 // ; DisplayPort B
> +#define PORT_C_DP 8 // ; DisplayPort C
> +#define PORT_D_DP 9 // ; DisplayPort D
> +#define PORT_A_DP 10 // ; DisplayPort A (for eDP on ILK)
> +#define PORT_B_HDMI 11 // ; HDMI B
> +#define PORT_C_HDMI 12 // ; HDMI C
> +#define PORT_D_HDMI 13 // ; HDMI D
> +#define PORT_B_DVI 14 // ; DVI B
> +#define PORT_C_DVI 15 // ; DVI C
> +#define PORT_D_DVI 16 // ; DVI D
> +#define PORT_MIPI_A 21 // ; MIPI
> +#define PORT_MIPI_B 22
> +#define PORT_MIPI_C 23
> +
> +
> +extern BOOLEAN gConnectAllHappened;
> +extern UINTN gCallbackKey;
> +
> +VOID
> +BdsBootDeviceSelect (
> + VOID
> +);
> +VOID FastBoot(VOID);
> +
> +extern BOOLEAN mModeInitialized;
> +
> +//
> +// Boot video resolution and text mode.
> +//
> +extern UINT32 mBootHorizontalResolution ;
> +extern UINT32 mBootVerticalResolution ;
> +extern UINT32 mBootTextModeColumn ;
> +extern UINT32 mBootTextModeRow ;
> +
> +//
> +// BIOS setup video resolution and text mode.
> +//
> +extern UINT32 mSetupTextModeColumn ;
> +extern UINT32 mSetupTextModeRow ;
> +extern UINT32 mSetupHorizontalResolution ;
> +extern UINT32 mSetupVerticalResolution ;
> +extern EFI_STATUS BdsSetConsoleMode (BOOLEAN);
> +#endif // _BDS_PLATFORM_H
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.i
> nf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.i
> nf
> new file mode 100644
> index 0000000000..d3bef0fa39
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.i
> nf
> @@ -0,0 +1,127 @@
> +#/** @file
> +# Component name for module PlatformBootManagerLib
> +#
> +# Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
> +
> +#
> +#
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformBdsLib
> + FILE_GUID = A6BC385D-59E5-4b77-87D7-200ABAA83C15
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER
> + EDK_RELEASE_VERSION = 0x00020000
> + EFI_SPECIFICATION_VERSION = 0x0002000A
> +
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + BdsPlatform.c
> + BdsPlatform.h
> + PlatformData.c
> + PlatformBdsStrings.uni
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + ShellPkg/ShellPkg.dec
> + CryptoPkg/CryptoPkg.dec
> + SecurityPkg/SecurityPkg.dec
> + SignedCapsulePkg/SignedCapsulePkg.dec
> + SourceLevelDebugPkg/SourceLevelDebugPkg.dec
> +
> +[LibraryClasses]
> + DxeServicesTableLib
> + BaseLib
> + MemoryAllocationLib
> + UefiBootServicesTableLib
> + UefiRuntimeServicesTableLib
> + BaseMemoryLib
> + DebugLib
> + PcdLib
> + GenericBdsLib
> + DevicePathLib
> + NetLib
> + UefiLib
> + HobLib
> + PciLib
> + PrintLib
> + BaseCryptLib
> +# TcgPhysicalPresenceLib
> + Tcg2PhysicalPresenceLib
> + FileHandleLib
> + S3BootScriptLib
> + SerialPortLib
> + CapsuleLib
> +
> +[Protocols]
> + gEfiFirmwareVolume2ProtocolGuid
> + gEfiSimpleNetworkProtocolGuid
> + gEfiLoadFileProtocolGuid
> + gEfiPciIoProtocolGuid
> + gEfiSmmAccess2ProtocolGuid
> + gEfiDxeSmmReadyToLockProtocolGuid
> + gEfiUserManagerProtocolGuid
> + gEfiDeferredImageLoadProtocolGuid
> + gEfiAcpiS3SaveProtocolGuid
> + gEfiSpiProtocolGuid ## PROTOCOL CONSUMES
> + gExitPmAuthProtocolGuid
> + gEfiTdtOperationProtocolGuid
> + gEfiGlobalNvsAreaProtocolGuid
> + gEfiMmioDeviceProtocolGuid
> + gEfiI2cMasterProtocolGuid
> + gEfiI2cHostProtocolGuid
> + gEsrtManagementProtocolGuid
> +
> +[Guids]
> + gEfiMemoryTypeInformationGuid
> + gEfiCapsuleVendorGuid
> + gEfiGlobalVariableGuid
> + gEfiNormalSetupGuid
> + gEfiPartTypeSystemPartGuid
> + gEfiEndOfDxeEventGroupGuid
> + gUefiShellFileGuid
> +
> +[Pcd]
> +
> gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiRsa2048Sha256TestPublicKey
> FileGuid
> +
> gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiPkcs7TestPublicKeyFileGuid
> + gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer
> + gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer
> + gEfiMdeModulePkgTokenSpaceGuid.PcdTestKeyUsed
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvShellBase
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvShellSize
> + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
> + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile
> + gPlatformModuleTokenSpaceGuid.PcdIFWISigBaseAddress
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution
> + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsStri
> ngs.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsStri
> ngs.uni
> new file mode 100644
> index 0000000000..101106f9f4
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsStri
> ngs.uni
> @@ -0,0 +1,30 @@
> +///** @file
> +//
> +// String definitions for Boot Option description.
> +//
> +// Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//**/
> +
> +/=#
> +
> +#langdef en-US "English"
> +#langdef fr-FR "Français"
> +
> +#string STR_DESCRIPTION_FLOPPY #language en-US "EFI Floppy"
> + #language fr-FR "fr-FR: EFI Floppy"
> +#string STR_DESCRIPTION_CD_DVD #language en-US "EFI
> DVD/CDROM"
> + #language fr-FR "fr-FR: EFI DVD/CDROM"
> +#string STR_DESCRIPTION_HARDDRIVE #language en-US "EFI Hard Drive"
> + #language fr-FR "fr-FR: EFI Hard Drive"
> +#string STR_DESCRIPTION_USB #language en-US "EFI USB Device"
> + #language fr-FR "fr-FR: EFI USB Device"
> +#string STR_DESCRIPTION_SCSI #language en-US "EFI SCSI Device"
> + #language fr-FR "fr-FR: EFI SCSI Device"
> +#string STR_DESCRIPTION_MISC #language en-US "EFI Misc Device"
> + #language fr-FR "fr-FR: EFI Misc Device"
> +#string STR_DESCRIPTION_NETWORK #language en-US "EFI Network"
> + #language fr-FR "fr-FR: EFI Network"
> +#string STR_DESCRIPTION_NON_BLOCK #language en-US "EFI Non-Block
> Boot Device"
> + #language fr-FR "fr-FR: EFI Non-Block Boot Device"
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformData.c
> new file mode 100644
> index 0000000000..9dff93f52b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformData.c
> @@ -0,0 +1,306 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + PlatformData.c
> +
> +Abstract:
> +
> + Defined the platform specific device path which will be used by
> + platform Bbd to perform the platform policy connect.
> +
> +--*/
> +
> +#include "BdsPlatform.h"
> +
> +//
> +// Predefined platform default time out value
> +//
> +UINT16 gPlatformBootTimeOutDefault = 10;
> +
> +//
> +// Predefined platform root bridge
> +//
> +PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0 = {
> + gPciRootBridge,
> + gEndEntire
> +};
> +
> +EFI_DEVICE_PATH_PROTOCOL* gPlatformRootBridges [] = {
> + (EFI_DEVICE_PATH_PROTOCOL*)&gPlatformRootBridge0,
> + NULL
> +};
> +
> +//
> +// Platform specific ISA keyboard device path
> +//
> +PLATFORM_ISA_KEYBOARD_DEVICE_PATH gIsaKeyboardDevicePath = {
> + gPciRootBridge,
> + gPciIsaBridge,
> + gPnpPs2Keyboard,
> + gEndEntire
> +};
> +
> +//
> +// Platform specific on chip PCI VGA device path
> +//
> +PLATFORM_ONBOARD_VGA_DEVICE_PATH gOnChipPciVgaDevicePath = {
> + gPciRootBridge,
> + PCI_DEVICE_PATH_NODE(0, 0x2),
> + gEndEntire
> +};
> +
> +//
> +// Platform specific plug in PCI VGA device path
> +//
> +PLATFORM_OFFBOARD_VGA_DEVICE_PATH gPlugInPciVgaDevicePath = {
> + gPciRootBridge,
> + PCI_DEVICE_PATH_NODE(0, 0x1),
> + PCI_DEVICE_PATH_NODE(0, 0x0),
> + gEndEntire
> +};
> +
> +//
> +// Platform specific ISA serial device path
> +//
> +PLATFORM_ISA_SERIAL_DEVICE_PATH gIsaSerialDevicePath = {
> + gPciRootBridge,
> + gPciIsaBridge,
> + gPnp16550ComPort,
> + gUart(115200, 8, 1, 1),
> + gPcAnsiTerminal,
> + gEndEntire
> +};
> +
> +
> +//
> +// Platform specific Button Array device path
> +//
> +HII_VENDOR_DEVICE_PATH gHiiVendorDevicePath0 = {
> + {
> + {
> + HARDWARE_DEVICE_PATH,
> + HW_VENDOR_DP,
> + {
> + (UINT8) (sizeof (VENDOR_DEVICE_PATH)),
> + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)
> + }
> + },
> +
> + //
> + // {C8752FDE-B5C8-4528-897D-6920FE771E38}
> + //
> + { 0xC8752FDE, 0xB5C8, 0x4528, { 0x89, 0x7D, 0x69, 0x20, 0xFE, 0x77, 0x1E,
> 0x38 } }
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + (UINT8) (END_DEVICE_PATH_LENGTH),
> + (UINT8) ((END_DEVICE_PATH_LENGTH) >> 8)
> + }
> + }
> +};
> +
> +USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = {
> + gUsbKeyboardMouse,
> + gEndEntire
> +};
> +
> +//
> +// Debug Agent UART Console device path
> +//
> +VENDOR_UART_DEVICE_PATH gDebugAgentUartDevicePath = {
> + {
> + {
> + HARDWARE_DEVICE_PATH,
> + HW_VENDOR_DP,
> + {
> + (UINT8) (sizeof (VENDOR_DEVICE_PATH)),
> + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)
> + }
> + },
> + EFI_DEBUG_AGENT_GUID,
> + },
> + {
> + {
> + MESSAGING_DEVICE_PATH,
> + MSG_UART_DP,
> + {
> + (UINT8) (sizeof (UART_DEVICE_PATH)),
> + (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8)
> + }
> + },
> + 0, // Reserved
> + 0, // BaudRate - Default
> + 0, // DataBits - Default
> + 0, // Parity - Default
> + 0, // StopBits - Default
> + },
> + {
> + {
> + MESSAGING_DEVICE_PATH,
> + MSG_VENDOR_DP,
> + {
> + (UINT8)(sizeof (VENDOR_DEVICE_PATH)),
> + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)
> + }
> + },
> + DEVICE_PATH_MESSAGING_PC_ANSI
> + },
> + gEndEntire
> +};
> +
> +//
> +// Predefined platform default console device path
> +//
> +BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole [] = {
> + {(EFI_DEVICE_PATH_PROTOCOL*)&gIsaSerialDevicePath, CONSOLE_ALL},
> + {(EFI_DEVICE_PATH_PROTOCOL*)&gHiiVendorDevicePath0, CONSOLE_IN},
> + {(EFI_DEVICE_PATH_PROTOCOL*)&gIsaKeyboardDevicePath,
> CONSOLE_IN},
> + {(EFI_DEVICE_PATH_PROTOCOL*)&gDebugAgentUartDevicePath,
> CONSOLE_ALL},
> + {(EFI_DEVICE_PATH_PROTOCOL*)&gUsbClassKeyboardDevicePath,
> CONSOLE_IN},
> + {NULL, 0}
> +};
> +
> +//
> +// All the possible platform PCI VGA device path
> +//
> +EFI_DEVICE_PATH_PROTOCOL* gPlatformAllPossiblePciVgaConsole [] = {
> + (EFI_DEVICE_PATH_PROTOCOL*)&gOnChipPciVgaDevicePath,
> + (EFI_DEVICE_PATH_PROTOCOL*)&gPlugInPciVgaDevicePath,
> + NULL
> +};
> +
> +//
> +// Legacy hard disk boot option
> +//
> +LEGACY_HD_DEVICE_PATH gLegacyHd = {
> + {
> + BBS_DEVICE_PATH,
> + BBS_BBS_DP,
> + (UINT8)(sizeof(BBS_BBS_DEVICE_PATH)),
> + (UINT8)((sizeof(BBS_BBS_DEVICE_PATH)) >> 8),
> + BBS_TYPE_HARDDRIVE,
> + 0,
> + 0
> + },
> + gEndEntire
> +};
> +
> +//
> +// Legacy cdrom boot option
> +//
> +LEGACY_HD_DEVICE_PATH gLegacyCdrom = {
> + {
> + BBS_DEVICE_PATH,
> + BBS_BBS_DP,
> + (UINT8)(sizeof(BBS_BBS_DEVICE_PATH)),
> + (UINT8)((sizeof(BBS_BBS_DEVICE_PATH)) >> 8),
> + BBS_TYPE_CDROM,
> + 0,
> + 0
> + },
> + gEndEntire
> +};
> +
> +//
> +// Predefined platform specific perdict boot option
> +//
> +EFI_DEVICE_PATH_PROTOCOL* gPlatformBootOption [] = {
> + (EFI_DEVICE_PATH_PROTOCOL*)&gLegacyHd,
> + (EFI_DEVICE_PATH_PROTOCOL*)&gLegacyCdrom,
> + NULL
> +};
> +
> +//
> +// Predefined platform specific driver option
> +//
> +EFI_DEVICE_PATH_PROTOCOL* gPlatformDriverOption [] = {
> + NULL
> +};
> +
> +//
> +// Predefined platform connect sequence
> +//
> +EFI_DEVICE_PATH_PROTOCOL* gPlatformConnectSequence [] = {
> + (EFI_DEVICE_PATH_PROTOCOL *)&gPlatformRootBridge0, // Force PCI
> enumer before Legacy OpROM shadow
> + NULL
> +};
> +
> +//
> +// Platform specific USB controller device path
> +//
> +PLATFORM_USB_DEVICE_PATH gUsbDevicePath0 = {
> + gPciRootBridge,
> + PCI_DEVICE_PATH_NODE(0, 0x1D),
> + gEndEntire
> +};
> +
> +PLATFORM_USB_DEVICE_PATH gUsbDevicePath1 = {
> + gPciRootBridge,
> + PCI_DEVICE_PATH_NODE(1, 0x1D),
> + gEndEntire
> +};
> +
> +PLATFORM_USB_DEVICE_PATH gUsbDevicePath2 = {
> + gPciRootBridge,
> + PCI_DEVICE_PATH_NODE(2, 0x1D),
> + gEndEntire
> +};
> +
> +PLATFORM_USB_DEVICE_PATH gUsbDevicePath3 = {
> + gPciRootBridge,
> + PCI_DEVICE_PATH_NODE(3, 0x1D),
> + gEndEntire
> +};
> +
> +//
> +// Predefined platform device path for user authtication
> +//
> +EFI_DEVICE_PATH_PROTOCOL* gUserAuthenticationDevice[] = {
> + //
> + // Predefined device path for secure card (USB disk).
> + //
> + (EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath0,
> + (EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath1,
> + (EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath2,
> + (EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath3,
> + NULL
> +};
> +
> +//
> +// Predefined platform console device path
> +//
> +BDS_CONSOLE_CONNECT_ENTRY gPlatformSimpleConsole [] = {
> + {(EFI_DEVICE_PATH_PROTOCOL*)&gOnChipPciVgaDevicePath,
> CONSOLE_OUT},
> + {(EFI_DEVICE_PATH_PROTOCOL*)&gIsaSerialDevicePath, CONSOLE_ALL},
> + {(EFI_DEVICE_PATH_PROTOCOL*)&gHiiVendorDevicePath0, CONSOLE_IN},
> + {(EFI_DEVICE_PATH_PROTOCOL*)&gDebugAgentUartDevicePath,
> CONSOLE_ALL},
> + {(EFI_DEVICE_PATH_PROTOCOL*)&gUsbClassKeyboardDevicePath,
> CONSOLE_IN},
> + {NULL, 0}
> +};
> +
> +//
> +// eMMC device at BDF(0x0, 0x17, 0x0)
> +//
> +PLATFORM_PCI_DEVICE_PATH gEmmcBootDevPath0 = {
> + gPciRootBridge,
> + PCI_DEVICE_PATH_NODE (0x00, 0x10),
> + gEndEntire
> +};
> +
> +//
> +// Predefined platform specific perdict boot option
> +//
> +EFI_DEVICE_PATH_PROTOCOL* gPlatformSimpleBootOption [] = {
> + (EFI_DEVICE_PATH_PROTOCOL*)&gEmmcBootDevPath0,
> + NULL
> +};
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmos
> Lib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmos
> Lib.c
> new file mode 100644
> index 0000000000..2a02cabcaf
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmos
> Lib.c
> @@ -0,0 +1,106 @@
> +/*++
> +
> +Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + CmosTable.h
> +
> +Abstract:
> +
> +--*/
> +
> +#include <Base.h>
> +#include <Library/IoLib.h>
> +#include <Library/PlatformCmosLib.h>
> +#include "CmosMap.h"
> +#include <PchAccess.h>
> +#include "PlatformBaseAddresses.h"
> +
> +#define DEFAULT_VALUE 0
> +#define DEFAULT_ATTRIBUTES 0
> +#define EXCLUDE_FROM_CHECKSUM
> CMOS_ATTRIBUTE_EXCLUDE_FROM_CHECKSUM
> +
> +#define CMOS_DEBUG_PRINT_LEVEL_DEFAULT_VALUE 0x46 //
> EFI_D_WARN|EFI_D_INFO|EFI_D_LOAD
> +#define CMOS_DEBUG_PRINT_LEVEL_3_DEFAULT_VALUE 0x80 //
> EFI_D_ERROR
> +
> +//
> +// Add the CMOS entry below
> +//
> +CMOS_ENTRY mCmosTable[] = {
> +{ CPU_HT_POLICY, CPU_HT_POLICY_ENABLED,
> EXCLUDE_FROM_CHECKSUM },
> +{ TPM_POLICY, TPM_POLICY_ENABLED, DEFAULT_ATTRIBUTES },
> +{ CMOS_LCDPANELTYPE_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
> +{ CMOS_LCDPANELSCALING_REG, DEFAULT_VALUE,
> DEFAULT_ATTRIBUTES },
> +{ CMOS_IGDBOOTTYPE_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
> +{ CMOS_BACKLIGHT_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
> +{ CMOS_LFP_PANEL_COLOR_DEPTH_REG, DEFAULT_VALUE,
> DEFAULT_ATTRIBUTES },
> +{ CMOS_EDP_ACTIVE_LFP_CONFIG_REG, DEFAULT_VALUE,
> DEFAULT_ATTRIBUTES },
> +{ CMOS_PRIMARY_DISPLAY_REG, DEFAULT_VALUE,
> DEFAULT_ATTRIBUTES },
> +{ CMOS_IGD_DISPLAY_PIPE_B_REG, DEFAULT_VALUE,
> DEFAULT_ATTRIBUTES },
> +{ CMOS_SDVOPANELTYPE_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
> +{ CMOS_PLATFORM_RESET_OS, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
> +{ CMOS_CPU_BSP_SELECT, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
> +{ CMOS_CPU_RATIO_OFFSET, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
> +{ CMOS_ICH_PORT80_OFFSET, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
> +{ CMOS_MAXRATIO_CONFIG_REG, DEFAULT_VALUE,
> DEFAULT_ATTRIBUTES },
> +{ RTC_ADDRESS_CENTURY, RTC_ADDRESS_CENTURY_DEFAULT,
> CMOS_ATTRIBUTE_EXCLUDE_FROM_CHECKSUM },
> +{ CMOS_POST_CODE_BREAK_REG, DEFAULT_VALUE,
> EXCLUDE_FROM_CHECKSUM },
> +{ CMOS_POST_CODE_BREAK_1_REG, DEFAULT_VALUE,
> EXCLUDE_FROM_CHECKSUM },
> +{ CMOS_POST_CODE_BREAK_2_REG, DEFAULT_VALUE,
> EXCLUDE_FROM_CHECKSUM },
> +{ CMOS_POST_CODE_BREAK_3_REG, DEFAULT_VALUE,
> EXCLUDE_FROM_CHECKSUM },
> +{ CMOS_DEBUG_PRINT_LEVEL_REG,
> CMOS_DEBUG_PRINT_LEVEL_DEFAULT_VALUE,
> EXCLUDE_FROM_CHECKSUM },
> +{ CMOS_DEBUG_PRINT_LEVEL_1_REG, DEFAULT_VALUE,
> EXCLUDE_FROM_CHECKSUM },
> +{ CMOS_DEBUG_PRINT_LEVEL_2_REG, DEFAULT_VALUE,
> EXCLUDE_FROM_CHECKSUM },
> +{ CMOS_DEBUG_PRINT_LEVEL_3_REG,
> CMOS_DEBUG_PRINT_LEVEL_3_DEFAULT_VALUE,
> EXCLUDE_FROM_CHECKSUM },
> +};
> +
> +/**
> + Funtion to return platform CMOS entry.
> +
> + @param [out] CmosEntry Platform CMOS entry.
> +
> + @param [out] CmosEntryCount Number of platform CMOS entry.
> +
> + @return Status.
> +**/
> +RETURN_STATUS
> +EFIAPI
> +GetPlatformCmosEntry (
> + OUT CMOS_ENTRY **CmosEntry,
> + OUT UINTN *CmosEntryCount
> + )
> +{
> + *CmosEntry = mCmosTable;
> + *CmosEntryCount = sizeof(mCmosTable)/sizeof(mCmosTable[0]);
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Function to check if Battery lost or CMOS cleared.
> +
> + @reval TRUE Battery is always present.
> + @reval FALSE CMOS is cleared.
> +**/
> +BOOLEAN
> +EFIAPI
> +CheckCmosBatteryStatus (
> + VOID
> + )
> +{
> + //
> + // Check if the CMOS battery is present
> + // Checks RTC_PWR_STS bit in the GEN_PMCON_1 register
> + //
> +
> + if ((MmioRead8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1) &
> B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) == 0) {
> + return TRUE;
> + } else {
> + return FALSE;
> + }
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmos
> Lib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmos
> Lib.inf
> new file mode 100644
> index 0000000000..c5d8b66591
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmos
> Lib.inf
> @@ -0,0 +1,30 @@
> +#/** @file
> +#
> +# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformCmosLib
> + FILE_GUID = ECA883EF-0CBE-40b6-84BC-FA4A709782F7
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PlatformCmosLib
> +
> +[Sources]
> + PlatformCmosLib.c
> +
> +[LibraryClasses]
> + IoLib
> +
> +[Packages]
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.c
> new file mode 100644
> index 0000000000..b99c3b0122
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.c
> @@ -0,0 +1,44 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +#include "PiPei.h"
> +#include <Library/HobLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Guid/MemoryConfigData.h>
> +#include <PlatformFspLib.h>
> +
> +EFI_STATUS
> +PlatformHobCreateFromFsp (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + VOID *HobList
> + )
> +{
> + VOID *HobData;
> + VOID *NewHobData;
> + UINTN DataSize;
> +
> + //
> + // Other hob, todo: put this into FspWrapPlatformLib
> + //
> + if ((HobList = GetNextGuidHob (&gEfiMemoryConfigDataGuid, HobList)) !=
> NULL) {
> + HobData = GET_GUID_HOB_DATA (HobList);
> + DataSize = GET_GUID_HOB_DATA_SIZE(HobList);
> + DEBUG((EFI_D_ERROR, "gEfiMemoryConfigDataGuid Hob found:
> 0x%x.\n", DataSize));
> +
> + NewHobData = BuildGuidHob (&gEfiMemoryConfigDataGuid, DataSize);
> + (*PeiServices)->CopyMem (
> + NewHobData,
> + HobData,
> + DataSize
> + );
> + }
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.i
> nf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.i
> nf
> new file mode 100644
> index 0000000000..ddd97c5ad9
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.i
> nf
> @@ -0,0 +1,49 @@
> +#
> +#
> +# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +# FSP Platform HOB Library
> +#
> +#
> +#
> +##
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformFspLib
> + FILE_GUID = 1305A712-33A6-4fa7-BA59-AEAC3362931A
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PlatformFspLib
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + PlatformFspLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + IntelFspWrapperPkg/IntelFspWrapperPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + HobLib
> +
> +[Guids]
> + gEfiMemoryConfigDataGuid
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLi
> b.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLi
> b.c
> new file mode 100644
> index 0000000000..fac998fefa
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLi
> b.c
> @@ -0,0 +1,235 @@
> +/** @file
> +
> + Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + IdeBus.h
> +
> +Abstract:
> +
> + System reset Library Services. This library class provides a set of
> + methods to reset whole system with manipulate ICH.
> +
> +**/
> +
> +
> +#include <Base.h>
> +
> +
> +#include <Library/ResetSystemLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PciLib.h>
> +
> +#include "PchRegs.h"
> +#include "Rsci.h"
> +#include "Platform.h"
> +
> +#define RESET_GENERATOR_PORT R_PCH_RST_CNT
> +
> +VOID
> +EFIAPI
> +PlatformResetHook (
> + UINT8 ResetType
> + )
> +{
> + //
> + // Platform need to save OS reset request/types for next Android boot
> + //
> + IoWrite8 (0x72, CMOS_RESET_TYPE_BY_OS);
> + IoWrite8 (0x73, ResetType);
> +}
> +
> +/**
> + Calling this function causes a system-wide reset. This sets
> + all circuitry within the system to its initial state. This type of reset
> + is asynchronous to system operation and operates without regard to
> + cycle boundaries.
> +
> + System reset should not return, if it returns, it means the system does
> + not support cold reset.
> +**/
> +VOID
> +EFIAPI
> +ResetCold (
> + VOID
> + )
> +{
> + PlatformResetHook(COLD_RESET);
> + IoWrite8 (RESET_GENERATOR_PORT, 0x2);
> + IoWrite8 (RESET_GENERATOR_PORT, 0x6);
> +}
> +
> +/**
> + Calling this function causes a system-wide initialization. The processors
> + are set to their initial state, and pending cycles are not corrupted.
> +
> + System reset should not return, if it returns, it means the system does
> + not support warm reset.
> +**/
> +VOID
> +EFIAPI
> +ResetWarm (
> + VOID
> + )
> +{
> + PlatformResetHook(WARM_RESET);
> + IoWrite8 (RESET_GENERATOR_PORT, 0x0);
> + IoWrite8 (RESET_GENERATOR_PORT, 0x4);
> +}
> +
> +/**
> + Calling this function causes the system to enter a power state equivalent
> + to the ACPI G2/S5 or G3 states.
> +
> + System shutdown should not return, if it returns, it means the system
> does
> + not support shut down reset.
> +**/
> +VOID
> +EFIAPI
> +ResetShutdown (
> + VOID
> + )
> +{
> + UINT16 PchPmioBase;
> + UINT16 Data16;
> + UINT32 Data32;
> +
> + PchPmioBase = (UINT16) (PciRead16 (PCI_LIB_ADDRESS(0,
> PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ACPI_BASE)) & ~BIT0);
> +
> + //
> + // Then, GPE0_EN should be disabled to avoid any GPI waking up the
> system from S5
> + //
> + Data16 = 0;
> + IoWrite16 (
> + (UINTN)(PchPmioBase + R_PCH_ACPI_GPE0a_EN),
> + (UINT16)Data16
> + );
> +
> + //
> + // Clear Sleep SMI Status
> + //
> + IoWrite16 (PchPmioBase + R_PCH_SMI_STS,
> + (UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_STS) |
> B_PCH_SMI_STS_ON_SLP_EN));
> + //
> + // Clear Sleep Type Enable
> + //
> + IoWrite16 (PchPmioBase + R_PCH_SMI_EN,
> + (UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_EN) &
> (~B_PCH_SMI_EN_ON_SLP_EN)));
> + //
> + // Clear Power Button Status
> + //
> + IoWrite16(PchPmioBase + R_PCH_ACPI_PM1_STS,
> B_PCH_ACPI_PM1_STS_PWRBTN);
> +
> + //
> + // Secondly, Power Button Status bit must be cleared
> + //
> + // Write a "1" to bit[8] of power button status register at
> + // (ABASE + PM1_STS) to clear this bit
> + // Clear it through SMI Status register
> + //
> + Data16 = B_PCH_SMI_STS_PM1_STS_REG;
> + IoWrite16 ((UINTN) (PchPmioBase + R_PCH_SMI_STS), Data16);
> +
> + //
> + // Finally, transform system into S5 sleep state
> + //
> + Data32 = IoRead32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT));
> +
> + Data32 = (UINT32) ((Data32 &~(B_PCH_ACPI_PM1_CNT_SLP_TYP +
> B_PCH_ACPI_PM1_CNT_SLP_EN)) | V_PCH_ACPI_PM1_CNT_S5);
> +
> + IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);
> +
> + Data32 = Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN;
> +
> + IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);
> +
> + return;
> +}
> +
> +/**
> + Calling this function causes the system to enter a power state for capsule
> + update.
> +
> + Reset update should not return, if it returns, it means the system does
> + not support capsule update.
> +
> +**/
> +VOID
> +EFIAPI
> +EnterS3WithImmediateWake (
> + VOID
> + )
> +{
> + ASSERT (FALSE);
> +}
> +
> +/**
> + This function causes a systemwide reset. The exact type of the reset is
> + defined by the EFI_GUID that follows the Null-terminated Unicode string
> passed
> + into ResetData. If the platform does not recognize the EFI_GUID in
> ResetData
> + the platform must pick a supported reset type to perform.The platform
> may
> + optionally log the parameters from any non-normal reset that occurs.
> +
> + @param[in] DataSize The size, in bytes, of ResetData.
> + @param[in] ResetData The data buffer starts with a Null-terminated
> string,
> + followed by the EFI_GUID.
> +**/
> +VOID
> +EFIAPI
> +ResetPlatformSpecific (
> + IN UINTN DataSize,
> + IN VOID *ResetData
> + )
> +{
> + ResetCold ();
> +}
> +
> +/**
> + The ResetSystem function resets the entire platform.
> +
> + @param[in] ResetType The type of reset to perform.
> + @param[in] ResetStatus The status code for the reset.
> + @param[in] DataSize The size, in bytes, of ResetData.
> + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm,
> or EfiResetShutdown
> + the data buffer starts with a Null-terminated string, optionally
> + followed by additional binary data. The string is a description
> + that the caller may use to further indicate the reason for the
> + system reset.
> +**/
> +VOID
> +EFIAPI
> +ResetSystem (
> + IN EFI_RESET_TYPE ResetType,
> + IN EFI_STATUS ResetStatus,
> + IN UINTN DataSize,
> + IN VOID *ResetData OPTIONAL
> + )
> +{
> + switch (ResetType) {
> + case EfiResetWarm:
> + ResetWarm ();
> + break;
> +
> + case EfiResetCold:
> + ResetCold ();
> + break;
> +
> + case EfiResetShutdown:
> + ResetShutdown ();
> + return;
> +
> + case EfiResetPlatformSpecific:
> + ResetPlatformSpecific (DataSize, ResetData);
> + return;
> +
> + default:
> + return;
> + }
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLi
> b.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLi
> b.inf
> new file mode 100644
> index 0000000000..db1a92b34e
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLi
> b.inf
> @@ -0,0 +1,47 @@
> +#/** @file
> +# Component description file for Intel Ich7 Reset System Library.
> +#
> +# Reset System Library that layers on top of the I/O Library to directly
> +# access a standard SMBUS host controller.
> +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = ResetSystemLib
> + FILE_GUID = D4FF05AA-3C7D-4b8a-A1EE-AA5EFA0B1732
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ResetSystemLib
> + EDK_RELEASE_VERSION = 0x00020000
> + EFI_SPECIFICATION_VERSION = 0x00020000
> +
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +[Sources.common]
> + ResetSystemLib.c
> +
> +
> +[Packages]
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + IoLib
> + BaseLib
> + DebugLib
> + PciLib
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPort
> Lib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPort
> Lib.h
> new file mode 100644
> index 0000000000..fe47e8f68d
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPort
> Lib.h
> @@ -0,0 +1,53 @@
> +/** @file
> + Header file of Serial port hardware definition.
> +
> + Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __PLATFORM_SERIAL_PORT_LIB_H_
> +#define __PLATFORM_SERIAL_PORT_LIB_H_
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +//
> +// UART Register Offsets
> +//
> +#define BAUD_LOW_OFFSET 0x00
> +#define BAUD_HIGH_OFFSET 0x01
> +#define IER_OFFSET 0x01
> +#define LCR_SHADOW_OFFSET 0x01
> +#define FCR_SHADOW_OFFSET 0x02
> +#define IR_CONTROL_OFFSET 0x02
> +#define FCR_OFFSET 0x02
> +#define EIR_OFFSET 0x02
> +#define BSR_OFFSET 0x03
> +#define LCR_OFFSET 0x03
> +#define MCR_OFFSET 0x04
> +#define LSR_OFFSET 0x05
> +#define MSR_OFFSET 0x06
> +
> +//
> +// UART Register Bit Defines
> +//
> +#define LSR_TXRDY 0x20
> +#define LSR_RXDA 0x01
> +#define DLAB 0x01
> +
> +#define UART_DATA 8
> +#define UART_STOP 1
> +#define UART_PARITY 0
> +#define UART_BREAK_SET 0
> +
> +VOID
> +InitializeSio (
> + VOID
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
> new file mode 100644
> index 0000000000..f6012593d0
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
> @@ -0,0 +1,246 @@
> +/** @file
> + Serial I/O Port library functions with no library constructor/destructor
> +
> + Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "PlatformSerialPortLib.h"
> +
> +UINT16 gComBase = 0x3f8;
> +UINTN gBps = 115200;
> +UINT8 gData = 8;
> +UINT8 gStop = 1;
> +UINT8 gParity = 0;
> +UINT8 gBreakSet = 0;
> +
> +/**
> + Initialize Serial Port
> +
> + The Baud Rate Divisor registers are programmed and the LCR
> + is used to configure the communications format. Hard coded
> + UART config comes from globals in DebugSerialPlatform lib.
> +
> + @param None
> +
> + @retval None
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +UARTInitialize (
> + VOID
> + )
> +{
> + UINTN Divisor;
> + UINT8 OutputData;
> + UINT8 Data;
> +
> + //
> + // Map 5..8 to 0..3
> + //
> + Data = (UINT8) (gData - (UINT8) 5);
> +
> + //
> + // Calculate divisor for baud generator
> + //
> + Divisor = 115200 / gBps;
> +
> + //
> + // Set communications format
> + //
> + OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) |
> ((gStop << 2) | Data))));
> + IoWrite8 (gComBase + LCR_OFFSET, OutputData);
> +
> + //
> + // Configure baud rate
> + //
> + IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8));
> + IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff));
> +
> + //
> + // Switch back to bank 0
> + //
> + OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) |
> ((gStop << 2) | Data))));
> + IoWrite8 (gComBase + LCR_OFFSET, OutputData);
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Common function to initialize UART Serial device and USB Serial device.
> +
> + @param None
> +
> + @retval None
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortInitialize (
> + VOID
> + )
> +{
> +
> + UARTInitialize ();
> +
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Write data to serial device.
> +
> + If the buffer is NULL, then return 0;
> + if NumberOfBytes is zero, then return 0.
> +
> + @param Buffer Point of data buffer which need to be writed.
> + @param NumberOfBytes Number of output bytes which are cached in
> Buffer.
> +
> + @retval 0 Write data failed.
> + @retval !0 Actual number of bytes writed to serial device.
> +
> +**/
> +UINTN
> +EFIAPI
> +UARTDbgOut (
> + IN UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> +)
> +{
> + UINTN Result;
> + UINT8 Data;
> +
> + if (NULL == Buffer) {
> + return 0;
> + }
> +
> + Result = NumberOfBytes;
> +
> + while (NumberOfBytes--) {
> + //
> + // Wait for the serial port to be ready.
> + //
> + do {
> + Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) +
> LSR_OFFSET);
> + } while ((Data & LSR_TXRDY) == 0);
> + IoWrite8 ((UINT16) PcdGet64 (PcdSerialRegisterBase), *Buffer++);
> + }
> +
> + return Result;
> +}
> +
> +/**
> + Common function to write data to UART Serial device and USB Serial device.
> +
> + @param Buffer Point of data buffer which need to be writed.
> + @param NumberOfBytes Number of output bytes which are cached in
> Buffer.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortWrite (
> + IN UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> +)
> +{
> + if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
> + UARTDbgOut (Buffer, NumberOfBytes);
> + }
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Read data from serial device and save the datas in buffer.
> +
> + If the buffer is NULL, then return 0;
> + if NumberOfBytes is zero, then return 0.
> +
> + @param Buffer Point of data buffer which need to be writed.
> + @param NumberOfBytes Number of output bytes which are cached in
> Buffer.
> +
> + @retval 0 Read data failed.
> + @retval !0 Actual number of bytes raed to serial device.
> +
> +**/
> +UINTN
> +EFIAPI
> +UARTDbgIn (
> + OUT UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> +)
> +{
> + UINTN Result;
> + UINT8 Data;
> +
> + if (NULL == Buffer) {
> + return 0;
> + }
> +
> + Result = NumberOfBytes;
> +
> + while (NumberOfBytes--) {
> + //
> + // Wait for the serial port to be ready.
> + //
> + do {
> + Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) +
> LSR_OFFSET);
> + } while ((Data & LSR_RXDA) == 0);
> +
> + *Buffer++ = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase));
> + }
> +
> + return Result;
> +}
> +
> +/**
> + Common function to Read data from UART serial device, USB serial device
> and save the datas in buffer.
> +
> + @param Buffer Point of data buffer which need to be writed.
> + @param NumberOfBytes Number of output bytes which are cached in
> Buffer.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortRead (
> + OUT UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> +)
> +{
> + if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
> + UARTDbgIn (Buffer, NumberOfBytes);
> + }
> +
> + return RETURN_SUCCESS;
> +}
> +
> +
> +/**
> + Polls a serial device to see if there is any data waiting to be read.
> +
> + Polls aserial device to see if there is any data waiting to be read.
> + If there is data waiting to be read from the serial device, then TRUE is
> returned.
> + If there is no data waiting to be read from the serial device, then FALSE is
> returned.
> +
> + @retval TRUE Data is waiting to be read from the serial device.
> + @retval FALSE There is no data waiting to be read from the serial
> device.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +SerialPortPoll (
> + VOID
> + )
> +{
> + UINT8 Data;
> +
> + //
> + // Read the serial port status.
> + //
> + Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) +
> LSR_OFFSET);
> +
> + return (BOOLEAN) ((Data & LSR_RXDA) != 0);
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf
> new file mode 100644
> index 0000000000..0e7a6d3cfc
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf
> @@ -0,0 +1,52 @@
> +#/** @file
> +#
> +# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SerialPortLib
> + FILE_GUID = 15B26F43-A389-4bae-BDE3-4BB0719B7D4F
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SerialPortLib
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +[Sources]
> + SerialPortLib.c
> + SioInit.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + PcdLib
> + IoLib
> + PciLib
> + TimerLib
> +
> +[FixedPcd.common]
> + gEfiSerialPortTokenSpaceGuid.PcdSerialBoudRate
> + gEfiSerialPortTokenSpaceGuid.PcdSerialRegisterBase
> +
> +[FeaturePcd]
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c
> new file mode 100644
> index 0000000000..d9d48539dc
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c
> @@ -0,0 +1,127 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + SioInit.c
> +
> +Abstract:
> +
> + Functions for LpcSio initialization
> +
> +--*/
> +
> +#include "PlatformSerialPortLib.h"
> +#include "SioInit.h"
> +
> +typedef struct {
> + UINT8 Register;
> + UINT8 Value;
> +} EFI_SIO_TABLE;
> +
> +EFI_SIO_TABLE mSioTableWpcn381u[] = {
> + {0x29, 0x0A0},
> + {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0},
> // Select UART0 device
> + {WPCN381U_BASE1_HI_REGISTER,
> (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base
> Address MSB
> + {WPCN381U_BASE1_LO_REGISTER,
> (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set
> Base Address LSB
> + {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to
> IRQ4
> + {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},
> // Enable it with Activation bit
> + {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1},
> // Select UART1 device
> + {WPCN381U_BASE1_HI_REGISTER,
> (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base
> Address MSB
> + {WPCN381U_BASE1_LO_REGISTER,
> (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set
> Base Address LSB
> + {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to
> IRQ3
> + {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},
> // Enable it with Activation bit
> + {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO},
> // Select GPIO device
> + {WPCN381U_BASE1_HI_REGISTER,
> (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base
> Address MSB
> + {WPCN381U_BASE1_LO_REGISTER,
> (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base
> Address LSB
> + {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},
> // Enable it with Activation bit
> + {0x21, 0x001}, // Global Device Enable
> + {0x26, 0x000}
> +};
> +
> +EFI_SIO_TABLE mSioTableWdcp376[] = {
> + {0x29, 0x0A0},
> + {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0},
> // Select UART0 device
> + {WPCN381U_BASE1_HI_REGISTER,
> (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base
> Address MSB
> + {WPCN381U_BASE1_LO_REGISTER,
> (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set
> Base Address LSB
> + {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to
> IRQ4
> + {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},
> // Enable it with Activation bit
> + {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1},
> // Select UART1 device
> + {WPCN381U_BASE1_HI_REGISTER,
> (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base
> Address MSB
> + {WPCN381U_BASE1_LO_REGISTER,
> (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set
> Base Address LSB
> + {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to
> IRQ3
> + {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},
> // Enable it with Activation bit
> + {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO},
> // Select GPIO device
> + {WPCN381U_BASE1_HI_REGISTER,
> (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base
> Address MSB
> + {WPCN381U_BASE1_LO_REGISTER,
> (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base
> Address LSB
> + {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},
> // Enable it with Activation bit
> + {0x21, 0x001}, // Global Device Enable
> + {0x26, 0x000},
> + {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K},
> // Select PS2 Keyboard
> + {WPCN381U_BASE1_HI_REGISTER,
> (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)}, // Set Base Address
> MSB
> + {WPCN381U_BASE1_LO_REGISTER,
> (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)}, // Set Base
> Address LSB
> + {WPCN381U_BASE2_HI_REGISTER,
> (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)}, // Set Base Address
> MSB
> + {WPCN381U_BASE2_LO_REGISTER,
> (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)}, // Set Base
> Address LSB
> + {WPCN381U_IRQ1_REGISTER, 0x011}, // Set to
> IRQ1
> + {0xF0, (SIO_KBC_CLOCK << 6)}, // Select KBC
> Clock Source
> + {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},
> // Enable it with Activation bit
> + {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M},
> // Select PS2 Mouse
> + {WPCN381U_IRQ1_REGISTER, 0x01c}, // Set to
> IRQ12
> + {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}
> // Enable it with Activation bit
> +};
> +
> +/**
> + Initialization for SIO.
> +
> + @param FfsHeader FV this PEIM was loaded from.
> + @param PeiServices General purpose services available to every PEIM.
> +
> + None
> +
> +**/
> +VOID
> +InitializeSio (
> + VOID
> + )
> +{
> + UINT16 Index;
> + UINT16 IndexPort;
> + UINT16 DataPort;
> +
> + //
> + // Super I/O initialization for Winbond WPCN381U
> + //
> + IndexPort = WPCN381U_CONFIG_INDEX;
> + DataPort = WPCN381U_CONFIG_DATA;
> +
> + //
> + // Check for Winbond WPCN381U
> + //
> + IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER); // Winbond
> WPCN381U Device ID register is 0x20
> +
> + if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) { // Winbond WPCN381U
> Device ID is 0xF4
> + //
> + // Configure WPCN381U SIO
> + //
> + for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof
> (EFI_SIO_TABLE); Index++) {
> + IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
> + IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
> + }
> + }
> +
> + if (IoRead8 (DataPort) == WDCP376_CHIP_ID) { // Winbond WDCP376
> Device ID is 0xF1
> + //
> + // Configure WDCP376 SIO
> + //
> + for (Index = 0; Index < sizeof (mSioTableWdcp376) / sizeof
> (EFI_SIO_TABLE); Index++) {
> + IoWrite8 (IndexPort, mSioTableWdcp376[Index].Register);
> + IoWrite8 (DataPort, mSioTableWdcp376[Index].Value);
> + }
> + }
> + return;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
> new file mode 100644
> index 0000000000..06fa19b93d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
> @@ -0,0 +1,62 @@
> +/** @file
> + Header file of Serial port hardware definition.
> +
> + Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _SIO_INIT_H_
> +#define _SIO_INIT_H_
> +
> +#define WPCN381U_CONFIG_INDEX 0x2E
> +#define WPCN381U_CONFIG_DATA 0x2F
> +#define WPCN381U_CONFIG_INDEX1 0x164E
> +#define WPCN381U_CONFIG_DATA1 0x164F
> +#define WPCN381U_CHIP_ID 0xF4
> +#define WDCP376_CHIP_ID 0xF1
> +
> +//
> +// SIO Logical Devices Numbers
> +//
> +#define WPCN381U_LDN_UART0 0x03 // LDN for Serial Port
> Controller
> +#define WPCN381U_LDN_UART1 0x02 // LDN for Parallel Port
> Controller
> +#define WPCN381U_LDN_PS2K 0x06 // LDN for PS2 Keyboard
> Controller
> +#define WPCN381U_LDN_PS2M 0x05 // LDN for PS2 Mouse
> Controller
> +#define WPCN381U_KB_BASE1_ADDRESS 0x60 // Base Address of KB
> controller
> +#define WPCN381U_KB_BASE2_ADDRESS 0x64 // Base Address of KB
> controller
> +#define SIO_KBC_CLOCK 0x01 // 0/1/2 - 8/12/16 MHz KBC Clock
> Source
> +#define WPCN381U_LDN_GPIO 0x07 // LDN for GPIO
> +
> +//
> +// SIO Registers Layout
> +//
> +#define WPCN381U_LD_SEL_REGISTER 0x07 // Logical Device Select
> Register Address
> +#define WPCN381U_DEV_ID_REGISTER 0x20 // Device Identification
> Register Address
> +#define WPCN381U_ACTIVATE_REGISTER 0x30 // Device Identification
> Register Address
> +#define WPCN381U_BASE1_HI_REGISTER 0x60 // Device BaseAddres
> Register #1 MSB Address
> +#define WPCN381U_BASE1_LO_REGISTER 0x61 // Device BaseAddres
> Register #1 LSB Address
> +#define WPCN381U_BASE2_HI_REGISTER 0x62 // Device BaseAddres
> Register #1 MSB Address
> +#define WPCN381U_BASE2_LO_REGISTER 0x63 // Device Ba1eAddres
> Register #1 LSB Address
> +#define WPCN381U_IRQ1_REGISTER 0x70 // Device IRQ Register #1
> Address
> +#define WPCN381U_IRQ2_REGISTER 0x71 // Device IRQ Register #2
> Address
> +
> +//
> +// SIO Activation Values
> +//
> +#define WPCN381U_ACTIVATE_VALUE 0x01 // Value to activate
> Device
> +#define WPCN381U_DEACTIVATE_VALUE 0x00 // Value to deactivate
> Device
> +
> +//
> +// SIO GPIO
> +//
> +#define WPCN381U_GPIO_BASE_ADDRESS 0x0A20 // SIO GPIO Base
> Address
> +
> +//
> +// SIO Serial Port Settings
> +//
> +#define WPCN381U_SERIAL_PORT0_BASE_ADDRESS 0x03F8 // Base
> Address of Serial Port 0 (COMA / UART0)
> +#define WPCN381U_SERIAL_PORT1_BASE_ADDRESS 0x02F8 // Base
> Address of Serial Port 1 (COMB / UART1)
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/SmbusLib/CommonHeader.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/SmbusLib/CommonHeader.h
> new file mode 100644
> index 0000000000..d34dd942d3
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/SmbusLib/CommonHeader.h
> @@ -0,0 +1,26 @@
> +/**@file
> + Common header file shared by all source files.
> +
> + This file includes package header files, library classes.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +**/
> +
> +#ifndef __COMMON_HEADER_H_
> +#define __COMMON_HEADER_H_
> +
> +
> +#include <Base.h>
> +#include <PchAccess.h>
> +
> +#include <Library/SmbusLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PciLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.c
> new file mode 100644
> index 0000000000..4052724812
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.c
> @@ -0,0 +1,873 @@
> +/** @file
> + Intel ICH9 SMBUS library implementation built upon I/O library.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include "CommonHeader.h"
> +
> +/**
> + Gets Io port base address of Smbus Host Controller.
> +
> + This internal function depends on a feature flag named
> PcdIchSmbusFixedIoPortBaseAddress
> + to retrieve Smbus Io port base. If that feature flag is true, it will get Smbus
> Io port base
> + address from a preset Pcd entry named PcdIchSmbusIoPortBaseAddress;
> otherwise, it will always
> + read Pci configuration space to get that value in each Smbus bus
> transaction.
> +
> + @return The Io port base address of Smbus host controller.
> +
> +**/
> +UINTN
> +InternalGetSmbusIoPortBaseAddress (
> + VOID
> + )
> +{
> + UINTN IoPortBaseAddress;
> +
> + IoPortBaseAddress = (UINTN) MmioRead32 (MmPciAddress (0,
> DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS,
> PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_BASE)) &
> B_PCH_SMBUS_BASE_BAR;
> +
> + //
> + // Make sure that the IO port base address has been properly set.
> + //
> + ASSERT (IoPortBaseAddress != 0);
> +
> + return IoPortBaseAddress;
> +}
> +
> +/**
> + Acquires the ownership of SMBUS.
> +
> + This internal function reads the host state register.
> + If the SMBUS is not available, RETURN_TIMEOUT is returned;
> + Otherwise, it performs some basic initializations and returns
> + RETURN_SUCCESS.
> +
> + @param IoPortBaseAddress The Io port base address of Smbus Host
> controller.
> +
> + @retval RETURN_SUCCESS The SMBUS command was executed
> successfully.
> + @retval RETURN_TIMEOUT A timeout occurred while executing the
> SMBUS command.
> +
> +**/
> +RETURN_STATUS
> +InternalSmBusAcquire (
> + UINTN IoPortBaseAddress
> + )
> +{
> + UINT8 HostStatus;
> +
> + HostStatus = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS);
> + if ((HostStatus & B_PCH_SMBUS_IUS) != 0) {
> + return RETURN_TIMEOUT;
> + } else if ((HostStatus & B_PCH_SMBUS_HBSY) != 0) {
> + //
> + // Clear host status register and exit.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS,
> B_PCH_SMBUS_HSTS_ALL);
> + return RETURN_TIMEOUT;
> + }
> + //
> + // Clear out any odd status information (Will Not Clear In Use).
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS, HostStatus);
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Starts the SMBUS transaction and waits until the end.
> +
> + This internal function start the SMBUS transaction and waits until the
> transaction
> + of SMBUS is over by polling the INTR bit of Host status register.
> + If the SMBUS is not available, RETURN_TIMEOUT is returned;
> + Otherwise, it performs some basic initializations and returns
> + RETURN_SUCCESS.
> +
> + @param IoPortBaseAddress The Io port base address of Smbus Host
> controller.
> + @param HostControl The Host control command to start SMBUS
> transaction.
> +
> + @retval RETURN_SUCCESS The SMBUS command was executed
> successfully.
> + @retval RETURN_CRC_ERROR The checksum is not correct (PEC is
> incorrect).
> + @retval RETURN_DEVICE_ERROR The request was not completed because
> a failure reflected
> + in the Host Status Register bit. Device errors are
> + a result of a transaction collision, illegal command field,
> + unclaimed cycle (host initiated), or bus errors (collisions).
> +
> +**/
> +RETURN_STATUS
> +InternalSmBusStart (
> + IN UINTN IoPortBaseAddress,
> + IN UINT8 HostControl
> + )
> +{
> + UINT8 HostStatus;
> + UINT8 AuxiliaryStatus;
> +
> + //
> + // Set Host Control Register (Initiate Operation, Interrupt disabled).
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HCTL,
> (UINT8)(HostControl + B_PCH_SMBUS_START));
> +
> + do {
> + //
> + // Poll INTR bit of Host Status Register.
> + //
> + HostStatus = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS);
> + } while ((HostStatus & (B_PCH_SMBUS_INTR | B_PCH_SMBUS_ERRORS |
> B_PCH_SMBUS_BYTE_DONE_STS)) == 0);
> +
> + if ((HostStatus & B_PCH_SMBUS_ERRORS) == 0) {
> + return RETURN_SUCCESS;
> + }
> +
> + //
> + // Clear error bits of Host Status Register.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS,
> B_PCH_SMBUS_ERRORS);
> +
> + //
> + // Read Auxiliary Status Register to judge CRC error.
> + //
> + AuxiliaryStatus = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_AUXS);
> + if ((AuxiliaryStatus & B_PCH_SMBUS_CRCE) != 0) {
> + return RETURN_CRC_ERROR;
> + }
> +
> + return RETURN_DEVICE_ERROR;
> +}
> +
> +/**
> + Executes an SMBUS quick, byte or word command.
> +
> + This internal function executes an SMBUS quick, byte or word commond.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> +
> + @param HostControl The value of Host Control Register to set.
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Value The byte/word write to the SMBUS.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The byte/word read from the SMBUS.
> +
> +**/
> +UINT16
> +InternalSmBusNonBlock (
> + IN UINT8 HostControl,
> + IN UINTN SmBusAddress,
> + IN UINT16 Value,
> + OUT RETURN_STATUS *Status
> + )
> +{
> + RETURN_STATUS ReturnStatus;
> + UINTN IoPortBaseAddress;
> + UINT8 AuxiliaryControl;
> +
> + IoPortBaseAddress = InternalGetSmbusIoPortBaseAddress ();
> +
> + //
> + // Try to acquire the ownership of ICH SMBUS.
> + //
> + ReturnStatus = InternalSmBusAcquire (IoPortBaseAddress);
> + if (RETURN_ERROR (ReturnStatus)) {
> + goto Done;
> + }
> +
> + //
> + // Set the appropriate Host Control Register and auxiliary Control Register.
> + //
> + AuxiliaryControl = 0;
> + if (SMBUS_LIB_PEC (SmBusAddress)) {
> + AuxiliaryControl |= B_PCH_SMBUS_AAC;
> + HostControl |= B_PCH_SMBUS_PEC_EN;
> + }
> +
> + //
> + // Set Host Command Register.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HCMD, (UINT8)
> SMBUS_LIB_COMMAND (SmBusAddress));
> +
> + //
> + // Write value to Host Data 0 and Host Data 1 Registers.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HD0, (UINT8) Value);
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HD1, (UINT8) (Value >> 8));
> +
> + //
> + // Set Auxiliary Control Register.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXC, AuxiliaryControl);
> +
> + //
> + // Set SMBUS slave address for the device to send/receive from.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_TSA, (UINT8)
> SmBusAddress);
> +
> + //
> + // Start the SMBUS transaction and wait for the end.
> + //
> + ReturnStatus = InternalSmBusStart (IoPortBaseAddress, HostControl);
> +
> + //
> + // Read value from Host Data 0 and Host Data 1 Registers.
> + //
> + Value = (UINT16)(IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HD1) <<
> 8);
> + Value = (UINT16)(Value | IoRead8 (IoPortBaseAddress +
> R_PCH_SMBUS_HD0));
> +
> + //
> + // Clear Host Status Register and Auxiliary Status Register.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS,
> B_PCH_SMBUS_HSTS_ALL);
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXS,
> B_PCH_SMBUS_CRCE);
> +
> +Done:
> + if (Status != NULL) {
> + *Status = ReturnStatus;
> + }
> +
> + return Value;
> +}
> +
> +/**
> + Executes an SMBUS quick read command.
> +
> + Executes an SMBUS quick read command on the SMBUS device specified
> by SmBusAddress.
> + Only the SMBUS slave address field of SmBusAddress is required.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + If PEC is set in SmBusAddress, then ASSERT().
> + If Command in SmBusAddress is not zero, then ASSERT().
> + If Length in SmBusAddress is not zero, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> +**/
> +VOID
> +EFIAPI
> +SmBusQuickRead (
> + IN UINTN SmBusAddress,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + ASSERT (!SMBUS_LIB_PEC (SmBusAddress));
> + ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> +
> + InternalSmBusNonBlock (
> + V_PCH_SMBUS_SMB_CMD_QUICK,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,
> + 0,
> + Status
> + );
> +}
> +
> +/**
> + Executes an SMBUS quick write command.
> +
> + Executes an SMBUS quick write command on the SMBUS device specified
> by SmBusAddress.
> + Only the SMBUS slave address field of SmBusAddress is required.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + If PEC is set in SmBusAddress, then ASSERT().
> + If Command in SmBusAddress is not zero, then ASSERT().
> + If Length in SmBusAddress is not zero, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> +**/
> +VOID
> +EFIAPI
> +SmBusQuickWrite (
> + IN UINTN SmBusAddress,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + ASSERT (!SMBUS_LIB_PEC (SmBusAddress));
> + ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> +
> + InternalSmBusNonBlock (
> + V_PCH_SMBUS_SMB_CMD_QUICK,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
> + 0,
> + Status
> + );
> +}
> +
> +/**
> + Executes an SMBUS receive byte command.
> +
> + Executes an SMBUS receive byte command on the SMBUS device specified
> by SmBusAddress.
> + Only the SMBUS slave address field of SmBusAddress is required.
> + The byte received from the SMBUS is returned.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + If Command in SmBusAddress is not zero, then ASSERT().
> + If Length in SmBusAddress is not zero, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The byte received from the SMBUS.
> +
> +**/
> +UINT8
> +EFIAPI
> +SmBusReceiveByte (
> + IN UINTN SmBusAddress,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + UINT8 ValueReturn = 0;
> +
> + ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> +
> + ValueReturn = (UINT8) InternalSmBusNonBlock (
> + V_PCH_SMBUS_SMB_CMD_BYTE,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,
> + 0,
> + Status
> + );
> + return ValueReturn;
> +
> + }
> +
> +/**
> + Executes an SMBUS send byte command.
> +
> + Executes an SMBUS send byte command on the SMBUS device specified
> by SmBusAddress.
> + The byte specified by Value is sent.
> + Only the SMBUS slave address field of SmBusAddress is required. Value is
> returned.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + If Command in SmBusAddress is not zero, then ASSERT().
> + If Length in SmBusAddress is not zero, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Value The 8-bit value to send.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT8
> +EFIAPI
> +SmBusSendByte (
> + IN UINTN SmBusAddress,
> + IN UINT8 Value,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + UINT8 ValueReturn = 0;
> +
> + ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> +
> + ValueReturn = (UINT8) InternalSmBusNonBlock (
> + V_PCH_SMBUS_SMB_CMD_BYTE,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
> + Value,
> + Status
> + );
> + return ValueReturn;
> +
> + }
> +
> +/**
> + Executes an SMBUS read data byte command.
> +
> + Executes an SMBUS read data byte command on the SMBUS device
> specified by SmBusAddress.
> + Only the SMBUS slave address and SMBUS command fields of
> SmBusAddress are required.
> + The 8-bit value read from the SMBUS is returned.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + If Length in SmBusAddress is not zero, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The byte read from the SMBUS.
> +
> +**/
> +UINT8
> +EFIAPI
> +SmBusReadDataByte (
> + IN UINTN SmBusAddress,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + UINT8 ValueReturn = 0;
> +
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> + ValueReturn = (UINT8) InternalSmBusNonBlock (
> + V_PCH_SMBUS_SMB_CMD_BYTE_DATA,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,
> + 0,
> + Status
> + );
> + return ValueReturn;
> +}
> +
> +/**
> + Executes an SMBUS write data byte command.
> +
> + Executes an SMBUS write data byte command on the SMBUS device
> specified by SmBusAddress.
> + The 8-bit value specified by Value is written.
> + Only the SMBUS slave address and SMBUS command fields of
> SmBusAddress are required.
> + Value is returned.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + If Length in SmBusAddress is not zero, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Value The 8-bit value to write.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT8
> +EFIAPI
> +SmBusWriteDataByte (
> + IN UINTN SmBusAddress,
> + IN UINT8 Value,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + UINT8 ValueReturn = 0;
> +
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> +
> + ValueReturn = (UINT8) InternalSmBusNonBlock (
> + V_PCH_SMBUS_SMB_CMD_BYTE_DATA,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
> + Value,
> + Status
> + );
> + return ValueReturn;
> +
> +}
> +
> +/**
> + Executes an SMBUS read data word command.
> +
> + Executes an SMBUS read data word command on the SMBUS device
> specified by SmBusAddress.
> + Only the SMBUS slave address and SMBUS command fields of
> SmBusAddress are required.
> + The 16-bit value read from the SMBUS is returned.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + If Length in SmBusAddress is not zero, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The byte read from the SMBUS.
> +
> +**/
> +UINT16
> +EFIAPI
> +SmBusReadDataWord (
> + IN UINTN SmBusAddress,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + UINT16 ValueReturn = 0;
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> +
> + ValueReturn = InternalSmBusNonBlock (
> + V_PCH_SMBUS_SMB_CMD_WORD_DATA,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,
> + 0,
> + Status
> + );
> + return ValueReturn;
> +
> +}
> +
> +/**
> + Executes an SMBUS write data word command.
> +
> + Executes an SMBUS write data word command on the SMBUS device
> specified by SmBusAddress.
> + The 16-bit value specified by Value is written.
> + Only the SMBUS slave address and SMBUS command fields of
> SmBusAddress are required.
> + Value is returned.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + If Length in SmBusAddress is not zero, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Value The 16-bit value to write.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +SmBusWriteDataWord (
> + IN UINTN SmBusAddress,
> + IN UINT16 Value,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + UINT16 ValueReturn = 0;
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> +
> + ValueReturn = InternalSmBusNonBlock (
> + V_PCH_SMBUS_SMB_CMD_WORD_DATA,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
> + Value,
> + Status
> + );
> + return ValueReturn;
> +}
> +
> +/**
> + Executes an SMBUS process call command.
> +
> + Executes an SMBUS process call command on the SMBUS device specified
> by SmBusAddress.
> + The 16-bit value specified by Value is written.
> + Only the SMBUS slave address and SMBUS command fields of
> SmBusAddress are required.
> + The 16-bit value returned by the process call command is returned.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + If Length in SmBusAddress is not zero, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Value The 16-bit value to write.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The 16-bit value returned by the process call command.
> +
> +**/
> +UINT16
> +EFIAPI
> +SmBusProcessCall (
> + IN UINTN SmBusAddress,
> + IN UINT16 Value,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + UINT16 ValueReturn = 0;
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> +
> + ValueReturn = InternalSmBusNonBlock (
> + V_PCH_SMBUS_SMB_CMD_PROCESS_CALL,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
> + Value,
> + Status
> + );
> + return ValueReturn;
> +}
> +
> +/**
> + Executes an SMBUS block command.
> +
> + Executes an SMBUS block read, block write and block write-block read
> command
> + on the SMBUS device specified by SmBusAddress.
> + Bytes are read from the SMBUS and stored in Buffer.
> + The number of bytes read is returned, and will never return a value larger
> than 32-bytes.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + It is the caller's responsibility to make sure Buffer is large enough for the
> total number of bytes read.
> + SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not
> need to be any larger than 32 bytes.
> +
> + @param HostControl The value of Host Control Register to set.
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param WriteBuffer Pointer to the buffer of bytes to write to the
> SMBUS.
> + @param ReadBuffer Pointer to the buffer of bytes to read from the
> SMBUS.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The number of bytes read from the SMBUS.
> +
> +**/
> +UINTN
> +InternalSmBusBlock (
> + IN UINT8 HostControl,
> + IN UINTN SmBusAddress,
> + IN UINT8 *WriteBuffer,
> + OUT UINT8 *ReadBuffer,
> + OUT RETURN_STATUS *Status
> + )
> +{
> + RETURN_STATUS ReturnStatus;
> + UINTN Index;
> + UINTN BytesCount;
> + UINTN IoPortBaseAddress;
> + UINT8 AuxiliaryControl;
> +
> + IoPortBaseAddress = InternalGetSmbusIoPortBaseAddress ();
> +
> + BytesCount = SMBUS_LIB_LENGTH (SmBusAddress);
> +
> + //
> + // Try to acquire the ownership of ICH SMBUS.
> + //
> + ReturnStatus = InternalSmBusAcquire (IoPortBaseAddress);
> + if (RETURN_ERROR (ReturnStatus)) {
> + goto Done;
> + }
> +
> + //
> + // Set the appropriate Host Control Register and auxiliary Control Register.
> + //
> + AuxiliaryControl = B_PCH_SMBUS_E32B;
> + if (SMBUS_LIB_PEC (SmBusAddress)) {
> + AuxiliaryControl |= B_PCH_SMBUS_AAC;
> + HostControl |= B_PCH_SMBUS_PEC_EN;
> + }
> +
> + //
> + // Set Host Command Register.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HCMD, (UINT8)
> SMBUS_LIB_COMMAND (SmBusAddress));
> +
> + //
> + // Set Auxiliary Control Regiester.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXC, AuxiliaryControl);
> +
> + //
> + // Clear byte pointer of 32-byte buffer.
> + //
> + IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HCTL);
> +
> + if (WriteBuffer != NULL) {
> + //
> + // Write the number of block to Host Block Data Byte Register.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HD0, (UINT8)
> BytesCount);
> +
> + //
> + // Write data block to Host Block Data Register.
> + //
> + for (Index = 0; Index < BytesCount; Index++) {
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HBD,
> WriteBuffer[Index]);
> + }
> + }
> +
> + //
> + // Set SMBUS slave address for the device to send/receive from.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_TSA, (UINT8)
> SmBusAddress);
> +
> + //
> + // Start the SMBUS transaction and wait for the end.
> + //
> + ReturnStatus = InternalSmBusStart (IoPortBaseAddress, HostControl);
> + if (RETURN_ERROR (ReturnStatus)) {
> + goto Done;
> + }
> +
> + if (ReadBuffer != NULL) {
> + //
> + // Read the number of block from host block data byte register.
> + //
> + BytesCount = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HD0);
> +
> + //
> + // Write data block from Host Block Data Register.
> + //
> + for (Index = 0; Index < BytesCount; Index++) {
> + ReadBuffer[Index] = IoRead8 (IoPortBaseAddress +
> R_PCH_SMBUS_HBD);
> + }
> + }
> +
> +Done:
> + //
> + // Clear Host Status Register and Auxiliary Status Register.
> + //
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS,
> B_PCH_SMBUS_HSTS_ALL);
> + IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXS,
> B_PCH_SMBUS_CRCE);
> +
> + if (Status != NULL) {
> + *Status = ReturnStatus;
> + }
> +
> + return BytesCount;
> +}
> +
> +/**
> + Executes an SMBUS read block command.
> +
> + Executes an SMBUS read block command on the SMBUS device specified
> by SmBusAddress.
> + Only the SMBUS slave address and SMBUS command fields of
> SmBusAddress are required.
> + Bytes are read from the SMBUS and stored in Buffer.
> + The number of bytes read is returned, and will never return a value larger
> than 32-bytes.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + It is the caller's responsibility to make sure Buffer is large enough for the
> total number of bytes read.
> + SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not
> need to be any larger than 32 bytes.
> + If Length in SmBusAddress is not zero, then ASSERT().
> + If Buffer is NULL, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Buffer Pointer to the buffer to store the bytes read from the
> SMBUS.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The number of bytes read.
> +
> +**/
> +UINTN
> +EFIAPI
> +SmBusReadBlock (
> + IN UINTN SmBusAddress,
> + OUT VOID *Buffer,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + UINTN BytesCount = 0;
> +
> + ASSERT (Buffer != NULL);
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> +
> +
> + BytesCount = InternalSmBusBlock (
> + V_PCH_SMBUS_SMB_CMD_BLOCK,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,
> + NULL,
> + Buffer,
> + Status
> + );
> + return BytesCount;
> +
> +}
> +
> +/**
> + Executes an SMBUS write block command.
> +
> + Executes an SMBUS write block command on the SMBUS device specified
> by SmBusAddress.
> + The SMBUS slave address, SMBUS command, and SMBUS length fields of
> SmBusAddress are required.
> + Bytes are written to the SMBUS from Buffer.
> + The number of bytes written is returned, and will never return a value
> larger than 32-bytes.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + If Length in SmBusAddress is zero or greater than 32, then ASSERT().
> + If Buffer is NULL, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param Buffer Pointer to the buffer to store the bytes read from the
> SMBUS.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The number of bytes written.
> +
> +**/
> +UINTN
> +EFIAPI
> +SmBusWriteBlock (
> + IN UINTN SmBusAddress,
> + OUT VOID *Buffer,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + UINTN BytesCount = 0;
> +
> + ASSERT (Buffer != NULL);
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) >= 1);
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) <= 32);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> +
> +
> + BytesCount = InternalSmBusBlock (
> +
> + V_PCH_SMBUS_SMB_CMD_BLOCK,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
> + Buffer,
> + NULL,
> + Status
> + );
> +
> + return BytesCount;
> +}
> +
> +/**
> + Executes an SMBUS block process call command.
> +
> + Executes an SMBUS block process call command on the SMBUS device
> specified by SmBusAddress.
> + The SMBUS slave address, SMBUS command, and SMBUS length fields of
> SmBusAddress are required.
> + Bytes are written to the SMBUS from WriteBuffer. Bytes are then read
> from the SMBUS into ReadBuffer.
> + If Status is not NULL, then the status of the executed command is returned
> in Status.
> + It is the caller's responsibility to make sure ReadBuffer is large enough for
> the total number of bytes read.
> + SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not
> need to be any larger than 32 bytes.
> + If Length in SmBusAddress is zero or greater than 32, then ASSERT().
> + If WriteBuffer is NULL, then ASSERT().
> + If ReadBuffer is NULL, then ASSERT().
> + If any reserved bits of SmBusAddress are set, then ASSERT().
> +
> + @param SmBusAddress Address that encodes the SMBUS Slave Address,
> + SMBUS Command, SMBUS Data Length, and PEC.
> + @param WriteBuffer Pointer to the buffer of bytes to write to the
> SMBUS.
> + @param ReadBuffer Pointer to the buffer of bytes to read from the
> SMBUS.
> + @param Status Return status for the executed command.
> + This is an optional parameter and may be NULL.
> +
> + @return The number of bytes written.
> +
> +**/
> +UINTN
> +EFIAPI
> +SmBusBlockProcessCall (
> + IN UINTN SmBusAddress,
> + IN VOID *WriteBuffer,
> + OUT VOID *ReadBuffer,
> + OUT RETURN_STATUS *Status OPTIONAL
> + )
> +{
> + UINTN BytesCount = 0;
> +
> + ASSERT (WriteBuffer != NULL);
> + ASSERT (ReadBuffer != NULL);
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) >= 1);
> + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) <= 32);
> + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
> +
> + BytesCount = InternalSmBusBlock (
> + V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS,
> + SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
> + WriteBuffer,
> + ReadBuffer,
> + Status
> + );
> + return BytesCount;
> +
> + }
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf
> new file mode 100644
> index 0000000000..b13e3de0cc
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf
> @@ -0,0 +1,46 @@
> +## @file
> +# Component description file for Intel Ich9 Smbus Library.
> +#
> +# SMBUS Library that layers on top of the I/O Library to directly
> +# access a standard SMBUS host controller.
> +# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SmbusLib
> + FILE_GUID = 0558CAEA-FEF3-4b6d-915E-8742EFE6DEE1
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SmbusLib
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + SmbusLib.c
> +
> +[Packages]
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + MdePkg/MdePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + PcdLib
> + DebugLib
> + PciLib
> + IoLib
> +
> +[Pcd.common]
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmm.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmm.c
> new file mode 100644
> index 0000000000..062994f088
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmm.c
> @@ -0,0 +1,89 @@
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + SmmIo.c
> +
> +Abstract:
> +
> + SMM I/O access utility implementation file, for Ia32
> +
> +--*/
> +
> +//
> +// Include files
> +//
> +#include "Library/StallSmmLib.h"
> +#include "Pi/PiSmmCis.h"
> +#include "PiDxe.h"
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include "PchAccess.h"
> +
> +/**
> + Delay for at least the request number of microseconds.
> + Timer used is ACPI time counter, which has 1us granularity.
> +
> + @param Microseconds Number of microseconds to delay.
> +
> + @retval None
> +
> +**/
> +VOID
> +SmmStall (
> + IN UINTN Microseconds
> + )
> +{
> + UINTN Ticks;
> + UINTN Counts;
> + UINTN CurrentTick;
> + UINTN OriginalTick;
> + UINTN RemainingTick;
> + UINT16 AcpiBaseAddr;
> +
> + if (Microseconds == 0) {
> + return;
> + }
> +
> + AcpiBaseAddr = PchLpcPciCfg16 (R_PCH_LPC_ACPI_BASE) &
> B_PCH_LPC_ACPI_BASE_BAR;
> +
> + OriginalTick = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_TMR);
> + CurrentTick = OriginalTick;
> +
> + //
> + // The timer frequency is 3.579545 MHz, so 1 ms corresponds 3.58 clocks
> + //
> + Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
> +
> + //
> + // The loops needed by timer overflow
> + //
> + Counts = Ticks / V_PCH_ACPI_PM1_TMR_MAX_VAL;
> +
> + //
> + // Remaining clocks within one loop
> + //
> + RemainingTick = Ticks % V_PCH_ACPI_PM1_TMR_MAX_VAL;
> +
> + //
> + // not intend to use TMROF_STS bit of register PM1_STS, because this
> adds extra
> + // one I/O operation, and maybe generate SMI
> + //
> + while ((Counts != 0) || (RemainingTick > CurrentTick)) {
> + CurrentTick = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_TMR);
> + //
> + // Check if timer overflow
> + //
> + if (CurrentTick < OriginalTick) {
> + Counts--;
> + }
> + OriginalTick = CurrentTick;
> + }
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmmLib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmmLib.inf
> new file mode 100644
> index 0000000000..703ea3238c
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmmLib.inf
> @@ -0,0 +1,51 @@
> +#/*++
> +#
> +# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +
> +#
> +# Module Name:
> +#
> +# SmmStallLib.inf
> +#
> +# Abstract:
> +#
> +# Component description file for SmmStall library
> +#
> +#--*/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = StallSmmLib
> + FILE_GUID = A6A16CCB-91B0-42f4-B4F3-D16D7A8662E6
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = StallSmmLib
> +
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + StallSmm.c
> +
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + PcdLib
> + PciLib
> + IoLib
> + BaseLib
> +
> +[Pcd.common]
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2De
> viceLibSeC.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2De
> viceLibSeC.c
> new file mode 100644
> index 0000000000..ad3d201e07
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2De
> viceLibSeC.c
> @@ -0,0 +1,117 @@
> +/*++
> +
> +Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +--*/
> +
> +#include <Uefi.h>
> +#include <Protocol/PttPassThru.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +//#include <Library/Tpm2DeviceLib.h>
> +
> +
> +PTT_PASS_THRU_PROTOCOL *mPttPassThruProtocol;
> +
> +
> +/**
> + The constructor function caches the pointer to PEI services.
> +
> + The constructor function caches the pointer to PEI services.
> + It will always return EFI_SUCCESS.
> +
> + @param FfsHeader Pointer to FFS header the loaded driver.
> + @param PeiServices Pointer to the PEI services.
> +
> + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
> +
> +**/
> +
> +EFI_STATUS
> +EFIAPI
> +Tpm2DeviceLibConstructor (
> + VOID
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> +
> + Status = gBS->LocateProtocol (&gPttPassThruProtocolGuid, NULL, (VOID
> **) &mPttPassThruProtocol);
> +
> + return Status;
> +}
> +
> +/**
> + This service enables the sending of commands to the TPM2.
> +
> + @param[in] InputParameterBlockSize Size of the TPM2 input parameter
> block.
> + @param[in] InputParameterBlock Pointer to the TPM2 input parameter
> block.
> + @param[in] OutputParameterBlockSize Size of the TPM2 output
> parameter block.
> + @param[in] OutputParameterBlock Pointer to the TPM2 output
> parameter block.
> +
> + @retval EFI_SUCCESS The command byte stream was successfully
> sent to the device and a response was successfully received.
> + @retval EFI_DEVICE_ERROR The command was not successfully sent to
> the device or a response was not successfully received from the device.
> + @retval EFI_BUFFER_TOO_SMALL The output parameter block is too
> small.
> +**/
> +EFI_STATUS
> +EFIAPI
> +Tpm2SubmitCommand (
> + IN UINT32 InputParameterBlockSize,
> + IN UINT8 *InputParameterBlock,
> + IN OUT UINT32 *OutputParameterBlockSize,
> + IN UINT8 *OutputParameterBlock
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = mPttPassThruProtocol->Tpm2SubmitCommand (
> + mPttPassThruProtocol,
> + InputParameterBlockSize,
> + InputParameterBlock,
> + OutputParameterBlockSize,
> + OutputParameterBlock
> + );
> +
> + return Status;
> +}
> +
> +/**
> + This service requests use TPM2.
> +
> + @retval EFI_SUCCESS Get the control of TPM2 chip.
> + @retval EFI_NOT_FOUND TPM2 not found.
> + @retval EFI_DEVICE_ERROR Unexpected device behavior.
> +**/
> +EFI_STATUS
> +EFIAPI
> +Tpm2RequestUseTpm (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = mPttPassThruProtocol->Tpm2RequestUseTpm
> (mPttPassThruProtocol);
> +
> + return Status;
> +}
> +
> +/**
> + This service register TPM2 device.
> +
> + @Param Tpm2Device TPM2 device
> +
> + @retval EFI_SUCCESS This TPM2 device is registered successfully.
> + @retval EFI_UNSUPPORTED System does not support register this TPM2
> device.
> + @retval EFI_ALREADY_STARTED System already register this TPM2 device.
> +**/
> +EFI_STATUS
> +EFIAPI
> +Tpm2RegisterTpm2DeviceLib (
> + IN PTT_TPM2_DEVICE_INTERFACE *Tpm2Device
> + )
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2De
> viceLibSeC.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2De
> viceLibSeC.inf
> new file mode 100644
> index 0000000000..9ee91527c1
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2De
> viceLibSeC.inf
> @@ -0,0 +1,61 @@
> +#/** @file
> +#
> +#
> +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#
> +#
> +#**/
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = Tpm2DeviceLibSeC
> + FILE_GUID = 294B196A-A3CC-4a43-857F-EEC26147857B
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = Tpm2DeviceLib | DXE_DRIVER
> DXE_SMM_DRIVER
> + CONSTRUCTOR = Tpm2DeviceLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources.common]
> + Tpm2DeviceLibSeC.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + SecurityPkg/SecurityPkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + PcdLib
> + UefiBootServicesTableLib
> +
> +
> +[Guids]
> + gEfiVLVTokenSpaceGuid
> +
> +[Pcd]
> + gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable
> + gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur
> + gEfiVLVTokenSpaceGuid.PcdFTPMCommand
> + gEfiVLVTokenSpaceGuid.PcdFTPMResponse
> + gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond
> + gEfiVLVTokenSpaceGuid.PcdFTPMStatus
> +
> +[Protocols]
> + gPttPassThruProtocolGuid
> +
> +[Depex]
> + gPttPassThruProtocolGuid
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2Dev
> iceLibSeC.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2Dev
> iceLibSeC.c
> new file mode 100644
> index 0000000000..12717a5f69
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2Dev
> iceLibSeC.c
> @@ -0,0 +1,145 @@
> +/*++
> +
> +Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +--*/
> +
> +#include <Uefi.h>
> +#include <PiPei.h>
> +#include <Ppi/PttPassThruPpi.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/PcdLib.h>
> +
> +
> +
> +
> +
> +
> +PTT_PASS_THRU_PPI *SecPttPassThruPpi = NULL;
> +
> +/**
> + The constructor function caches the pointer to PEI services.
> +
> + The constructor function caches the pointer to PEI services.
> + It will always return EFI_SUCCESS.
> +
> + @param FfsHeader Pointer to FFS header the loaded driver.
> + @param PeiServices Pointer to the PEI services.
> +
> + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +Tpm2DeviceLibConstructor (
> + VOID
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> +
> + Status = PeiServicesLocatePpi (&gPttPassThruPpiGuid, 0, NULL, (VOID **)
> &SecPttPassThruPpi);
> + if (EFI_ERROR (Status)) {
> + // Locate the PPI failed
> + SecPttPassThruPpi = NULL;
> + }
> + return Status;
> +}
> +
> +/**
> + This service enables the sending of commands to the TPM2.
> +
> + @param[in] InputParameterBlockSize Size of the TPM2 input parameter
> block.
> + @param[in] InputParameterBlock Pointer to the TPM2 input parameter
> block.
> + @param[in] OutputParameterBlockSize Size of the TPM2 output
> parameter block.
> + @param[in] OutputParameterBlock Pointer to the TPM2 output
> parameter block.
> +
> + @retval EFI_SUCCESS The command byte stream was successfully
> sent to the device and a response was successfully received.
> + @retval EFI_DEVICE_ERROR The command was not successfully sent to
> the device or a response was not successfully received from the device.
> + @retval EFI_BUFFER_TOO_SMALL The output parameter block is too
> small.
> +**/
> +EFI_STATUS
> +EFIAPI
> +Tpm2SubmitCommand (
> + IN UINT32 InputParameterBlockSize,
> + IN UINT8 *InputParameterBlock,
> + IN OUT UINT32 *OutputParameterBlockSize,
> + IN UINT8 *OutputParameterBlock
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> +
> + if(NULL == InputParameterBlock || NULL == OutputParameterBlock || 0
> == InputParameterBlockSize) {
> + DEBUG ((EFI_D_ERROR, "Buffer == NULL or InputParameterBlockSize ==
> 0\n"));
> + Status = EFI_INVALID_PARAMETER;
> + return Status;
> + }
> +
> + if (NULL == SecPttPassThruPpi) {
> + // Don't locate PPI by calling Tpm2DeviceLibConstructor() function??
> + Status = EFI_DEVICE_ERROR;
> + return Status;
> + }
> +
> + Status = SecPttPassThruPpi->Tpm2SubmitCommand (
> + SecPttPassThruPpi,
> + InputParameterBlockSize,
> + InputParameterBlock,
> + OutputParameterBlockSize,
> + OutputParameterBlock
> + );
> +
> + return Status;
> +}
> +
> +/**
> + This service requests use TPM2.
> +
> + @retval EFI_SUCCESS Get the control of TPM2 chip.
> + @retval EFI_NOT_FOUND TPM2 not found.
> + @retval EFI_DEVICE_ERROR Unexpected device behavior.
> +**/
> +EFI_STATUS
> +EFIAPI
> +Tpm2RequestUseTpm (
> + VOID
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> +
> + if (NULL == SecPttPassThruPpi) {
> + // Don't locate PPI by calling Tpm2DeviceLibConstructor() function??
> + Status = EFI_DEVICE_ERROR;
> + return Status;
> + }
> +
> + Status = SecPttPassThruPpi->Tpm2RequestUseTpm (SecPttPassThruPpi);
> +
> + return Status;
> +}
> +
> +/**
> + This service register TPM2 device.
> +
> + @Param Tpm2Device TPM2 device
> +
> + @retval EFI_SUCCESS This TPM2 device is registered successfully.
> + @retval EFI_UNSUPPORTED System does not support register this TPM2
> device.
> + @retval EFI_ALREADY_STARTED System already register this TPM2 device.
> +**/
> +EFI_STATUS
> +EFIAPI
> +Tpm2RegisterTpm2DeviceLib (
> + IN PTT_TPM2_DEVICE_INTERFACE *Tpm2Device
> + )
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2Dev
> iceLibSeC.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2Dev
> iceLibSeC.inf
> new file mode 100644
> index 0000000000..a9b2948597
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2Dev
> iceLibSeC.inf
> @@ -0,0 +1,60 @@
> +#/** @file
> +#
> +#
> +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#
> +#
> +#**/
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = Tpm2DeviceLibSeC
> + FILE_GUID = 1EEA2BFE-01CB-40cc-A34E-CB224C800AA2
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = Tpm2DeviceLib | PEI_DRIVER PEIM
> + CONSTRUCTOR = Tpm2DeviceLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources.common]
> + Tpm2DeviceLibSeC.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + SecurityPkg/SecurityPkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + MemoryAllocationLib
> + DebugLib
> + IoLib
> + PciLib
> + TimerLib
> + PcdLib
> + PeiServicesLib
> + PeimEntryPoint
> +
> +
> +[Guids]
> +
> +[Ppis]
> + gPttPassThruPpiGuid
> +
> +[Depex]
> + gPttPassThruPpiGuid
> +
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Logo/Logo.bmp
> b/Platform/Intel/Vlv2TbltDevicePkg/Logo/Logo.bmp
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..26ac1a81dad1de6c6f94c27b91
> d448300a339059
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> zCK*a`*wcDLz1Dy*3Jc-
> @aA4&GWK_O&32SP9+D8h|O!QhrsMEb)n}+TsSoX1|?#ZO?
> zo=yu8^ou&B<q?t+-
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> A#W
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> jN~lFIUe~+Y8QIFf)Y5|bke9SMIb=%YtUEAjQ6#h;vG?}L at E|s7
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>
> literal 0
> HcmV?d00001
>
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.c
> new file mode 100644
> index 0000000000..b1fb4adb34
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.c
> @@ -0,0 +1,185 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + LegacyMetronome.c
> +
> +Abstract:
> +
> + This contains the installation function for the driver.
> +
> +--*/
> +
> +#include "LegacyMetronome.h"
> +
> +//
> +// Handle for the Metronome Architectural Protocol instance produced by
> this driver
> +//
> +EFI_HANDLE mMetronomeHandle = NULL;
> +
> +//
> +// The Metronome Architectural Protocol instance produced by this driver
> +//
> +EFI_METRONOME_ARCH_PROTOCOL mMetronome = {
> + WaitForTick,
> + TICK_PERIOD
> +};
> +
> +//
> +// The CPU I/O Protocol used to access system hardware
> +//
> +EFI_CPU_IO_PROTOCOL *mCpuIo = NULL;
> +
> +//
> +// Worker Functions
> +//
> +
> +/**
> + Write an 8 bit value to an I/O port and save it to the S3 script
> +
> + @param Port IO Port
> + @param Data Data in IO Port
> +
> + @retval None.
> +
> +**/
> +VOID
> +ScriptWriteIo8 (
> + UINT16 Port,
> + UINT8 Data
> + )
> +{
> + mCpuIo->Io.Write (
> + mCpuIo,
> + EfiCpuIoWidthUint8,
> + Port,
> + 1,
> + &Data
> + );
> +
> +}
> +
> +/**
> +
> + Read the refresh bit from the REFRESH_PORT
> +
> + @param None.
> +
> + @retval Refresh bit.
> +
> +**/
> +UINT8
> +ReadRefresh (
> + VOID
> + )
> +{
> + UINT8 Data;
> +
> + mCpuIo->Io.Read (
> + mCpuIo,
> + EfiCpuIoWidthUint8,
> + REFRESH_PORT,
> + 1,
> + &Data
> + );
> + return (UINT8) (Data & REFRESH_ON);
> +}
> +
> +/**
> +
> + Waits for the TickNumber of ticks from a known platform time source.
> +
> + @param This Pointer to the protocol instance.
> + @param TickNumber Tick Number to be waited
> +
> +
> + @retval EFI_SUCCESS If number of ticks occurred.
> + @retval EFI_NOT_FOUND Could not locate CPU IO protocol
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +WaitForTick (
> + IN EFI_METRONOME_ARCH_PROTOCOL *This,
> + IN UINT32 TickNumber
> + )
> +{
> + //
> + // Wait for TickNumber toggles of the Refresh bit
> + //
> + for (; TickNumber != 0x00; TickNumber--) {
> + while (ReadRefresh () == REFRESH_ON)
> + ;
> + while (ReadRefresh () == REFRESH_OFF)
> + ;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +//
> +// Driver Entry Point
> +//
> +/**
> + Install the LegacyMetronome driver. Loads a Metronome Arch Protocol
> based
> + on the Port 61 timer.
> +
> + @param ImageHandle Handle for the image of this driver
> + @param SystemTable Pointer to the EFI System Table
> +
> + @retval EFI_SUCCESS Metronome Architectural Protocol Installed
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InstallLegacyMetronome (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> +
> + //
> + // Make sure the Metronome Architectural Protocol is not already installed
> in the system
> + //
> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL,
> &gEfiMetronomeArchProtocolGuid);
> +
> + //
> + // Get the CPU I/O Protocol that this driver requires
> + // If the CPU I/O Protocol is not found, then ASSERT because the
> dependency expression
> + // should guarantee that it is present in the handle database.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiCpuIoProtocolGuid,
> + NULL,
> + (void **)&mCpuIo
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Program port 61 timer 1 as refresh timer. We could use ACPI timer in the
> + // future.
> + //
> + ScriptWriteIo8 (TIMER1_CONTROL_PORT, LOAD_COUNTER1_LSB);
> + ScriptWriteIo8 (TIMER1_COUNT_PORT, COUNTER1_COUNT);
> +
> + //
> + // Install on a new handle
> + //
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &mMetronomeHandle,
> + &gEfiMetronomeArchProtocolGuid,
> + &mMetronome,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.h
> new file mode 100644
> index 0000000000..9599eca702
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.h
> @@ -0,0 +1,64 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + LegacyMetronome.h
> +
> +Abstract:
> +
> + Driver implementing the EFI 2.0 metronome protocol using the legacy
> PORT 61
> + timer.
> +
> +--*/
> +
> +#ifndef _LEGACY_METRONOME_H
> +#define _LEGACY_METRONOME_H
> +
> +//
> +// Statements that include other files
> +//
> +#include "Protocol/Metronome.h"
> +#include "Protocol/CpuIo.h"
> +#include "Library/DebugLib.h"
> +#include "Library/UefiBootServicesTableLib.h"
> +
> +
> +//
> +// Private definitions
> +//
> +#define TICK_PERIOD 300
> +#define REFRESH_PORT 0x61
> +#define REFRESH_ON 0x10
> +#define REFRESH_OFF 0x00
> +#define TIMER1_CONTROL_PORT 0x43
> +#define TIMER1_COUNT_PORT 0x41
> +#define LOAD_COUNTER1_LSB 0x54
> +#define COUNTER1_COUNT 0x12
> +
> +//
> +// Function Prototypes
> +//
> +/**
> + Waits for the TickNumber of ticks from a known platform time source.
> +
> + @param This Pointer to the protocol instance.
> + @param TickNumber Tick Number to be waited
> +
> + @retval EFI_SUCCESS If number of ticks occurred.
> + @retval EFI_NOT_FOUND Could not locate CPU IO protocol
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +WaitForTick (
> + IN EFI_METRONOME_ARCH_PROTOCOL *This,
> + IN UINT32 TickNumber
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Metronome/Metronome.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Metronome/Metronome.inf
> new file mode 100644
> index 0000000000..173370d652
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Metronome/Metronome.inf
> @@ -0,0 +1,49 @@
> +#
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +
> +# Module Name:
> +#
> +# LegacyMetronome.inf
> +#
> +# Abstract:
> +#
> +# Component description file for LegacyMetronome module
> +#
> +#--*/
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = LegacyMetronome
> + FILE_GUID = 07A9330A-F347-11d4-9A49-0090273FC14D
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = InstallLegacyMetronome
> +
> +[sources.common]
> + LegacyMetronome.c
> + LegacyMetronome.h
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> +
> +[LibraryClasses]
> + UefiDriverEntryPoint
> + UefiBootServicesTableLib
> + DevicePathLib
> + UefiLib
> +
> +[Protocols]
> +
> +gEfiMetronomeArchProtocolGuid
> +gEfiCpuIoProtocolGuid
> +
> +[Depex]
> +gEfiCpuIoProtocolGuid AND gEfiBootScriptSaveProtocolGuid
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/EfiStatusCode.h
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/EfiStatusCode.h
> new file mode 100644
> index 0000000000..1d396ffde2
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/EfiStatusCode.h
> @@ -0,0 +1,178 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + EfiStatusCode.h
> +
> +Abstract:
> +
> + Status Code Definitions, according to Intel Platform Innovation Framework
> + for EFI Status Codes Specification
> + Revision 0.92
> +
> + The file is divided into sections for ease of use.
> +
> + Section: Contents:
> + 1 General Status Code Definitions
> + 2 Class definitions
> + 3 Computing Unit Subclasses, Progress and Error Codes
> + 4 Peripheral Subclasses, Progress and Error Codes.
> + 5 IO Bus Subclasses, Progress and Error Codes.
> + 6 Software Subclasses, Progress and Error Codes.
> + 7 Debug Codes
> +
> +--*/
> +
> +#ifndef _EFI_STATUS_CODE_H_
> +#define _EFI_STATUS_CODE_H_
> +
> +
> +
> +#define EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE
> (EFI_SUBCLASS_SPECIFIC | 0x00000000)
> +#define EFI_SW_PEIM_EC_INVALID_CAPSULE_DESCRIPTOR
> (EFI_SUBCLASS_SPECIFIC | 0x00000001)
> +
> +
> +
> +#define EFI_SW_PEIM_PC_RECOVERY_BEGIN (EFI_SUBCLASS_SPECIFIC |
> 0x00000000)
> +#define EFI_SW_PEIM_PC_CAPSULE_LOAD (EFI_SUBCLASS_SPECIFIC |
> 0x00000001)
> +#define EFI_SW_PEIM_PC_CAPSULE_START (EFI_SUBCLASS_SPECIFIC |
> 0x00000002)
> +#define EFI_SW_PEIM_PC_RECOVERY_USER (EFI_SUBCLASS_SPECIFIC |
> 0x00000003)
> +#define EFI_SW_PEIM_PC_RECOVERY_AUTO (EFI_SUBCLASS_SPECIFIC |
> 0x00000004)
> +
> +
> +
> +#define EFI_CU_MEMORY_PC_SPD_READ (EFI_SUBCLASS_SPECIFIC |
> 0x00000000)
> +#define EFI_CU_MEMORY_PC_PRESENCE_DETECT
> (EFI_SUBCLASS_SPECIFIC | 0x00000001)
> +#define EFI_CU_MEMORY_PC_TIMING (EFI_SUBCLASS_SPECIFIC |
> 0x00000002)
> +#define EFI_CU_MEMORY_PC_CONFIGURING (EFI_SUBCLASS_SPECIFIC
> | 0x00000003)
> +#define EFI_CU_MEMORY_PC_OPTIMIZING (EFI_SUBCLASS_SPECIFIC |
> 0x00000004)
> +#define EFI_CU_MEMORY_PC_INIT (EFI_SUBCLASS_SPECIFIC |
> 0x00000005)
> +#define EFI_CU_MEMORY_PC_TEST (EFI_SUBCLASS_SPECIFIC |
> 0x00000006)
> +#define EFI_CU_MEMORY_PC_COMPLETE (EFI_SUBCLASS_SPECIFIC |
> 0x00000007)
> +#define EFI_CU_MEMORY_PC_INIT_BEGIN (EFI_SUBCLASS_SPECIFIC |
> 0x00000008)
> +
> +
> +#define EFI_DC_UNSPECIFIED 0x0
> +
> +//
> +// CPU PEI
> +//
> +#define EFI_CU_HP_PC_PEI_INIT (EFI_SUBCLASS_SPECIFIC |
> 0x00000010)
> +#define EFI_CU_HP_PC_PEI_STEP1 (EFI_SUBCLASS_SPECIFIC |
> 0x00000011)
> +#define EFI_CU_HP_PC_PEI_STEP2 (EFI_SUBCLASS_SPECIFIC |
> 0x00000012)
> +#define EFI_CU_HP_PC_PEI_STEP3 (EFI_SUBCLASS_SPECIFIC |
> 0x00000013)
> +#define EFI_CU_HP_PC_PEI_STEP4 (EFI_SUBCLASS_SPECIFIC |
> 0x00000014)
> +#define EFI_CU_HP_PC_PEI_STEP5 (EFI_SUBCLASS_SPECIFIC |
> 0x00000015)
> +#define EFI_CU_HP_PC_PEI_STEP6 (EFI_SUBCLASS_SPECIFIC |
> 0x00000016)
> +#define EFI_CU_HP_PC_PEI_STEP7 (EFI_SUBCLASS_SPECIFIC |
> 0x00000017)
> +#define EFI_CU_HP_PC_PEI_STEP8 (EFI_SUBCLASS_SPECIFIC |
> 0x00000018)
> +#define EFI_CU_HP_PC_PEI_STEP9 (EFI_SUBCLASS_SPECIFIC |
> 0x00000019)
> +#define EFI_CU_HP_PC_PEI_STEP10 (EFI_SUBCLASS_SPECIFIC |
> 0x0000001A)
> +#define EFI_CU_HP_PC_PEI_STEP11 (EFI_SUBCLASS_SPECIFIC |
> 0x0000001B)
> +#define EFI_CU_HP_PC_PEI_STEP12 (EFI_SUBCLASS_SPECIFIC |
> 0x0000001C)
> +#define EFI_CU_HP_PC_PEI_STEP13 (EFI_SUBCLASS_SPECIFIC |
> 0x0000001D)
> +#define EFI_CU_HP_PC_PEI_STEP14 (EFI_SUBCLASS_SPECIFIC |
> 0x0000001E)
> +#define EFI_CU_HP_PC_PEI_END (EFI_SUBCLASS_SPECIFIC |
> 0x0000001F)
> +
> +//
> +// CPU DXE
> +//
> +#define EFI_CU_HP_PC_DXE_INIT (EFI_SUBCLASS_SPECIFIC |
> 0x00000020)
> +#define EFI_CU_HP_PC_DXE_STEP1 (EFI_SUBCLASS_SPECIFIC |
> 0x00000021)
> +#define EFI_CU_HP_PC_DXE_STEP2 (EFI_SUBCLASS_SPECIFIC |
> 0x00000022)
> +#define EFI_CU_HP_PC_DXE_STEP3 (EFI_SUBCLASS_SPECIFIC |
> 0x00000023)
> +#define EFI_CU_HP_PC_DXE_STEP4 (EFI_SUBCLASS_SPECIFIC |
> 0x00000024)
> +#define EFI_CU_HP_PC_DXE_STEP5 (EFI_SUBCLASS_SPECIFIC |
> 0x00000025)
> +#define EFI_CU_HP_PC_DXE_STEP6 (EFI_SUBCLASS_SPECIFIC |
> 0x00000026)
> +#define EFI_CU_HP_PC_DXE_STEP7 (EFI_SUBCLASS_SPECIFIC |
> 0x00000027)
> +#define EFI_CU_HP_PC_DXE_STEP8 (EFI_SUBCLASS_SPECIFIC |
> 0x00000028)
> +#define EFI_CU_HP_PC_DXE_STEP9 (EFI_SUBCLASS_SPECIFIC |
> 0x00000029)
> +#define EFI_CU_HP_PC_DXE_STEP10 (EFI_SUBCLASS_SPECIFIC |
> 0x0000002A)
> +#define EFI_CU_HP_PC_DXE_STEP11 (EFI_SUBCLASS_SPECIFIC |
> 0x0000002B)
> +#define EFI_CU_HP_PC_DXE_STEP12 (EFI_SUBCLASS_SPECIFIC |
> 0x0000002C)
> +#define EFI_CU_HP_PC_DXE_STEP13 (EFI_SUBCLASS_SPECIFIC |
> 0x0000002D)
> +#define EFI_CU_HP_PC_DXE_STEP14 (EFI_SUBCLASS_SPECIFIC |
> 0x0000002E)
> +#define EFI_CU_HP_PC_DXE_END (EFI_SUBCLASS_SPECIFIC |
> 0x0000002F)
> +
> +//
> +// CPU SMM PEI
> +//
> +#define EFI_CU_HP_PC_SMM_PEI_INIT (EFI_SUBCLASS_SPECIFIC |
> 0x00000030)
> +#define EFI_CU_HP_PC_SMM_PEI_STEP1 (EFI_SUBCLASS_SPECIFIC
> | 0x00000031)
> +#define EFI_CU_HP_PC_SMM_PEI_STEP2 (EFI_SUBCLASS_SPECIFIC
> | 0x00000032)
> +#define EFI_CU_HP_PC_SMM_PEI_STEP3 (EFI_SUBCLASS_SPECIFIC
> | 0x00000033)
> +#define EFI_CU_HP_PC_SMM_PEI_STEP4 (EFI_SUBCLASS_SPECIFIC
> | 0x00000034)
> +#define EFI_CU_HP_PC_SMM_PEI_STEP5 (EFI_SUBCLASS_SPECIFIC
> | 0x00000035)
> +#define EFI_CU_HP_PC_SMM_PEI_STEP6 (EFI_SUBCLASS_SPECIFIC
> | 0x00000036)
> +#define EFI_CU_HP_PC_SMM_PEI_END (EFI_SUBCLASS_SPECIFIC
> | 0x0000003F)
> +
> +//
> +// CPU SMM DXE
> +//
> +#define EFI_CU_HP_PC_SMM_DXE_INIT (EFI_SUBCLASS_SPECIFIC
> | 0x00000040)
> +#define EFI_CU_HP_PC_SMM_DXE_STEP1
> (EFI_SUBCLASS_SPECIFIC | 0x00000041)
> +#define EFI_CU_HP_PC_SMM_DXE_STEP2
> (EFI_SUBCLASS_SPECIFIC | 0x00000042)
> +#define EFI_CU_HP_PC_SMM_DXE_STEP3
> (EFI_SUBCLASS_SPECIFIC | 0x00000043)
> +#define EFI_CU_HP_PC_SMM_DXE_STEP4
> (EFI_SUBCLASS_SPECIFIC | 0x00000044)
> +#define EFI_CU_HP_PC_SMM_DXE_STEP5
> (EFI_SUBCLASS_SPECIFIC | 0x00000045)
> +#define EFI_CU_HP_PC_SMM_DXE_STEP6
> (EFI_SUBCLASS_SPECIFIC | 0x00000046)
> +#define EFI_CU_HP_PC_SMM_DXE_END (EFI_SUBCLASS_SPECIFIC
> | 0x0000004F)
> +
> +//
> +// PEI before memory initialization
> +//
> +#define EFI_CU_PLATFORM_PEI_INIT (EFI_OEM_SPECIFIC |
> 0x00000001)
> +#define EFI_CU_PLATFORM_PEI_STEP1 (EFI_OEM_SPECIFIC |
> 0x00000002)
> +#define EFI_CU_PLATFORM_PEI_STEP2 (EFI_OEM_SPECIFIC |
> 0x00000003)
> +#define EFI_CU_PLATFORM_PEI_STEP3 (EFI_OEM_SPECIFIC |
> 0x00000004)
> +#define EFI_CU_PLATFORM_PEI_STEP4 (EFI_OEM_SPECIFIC |
> 0x00000005)
> +#define EFI_CU_SMBUS_PEI_INIT (EFI_OEM_SPECIFIC |
> 0x00000006)
> +#define EFI_CU_SMBUS_PEI_EXEC_ENTRY (EFI_OEM_SPECIFIC |
> 0x00000007)
> +#define EFI_CU_SMBUS_PEI_EXEC_EXIT (EFI_OEM_SPECIFIC |
> 0x00000008)
> +#define EFI_CU_CLOCK_PEI_INIT_ENTRY (EFI_OEM_SPECIFIC |
> 0x00000009)
> +#define EFI_CU_CLOCK_PEI_INIT_EXIT (EFI_OEM_SPECIFIC |
> 0x0000000A)
> +#define EFI_CU_MEMORY_PC_PROG_MTRR (EFI_OEM_SPECIFIC |
> 0x0000000B)
> +#define EFI_CU_MEMORY_PC_PROG_MTRR_END
> (EFI_OEM_SPECIFIC | 0x0000000C)
> +#define EFI_CU_PLATFORM_PEI_STEP12 (EFI_OEM_SPECIFIC |
> 0x0000000D)
> +#define EFI_CU_PLATFORM_PEI_STEP13 (EFI_OEM_SPECIFIC |
> 0x0000000E)
> +#define EFI_CU_PLATFORM_PEI_END (EFI_OEM_SPECIFIC |
> 0x0000000F)
> +
> +#define EFI_CU_PLATFORM_DXE_INIT (EFI_OEM_SPECIFIC |
> 0x00000011)
> +#define EFI_CU_PLATFORM_DXE_STEP1 (EFI_OEM_SPECIFIC |
> 0x00000012)
> +#define EFI_CU_PLATFORM_DXE_STEP2 (EFI_OEM_SPECIFIC |
> 0x00000013)
> +#define EFI_CU_PLATFORM_DXE_STEP3 (EFI_OEM_SPECIFIC |
> 0x00000014)
> +#define EFI_CU_PLATFORM_DXE_STEP4 (EFI_OEM_SPECIFIC |
> 0x00000015)
> +#define EFI_CU_PLATFORM_DXE_INIT_DONE (EFI_OEM_SPECIFIC |
> 0x00000016)
> +
> +#define EFI_CU_OVERCLOCK_PEI_INIT_ENTRY (EFI_OEM_SPECIFIC |
> 0x00000017)
> +#define EFI_CU_OVERCLOCK_PEI_INIT_EXIT (EFI_OEM_SPECIFIC |
> 0x00000018)
> +
> +//
> +// BDS
> +//
> +#define EFI_CU_BDS_INIT (EFI_OEM_SPECIFIC | 0x00000060)
> +#define EFI_CU_BDS_STEP1 (EFI_OEM_SPECIFIC |
> 0x00000061)
> +#define EFI_CU_BDS_STEP2 (EFI_OEM_SPECIFIC |
> 0x00000062)
> +#define EFI_CU_BDS_STEP3 (EFI_OEM_SPECIFIC |
> 0x00000063)
> +#define EFI_CU_BDS_STEP4 (EFI_OEM_SPECIFIC |
> 0x00000064)
> +#define EFI_CU_BDS_STEP5 (EFI_OEM_SPECIFIC |
> 0x00000065)
> +#define EFI_CU_BDS_STEP6 (EFI_OEM_SPECIFIC |
> 0x00000066)
> +#define EFI_CU_BDS_STEP7 (EFI_OEM_SPECIFIC |
> 0x00000067)
> +#define EFI_CU_BDS_STEP8 (EFI_OEM_SPECIFIC |
> 0x00000068)
> +#define EFI_CU_BDS_STEP9 (EFI_OEM_SPECIFIC |
> 0x00000069)
> +#define EFI_CU_BDS_STEP10 (EFI_OEM_SPECIFIC |
> 0x0000006A)
> +#define EFI_CU_BDS_STEP11 (EFI_OEM_SPECIFIC |
> 0x0000006B)
> +#define EFI_CU_BDS_STEP12 (EFI_OEM_SPECIFIC |
> 0x0000006C)
> +#define EFI_CU_BDS_STEP13 (EFI_OEM_SPECIFIC |
> 0x0000006D)
> +#define EFI_CU_BDS_STEP14 (EFI_OEM_SPECIFIC |
> 0x0000006E)
> +#define EFI_CU_BDS_END (EFI_OEM_SPECIFIC | 0x0000006F)
> +
> +
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.c
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.c
> new file mode 100644
> index 0000000000..8283483ff8
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.c
> @@ -0,0 +1,132 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + MonoStatusCode.c
> +
> +Abstract:
> +
> + PEIM to provide the status code functionality, to aid in system debug.
> + It includes output to 0x80 port and/or to serial port.
> + This PEIM is monolithic. Different platform should provide different library.
> +
> +--*/
> +
> +#include "MonoStatusCode.h"
> +#include "PlatformStatusCode.h"
> +#define CMOS_EFI_DEBUG 0x14
> +
> +//
> +// Module globals
> +//
> +EFI_PEI_PROGRESS_CODE_PPI mStatusCodePpi =
> { PlatformReportStatusCode };
> +
> +EFI_PEI_PPI_DESCRIPTOR mPpiListStatusCode = {
> + (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gEfiPeiStatusCodePpiGuid,
> + &mStatusCodePpi
> +};
> +
> +//
> +// Function implemenations
> +//
> +
> +/**
> + Translate from a DXE status code interface into a PEI-callable
> + interface, making the PEI the least common denominator..
> +
> + Same as DXE ReportStatusCode RT service
> +
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +TranslateDxeStatusCodeToPeiStatusCode (
> + IN EFI_STATUS_CODE_TYPE CodeType,
> + IN EFI_STATUS_CODE_VALUE Value,
> + IN UINT32 Instance,
> + IN EFI_GUID * CallerId,
> + IN EFI_STATUS_CODE_DATA * Data OPTIONAL
> + )
> +{
> + return PlatformReportStatusCode (NULL, CodeType, Value, Instance,
> CallerId, Data);
> +}
> +
> +/**
> + Build a hob describing the status code listener that has been installed.
> + This will be used by DXE code until a runtime status code listener is
> + installed.
> +
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval Status EFI_SUCCESS if the interface could be successfully
> + installed
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeDxeReportStatusCode (
> + IN const EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status = EFI_UNSUPPORTED;
> +
> + VOID *Instance;
> +
> + VOID *Result;
> +
> + Instance = (VOID *) (UINTN) TranslateDxeStatusCodeToPeiStatusCode;
> +
> + Result = BuildGuidDataHob (
> + &gEfiStatusCodeRuntimeProtocolGuid,
> + &Instance,
> + sizeof (VOID *)
> + );
> + if (Result != NULL) {
> + Status = EFI_SUCCESS;
> + }
> + return Status;
> +}
> +
> +/**
> + Initialize the platform status codes and publish the platform status code
> + PPI.
> +
> + @param FfsHeader FV this PEIM was loaded from.
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval Status EFI_SUCCESS
> +
> +**/
> +VOID
> +EFIAPI
> +InitializeMonoStatusCode (
> + IN EFI_FFS_FILE_HEADER *FfsHeader,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> +
> + //
> + // Initialize status code listeners.
> + //
> + PlatformInitializeStatusCode (FfsHeader, PeiServices);
> +
> + //
> + // Publish the status code capability to other modules
> + //
> + Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiListStatusCode);
> +
> + ASSERT_EFI_ERROR (Status);
> +
> + DEBUG ((DEBUG_ERROR, "\nMono Status Code PEIM Loaded\n"));
> +
> + return ;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.h
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.h
> new file mode 100644
> index 0000000000..0b256093a6
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.h
> @@ -0,0 +1,128 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + MonoStatusCode.h
> +
> +Abstract:
> +
> + Monolithic single PEIM to provide the status code functionality.
> + The PEIM is a blend of libraries that correspond to the different status
> code
> + listeners that a platform installs.
> +
> +--*/
> +
> +#ifndef _MONO_STATUS_CODE_H_
> +#define _MONO_STATUS_CODE_H_
> +
> +//
> +// Statements that include other files.
> +//
> +#include "PiPei.h"
> +
> +#include "Pi/PiBootMode.h"
> +
> +#include "Ppi/StatusCode.h"
> +#include "Ppi/MemoryDiscovered.h"
> +#include "Ppi/FvLoadFile.h"
> +
> +#include "Library/HobLib.h"
> +#include "Library/DebugLib.h"
> +#include "Library/IoLib.h"
> +#include "Library/SerialPortLib.h"
> +#include "Protocol/StatusCode.h"
> +
> +
> +#ifndef _STATUS_CODE_ENABLER_H_
> +#define _STATUS_CODE_ENABLER_H_
> +
> +#ifdef EFI_DEBUG
> +
> +#define EFI_STATUS_CODE_ENABLER_HOB_GUID \
> + { \
> + 0x5ffc6cf3, 0x71ad, 0x46f5, 0xbd, 0x8b, 0x7e, 0x8f, 0xfe, 0x19, 0x7, 0xd7 \
> + }
> +
> +extern EFI_GUID gEfiSerialStatusCodeEnablerHobGuid;
> +
> +typedef struct _EFI_STATUS_CODE_INFO {
> + BOOLEAN StatusCodeDisable;
> +} EFI_STATUS_CODE_INFO;
> +
> +#endif
> +#endif
> +
> +
> +
> +//
> +// Platform specific function Declarations. These must be implemented in a
> +// subdirectory named PlatformName in a file named PlatformStatusCode.c.
> +//
> +
> +//
> +// This is the platform function to initialize the listeners desired by the
> +// platform.
> +//
> +VOID
> +PlatformInitializeStatusCode (
> + IN EFI_FFS_FILE_HEADER *FfsHeader,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +//
> +// This is the platform function that calls all of the listeners desired by the
> +// platform.
> +//
> +EFI_STATUS
> +EFIAPI
> +PlatformReportStatusCode (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_STATUS_CODE_TYPE CodeType,
> + IN EFI_STATUS_CODE_VALUE Value,
> + IN UINT32 Instance,
> + IN CONST EFI_GUID * CallerId,
> + IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL
> + );
> +
> +//
> +// Platform independent function Declarations
> +//
> +//
> +// Initialize the status code listeners and publish the status code PPI.
> +//
> +VOID
> +EFIAPI
> +InitializeMonoStatusCode (
> + IN EFI_FFS_FILE_HEADER *FfsHeader,
> + IN const EFI_PEI_SERVICES **PeiServices
> + );
> +
> +//
> +// Convert a DXE status code call into a PEI status code call.
> +//
> +EFI_STATUS
> +EFIAPI
> +TranslateDxeStatusCodeToPeiStatusCode (
> + IN EFI_STATUS_CODE_TYPE CodeType,
> + IN EFI_STATUS_CODE_VALUE Value,
> + IN UINT32 Instance,
> + IN EFI_GUID * CallerId,
> + IN EFI_STATUS_CODE_DATA * Data OPTIONAL
> + );
> +
> +//
> +// Publish a HOB that contains the listener to be used by DXE.
> +//
> +EFI_STATUS
> +EFIAPI
> +InitializeDxeReportStatusCode (
> + IN const EFI_PEI_SERVICES **PeiServices
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.inf
> new file mode 100644
> index 0000000000..f1be5b8d6c
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.inf
> @@ -0,0 +1,72 @@
> +#
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +# Module Name:
> +#
> +# MonoStatusCode.inf
> +#
> +# Abstract:
> +#
> +# Component description file for Status Code PEI module
> +#
> +#--*/
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = MonoStatusCode
> + FILE_GUID = 4BB346D2-8076-4671-8BC9-7B95CBB9A6DF
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> +# ENTRY_POINT = InstallMonoStatusCode
> + LIBRARY_CLASS = MonoStatusCodeLib
> +
> +[sources.common]
> + MonoStatusCode.c
> + MonoStatusCode.h
> + PlatformStatusCode.c
> + PlatformStatusCode.h
> + PeiPostCode.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2SocBinPkg/Vlv2SocBinPkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> +
> +[LibraryClasses]
> + PeimEntryPoint
> + HobLib
> + DebugLib
> + SerialPortLib
> + ReportStatusCodeLib
> + PrintLib
> + BaseMemoryLib
> + PchPlatformLib
> +
> +[Ppis]
> + gEfiPeiMemoryDiscoveredPpiGuid
> + gEfiPeiStatusCodePpiGuid
> + gEfiPeiFvFileLoaderPpiGuid
> +
> +[Protocols]
> + gEfiStatusCodeRuntimeProtocolGuid
> +
> +[Pcd]
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam
> +
> +[Guids]
> + gEfiPlatformCpuInfoGuid
> + gEfiHtBistHobGuid
> + gEfiStatusCodeDataTypeStringGuid ## CONSUMES
> +
> +[Depex]
> + TRUE
> +
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/PeiPostCode.c
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/PeiPostCode.c
> new file mode 100644
> index 0000000000..92dbef551e
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/PeiPostCode.c
> @@ -0,0 +1,121 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + PeiPostCode.c
> +
> +Abstract:
> +
> + Worker functions for PostCode
> +
> +--*/
> +
> +#include "EfiStatusCode.h"
> +
> +#pragma pack(1)
> +typedef struct {
> + EFI_STATUS_CODE_VALUE StatusValue;
> + UINT8 Port80Value;
> +} EFI_STATUS_CODE_TO_PORT_80;
> +#pragma pack()
> +
> +//
> +// see Edk\Foundation\Library\EfiCommonLib\PostCode.c for DXE/BDS
> POST codes.
> +//
> +EFI_STATUS_CODE_TO_PORT_80 mPeiPort80Table[] = {
> + //
> + // Platform init
> + //
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_INIT,
> 0x11},
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP1,
> 0x12},
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP2,
> 0x13},
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP3,
> 0x14},
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP4,
> 0x15},
> +
> + //
> + // SMBUS
> + //
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_INIT, 0x16},
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_EXEC_ENTRY,
> 0x17},
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_EXEC_EXIT,
> 0x18},
> +
> + //
> + // Clock
> + //
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_ENTRY,
> 0x19},
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_EXIT,
> 0x1A},
> +
> + //
> + // Over clocking support
> + //
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_OVERCLOCK_PEI_INIT_ENTRY,
> 0x1B},
> + {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_OVERCLOCK_PEI_INIT_EXIT,
> 0x1C},
> +
> + //
> + // MRC
> + //
> + {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_INIT_BEGIN,
> 0x21},
> + {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_SPD_READ,
> 0x23},
> + {EFI_COMPUTING_UNIT_MEMORY |
> EFI_CU_MEMORY_PC_PRESENCE_DETECT, 0x24},
> + {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TIMING,
> 0x25},
> + {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_OPTIMIZING,
> 0x26},
> + {EFI_COMPUTING_UNIT_MEMORY |
> EFI_CU_MEMORY_PC_CONFIGURING, 0x27},
> + {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TEST,
> 0x28},
> + {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_COMPLETE,
> 0x29},
> +
> + //
> + // Platform Init after MRC
> + //
> + {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PROG_MTRR,
> 0x2A},
> + {EFI_COMPUTING_UNIT_MEMORY |
> EFI_CU_MEMORY_PC_PROG_MTRR_END, 0x2B},
> +
> + {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_BEGIN,
> 0x31},
> + {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_AUTO,
> 0x32},
> + {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_LOAD,
> 0x33},
> + {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_START,
> 0x34},
> + {EFI_SOFTWARE_PEI_MODULE |
> EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE, 0x35},
> +
> + {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_INIT,
> 0x41},
> + {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_STEP1,
> 0x42},
> + {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_END,
> 0x43},
> + {EFI_COMPUTING_UNIT_HOST_PROCESSOR |
> EFI_CU_HP_PC_SMM_PEI_INIT, 0x44},
> + {EFI_COMPUTING_UNIT_HOST_PROCESSOR |
> EFI_CU_HP_PC_SMM_PEI_STEP1, 0x45},
> + {EFI_COMPUTING_UNIT_HOST_PROCESSOR |
> EFI_CU_HP_PC_SMM_PEI_END, 0x46}
> +};
> +
> +BOOLEAN
> +PeiCodeTypeToPostCode (
> + IN EFI_STATUS_CODE_TYPE CodeType,
> + IN EFI_STATUS_CODE_VALUE Value,
> + OUT UINT8 *PostCode
> + )
> +{
> + UINTN Index;
> +
> + if (CodeType == EFI_PROGRESS_CODE) {
> + if ((Value == (EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_BEGIN)) ||
> + (Value == (EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_END)) ||
> + (Value == (EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_BEGIN)) ||
> + (Value == (EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_END))) {
> + return FALSE;
> + }
> + } else {
> + return FALSE;
> + }
> +
> + for (Index = 0; Index <
> sizeof(mPeiPort80Table)/sizeof(EFI_STATUS_CODE_TO_PORT_80); Index++)
> {
> + if (mPeiPort80Table[Index].StatusValue == Value) {
> + *PostCode = mPeiPort80Table[Index].Port80Value;
> + return TRUE;
> + }
> + }
> +
> + return FALSE;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.c
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.
> c
> new file mode 100644
> index 0000000000..a1abddc512
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.
> c
> @@ -0,0 +1,381 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + PlatformStatusCode.c
> +
> +Abstract:
> +
> + Contains Platform specific implementations required to use status codes.
> +
> +--*/
> +
> +#include "PlatformStatusCode.h"
> +#include <PchRegs.h>
> +#include <PlatformBaseAddresses.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/PcdLib.h>
> +
> +typedef struct {
> + EFI_STATUS_CODE_DATA DataHeader;
> + EFI_HANDLE Handle;
> +} PEIM_FILE_HANDLE_EXTENDED_DATA;
> +
> +#define CONFIG_PORT0 0x4E
> +#define PCI_IDX 0xCF8
> +#define PCI_DAT 0xCFC
> +
> +#define PCI_LPC_BASE (0x8000F800)
> +#define PCI_LPC_REG(x) (PCI_LPC_BASE + (x))
> +
> +//
> +// Function implementations
> +//
> +BOOLEAN
> +PeiCodeTypeToPostCode (
> + IN EFI_STATUS_CODE_TYPE CodeType,
> + IN EFI_STATUS_CODE_VALUE Value,
> + OUT UINT8 *PostCode
> + );
> +
> +/**
> + Provide a port 80 status code
> +
> + @param Same as ReportStatusCode PPI
> +
> + @retval EFI_SUCCESS Always returns success.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +Port80ReportStatusCode (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_STATUS_CODE_TYPE CodeType,
> + IN EFI_STATUS_CODE_VALUE Value,
> + IN UINT32 Instance,
> + IN CONST EFI_GUID *CallerId,
> + IN CONST EFI_STATUS_CODE_DATA *Data OPTIONAL
> + )
> +
> +{
> + EFI_STATUS Status;
> + EFI_FV_FILE_INFO FvFileInfo;
> + UINT16 Port80Code = 0;
> +
> + //
> + // Progress or error code, Output Port 80h card.
> + //
> + if (!PeiCodeTypeToPostCode (CodeType, Value, (UINT8 *)&Port80Code)) {
> + if ((Data != NULL) && (Value ==(EFI_SOFTWARE_PEI_CORE |
> EFI_SW_PC_INIT_BEGIN))){
> + Status = PeiServicesFfsGetFileInfo (
> + ((PEIM_FILE_HANDLE_EXTENDED_DATA *) (Data + 1))->Handle,
> + &FvFileInfo
> + );
> + if (!EFI_ERROR (Status)) {
> + Port80Code = (FvFileInfo.FileName.Data4[6]<<8) +
> (FvFileInfo.FileName.Data4[7]);
> + }
> + }
> + }
> + if (Port80Code != 0){
> + IoWrite16 (0x80, (UINT16) Port80Code);
> + DEBUG ((EFI_D_ERROR, "POSTCODE=<%04x>\n", Port80Code));
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Provide a serial status code
> +
> + @param Same as ReportStatusCode PPI
> +
> + @retval EFI_SUCCESS Always returns success.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SerialReportStatusCode (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_STATUS_CODE_TYPE CodeType,
> + IN EFI_STATUS_CODE_VALUE Value,
> + IN UINT32 Instance,
> + IN CONST EFI_GUID * CallerId,
> + IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL
> + )
> +{
> + CHAR8 *Filename;
> + CHAR8 *Description;
> + CHAR8 *Format;
> + CHAR8 Buffer[EFI_STATUS_CODE_DATA_MAX_SIZE];
> + UINT32 ErrorLevel;
> + UINT32 LineNumber;
> + UINTN CharCount;
> + BASE_LIST Marker;
> +
> + Buffer[0] = '\0';
> +
> + if (Data != NULL &&
> + ReportStatusCodeExtractAssertInfo (CodeType, Value, Data, &Filename,
> &Description, &LineNumber)) {
> + //
> + // Print ASSERT() information into output buffer.
> + //
> + CharCount = AsciiSPrint (
> + Buffer,
> + sizeof (Buffer),
> + "\n\rPEI_ASSERT!: %a (%d): %a\n\r",
> + Filename,
> + LineNumber,
> + Description
> + );
> + } else if (Data != NULL &&
> + ReportStatusCodeExtractDebugInfo (Data, &ErrorLevel, &Marker,
> &Format)) {
> + //
> + // Print DEBUG() information into output buffer.
> + //
> + CharCount = AsciiBSPrint (
> + Buffer,
> + sizeof (Buffer),
> + Format,
> + Marker
> + );
> + } else if ((CodeType & EFI_STATUS_CODE_TYPE_MASK) ==
> EFI_ERROR_CODE) {
> + //
> + // Print ERROR information into output buffer.
> + //
> + CharCount = AsciiSPrint (
> + Buffer,
> + sizeof (Buffer),
> + "ERROR: C%x:V%x I%x",
> + CodeType,
> + Value,
> + Instance
> + );
> +
> + ASSERT(CharCount > 0);
> +
> + if (CallerId != NULL) {
> + CharCount += AsciiSPrint (
> + &Buffer[CharCount],
> + (sizeof (Buffer) - (sizeof (Buffer[0]) * CharCount)),
> + " %g",
> + CallerId
> + );
> + }
> +
> + if (Data != NULL) {
> + CharCount += AsciiSPrint (
> + &Buffer[CharCount],
> + (sizeof (Buffer) - (sizeof (Buffer[0]) * CharCount)),
> + " %x",
> + Data
> + );
> + }
> +
> + CharCount += AsciiSPrint (
> + &Buffer[CharCount],
> + (sizeof (Buffer) - (sizeof (Buffer[0]) * CharCount)),
> + "\n\r"
> + );
> + } else if ((CodeType & EFI_STATUS_CODE_TYPE_MASK) ==
> EFI_PROGRESS_CODE) {
> + //
> + // Print PROGRESS information into output buffer.
> + //
> + CharCount = AsciiSPrint (
> + Buffer,
> + sizeof (Buffer),
> + "PROGRESS CODE: V%x I%x\n\r",
> + Value,
> + Instance
> + );
> + } else if (Data != NULL &&
> + CompareGuid (&Data->Type, &gEfiStatusCodeDataTypeStringGuid)
> &&
> + ((EFI_STATUS_CODE_STRING_DATA *) Data)->StringType ==
> EfiStringAscii) {
> + //
> + // EFI_STATUS_CODE_STRING_DATA
> + //
> + CharCount = AsciiSPrint (
> + Buffer,
> + sizeof (Buffer),
> + "%a\n\r",
> + ((EFI_STATUS_CODE_STRING_DATA *) Data)->String.Ascii
> + );
> + } else {
> + //
> + // Code type is not defined.
> + //
> + CharCount = AsciiSPrint (
> + Buffer,
> + sizeof (Buffer),
> + "Undefined: C%x:V%x I%x\n\r",
> + CodeType,
> + Value,
> + Instance
> + );
> + }
> +
> + //
> + // Call SerialPort Lib function to do print.
> + //
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +
> + Call all status code listeners in the MonoStatusCode.
> +
> + @param PeiServices The PEI core services table.
> + @param CodeType Type of Status Code.
> + @param Value Value to output for Status Code.
> + @param Instance Instance Number of this status code.
> + @param CallerId ID of the caller of this status code.
> + @param Data Optional data associated with this status code.
> +
> + @retval EFI_SUCCESS If status code is successfully reported.
> + @retval EFI_NOT_AVAILABLE_YET If StatusCodePpi has not been
> installed.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PlatformReportStatusCode (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_STATUS_CODE_TYPE CodeType,
> + IN EFI_STATUS_CODE_VALUE Value,
> + IN UINT32 Instance,
> + IN CONST EFI_GUID * CallerId,
> + IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL
> + )
> +{
> + //
> + // If we are in debug mode, we will allow serial status codes
> + //
> + SerialReportStatusCode (PeiServices, CodeType, Value, Instance, CallerId,
> Data);
> +
> + Port80ReportStatusCode (PeiServices, CodeType, Value, Instance, CallerId,
> Data);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Install the PEIM. Initialize listeners, publish the PPI and HOB for PEI and
> + DXE use respectively.
> +
> + @param FfsHeader FV this PEIM was loaded from.
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval EFI_SUCCESS The function always returns success.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InstallMonoStatusCode (
> + IN EFI_FFS_FILE_HEADER *FfsHeader,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> +
> + //
> + // Initialize all listeners
> + //
> + InitializeMonoStatusCode (FfsHeader, PeiServices);
> +
> + //
> + // Publish the listener in a HOB for DXE use.
> + //
> + InitializeDxeReportStatusCode (PeiServices);
> +
> + return EFI_SUCCESS;
> +}
> +
> +#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3
> Enable
> +#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4 BIT4 // UART IRQ4
> Enable
> +#define PCIEX_BASE_ADDRESS 0xE0000000
> +#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32)
> (31 << 15)
> +#define SB_RCBA 0xfed1c000
> +
> +extern PCH_STEPPING EFIAPI PchStepping (VOID);
> +
> +VOID
> +RamDebugInit (
> + VOID
> + );
> +
> +/**
> + Enable legacy decoding on ICH6
> +
> + @param none
> +
> + @retval EFI_SUCCESS Always returns success.
> +
> +**/
> +EFI_STATUS
> +EnableInternalUart(
> + VOID
> + )
> +{
> +
> + //
> + // Program and enable PMC Base.
> + //
> + IoWrite32 (PCI_IDX, PCI_LPC_REG(R_PCH_LPC_PMC_BASE));
> + IoWrite32 (PCI_DAT, (PMC_BASE_ADDRESS |
> B_PCH_LPC_PMC_BASE_EN));
> +
> + //
> + // Enable COM1 for debug message output.
> + //
> + MmioAndThenOr32 (PMC_BASE_ADDRESS +
> R_PCH_PMC_GEN_PMCON_1, (UINT32)
> (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR +
> B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);
> +
> + //
> + // Silicon Steppings
> + //
> + if (PchStepping()>= PchB0)
> + MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8)
> V_PCH_ILB_IRQE_UARTIRQEN_IRQ4);
> + else
> + MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8)
> V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);
> + MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));
> + MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L
> + MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));
> + MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L
> + MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8)
> B_PCH_LPC_UART_CTRL_COM1_EN);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + INIT the SIO. Ported this code and I don't undertand the comments either.
> +
> + @param FfsHeader FV this PEIM was loaded from.
> + @param PeiServices General purpose services available to every PEIM.
> +
> + None
> +
> +**/
> +VOID
> +EFIAPI
> +PlatformInitializeStatusCode (
> + IN EFI_FFS_FILE_HEADER *FfsHeader,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> +
> + //
> + // Enable internal COM1 on South Cluster.
> + //
> + EnableInternalUart();
> +
> +
> + //
> + // Initialize additional debug status code listeners.
> + //
> + SerialPortInitialize();
> +
> +}
> +//#endif //EFI_DEBUG
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.
> h
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.
> h
> new file mode 100644
> index 0000000000..42b7c9a2c8
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.
> h
> @@ -0,0 +1,138 @@
> +/*++
> +
> + Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +Module Name:
> +
> + PlatformStatusCode.h
> +
> +Abstract:
> +
> + Contains Platform specific implementations required to use status codes.
> +
> +--*/
> +
> +#ifndef _PLATFORM_STATUS_CODE_H_
> +#define _PLATFORM_STATUS_CODE_H_
> +
> +
> +#define CONFIG_PORT0 0x4E
> +#define INDEX_PORT0 0x4E
> +#define DATA_PORT0 0x4F
> +#define PCI_IDX 0xCF8
> +#define PCI_DAT 0xCFC
> +
> +#include "MonoStatusCode.h"
> +#ifndef _PEI_PORT_80_STATUS_CODE_H_
> +#define _PEI_PORT_80_STATUS_CODE_H_
> +
> +
> +
> +//
> +// Status code reporting function
> +//
> +EFI_STATUS
> +Port80ReportStatusCode (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_STATUS_CODE_TYPE CodeType,
> + IN EFI_STATUS_CODE_VALUE Value,
> + IN UINT32 Instance,
> + IN CONST EFI_GUID * CallerId,
> + IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL
> + );
> +
> +#endif
> +
> +#ifndef _PEI_SERIAL_STATUS_CODE_LIB_H_
> +#define _PEI_SERIAL_STATUS_CODE_LIB_H_
> +
> +
> +#include <Guid/StatusCodeDataTypeId.h>
> +#include <Guid/StatusCodeDataTypeDebug.h>
> +#include <Library/ReportStatusCodeLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/BaseMemoryLib.h>
> +
> +//
> +// Initialization function
> +//
> +VOID
> +SerialInitializeStatusCode (
> + VOID
> + );
> +
> +//
> +// Status code reporting function
> +//
> +EFI_STATUS
> +SerialReportStatusCode (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_STATUS_CODE_TYPE CodeType,
> + IN EFI_STATUS_CODE_VALUE Value,
> + IN UINT32 Instance,
> + IN CONST EFI_GUID * CallerId,
> + IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL
> + );
> +
> +#endif
> +
> +extern EFI_PEI_PROGRESS_CODE_PPI mStatusCodePpi;
> +extern EFI_PEI_PPI_DESCRIPTOR mPpiListStatusCode;
> +#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8))
> +#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) |
> (EFI_SIGNATURE_16 (C, D) << 16))
> +#define STATUSCODE_PEIM_SIGNATURE EFI_SIGNATURE_32 ('p', 's', 't', 'c')
> +
> +typedef struct {
> + UINT32 Signature;
> + EFI_FFS_FILE_HEADER *FfsHeader;
> + EFI_PEI_NOTIFY_DESCRIPTOR StatusCodeNotify;
> +} STATUSCODE_CALLBACK_STATE_INFORMATION;
> +
> +#pragma pack(1)
> +typedef struct {
> + UINT16 Limit;
> + UINT32 Base;
> +} GDT_DSCRIPTOR;
> +#pragma pack()
> +
> +#define STATUSCODE_PEIM_FROM_THIS(a) \
> + BASE_CR ( \
> + a, \
> + STATUSCODE_CALLBACK_STATE_INFORMATION, \
> + StatusCodeNotify \
> + )
> +
> +VOID
> +EFIAPI
> +PlatformInitializeStatusCode (
> + IN EFI_FFS_FILE_HEADER *FfsHeader,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +
> +//
> +// Function declarations
> +//
> +/**
> + Install Firmware Volume Hob's once there is main memory
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param NotifyDescriptor Not Used
> + @param Ppi Not Used
> +
> + @retval Status EFI_SUCCESS if the interface could be successfully
> + installed
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +MemoryDiscoveredPpiNotifyCallback (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsBoot.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsBoot.c
> new file mode 100644
> index 0000000000..3034853695
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsBoot.c
> @@ -0,0 +1,4490 @@
> +/** @file
> + BDS Lib functions which relate with create or process the boot option.
> +
> +Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "InternalBdsLib.h"
> +#include "String.h"
> +#include <Library/NetLib.h>
> +#include "Library/DebugLib.h"
> +
> +BOOLEAN mEnumBootDevice = FALSE;
> +EFI_HII_HANDLE gBdsLibStringPackHandle = NULL;
> +
> +/**
> +
> + End Perf entry of BDS
> +
> + @param Event The triggered event.
> + @param Context Context for this event.
> +
> +**/
> +VOID
> +EFIAPI
> +BmEndOfBdsPerfCode (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + //
> + // Record the performance data for End of BDS
> + //
> + PERF_END(NULL, "BDS", NULL, 0);
> +
> + return ;
> +}
> +
> +/**
> + The constructor function register UNI strings into imageHandle.
> +
> + It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
> +
> + @param ImageHandle The firmware allocated handle for the EFI image.
> + @param SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The constructor successfully added string package.
> + @retval Other value The constructor can't add string package.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +GenericBdsLibConstructor (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> +
> + gBdsLibStringPackHandle = HiiAddPackages (
> + &gBdsLibStringPackageGuid,
> + ImageHandle,
> + GenericBdsLibStrings,
> + NULL
> + );
> +
> + ASSERT (gBdsLibStringPackHandle != NULL);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Deletete the Boot Option from EFI Variable. The Boot Order Arrray
> + is also updated.
> +
> + @param OptionNumber The number of Boot option want to be deleted.
> + @param BootOrder The Boot Order array.
> + @param BootOrderSize The size of the Boot Order Array.
> +
> + @retval EFI_SUCCESS The Boot Option Variable was found and
> removed
> + @retval EFI_UNSUPPORTED The Boot Option Variable store was
> inaccessible
> + @retval EFI_NOT_FOUND The Boot Option Variable was not found
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsDeleteBootOption (
> + IN UINTN OptionNumber,
> + IN OUT UINT16 *BootOrder,
> + IN OUT UINTN *BootOrderSize
> + )
> +{
> + CHAR16 BootOption[9];
> + UINTN Index;
> + EFI_STATUS Status;
> +
> + UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x",
> OptionNumber);
> + Status = gRT->SetVariable (
> + BootOption,
> + &gEfiGlobalVariableGuid,
> + 0,
> + 0,
> + NULL
> + );
> + //
> + // Deleting variable with existing variable implementation shouldn't fail.
> + //
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // adjust boot order array
> + //
> + for (Index = 0; Index < *BootOrderSize / sizeof (UINT16); Index++) {
> + if (BootOrder[Index] == OptionNumber) {
> + CopyMem (&BootOrder[Index], &BootOrder[Index+1], *BootOrderSize
> - (Index+1) * sizeof (UINT16));
> + *BootOrderSize -= sizeof (UINT16);
> + break;
> + }
> + }
> +
> + return Status;
> +}
> +/**
> +
> + Translate the first n characters of an Ascii string to
> + Unicode characters. The count n is indicated by parameter
> + Size. If Size is greater than the length of string, then
> + the entire string is translated.
> +
> +
> + @param AStr Pointer to input Ascii string.
> + @param Size The number of characters to translate.
> + @param UStr Pointer to output Unicode string buffer.
> +
> +**/
> +VOID
> +AsciiToUnicodeSize (
> + IN UINT8 *AStr,
> + IN UINTN Size,
> + OUT UINT16 *UStr
> + )
> +{
> + UINTN Idx;
> +
> + Idx = 0;
> + while (AStr[Idx] != 0) {
> + UStr[Idx] = (CHAR16) AStr[Idx];
> + if (Idx == Size) {
> + break;
> + }
> +
> + Idx++;
> + }
> + UStr[Idx] = 0;
> +}
> +
> +/**
> + Build Legacy Device Name String according.
> +
> + @param CurBBSEntry BBS Table.
> + @param Index Index.
> + @param BufSize The buffer size.
> + @param BootString The output string.
> +
> +**/
> +VOID
> +BdsBuildLegacyDevNameString (
> + IN BBS_TABLE *CurBBSEntry,
> + IN UINTN Index,
> + IN UINTN BufSize,
> + OUT CHAR16 *BootString
> + )
> +{
> + CHAR16 *Fmt;
> + CHAR16 *Type;
> + UINT8 *StringDesc;
> + CHAR16 Temp[80];
> +
> + switch (Index) {
> + //
> + // Primary Master
> + //
> + case 1:
> + Fmt = L"Primary Master %s";
> + break;
> +
> + //
> + // Primary Slave
> + //
> + case 2:
> + Fmt = L"Primary Slave %s";
> + break;
> +
> + //
> + // Secondary Master
> + //
> + case 3:
> + Fmt = L"Secondary Master %s";
> + break;
> +
> + //
> + // Secondary Slave
> + //
> + case 4:
> + Fmt = L"Secondary Slave %s";
> + break;
> +
> + default:
> + Fmt = L"%s";
> + break;
> + }
> +
> + switch (CurBBSEntry->DeviceType) {
> + case BBS_FLOPPY:
> + Type = L"Floppy";
> + break;
> +
> + case BBS_HARDDISK:
> + Type = L"Harddisk";
> + break;
> +
> + case BBS_CDROM:
> + Type = L"CDROM";
> + break;
> +
> + case BBS_PCMCIA:
> + Type = L"PCMCIAe";
> + break;
> +
> + case BBS_USB:
> + Type = L"USB";
> + break;
> +
> + case BBS_EMBED_NETWORK:
> + Type = L"Network";
> + break;
> +
> + case BBS_BEV_DEVICE:
> + Type = L"BEVe";
> + break;
> +
> + case BBS_UNKNOWN:
> + default:
> + Type = L"Unknown";
> + break;
> + }
> + //
> + // If current BBS entry has its description then use it.
> + //
> + StringDesc = (UINT8 *) (UINTN) ((CurBBSEntry->DescStringSegment << 4)
> + CurBBSEntry->DescStringOffset);
> + if (NULL != StringDesc) {
> + //
> + // Only get fisrt 32 characters, this is suggested by BBS spec
> + //
> + AsciiToUnicodeSize (StringDesc, 32, Temp);
> + Fmt = L"%s";
> + Type = Temp;
> + }
> +
> + //
> + // BbsTable 16 entries are for onboard IDE.
> + // Set description string for SATA harddisks, Harddisk 0 ~ Harddisk 11
> + //
> + if (Index >= 5 && Index <= 16 && (CurBBSEntry->DeviceType ==
> BBS_HARDDISK || CurBBSEntry->DeviceType == BBS_CDROM)) {
> + Fmt = L"%s %d";
> + UnicodeSPrint (BootString, BufSize, Fmt, Type, Index - 5);
> + } else {
> + UnicodeSPrint (BootString, BufSize, Fmt, Type);
> + }
> +}
> +
> +/**
> +
> + Create a legacy boot option for the specified entry of
> + BBS table, save it as variable, and append it to the boot
> + order list.
> +
> +
> + @param CurrentBbsEntry Pointer to current BBS table.
> + @param CurrentBbsDevPath Pointer to the Device Path Protocol instance
> of BBS
> + @param Index Index of the specified entry in BBS table.
> + @param BootOrderList On input, the original boot order list.
> + On output, the new boot order list attached with the
> + created node.
> + @param BootOrderListSize On input, the original size of boot order list.
> + On output, the size of new boot order list.
> +
> + @retval EFI_SUCCESS Boot Option successfully created.
> + @retval EFI_OUT_OF_RESOURCES Fail to allocate necessary memory.
> + @retval Other Error occurs while setting variable.
> +
> +**/
> +EFI_STATUS
> +BdsCreateLegacyBootOption (
> + IN BBS_TABLE *CurrentBbsEntry,
> + IN EFI_DEVICE_PATH_PROTOCOL *CurrentBbsDevPath,
> + IN UINTN Index,
> + IN OUT UINT16 **BootOrderList,
> + IN OUT UINTN *BootOrderListSize
> + )
> +{
> + EFI_STATUS Status;
> + UINT16 CurrentBootOptionNo;
> + UINT16 BootString[10];
> + CHAR16 BootDesc[100];
> + CHAR8 HelpString[100];
> + UINT16 *NewBootOrderList;
> + UINTN BufferSize;
> + UINTN StringLen;
> + VOID *Buffer;
> + UINT8 *Ptr;
> + UINT16 CurrentBbsDevPathSize;
> + UINTN BootOrderIndex;
> + UINTN BootOrderLastIndex;
> + UINTN ArrayIndex;
> + BOOLEAN IndexNotFound;
> + BBS_BBS_DEVICE_PATH *NewBbsDevPathNode;
> +
> + if ((*BootOrderList) == NULL) {
> + CurrentBootOptionNo = 0;
> + } else {
> + for (ArrayIndex = 0; ArrayIndex < (UINTN) (*BootOrderListSize / sizeof
> (UINT16)); ArrayIndex++) {
> + IndexNotFound = TRUE;
> + for (BootOrderIndex = 0; BootOrderIndex < (UINTN) (*BootOrderListSize
> / sizeof (UINT16)); BootOrderIndex++) {
> + if ((*BootOrderList)[BootOrderIndex] == ArrayIndex) {
> + IndexNotFound = FALSE;
> + break;
> + }
> + }
> +
> + if (!IndexNotFound) {
> + continue;
> + } else {
> + break;
> + }
> + }
> +
> + CurrentBootOptionNo = (UINT16) ArrayIndex;
> + }
> +
> + UnicodeSPrint (
> + BootString,
> + sizeof (BootString),
> + L"Boot%04x",
> + CurrentBootOptionNo
> + );
> +
> + BdsBuildLegacyDevNameString (CurrentBbsEntry, Index, sizeof (BootDesc),
> BootDesc);
> +
> + //
> + // Create new BBS device path node with description string
> + //
> + UnicodeStrToAsciiStr (BootDesc, HelpString);
> +
> + StringLen = AsciiStrLen (HelpString);
> + NewBbsDevPathNode = AllocateZeroPool (sizeof (BBS_BBS_DEVICE_PATH)
> + StringLen);
> + if (NewBbsDevPathNode == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + CopyMem (NewBbsDevPathNode, CurrentBbsDevPath, sizeof
> (BBS_BBS_DEVICE_PATH));
> + CopyMem (NewBbsDevPathNode->String, HelpString, StringLen + 1);
> + SetDevicePathNodeLength (&(NewBbsDevPathNode->Header), sizeof
> (BBS_BBS_DEVICE_PATH) + StringLen);
> +
> + //
> + // Create entire new CurrentBbsDevPath with end node
> + //
> + CurrentBbsDevPath = AppendDevicePathNode (
> + NULL,
> + (EFI_DEVICE_PATH_PROTOCOL *) NewBbsDevPathNode
> + );
> + if (CurrentBbsDevPath == NULL) {
> + FreePool (NewBbsDevPathNode);
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + CurrentBbsDevPathSize = (UINT16) (GetDevicePathSize
> (CurrentBbsDevPath));
> +
> + BufferSize = sizeof (UINT32) +
> + sizeof (UINT16) +
> + StrSize (BootDesc) +
> + CurrentBbsDevPathSize +
> + sizeof (BBS_TABLE) +
> + sizeof (UINT16);
> +
> + Buffer = AllocateZeroPool (BufferSize);
> + if (Buffer == NULL) {
> + FreePool (NewBbsDevPathNode);
> + FreePool (CurrentBbsDevPath);
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + Ptr = (UINT8 *) Buffer;
> +
> + *((UINT32 *) Ptr) = LOAD_OPTION_ACTIVE;
> + Ptr += sizeof (UINT32);
> +
> + *((UINT16 *) Ptr) = CurrentBbsDevPathSize;
> + Ptr += sizeof (UINT16);
> +
> + CopyMem (
> + Ptr,
> + BootDesc,
> + StrSize (BootDesc)
> + );
> + Ptr += StrSize (BootDesc);
> +
> + CopyMem (
> + Ptr,
> + CurrentBbsDevPath,
> + CurrentBbsDevPathSize
> + );
> + Ptr += CurrentBbsDevPathSize;
> +
> + CopyMem (
> + Ptr,
> + CurrentBbsEntry,
> + sizeof (BBS_TABLE)
> + );
> +
> + Ptr += sizeof (BBS_TABLE);
> + *((UINT16 *) Ptr) = (UINT16) Index;
> +
> + Status = gRT->SetVariable (
> + BootString,
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + BufferSize,
> + Buffer
> + );
> +
> + FreePool (Buffer);
> +
> + Buffer = NULL;
> +
> + NewBootOrderList = AllocateZeroPool (*BootOrderListSize + sizeof
> (UINT16));
> + if (NULL == NewBootOrderList) {
> + FreePool (NewBbsDevPathNode);
> + FreePool (CurrentBbsDevPath);
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + if (*BootOrderList != NULL) {
> + CopyMem (NewBootOrderList, *BootOrderList, *BootOrderListSize);
> + FreePool (*BootOrderList);
> + }
> +
> + BootOrderLastIndex = (UINTN) (*BootOrderListSize / sizeof
> (UINT16));
> + NewBootOrderList[BootOrderLastIndex] = CurrentBootOptionNo;
> + *BootOrderListSize += sizeof (UINT16);
> + *BootOrderList = NewBootOrderList;
> +
> + FreePool (NewBbsDevPathNode);
> + FreePool (CurrentBbsDevPath);
> + return Status;
> +}
> +
> +/**
> + Check if the boot option is a legacy one.
> +
> + @param BootOptionVar The boot option data payload.
> + @param BbsEntry The BBS Table.
> + @param BbsIndex The table index.
> +
> + @retval TRUE It is a legacy boot option.
> + @retval FALSE It is not a legacy boot option.
> +
> +**/
> +BOOLEAN
> +BdsIsLegacyBootOption (
> + IN UINT8 *BootOptionVar,
> + OUT BBS_TABLE **BbsEntry,
> + OUT UINT16 *BbsIndex
> + )
> +{
> + UINT8 *Ptr;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + BOOLEAN Ret;
> + UINT16 DevPathLen;
> +
> + Ptr = BootOptionVar;
> + Ptr += sizeof (UINT32);
> + DevPathLen = *(UINT16 *) Ptr;
> + Ptr += sizeof (UINT16);
> + Ptr += StrSize ((UINT16 *) Ptr);
> + DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) Ptr;
> + if ((BBS_DEVICE_PATH == DevicePath->Type) && (BBS_BBS_DP ==
> DevicePath->SubType)) {
> + Ptr += DevPathLen;
> + *BbsEntry = (BBS_TABLE *) Ptr;
> + Ptr += sizeof (BBS_TABLE);
> + *BbsIndex = *(UINT16 *) Ptr;
> + Ret = TRUE;
> + } else {
> + *BbsEntry = NULL;
> + Ret = FALSE;
> + }
> +
> + return Ret;
> +}
> +
> +/**
> + Delete all the invalid legacy boot options.
> +
> + @retval EFI_SUCCESS All invalide legacy boot options are deleted.
> + @retval EFI_OUT_OF_RESOURCES Fail to allocate necessary memory.
> + @retval EFI_NOT_FOUND Fail to retrive variable of boot order.
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsDeleteAllInvalidLegacyBootOptions (
> + VOID
> + )
> +{
> + UINT16 *BootOrder;
> + UINT8 *BootOptionVar;
> + UINTN BootOrderSize;
> + UINTN BootOptionSize;
> + EFI_STATUS Status;
> + UINT16 HddCount;
> + UINT16 BbsCount;
> + HDD_INFO *LocalHddInfo;
> + BBS_TABLE *LocalBbsTable;
> + BBS_TABLE *BbsEntry;
> + UINT16 BbsIndex;
> + EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;
> + UINTN Index;
> + UINT16 BootOption[10];
> + UINT16 BootDesc[100];
> + BOOLEAN DescStringMatch;
> +
> + Status = EFI_SUCCESS;
> + BootOrder = NULL;
> + BootOrderSize = 0;
> + HddCount = 0;
> + BbsCount = 0;
> + LocalHddInfo = NULL;
> + LocalBbsTable = NULL;
> + BbsEntry = NULL;
> +
> + Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL,
> (VOID **) &LegacyBios);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + BootOrder = BdsLibGetVariableAndSize (
> + L"BootOrder",
> + &gEfiGlobalVariableGuid,
> + &BootOrderSize
> + );
> + if (BootOrder == NULL) {
> + return EFI_NOT_FOUND;
> + }
> +
> + LegacyBios->GetBbsInfo (
> + LegacyBios,
> + &HddCount,
> + &LocalHddInfo,
> + &BbsCount,
> + &LocalBbsTable
> + );
> +
> + Index = 0;
> + while (Index < BootOrderSize / sizeof (UINT16)) {
> + UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x",
> BootOrder[Index]);
> + BootOptionVar = BdsLibGetVariableAndSize (
> + BootOption,
> + &gEfiGlobalVariableGuid,
> + &BootOptionSize
> + );
> + if (NULL == BootOptionVar) {
> + BootOptionSize = 0;
> + Status = gRT->GetVariable (
> + BootOption,
> + &gEfiGlobalVariableGuid,
> + NULL,
> + &BootOptionSize,
> + BootOptionVar
> + );
> + if (Status == EFI_NOT_FOUND) {
> + //
> + // Update BootOrder
> + //
> + BdsDeleteBootOption (
> + BootOrder[Index],
> + BootOrder,
> + &BootOrderSize
> + );
> + continue;
> + } else {
> + FreePool (BootOrder);
> + return EFI_OUT_OF_RESOURCES;
> + }
> + }
> +
> + //
> + // Skip Non-Legacy boot option
> + //
> + if (!BdsIsLegacyBootOption (BootOptionVar, &BbsEntry, &BbsIndex)) {
> + if (BootOptionVar!= NULL) {
> + FreePool (BootOptionVar);
> + }
> + Index++;
> + continue;
> + }
> +
> + if (BbsIndex < BbsCount) {
> + //
> + // Check if BBS Description String is changed
> + //
> + DescStringMatch = FALSE;
> + BdsBuildLegacyDevNameString (
> + &LocalBbsTable[BbsIndex],
> + BbsIndex,
> + sizeof (BootDesc),
> + BootDesc
> + );
> +
> + if (StrCmp (BootDesc, (UINT16*)(BootOptionVar + sizeof (UINT32) +
> sizeof (UINT16))) == 0) {
> + DescStringMatch = TRUE;
> + }
> +
> + if (!((LocalBbsTable[BbsIndex].BootPriority == BBS_IGNORE_ENTRY) ||
> + (LocalBbsTable[BbsIndex].BootPriority ==
> BBS_DO_NOT_BOOT_FROM)) &&
> + (LocalBbsTable[BbsIndex].DeviceType == BbsEntry->DeviceType) &&
> + DescStringMatch) {
> + Index++;
> + continue;
> + }
> + }
> +
> + if (BootOptionVar != NULL) {
> + FreePool (BootOptionVar);
> + }
> + //
> + // should delete
> + //
> + BdsDeleteBootOption (
> + BootOrder[Index],
> + BootOrder,
> + &BootOrderSize
> + );
> + }
> +
> + //
> + // Adjust the number of boot options.
> + //
> + Status = gRT->SetVariable (
> + L"BootOrder",
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + BootOrderSize,
> + BootOrder
> + );
> + //
> + // Shrinking variable with existing variable implementation shouldn't fail.
> + //
> + ASSERT_EFI_ERROR (Status);
> + FreePool (BootOrder);
> +
> + return Status;
> +}
> +
> +/**
> + Find all legacy boot option by device type.
> +
> + @param BootOrder The boot order array.
> + @param BootOptionNum The number of boot option.
> + @param DevType Device type.
> + @param DevName Device name.
> + @param Attribute The boot option attribute.
> + @param BbsIndex The BBS table index.
> + @param OptionNumber The boot option index.
> +
> + @retval TRUE The Legacy boot option is found.
> + @retval FALSE The legacy boot option is not found.
> +
> +**/
> +BOOLEAN
> +BdsFindLegacyBootOptionByDevTypeAndName (
> + IN UINT16 *BootOrder,
> + IN UINTN BootOptionNum,
> + IN UINT16 DevType,
> + IN CHAR16 *DevName,
> + OUT UINT32 *Attribute,
> + OUT UINT16 *BbsIndex,
> + OUT UINT16 *OptionNumber
> + )
> +{
> + UINTN Index;
> + CHAR16 BootOption[9];
> + UINTN BootOptionSize;
> + UINT8 *BootOptionVar;
> + BBS_TABLE *BbsEntry;
> + BOOLEAN Found;
> +
> + BbsEntry = NULL;
> + Found = FALSE;
> +
> + if (NULL == BootOrder) {
> + return Found;
> + }
> +
> + //
> + // Loop all boot option from variable
> + //
> + for (Index = 0; Index < BootOptionNum; Index++) {
> + UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x", (UINTN)
> BootOrder[Index]);
> + BootOptionVar = BdsLibGetVariableAndSize (
> + BootOption,
> + &gEfiGlobalVariableGuid,
> + &BootOptionSize
> + );
> + if (NULL == BootOptionVar) {
> + continue;
> + }
> +
> + //
> + // Skip Non-legacy boot option
> + //
> + if (!BdsIsLegacyBootOption (BootOptionVar, &BbsEntry, BbsIndex)) {
> + FreePool (BootOptionVar);
> + continue;
> + }
> +
> + if (
> + (BbsEntry->DeviceType != DevType) ||
> + (StrCmp (DevName, (CHAR16*)(BootOptionVar + sizeof (UINT32) +
> sizeof (UINT16))) != 0)
> + ) {
> + FreePool (BootOptionVar);
> + continue;
> + }
> +
> + *Attribute = *(UINT32 *) BootOptionVar;
> + *OptionNumber = BootOrder[Index];
> + Found = TRUE;
> + FreePool (BootOptionVar);
> + break;
> + }
> +
> + return Found;
> +}
> +
> +/**
> + Create a legacy boot option.
> +
> + @param BbsItem The BBS Table entry.
> + @param Index Index of the specified entry in BBS table.
> + @param BootOrderList The boot order list.
> + @param BootOrderListSize The size of boot order list.
> +
> + @retval EFI_OUT_OF_RESOURCE No enough memory.
> + @retval EFI_SUCCESS The function complete successfully.
> + @return Other value if the legacy boot option is not created.
> +
> +**/
> +EFI_STATUS
> +BdsCreateOneLegacyBootOption (
> + IN BBS_TABLE *BbsItem,
> + IN UINTN Index,
> + IN OUT UINT16 **BootOrderList,
> + IN OUT UINTN *BootOrderListSize
> + )
> +{
> + BBS_BBS_DEVICE_PATH BbsDevPathNode;
> + EFI_STATUS Status;
> + EFI_DEVICE_PATH_PROTOCOL *DevPath;
> +
> + DevPath = NULL;
> +
> + //
> + // Create device path node.
> + //
> + BbsDevPathNode.Header.Type = BBS_DEVICE_PATH;
> + BbsDevPathNode.Header.SubType = BBS_BBS_DP;
> + SetDevicePathNodeLength (&BbsDevPathNode.Header, sizeof
> (BBS_BBS_DEVICE_PATH));
> + BbsDevPathNode.DeviceType = BbsItem->DeviceType;
> + CopyMem (&BbsDevPathNode.StatusFlag, &BbsItem->StatusFlags, sizeof
> (UINT16));
> +
> + DevPath = AppendDevicePathNode (
> + NULL,
> + (EFI_DEVICE_PATH_PROTOCOL *) &BbsDevPathNode
> + );
> + if (NULL == DevPath) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + Status = BdsCreateLegacyBootOption (
> + BbsItem,
> + DevPath,
> + Index,
> + BootOrderList,
> + BootOrderListSize
> + );
> + BbsItem->BootPriority = 0x00;
> +
> + FreePool (DevPath);
> +
> + return Status;
> +}
> +
> +/**
> + Add the legacy boot options from BBS table if they do not exist.
> +
> + @retval EFI_SUCCESS The boot options are added successfully
> + or they are already in boot options.
> + @retval EFI_NOT_FOUND No legacy boot options is found.
> + @retval EFI_OUT_OF_RESOURCE No enough memory.
> + @return Other value LegacyBoot options are not added.
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsAddNonExistingLegacyBootOptions (
> + VOID
> + )
> +{
> + UINT16 *BootOrder;
> + UINTN BootOrderSize;
> + EFI_STATUS Status;
> + CHAR16 Desc[100];
> + UINT16 HddCount;
> + UINT16 BbsCount;
> + HDD_INFO *LocalHddInfo;
> + BBS_TABLE *LocalBbsTable;
> + UINT16 BbsIndex;
> + EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;
> + UINT16 Index;
> + UINT32 Attribute;
> + UINT16 OptionNumber;
> + BOOLEAN Exist;
> +
> + HddCount = 0;
> + BbsCount = 0;
> + LocalHddInfo = NULL;
> + LocalBbsTable = NULL;
> +
> + Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL,
> (VOID **) &LegacyBios);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + LegacyBios->GetBbsInfo (
> + LegacyBios,
> + &HddCount,
> + &LocalHddInfo,
> + &BbsCount,
> + &LocalBbsTable
> + );
> +
> + BootOrder = BdsLibGetVariableAndSize (
> + L"BootOrder",
> + &gEfiGlobalVariableGuid,
> + &BootOrderSize
> + );
> + if (BootOrder == NULL) {
> + BootOrderSize = 0;
> + }
> +
> + for (Index = 0; Index < BbsCount; Index++) {
> + if ((LocalBbsTable[Index].BootPriority == BBS_IGNORE_ENTRY) ||
> + (LocalBbsTable[Index].BootPriority == BBS_DO_NOT_BOOT_FROM)
> + ) {
> + continue;
> + }
> +
> + BdsBuildLegacyDevNameString (&LocalBbsTable[Index], Index, sizeof
> (Desc), Desc);
> +
> + Exist = BdsFindLegacyBootOptionByDevTypeAndName (
> + BootOrder,
> + BootOrderSize / sizeof (UINT16),
> + LocalBbsTable[Index].DeviceType,
> + Desc,
> + &Attribute,
> + &BbsIndex,
> + &OptionNumber
> + );
> + if (!Exist) {
> + //
> + // Not found such type of legacy device in boot options or we found but
> it's disabled
> + // so we have to create one and put it to the tail of boot order list
> + //
> + Status = BdsCreateOneLegacyBootOption (
> + &LocalBbsTable[Index],
> + Index,
> + &BootOrder,
> + &BootOrderSize
> + );
> + if (!EFI_ERROR (Status)) {
> + ASSERT (BootOrder != NULL);
> + BbsIndex = Index;
> + OptionNumber = BootOrder[BootOrderSize / sizeof (UINT16) - 1];
> + }
> + }
> +
> + ASSERT (BbsIndex == Index);
> + }
> +
> + Status = gRT->SetVariable (
> + L"BootOrder",
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + BootOrderSize,
> + BootOrder
> + );
> + if (BootOrder != NULL) {
> + FreePool (BootOrder);
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Fill the device order buffer.
> +
> + @param BbsTable The BBS table.
> + @param BbsType The BBS Type.
> + @param BbsCount The BBS Count.
> + @param Buf device order buffer.
> +
> + @return The device order buffer.
> +
> +**/
> +UINT16 *
> +BdsFillDevOrderBuf (
> + IN BBS_TABLE *BbsTable,
> + IN BBS_TYPE BbsType,
> + IN UINTN BbsCount,
> + OUT UINT16 *Buf
> + )
> +{
> + UINTN Index;
> +
> + for (Index = 0; Index < BbsCount; Index++) {
> + if (BbsTable[Index].BootPriority == BBS_IGNORE_ENTRY) {
> + continue;
> + }
> +
> + if (BbsTable[Index].DeviceType != BbsType) {
> + continue;
> + }
> +
> + *Buf = (UINT16) (Index & 0xFF);
> + Buf++;
> + }
> +
> + return Buf;
> +}
> +
> +/**
> + Create the device order buffer.
> +
> + @param BbsTable The BBS table.
> + @param BbsCount The BBS Count.
> +
> + @retval EFI_SUCCES The buffer is created and the EFI variable
> named
> + VAR_LEGACY_DEV_ORDER and
> gEfiLegacyDevOrderVariableGuid is
> + set correctly.
> + @retval EFI_OUT_OF_RESOURCES Memmory or storage is not enough.
> + @retval EFI_DEVICE_ERROR Fail to add the device order into EFI variable
> fail
> + because of hardware error.
> +**/
> +EFI_STATUS
> +BdsCreateDevOrder (
> + IN BBS_TABLE *BbsTable,
> + IN UINT16 BbsCount
> + )
> +{
> + UINTN Index;
> + UINTN FDCount;
> + UINTN HDCount;
> + UINTN CDCount;
> + UINTN NETCount;
> + UINTN BEVCount;
> + UINTN TotalSize;
> + UINTN HeaderSize;
> + LEGACY_DEV_ORDER_ENTRY *DevOrder;
> + LEGACY_DEV_ORDER_ENTRY *DevOrderPtr;
> + EFI_STATUS Status;
> +
> + FDCount = 0;
> + HDCount = 0;
> + CDCount = 0;
> + NETCount = 0;
> + BEVCount = 0;
> + TotalSize = 0;
> + HeaderSize = sizeof (BBS_TYPE) + sizeof (UINT16);
> + DevOrder = NULL;
> + Status = EFI_SUCCESS;
> +
> + //
> + // Count all boot devices
> + //
> + for (Index = 0; Index < BbsCount; Index++) {
> + if (BbsTable[Index].BootPriority == BBS_IGNORE_ENTRY) {
> + continue;
> + }
> +
> + switch (BbsTable[Index].DeviceType) {
> + case BBS_FLOPPY:
> + FDCount++;
> + break;
> +
> + case BBS_HARDDISK:
> + HDCount++;
> + break;
> +
> + case BBS_CDROM:
> + CDCount++;
> + break;
> +
> + case BBS_EMBED_NETWORK:
> + NETCount++;
> + break;
> +
> + case BBS_BEV_DEVICE:
> + BEVCount++;
> + break;
> +
> + default:
> + break;
> + }
> + }
> +
> + TotalSize += (HeaderSize + sizeof (UINT16) * FDCount);
> + TotalSize += (HeaderSize + sizeof (UINT16) * HDCount);
> + TotalSize += (HeaderSize + sizeof (UINT16) * CDCount);
> + TotalSize += (HeaderSize + sizeof (UINT16) * NETCount);
> + TotalSize += (HeaderSize + sizeof (UINT16) * BEVCount);
> +
> + //
> + // Create buffer to hold all boot device order
> + //
> + DevOrder = AllocateZeroPool (TotalSize);
> + if (NULL == DevOrder) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + DevOrderPtr = DevOrder;
> +
> + DevOrderPtr->BbsType = BBS_FLOPPY;
> + DevOrderPtr->Length = (UINT16) (sizeof (DevOrderPtr->Length) +
> FDCount * sizeof (UINT16));
> + DevOrderPtr = (LEGACY_DEV_ORDER_ENTRY *) BdsFillDevOrderBuf
> (BbsTable, BBS_FLOPPY, BbsCount, DevOrderPtr->Data);
> +
> + DevOrderPtr->BbsType = BBS_HARDDISK;
> + DevOrderPtr->Length = (UINT16) (sizeof (UINT16) + HDCount * sizeof
> (UINT16));
> + DevOrderPtr = (LEGACY_DEV_ORDER_ENTRY *) BdsFillDevOrderBuf
> (BbsTable, BBS_HARDDISK, BbsCount, DevOrderPtr->Data);
> +
> + DevOrderPtr->BbsType = BBS_CDROM;
> + DevOrderPtr->Length = (UINT16) (sizeof (UINT16) + CDCount * sizeof
> (UINT16));
> + DevOrderPtr = (LEGACY_DEV_ORDER_ENTRY *) BdsFillDevOrderBuf
> (BbsTable, BBS_CDROM, BbsCount, DevOrderPtr->Data);
> +
> + DevOrderPtr->BbsType = BBS_EMBED_NETWORK;
> + DevOrderPtr->Length = (UINT16) (sizeof (UINT16) + NETCount * sizeof
> (UINT16));
> + DevOrderPtr = (LEGACY_DEV_ORDER_ENTRY *) BdsFillDevOrderBuf
> (BbsTable, BBS_EMBED_NETWORK, BbsCount, DevOrderPtr->Data);
> +
> + DevOrderPtr->BbsType = BBS_BEV_DEVICE;
> + DevOrderPtr->Length = (UINT16) (sizeof (UINT16) + BEVCount * sizeof
> (UINT16));
> + DevOrderPtr = (LEGACY_DEV_ORDER_ENTRY *) BdsFillDevOrderBuf
> (BbsTable, BBS_BEV_DEVICE, BbsCount, DevOrderPtr->Data);
> +
> + ASSERT (TotalSize == (UINTN) ((UINT8 *) DevOrderPtr - (UINT8 *)
> DevOrder));
> +
> + //
> + // Save device order for legacy boot device to variable.
> + //
> + Status = gRT->SetVariable (
> + VAR_LEGACY_DEV_ORDER,
> + &gEfiLegacyDevOrderVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_NON_VOLATILE,
> + TotalSize,
> + DevOrder
> + );
> + FreePool (DevOrder);
> +
> + return Status;
> +}
> +
> +/**
> + Add the legacy boot devices from BBS table into
> + the legacy device boot order.
> +
> + @retval EFI_SUCCESS The boot devices are added successfully.
> + @retval EFI_NOT_FOUND The legacy boot devices are not found.
> + @retval EFI_OUT_OF_RESOURCES Memmory or storage is not enough.
> + @retval EFI_DEVICE_ERROR Fail to add the legacy device boot order into
> EFI variable
> + because of hardware error.
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsUpdateLegacyDevOrder (
> + VOID
> + )
> +{
> + LEGACY_DEV_ORDER_ENTRY *DevOrder;
> + LEGACY_DEV_ORDER_ENTRY *NewDevOrder;
> + LEGACY_DEV_ORDER_ENTRY *Ptr;
> + LEGACY_DEV_ORDER_ENTRY *NewPtr;
> + UINTN DevOrderSize;
> + EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;
> + EFI_STATUS Status;
> + UINT16 HddCount;
> + UINT16 BbsCount;
> + HDD_INFO *LocalHddInfo;
> + BBS_TABLE *LocalBbsTable;
> + UINTN Index;
> + UINTN Index2;
> + UINTN *Idx;
> + UINTN FDCount;
> + UINTN HDCount;
> + UINTN CDCount;
> + UINTN NETCount;
> + UINTN BEVCount;
> + UINTN TotalSize;
> + UINTN HeaderSize;
> + UINT16 *NewFDPtr;
> + UINT16 *NewHDPtr;
> + UINT16 *NewCDPtr;
> + UINT16 *NewNETPtr;
> + UINT16 *NewBEVPtr;
> + UINT16 *NewDevPtr;
> + UINTN FDIndex;
> + UINTN HDIndex;
> + UINTN CDIndex;
> + UINTN NETIndex;
> + UINTN BEVIndex;
> +
> + Idx = NULL;
> + FDCount = 0;
> + HDCount = 0;
> + CDCount = 0;
> + NETCount = 0;
> + BEVCount = 0;
> + TotalSize = 0;
> + HeaderSize = sizeof (BBS_TYPE) + sizeof (UINT16);
> + FDIndex = 0;
> + HDIndex = 0;
> + CDIndex = 0;
> + NETIndex = 0;
> + BEVIndex = 0;
> + NewDevPtr = NULL;
> +
> + Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL,
> (VOID **) &LegacyBios);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + Status = LegacyBios->GetBbsInfo (
> + LegacyBios,
> + &HddCount,
> + &LocalHddInfo,
> + &BbsCount,
> + &LocalBbsTable
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + DevOrder = BdsLibGetVariableAndSize (
> + VAR_LEGACY_DEV_ORDER,
> + &gEfiLegacyDevOrderVariableGuid,
> + &DevOrderSize
> + );
> + if (NULL == DevOrder) {
> + return BdsCreateDevOrder (LocalBbsTable, BbsCount);
> + }
> + //
> + // First we figure out how many boot devices with same device type
> respectively
> + //
> + for (Index = 0; Index < BbsCount; Index++) {
> + if ((LocalBbsTable[Index].BootPriority == BBS_IGNORE_ENTRY) ||
> + (LocalBbsTable[Index].BootPriority == BBS_DO_NOT_BOOT_FROM)
> + ) {
> + continue;
> + }
> +
> + switch (LocalBbsTable[Index].DeviceType) {
> + case BBS_FLOPPY:
> + FDCount++;
> + break;
> +
> + case BBS_HARDDISK:
> + HDCount++;
> + break;
> +
> + case BBS_CDROM:
> + CDCount++;
> + break;
> +
> + case BBS_EMBED_NETWORK:
> + NETCount++;
> + break;
> +
> + case BBS_BEV_DEVICE:
> + BEVCount++;
> + break;
> +
> + default:
> + break;
> + }
> + }
> +
> + TotalSize += (HeaderSize + FDCount * sizeof (UINT16));
> + TotalSize += (HeaderSize + HDCount * sizeof (UINT16));
> + TotalSize += (HeaderSize + CDCount * sizeof (UINT16));
> + TotalSize += (HeaderSize + NETCount * sizeof (UINT16));
> + TotalSize += (HeaderSize + BEVCount * sizeof (UINT16));
> +
> + NewDevOrder = AllocateZeroPool (TotalSize);
> + if (NULL == NewDevOrder) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> +
> +
> + //
> + // copy FD
> + //
> + Ptr = DevOrder;
> + NewPtr = NewDevOrder;
> + NewPtr->BbsType = Ptr->BbsType;
> + NewPtr->Length = (UINT16) (sizeof (UINT16) + FDCount * sizeof (UINT16));
> + for (Index = 0; Index < Ptr->Length / sizeof (UINT16) - 1; Index++) {
> + if (LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_IGNORE_ENTRY ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_DO_NOT_BOOT_FROM ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].DeviceType != BBS_FLOPPY
> + ) {
> + continue;
> + }
> +
> + NewPtr->Data[FDIndex] = Ptr->Data[Index];
> + FDIndex++;
> + }
> + NewFDPtr = NewPtr->Data;
> +
> + //
> + // copy HD
> + //
> + Ptr = (LEGACY_DEV_ORDER_ENTRY *) (&Ptr->Data[Ptr->Length /
> sizeof (UINT16) - 1]);
> + NewPtr = (LEGACY_DEV_ORDER_ENTRY *) (&NewPtr->Data[NewPtr-
> >Length / sizeof (UINT16) -1]);
> + NewPtr->BbsType = Ptr->BbsType;
> + NewPtr->Length = (UINT16) (sizeof (UINT16) + HDCount * sizeof
> (UINT16));
> + for (Index = 0; Index < Ptr->Length / sizeof (UINT16) - 1; Index++) {
> + if (LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_IGNORE_ENTRY ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_DO_NOT_BOOT_FROM ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_LOWEST_PRIORITY ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].DeviceType != BBS_HARDDISK
> + ) {
> + continue;
> + }
> +
> + NewPtr->Data[HDIndex] = Ptr->Data[Index];
> + HDIndex++;
> + }
> + NewHDPtr = NewPtr->Data;
> +
> + //
> + // copy CD
> + //
> + Ptr = (LEGACY_DEV_ORDER_ENTRY *) (&Ptr->Data[Ptr->Length / sizeof
> (UINT16) - 1]);
> + NewPtr = (LEGACY_DEV_ORDER_ENTRY *) (&NewPtr->Data[NewPtr-
> >Length / sizeof (UINT16) -1]);
> + NewPtr->BbsType = Ptr->BbsType;
> + NewPtr->Length = (UINT16) (sizeof (UINT16) + CDCount * sizeof
> (UINT16));
> + for (Index = 0; Index < Ptr->Length / sizeof (UINT16) - 1; Index++) {
> + if (LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_IGNORE_ENTRY ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_DO_NOT_BOOT_FROM ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_LOWEST_PRIORITY ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].DeviceType != BBS_CDROM
> + ) {
> + continue;
> + }
> +
> + NewPtr->Data[CDIndex] = Ptr->Data[Index];
> + CDIndex++;
> + }
> + NewCDPtr = NewPtr->Data;
> +
> + //
> + // copy NET
> + //
> + Ptr = (LEGACY_DEV_ORDER_ENTRY *) (&Ptr->Data[Ptr->Length / sizeof
> (UINT16) - 1]);
> + NewPtr = (LEGACY_DEV_ORDER_ENTRY *) (&NewPtr->Data[NewPtr-
> >Length / sizeof (UINT16) -1]);
> + NewPtr->BbsType = Ptr->BbsType;
> + NewPtr->Length = (UINT16) (sizeof (UINT16) + NETCount * sizeof
> (UINT16));
> + for (Index = 0; Index < Ptr->Length / sizeof (UINT16) - 1; Index++) {
> + if (LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_IGNORE_ENTRY ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_DO_NOT_BOOT_FROM ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_LOWEST_PRIORITY ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].DeviceType !=
> BBS_EMBED_NETWORK
> + ) {
> + continue;
> + }
> +
> + NewPtr->Data[NETIndex] = Ptr->Data[Index];
> + NETIndex++;
> + }
> + NewNETPtr = NewPtr->Data;
> +
> + //
> + // copy BEV
> + //
> + Ptr = (LEGACY_DEV_ORDER_ENTRY *) (&Ptr->Data[Ptr->Length / sizeof
> (UINT16) - 1]);
> + NewPtr = (LEGACY_DEV_ORDER_ENTRY *) (&NewPtr->Data[NewPtr-
> >Length / sizeof (UINT16) -1]);
> + NewPtr->BbsType = Ptr->BbsType;
> + NewPtr->Length = (UINT16) (sizeof (UINT16) + BEVCount * sizeof
> (UINT16));
> + for (Index = 0; Index < Ptr->Length / sizeof (UINT16) - 1; Index++) {
> + if (LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_IGNORE_ENTRY ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_DO_NOT_BOOT_FROM ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority ==
> BBS_LOWEST_PRIORITY ||
> + LocalBbsTable[Ptr->Data[Index] & 0xFF].DeviceType !=
> BBS_BEV_DEVICE
> + ) {
> + continue;
> + }
> +
> + NewPtr->Data[BEVIndex] = Ptr->Data[Index];
> + BEVIndex++;
> + }
> + NewBEVPtr = NewPtr->Data;
> +
> + for (Index = 0; Index < BbsCount; Index++) {
> + if ((LocalBbsTable[Index].BootPriority == BBS_IGNORE_ENTRY) ||
> + (LocalBbsTable[Index].BootPriority == BBS_DO_NOT_BOOT_FROM)
> + ) {
> + continue;
> + }
> +
> + switch (LocalBbsTable[Index].DeviceType) {
> + case BBS_FLOPPY:
> + Idx = &FDIndex;
> + NewDevPtr = NewFDPtr;
> + break;
> +
> + case BBS_HARDDISK:
> + Idx = &HDIndex;
> + NewDevPtr = NewHDPtr;
> + break;
> +
> + case BBS_CDROM:
> + Idx = &CDIndex;
> + NewDevPtr = NewCDPtr;
> + break;
> +
> + case BBS_EMBED_NETWORK:
> + Idx = &NETIndex;
> + NewDevPtr = NewNETPtr;
> + break;
> +
> + case BBS_BEV_DEVICE:
> + Idx = &BEVIndex;
> + NewDevPtr = NewBEVPtr;
> + break;
> +
> + default:
> + Idx = NULL;
> + break;
> + }
> + //
> + // at this point we have copied those valid indexes to new buffer
> + // and we should check if there is any new appeared boot device
> + //
> + if (Idx != NULL) {
> + for (Index2 = 0; Index2 < *Idx; Index2++) {
> + if ((NewDevPtr[Index2] & 0xFF) == (UINT16) Index) {
> + break;
> + }
> + }
> +
> + if (Index2 == *Idx) {
> + //
> + // Index2 == *Idx means we didn't find Index
> + // so Index is a new appeared device's index in BBS table
> + // insert it before disabled indexes.
> + //
> + for (Index2 = 0; Index2 < *Idx; Index2++) {
> + if ((NewDevPtr[Index2] & 0xFF00) == 0xFF00) {
> + break;
> + }
> + }
> + CopyMem (&NewDevPtr[Index2 + 1], &NewDevPtr[Index2], (*Idx -
> Index2) * sizeof (UINT16));
> + NewDevPtr[Index2] = (UINT16) (Index & 0xFF);
> + (*Idx)++;
> + }
> + }
> + }
> +
> + FreePool (DevOrder);
> +
> + Status = gRT->SetVariable (
> + VAR_LEGACY_DEV_ORDER,
> + &gEfiLegacyDevOrderVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_NON_VOLATILE,
> + TotalSize,
> + NewDevOrder
> + );
> + FreePool (NewDevOrder);
> +
> + return Status;
> +}
> +
> +/**
> + Set Boot Priority for specified device type.
> +
> + @param DeviceType The device type.
> + @param BbsIndex The BBS index to set the highest priority. Ignore
> when -1.
> + @param LocalBbsTable The BBS table.
> + @param Priority The prority table.
> +
> + @retval EFI_SUCCESS The function completes successfully.
> + @retval EFI_NOT_FOUND Failed to find device.
> + @retval EFI_OUT_OF_RESOURCES Failed to get the efi variable of device
> order.
> +
> +**/
> +EFI_STATUS
> +BdsSetBootPriority4SameTypeDev (
> + IN UINT16 DeviceType,
> + IN UINTN BbsIndex,
> + IN OUT BBS_TABLE *LocalBbsTable,
> + IN OUT UINT16 *Priority
> + )
> +{
> + LEGACY_DEV_ORDER_ENTRY *DevOrder;
> + LEGACY_DEV_ORDER_ENTRY *DevOrderPtr;
> + UINTN DevOrderSize;
> + UINTN Index;
> +
> + DevOrder = BdsLibGetVariableAndSize (
> + VAR_LEGACY_DEV_ORDER,
> + &gEfiLegacyDevOrderVariableGuid,
> + &DevOrderSize
> + );
> + if (NULL == DevOrder) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + DevOrderPtr = DevOrder;
> + while ((UINT8 *) DevOrderPtr < (UINT8 *) DevOrder + DevOrderSize) {
> + if (DevOrderPtr->BbsType == DeviceType) {
> + break;
> + }
> +
> + DevOrderPtr = (LEGACY_DEV_ORDER_ENTRY *) ((UINTN) DevOrderPtr +
> sizeof (BBS_TYPE) + DevOrderPtr->Length);
> + }
> +
> + if ((UINT8 *) DevOrderPtr >= (UINT8 *) DevOrder + DevOrderSize) {
> + FreePool (DevOrder);
> + return EFI_NOT_FOUND;
> + }
> +
> + if (BbsIndex != (UINTN) -1) {
> + LocalBbsTable[BbsIndex].BootPriority = *Priority;
> + (*Priority)++;
> + }
> + //
> + // If the high byte of the DevIndex is 0xFF, it indicates that this device has
> been disabled.
> + //
> + for (Index = 0; Index < DevOrderPtr->Length / sizeof (UINT16) - 1; Index++)
> {
> + if ((DevOrderPtr->Data[Index] & 0xFF00) == 0xFF00) {
> + //
> + // LocalBbsTable[DevIndex[Index] & 0xFF].BootPriority =
> BBS_DISABLED_ENTRY;
> + //
> + } else if (DevOrderPtr->Data[Index] != BbsIndex) {
> + LocalBbsTable[DevOrderPtr->Data[Index]].BootPriority = *Priority;
> + (*Priority)++;
> + }
> + }
> +
> + FreePool (DevOrder);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Print the BBS Table.
> +
> + @param LocalBbsTable The BBS table.
> + @param BbsCount The count of entry in BBS table.
> +**/
> +VOID
> +PrintBbsTable (
> + IN BBS_TABLE *LocalBbsTable,
> + IN UINT16 BbsCount
> + )
> +{
> + UINT16 Idx;
> +
> + DEBUG ((DEBUG_ERROR, "\n"));
> + DEBUG ((DEBUG_ERROR, " NO Prio bb/dd/ff cl/sc Type Stat
> segm:offs\n"));
> + DEBUG ((DEBUG_ERROR,
> "=============================================\n"));
> + for (Idx = 0; Idx < BbsCount; Idx++) {
> + if ((LocalBbsTable[Idx].BootPriority == BBS_IGNORE_ENTRY) ||
> + (LocalBbsTable[Idx].BootPriority == BBS_DO_NOT_BOOT_FROM) ||
> + (LocalBbsTable[Idx].BootPriority == BBS_LOWEST_PRIORITY)
> + ) {
> + continue;
> + }
> +
> + DEBUG (
> + (DEBUG_ERROR,
> + " %02x: %04x %02x/%02x/%02x %02x/%02x %04x %04x %04x:%04x\n",
> + (UINTN) Idx,
> + (UINTN) LocalBbsTable[Idx].BootPriority,
> + (UINTN) LocalBbsTable[Idx].Bus,
> + (UINTN) LocalBbsTable[Idx].Device,
> + (UINTN) LocalBbsTable[Idx].Function,
> + (UINTN) LocalBbsTable[Idx].Class,
> + (UINTN) LocalBbsTable[Idx].SubClass,
> + (UINTN) LocalBbsTable[Idx].DeviceType,
> + (UINTN) * (UINT16 *) &LocalBbsTable[Idx].StatusFlags,
> + (UINTN) LocalBbsTable[Idx].BootHandlerSegment,
> + (UINTN) LocalBbsTable[Idx].BootHandlerOffset,
> + (UINTN) ((LocalBbsTable[Idx].MfgStringSegment << 4) +
> LocalBbsTable[Idx].MfgStringOffset),
> + (UINTN) ((LocalBbsTable[Idx].DescStringSegment << 4) +
> LocalBbsTable[Idx].DescStringOffset))
> + );
> + }
> +
> + DEBUG ((DEBUG_ERROR, "\n"));
> +}
> +
> +/**
> + Set the boot priority for BBS entries based on boot option entry and boot
> order.
> +
> + @param Entry The boot option is to be checked for refresh BBS
> table.
> +
> + @retval EFI_SUCCESS The boot priority for BBS entries is refreshed
> successfully.
> + @retval EFI_NOT_FOUND BBS entries can't be found.
> + @retval EFI_OUT_OF_RESOURCES Failed to get the legacy device boot
> order.
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsRefreshBbsTableForBoot (
> + IN BDS_COMMON_OPTION *Entry
> + )
> +{
> + EFI_STATUS Status;
> + UINT16 BbsIndex;
> + UINT16 HddCount;
> + UINT16 BbsCount;
> + HDD_INFO *LocalHddInfo;
> + BBS_TABLE *LocalBbsTable;
> + UINT16 DevType;
> + EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;
> + UINTN Index;
> + UINT16 Priority;
> + UINT16 *BootOrder;
> + UINTN BootOrderSize;
> + UINT8 *BootOptionVar;
> + UINTN BootOptionSize;
> + CHAR16 BootOption[9];
> + UINT8 *Ptr;
> + UINT16 DevPathLen;
> + EFI_DEVICE_PATH_PROTOCOL *DevPath;
> + UINT16 *DeviceType;
> + UINTN DeviceTypeCount;
> + UINTN DeviceTypeIndex;
> +
> + HddCount = 0;
> + BbsCount = 0;
> + LocalHddInfo = NULL;
> + LocalBbsTable = NULL;
> + DevType = BBS_UNKNOWN;
> +
> + Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL,
> (VOID **) &LegacyBios);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + LegacyBios->GetBbsInfo (
> + LegacyBios,
> + &HddCount,
> + &LocalHddInfo,
> + &BbsCount,
> + &LocalBbsTable
> + );
> + //
> + // First, set all the present devices' boot priority to
> BBS_UNPRIORITIZED_ENTRY
> + // We will set them according to the settings setup by user
> + //
> + for (Index = 0; Index < BbsCount; Index++) {
> + if (!((BBS_IGNORE_ENTRY == LocalBbsTable[Index].BootPriority) ||
> + (BBS_DO_NOT_BOOT_FROM == LocalBbsTable[Index].BootPriority) ||
> + (BBS_LOWEST_PRIORITY == LocalBbsTable[Index].BootPriority))) {
> + LocalBbsTable[Index].BootPriority = BBS_UNPRIORITIZED_ENTRY;
> + }
> + }
> + //
> + // boot priority always starts at 0
> + //
> + Priority = 0;
> + if (Entry->LoadOptionsSize == sizeof (BBS_TABLE) + sizeof (UINT16)) {
> + //
> + // If Entry stands for a legacy boot option, we prioritize the devices with
> the same type first.
> + //
> + DevType = ((BBS_TABLE *) Entry->LoadOptions)->DeviceType;
> + BbsIndex = *(UINT16 *) ((BBS_TABLE *) Entry->LoadOptions + 1);
> + Status = BdsSetBootPriority4SameTypeDev (
> + DevType,
> + BbsIndex,
> + LocalBbsTable,
> + &Priority
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + }
> + //
> + // we have to set the boot priority for other BBS entries with different
> device types
> + //
> + BootOrder = BdsLibGetVariableAndSize (
> + L"BootOrder",
> + &gEfiGlobalVariableGuid,
> + &BootOrderSize
> + );
> + DeviceType = AllocatePool (BootOrderSize + sizeof (UINT16));
> + ASSERT (DeviceType != NULL);
> +
> + DeviceType[0] = DevType;
> + DeviceTypeCount = 1;
> + for (Index = 0; ((BootOrder != NULL) && (Index < BootOrderSize / sizeof
> (UINT16))); Index++) {
> + UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x",
> BootOrder[Index]);
> + BootOptionVar = BdsLibGetVariableAndSize (
> + BootOption,
> + &gEfiGlobalVariableGuid,
> + &BootOptionSize
> + );
> + if (NULL == BootOptionVar) {
> + continue;
> + }
> +
> + Ptr = BootOptionVar;
> +
> + Ptr += sizeof (UINT32);
> + DevPathLen = *(UINT16 *) Ptr;
> + Ptr += sizeof (UINT16);
> + Ptr += StrSize ((UINT16 *) Ptr);
> + DevPath = (EFI_DEVICE_PATH_PROTOCOL *) Ptr;
> + if (BBS_DEVICE_PATH != DevPath->Type || BBS_BBS_DP != DevPath-
> >SubType) {
> + FreePool (BootOptionVar);
> + continue;
> + }
> +
> + Ptr += DevPathLen;
> + DevType = ((BBS_TABLE *) Ptr)->DeviceType;
> + for (DeviceTypeIndex = 0; DeviceTypeIndex < DeviceTypeCount;
> DeviceTypeIndex++) {
> + if (DeviceType[DeviceTypeIndex] == DevType) {
> + break;
> + }
> + }
> + if (DeviceTypeIndex < DeviceTypeCount) {
> + //
> + // We don't want to process twice for a device type
> + //
> + FreePool (BootOptionVar);
> + continue;
> + }
> +
> + DeviceType[DeviceTypeCount] = DevType;
> + DeviceTypeCount++;
> +
> + Status = BdsSetBootPriority4SameTypeDev (
> + DevType,
> + (UINTN) -1,
> + LocalBbsTable,
> + &Priority
> + );
> + FreePool (BootOptionVar);
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + }
> +
> + FreePool (DeviceType);
> +
> + if (BootOrder != NULL) {
> + FreePool (BootOrder);
> + }
> +
> + DEBUG_CODE_BEGIN();
> + PrintBbsTable (LocalBbsTable, BbsCount);
> + DEBUG_CODE_END();
> +
> + return Status;
> +}
> +
> +/**
> + Boot the legacy system with the boot option
> +
> + @param Option The legacy boot option which have BBS device
> path
> +
> + @retval EFI_UNSUPPORTED There is no legacybios protocol, do not
> support
> + legacy boot.
> + @retval EFI_STATUS Return the status of LegacyBios->LegacyBoot ().
> +
> +**/
> +EFI_STATUS
> +BdsLibDoLegacyBoot (
> + IN BDS_COMMON_OPTION *Option
> + )
> +{
> + EFI_STATUS Status;
> + EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;
> + EFI_EVENT LegacyBootEvent;
> +
> + Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL, (VOID
> **) &LegacyBios);
> + if (EFI_ERROR (Status)) {
> + //
> + // If no LegacyBios protocol we do not support legacy boot
> + //
> + return EFI_UNSUPPORTED;
> + }
> + //
> + // Notes: if we separate the int 19, then we don't need to refresh BBS
> + //
> + BdsRefreshBbsTableForBoot (Option);
> +
> + //
> + // Write boot to OS performance data for legacy boot.
> + //
> + PERF_CODE (
> + //
> + // Create an event to be signalled when Legacy Boot occurs to write
> performance data.
> + //
> + Status = EfiCreateEventLegacyBootEx(
> + TPL_NOTIFY,
> + BmEndOfBdsPerfCode,
> + NULL,
> + &LegacyBootEvent
> + );
> + ASSERT_EFI_ERROR (Status);
> + );
> +
> + DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Legacy Boot: %S\n", Option-
> >Description));
> + return LegacyBios->LegacyBoot (
> + LegacyBios,
> + (BBS_BBS_DEVICE_PATH *) Option->DevicePath,
> + Option->LoadOptionsSize,
> + Option->LoadOptions
> + );
> +}
> +
> +/**
> + Internal function to check if the input boot option is a valid EFI NV
> Boot####.
> +
> + @param OptionToCheck Boot option to be checked.
> +
> + @retval TRUE This boot option matches a valid EFI NV Boot####.
> + @retval FALSE If not.
> +
> +**/
> +BOOLEAN
> +IsBootOptionValidNVVarialbe (
> + IN BDS_COMMON_OPTION *OptionToCheck
> + )
> +{
> + LIST_ENTRY TempList;
> + BDS_COMMON_OPTION *BootOption;
> + BOOLEAN Valid;
> + CHAR16 OptionName[20];
> +
> + Valid = FALSE;
> +
> + InitializeListHead (&TempList);
> + UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x",
> OptionToCheck->BootCurrent);
> +
> + BootOption = BdsLibVariableToOption (&TempList, OptionName);
> + if (BootOption == NULL) {
> + return FALSE;
> + }
> +
> + //
> + // If the Boot Option Number and Device Path matches, OptionToCheck
> matches a
> + // valid EFI NV Boot####.
> + //
> + if ((OptionToCheck->BootCurrent == BootOption->BootCurrent) &&
> + (CompareMem (OptionToCheck->DevicePath, BootOption->DevicePath,
> GetDevicePathSize (OptionToCheck->DevicePath)) == 0))
> + {
> + Valid = TRUE;
> + }
> +
> + FreePool (BootOption);
> +
> + return Valid;
> +}
> +
> +/**
> + Check whether a USB device match the specified USB Class device path.
> This
> + function follows "Load Option Processing" behavior in UEFI specification.
> +
> + @param UsbIo USB I/O protocol associated with the USB device.
> + @param UsbClass The USB Class device path to match.
> +
> + @retval TRUE The USB device match the USB Class device path.
> + @retval FALSE The USB device does not match the USB Class device path.
> +
> +**/
> +BOOLEAN
> +BdsMatchUsbClass (
> + IN EFI_USB_IO_PROTOCOL *UsbIo,
> + IN USB_CLASS_DEVICE_PATH *UsbClass
> + )
> +{
> + EFI_STATUS Status;
> + EFI_USB_DEVICE_DESCRIPTOR DevDesc;
> + EFI_USB_INTERFACE_DESCRIPTOR IfDesc;
> + UINT8 DeviceClass;
> + UINT8 DeviceSubClass;
> + UINT8 DeviceProtocol;
> +
> + if ((DevicePathType (UsbClass) != MESSAGING_DEVICE_PATH) ||
> + (DevicePathSubType (UsbClass) != MSG_USB_CLASS_DP)){
> + return FALSE;
> + }
> +
> + //
> + // Check Vendor Id and Product Id.
> + //
> + Status = UsbIo->UsbGetDeviceDescriptor (UsbIo, &DevDesc);
> + if (EFI_ERROR (Status)) {
> + return FALSE;
> + }
> +
> + if ((UsbClass->VendorId != 0xffff) &&
> + (UsbClass->VendorId != DevDesc.IdVendor)) {
> + return FALSE;
> + }
> +
> + if ((UsbClass->ProductId != 0xffff) &&
> + (UsbClass->ProductId != DevDesc.IdProduct)) {
> + return FALSE;
> + }
> +
> + DeviceClass = DevDesc.DeviceClass;
> + DeviceSubClass = DevDesc.DeviceSubClass;
> + DeviceProtocol = DevDesc.DeviceProtocol;
> + if (DeviceClass == 0) {
> + //
> + // If Class in Device Descriptor is set to 0, use the Class, SubClass and
> + // Protocol in Interface Descriptor instead.
> + //
> + Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &IfDesc);
> + if (EFI_ERROR (Status)) {
> + return FALSE;
> + }
> +
> + DeviceClass = IfDesc.InterfaceClass;
> + DeviceSubClass = IfDesc.InterfaceSubClass;
> + DeviceProtocol = IfDesc.InterfaceProtocol;
> + }
> +
> + //
> + // Check Class, SubClass and Protocol.
> + //
> + if ((UsbClass->DeviceClass != 0xff) &&
> + (UsbClass->DeviceClass != DeviceClass)) {
> + return FALSE;
> + }
> +
> + if ((UsbClass->DeviceSubClass != 0xff) &&
> + (UsbClass->DeviceSubClass != DeviceSubClass)) {
> + return FALSE;
> + }
> +
> + if ((UsbClass->DeviceProtocol != 0xff) &&
> + (UsbClass->DeviceProtocol != DeviceProtocol)) {
> + return FALSE;
> + }
> +
> + return TRUE;
> +}
> +
> +/**
> + Check whether a USB device match the specified USB WWID device path.
> This
> + function follows "Load Option Processing" behavior in UEFI specification.
> +
> + @param UsbIo USB I/O protocol associated with the USB device.
> + @param UsbWwid The USB WWID device path to match.
> +
> + @retval TRUE The USB device match the USB WWID device path.
> + @retval FALSE The USB device does not match the USB WWID device
> path.
> +
> +**/
> +BOOLEAN
> +BdsMatchUsbWwid (
> + IN EFI_USB_IO_PROTOCOL *UsbIo,
> + IN USB_WWID_DEVICE_PATH *UsbWwid
> + )
> +{
> + EFI_STATUS Status;
> + EFI_USB_DEVICE_DESCRIPTOR DevDesc;
> + EFI_USB_INTERFACE_DESCRIPTOR IfDesc;
> + UINT16 *LangIdTable;
> + UINT16 TableSize;
> + UINT16 Index;
> + CHAR16 *CompareStr;
> + UINTN CompareLen;
> + CHAR16 *SerialNumberStr;
> + UINTN Length;
> +
> + if ((DevicePathType (UsbWwid) != MESSAGING_DEVICE_PATH) ||
> + (DevicePathSubType (UsbWwid) != MSG_USB_WWID_DP )){
> + return FALSE;
> + }
> +
> + //
> + // Check Vendor Id and Product Id.
> + //
> + Status = UsbIo->UsbGetDeviceDescriptor (UsbIo, &DevDesc);
> + if (EFI_ERROR (Status)) {
> + return FALSE;
> + }
> + if ((DevDesc.IdVendor != UsbWwid->VendorId) ||
> + (DevDesc.IdProduct != UsbWwid->ProductId)) {
> + return FALSE;
> + }
> +
> + //
> + // Check Interface Number.
> + //
> + Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &IfDesc);
> + if (EFI_ERROR (Status)) {
> + return FALSE;
> + }
> + if (IfDesc.InterfaceNumber != UsbWwid->InterfaceNumber) {
> + return FALSE;
> + }
> +
> + //
> + // Check Serial Number.
> + //
> + if (DevDesc.StrSerialNumber == 0) {
> + return FALSE;
> + }
> +
> + //
> + // Get all supported languages.
> + //
> + TableSize = 0;
> + LangIdTable = NULL;
> + Status = UsbIo->UsbGetSupportedLanguages (UsbIo, &LangIdTable,
> &TableSize);
> + if (EFI_ERROR (Status) || (TableSize == 0) || (LangIdTable == NULL)) {
> + return FALSE;
> + }
> +
> + //
> + // Serial number in USB WWID device path is the last 64-or-less UTF-16
> characters.
> + //
> + CompareStr = (CHAR16 *) (UINTN) (UsbWwid + 1);
> + CompareLen = (DevicePathNodeLength (UsbWwid) - sizeof
> (USB_WWID_DEVICE_PATH)) / sizeof (CHAR16);
> + if (CompareStr[CompareLen - 1] == L'\0') {
> + CompareLen--;
> + }
> +
> + //
> + // Compare serial number in each supported language.
> + //
> + for (Index = 0; Index < TableSize / sizeof (UINT16); Index++) {
> + SerialNumberStr = NULL;
> + Status = UsbIo->UsbGetStringDescriptor (
> + UsbIo,
> + LangIdTable[Index],
> + DevDesc.StrSerialNumber,
> + &SerialNumberStr
> + );
> + if (EFI_ERROR (Status) || (SerialNumberStr == NULL)) {
> + continue;
> + }
> +
> + Length = StrLen (SerialNumberStr);
> + if ((Length >= CompareLen) &&
> + (CompareMem (SerialNumberStr + Length - CompareLen, CompareStr,
> CompareLen * sizeof (CHAR16)) == 0)) {
> + FreePool (SerialNumberStr);
> + return TRUE;
> + }
> +
> + FreePool (SerialNumberStr);
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Find a USB device path which match the specified short-form device path
> start
> + with USB Class or USB WWID device path and load the boot file then return
> the
> + image handle. If ParentDevicePath is NULL, this function will search in all
> USB
> + devices of the platform. If ParentDevicePath is not NULL,this function will
> only
> + search in its child devices.
> +
> + @param ParentDevicePath The device path of the parent.
> + @param ShortFormDevicePath The USB Class or USB WWID device path
> to match.
> +
> + @return The image Handle if find load file from specified short-form
> device path
> + or NULL if not found.
> +
> +**/
> +EFI_HANDLE *
> +BdsFindUsbDevice (
> + IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
> + IN EFI_DEVICE_PATH_PROTOCOL *ShortFormDevicePath
> + )
> +{
> + EFI_STATUS Status;
> + UINTN UsbIoHandleCount;
> + EFI_HANDLE *UsbIoHandleBuffer;
> + EFI_DEVICE_PATH_PROTOCOL *UsbIoDevicePath;
> + EFI_USB_IO_PROTOCOL *UsbIo;
> + UINTN Index;
> + UINTN ParentSize;
> + UINTN Size;
> + EFI_HANDLE ImageHandle;
> + EFI_HANDLE Handle;
> + EFI_DEVICE_PATH_PROTOCOL *FullDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *NextDevicePath;
> +
> + FullDevicePath = NULL;
> + ImageHandle = NULL;
> +
> + //
> + // Get all UsbIo Handles.
> + //
> + UsbIoHandleCount = 0;
> + UsbIoHandleBuffer = NULL;
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiUsbIoProtocolGuid,
> + NULL,
> + &UsbIoHandleCount,
> + &UsbIoHandleBuffer
> + );
> + if (EFI_ERROR (Status) || (UsbIoHandleCount == 0) || (UsbIoHandleBuffer
> == NULL)) {
> + return NULL;
> + }
> +
> + ParentSize = (ParentDevicePath == NULL) ? 0 : GetDevicePathSize
> (ParentDevicePath);
> + for (Index = 0; Index < UsbIoHandleCount; Index++) {
> + //
> + // Get the Usb IO interface.
> + //
> + Status = gBS->HandleProtocol(
> + UsbIoHandleBuffer[Index],
> + &gEfiUsbIoProtocolGuid,
> + (VOID **) &UsbIo
> + );
> + if (EFI_ERROR (Status)) {
> + continue;
> + }
> +
> + UsbIoDevicePath = DevicePathFromHandle (UsbIoHandleBuffer[Index]);
> + if (UsbIoDevicePath == NULL) {
> + continue;
> + }
> +
> + if (ParentDevicePath != NULL) {
> + //
> + // Compare starting part of UsbIoHandle's device path with
> ParentDevicePath.
> + //
> + Size = GetDevicePathSize (UsbIoDevicePath);
> + if ((Size < ParentSize) ||
> + (CompareMem (UsbIoDevicePath, ParentDevicePath, ParentSize -
> END_DEVICE_PATH_LENGTH) != 0)) {
> + continue;
> + }
> + }
> +
> + if (BdsMatchUsbClass (UsbIo, (USB_CLASS_DEVICE_PATH *)
> ShortFormDevicePath) ||
> + BdsMatchUsbWwid (UsbIo, (USB_WWID_DEVICE_PATH *)
> ShortFormDevicePath)) {
> + //
> + // Try to find if there is the boot file in this DevicePath
> + //
> + NextDevicePath = NextDevicePathNode (ShortFormDevicePath);
> + if (!IsDevicePathEnd (NextDevicePath)) {
> + FullDevicePath = AppendDevicePath (UsbIoDevicePath,
> NextDevicePath);
> + //
> + // Connect the full device path, so that Simple File System protocol
> + // could be installed for this USB device.
> + //
> + BdsLibConnectDevicePath (FullDevicePath);
> + REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32
> (PcdProgressCodeOsLoaderLoad));
> + Status = gBS->LoadImage (
> + TRUE,
> + gImageHandle,
> + FullDevicePath,
> + NULL,
> + 0,
> + &ImageHandle
> + );
> + FreePool (FullDevicePath);
> + } else {
> + FullDevicePath = UsbIoDevicePath;
> + Status = EFI_NOT_FOUND;
> + }
> +
> + //
> + // If we didn't find an image directly, we need to try as if it is a removable
> device boot option
> + // and load the image according to the default boot behavior for
> removable device.
> + //
> + if (EFI_ERROR (Status)) {
> + //
> + // check if there is a bootable removable media could be found in this
> device path ,
> + // and get the bootable media handle
> + //
> + Handle = BdsLibGetBootableHandle(UsbIoDevicePath);
> + if (Handle == NULL) {
> + continue;
> + }
> + //
> + // Load the default boot file \EFI\BOOT\boot{machinename}.EFI from
> removable Media
> + // machinename is ia32, ia64, x64, ...
> + //
> + FullDevicePath = FileDevicePath (Handle,
> EFI_REMOVABLE_MEDIA_FILE_NAME);
> + if (FullDevicePath != NULL) {
> + REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32
> (PcdProgressCodeOsLoaderLoad));
> + Status = gBS->LoadImage (
> + TRUE,
> + gImageHandle,
> + FullDevicePath,
> + NULL,
> + 0,
> + &ImageHandle
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + // The DevicePath failed, and it's not a valid
> + // removable media device.
> + //
> + continue;
> + }
> + } else {
> + continue;
> + }
> + }
> + break;
> + }
> + }
> +
> + FreePool (UsbIoHandleBuffer);
> + return ImageHandle;
> +}
> +
> +/**
> + Expand USB Class or USB WWID device path node to be full device path of
> a USB
> + device in platform then load the boot file on this full device path and
> return the
> + image handle.
> +
> + This function support following 4 cases:
> + 1) Boot Option device path starts with a USB Class or USB WWID device
> path,
> + and there is no Media FilePath device path in the end.
> + In this case, it will follow Removable Media Boot Behavior.
> + 2) Boot Option device path starts with a USB Class or USB WWID device
> path,
> + and ended with Media FilePath device path.
> + 3) Boot Option device path starts with a full device path to a USB Host
> Controller,
> + contains a USB Class or USB WWID device path node, while not ended
> with Media
> + FilePath device path. In this case, it will follow Removable Media Boot
> Behavior.
> + 4) Boot Option device path starts with a full device path to a USB Host
> Controller,
> + contains a USB Class or USB WWID device path node, and ended with
> Media
> + FilePath device path.
> +
> + @param DevicePath The Boot Option device path.
> +
> + @return The image handle of boot file, or NULL if there is no boot file
> found in
> + the specified USB Class or USB WWID device path.
> +
> +**/
> +EFI_HANDLE *
> +BdsExpandUsbShortFormDevicePath (
> + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
> + )
> +{
> + EFI_HANDLE *ImageHandle;
> + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *ShortFormDevicePath;
> +
> + //
> + // Search for USB Class or USB WWID device path node.
> + //
> + ShortFormDevicePath = NULL;
> + ImageHandle = NULL;
> + TempDevicePath = DevicePath;
> + while (!IsDevicePathEnd (TempDevicePath)) {
> + if ((DevicePathType (TempDevicePath) == MESSAGING_DEVICE_PATH)
> &&
> + ((DevicePathSubType (TempDevicePath) == MSG_USB_CLASS_DP) ||
> + (DevicePathSubType (TempDevicePath) == MSG_USB_WWID_DP))) {
> + ShortFormDevicePath = TempDevicePath;
> + break;
> + }
> + TempDevicePath = NextDevicePathNode (TempDevicePath);
> + }
> +
> + if (ShortFormDevicePath == NULL) {
> + //
> + // No USB Class or USB WWID device path node found, do nothing.
> + //
> + return NULL;
> + }
> +
> + if (ShortFormDevicePath == DevicePath) {
> + //
> + // Boot Option device path starts with USB Class or USB WWID device
> path.
> + //
> + ImageHandle = BdsFindUsbDevice (NULL, ShortFormDevicePath);
> + if (ImageHandle == NULL) {
> + //
> + // Failed to find a match in existing devices, connect the short form USB
> + // device path and try again.
> + //
> + BdsLibConnectUsbDevByShortFormDP (0xff, ShortFormDevicePath);
> + ImageHandle = BdsFindUsbDevice (NULL, ShortFormDevicePath);
> + }
> + } else {
> + //
> + // Boot Option device path contains USB Class or USB WWID device path
> node.
> + //
> +
> + //
> + // Prepare the parent device path for search.
> + //
> + TempDevicePath = DuplicateDevicePath (DevicePath);
> + ASSERT (TempDevicePath != NULL);
> + SetDevicePathEndNode (((UINT8 *) TempDevicePath) + ((UINTN)
> ShortFormDevicePath - (UINTN) DevicePath));
> +
> + //
> + // The USB Host Controller device path is already in Boot Option device
> path
> + // and USB Bus driver already support RemainingDevicePath starts with
> USB
> + // Class or USB WWID device path, so just search in existing USB devices
> and
> + // doesn't perform ConnectController here.
> + //
> + ImageHandle = BdsFindUsbDevice (TempDevicePath,
> ShortFormDevicePath);
> + FreePool (TempDevicePath);
> + }
> +
> + return ImageHandle;
> +}
> +
> +/**
> + Process the boot option follow the UEFI specification and
> + special treat the legacy boot option with BBS_DEVICE_PATH.
> +
> + @param Option The boot option need to be processed
> + @param DevicePath The device path which describe where to load
> the
> + boot image or the legacy BBS device path to boot
> + the legacy OS
> + @param ExitDataSize The size of exit data.
> + @param ExitData Data returned when Boot image failed.
> +
> + @retval EFI_SUCCESS Boot from the input boot option successfully.
> + @retval EFI_NOT_FOUND If the Device Path is not found in the
> system
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibBootViaBootOption (
> + IN BDS_COMMON_OPTION *Option,
> + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
> + OUT UINTN *ExitDataSize,
> + OUT CHAR16 **ExitData OPTIONAL
> + )
> +{
> + EFI_STATUS Status;
> + EFI_STATUS StatusLogo;
> + EFI_HANDLE Handle;
> + EFI_HANDLE ImageHandle;
> + EFI_DEVICE_PATH_PROTOCOL *FilePath;
> + EFI_LOADED_IMAGE_PROTOCOL *ImageInfo;
> + EFI_DEVICE_PATH_PROTOCOL *WorkingDevicePath;
> + EFI_ACPI_S3_SAVE_PROTOCOL *AcpiS3Save;
> + LIST_ENTRY TempBootLists;
> + EFI_BOOT_LOGO_PROTOCOL *BootLogo;
> +
> + *ExitDataSize = 0;
> + *ExitData = NULL;
> +
> + //
> + // Notes: this code can be remove after the s3 script table
> + // hook on the event EVT_SIGNAL_READY_TO_BOOT or
> + // EVT_SIGNAL_LEGACY_BOOT
> + //
> + Status = gBS->LocateProtocol (&gEfiAcpiS3SaveProtocolGuid, NULL, (VOID
> **) &AcpiS3Save);
> + if (!EFI_ERROR (Status)) {
> + AcpiS3Save->S3Save (AcpiS3Save, NULL);
> + }
> + //
> + // If it's Device Path that starts with a hard drive path, append it with the
> front part to compose a
> + // full device path
> + //
> + WorkingDevicePath = NULL;
> + if ((DevicePathType (DevicePath) == MEDIA_DEVICE_PATH) &&
> + (DevicePathSubType (DevicePath) == MEDIA_HARDDRIVE_DP)) {
> + WorkingDevicePath = BdsExpandPartitionPartialDevicePathToFull (
> + (HARDDRIVE_DEVICE_PATH *)DevicePath
> + );
> + if (WorkingDevicePath != NULL) {
> + DevicePath = WorkingDevicePath;
> + }
> + }
> +
> + //
> + // Set Boot Current
> + //
> + if (IsBootOptionValidNVVarialbe (Option)) {
> + //
> + // For a temporary boot (i.e. a boot by selected a EFI Shell using "Boot
> From File"), Boot Current is actually not valid.
> + // In this case, "BootCurrent" is not created.
> + // Only create the BootCurrent variable when it points to a valid Boot####
> variable.
> + //
> + SetVariableAndReportStatusCodeOnError (
> + L"BootCurrent",
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS,
> + sizeof (UINT16),
> + &Option->BootCurrent
> + );
> + }
> +
> + //
> + // Report Status Code to indicate ReadyToBoot event will be signalled
> + //
> + REPORT_STATUS_CODE (EFI_PROGRESS_CODE,
> (EFI_SOFTWARE_DXE_BS_DRIVER |
> EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT));
> +
> + //
> + // Signal the EVT_SIGNAL_READY_TO_BOOT event
> + //
> + EfiSignalEventReadyToBoot();
> +
> + //
> + // Expand USB Class or USB WWID device path node to be full device path
> of a USB
> + // device in platform then load the boot file on this full device path and get
> the
> + // image handle.
> + //
> + ImageHandle = BdsExpandUsbShortFormDevicePath (DevicePath);
> +
> + //
> + // Adjust the different type memory page number just before booting
> + // and save the updated info into the variable for next boot to use
> + //
> + BdsSetMemoryTypeInformationVariable ();
> +
> + //
> + // By expanding the USB Class or WWID device path, the ImageHandle has
> returnned.
> + // Here get the ImageHandle for the non USB class or WWID device path.
> + //
> + if (ImageHandle == NULL) {
> + ASSERT (Option->DevicePath != NULL);
> + if ((DevicePathType (Option->DevicePath) == BBS_DEVICE_PATH) &&
> + (DevicePathSubType (Option->DevicePath) == BBS_BBS_DP)
> + ) {
> + //
> + // Check to see if we should legacy BOOT. If yes then do the legacy boot
> + //
> + return BdsLibDoLegacyBoot (Option);
> + }
> +
> + //
> + // If the boot option point to Internal FV shell, make sure it is valid
> + //
> + Status = BdsLibUpdateFvFileDevicePath (&DevicePath,
> &gUefiShellFileGuid);
> + if (!EFI_ERROR(Status)) {
> + if (Option->DevicePath != NULL) {
> + FreePool(Option->DevicePath);
> + }
> + Option->DevicePath = AllocateZeroPool (GetDevicePathSize
> (DevicePath));
> + ASSERT(Option->DevicePath != NULL);
> + CopyMem (Option->DevicePath, DevicePath, GetDevicePathSize
> (DevicePath));
> + //
> + // Update the shell boot option
> + //
> + InitializeListHead (&TempBootLists);
> + BdsLibRegisterNewOption (&TempBootLists, DevicePath, L"EFI Internal
> Shell", L"BootOrder");
> +
> + //
> + // free the temporary device path created by
> BdsLibUpdateFvFileDevicePath()
> + //
> + FreePool (DevicePath);
> + DevicePath = Option->DevicePath;
> + }
> +
> + DEBUG_CODE_BEGIN();
> +
> + if (Option->Description == NULL) {
> + DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Booting from unknown device
> path\n"));
> + } else {
> + DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Booting %S\n", Option-
> >Description));
> + }
> +
> + DEBUG_CODE_END();
> +
> + //
> + // Report status code for OS Loader LoadImage.
> + //
> + REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32
> (PcdProgressCodeOsLoaderLoad));
> + Status = gBS->LoadImage (
> + TRUE,
> + gImageHandle,
> + DevicePath,
> + NULL,
> + 0,
> + &ImageHandle
> + );
> +
> + //
> + // If we didn't find an image directly, we need to try as if it is a removable
> device boot option
> + // and load the image according to the default boot behavior for
> removable device.
> + //
> + if (EFI_ERROR (Status)) {
> + //
> + // check if there is a bootable removable media could be found in this
> device path ,
> + // and get the bootable media handle
> + //
> + Handle = BdsLibGetBootableHandle(DevicePath);
> + if (Handle != NULL) {
> + //
> + // Load the default boot file \EFI\BOOT\boot{machinename}.EFI from
> removable Media
> + // machinename is ia32, ia64, x64, ...
> + //
> + FilePath = FileDevicePath (Handle,
> EFI_REMOVABLE_MEDIA_FILE_NAME);
> + if (FilePath != NULL) {
> + REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32
> (PcdProgressCodeOsLoaderLoad));
> + Status = gBS->LoadImage (
> + TRUE,
> + gImageHandle,
> + FilePath,
> + NULL,
> + 0,
> + &ImageHandle
> + );
> + }
> + }
> + }
> + }
> + //
> + // Provide the image with it's load options
> + //
> + if ((ImageHandle == NULL) || (EFI_ERROR(Status))) {
> + //
> + // Report Status Code to indicate that the failure to load boot option
> + //
> + REPORT_STATUS_CODE (
> + EFI_ERROR_CODE | EFI_ERROR_MINOR,
> + (EFI_SOFTWARE_DXE_BS_DRIVER |
> EFI_SW_DXE_BS_EC_BOOT_OPTION_LOAD_ERROR)
> + );
> + goto Done;
> + }
> +
> + Status = gBS->HandleProtocol (ImageHandle,
> &gEfiLoadedImageProtocolGuid, (VOID **) &ImageInfo);
> + ASSERT_EFI_ERROR (Status);
> +
> + if (Option->LoadOptionsSize != 0) {
> + ImageInfo->LoadOptionsSize = Option->LoadOptionsSize;
> + ImageInfo->LoadOptions = Option->LoadOptions;
> + }
> +
> + //
> + // Clean to NULL because the image is loaded directly from the firmwares
> boot manager.
> + //
> + ImageInfo->ParentHandle = NULL;
> +
> + //
> + // Before calling the image, enable the Watchdog Timer for
> + // the 5 Minute period
> + //
> + gBS->SetWatchdogTimer (5 * 60, 0x0000, 0x00, NULL);
> +
> + //
> + // Write boot to OS performance data for UEFI boot
> + //
> + PERF_CODE (
> + BmEndOfBdsPerfCode (NULL, NULL);
> + );
> +
> + //
> + // Report status code for OS Loader StartImage.
> + //
> + REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32
> (PcdProgressCodeOsLoaderStart));
> +
> + Status = gBS->StartImage (ImageHandle, ExitDataSize, ExitData);
> + DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Image Return Status = %r\n",
> Status));
> + if (EFI_ERROR (Status)) {
> + //
> + // Report Status Code to indicate that boot failure
> + //
> + REPORT_STATUS_CODE (
> + EFI_ERROR_CODE | EFI_ERROR_MINOR,
> + (EFI_SOFTWARE_DXE_BS_DRIVER |
> EFI_SW_DXE_BS_EC_BOOT_OPTION_FAILED)
> + );
> + }
> +
> + //
> + // Clear the Watchdog Timer after the image returns
> + //
> + gBS->SetWatchdogTimer (0x0000, 0x0000, 0x0000, NULL);
> +
> +Done:
> + //
> + // Set Logo status invalid after trying one boot option
> + //
> + BootLogo = NULL;
> + StatusLogo = gBS->LocateProtocol (&gEfiBootLogoProtocolGuid, NULL,
> (VOID **) &BootLogo);
> + if (!EFI_ERROR (StatusLogo) && (BootLogo != NULL)) {
> + BootLogo->SetBootLogo (BootLogo, NULL, 0, 0, 0, 0);
> + }
> +
> + //
> + // Clear Boot Current
> + // Deleting variable with current implementation shouldn't fail.
> + //
> + gRT->SetVariable (
> + L"BootCurrent",
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS,
> + 0,
> + NULL
> + );
> +
> + return Status;
> +}
> +
> +
> +/**
> + Expand a device path that starts with a hard drive media device path node
> to be a
> + full device path that includes the full hardware path to the device. We
> need
> + to do this so it can be booted. As an optimization the front match (the part
> point
> + to the partition node. E.g. ACPI() /PCI()/ATA()/Partition() ) is saved in a
> variable
> + so a connect all is not required on every boot. All successful history device
> path
> + which point to partition node (the front part) will be saved.
> +
> + @param HardDriveDevicePath EFI Device Path to boot, if it starts with a
> hard
> + drive media device path.
> + @return A Pointer to the full device path or NULL if a valid Hard Drive devic
> path
> + cannot be found.
> +
> +**/
> +EFI_DEVICE_PATH_PROTOCOL *
> +EFIAPI
> +BdsExpandPartitionPartialDevicePathToFull (
> + IN HARDDRIVE_DEVICE_PATH *HardDriveDevicePath
> + )
> +{
> + EFI_STATUS Status;
> + UINTN BlockIoHandleCount;
> + EFI_HANDLE *BlockIoBuffer;
> + EFI_DEVICE_PATH_PROTOCOL *FullDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *BlockIoDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + UINTN Index;
> + UINTN InstanceNum;
> + EFI_DEVICE_PATH_PROTOCOL *CachedDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *TempNewDevicePath;
> + UINTN CachedDevicePathSize;
> + BOOLEAN DeviceExist;
> + BOOLEAN NeedAdjust;
> + EFI_DEVICE_PATH_PROTOCOL *Instance;
> + UINTN Size;
> +
> + FullDevicePath = NULL;
> + //
> + // Check if there is prestore HD_BOOT_DEVICE_PATH_VARIABLE_NAME
> variable.
> + // If exist, search the front path which point to partition node in the
> variable instants.
> + // If fail to find or HD_BOOT_DEVICE_PATH_VARIABLE_NAME not exist,
> reconnect all and search in all system
> + //
> + GetVariable2 (
> + HD_BOOT_DEVICE_PATH_VARIABLE_NAME,
> + &gHdBootDevicePathVariablGuid,
> + (VOID **) &CachedDevicePath,
> + &CachedDevicePathSize
> + );
> +
> + //
> + // Delete the invalid HD_BOOT_DEVICE_PATH_VARIABLE_NAME variable.
> + //
> + if ((CachedDevicePath != NULL) && !IsDevicePathValid (CachedDevicePath,
> CachedDevicePathSize)) {
> + FreePool (CachedDevicePath);
> + CachedDevicePath = NULL;
> + Status = gRT->SetVariable (
> + HD_BOOT_DEVICE_PATH_VARIABLE_NAME,
> + &gHdBootDevicePathVariablGuid,
> + 0,
> + 0,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + if (CachedDevicePath != NULL) {
> + TempNewDevicePath = CachedDevicePath;
> + DeviceExist = FALSE;
> + NeedAdjust = FALSE;
> + do {
> + //
> + // Check every instance of the variable
> + // First, check whether the instance contain the partition node, which is
> needed for distinguishing multi
> + // partial partition boot option. Second, check whether the instance
> could be connected.
> + //
> + Instance = GetNextDevicePathInstance (&TempNewDevicePath, &Size);
> + if (MatchPartitionDevicePathNode (Instance, HardDriveDevicePath)) {
> + //
> + // Connect the device path instance, the device path point to hard drive
> media device path node
> + // e.g. ACPI() /PCI()/ATA()/Partition()
> + //
> + Status = BdsLibConnectDevicePath (Instance);
> + if (!EFI_ERROR (Status)) {
> + DeviceExist = TRUE;
> + break;
> + }
> + }
> + //
> + // Come here means the first instance is not matched
> + //
> + NeedAdjust = TRUE;
> + FreePool(Instance);
> + } while (TempNewDevicePath != NULL);
> +
> + if (DeviceExist) {
> + //
> + // Find the matched device path.
> + // Append the file path information from the boot option and return the
> fully expanded device path.
> + //
> + DevicePath = NextDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *)
> HardDriveDevicePath);
> + FullDevicePath = AppendDevicePath (Instance, DevicePath);
> +
> + //
> + // Adjust the HD_BOOT_DEVICE_PATH_VARIABLE_NAME instances
> sequence if the matched one is not first one.
> + //
> + if (NeedAdjust) {
> + //
> + // First delete the matched instance.
> + //
> + TempNewDevicePath = CachedDevicePath;
> + CachedDevicePath = BdsLibDelPartMatchInstance (CachedDevicePath,
> Instance );
> + FreePool (TempNewDevicePath);
> +
> + //
> + // Second, append the remaining path after the matched instance
> + //
> + TempNewDevicePath = CachedDevicePath;
> + CachedDevicePath = AppendDevicePathInstance (Instance,
> CachedDevicePath );
> + FreePool (TempNewDevicePath);
> + //
> + // Save the matching Device Path so we don't need to do a connect all
> next time
> + // Failure to set the variable only impacts the performance when next
> time expanding the short-form device path.
> + //
> + Status = gRT->SetVariable (
> + HD_BOOT_DEVICE_PATH_VARIABLE_NAME,
> + &gHdBootDevicePathVariablGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_NON_VOLATILE,
> + GetDevicePathSize (CachedDevicePath),
> + CachedDevicePath
> + );
> + }
> +
> + FreePool (Instance);
> + FreePool (CachedDevicePath);
> + return FullDevicePath;
> + }
> + }
> +
> + //
> + // If we get here we fail to find or
> HD_BOOT_DEVICE_PATH_VARIABLE_NAME not exist, and now we need
> + // to search all devices in the system for a matched partition
> + //
> + BdsLibConnectAllDriversToAllControllers ();
> + Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiBlockIoProtocolGuid,
> NULL, &BlockIoHandleCount, &BlockIoBuffer);
> + if (EFI_ERROR (Status) || BlockIoHandleCount == 0 || BlockIoBuffer ==
> NULL) {
> + //
> + // If there was an error or there are no device handles that support
> + // the BLOCK_IO Protocol, then return.
> + //
> + return NULL;
> + }
> + //
> + // Loop through all the device handles that support the BLOCK_IO Protocol
> + //
> + for (Index = 0; Index < BlockIoHandleCount; Index++) {
> +
> + Status = gBS->HandleProtocol (BlockIoBuffer[Index],
> &gEfiDevicePathProtocolGuid, (VOID *) &BlockIoDevicePath);
> + if (EFI_ERROR (Status) || BlockIoDevicePath == NULL) {
> + continue;
> + }
> +
> + if (MatchPartitionDevicePathNode (BlockIoDevicePath,
> HardDriveDevicePath)) {
> + //
> + // Find the matched partition device path
> + //
> + DevicePath = NextDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *)
> HardDriveDevicePath);
> + FullDevicePath = AppendDevicePath (BlockIoDevicePath, DevicePath);
> +
> + //
> + // Save the matched partition device path in
> HD_BOOT_DEVICE_PATH_VARIABLE_NAME variable
> + //
> + if (CachedDevicePath != NULL) {
> + //
> + // Save the matched partition device path as first instance of
> HD_BOOT_DEVICE_PATH_VARIABLE_NAME variable
> + //
> + if (BdsLibMatchDevicePaths (CachedDevicePath, BlockIoDevicePath)) {
> + TempNewDevicePath = CachedDevicePath;
> + CachedDevicePath = BdsLibDelPartMatchInstance (CachedDevicePath,
> BlockIoDevicePath);
> + FreePool(TempNewDevicePath);
> + }
> +
> + if (CachedDevicePath != NULL) {
> + TempNewDevicePath = CachedDevicePath;
> + CachedDevicePath = AppendDevicePathInstance (BlockIoDevicePath,
> CachedDevicePath);
> + FreePool(TempNewDevicePath);
> + } else {
> + CachedDevicePath = DuplicateDevicePath (BlockIoDevicePath);
> + }
> +
> + //
> + // Here limit the device path instance number to 12, which is max
> number for a system support 3 IDE controller
> + // If the user try to boot many OS in different HDs or partitions, in
> theory,
> + // the HD_BOOT_DEVICE_PATH_VARIABLE_NAME variable maybe
> become larger and larger.
> + //
> + InstanceNum = 0;
> + ASSERT (CachedDevicePath != NULL);
> + TempNewDevicePath = CachedDevicePath;
> + while (!IsDevicePathEnd (TempNewDevicePath)) {
> + TempNewDevicePath = NextDevicePathNode (TempNewDevicePath);
> + //
> + // Parse one instance
> + //
> + while (!IsDevicePathEndType (TempNewDevicePath)) {
> + TempNewDevicePath = NextDevicePathNode (TempNewDevicePath);
> + }
> + InstanceNum++;
> + //
> + // If the CachedDevicePath variable contain too much instance, only
> remain 12 instances.
> + //
> + if (InstanceNum >= 12) {
> + SetDevicePathEndNode (TempNewDevicePath);
> + break;
> + }
> + }
> + } else {
> + CachedDevicePath = DuplicateDevicePath (BlockIoDevicePath);
> + }
> +
> + //
> + // Save the matching Device Path so we don't need to do a connect all
> next time
> + // Failure to set the variable only impacts the performance when next
> time expanding the short-form device path.
> + //
> + Status = gRT->SetVariable (
> + HD_BOOT_DEVICE_PATH_VARIABLE_NAME,
> + &gHdBootDevicePathVariablGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_NON_VOLATILE,
> + GetDevicePathSize (CachedDevicePath),
> + CachedDevicePath
> + );
> +
> + break;
> + }
> + }
> +
> + if (CachedDevicePath != NULL) {
> + FreePool (CachedDevicePath);
> + }
> + if (BlockIoBuffer != NULL) {
> + FreePool (BlockIoBuffer);
> + }
> + return FullDevicePath;
> +}
> +
> +/**
> + Check whether there is a instance in BlockIoDevicePath, which contain
> multi device path
> + instances, has the same partition node with HardDriveDevicePath device
> path
> +
> + @param BlockIoDevicePath Multi device path instances which need to
> check
> + @param HardDriveDevicePath A device path which starts with a hard
> drive media
> + device path.
> +
> + @retval TRUE There is a matched device path instance.
> + @retval FALSE There is no matched device path instance.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +MatchPartitionDevicePathNode (
> + IN EFI_DEVICE_PATH_PROTOCOL *BlockIoDevicePath,
> + IN HARDDRIVE_DEVICE_PATH *HardDriveDevicePath
> + )
> +{
> + HARDDRIVE_DEVICE_PATH *TmpHdPath;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + BOOLEAN Match;
> + EFI_DEVICE_PATH_PROTOCOL *BlockIoHdDevicePathNode;
> +
> + if ((BlockIoDevicePath == NULL) || (HardDriveDevicePath == NULL)) {
> + return FALSE;
> + }
> +
> + //
> + // Make PreviousDevicePath == the device path node before the end
> node
> + //
> + DevicePath = BlockIoDevicePath;
> + BlockIoHdDevicePathNode = NULL;
> +
> + //
> + // find the partition device path node
> + //
> + while (!IsDevicePathEnd (DevicePath)) {
> + if ((DevicePathType (DevicePath) == MEDIA_DEVICE_PATH) &&
> + (DevicePathSubType (DevicePath) == MEDIA_HARDDRIVE_DP)
> + ) {
> + BlockIoHdDevicePathNode = DevicePath;
> + break;
> + }
> +
> + DevicePath = NextDevicePathNode (DevicePath);
> + }
> +
> + if (BlockIoHdDevicePathNode == NULL) {
> + return FALSE;
> + }
> + //
> + // See if the harddrive device path in blockio matches the orig Hard Drive
> Node
> + //
> + TmpHdPath = (HARDDRIVE_DEVICE_PATH *) BlockIoHdDevicePathNode;
> + Match = FALSE;
> +
> + //
> + // Check for the match
> + //
> + if ((TmpHdPath->MBRType == HardDriveDevicePath->MBRType) &&
> + (TmpHdPath->SignatureType == HardDriveDevicePath->SignatureType))
> {
> + switch (TmpHdPath->SignatureType) {
> + case SIGNATURE_TYPE_GUID:
> + Match = CompareGuid ((EFI_GUID *)TmpHdPath->Signature, (EFI_GUID
> *)HardDriveDevicePath->Signature);
> + break;
> + case SIGNATURE_TYPE_MBR:
> + Match = (BOOLEAN)(*((UINT32 *)(&(TmpHdPath->Signature[0]))) ==
> ReadUnaligned32((UINT32 *)(&(HardDriveDevicePath->Signature[0]))));
> + break;
> + default:
> + Match = FALSE;
> + break;
> + }
> + }
> +
> + return Match;
> +}
> +
> +/**
> + Delete the boot option associated with the handle passed in.
> +
> + @param Handle The handle which present the device path to
> create
> + boot option
> +
> + @retval EFI_SUCCESS Delete the boot option success
> + @retval EFI_NOT_FOUND If the Device Path is not found in the
> system
> + @retval EFI_OUT_OF_RESOURCES Lack of memory resource
> + @retval Other Error return value from SetVariable()
> +
> +**/
> +EFI_STATUS
> +BdsLibDeleteOptionFromHandle (
> + IN EFI_HANDLE Handle
> + )
> +{
> + UINT16 *BootOrder;
> + UINT8 *BootOptionVar;
> + UINTN BootOrderSize;
> + UINTN BootOptionSize;
> + EFI_STATUS Status;
> + UINTN Index;
> + UINT16 BootOption[BOOT_OPTION_MAX_CHAR];
> + UINTN DevicePathSize;
> + UINTN OptionDevicePathSize;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *OptionDevicePath;
> + UINT8 *TempPtr;
> +
> + Status = EFI_SUCCESS;
> + BootOrder = NULL;
> + BootOrderSize = 0;
> +
> + //
> + // Check "BootOrder" variable, if no, means there is no any boot order.
> + //
> + BootOrder = BdsLibGetVariableAndSize (
> + L"BootOrder",
> + &gEfiGlobalVariableGuid,
> + &BootOrderSize
> + );
> + if (BootOrder == NULL) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // Convert device handle to device path protocol instance
> + //
> + DevicePath = DevicePathFromHandle (Handle);
> + if (DevicePath == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + DevicePathSize = GetDevicePathSize (DevicePath);
> +
> + //
> + // Loop all boot order variable and find the matching device path
> + //
> + Index = 0;
> + while (Index < BootOrderSize / sizeof (UINT16)) {
> + UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x",
> BootOrder[Index]);
> + BootOptionVar = BdsLibGetVariableAndSize (
> + BootOption,
> + &gEfiGlobalVariableGuid,
> + &BootOptionSize
> + );
> +
> + if (BootOptionVar == NULL) {
> + FreePool (BootOrder);
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + if (!ValidateOption(BootOptionVar, BootOptionSize)) {
> + BdsDeleteBootOption (BootOrder[Index], BootOrder, &BootOrderSize);
> + FreePool (BootOptionVar);
> + Index++;
> + continue;
> + }
> +
> + TempPtr = BootOptionVar;
> + TempPtr += sizeof (UINT32) + sizeof (UINT16);
> + TempPtr += StrSize ((CHAR16 *) TempPtr);
> + OptionDevicePath = (EFI_DEVICE_PATH_PROTOCOL *) TempPtr;
> + OptionDevicePathSize = GetDevicePathSize (OptionDevicePath);
> +
> + //
> + // Check whether the device path match
> + //
> + if ((OptionDevicePathSize == DevicePathSize) &&
> + (CompareMem (DevicePath, OptionDevicePath, DevicePathSize) == 0))
> {
> + BdsDeleteBootOption (BootOrder[Index], BootOrder, &BootOrderSize);
> + FreePool (BootOptionVar);
> + break;
> + }
> +
> + FreePool (BootOptionVar);
> + Index++;
> + }
> +
> + //
> + // Adjust number of boot option for "BootOrder" variable.
> + //
> + Status = gRT->SetVariable (
> + L"BootOrder",
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + BootOrderSize,
> + BootOrder
> + );
> + //
> + // Shrinking variable with existing variable implementation shouldn't fail.
> + //
> + ASSERT_EFI_ERROR (Status);
> +
> + FreePool (BootOrder);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Delete all invalid EFI boot options.
> +
> + @retval EFI_SUCCESS Delete all invalid boot option success
> + @retval EFI_NOT_FOUND Variable "BootOrder" is not found
> + @retval EFI_OUT_OF_RESOURCES Lack of memory resource
> + @retval Other Error return value from SetVariable()
> +
> +**/
> +EFI_STATUS
> +BdsDeleteAllInvalidEfiBootOption (
> + VOID
> + )
> +{
> + UINT16 *BootOrder;
> + UINT8 *BootOptionVar;
> + UINTN BootOrderSize;
> + UINTN BootOptionSize;
> + EFI_STATUS Status;
> + UINTN Index;
> + UINTN Index2;
> + UINT16 BootOption[BOOT_OPTION_MAX_CHAR];
> + EFI_DEVICE_PATH_PROTOCOL *OptionDevicePath;
> + UINT8 *TempPtr;
> + CHAR16 *Description;
> + BOOLEAN Corrupted;
> +
> + Status = EFI_SUCCESS;
> + BootOrder = NULL;
> + Description = NULL;
> + OptionDevicePath = NULL;
> + BootOrderSize = 0;
> + Corrupted = FALSE;
> +
> + //
> + // Check "BootOrder" variable firstly, this variable hold the number of boot
> options
> + //
> + BootOrder = BdsLibGetVariableAndSize (
> + L"BootOrder",
> + &gEfiGlobalVariableGuid,
> + &BootOrderSize
> + );
> + if (NULL == BootOrder) {
> + return EFI_NOT_FOUND;
> + }
> +
> + Index = 0;
> + while (Index < BootOrderSize / sizeof (UINT16)) {
> + UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x",
> BootOrder[Index]);
> + BootOptionVar = BdsLibGetVariableAndSize (
> + BootOption,
> + &gEfiGlobalVariableGuid,
> + &BootOptionSize
> + );
> + if (NULL == BootOptionVar) {
> + FreePool (BootOrder);
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + if (!ValidateOption(BootOptionVar, BootOptionSize)) {
> + Corrupted = TRUE;
> + } else {
> + TempPtr = BootOptionVar;
> + TempPtr += sizeof (UINT32) + sizeof (UINT16);
> + Description = (CHAR16 *) TempPtr;
> + TempPtr += StrSize ((CHAR16 *) TempPtr);
> + OptionDevicePath = (EFI_DEVICE_PATH_PROTOCOL *) TempPtr;
> +
> + //
> + // Skip legacy boot option (BBS boot device)
> + //
> + if ((DevicePathType (OptionDevicePath) == BBS_DEVICE_PATH) &&
> + (DevicePathSubType (OptionDevicePath) == BBS_BBS_DP)) {
> + FreePool (BootOptionVar);
> + Index++;
> + continue;
> + }
> + }
> +
> + if (Corrupted || !BdsLibIsValidEFIBootOptDevicePathExt
> (OptionDevicePath, FALSE, Description)) {
> + //
> + // Delete this invalid boot option "Boot####"
> + //
> + Status = gRT->SetVariable (
> + BootOption,
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + 0,
> + NULL
> + );
> + //
> + // Deleting variable with current variable implementation shouldn't fail.
> + //
> + ASSERT_EFI_ERROR (Status);
> + //
> + // Mark this boot option in boot order as deleted
> + //
> + BootOrder[Index] = 0xffff;
> + Corrupted = FALSE;
> + }
> +
> + FreePool (BootOptionVar);
> + Index++;
> + }
> +
> + //
> + // Adjust boot order array
> + //
> + Index2 = 0;
> + for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) {
> + if (BootOrder[Index] != 0xffff) {
> + BootOrder[Index2] = BootOrder[Index];
> + Index2 ++;
> + }
> + }
> + Status = gRT->SetVariable (
> + L"BootOrder",
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + Index2 * sizeof (UINT16),
> + BootOrder
> + );
> + //
> + // Shrinking variable with current variable implementation shouldn't fail.
> + //
> + ASSERT_EFI_ERROR (Status);
> +
> + FreePool (BootOrder);
> +
> + return Status;
> +}
> +
> +
> +/**
> + For EFI boot option, BDS separate them as six types:
> + 1. Network - The boot option points to the SimpleNetworkProtocol device.
> + Bds will try to automatically create this type boot option when
> enumerate.
> + 2. Shell - The boot option points to internal flash shell.
> + Bds will try to automatically create this type boot option when
> enumerate.
> + 3. Removable BlockIo - The boot option only points to the removable
> media
> + device, like USB flash disk, DVD, Floppy etc.
> + These device should contain a *removable* blockIo
> + protocol in their device handle.
> + Bds will try to automatically create this type boot option
> + when enumerate.
> + 4. Fixed BlockIo - The boot option only points to a Fixed blockIo device,
> + like HardDisk.
> + These device should contain a *fixed* blockIo
> + protocol in their device handle.
> + BDS will skip fixed blockIo devices, and NOT
> + automatically create boot option for them. But BDS
> + will help to delete those fixed blockIo boot option,
> + whose description rule conflict with other auto-created
> + boot options.
> + 5. Non-BlockIo Simplefile - The boot option points to a device whose
> handle
> + has SimpleFileSystem Protocol, but has no blockio
> + protocol. These devices do not offer blockIo
> + protocol, but BDS still can get the
> + \EFI\BOOT\boot{machinename}.EFI by SimpleFileSystem
> + Protocol.
> + 6. File - The boot option points to a file. These boot options are usually
> + created by user manually or OS loader. BDS will not delete or modify
> + these boot options.
> +
> + This function will enumerate all possible boot device in the system, and
> + automatically create boot options for Network, Shell, Removable BlockIo,
> + and Non-BlockIo Simplefile devices.
> + It will only execute once of every boot.
> +
> + @param BdsBootOptionList The header of the link list which indexed all
> + current boot options
> +
> + @retval EFI_SUCCESS Finished all the boot device enumerate and
> create
> + the boot option base on that boot device
> +
> + @retval EFI_OUT_OF_RESOURCES Failed to enumerate the boot device
> and create the boot option list
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibEnumerateAllBootOption (
> + IN OUT LIST_ENTRY *BdsBootOptionList
> + )
> +{
> + EFI_STATUS Status;
> + UINT16 FloppyNumber;
> + UINT16 HarddriveNumber;
> + UINT16 CdromNumber;
> + UINT16 UsbNumber;
> + UINT16 MiscNumber;
> + UINT16 ScsiNumber;
> + UINT16 NonBlockNumber;
> + UINTN NumberBlockIoHandles;
> + EFI_HANDLE *BlockIoHandles;
> + EFI_BLOCK_IO_PROTOCOL *BlkIo;
> + BOOLEAN Removable[2];
> + UINTN RemovableIndex;
> + UINTN Index;
> + UINTN NumOfLoadFileHandles;
> + EFI_HANDLE *LoadFileHandles;
> + UINTN FvHandleCount;
> + EFI_HANDLE *FvHandleBuffer;
> + EFI_FV_FILETYPE Type;
> + UINTN Size;
> + EFI_FV_FILE_ATTRIBUTES Attributes;
> + UINT32 AuthenticationStatus;
> + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + UINTN DevicePathType;
> + CHAR16 Buffer[40];
> + EFI_HANDLE *FileSystemHandles;
> + UINTN NumberFileSystemHandles;
> + BOOLEAN NeedDelete;
> + EFI_IMAGE_DOS_HEADER DosHeader;
> + CHAR8 *PlatLang;
> + CHAR8 *LastLang;
> + EFI_IMAGE_OPTIONAL_HEADER_UNION HdrData;
> + EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
> + CHAR16 *MacStr;
> + CHAR16 *IPverStr;
> + EFI_HANDLE *NetworkHandles;
> + UINTN BufferSize;
> +
> + FloppyNumber = 0;
> + HarddriveNumber = 0;
> + CdromNumber = 0;
> + UsbNumber = 0;
> + MiscNumber = 0;
> + ScsiNumber = 0;
> + PlatLang = NULL;
> + LastLang = NULL;
> + ZeroMem (Buffer, sizeof (Buffer));
> +
> + //
> + // If the boot device enumerate happened, just get the boot
> + // device from the boot order variable
> + //
> + if (mEnumBootDevice) {
> + GetVariable2 (LAST_ENUM_LANGUAGE_VARIABLE_NAME,
> &gLastEnumLangGuid, (VOID**)&LastLang, NULL);
> + GetEfiGlobalVariable2 (L"PlatformLang", (VOID**)&PlatLang, NULL);
> + ASSERT (PlatLang != NULL);
> + if ((LastLang != NULL) && (AsciiStrCmp (LastLang, PlatLang) == 0)) {
> + Status = BdsLibBuildOptionFromVar (BdsBootOptionList, L"BootOrder");
> + FreePool (LastLang);
> + FreePool (PlatLang);
> + return Status;
> + } else {
> + Status = gRT->SetVariable (
> + LAST_ENUM_LANGUAGE_VARIABLE_NAME,
> + &gLastEnumLangGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + AsciiStrSize (PlatLang),
> + PlatLang
> + );
> + //
> + // Failure to set the variable only impacts the performance next time
> enumerating the boot options.
> + //
> +
> + if (LastLang != NULL) {
> + FreePool (LastLang);
> + }
> + FreePool (PlatLang);
> + }
> + }
> +
> + //
> + // Notes: this dirty code is to get the legacy boot option from the
> + // BBS table and create to variable as the EFI boot option, it should
> + // be removed after the CSM can provide legacy boot option directly
> + //
> + REFRESH_LEGACY_BOOT_OPTIONS;
> +
> + //
> + // Delete invalid boot option
> + //
> + BdsDeleteAllInvalidEfiBootOption ();
> +
> + //
> + // Parse removable media followed by fixed media.
> + // The Removable[] array is used by the for-loop below to create
> removable media boot options
> + // at first, and then to create fixed media boot options.
> + //
> + Removable[0] = FALSE;
> + Removable[1] = TRUE;
> +
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiBlockIoProtocolGuid,
> + NULL,
> + &NumberBlockIoHandles,
> + &BlockIoHandles
> + );
> +
> + for (RemovableIndex = 0; RemovableIndex < 2; RemovableIndex++) {
> + for (Index = 0; Index < NumberBlockIoHandles; Index++) {
> + Status = gBS->HandleProtocol (
> + BlockIoHandles[Index],
> + &gEfiBlockIoProtocolGuid,
> + (VOID **) &BlkIo
> + );
> + //
> + // skip the logical partition
> + //
> + if (EFI_ERROR (Status) || BlkIo->Media->LogicalPartition) {
> + continue;
> + }
> +
> + //
> + // firstly fixed block io then the removable block io
> + //
> + if (BlkIo->Media->RemovableMedia == Removable[RemovableIndex]) {
> + continue;
> + }
> + DevicePath = DevicePathFromHandle (BlockIoHandles[Index]);
> + DevicePathType = BdsGetBootTypeFromDevicePath (DevicePath);
> +
> + switch (DevicePathType) {
> + case BDS_EFI_ACPI_FLOPPY_BOOT:
> + if (FloppyNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_FLOPPY)), FloppyNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_FLOPPY)));
> + }
> + BdsLibBuildOptionFromHandle (BlockIoHandles[Index],
> BdsBootOptionList, Buffer);
> + FloppyNumber++;
> + break;
> +
> + //
> + // Assume a removable SATA device should be the DVD/CD device, a
> fixed SATA device should be the Hard Drive device.
> + //
> + case BDS_EFI_MESSAGE_ATAPI_BOOT:
> + case BDS_EFI_MESSAGE_SATA_BOOT:
> + if (BlkIo->Media->RemovableMedia) {
> + if (CdromNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_CD_DVD)), CdromNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_CD_DVD)));
> + }
> + CdromNumber++;
> + } else {
> + if (HarddriveNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_HARDDRIVE)), HarddriveNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_HARDDRIVE)));
> + }
> + HarddriveNumber++;
> + }
> + DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Buffer: %S\n", Buffer));
> + BdsLibBuildOptionFromHandle (BlockIoHandles[Index],
> BdsBootOptionList, Buffer);
> + break;
> +
> + case BDS_EFI_MESSAGE_USB_DEVICE_BOOT:
> + if (UsbNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_USB)), UsbNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_USB)));
> + }
> + BdsLibBuildOptionFromHandle (BlockIoHandles[Index],
> BdsBootOptionList, Buffer);
> + UsbNumber++;
> + break;
> +
> + case BDS_EFI_MESSAGE_SCSI_BOOT:
> + if (ScsiNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_SCSI)), ScsiNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_SCSI)));
> + }
> + BdsLibBuildOptionFromHandle (BlockIoHandles[Index],
> BdsBootOptionList, Buffer);
> + ScsiNumber++;
> + break;
> +
> + case BDS_EFI_MESSAGE_MISC_BOOT:
> + default:
> + if (MiscNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_MISC)), MiscNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_MISC)));
> + }
> + BdsLibBuildOptionFromHandle (BlockIoHandles[Index],
> BdsBootOptionList, Buffer);
> + MiscNumber++;
> + break;
> + }
> + }
> + }
> +
> + if (NumberBlockIoHandles != 0) {
> + FreePool (BlockIoHandles);
> + }
> +
> + //
> + // If there is simple file protocol which does not consume block Io protocol,
> create a boot option for it here.
> + //
> + NonBlockNumber = 0;
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiSimpleFileSystemProtocolGuid,
> + NULL,
> + &NumberFileSystemHandles,
> + &FileSystemHandles
> + );
> + for (Index = 0; Index < NumberFileSystemHandles; Index++) {
> + Status = gBS->HandleProtocol (
> + FileSystemHandles[Index],
> + &gEfiBlockIoProtocolGuid,
> + (VOID **) &BlkIo
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Skip if the file system handle supports a BlkIo protocol,
> + //
> + continue;
> + }
> +
> + //
> + // Do the removable Media thing. \EFI\BOOT\boot{machinename}.EFI
> + // machinename is ia32, ia64, x64, ...
> + //
> + Hdr.Union = &HdrData;
> + NeedDelete = TRUE;
> + Status = BdsLibGetImageHeader (
> + FileSystemHandles[Index],
> + EFI_REMOVABLE_MEDIA_FILE_NAME,
> + &DosHeader,
> + Hdr
> + );
> + if (!EFI_ERROR (Status) &&
> + EFI_IMAGE_MACHINE_TYPE_SUPPORTED (Hdr.Pe32-
> >FileHeader.Machine) &&
> + Hdr.Pe32->OptionalHeader.Subsystem ==
> EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION) {
> + NeedDelete = FALSE;
> + }
> +
> + if (NeedDelete) {
> + //
> + // No such file or the file is not a EFI application, delete this boot option
> + //
> + BdsLibDeleteOptionFromHandle (FileSystemHandles[Index]);
> + } else {
> + if (NonBlockNumber != 0) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_NON_BLOCK)), NonBlockNumber);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_NON_BLOCK)));
> + }
> + BdsLibBuildOptionFromHandle (FileSystemHandles[Index],
> BdsBootOptionList, Buffer);
> + NonBlockNumber++;
> + }
> + }
> +
> + if (NumberFileSystemHandles != 0) {
> + FreePool (FileSystemHandles);
> + }
> +
> + //
> + // Parse Network Boot Device
> + //
> + NumOfLoadFileHandles = 0;
> + //
> + // Search Load File protocol for PXE boot option.
> + //
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiLoadFileProtocolGuid,
> + NULL,
> + &NumOfLoadFileHandles,
> + &LoadFileHandles
> + );
> +
> + for (Index = 0; Index < NumOfLoadFileHandles; Index++) {
> +
> +//
> +//Locate EFI_DEVICE_PATH_PROTOCOL to dynamically get IPv4/IPv6
> protocol information.
> +//
> +
> + Status = gBS->HandleProtocol (
> + LoadFileHandles[Index],
> + &gEfiDevicePathProtocolGuid,
> + (VOID **) &DevicePath
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> +
> + while (!IsDevicePathEnd (DevicePath)) {
> + if ((DevicePath->Type == MESSAGING_DEVICE_PATH) &&
> + (DevicePath->SubType == MSG_IPv4_DP)) {
> +
> + //
> + //Get handle infomation
> + //
> + BufferSize = 0;
> + NetworkHandles = NULL;
> + Status = gBS->LocateHandle (
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + NetworkHandles
> + );
> +
> + if (Status == EFI_BUFFER_TOO_SMALL) {
> + NetworkHandles = AllocateZeroPool(BufferSize);
> + if (NetworkHandles == NULL) {
> + return (EFI_OUT_OF_RESOURCES);
> + }
> + Status = gBS->LocateHandle(
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + NetworkHandles
> + );
> + }
> +
> + //
> + //Get the MAC string
> + //
> + Status = NetLibGetMacString (
> + *NetworkHandles,
> + NULL,
> + &MacStr
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + IPverStr = L" IPv4";
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s%s%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_NETWORK)),MacStr,IPverStr);
> + break;
> + }
> + if((DevicePath->Type == MESSAGING_DEVICE_PATH) &&
> + (DevicePath->SubType == MSG_IPv6_DP)) {
> +
> + //
> + //Get handle infomation
> + //
> + BufferSize = 0;
> + NetworkHandles = NULL;
> + Status = gBS->LocateHandle (
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + NetworkHandles
> + );
> +
> + if (Status == EFI_BUFFER_TOO_SMALL) {
> + NetworkHandles = AllocateZeroPool(BufferSize);
> + if (NetworkHandles == NULL) {
> + return (EFI_OUT_OF_RESOURCES);
> + }
> + Status = gBS->LocateHandle(
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + NetworkHandles
> + );
> + }
> +
> + //
> + //Get the MAC string
> + //
> + Status = NetLibGetMacString (
> + *NetworkHandles,
> + NULL,
> + &MacStr
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + IPverStr = L" IPv6";
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s%s%s", BdsLibGetStringById
> (STRING_TOKEN (STR_DESCRIPTION_NETWORK)),MacStr,IPverStr);
> + break;
> + }
> + DevicePath = NextDevicePathNode (DevicePath);
> + }
> +
> + BdsLibBuildOptionFromHandle (LoadFileHandles[Index],
> BdsBootOptionList, Buffer);
> + }
> +
> + if (NumOfLoadFileHandles != 0) {
> + FreePool (LoadFileHandles);
> + }
> +
> + //
> + // Check if we have on flash shell
> + //
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiFirmwareVolume2ProtocolGuid,
> + NULL,
> + &FvHandleCount,
> + &FvHandleBuffer
> + );
> + for (Index = 0; Index < FvHandleCount; Index++) {
> + gBS->HandleProtocol (
> + FvHandleBuffer[Index],
> + &gEfiFirmwareVolume2ProtocolGuid,
> + (VOID **) &Fv
> + );
> +
> + Status = Fv->ReadFile (
> + Fv,
> + &gUefiShellFileGuid,
> + NULL,
> + &Size,
> + &Type,
> + &Attributes,
> + &AuthenticationStatus
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + // Skip if no shell file in the FV
> + //
> + continue;
> + }
> + //
> + // Build the shell boot option
> + //
> + BdsLibBuildOptionFromShell (FvHandleBuffer[Index], BdsBootOptionList);
> + }
> +
> + if (FvHandleCount != 0) {
> + FreePool (FvHandleBuffer);
> + }
> + //
> + // Make sure every boot only have one time
> + // boot device enumerate
> + //
> + Status = BdsLibBuildOptionFromVar (BdsBootOptionList, L"BootOrder");
> + mEnumBootDevice = TRUE;
> +
> + return Status;
> +}
> +
> +/**
> + Build the boot option with the handle parsed in
> +
> + @param Handle The handle which present the device path to
> create
> + boot option
> + @param BdsBootOptionList The header of the link list which indexed all
> + current boot options
> + @param String The description of the boot option.
> +
> +**/
> +VOID
> +EFIAPI
> +BdsLibBuildOptionFromHandle (
> + IN EFI_HANDLE Handle,
> + IN LIST_ENTRY *BdsBootOptionList,
> + IN CHAR16 *String
> + )
> +{
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> +
> + DevicePath = DevicePathFromHandle (Handle);
> +
> + //
> + // Create and register new boot option
> + //
> + BdsLibRegisterNewOption (BdsBootOptionList, DevicePath, String,
> L"BootOrder");
> +}
> +
> +
> +/**
> + Build the on flash shell boot option with the handle parsed in.
> +
> + @param Handle The handle which present the device path to
> create
> + on flash shell boot option
> + @param BdsBootOptionList The header of the link list which indexed all
> + current boot options
> +
> +**/
> +VOID
> +EFIAPI
> +BdsLibBuildOptionFromShell (
> + IN EFI_HANDLE Handle,
> + IN OUT LIST_ENTRY *BdsBootOptionList
> + )
> +{
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH ShellNode;
> +
> + DevicePath = DevicePathFromHandle (Handle);
> +
> + //
> + // Build the shell device path
> + //
> + EfiInitializeFwVolDevicepathNode (&ShellNode, &gUefiShellFileGuid);
> +
> + DevicePath = AppendDevicePathNode (DevicePath,
> (EFI_DEVICE_PATH_PROTOCOL *) &ShellNode);
> +
> + //
> + // Create and register the shell boot option
> + //
> + BdsLibRegisterNewOption (BdsBootOptionList, DevicePath, L"EFI Internal
> Shell", L"BootOrder");
> +
> +}
> +
> +/**
> + Boot from the UEFI spec defined "BootNext" variable.
> +
> +**/
> +VOID
> +EFIAPI
> +BdsLibBootNext (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + UINT16 *BootNext;
> + UINTN BootNextSize;
> + CHAR16 Buffer[20];
> + BDS_COMMON_OPTION *BootOption;
> + LIST_ENTRY TempList;
> + UINTN ExitDataSize;
> + CHAR16 *ExitData;
> +
> + //
> + // Init the boot option name buffer and temp link list
> + //
> + InitializeListHead (&TempList);
> + ZeroMem (Buffer, sizeof (Buffer));
> +
> + BootNext = BdsLibGetVariableAndSize (
> + L"BootNext",
> + &gEfiGlobalVariableGuid,
> + &BootNextSize
> + );
> +
> + //
> + // Clear the boot next variable first
> + //
> + if (BootNext != NULL) {
> + Status = gRT->SetVariable (
> + L"BootNext",
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + 0,
> + NULL
> + );
> + //
> + // Deleting variable with current variable implementation shouldn't fail.
> + //
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Start to build the boot option and try to boot
> + //
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"Boot%04x", *BootNext);
> + BootOption = BdsLibVariableToOption (&TempList, Buffer);
> + ASSERT (BootOption != NULL);
> + BdsLibConnectDevicePath (BootOption->DevicePath);
> + BdsLibBootViaBootOption (BootOption, BootOption->DevicePath,
> &ExitDataSize, &ExitData);
> + FreePool(BootOption);
> + FreePool(BootNext);
> + }
> +
> +}
> +
> +/**
> + Return the bootable media handle.
> + First, check the device is connected
> + Second, check whether the device path point to a device which support
> SimpleFileSystemProtocol,
> + Third, detect the the default boot file in the Media, and return the
> removable Media handle.
> +
> + @param DevicePath Device Path to a bootable device
> +
> + @return The bootable media handle. If the media on the DevicePath is
> not bootable, NULL will return.
> +
> +**/
> +EFI_HANDLE
> +EFIAPI
> +BdsLibGetBootableHandle (
> + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
> + )
> +{
> + EFI_STATUS Status;
> + EFI_TPL OldTpl;
> + EFI_DEVICE_PATH_PROTOCOL *UpdatedDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *DupDevicePath;
> + EFI_HANDLE Handle;
> + EFI_BLOCK_IO_PROTOCOL *BlockIo;
> + VOID *Buffer;
> + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
> + UINTN Size;
> + UINTN TempSize;
> + EFI_HANDLE ReturnHandle;
> + EFI_HANDLE *SimpleFileSystemHandles;
> +
> + UINTN NumberSimpleFileSystemHandles;
> + UINTN Index;
> + EFI_IMAGE_DOS_HEADER DosHeader;
> + EFI_IMAGE_OPTIONAL_HEADER_UNION HdrData;
> + EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
> +
> + UpdatedDevicePath = DevicePath;
> +
> + //
> + // Enter to critical section to protect the acquired BlockIo instance
> + // from getting released due to the USB mass storage hotplug event
> + //
> + OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
> +
> + //
> + // Check whether the device is connected
> + //
> + Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid,
> &UpdatedDevicePath, &Handle);
> + if (EFI_ERROR (Status)) {
> + //
> + // Skip the case that the boot option point to a simple file protocol which
> does not consume block Io protocol,
> + //
> + Status = gBS->LocateDevicePath (&gEfiSimpleFileSystemProtocolGuid,
> &UpdatedDevicePath, &Handle);
> + if (EFI_ERROR (Status)) {
> + //
> + // Fail to find the proper BlockIo and simple file protocol, maybe because
> device not present, we need to connect it firstly
> + //
> + UpdatedDevicePath = DevicePath;
> + Status = gBS->LocateDevicePath (&gEfiDevicePathProtocolGuid,
> &UpdatedDevicePath, &Handle);
> + gBS->ConnectController (Handle, NULL, NULL, TRUE);
> + }
> + } else {
> + //
> + // For removable device boot option, its contained device path only point
> to the removable device handle,
> + // should make sure all its children handles (its child partion or media
> handles) are created and connected.
> + //
> + gBS->ConnectController (Handle, NULL, NULL, TRUE);
> + //
> + // Get BlockIo protocol and check removable attribute
> + //
> + Status = gBS->HandleProtocol (Handle, &gEfiBlockIoProtocolGuid, (VOID
> **)&BlockIo);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Issue a dummy read to the device to check for media change.
> + // When the removable media is changed, any Block IO read/write will
> + // cause the BlockIo protocol be reinstalled and EFI_MEDIA_CHANGED is
> + // returned. After the Block IO protocol is reinstalled, subsequent
> + // Block IO read/write will success.
> + //
> + Buffer = AllocatePool (BlockIo->Media->BlockSize);
> + if (Buffer != NULL) {
> + BlockIo->ReadBlocks (
> + BlockIo,
> + BlockIo->Media->MediaId,
> + 0,
> + BlockIo->Media->BlockSize,
> + Buffer
> + );
> + FreePool(Buffer);
> + }
> + }
> +
> + //
> + // Detect the the default boot file from removable Media
> + //
> +
> + //
> + // If fail to get bootable handle specified by a USB boot option, the BDS
> should try to find other bootable device in the same USB bus
> + // Try to locate the USB node device path first, if fail then use its previous
> PCI node to search
> + //
> + DupDevicePath = DuplicateDevicePath (DevicePath);
> + ASSERT (DupDevicePath != NULL);
> +
> + UpdatedDevicePath = DupDevicePath;
> + Status = gBS->LocateDevicePath (&gEfiDevicePathProtocolGuid,
> &UpdatedDevicePath, &Handle);
> + //
> + // if the resulting device path point to a usb node, and the usb node is a
> dummy node, should only let device path only point to the previous Pci node
> + // Acpi()/Pci()/Usb() --> Acpi()/Pci()
> + //
> + if ((DevicePathType (UpdatedDevicePath) == MESSAGING_DEVICE_PATH)
> &&
> + (DevicePathSubType (UpdatedDevicePath) == MSG_USB_DP)) {
> + //
> + // Remove the usb node, let the device path only point to PCI node
> + //
> + SetDevicePathEndNode (UpdatedDevicePath);
> + UpdatedDevicePath = DupDevicePath;
> + } else {
> + UpdatedDevicePath = DevicePath;
> + }
> +
> + //
> + // Get the device path size of boot option
> + //
> + Size = GetDevicePathSize(UpdatedDevicePath) - sizeof
> (EFI_DEVICE_PATH_PROTOCOL); // minus the end node
> + ReturnHandle = NULL;
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiSimpleFileSystemProtocolGuid,
> + NULL,
> + &NumberSimpleFileSystemHandles,
> + &SimpleFileSystemHandles
> + );
> + for (Index = 0; Index < NumberSimpleFileSystemHandles; Index++) {
> + //
> + // Get the device path size of SimpleFileSystem handle
> + //
> + TempDevicePath = DevicePathFromHandle
> (SimpleFileSystemHandles[Index]);
> + TempSize = GetDevicePathSize (TempDevicePath)- sizeof
> (EFI_DEVICE_PATH_PROTOCOL); // minus the end node
> + //
> + // Check whether the device path of boot option is part of the
> SimpleFileSystem handle's device path
> + //
> + if (Size <= TempSize && CompareMem (TempDevicePath,
> UpdatedDevicePath, Size)==0) {
> + //
> + // Load the default boot file \EFI\BOOT\boot{machinename}.EFI from
> removable Media
> + // machinename is ia32, ia64, x64, ...
> + //
> + Hdr.Union = &HdrData;
> + Status = BdsLibGetImageHeader (
> + SimpleFileSystemHandles[Index],
> + EFI_REMOVABLE_MEDIA_FILE_NAME,
> + &DosHeader,
> + Hdr
> + );
> + if (!EFI_ERROR (Status) &&
> + EFI_IMAGE_MACHINE_TYPE_SUPPORTED (Hdr.Pe32-
> >FileHeader.Machine) &&
> + Hdr.Pe32->OptionalHeader.Subsystem ==
> EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION) {
> + ReturnHandle = SimpleFileSystemHandles[Index];
> + break;
> + }
> + }
> + }
> +
> + FreePool(DupDevicePath);
> +
> + if (SimpleFileSystemHandles != NULL) {
> + FreePool(SimpleFileSystemHandles);
> + }
> +
> + gBS->RestoreTPL (OldTpl);
> +
> + return ReturnHandle;
> +}
> +
> +/**
> + Check to see if the network cable is plugged in. If the DevicePath is not
> + connected it will be connected.
> +
> + @param DevicePath Device Path to check
> +
> + @retval TRUE DevicePath points to an Network that is connected
> + @retval FALSE DevicePath does not point to a bootable network
> +
> +**/
> +BOOLEAN
> +BdsLibNetworkBootWithMediaPresent (
> + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
> + )
> +{
> + EFI_STATUS Status;
> + EFI_DEVICE_PATH_PROTOCOL *UpdatedDevicePath;
> + EFI_HANDLE Handle;
> + EFI_SIMPLE_NETWORK_PROTOCOL *Snp;
> + BOOLEAN MediaPresent;
> + UINT32 InterruptStatus;
> +
> + MediaPresent = FALSE;
> +
> + UpdatedDevicePath = DevicePath;
> + //
> + // Locate Load File Protocol for PXE boot option first
> + //
> + Status = gBS->LocateDevicePath (&gEfiLoadFileProtocolGuid,
> &UpdatedDevicePath, &Handle);
> + if (EFI_ERROR (Status)) {
> + //
> + // Device not present so see if we need to connect it
> + //
> + Status = BdsLibConnectDevicePath (DevicePath);
> + if (!EFI_ERROR (Status)) {
> + //
> + // This one should work after we did the connect
> + //
> + Status = gBS->LocateDevicePath (&gEfiLoadFileProtocolGuid,
> &UpdatedDevicePath, &Handle);
> + }
> + }
> +
> + if (!EFI_ERROR (Status)) {
> + Status = gBS->HandleProtocol (Handle, &gEfiSimpleNetworkProtocolGuid,
> (VOID **)&Snp);
> + if (EFI_ERROR (Status)) {
> + //
> + // Failed to open SNP from this handle, try to get SNP from parent
> handle
> + //
> + UpdatedDevicePath = DevicePathFromHandle (Handle);
> + if (UpdatedDevicePath != NULL) {
> + Status = gBS->LocateDevicePath (&gEfiSimpleNetworkProtocolGuid,
> &UpdatedDevicePath, &Handle);
> + if (!EFI_ERROR (Status)) {
> + //
> + // SNP handle found, get SNP from it
> + //
> + Status = gBS->HandleProtocol (Handle,
> &gEfiSimpleNetworkProtocolGuid, (VOID **) &Snp);
> + }
> + }
> + }
> +
> + if (!EFI_ERROR (Status)) {
> + if (Snp->Mode->MediaPresentSupported) {
> + if (Snp->Mode->State == EfiSimpleNetworkInitialized) {
> + //
> + // Invoke Snp->GetStatus() to refresh the media status
> + //
> + Snp->GetStatus (Snp, &InterruptStatus, NULL);
> +
> + //
> + // In case some one else is using the SNP check to see if it's connected
> + //
> + MediaPresent = Snp->Mode->MediaPresent;
> + } else {
> + //
> + // No one is using SNP so we need to Start and Initialize so
> + // MediaPresent will be valid.
> + //
> + Status = Snp->Start (Snp);
> + if (!EFI_ERROR (Status)) {
> + Status = Snp->Initialize (Snp, 0, 0);
> + if (!EFI_ERROR (Status)) {
> + MediaPresent = Snp->Mode->MediaPresent;
> + Snp->Shutdown (Snp);
> + }
> + Snp->Stop (Snp);
> + }
> + }
> + } else {
> + MediaPresent = TRUE;
> + }
> + }
> + }
> +
> + return MediaPresent;
> +}
> +
> +/**
> + For a bootable Device path, return its boot type.
> +
> + @param DevicePath The bootable device Path to check
> +
> + @retval BDS_EFI_MEDIA_HD_BOOT If given device path contains
> MEDIA_DEVICE_PATH type device path node
> + which subtype is MEDIA_HARDDRIVE_DP
> + @retval BDS_EFI_MEDIA_CDROM_BOOT If given device path contains
> MEDIA_DEVICE_PATH type device path node
> + which subtype is MEDIA_CDROM_DP
> + @retval BDS_EFI_ACPI_FLOPPY_BOOT If given device path contains
> ACPI_DEVICE_PATH type device path node
> + which HID is floppy device.
> + @retval BDS_EFI_MESSAGE_ATAPI_BOOT If given device path contains
> MESSAGING_DEVICE_PATH type device path node
> + and its last device path node's subtype is
> MSG_ATAPI_DP.
> + @retval BDS_EFI_MESSAGE_SCSI_BOOT If given device path contains
> MESSAGING_DEVICE_PATH type device path node
> + and its last device path node's subtype is
> MSG_SCSI_DP.
> + @retval BDS_EFI_MESSAGE_USB_DEVICE_BOOT If given device path
> contains MESSAGING_DEVICE_PATH type device path node
> + and its last device path node's subtype is
> MSG_USB_DP.
> + @retval BDS_EFI_MESSAGE_MISC_BOOT If the device path not
> contains any media device path node, and
> + its last device path node point to a message device
> path node.
> + @retval BDS_LEGACY_BBS_BOOT If given device path contains
> BBS_DEVICE_PATH type device path node.
> + @retval BDS_EFI_UNSUPPORT An EFI Removable BlockIO device
> path not point to a media and message device,
> +
> +**/
> +UINT32
> +EFIAPI
> +BdsGetBootTypeFromDevicePath (
> + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
> + )
> +{
> + ACPI_HID_DEVICE_PATH *Acpi;
> + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *LastDeviceNode;
> + UINT32 BootType;
> +
> + if (NULL == DevicePath) {
> + return BDS_EFI_UNSUPPORT;
> + }
> +
> + TempDevicePath = DevicePath;
> +
> + while (!IsDevicePathEndType (TempDevicePath)) {
> + switch (DevicePathType (TempDevicePath)) {
> + case BBS_DEVICE_PATH:
> + return BDS_LEGACY_BBS_BOOT;
> + case MEDIA_DEVICE_PATH:
> + if (DevicePathSubType (TempDevicePath) == MEDIA_HARDDRIVE_DP) {
> + return BDS_EFI_MEDIA_HD_BOOT;
> + } else if (DevicePathSubType (TempDevicePath) == MEDIA_CDROM_DP)
> {
> + return BDS_EFI_MEDIA_CDROM_BOOT;
> + }
> + break;
> + case ACPI_DEVICE_PATH:
> + Acpi = (ACPI_HID_DEVICE_PATH *) TempDevicePath;
> + if (EISA_ID_TO_NUM (Acpi->HID) == 0x0604) {
> + return BDS_EFI_ACPI_FLOPPY_BOOT;
> + }
> + break;
> + case MESSAGING_DEVICE_PATH:
> + //
> + // Get the last device path node
> + //
> + LastDeviceNode = NextDevicePathNode (TempDevicePath);
> + if (DevicePathSubType(LastDeviceNode) ==
> MSG_DEVICE_LOGICAL_UNIT_DP) {
> + //
> + // if the next node type is Device Logical Unit, which specify the Logical
> Unit Number (LUN),
> + // skip it
> + //
> + LastDeviceNode = NextDevicePathNode (LastDeviceNode);
> + }
> + //
> + // if the device path not only point to driver device, it is not a messaging
> device path,
> + //
> + if (!IsDevicePathEndType (LastDeviceNode)) {
> + break;
> + }
> +
> + switch (DevicePathSubType (TempDevicePath)) {
> + case MSG_ATAPI_DP:
> + BootType = BDS_EFI_MESSAGE_ATAPI_BOOT;
> + break;
> +
> + case MSG_USB_DP:
> + BootType = BDS_EFI_MESSAGE_USB_DEVICE_BOOT;
> + break;
> +
> + case MSG_SCSI_DP:
> + BootType = BDS_EFI_MESSAGE_SCSI_BOOT;
> + break;
> +
> + case MSG_SATA_DP:
> + BootType = BDS_EFI_MESSAGE_SATA_BOOT;
> + break;
> +
> + case MSG_MAC_ADDR_DP:
> + case MSG_VLAN_DP:
> + case MSG_IPv4_DP:
> + case MSG_IPv6_DP:
> + BootType = BDS_EFI_MESSAGE_MAC_BOOT;
> + break;
> +
> + default:
> + BootType = BDS_EFI_MESSAGE_MISC_BOOT;
> + break;
> + }
> + return BootType;
> +
> + default:
> + break;
> + }
> + TempDevicePath = NextDevicePathNode (TempDevicePath);
> + }
> +
> + return BDS_EFI_UNSUPPORT;
> +}
> +
> +/**
> + Check whether the Device path in a boot option point to a valid bootable
> device,
> + And if CheckMedia is true, check the device is ready to boot now.
> +
> + @param DevPath the Device path in a boot option
> + @param CheckMedia if true, check the device is ready to boot now.
> +
> + @retval TRUE the Device path is valid
> + @retval FALSE the Device path is invalid .
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +BdsLibIsValidEFIBootOptDevicePath (
> + IN EFI_DEVICE_PATH_PROTOCOL *DevPath,
> + IN BOOLEAN CheckMedia
> + )
> +{
> + return BdsLibIsValidEFIBootOptDevicePathExt (DevPath, CheckMedia,
> NULL);
> +}
> +
> +/**
> + Check whether the Device path in a boot option point to a valid bootable
> device,
> + And if CheckMedia is true, check the device is ready to boot now.
> + If Description is not NULL and the device path point to a fixed BlockIo
> + device, check the description whether conflict with other auto-created
> + boot options.
> +
> + @param DevPath the Device path in a boot option
> + @param CheckMedia if true, check the device is ready to boot now.
> + @param Description the description in a boot option
> +
> + @retval TRUE the Device path is valid
> + @retval FALSE the Device path is invalid .
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +BdsLibIsValidEFIBootOptDevicePathExt (
> + IN EFI_DEVICE_PATH_PROTOCOL *DevPath,
> + IN BOOLEAN CheckMedia,
> + IN CHAR16 *Description
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE Handle;
> + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *LastDeviceNode;
> + EFI_BLOCK_IO_PROTOCOL *BlockIo;
> +
> + TempDevicePath = DevPath;
> + LastDeviceNode = DevPath;
> +
> + //
> + // Check if it's a valid boot option for network boot device.
> + // Check if there is EfiLoadFileProtocol installed.
> + // If yes, that means there is a boot option for network.
> + //
> + Status = gBS->LocateDevicePath (
> + &gEfiLoadFileProtocolGuid,
> + &TempDevicePath,
> + &Handle
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + // Device not present so see if we need to connect it
> + //
> + TempDevicePath = DevPath;
> + BdsLibConnectDevicePath (TempDevicePath);
> + Status = gBS->LocateDevicePath (
> + &gEfiLoadFileProtocolGuid,
> + &TempDevicePath,
> + &Handle
> + );
> + }
> +
> + if (!EFI_ERROR (Status)) {
> + if (!IsDevicePathEnd (TempDevicePath)) {
> + //
> + // LoadFile protocol is not installed on handle with exactly the same
> DevPath
> + //
> + return FALSE;
> + }
> +
> + if (CheckMedia) {
> + //
> + // Test if it is ready to boot now
> + //
> + if (BdsLibNetworkBootWithMediaPresent(DevPath)) {
> + return TRUE;
> + }
> + } else {
> + return TRUE;
> + }
> + }
> +
> + //
> + // If the boot option point to a file, it is a valid EFI boot option,
> + // and assume it is ready to boot now
> + //
> + while (!IsDevicePathEnd (TempDevicePath)) {
> + //
> + // If there is USB Class or USB WWID device path node, treat it as valid EFI
> + // Boot Option. BdsExpandUsbShortFormDevicePath () will be used to
> expand it
> + // to full device path.
> + //
> + if ((DevicePathType (TempDevicePath) == MESSAGING_DEVICE_PATH)
> &&
> + ((DevicePathSubType (TempDevicePath) == MSG_USB_CLASS_DP) ||
> + (DevicePathSubType (TempDevicePath) == MSG_USB_WWID_DP))) {
> + return TRUE;
> + }
> +
> + LastDeviceNode = TempDevicePath;
> + TempDevicePath = NextDevicePathNode (TempDevicePath);
> + }
> + if ((DevicePathType (LastDeviceNode) == MEDIA_DEVICE_PATH) &&
> + (DevicePathSubType (LastDeviceNode) == MEDIA_FILEPATH_DP)) {
> + return TRUE;
> + }
> +
> + //
> + // Check if it's a valid boot option for internal FV application
> + //
> + if (EfiGetNameGuidFromFwVolDevicePathNode
> ((MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) LastDeviceNode) != NULL) {
> + //
> + // If the boot option point to internal FV application, make sure it is valid
> + //
> + TempDevicePath = DevPath;
> + Status = BdsLibUpdateFvFileDevicePath (
> + &TempDevicePath,
> + EfiGetNameGuidFromFwVolDevicePathNode
> ((MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) LastDeviceNode)
> + );
> + if (Status == EFI_ALREADY_STARTED) {
> + return TRUE;
> + } else {
> + if (Status == EFI_SUCCESS) {
> + FreePool (TempDevicePath);
> + }
> + return FALSE;
> + }
> + }
> +
> + //
> + // If the boot option point to a blockIO device:
> + // if it is a removable blockIo device, it is valid.
> + // if it is a fixed blockIo device, check its description confliction.
> + //
> + TempDevicePath = DevPath;
> + Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid,
> &TempDevicePath, &Handle);
> + if (EFI_ERROR (Status)) {
> + //
> + // Device not present so see if we need to connect it
> + //
> + Status = BdsLibConnectDevicePath (DevPath);
> + if (!EFI_ERROR (Status)) {
> + //
> + // Try again to get the Block Io protocol after we did the connect
> + //
> + TempDevicePath = DevPath;
> + Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid,
> &TempDevicePath, &Handle);
> + }
> + }
> +
> + if (!EFI_ERROR (Status)) {
> + Status = gBS->HandleProtocol (Handle, &gEfiBlockIoProtocolGuid, (VOID
> **)&BlockIo);
> + if (!EFI_ERROR (Status)) {
> + if (CheckMedia) {
> + //
> + // Test if it is ready to boot now
> + //
> + if (BdsLibGetBootableHandle (DevPath) != NULL) {
> + return TRUE;
> + }
> + } else {
> + return TRUE;
> + }
> + }
> + } else {
> + //
> + // if the boot option point to a simple file protocol which does not
> consume block Io protocol, it is also a valid EFI boot option,
> + //
> + Status = gBS->LocateDevicePath (&gEfiSimpleFileSystemProtocolGuid,
> &TempDevicePath, &Handle);
> + if (!EFI_ERROR (Status)) {
> + if (CheckMedia) {
> + //
> + // Test if it is ready to boot now
> + //
> + if (BdsLibGetBootableHandle (DevPath) != NULL) {
> + return TRUE;
> + }
> + } else {
> + return TRUE;
> + }
> + }
> + }
> +
> + return FALSE;
> +}
> +
> +
> +/**
> + According to a file guild, check a Fv file device path is valid. If it is invalid,
> + try to return the valid device path.
> + FV address maybe changes for memory layout adjust from time to time,
> use this function
> + could promise the Fv file device path is right.
> +
> + @param DevicePath on input, the Fv file device path need to check
> on
> + output, the updated valid Fv file device path
> + @param FileGuid the Fv file guild
> +
> + @retval EFI_INVALID_PARAMETER the input DevicePath or FileGuid is
> invalid
> + parameter
> + @retval EFI_UNSUPPORTED the input DevicePath does not contain Fv
> file
> + guild at all
> + @retval EFI_ALREADY_STARTED the input DevicePath has pointed to Fv
> file, it is
> + valid
> + @retval EFI_SUCCESS has successfully updated the invalid DevicePath,
> + and return the updated device path in DevicePath
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibUpdateFvFileDevicePath (
> + IN OUT EFI_DEVICE_PATH_PROTOCOL ** DevicePath,
> + IN EFI_GUID *FileGuid
> + )
> +{
> + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *LastDeviceNode;
> + EFI_STATUS Status;
> + EFI_GUID *GuidPoint;
> + UINTN Index;
> + UINTN FvHandleCount;
> + EFI_HANDLE *FvHandleBuffer;
> + EFI_FV_FILETYPE Type;
> + UINTN Size;
> + EFI_FV_FILE_ATTRIBUTES Attributes;
> + UINT32 AuthenticationStatus;
> + BOOLEAN FindFvFile;
> + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
> + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
> + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FvFileNode;
> + EFI_HANDLE FoundFvHandle;
> + EFI_DEVICE_PATH_PROTOCOL *NewDevicePath;
> +
> + if ((DevicePath == NULL) || (*DevicePath == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> + if (FileGuid == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check whether the device path point to the default the input Fv file
> + //
> + TempDevicePath = *DevicePath;
> + LastDeviceNode = TempDevicePath;
> + while (!IsDevicePathEnd (TempDevicePath)) {
> + LastDeviceNode = TempDevicePath;
> + TempDevicePath = NextDevicePathNode (TempDevicePath);
> + }
> + GuidPoint = EfiGetNameGuidFromFwVolDevicePathNode (
> + (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) LastDeviceNode
> + );
> + if (GuidPoint == NULL) {
> + //
> + // if this option does not points to a Fv file, just return EFI_UNSUPPORTED
> + //
> + return EFI_UNSUPPORTED;
> + }
> + if (!CompareGuid (GuidPoint, FileGuid)) {
> + //
> + // If the Fv file is not the input file guid, just return EFI_UNSUPPORTED
> + //
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Check whether the input Fv file device path is valid
> + //
> + TempDevicePath = *DevicePath;
> + FoundFvHandle = NULL;
> + Status = gBS->LocateDevicePath (
> + &gEfiFirmwareVolume2ProtocolGuid,
> + &TempDevicePath,
> + &FoundFvHandle
> + );
> + if (!EFI_ERROR (Status)) {
> + Status = gBS->HandleProtocol (
> + FoundFvHandle,
> + &gEfiFirmwareVolume2ProtocolGuid,
> + (VOID **) &Fv
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Set FV ReadFile Buffer as NULL, only need to check whether input Fv
> file exist there
> + //
> + Status = Fv->ReadFile (
> + Fv,
> + FileGuid,
> + NULL,
> + &Size,
> + &Type,
> + &Attributes,
> + &AuthenticationStatus
> + );
> + if (!EFI_ERROR (Status)) {
> + return EFI_ALREADY_STARTED;
> + }
> + }
> + }
> +
> + //
> + // Look for the input wanted FV file in current FV
> + // First, try to look for in Bds own FV. Bds and input wanted FV file usually
> are in the same FV
> + //
> + FindFvFile = FALSE;
> + FoundFvHandle = NULL;
> + Status = gBS->HandleProtocol (
> + gImageHandle,
> + &gEfiLoadedImageProtocolGuid,
> + (VOID **) &LoadedImage
> + );
> + if (!EFI_ERROR (Status)) {
> + Status = gBS->HandleProtocol (
> + LoadedImage->DeviceHandle,
> + &gEfiFirmwareVolume2ProtocolGuid,
> + (VOID **) &Fv
> + );
> + if (!EFI_ERROR (Status)) {
> + Status = Fv->ReadFile (
> + Fv,
> + FileGuid,
> + NULL,
> + &Size,
> + &Type,
> + &Attributes,
> + &AuthenticationStatus
> + );
> + if (!EFI_ERROR (Status)) {
> + FindFvFile = TRUE;
> + FoundFvHandle = LoadedImage->DeviceHandle;
> + }
> + }
> + }
> + //
> + // Second, if fail to find, try to enumerate all FV
> + //
> + if (!FindFvFile) {
> + FvHandleBuffer = NULL;
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiFirmwareVolume2ProtocolGuid,
> + NULL,
> + &FvHandleCount,
> + &FvHandleBuffer
> + );
> + for (Index = 0; Index < FvHandleCount; Index++) {
> + gBS->HandleProtocol (
> + FvHandleBuffer[Index],
> + &gEfiFirmwareVolume2ProtocolGuid,
> + (VOID **) &Fv
> + );
> +
> + Status = Fv->ReadFile (
> + Fv,
> + FileGuid,
> + NULL,
> + &Size,
> + &Type,
> + &Attributes,
> + &AuthenticationStatus
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + // Skip if input Fv file not in the FV
> + //
> + continue;
> + }
> + FindFvFile = TRUE;
> + FoundFvHandle = FvHandleBuffer[Index];
> + break;
> + }
> +
> + if (FvHandleBuffer != NULL) {
> + FreePool (FvHandleBuffer);
> + }
> + }
> +
> + if (FindFvFile) {
> + //
> + // Build the shell device path
> + //
> + NewDevicePath = DevicePathFromHandle (FoundFvHandle);
> + EfiInitializeFwVolDevicepathNode (&FvFileNode, FileGuid);
> + NewDevicePath = AppendDevicePathNode (NewDevicePath,
> (EFI_DEVICE_PATH_PROTOCOL *) &FvFileNode);
> + ASSERT (NewDevicePath != NULL);
> + *DevicePath = NewDevicePath;
> + return EFI_SUCCESS;
> + }
> + return EFI_NOT_FOUND;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsConnect.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsConnect.c
> new file mode 100644
> index 0000000000..dfeefc01b8
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsConnect.c
> @@ -0,0 +1,429 @@
> +/** @file
> + BDS Lib functions which relate with connect the device
> +
> +Copyright (c) 2004 - 2013, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "InternalBdsLib.h"
> +
> +
> +/**
> + This function will connect all the system driver to controller
> + first, and then special connect the default console, this make
> + sure all the system controller available and the platform default
> + console connected.
> +
> +**/
> +VOID
> +EFIAPI
> +BdsLibConnectAll (
> + VOID
> + )
> +{
> + //
> + // Connect the platform console first
> + //
> + BdsLibConnectAllDefaultConsoles ();
> +
> + //
> + // Generic way to connect all the drivers
> + //
> + BdsLibConnectAllDriversToAllControllers ();
> +
> + //
> + // Here we have the assumption that we have already had
> + // platform default console
> + //
> + BdsLibConnectAllDefaultConsoles ();
> +}
> +
> +
> +/**
> + This function will connect all the system drivers to all controllers
> + first, and then connect all the console devices the system current
> + have. After this we should get all the device work and console available
> + if the system have console device.
> +
> +**/
> +VOID
> +BdsLibGenericConnectAll (
> + VOID
> + )
> +{
> + //
> + // Most generic way to connect all the drivers
> + //
> + BdsLibConnectAllDriversToAllControllers ();
> + BdsLibConnectAllConsoles ();
> +}
> +
> +/**
> + This function will create all handles associate with every device
> + path node. If the handle associate with one device path node can not
> + be created successfully, then still give chance to do the dispatch,
> + which load the missing drivers if possible.
> +
> + @param DevicePathToConnect The device path which will be connected,
> it can be
> + a multi-instance device path
> +
> + @retval EFI_SUCCESS All handles associate with every device path
> node
> + have been created
> + @retval EFI_OUT_OF_RESOURCES There is no resource to create new
> handles
> + @retval EFI_NOT_FOUND Create the handle associate with one device
> path
> + node failed
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibConnectDevicePath (
> + IN EFI_DEVICE_PATH_PROTOCOL *DevicePathToConnect
> + )
> +{
> + EFI_STATUS Status;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *CopyOfDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *Instance;
> + EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *Next;
> + EFI_HANDLE Handle;
> + EFI_HANDLE PreviousHandle;
> + UINTN Size;
> + EFI_TPL CurrentTpl;
> +
> + if (DevicePathToConnect == NULL) {
> + return EFI_SUCCESS;
> + }
> +
> + CurrentTpl = EfiGetCurrentTpl ();
> +
> + DevicePath = DuplicateDevicePath (DevicePathToConnect);
> + if (DevicePath == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + CopyOfDevicePath = DevicePath;
> +
> + do {
> + //
> + // The outer loop handles multi instance device paths.
> + // Only console variables contain multiple instance device paths.
> + //
> + // After this call DevicePath points to the next Instance
> + //
> + Instance = GetNextDevicePathInstance (&DevicePath, &Size);
> + if (Instance == NULL) {
> + FreePool (CopyOfDevicePath);
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + Next = Instance;
> + while (!IsDevicePathEndType (Next)) {
> + Next = NextDevicePathNode (Next);
> + }
> +
> + SetDevicePathEndNode (Next);
> +
> + //
> + // Start the real work of connect with RemainingDevicePath
> + //
> + PreviousHandle = NULL;
> + do {
> + //
> + // Find the handle that best matches the Device Path. If it is only a
> + // partial match the remaining part of the device path is returned in
> + // RemainingDevicePath.
> + //
> + RemainingDevicePath = Instance;
> + Status = gBS->LocateDevicePath (&gEfiDevicePathProtocolGuid,
> &RemainingDevicePath, &Handle);
> +
> + if (!EFI_ERROR (Status)) {
> + if (Handle == PreviousHandle) {
> + //
> + // If no forward progress is made try invoking the Dispatcher.
> + // A new FV may have been added to the system an new drivers
> + // may now be found.
> + // Status == EFI_SUCCESS means a driver was dispatched
> + // Status == EFI_NOT_FOUND means no new drivers were dispatched
> + //
> + if (CurrentTpl == TPL_APPLICATION) {
> + //
> + // Dispatch calls LoadImage/StartImage which cannot run at TPL >
> TPL_APPLICATION
> + //
> + Status = gDS->Dispatch ();
> + } else {
> + //
> + // Always return EFI_NOT_FOUND here
> + // to prevent dead loop when control handle is found but connection
> failded case
> + //
> + Status = EFI_NOT_FOUND;
> + }
> + }
> +
> + if (!EFI_ERROR (Status)) {
> + PreviousHandle = Handle;
> + //
> + // Connect all drivers that apply to Handle and RemainingDevicePath,
> + // the Recursive flag is FALSE so only one level will be expanded.
> + //
> + // Do not check the connect status here, if the connect controller fail,
> + // then still give the chance to do dispatch, because partial
> + // RemainingDevicepath may be in the new FV
> + //
> + // 1. If the connect fail, RemainingDevicepath and handle will not
> + // change, so next time will do the dispatch, then dispatch's status
> + // will take effect
> + // 2. If the connect success, the RemainingDevicepath and handle will
> + // change, then avoid the dispatch, we have chance to continue the
> + // next connection
> + //
> + gBS->ConnectController (Handle, NULL, RemainingDevicePath, FALSE);
> + }
> + }
> + //
> + // Loop until RemainingDevicePath is an empty device path
> + //
> + } while (!EFI_ERROR (Status) && !IsDevicePathEnd
> (RemainingDevicePath));
> +
> + } while (DevicePath != NULL);
> +
> + if (CopyOfDevicePath != NULL) {
> + FreePool (CopyOfDevicePath);
> + }
> + //
> + // All handle with DevicePath exists in the handle database
> + //
> + return Status;
> +}
> +
> +/**
> + This function will connect all current system handles recursively.
> +
> + gBS->ConnectController() service is invoked for each handle exist in
> system handler buffer.
> + If the handle is bus type handler, all childrens also will be connected
> recursively
> + by gBS->ConnectController().
> +
> + @retval EFI_SUCCESS All handles and it's child handle have been
> connected
> + @retval EFI_STATUS Error status returned by of gBS-
> >LocateHandleBuffer().
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibConnectAllEfi (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + UINTN HandleCount;
> + EFI_HANDLE *HandleBuffer;
> + UINTN Index;
> +
> + Status = gBS->LocateHandleBuffer (
> + AllHandles,
> + NULL,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + for (Index = 0; Index < HandleCount; Index++) {
> + Status = gBS->ConnectController (HandleBuffer[Index], NULL, NULL,
> TRUE);
> + }
> +
> + if (HandleBuffer != NULL) {
> + FreePool (HandleBuffer);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function will disconnect all current system handles.
> +
> + gBS->DisconnectController() is invoked for each handle exists in system
> handle buffer.
> + If handle is a bus type handle, all childrens also are disconnected
> recursively by
> + gBS->DisconnectController().
> +
> + @retval EFI_SUCCESS All handles have been disconnected
> + @retval EFI_STATUS Error status returned by of gBS-
> >LocateHandleBuffer().
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibDisconnectAllEfi (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + UINTN HandleCount;
> + EFI_HANDLE *HandleBuffer;
> + UINTN Index;
> +
> + //
> + // Disconnect all
> + //
> + Status = gBS->LocateHandleBuffer (
> + AllHandles,
> + NULL,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + for (Index = 0; Index < HandleCount; Index++) {
> + Status = gBS->DisconnectController (HandleBuffer[Index], NULL, NULL);
> + }
> +
> + if (HandleBuffer != NULL) {
> + FreePool (HandleBuffer);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Connects all drivers to all controllers.
> + This function make sure all the current system driver will manage
> + the correspoinding controllers if have. And at the same time, make
> + sure all the system controllers have driver to manage it if have.
> +
> +**/
> +VOID
> +EFIAPI
> +BdsLibConnectAllDriversToAllControllers (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> +
> + do {
> + //
> + // Connect All EFI 1.10 drivers following EFI 1.10 algorithm
> + //
> + BdsLibConnectAllEfi ();
> +
> + //
> + // Check to see if it's possible to dispatch an more DXE drivers.
> + // The BdsLibConnectAllEfi () may have made new DXE drivers show up.
> + // If anything is Dispatched Status == EFI_SUCCESS and we will try
> + // the connect again.
> + //
> + Status = gDS->Dispatch ();
> +
> + } while (!EFI_ERROR (Status));
> +
> +}
> +
> +
> +/**
> + Connect the specific Usb device which match the short form device path,
> + and whose bus is determined by Host Controller (Uhci or Ehci).
> +
> + @param HostControllerPI Uhci (0x00) or Ehci (0x20) or Both uhci and
> ehci
> + (0xFF)
> + @param RemainingDevicePath a short-form device path that starts with
> the first
> + element being a USB WWID or a USB Class device
> + path
> +
> + @return EFI_INVALID_PARAMETER RemainingDevicePath is NULL pointer.
> + RemainingDevicePath is not a USB device path.
> + Invalid HostControllerPI type.
> + @return EFI_SUCCESS Success to connect USB device
> + @return EFI_NOT_FOUND Fail to find handle for USB controller to
> connect.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibConnectUsbDevByShortFormDP(
> + IN UINT8 HostControllerPI,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE *HandleArray;
> + UINTN HandleArrayCount;
> + UINTN Index;
> + EFI_PCI_IO_PROTOCOL *PciIo;
> + UINT8 Class[3];
> + BOOLEAN AtLeastOneConnected;
> +
> + //
> + // Check the passed in parameters
> + //
> + if (RemainingDevicePath == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if ((DevicePathType (RemainingDevicePath) != MESSAGING_DEVICE_PATH)
> ||
> + ((DevicePathSubType (RemainingDevicePath) != MSG_USB_CLASS_DP)
> + && (DevicePathSubType (RemainingDevicePath) !=
> MSG_USB_WWID_DP)
> + )) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if (HostControllerPI != 0xFF &&
> + HostControllerPI != 0x00 &&
> + HostControllerPI != 0x20) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Find the usb host controller firstly, then connect with the remaining
> device path
> + //
> + AtLeastOneConnected = FALSE;
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiPciIoProtocolGuid,
> + NULL,
> + &HandleArrayCount,
> + &HandleArray
> + );
> + if (!EFI_ERROR (Status)) {
> + for (Index = 0; Index < HandleArrayCount; Index++) {
> + Status = gBS->HandleProtocol (
> + HandleArray[Index],
> + &gEfiPciIoProtocolGuid,
> + (VOID **)&PciIo
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Check whether the Pci device is the wanted usb host controller
> + //
> + Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x09, 3, &Class);
> + if (!EFI_ERROR (Status)) {
> + if ((PCI_CLASS_SERIAL == Class[2]) &&
> + (PCI_CLASS_SERIAL_USB == Class[1])) {
> + if (HostControllerPI == Class[0] || HostControllerPI == 0xFF) {
> + Status = gBS->ConnectController (
> + HandleArray[Index],
> + NULL,
> + RemainingDevicePath,
> + FALSE
> + );
> + if (!EFI_ERROR(Status)) {
> + AtLeastOneConnected = TRUE;
> + }
> + }
> + }
> + }
> + }
> + }
> +
> + if (HandleArray != NULL) {
> + FreePool (HandleArray);
> + }
> +
> + if (AtLeastOneConnected) {
> + return EFI_SUCCESS;
> + }
> + }
> +
> + return EFI_NOT_FOUND;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsConsole.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsConsole.c
> new file mode 100644
> index 0000000000..2fffd9e4bc
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsConsole.c
> @@ -0,0 +1,1061 @@
> +/** @file
> + BDS Lib functions which contain all the code to connect console device
> +
> +Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "InternalBdsLib.h"
> +
> +
> +/**
> + Check if we need to save the EFI variable with "ConVarName" as name
> + as NV type
> + If ConVarName is NULL, then ASSERT().
> +
> + @param ConVarName The name of the EFI variable.
> +
> + @retval TRUE Set the EFI variable as NV type.
> + @retval FALSE EFI variable as NV type can be set NonNV.
> +**/
> +BOOLEAN
> +IsNvNeed (
> + IN CHAR16 *ConVarName
> + )
> +{
> + CHAR16 *Ptr;
> +
> + ASSERT (ConVarName != NULL);
> +
> + Ptr = ConVarName;
> +
> + //
> + // If the variable includes "Dev" at last, we consider
> + // it does not support NV attribute.
> + //
> + while (*Ptr != L'\0') {
> + Ptr++;
> + }
> +
> + if (((INTN)((UINTN)Ptr - (UINTN)ConVarName) / sizeof (CHAR16)) <= 3) {
> + return TRUE;
> + }
> +
> + if ((*(Ptr - 3) == 'D') && (*(Ptr - 2) == 'e') && (*(Ptr - 1) == 'v')) {
> + return FALSE;
> + } else {
> + return TRUE;
> + }
> +}
> +
> +/**
> + Fill console handle in System Table if there are no valid console handle in.
> +
> + Firstly, check the validation of console handle in System Table. If it is invalid,
> + update it by the first console device handle from EFI console variable.
> +
> + @param VarName The name of the EFI console variable.
> + @param ConsoleGuid Specified Console protocol GUID.
> + @param ConsoleHandle On IN, console handle in System Table to be
> checked.
> + On OUT, new console handle in system table.
> + @param ProtocolInterface On IN, console protocol on console handle in
> System Table to be checked.
> + On OUT, new console protocol on new console handle in
> system table.
> +
> + @retval TRUE System Table has been updated.
> + @retval FALSE System Table hasn't been updated.
> +
> +**/
> +BOOLEAN
> +UpdateSystemTableConsole (
> + IN CHAR16 *VarName,
> + IN EFI_GUID *ConsoleGuid,
> + IN OUT EFI_HANDLE *ConsoleHandle,
> + IN OUT VOID **ProtocolInterface
> + )
> +{
> + EFI_STATUS Status;
> + UINTN DevicePathSize;
> + EFI_DEVICE_PATH_PROTOCOL *FullDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *VarConsole;
> + EFI_DEVICE_PATH_PROTOCOL *Instance;
> + VOID *Interface;
> + EFI_HANDLE NewHandle;
> + EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *TextOut;
> +
> + ASSERT (VarName != NULL);
> + ASSERT (ConsoleHandle != NULL);
> + ASSERT (ConsoleGuid != NULL);
> + ASSERT (ProtocolInterface != NULL);
> +
> + if (*ConsoleHandle != NULL) {
> + Status = gBS->HandleProtocol (
> + *ConsoleHandle,
> + ConsoleGuid,
> + &Interface
> + );
> + if (Status == EFI_SUCCESS && Interface == *ProtocolInterface) {
> + //
> + // If ConsoleHandle is valid and console protocol on this handle also
> + // also matched, just return.
> + //
> + return FALSE;
> + }
> + }
> +
> + //
> + // Get all possible consoles device path from EFI variable
> + //
> + VarConsole = BdsLibGetVariableAndSize (
> + VarName,
> + &gEfiGlobalVariableGuid,
> + &DevicePathSize
> + );
> + if (VarConsole == NULL) {
> + //
> + // If there is no any console device, just return.
> + //
> + return FALSE;
> + }
> +
> + FullDevicePath = VarConsole;
> +
> + do {
> + //
> + // Check every instance of the console variable
> + //
> + Instance = GetNextDevicePathInstance (&VarConsole, &DevicePathSize);
> + if (Instance == NULL) {
> + FreePool (FullDevicePath);
> + ASSERT (FALSE);
> + }
> +
> + //
> + // Find console device handle by device path instance
> + //
> + Status = gBS->LocateDevicePath (
> + ConsoleGuid,
> + &Instance,
> + &NewHandle
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Get the console protocol on this console device handle
> + //
> + Status = gBS->HandleProtocol (
> + NewHandle,
> + ConsoleGuid,
> + &Interface
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Update new console handle in System Table.
> + //
> + *ConsoleHandle = NewHandle;
> + *ProtocolInterface = Interface;
> + if (CompareGuid (ConsoleGuid, &gEfiSimpleTextOutProtocolGuid)) {
> + //
> + // If it is console out device, set console mode 80x25 if current mode is
> invalid.
> + //
> + TextOut = (EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *) Interface;
> + if (TextOut->Mode->Mode == -1) {
> + TextOut->SetMode (TextOut, 0);
> + }
> + }
> + return TRUE;
> + }
> + }
> +
> + } while (Instance != NULL);
> +
> + //
> + // No any available console devcie found.
> + //
> + return FALSE;
> +}
> +
> +/**
> + This function update console variable based on ConVarName, it can
> + add or remove one specific console device path from the variable
> +
> + @param ConVarName Console related variable name, ConIn,
> ConOut,
> + ErrOut.
> + @param CustomizedConDevicePath The console device path which will
> be added to
> + the console variable ConVarName, this parameter
> + can not be multi-instance.
> + @param ExclusiveDevicePath The console device path which will be
> removed
> + from the console variable ConVarName, this
> + parameter can not be multi-instance.
> +
> + @retval EFI_UNSUPPORTED The added device path is same to the
> removed one.
> + @retval EFI_SUCCESS Success add or remove the device path from
> the
> + console variable.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibUpdateConsoleVariable (
> + IN CHAR16 *ConVarName,
> + IN EFI_DEVICE_PATH_PROTOCOL *CustomizedConDevicePath,
> + IN EFI_DEVICE_PATH_PROTOCOL *ExclusiveDevicePath
> + )
> +{
> + EFI_STATUS Status;
> + EFI_DEVICE_PATH_PROTOCOL *VarConsole;
> + UINTN DevicePathSize;
> + EFI_DEVICE_PATH_PROTOCOL *NewDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *TempNewDevicePath;
> + UINT32 Attributes;
> +
> + VarConsole = NULL;
> + DevicePathSize = 0;
> +
> + //
> + // Notes: check the device path point, here should check
> + // with compare memory
> + //
> + if (CustomizedConDevicePath == ExclusiveDevicePath) {
> + return EFI_UNSUPPORTED;
> + }
> + //
> + // Delete the ExclusiveDevicePath from current default console
> + //
> + VarConsole = BdsLibGetVariableAndSize (
> + ConVarName,
> + &gEfiGlobalVariableGuid,
> + &DevicePathSize
> + );
> +
> + //
> + // Initialize NewDevicePath
> + //
> + NewDevicePath = VarConsole;
> +
> + //
> + // If ExclusiveDevicePath is even the part of the instance in VarConsole,
> delete it.
> + // In the end, NewDevicePath is the final device path.
> + //
> + if (ExclusiveDevicePath != NULL && VarConsole != NULL) {
> + NewDevicePath = BdsLibDelPartMatchInstance (VarConsole,
> ExclusiveDevicePath);
> + }
> + //
> + // Try to append customized device path to NewDevicePath.
> + //
> + if (CustomizedConDevicePath != NULL) {
> + if (!BdsLibMatchDevicePaths (NewDevicePath,
> CustomizedConDevicePath)) {
> + //
> + // Check if there is part of CustomizedConDevicePath in NewDevicePath,
> delete it.
> + //
> + NewDevicePath = BdsLibDelPartMatchInstance (NewDevicePath,
> CustomizedConDevicePath);
> + //
> + // In the first check, the default console variable will be
> _ModuleEntryPoint,
> + // just append current customized device path
> + //
> + TempNewDevicePath = NewDevicePath;
> + NewDevicePath = AppendDevicePathInstance (NewDevicePath,
> CustomizedConDevicePath);
> + if (TempNewDevicePath != NULL) {
> + FreePool(TempNewDevicePath);
> + }
> + }
> + }
> +
> + //
> + // The attribute for ConInDev, ConOutDev and ErrOutDev does not include
> NV.
> + //
> + if (IsNvNeed(ConVarName)) {
> + //
> + // ConVarName has NV attribute.
> + //
> + Attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE;
> + } else {
> + //
> + // ConVarName does not have NV attribute.
> + //
> + Attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS;
> + }
> +
> + //
> + // Finally, Update the variable of the default console by NewDevicePath
> + //
> + DevicePathSize = GetDevicePathSize (NewDevicePath);
> + Status = SetVariableAndReportStatusCodeOnError (
> + ConVarName,
> + &gEfiGlobalVariableGuid,
> + Attributes,
> + DevicePathSize,
> + NewDevicePath
> + );
> + if ((DevicePathSize == 0) && (Status == EFI_NOT_FOUND)) {
> + Status = EFI_SUCCESS;
> + }
> +
> + if (VarConsole == NewDevicePath) {
> + if (VarConsole != NULL) {
> + FreePool(VarConsole);
> + }
> + } else {
> + if (VarConsole != NULL) {
> + FreePool(VarConsole);
> + }
> + if (NewDevicePath != NULL) {
> + FreePool(NewDevicePath);
> + }
> + }
> +
> + return Status;
> +
> +}
> +
> +
> +/**
> + Connect the console device base on the variable ConVarName, if
> + device path of the ConVarName is multi-instance device path and
> + anyone of the instances is connected success, then this function
> + will return success.
> + If the handle associate with one device path node can not
> + be created successfully, then still give chance to do the dispatch,
> + which load the missing drivers if possible..
> +
> + @param ConVarName Console related variable name, ConIn,
> ConOut,
> + ErrOut.
> +
> + @retval EFI_NOT_FOUND There is not any console devices
> connected
> + success
> + @retval EFI_SUCCESS Success connect any one instance of the
> console
> + device path base on the variable ConVarName.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibConnectConsoleVariable (
> + IN CHAR16 *ConVarName
> + )
> +{
> + EFI_STATUS Status;
> + EFI_DEVICE_PATH_PROTOCOL *StartDevicePath;
> + UINTN VariableSize;
> + EFI_DEVICE_PATH_PROTOCOL *Instance;
> + EFI_DEVICE_PATH_PROTOCOL *Next;
> + EFI_DEVICE_PATH_PROTOCOL *CopyOfDevicePath;
> + UINTN Size;
> + BOOLEAN DeviceExist;
> +
> + Status = EFI_SUCCESS;
> + DeviceExist = FALSE;
> +
> + //
> + // Check if the console variable exist
> + //
> + StartDevicePath = BdsLibGetVariableAndSize (
> + ConVarName,
> + &gEfiGlobalVariableGuid,
> + &VariableSize
> + );
> + if (StartDevicePath == NULL) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + CopyOfDevicePath = StartDevicePath;
> + do {
> + //
> + // Check every instance of the console variable
> + //
> + Instance = GetNextDevicePathInstance (&CopyOfDevicePath, &Size);
> + if (Instance == NULL) {
> + FreePool (StartDevicePath);
> + return EFI_UNSUPPORTED;
> + }
> +
> + Next = Instance;
> + while (!IsDevicePathEndType (Next)) {
> + Next = NextDevicePathNode (Next);
> + }
> +
> + SetDevicePathEndNode (Next);
> + //
> + // Connect the USB console
> + // USB console device path is a short-form device path that
> + // starts with the first element being a USB WWID
> + // or a USB Class device path
> + //
> + if ((DevicePathType (Instance) == MESSAGING_DEVICE_PATH) &&
> + ((DevicePathSubType (Instance) == MSG_USB_CLASS_DP)
> + || (DevicePathSubType (Instance) == MSG_USB_WWID_DP)
> + )) {
> + Status = BdsLibConnectUsbDevByShortFormDP (0xFF, Instance);
> + if (!EFI_ERROR (Status)) {
> + DeviceExist = TRUE;
> + }
> + } else {
> + //
> + // Connect the instance device path
> + //
> + Status = BdsLibConnectDevicePath (Instance);
> +
> + if (EFI_ERROR (Status)) {
> + //
> + // Delete the instance from the console varialbe
> + //
> + BdsLibUpdateConsoleVariable (ConVarName, NULL, Instance);
> + } else {
> + DeviceExist = TRUE;
> + }
> + }
> + FreePool(Instance);
> + } while (CopyOfDevicePath != NULL);
> +
> + FreePool (StartDevicePath);
> +
> + if (!DeviceExist) {
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function will search every simpletext device in current system,
> + and make every simpletext device as pertantial console device.
> +
> +**/
> +VOID
> +EFIAPI
> +BdsLibConnectAllConsoles (
> + VOID
> + )
> +{
> + UINTN Index;
> + EFI_DEVICE_PATH_PROTOCOL *ConDevicePath;
> + UINTN HandleCount;
> + EFI_HANDLE *HandleBuffer;
> +
> + Index = 0;
> + HandleCount = 0;
> + HandleBuffer = NULL;
> + ConDevicePath = NULL;
> +
> + //
> + // Update all the console variables
> + //
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiSimpleTextInProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> +
> + for (Index = 0; Index < HandleCount; Index++) {
> + gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gEfiDevicePathProtocolGuid,
> + (VOID **) &ConDevicePath
> + );
> + BdsLibUpdateConsoleVariable (L"ConIn", ConDevicePath, NULL);
> + }
> +
> + if (HandleBuffer != NULL) {
> + FreePool(HandleBuffer);
> + HandleBuffer = NULL;
> + }
> +
> + gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiSimpleTextOutProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> + for (Index = 0; Index < HandleCount; Index++) {
> + gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gEfiDevicePathProtocolGuid,
> + (VOID **) &ConDevicePath
> + );
> + BdsLibUpdateConsoleVariable (L"ConOut", ConDevicePath, NULL);
> + BdsLibUpdateConsoleVariable (L"ErrOut", ConDevicePath, NULL);
> + }
> +
> + if (HandleBuffer != NULL) {
> + FreePool(HandleBuffer);
> + }
> +
> + //
> + // Connect all console variables
> + //
> + BdsLibConnectAllDefaultConsoles ();
> +
> +}
> +
> +/**
> + This function will connect console device base on the console
> + device variable ConIn, ConOut and ErrOut.
> +
> + @retval EFI_SUCCESS At least one of the ConIn and ConOut device
> have
> + been connected success.
> + @retval EFI_STATUS Return the status of
> BdsLibConnectConsoleVariable ().
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibConnectAllDefaultConsoles (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + BOOLEAN SystemTableUpdated;
> +
> + //
> + // Connect all default console variables
> + //
> +
> + //
> + // It seems impossible not to have any ConOut device on platform,
> + // so we check the status here.
> + //
> + Status = BdsLibConnectConsoleVariable (L"ConOut");
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Insert the performance probe for Console Out
> + //
> + PERF_START (NULL, "ConOut", "BDS", 1);
> + PERF_END (NULL, "ConOut", "BDS", 0);
> +
> + //
> + // Because possibly the platform is legacy free, in such case,
> + // ConIn devices (Serial Port and PS2 Keyboard ) does not exist,
> + // so we need not check the status.
> + //
> + BdsLibConnectConsoleVariable (L"ConIn");
> +
> + //
> + // The _ModuleEntryPoint err out var is legal.
> + //
> + BdsLibConnectConsoleVariable (L"ErrOut");
> +
> + SystemTableUpdated = FALSE;
> + //
> + // Fill console handles in System Table if no console device assignd.
> + //
> + if (UpdateSystemTableConsole (L"ConIn", &gEfiSimpleTextInProtocolGuid,
> &gST->ConsoleInHandle, (VOID **) &gST->ConIn)) {
> + SystemTableUpdated = TRUE;
> + }
> + if (UpdateSystemTableConsole (L"ConOut",
> &gEfiSimpleTextOutProtocolGuid, &gST->ConsoleOutHandle, (VOID **)
> &gST->ConOut)) {
> + SystemTableUpdated = TRUE;
> + }
> + if (UpdateSystemTableConsole (L"ErrOut",
> &gEfiSimpleTextOutProtocolGuid, &gST->StandardErrorHandle, (VOID **)
> &gST->StdErr)) {
> + SystemTableUpdated = TRUE;
> + }
> +
> + if (SystemTableUpdated) {
> + //
> + // Update the CRC32 in the EFI System Table header
> + //
> + gST->Hdr.CRC32 = 0;
> + gBS->CalculateCrc32 (
> + (UINT8 *) &gST->Hdr,
> + gST->Hdr.HeaderSize,
> + &gST->Hdr.CRC32
> + );
> + }
> +
> + //
> + // If any component set PcdTestKeyUsed to TRUE because use of a test
> key
> + // was detected, then display a warning message on the debug log and the
> console
> + //
> + if (PcdGetBool (PcdTestKeyUsed) == TRUE) {
> + DEBUG ((DEBUG_ERROR,
> "**********************************\n"));
> + DEBUG ((DEBUG_ERROR, "** WARNING: Test Key is used. **\n"));
> + DEBUG ((DEBUG_ERROR,
> "**********************************\n"));
> + Print (L"** WARNING: Test Key is used. **\n");
> + }
> +
> + return EFI_SUCCESS;
> +
> +}
> +
> +/**
> + This function will connect console device except ConIn base on the console
> + device variable ConOut and ErrOut.
> +
> + @retval EFI_SUCCESS At least one of the ConOut device have
> + been connected success.
> + @retval EFI_STATUS Return the status of
> BdsLibConnectConsoleVariable ().
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibConnectAllDefaultConsolesWithOutConIn (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + BOOLEAN SystemTableUpdated;
> +
> + //
> + // Connect all default console variables except ConIn
> + //
> +
> + //
> + // It seems impossible not to have any ConOut device on platform,
> + // so we check the status here.
> + //
> + Status = BdsLibConnectConsoleVariable (L"ConOut");
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Insert the performance probe for Console Out
> + //
> + PERF_START (NULL, "ConOut", "BDS", 1);
> + PERF_END (NULL, "ConOut", "BDS", 0);
> +
> + //
> + // The _ModuleEntryPoint err out var is legal.
> + //
> + BdsLibConnectConsoleVariable (L"ErrOut");
> +
> + SystemTableUpdated = FALSE;
> + //
> + // Fill console handles in System Table if no console device assignd.
> + //
> + if (UpdateSystemTableConsole (L"ConOut",
> &gEfiSimpleTextOutProtocolGuid, &gST->ConsoleOutHandle, (VOID **)
> &gST->ConOut)) {
> + SystemTableUpdated = TRUE;
> + }
> + if (UpdateSystemTableConsole (L"ErrOut",
> &gEfiSimpleTextOutProtocolGuid, &gST->StandardErrorHandle, (VOID **)
> &gST->StdErr)) {
> + SystemTableUpdated = TRUE;
> + }
> +
> + if (SystemTableUpdated) {
> + //
> + // Update the CRC32 in the EFI System Table header
> + //
> + gST->Hdr.CRC32 = 0;
> + gBS->CalculateCrc32 (
> + (UINT8 *) &gST->Hdr,
> + gST->Hdr.HeaderSize,
> + &gST->Hdr.CRC32
> + );
> + }
> +
> + return EFI_SUCCESS;
> +
> +}
> +
> +/**
> + Use SystemTable Conout to stop video based Simple Text Out consoles
> from going
> + to the video device. Put up LogoFile on every video device that is a console.
> +
> + @param[in] LogoFile File name of logo to display on the center of the
> screen.
> +
> + @retval EFI_SUCCESS ConsoleControl has been flipped to graphics and
> logo displayed.
> + @retval EFI_UNSUPPORTED Logo not found
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +EnableQuietBoot (
> + IN EFI_GUID *LogoFile
> + )
> +{
> + EFI_STATUS Status;
> + EFI_OEM_BADGING_PROTOCOL *Badging;
> + UINT32 SizeOfX;
> + UINT32 SizeOfY;
> + INTN DestX;
> + INTN DestY;
> + UINT8 *ImageData;
> + UINTN ImageSize;
> + UINTN BltSize;
> + UINT32 Instance;
> + EFI_BADGING_FORMAT Format;
> + EFI_BADGING_DISPLAY_ATTRIBUTE Attribute;
> + UINTN CoordinateX;
> + UINTN CoordinateY;
> + UINTN Height;
> + UINTN Width;
> + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;
> + EFI_UGA_DRAW_PROTOCOL *UgaDraw;
> + UINT32 ColorDepth;
> + UINT32 RefreshRate;
> + EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;
> + EFI_BOOT_LOGO_PROTOCOL *BootLogo;
> + UINTN NumberOfLogos;
> + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *LogoBlt;
> + UINTN LogoDestX;
> + UINTN LogoDestY;
> + UINTN LogoHeight;
> + UINTN LogoWidth;
> + UINTN NewDestX;
> + UINTN NewDestY;
> + UINTN NewHeight;
> + UINTN NewWidth;
> + UINT64 BufferSize;
> +
> + UgaDraw = NULL;
> + //
> + // Try to open GOP first
> + //
> + Status = gBS->HandleProtocol (gST->ConsoleOutHandle,
> &gEfiGraphicsOutputProtocolGuid, (VOID **) &GraphicsOutput);
> + if (EFI_ERROR (Status) && FeaturePcdGet (PcdUgaConsumeSupport)) {
> + GraphicsOutput = NULL;
> + //
> + // Open GOP failed, try to open UGA
> + //
> + Status = gBS->HandleProtocol (gST->ConsoleOutHandle,
> &gEfiUgaDrawProtocolGuid, (VOID **) &UgaDraw);
> + }
> + if (EFI_ERROR (Status)) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Try to open Boot Logo Protocol.
> + //
> + BootLogo = NULL;
> + gBS->LocateProtocol (&gEfiBootLogoProtocolGuid, NULL, (VOID **)
> &BootLogo);
> +
> + //
> + // Erase Cursor from screen
> + //
> + gST->ConOut->EnableCursor (gST->ConOut, FALSE);
> +
> + Badging = NULL;
> + Status = gBS->LocateProtocol (&gEfiOEMBadgingProtocolGuid, NULL,
> (VOID **) &Badging);
> +
> + if (GraphicsOutput != NULL) {
> + SizeOfX = GraphicsOutput->Mode->Info->HorizontalResolution;
> + SizeOfY = GraphicsOutput->Mode->Info->VerticalResolution;
> +
> + } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport))
> {
> + Status = UgaDraw->GetMode (UgaDraw, &SizeOfX, &SizeOfY,
> &ColorDepth, &RefreshRate);
> + if (EFI_ERROR (Status)) {
> + return EFI_UNSUPPORTED;
> + }
> + } else {
> + return EFI_UNSUPPORTED;
> + }
> +
> + Blt = NULL;
> + NumberOfLogos = 0;
> + LogoDestX = 0;
> + LogoDestY = 0;
> + LogoHeight = 0;
> + LogoWidth = 0;
> + NewDestX = 0;
> + NewDestY = 0;
> + NewHeight = 0;
> + NewWidth = 0;
> + Instance = 0;
> + while (1) {
> + ImageData = NULL;
> + ImageSize = 0;
> +
> + if (Badging != NULL) {
> + //
> + // Get image from OEMBadging protocol.
> + //
> + Status = Badging->GetImage (
> + Badging,
> + &Instance,
> + &Format,
> + &ImageData,
> + &ImageSize,
> + &Attribute,
> + &CoordinateX,
> + &CoordinateY
> + );
> + if (EFI_ERROR (Status)) {
> + goto Done;
> + }
> +
> + //
> + // Currently only support BMP format.
> + //
> + if (Format != EfiBadgingFormatBMP) {
> + if (ImageData != NULL) {
> + FreePool (ImageData);
> + }
> + continue;
> + }
> + } else {
> + //
> + // Get the specified image from FV.
> + //
> + Status = GetSectionFromAnyFv (LogoFile, EFI_SECTION_RAW, 0, (VOID
> **) &ImageData, &ImageSize);
> + if (EFI_ERROR (Status)) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + CoordinateX = 0;
> + CoordinateY = 0;
> + if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) {
> + Attribute = EfiBadgingDisplayAttributeCenter;
> + } else {
> + Attribute = EfiBadgingDisplayAttributeCustomized;
> + }
> + }
> +
> + if (Blt != NULL) {
> + FreePool (Blt);
> + }
> + Blt = NULL;
> + Status = TranslateBmpToGopBlt (
> + ImageData,
> + ImageSize,
> + &Blt,
> + &BltSize,
> + &Height,
> + &Width
> + );
> + if (EFI_ERROR (Status)) {
> + FreePool (ImageData);
> +
> + if (Badging == NULL) {
> + return Status;
> + } else {
> + continue;
> + }
> + }
> +
> + //
> + // Calculate the display position according to Attribute.
> + //
> + switch (Attribute) {
> + case EfiBadgingDisplayAttributeLeftTop:
> + DestX = CoordinateX;
> + DestY = CoordinateY;
> + break;
> +
> + case EfiBadgingDisplayAttributeCenterTop:
> + DestX = (SizeOfX - Width) / 2;
> + DestY = CoordinateY;
> + break;
> +
> + case EfiBadgingDisplayAttributeRightTop:
> + DestX = (SizeOfX - Width - CoordinateX);
> + DestY = CoordinateY;;
> + break;
> +
> + case EfiBadgingDisplayAttributeCenterRight:
> + DestX = (SizeOfX - Width - CoordinateX);
> + DestY = (SizeOfY - Height) / 2;
> + break;
> +
> + case EfiBadgingDisplayAttributeRightBottom:
> + DestX = (SizeOfX - Width - CoordinateX);
> + DestY = (SizeOfY - Height - CoordinateY);
> + break;
> +
> + case EfiBadgingDisplayAttributeCenterBottom:
> + DestX = (SizeOfX - Width) / 2;
> + DestY = (SizeOfY - Height - CoordinateY);
> + break;
> +
> + case EfiBadgingDisplayAttributeLeftBottom:
> + DestX = CoordinateX;
> + DestY = (SizeOfY - Height - CoordinateY);
> + break;
> +
> + case EfiBadgingDisplayAttributeCenterLeft:
> + DestX = CoordinateX;
> + DestY = (SizeOfY - Height) / 2;
> + break;
> +
> + case EfiBadgingDisplayAttributeCenter:
> + DestX = (SizeOfX - Width) / 2;
> + DestY = (SizeOfY - Height) / 2;
> + break;
> +
> + case EfiBadgingDisplayAttributeCustomized:
> + DestX = (SizeOfX - Width) / 2;
> + DestY = ((SizeOfY * 382) / 1000) - Height / 2;
> + break;
> +
> + default:
> + DestX = CoordinateX;
> + DestY = CoordinateY;
> + break;
> + }
> +
> + if ((DestX >= 0) && (DestY >= 0)) {
> + if (GraphicsOutput != NULL) {
> + Status = GraphicsOutput->Blt (
> + GraphicsOutput,
> + Blt,
> + EfiBltBufferToVideo,
> + 0,
> + 0,
> + (UINTN) DestX,
> + (UINTN) DestY,
> + Width,
> + Height,
> + Width * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
> + );
> + } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport))
> {
> + Status = UgaDraw->Blt (
> + UgaDraw,
> + (EFI_UGA_PIXEL *) Blt,
> + EfiUgaBltBufferToVideo,
> + 0,
> + 0,
> + (UINTN) DestX,
> + (UINTN) DestY,
> + Width,
> + Height,
> + Width * sizeof (EFI_UGA_PIXEL)
> + );
> + } else {
> + Status = EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Report displayed Logo information.
> + //
> + if (!EFI_ERROR (Status)) {
> + NumberOfLogos++;
> +
> + if (LogoWidth == 0) {
> + //
> + // The first Logo.
> + //
> + LogoDestX = (UINTN) DestX;
> + LogoDestY = (UINTN) DestY;
> + LogoWidth = Width;
> + LogoHeight = Height;
> + } else {
> + //
> + // Merge new logo with old one.
> + //
> + NewDestX = MIN ((UINTN) DestX, LogoDestX);
> + NewDestY = MIN ((UINTN) DestY, LogoDestY);
> + NewWidth = MAX ((UINTN) DestX + Width, LogoDestX + LogoWidth) -
> NewDestX;
> + NewHeight = MAX ((UINTN) DestY + Height, LogoDestY + LogoHeight) -
> NewDestY;
> +
> + LogoDestX = NewDestX;
> + LogoDestY = NewDestY;
> + LogoWidth = NewWidth;
> + LogoHeight = NewHeight;
> + }
> + }
> + }
> +
> + FreePool (ImageData);
> +
> + if (Badging == NULL) {
> + break;
> + }
> + }
> +
> +Done:
> + if (BootLogo == NULL || NumberOfLogos == 0) {
> + //
> + // No logo displayed.
> + //
> + if (Blt != NULL) {
> + FreePool (Blt);
> + }
> +
> + return Status;
> + }
> +
> + //
> + // Advertise displayed Logo information.
> + //
> + if (NumberOfLogos == 1) {
> + //
> + // Only one logo displayed, use its Blt buffer directly for BootLogo
> protocol.
> + //
> + LogoBlt = Blt;
> + Status = EFI_SUCCESS;
> + } else {
> + //
> + // More than one Logo displayed, get merged BltBuffer using
> VideoToBuffer operation.
> + //
> + if (Blt != NULL) {
> + FreePool (Blt);
> + }
> +
> + //
> + // Ensure the LogoHeight * LogoWidth doesn't overflow
> + //
> + if (LogoHeight > DivU64x64Remainder ((UINTN) ~0, LogoWidth, NULL)) {
> + return EFI_UNSUPPORTED;
> + }
> + BufferSize = MultU64x64 (LogoWidth, LogoHeight);
> +
> + //
> + // Ensure the BufferSize * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
> doesn't overflow
> + //
> + if (BufferSize > DivU64x32 ((UINTN) ~0, sizeof
> (EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + LogoBlt = AllocateZeroPool ((UINTN)BufferSize * sizeof
> (EFI_GRAPHICS_OUTPUT_BLT_PIXEL));
> + if (LogoBlt == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + if (GraphicsOutput != NULL) {
> + Status = GraphicsOutput->Blt (
> + GraphicsOutput,
> + LogoBlt,
> + EfiBltVideoToBltBuffer,
> + LogoDestX,
> + LogoDestY,
> + 0,
> + 0,
> + LogoWidth,
> + LogoHeight,
> + LogoWidth * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
> + );
> + } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport))
> {
> + Status = UgaDraw->Blt (
> + UgaDraw,
> + (EFI_UGA_PIXEL *) LogoBlt,
> + EfiUgaVideoToBltBuffer,
> + LogoDestX,
> + LogoDestY,
> + 0,
> + 0,
> + LogoWidth,
> + LogoHeight,
> + LogoWidth * sizeof (EFI_UGA_PIXEL)
> + );
> + } else {
> + Status = EFI_UNSUPPORTED;
> + }
> + }
> +
> + if (!EFI_ERROR (Status)) {
> + BootLogo->SetBootLogo (BootLogo, LogoBlt, LogoDestX, LogoDestY,
> LogoWidth, LogoHeight);
> + }
> + FreePool (LogoBlt);
> +
> + return Status;
> +}
> +
> +/**
> + Use SystemTable Conout to turn on video based Simple Text Out consoles.
> The
> + Simple Text Out screens will now be synced up with all non video output
> devices
> +
> + @retval EFI_SUCCESS UGA devices are back in text mode and synced up.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +DisableQuietBoot (
> + VOID
> + )
> +{
> +
> + //
> + // Enable Cursor on Screen
> + //
> + gST->ConOut->EnableCursor (gST->ConOut, TRUE);
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsMisc.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsMisc.c
> new file mode 100644
> index 0000000000..313a1ea9f6
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/BdsMisc.c
> @@ -0,0 +1,1575 @@
> +/** @file
> + Misc BDS library function
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "InternalBdsLib.h"
> +
> +
> +#define MAX_STRING_LEN 200
> +
> +BOOLEAN mFeaturerSwitch = TRUE;
> +BOOLEAN mResetRequired = FALSE;
> +
> +extern UINT16 gPlatformBootTimeOutDefault;
> +
> +/**
> + The function will go through the driver option link list, load and start
> + every driver the driver option device path point to.
> +
> + @param BdsDriverLists The header of the current driver option link list
> +
> +**/
> +VOID
> +EFIAPI
> +BdsLibLoadDrivers (
> + IN LIST_ENTRY *BdsDriverLists
> + )
> +{
> + EFI_STATUS Status;
> + LIST_ENTRY *Link;
> + BDS_COMMON_OPTION *Option;
> + EFI_HANDLE ImageHandle;
> + EFI_LOADED_IMAGE_PROTOCOL *ImageInfo;
> + UINTN ExitDataSize;
> + CHAR16 *ExitData;
> + BOOLEAN ReconnectAll;
> +
> + ReconnectAll = FALSE;
> +
> + //
> + // Process the driver option
> + //
> + for (Link = BdsDriverLists->ForwardLink; Link != BdsDriverLists; Link = Link-
> >ForwardLink) {
> + Option = CR (Link, BDS_COMMON_OPTION, Link,
> BDS_LOAD_OPTION_SIGNATURE);
> +
> + //
> + // If a load option is not marked as LOAD_OPTION_ACTIVE,
> + // the boot manager will not automatically load the option.
> + //
> + if (!IS_LOAD_OPTION_TYPE (Option->Attribute, LOAD_OPTION_ACTIVE))
> {
> + continue;
> + }
> +
> + //
> + // If a driver load option is marked as LOAD_OPTION_FORCE_RECONNECT,
> + // then all of the EFI drivers in the system will be disconnected and
> + // reconnected after the last driver load option is processed.
> + //
> + if (IS_LOAD_OPTION_TYPE (Option->Attribute,
> LOAD_OPTION_FORCE_RECONNECT)) {
> + ReconnectAll = TRUE;
> + }
> +
> + //
> + // Make sure the driver path is connected.
> + //
> + BdsLibConnectDevicePath (Option->DevicePath);
> +
> + //
> + // Load and start the image that Driver#### describes
> + //
> + Status = gBS->LoadImage (
> + FALSE,
> + gImageHandle,
> + Option->DevicePath,
> + NULL,
> + 0,
> + &ImageHandle
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + gBS->HandleProtocol (ImageHandle, &gEfiLoadedImageProtocolGuid,
> (VOID **) &ImageInfo);
> +
> + //
> + // Verify whether this image is a driver, if not,
> + // exit it and continue to parse next load option
> + //
> + if (ImageInfo->ImageCodeType != EfiBootServicesCode && ImageInfo-
> >ImageCodeType != EfiRuntimeServicesCode) {
> + gBS->Exit (ImageHandle, EFI_INVALID_PARAMETER, 0, NULL);
> + continue;
> + }
> +
> + if (Option->LoadOptionsSize != 0) {
> + ImageInfo->LoadOptionsSize = Option->LoadOptionsSize;
> + ImageInfo->LoadOptions = Option->LoadOptions;
> + }
> + //
> + // Before calling the image, enable the Watchdog Timer for
> + // the 5 Minute period
> + //
> + gBS->SetWatchdogTimer (5 * 60, 0x0000, 0x00, NULL);
> +
> + Status = gBS->StartImage (ImageHandle, &ExitDataSize, &ExitData);
> + DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Driver Return Status = %r\n",
> Status));
> +
> + //
> + // Clear the Watchdog Timer after the image returns
> + //
> + gBS->SetWatchdogTimer (0x0000, 0x0000, 0x0000, NULL);
> + }
> + }
> +
> + //
> + // Process the LOAD_OPTION_FORCE_RECONNECT driver option
> + //
> + if (ReconnectAll) {
> + BdsLibDisconnectAllEfi ();
> + BdsLibConnectAll ();
> + }
> +
> +}
> +
> +/**
> + Get the Option Number that does not used.
> + Try to locate the specific option variable one by one utile find a free
> number.
> +
> + @param VariableName Indicate if the boot#### or driver#### option
> +
> + @return The Minimal Free Option Number
> +
> +**/
> +UINT16
> +BdsLibGetFreeOptionNumber (
> + IN CHAR16 *VariableName
> + )
> +{
> + UINTN Index;
> + CHAR16 StrTemp[10];
> + UINT16 *OptionBuffer;
> + UINTN OptionSize;
> +
> + //
> + // Try to find the minimum free number from 0, 1, 2, 3....
> + //
> + Index = 0;
> + do {
> + if (*VariableName == 'B') {
> + UnicodeSPrint (StrTemp, sizeof (StrTemp), L"Boot%04x", Index);
> + } else {
> + UnicodeSPrint (StrTemp, sizeof (StrTemp), L"Driver%04x", Index);
> + }
> + //
> + // try if the option number is used
> + //
> + OptionBuffer = BdsLibGetVariableAndSize (
> + StrTemp,
> + &gEfiGlobalVariableGuid,
> + &OptionSize
> + );
> + if (OptionBuffer == NULL) {
> + break;
> + }
> + FreePool(OptionBuffer);
> + Index++;
> + } while (TRUE);
> +
> + return ((UINT16) Index);
> +}
> +
> +
> +/**
> + This function will register the new boot#### or driver#### option base on
> + the VariableName. The new registered boot#### or driver#### will be
> linked
> + to BdsOptionList and also update to the VariableName. After the
> boot#### or
> + driver#### updated, the BootOrder or DriverOrder will also be updated.
> +
> + @param BdsOptionList The header of the boot#### or driver#### link
> list
> + @param DevicePath The device path which the boot#### or
> driver####
> + option present
> + @param String The description of the boot#### or driver####
> + @param VariableName Indicate if the boot#### or driver#### option
> +
> + @retval EFI_SUCCESS The boot#### or driver#### have been success
> + registered
> + @retval EFI_STATUS Return the status of gRT->SetVariable ().
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibRegisterNewOption (
> + IN LIST_ENTRY *BdsOptionList,
> + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
> + IN CHAR16 *String,
> + IN CHAR16 *VariableName
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> + UINT16 RegisterOptionNumber;
> + UINT16 *TempOptionPtr;
> + UINTN TempOptionSize;
> + UINT16 *OptionOrderPtr;
> + VOID *OptionPtr;
> + UINTN OptionSize;
> + UINT8 *TempPtr;
> + EFI_DEVICE_PATH_PROTOCOL *OptionDevicePath;
> + CHAR16 *Description;
> + CHAR16 OptionName[10];
> + BOOLEAN UpdateDescription;
> + UINT16 BootOrderEntry;
> + UINTN OrderItemNum;
> +
> + if (DevicePath == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + OptionPtr = NULL;
> + OptionSize = 0;
> + TempPtr = NULL;
> + OptionDevicePath = NULL;
> + Description = NULL;
> + OptionOrderPtr = NULL;
> + UpdateDescription = FALSE;
> + Status = EFI_SUCCESS;
> + ZeroMem (OptionName, sizeof (OptionName));
> +
> + TempOptionSize = 0;
> + TempOptionPtr = BdsLibGetVariableAndSize (
> + VariableName,
> + &gEfiGlobalVariableGuid,
> + &TempOptionSize
> + );
> + //
> + // Compare with current option variable if the previous option is set in
> global variable.
> + //
> + for (Index = 0; Index < TempOptionSize / sizeof (UINT16); Index++) {
> + //
> + // TempOptionPtr must not be NULL if we have non-zero
> TempOptionSize.
> + //
> + ASSERT (TempOptionPtr != NULL);
> +
> + if (*VariableName == 'B') {
> + UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x",
> TempOptionPtr[Index]);
> + } else {
> + UnicodeSPrint (OptionName, sizeof (OptionName), L"Driver%04x",
> TempOptionPtr[Index]);
> + }
> +
> + OptionPtr = BdsLibGetVariableAndSize (
> + OptionName,
> + &gEfiGlobalVariableGuid,
> + &OptionSize
> + );
> + if (OptionPtr == NULL) {
> + continue;
> + }
> +
> + //
> + // Validate the variable.
> + //
> + if (!ValidateOption(OptionPtr, OptionSize)) {
> + FreePool(OptionPtr);
> + continue;
> + }
> +
> + TempPtr = OptionPtr;
> + TempPtr += sizeof (UINT32) + sizeof (UINT16);
> + Description = (CHAR16 *) TempPtr;
> + TempPtr += StrSize ((CHAR16 *) TempPtr);
> + OptionDevicePath = (EFI_DEVICE_PATH_PROTOCOL *) TempPtr;
> +
> + //
> + // Notes: the description may will change base on the GetStringToken
> + //
> + if (CompareMem (OptionDevicePath, DevicePath, GetDevicePathSize
> (OptionDevicePath)) == 0) {
> + if (CompareMem (Description, String, StrSize (Description)) == 0) {
> + //
> + // Got the option, so just return
> + //
> + FreePool (OptionPtr);
> + FreePool (TempOptionPtr);
> + return EFI_SUCCESS;
> + } else {
> + //
> + // Option description changed, need update.
> + //
> + UpdateDescription = TRUE;
> + FreePool (OptionPtr);
> + break;
> + }
> + }
> +
> + FreePool (OptionPtr);
> + }
> +
> + OptionSize = sizeof (UINT32) + sizeof (UINT16) + StrSize (String);
> + OptionSize += GetDevicePathSize (DevicePath);
> + OptionPtr = AllocateZeroPool (OptionSize);
> + ASSERT (OptionPtr != NULL);
> +
> + TempPtr = OptionPtr;
> + *(UINT32 *) TempPtr = LOAD_OPTION_ACTIVE;
> + TempPtr += sizeof (UINT32);
> + *(UINT16 *) TempPtr = (UINT16) GetDevicePathSize (DevicePath);
> + TempPtr += sizeof (UINT16);
> + CopyMem (TempPtr, String, StrSize (String));
> + TempPtr += StrSize (String);
> + CopyMem (TempPtr, DevicePath, GetDevicePathSize (DevicePath));
> +
> + if (UpdateDescription) {
> + //
> + // The number in option#### to be updated.
> + // In this case, we must have non-NULL TempOptionPtr.
> + //
> + ASSERT (TempOptionPtr != NULL);
> + RegisterOptionNumber = TempOptionPtr[Index];
> + } else {
> + //
> + // The new option#### number
> + //
> + RegisterOptionNumber = BdsLibGetFreeOptionNumber(VariableName);
> + }
> +
> + if (*VariableName == 'B') {
> + UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x",
> RegisterOptionNumber);
> + } else {
> + UnicodeSPrint (OptionName, sizeof (OptionName), L"Driver%04x",
> RegisterOptionNumber);
> + }
> +
> + Status = gRT->SetVariable (
> + OptionName,
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + OptionSize,
> + OptionPtr
> + );
> + //
> + // Return if only need to update a changed description or fail to set option.
> + //
> + if (EFI_ERROR (Status) || UpdateDescription) {
> + FreePool (OptionPtr);
> + if (TempOptionPtr != NULL) {
> + FreePool (TempOptionPtr);
> + }
> + return Status;
> + }
> +
> + FreePool (OptionPtr);
> +
> + //
> + // Update the option order variable
> + //
> +
> + //
> + // If no option order
> + //
> + if (TempOptionSize == 0) {
> + BootOrderEntry = 0;
> + Status = gRT->SetVariable (
> + VariableName,
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + sizeof (UINT16),
> + &BootOrderEntry
> + );
> + if (TempOptionPtr != NULL) {
> + FreePool (TempOptionPtr);
> + }
> + return Status;
> + }
> +
> + //
> + // TempOptionPtr must not be NULL if TempOptionSize is not zero.
> + //
> + ASSERT (TempOptionPtr != NULL);
> + //
> + // Append the new option number to the original option order
> + //
> + OrderItemNum = (TempOptionSize / sizeof (UINT16)) + 1 ;
> + OptionOrderPtr = AllocateZeroPool ( OrderItemNum * sizeof (UINT16));
> + ASSERT (OptionOrderPtr!= NULL);
> + CopyMem (OptionOrderPtr, TempOptionPtr, (OrderItemNum - 1) * sizeof
> (UINT16));
> +
> + OptionOrderPtr[Index] = RegisterOptionNumber;
> +
> + Status = gRT->SetVariable (
> + VariableName,
> + &gEfiGlobalVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + OrderItemNum * sizeof (UINT16),
> + OptionOrderPtr
> + );
> + FreePool (TempOptionPtr);
> + FreePool (OptionOrderPtr);
> +
> + return Status;
> +}
> +
> +/**
> + Returns the size of a device path in bytes.
> +
> + This function returns the size, in bytes, of the device path data structure
> + specified by DevicePath including the end of device path node. If
> DevicePath
> + is NULL, then 0 is returned. If the length of the device path is bigger than
> + MaxSize, also return 0 to indicate this is an invalidate device path.
> +
> + @param DevicePath A pointer to a device path data structure.
> + @param MaxSize Max valid device path size. If big than this size,
> + return error.
> +
> + @retval 0 An invalid device path.
> + @retval Others The size of a device path in bytes.
> +
> +**/
> +UINTN
> +GetDevicePathSizeEx (
> + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,
> + IN UINTN MaxSize
> + )
> +{
> + UINTN Size;
> + UINTN NodeSize;
> +
> + if (DevicePath == NULL) {
> + return 0;
> + }
> +
> + //
> + // Search for the end of the device path structure
> + //
> + Size = 0;
> + while (!IsDevicePathEnd (DevicePath)) {
> + NodeSize = DevicePathNodeLength (DevicePath);
> + if (NodeSize < END_DEVICE_PATH_LENGTH) {
> + return 0;
> + }
> + Size += NodeSize;
> + if (Size > MaxSize) {
> + return 0;
> + }
> + DevicePath = NextDevicePathNode (DevicePath);
> + }
> + Size += DevicePathNodeLength (DevicePath);
> + if (Size > MaxSize) {
> + return 0;
> + }
> +
> + return Size;
> +}
> +
> +/**
> + Returns the length of a Null-terminated Unicode string. If the length is
> + bigger than MaxStringLen, return length 0 to indicate that this is an
> + invalidate string.
> +
> + This function returns the byte length of Unicode characters in the Null-
> terminated
> + Unicode string specified by String.
> +
> + If String is NULL, then ASSERT().
> + If String is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param String A pointer to a Null-terminated Unicode string.
> + @param MaxStringLen Max string len in this string.
> +
> + @retval 0 An invalid string.
> + @retval Others The length of String.
> +
> +**/
> +UINTN
> +StrSizeEx (
> + IN CONST CHAR16 *String,
> + IN UINTN MaxStringLen
> + )
> +{
> + UINTN Length;
> +
> + ASSERT (String != NULL && MaxStringLen != 0);
> + ASSERT (((UINTN) String & BIT0) == 0);
> +
> + for (Length = 0; *String != L'\0' && MaxStringLen != Length; String++,
> Length+=2);
> +
> + if (*String != L'\0' && MaxStringLen == Length) {
> + return 0;
> + }
> +
> + return Length + 2;
> +}
> +
> +/**
> + Validate the EFI Boot#### variable (VendorGuid/Name)
> +
> + @param Variable Boot#### variable data.
> + @param VariableSize Returns the size of the EFI variable that was
> read
> +
> + @retval TRUE The variable data is correct.
> + @retval FALSE The variable data is corrupted.
> +
> +**/
> +BOOLEAN
> +ValidateOption (
> + UINT8 *Variable,
> + UINTN VariableSize
> + )
> +{
> + UINT16 FilePathSize;
> + UINT8 *TempPtr;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + UINTN TempSize;
> +
> + if (VariableSize <= sizeof (UINT16) + sizeof (UINT32)) {
> + return FALSE;
> + }
> +
> + //
> + // Skip the option attribute
> + //
> + TempPtr = Variable;
> + TempPtr += sizeof (UINT32);
> +
> + //
> + // Get the option's device path size
> + //
> + FilePathSize = *(UINT16 *) TempPtr;
> + TempPtr += sizeof (UINT16);
> +
> + //
> + // Get the option's description string size
> + //
> + TempSize = StrSizeEx ((CHAR16 *) TempPtr, VariableSize - sizeof (UINT16) -
> sizeof (UINT32));
> + TempPtr += TempSize;
> +
> + //
> + // Get the option's device path
> + //
> + DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) TempPtr;
> + TempPtr += FilePathSize;
> +
> + //
> + // Validation boot option variable.
> + //
> + if ((FilePathSize == 0) || (TempSize == 0)) {
> + return FALSE;
> + }
> +
> + if (TempSize + FilePathSize + sizeof (UINT16) + sizeof (UINT32) >
> VariableSize) {
> + return FALSE;
> + }
> +
> + return (BOOLEAN) (GetDevicePathSizeEx (DevicePath, FilePathSize) != 0);
> +}
> +
> +/**
> + Convert a single character to number.
> + It assumes the input Char is in the scope of L'0' ~ L'9' and L'A' ~ L'F'
> +
> + @param Char The input char which need to change to a hex number.
> +
> +**/
> +UINTN
> +CharToUint (
> + IN CHAR16 Char
> + )
> +{
> + if ((Char >= L'0') && (Char <= L'9')) {
> + return (UINTN) (Char - L'0');
> + }
> +
> + if ((Char >= L'A') && (Char <= L'F')) {
> + return (UINTN) (Char - L'A' + 0xA);
> + }
> +
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Build the boot#### or driver#### option from the VariableName, the
> + build boot#### or driver#### will also be linked to BdsCommonOptionList.
> +
> + @param BdsCommonOptionList The header of the boot#### or
> driver#### option
> + link list
> + @param VariableName EFI Variable name indicate if it is boot#### or
> + driver####
> +
> + @retval BDS_COMMON_OPTION Get the option just been created
> + @retval NULL Failed to get the new option
> +
> +**/
> +BDS_COMMON_OPTION *
> +EFIAPI
> +BdsLibVariableToOption (
> + IN OUT LIST_ENTRY *BdsCommonOptionList,
> + IN CHAR16 *VariableName
> + )
> +{
> + UINT32 Attribute;
> + UINT16 FilePathSize;
> + UINT8 *Variable;
> + UINT8 *TempPtr;
> + UINTN VariableSize;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + BDS_COMMON_OPTION *Option;
> + VOID *LoadOptions;
> + UINT32 LoadOptionsSize;
> + CHAR16 *Description;
> + UINT8 NumOff;
> +
> + //
> + // Read the variable. We will never free this data.
> + //
> + Variable = BdsLibGetVariableAndSize (
> + VariableName,
> + &gEfiGlobalVariableGuid,
> + &VariableSize
> + );
> + if (Variable == NULL) {
> + return NULL;
> + }
> +
> + //
> + // Validate Boot#### variable data.
> + //
> + if (!ValidateOption(Variable, VariableSize)) {
> + FreePool (Variable);
> + return NULL;
> + }
> +
> + //
> + // Notes: careful defined the variable of Boot#### or
> + // Driver####, consider use some macro to abstract the code
> + //
> + //
> + // Get the option attribute
> + //
> + TempPtr = Variable;
> + Attribute = *(UINT32 *) Variable;
> + TempPtr += sizeof (UINT32);
> +
> + //
> + // Get the option's device path size
> + //
> + FilePathSize = *(UINT16 *) TempPtr;
> + TempPtr += sizeof (UINT16);
> +
> + //
> + // Get the option's description string
> + //
> + Description = (CHAR16 *) TempPtr;
> +
> + //
> + // Get the option's description string size
> + //
> + TempPtr += StrSize((CHAR16 *) TempPtr);
> +
> + //
> + // Get the option's device path
> + //
> + DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) TempPtr;
> + TempPtr += FilePathSize;
> +
> + //
> + // Get load opion data.
> + //
> + LoadOptions = TempPtr;
> + LoadOptionsSize = (UINT32) (VariableSize - (UINTN) (TempPtr - Variable));
> +
> + //
> + // The Console variables may have multiple device paths, so make
> + // an Entry for each one.
> + //
> + Option = AllocateZeroPool (sizeof (BDS_COMMON_OPTION));
> + if (Option == NULL) {
> + FreePool (Variable);
> + return NULL;
> + }
> +
> + Option->Signature = BDS_LOAD_OPTION_SIGNATURE;
> + Option->DevicePath = AllocateZeroPool (GetDevicePathSize (DevicePath));
> + ASSERT(Option->DevicePath != NULL);
> + CopyMem (Option->DevicePath, DevicePath, GetDevicePathSize
> (DevicePath));
> +
> + Option->Attribute = Attribute;
> + Option->Description = AllocateZeroPool (StrSize (Description));
> + ASSERT(Option->Description != NULL);
> + CopyMem (Option->Description, Description, StrSize (Description));
> +
> + Option->LoadOptions = AllocateZeroPool (LoadOptionsSize);
> + ASSERT(Option->LoadOptions != NULL);
> + CopyMem (Option->LoadOptions, LoadOptions, LoadOptionsSize);
> + Option->LoadOptionsSize = LoadOptionsSize;
> +
> + //
> + // Get the value from VariableName Unicode string
> + // since the ISO standard assumes ASCII equivalent abbreviations, we can
> be safe in converting this
> + // Unicode stream to ASCII without any loss in meaning.
> + //
> + if (*VariableName == 'B') {
> + NumOff = (UINT8) (sizeof (L"Boot") / sizeof (CHAR16) - 1);
> + Option->BootCurrent = (UINT16) (CharToUint (VariableName[NumOff+0])
> * 0x1000)
> + + (UINT16) (CharToUint (VariableName[NumOff+1]) * 0x100)
> + + (UINT16) (CharToUint (VariableName[NumOff+2]) * 0x10)
> + + (UINT16) (CharToUint (VariableName[NumOff+3]) * 0x1);
> + }
> + InsertTailList (BdsCommonOptionList, &Option->Link);
> + FreePool (Variable);
> + return Option;
> +}
> +
> +/**
> + Process BootOrder, or DriverOrder variables, by calling
> + BdsLibVariableToOption () for each UINT16 in the variables.
> +
> + @param BdsCommonOptionList The header of the option list base on
> variable
> + VariableName
> + @param VariableName EFI Variable name indicate the BootOrder or
> + DriverOrder
> +
> + @retval EFI_SUCCESS Success create the boot option or driver option
> + list
> + @retval EFI_OUT_OF_RESOURCES Failed to get the boot option or driver
> option list
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibBuildOptionFromVar (
> + IN LIST_ENTRY *BdsCommonOptionList,
> + IN CHAR16 *VariableName
> + )
> +{
> + UINT16 *OptionOrder;
> + UINTN OptionOrderSize;
> + UINTN Index;
> + BDS_COMMON_OPTION *Option;
> + CHAR16 OptionName[20];
> +
> + //
> + // Zero Buffer in order to get all BOOT#### variables
> + //
> + ZeroMem (OptionName, sizeof (OptionName));
> +
> + //
> + // Read the BootOrder, or DriverOrder variable.
> + //
> + OptionOrder = BdsLibGetVariableAndSize (
> + VariableName,
> + &gEfiGlobalVariableGuid,
> + &OptionOrderSize
> + );
> + if (OptionOrder == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + for (Index = 0; Index < OptionOrderSize / sizeof (UINT16); Index++) {
> + if (*VariableName == 'B') {
> + UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x",
> OptionOrder[Index]);
> + } else {
> + UnicodeSPrint (OptionName, sizeof (OptionName), L"Driver%04x",
> OptionOrder[Index]);
> + }
> +
> + Option = BdsLibVariableToOption (BdsCommonOptionList,
> OptionName);
> + if (Option != NULL) {
> + Option->BootCurrent = OptionOrder[Index];
> + }
> + }
> +
> + FreePool (OptionOrder);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Get boot mode by looking up configuration table and parsing HOB list
> +
> + @param BootMode Boot mode from PEI handoff HOB.
> +
> + @retval EFI_SUCCESS Successfully get boot mode
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibGetBootMode (
> + OUT EFI_BOOT_MODE *BootMode
> + )
> +{
> + *BootMode = GetBootModeHob ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Read the EFI variable (VendorGuid/Name) and return a dynamically
> allocated
> + buffer, and the size of the buffer. If failure return NULL.
> +
> + @param Name String part of EFI variable name
> + @param VendorGuid GUID part of EFI variable name
> + @param VariableSize Returns the size of the EFI variable that was
> read
> +
> + @return Dynamically allocated memory that contains a copy of
> the EFI variable
> + Caller is responsible freeing the buffer.
> + @retval NULL Variable was not read
> +
> +**/
> +VOID *
> +EFIAPI
> +BdsLibGetVariableAndSize (
> + IN CHAR16 *Name,
> + IN EFI_GUID *VendorGuid,
> + OUT UINTN *VariableSize
> + )
> +{
> + EFI_STATUS Status;
> + UINTN BufferSize;
> + VOID *Buffer;
> +
> + Buffer = NULL;
> +
> + //
> + // Pass in a zero size buffer to find the required buffer size.
> + //
> + BufferSize = 0;
> + Status = gRT->GetVariable (Name, VendorGuid, NULL, &BufferSize,
> Buffer);
> + if (Status == EFI_BUFFER_TOO_SMALL) {
> + //
> + // Allocate the buffer to return
> + //
> + Buffer = AllocateZeroPool (BufferSize);
> + if (Buffer == NULL) {
> + *VariableSize = 0;
> + return NULL;
> + }
> + //
> + // Read variable into the allocated buffer.
> + //
> + Status = gRT->GetVariable (Name, VendorGuid, NULL, &BufferSize,
> Buffer);
> + if (EFI_ERROR (Status)) {
> + FreePool (Buffer);
> + BufferSize = 0;
> + Buffer = NULL;
> + }
> + }
> +
> + ASSERT (((Buffer == NULL) && (BufferSize == 0)) ||
> + ((Buffer != NULL) && (BufferSize != 0))
> + );
> + *VariableSize = BufferSize;
> + return Buffer;
> +}
> +
> +/**
> + Delete the instance in Multi which matches partly with Single instance
> +
> + @param Multi A pointer to a multi-instance device path data
> + structure.
> + @param Single A pointer to a single-instance device path data
> + structure.
> +
> + @return This function will remove the device path instances in Multi which
> partly
> + match with the Single, and return the result device path. If there is no
> + remaining device path as a result, this function will return NULL.
> +
> +**/
> +EFI_DEVICE_PATH_PROTOCOL *
> +EFIAPI
> +BdsLibDelPartMatchInstance (
> + IN EFI_DEVICE_PATH_PROTOCOL *Multi,
> + IN EFI_DEVICE_PATH_PROTOCOL *Single
> + )
> +{
> + EFI_DEVICE_PATH_PROTOCOL *Instance;
> + EFI_DEVICE_PATH_PROTOCOL *NewDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *TempNewDevicePath;
> + UINTN InstanceSize;
> + UINTN SingleDpSize;
> + UINTN Size;
> +
> + NewDevicePath = NULL;
> + TempNewDevicePath = NULL;
> +
> + if (Multi == NULL || Single == NULL) {
> + return Multi;
> + }
> +
> + Instance = GetNextDevicePathInstance (&Multi, &InstanceSize);
> + SingleDpSize = GetDevicePathSize (Single) - END_DEVICE_PATH_LENGTH;
> + InstanceSize -= END_DEVICE_PATH_LENGTH;
> +
> + while (Instance != NULL) {
> +
> + Size = (SingleDpSize < InstanceSize) ? SingleDpSize : InstanceSize;
> +
> + if ((CompareMem (Instance, Single, Size) != 0)) {
> + //
> + // Append the device path instance which does not match with Single
> + //
> + TempNewDevicePath = NewDevicePath;
> + NewDevicePath = AppendDevicePathInstance (NewDevicePath,
> Instance);
> + if (TempNewDevicePath != NULL) {
> + FreePool(TempNewDevicePath);
> + }
> + }
> + FreePool(Instance);
> + Instance = GetNextDevicePathInstance (&Multi, &InstanceSize);
> + InstanceSize -= END_DEVICE_PATH_LENGTH;
> + }
> +
> + return NewDevicePath;
> +}
> +
> +/**
> + Function compares a device path data structure to that of all the nodes of a
> + second device path instance.
> +
> + @param Multi A pointer to a multi-instance device path data
> + structure.
> + @param Single A pointer to a single-instance device path data
> + structure.
> +
> + @retval TRUE If the Single device path is contained within Multi
> device path.
> + @retval FALSE The Single device path is not match within Multi
> device path.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +BdsLibMatchDevicePaths (
> + IN EFI_DEVICE_PATH_PROTOCOL *Multi,
> + IN EFI_DEVICE_PATH_PROTOCOL *Single
> + )
> +{
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePathInst;
> + UINTN Size;
> +
> + if (Multi == NULL || Single == NULL) {
> + return FALSE;
> + }
> +
> + DevicePath = Multi;
> + DevicePathInst = GetNextDevicePathInstance (&DevicePath, &Size);
> +
> + //
> + // Search for the match of 'Single' in 'Multi'
> + //
> + while (DevicePathInst != NULL) {
> + //
> + // If the single device path is found in multiple device paths,
> + // return success
> + //
> + if (CompareMem (Single, DevicePathInst, Size) == 0) {
> + FreePool (DevicePathInst);
> + return TRUE;
> + }
> +
> + FreePool (DevicePathInst);
> + DevicePathInst = GetNextDevicePathInstance (&DevicePath, &Size);
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + This function prints a series of strings.
> +
> + @param ConOut Pointer to
> EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL
> + @param ... A variable argument list containing series of
> + strings, the last string must be NULL.
> +
> + @retval EFI_SUCCESS Success print out the string using ConOut.
> + @retval EFI_STATUS Return the status of the ConOut->OutputString
> ().
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibOutputStrings (
> + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *ConOut,
> + ...
> + )
> +{
> + VA_LIST Args;
> + EFI_STATUS Status;
> + CHAR16 *String;
> +
> + Status = EFI_SUCCESS;
> + VA_START (Args, ConOut);
> +
> + while (!EFI_ERROR (Status)) {
> + //
> + // If String is NULL, then it's the end of the list
> + //
> + String = VA_ARG (Args, CHAR16 *);
> + if (String == NULL) {
> + break;
> + }
> +
> + Status = ConOut->OutputString (ConOut, String);
> +
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + }
> +
> + VA_END(Args);
> + return Status;
> +}
> +
> +//
> +// Following are BDS Lib functions which contain all the code about setup
> browser reset reminder feature.
> +// Setup Browser reset reminder feature is that an reset reminder will be
> given before user leaves the setup browser if
> +// user change any option setting which needs a reset to be effective, and
> the reset will be applied according to the user selection.
> +//
> +
> +
> +/**
> + Enable the setup browser reset reminder feature.
> + This routine is used in platform tip. If the platform policy need the feature,
> use the routine to enable it.
> +
> +**/
> +VOID
> +EFIAPI
> +EnableResetReminderFeature (
> + VOID
> + )
> +{
> + mFeaturerSwitch = TRUE;
> +}
> +
> +
> +/**
> + Disable the setup browser reset reminder feature.
> + This routine is used in platform tip. If the platform policy do not want the
> feature, use the routine to disable it.
> +
> +**/
> +VOID
> +EFIAPI
> +DisableResetReminderFeature (
> + VOID
> + )
> +{
> + mFeaturerSwitch = FALSE;
> +}
> +
> +
> +/**
> + Record the info that a reset is required.
> + A module boolean variable is used to record whether a reset is required.
> +
> +**/
> +VOID
> +EFIAPI
> +EnableResetRequired (
> + VOID
> + )
> +{
> + mResetRequired = TRUE;
> +}
> +
> +
> +/**
> + Record the info that no reset is required.
> + A module boolean variable is used to record whether a reset is required.
> +
> +**/
> +VOID
> +EFIAPI
> +DisableResetRequired (
> + VOID
> + )
> +{
> + mResetRequired = FALSE;
> +}
> +
> +
> +/**
> + Check whether platform policy enable the reset reminder feature. The
> default is enabled.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +IsResetReminderFeatureEnable (
> + VOID
> + )
> +{
> + return mFeaturerSwitch;
> +}
> +
> +
> +/**
> + Check if user changed any option setting which needs a system reset to be
> effective.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +IsResetRequired (
> + VOID
> + )
> +{
> + return mResetRequired;
> +}
> +
> +
> +/**
> + Check whether a reset is needed, and finish the reset reminder feature.
> + If a reset is needed, Popup a menu to notice user, and finish the feature
> + according to the user selection.
> +
> +**/
> +VOID
> +EFIAPI
> +SetupResetReminder (
> + VOID
> + )
> +{
> + EFI_INPUT_KEY Key;
> + CHAR16 *StringBuffer1;
> + CHAR16 *StringBuffer2;
> +
> +
> + //
> + //check any reset required change is applied? if yes, reset system
> + //
> + if (IsResetReminderFeatureEnable ()) {
> + if (IsResetRequired ()) {
> +
> + StringBuffer1 = AllocateZeroPool (MAX_STRING_LEN * sizeof (CHAR16));
> + ASSERT (StringBuffer1 != NULL);
> + StringBuffer2 = AllocateZeroPool (MAX_STRING_LEN * sizeof (CHAR16));
> + ASSERT (StringBuffer2 != NULL);
> + StrCpy (StringBuffer1, L"Configuration changed. Reset to apply it Now.");
> + StrCpy (StringBuffer2, L"Press ENTER to reset");
> + //
> + // Popup a menu to notice user
> + //
> + do {
> + CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key,
> StringBuffer1, StringBuffer2, NULL);
> + } while (Key.UnicodeChar != CHAR_CARRIAGE_RETURN);
> +
> + FreePool (StringBuffer1);
> + FreePool (StringBuffer2);
> +
> + gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
> + }
> + }
> +}
> +
> +/**
> + Get the headers (dos, image, optional header) from an image
> +
> + @param Device SimpleFileSystem device handle
> + @param FileName File name for the image
> + @param DosHeader Pointer to dos header
> + @param Hdr The buffer in which to return the PE32, PE32+, or TE
> header.
> +
> + @retval EFI_SUCCESS Successfully get the machine type.
> + @retval EFI_NOT_FOUND The file is not found.
> + @retval EFI_LOAD_ERROR File is not a valid image file.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibGetImageHeader (
> + IN EFI_HANDLE Device,
> + IN CHAR16 *FileName,
> + OUT EFI_IMAGE_DOS_HEADER *DosHeader,
> + OUT EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr
> + )
> +{
> + EFI_STATUS Status;
> + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *Volume;
> + EFI_FILE_HANDLE Root;
> + EFI_FILE_HANDLE ThisFile;
> + UINTN BufferSize;
> + UINT64 FileSize;
> + EFI_FILE_INFO *Info;
> +
> + Root = NULL;
> + ThisFile = NULL;
> + //
> + // Handle the file system interface to the device
> + //
> + Status = gBS->HandleProtocol (
> + Device,
> + &gEfiSimpleFileSystemProtocolGuid,
> + (VOID *) &Volume
> + );
> + if (EFI_ERROR (Status)) {
> + goto Done;
> + }
> +
> + Status = Volume->OpenVolume (
> + Volume,
> + &Root
> + );
> + if (EFI_ERROR (Status)) {
> + Root = NULL;
> + goto Done;
> + }
> + ASSERT (Root != NULL);
> + Status = Root->Open (Root, &ThisFile, FileName, EFI_FILE_MODE_READ, 0);
> + if (EFI_ERROR (Status)) {
> + goto Done;
> + }
> + ASSERT (ThisFile != NULL);
> +
> + //
> + // Get file size
> + //
> + BufferSize = SIZE_OF_EFI_FILE_INFO + 200;
> + do {
> + Info = NULL;
> + Status = gBS->AllocatePool (EfiBootServicesData, BufferSize, (VOID **)
> &Info);
> + if (EFI_ERROR (Status)) {
> + goto Done;
> + }
> + Status = ThisFile->GetInfo (
> + ThisFile,
> + &gEfiFileInfoGuid,
> + &BufferSize,
> + Info
> + );
> + if (!EFI_ERROR (Status)) {
> + break;
> + }
> + if (Status != EFI_BUFFER_TOO_SMALL) {
> + FreePool (Info);
> + goto Done;
> + }
> + FreePool (Info);
> + } while (TRUE);
> +
> + FileSize = Info->FileSize;
> + FreePool (Info);
> +
> + //
> + // Read dos header
> + //
> + BufferSize = sizeof (EFI_IMAGE_DOS_HEADER);
> + Status = ThisFile->Read (ThisFile, &BufferSize, DosHeader);
> + if (EFI_ERROR (Status) ||
> + BufferSize < sizeof (EFI_IMAGE_DOS_HEADER) ||
> + FileSize <= DosHeader->e_lfanew ||
> + DosHeader->e_magic != EFI_IMAGE_DOS_SIGNATURE) {
> + Status = EFI_LOAD_ERROR;
> + goto Done;
> + }
> +
> + //
> + // Move to PE signature
> + //
> + Status = ThisFile->SetPosition (ThisFile, DosHeader->e_lfanew);
> + if (EFI_ERROR (Status)) {
> + Status = EFI_LOAD_ERROR;
> + goto Done;
> + }
> +
> + //
> + // Read and check PE signature
> + //
> + BufferSize = sizeof (EFI_IMAGE_OPTIONAL_HEADER_UNION);
> + Status = ThisFile->Read (ThisFile, &BufferSize, Hdr.Pe32);
> + if (EFI_ERROR (Status) ||
> + BufferSize < sizeof (EFI_IMAGE_OPTIONAL_HEADER_UNION) ||
> + Hdr.Pe32->Signature != EFI_IMAGE_NT_SIGNATURE) {
> + Status = EFI_LOAD_ERROR;
> + goto Done;
> + }
> +
> + //
> + // Check PE32 or PE32+ magic
> + //
> + if (Hdr.Pe32->OptionalHeader.Magic !=
> EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC &&
> + Hdr.Pe32->OptionalHeader.Magic !=
> EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC) {
> + Status = EFI_LOAD_ERROR;
> + goto Done;
> + }
> +
> + Done:
> + if (ThisFile != NULL) {
> + ThisFile->Close (ThisFile);
> + }
> + if (Root != NULL) {
> + Root->Close (Root);
> + }
> + return Status;
> +}
> +
> +/**
> + This routine adjust the memory information for different memory type
> and
> + save them into the variables for next boot.
> +**/
> +VOID
> +BdsSetMemoryTypeInformationVariable (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + EFI_MEMORY_TYPE_INFORMATION *PreviousMemoryTypeInformation;
> + EFI_MEMORY_TYPE_INFORMATION *CurrentMemoryTypeInformation;
> + UINTN VariableSize;
> + UINTN Index;
> + UINTN Index1;
> + UINT32 Previous;
> + UINT32 Current;
> + UINT32 Next;
> + EFI_HOB_GUID_TYPE *GuidHob;
> + BOOLEAN MemoryTypeInformationModified;
> + BOOLEAN MemoryTypeInformationVariableExists;
> + EFI_BOOT_MODE BootMode;
> +
> + MemoryTypeInformationModified = FALSE;
> + MemoryTypeInformationVariableExists = FALSE;
> +
> +
> + BootMode = GetBootModeHob ();
> + //
> + // In BOOT_IN_RECOVERY_MODE, Variable region is not reliable.
> + //
> + if (BootMode == BOOT_IN_RECOVERY_MODE) {
> + return;
> + }
> +
> + //
> + // Only check the the Memory Type Information variable in the boot mode
> + // other than BOOT_WITH_DEFAULT_SETTINGS because the Memory Type
> + // Information is not valid in this boot mode.
> + //
> + if (BootMode != BOOT_WITH_DEFAULT_SETTINGS) {
> + VariableSize = 0;
> + Status = gRT->GetVariable (
> + EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
> + &gEfiMemoryTypeInformationGuid,
> + NULL,
> + &VariableSize,
> + NULL
> + );
> + if (Status == EFI_BUFFER_TOO_SMALL) {
> + MemoryTypeInformationVariableExists = TRUE;
> + }
> + }
> +
> + //
> + // Retrieve the current memory usage statistics. If they are not found,
> then
> + // no adjustments can be made to the Memory Type Information variable.
> + //
> + Status = EfiGetSystemConfigurationTable (
> + &gEfiMemoryTypeInformationGuid,
> + (VOID **) &CurrentMemoryTypeInformation
> + );
> + if (EFI_ERROR (Status) || CurrentMemoryTypeInformation == NULL) {
> + return;
> + }
> +
> + //
> + // Get the Memory Type Information settings from Hob if they exist,
> + // PEI is responsible for getting them from variable and build a Hob to save
> them.
> + // If the previous Memory Type Information is not available, then set
> defaults
> + //
> + GuidHob = GetFirstGuidHob (&gEfiMemoryTypeInformationGuid);
> + if (GuidHob == NULL) {
> + //
> + // If Platform has not built Memory Type Info into the Hob, just return.
> + //
> + return;
> + }
> + PreviousMemoryTypeInformation = GET_GUID_HOB_DATA (GuidHob);
> + VariableSize = GET_GUID_HOB_DATA_SIZE (GuidHob);
> +
> + //
> + // Use a heuristic to adjust the Memory Type Information for the next
> boot
> + //
> + DEBUG ((EFI_D_INFO, "Memory Previous Current Next \n"));
> + DEBUG ((EFI_D_INFO, " Type Pages Pages Pages \n"));
> + DEBUG ((EFI_D_INFO, "====== ======== ======== ========\n"));
> +
> + for (Index = 0; PreviousMemoryTypeInformation[Index].Type !=
> EfiMaxMemoryType; Index++) {
> +
> + for (Index1 = 0; CurrentMemoryTypeInformation[Index1].Type !=
> EfiMaxMemoryType; Index1++) {
> + if (PreviousMemoryTypeInformation[Index].Type ==
> CurrentMemoryTypeInformation[Index1].Type) {
> + break;
> + }
> + }
> + if (CurrentMemoryTypeInformation[Index1].Type ==
> EfiMaxMemoryType) {
> + continue;
> + }
> +
> + //
> + // Previous is the number of pages pre-allocated
> + // Current is the number of pages actually needed
> + //
> + Previous = PreviousMemoryTypeInformation[Index].NumberOfPages;
> + Current = CurrentMemoryTypeInformation[Index1].NumberOfPages;
> + Next = Previous;
> +
> + //
> + // Inconsistent Memory Reserved across bootings may lead to S4 fail
> + // Write next varible to 125% * current when the pre-allocated memory is:
> + // 1. More than 150% of needed memory and boot mode is
> BOOT_WITH_DEFAULT_SETTING
> + // 2. Less than the needed memory
> + //
> + if ((Current + (Current >> 1)) < Previous) {
> + if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) {
> + Next = Current + (Current >> 2);
> + }
> + } else if (Current > Previous) {
> + Next = Current + (Current >> 2);
> + }
> + if (Next > 0 && Next < 4) {
> + Next = 4;
> + }
> +
> + if (Next != Previous) {
> + PreviousMemoryTypeInformation[Index].NumberOfPages = Next;
> + MemoryTypeInformationModified = TRUE;
> + }
> +
> + DEBUG ((EFI_D_INFO, " %02x %08x %08x %08x\n",
> PreviousMemoryTypeInformation[Index].Type, Previous, Current, Next));
> + }
> +
> + //
> + // If any changes were made to the Memory Type Information settings,
> then set the new variable value;
> + // Or create the variable in first boot.
> + //
> + if (MemoryTypeInformationModified
> || !MemoryTypeInformationVariableExists) {
> + Status = SetVariableAndReportStatusCodeOnError (
> + EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
> + &gEfiMemoryTypeInformationGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + VariableSize,
> + PreviousMemoryTypeInformation
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + //
> + // If the Memory Type Information settings have been modified, then
> reset the platform
> + // so the new Memory Type Information setting will be used to
> guarantee that an S4
> + // entry/resume cycle will not fail.
> + //
> + if (MemoryTypeInformationModified && PcdGetBool
> (PcdResetOnMemoryTypeInformationChange)) {
> + DEBUG ((EFI_D_INFO, "Memory Type Information settings change.
> Warm Reset!!!\n"));
> + gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);
> + }
> + } else {
> + DEBUG ((EFI_D_ERROR, "Memory Type Information settings cannot be
> saved. OS S4 may fail!\n"));
> + }
> + }
> +}
> +
> +/**
> + This routine is kept for backward compatibility.
> +**/
> +VOID
> +EFIAPI
> +BdsLibSaveMemoryTypeInformation (
> + VOID
> + )
> +{
> +}
> +
> +
> +/**
> + Identify a user and, if authenticated, returns the current user profile
> handle.
> +
> + @param[out] User Point to user profile handle.
> +
> + @retval EFI_SUCCESS User is successfully identified, or user
> identification
> + is not supported.
> + @retval EFI_ACCESS_DENIED User is not successfully identified
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibUserIdentify (
> + OUT EFI_USER_PROFILE_HANDLE *User
> + )
> +{
> + EFI_STATUS Status;
> + EFI_USER_MANAGER_PROTOCOL *Manager;
> +
> + Status = gBS->LocateProtocol (
> + &gEfiUserManagerProtocolGuid,
> + NULL,
> + (VOID **) &Manager
> + );
> + if (EFI_ERROR (Status)) {
> + return EFI_SUCCESS;
> + }
> +
> + return Manager->Identify (Manager, User);
> +}
> +
> +/**
> + Set the variable and report the error through status code upon failure.
> +
> + @param VariableName A Null-terminated string that is the name of
> the vendor's variable.
> + Each VariableName is unique for each VendorGuid.
> VariableName must
> + contain 1 or more characters. If VariableName is an empty
> string,
> + then EFI_INVALID_PARAMETER is returned.
> + @param VendorGuid A unique identifier for the vendor.
> + @param Attributes Attributes bitmask to set for the variable.
> + @param DataSize The size in bytes of the Data buffer. Unless the
> EFI_VARIABLE_APPEND_WRITE,
> + EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS, or
> +
> EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS attribute is
> set, a size of zero
> + causes the variable to be deleted. When the
> EFI_VARIABLE_APPEND_WRITE attribute is
> + set, then a SetVariable() call with a DataSize of zero will not
> cause any change to
> + the variable value (the timestamp associated with the
> variable may be updated however
> + even if no new data value is provided,see the description
> of the
> + EFI_VARIABLE_AUTHENTICATION_2 descriptor below. In
> this case the DataSize will not
> + be zero since the EFI_VARIABLE_AUTHENTICATION_2
> descriptor will be populated).
> + @param Data The contents for the variable.
> +
> + @retval EFI_SUCCESS The firmware has successfully stored the
> variable and its data as
> + defined by the Attributes.
> + @retval EFI_INVALID_PARAMETER An invalid combination of attribute bits,
> name, and GUID was supplied, or the
> + DataSize exceeds the maximum allowed.
> + @retval EFI_INVALID_PARAMETER VariableName is an empty string.
> + @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold
> the variable and its data.
> + @retval EFI_DEVICE_ERROR The variable could not be retrieved due to
> a hardware error.
> + @retval EFI_WRITE_PROTECTED The variable in question is read-only.
> + @retval EFI_WRITE_PROTECTED The variable in question cannot be
> deleted.
> + @retval EFI_SECURITY_VIOLATION The variable could not be written due
> to EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS
> + or
> EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACESS being set, but
> the AuthInfo
> + does NOT pass the validation check carried out by the
> firmware.
> +
> + @retval EFI_NOT_FOUND The variable trying to be updated or
> deleted was not found.
> +**/
> +EFI_STATUS
> +SetVariableAndReportStatusCodeOnError (
> + IN CHAR16 *VariableName,
> + IN EFI_GUID *VendorGuid,
> + IN UINT32 Attributes,
> + IN UINTN DataSize,
> + IN VOID *Data
> + )
> +{
> + EFI_STATUS Status;
> + EDKII_SET_VARIABLE_STATUS *SetVariableStatus;
> + UINTN NameSize;
> +
> + Status = gRT->SetVariable (
> + VariableName,
> + VendorGuid,
> + Attributes,
> + DataSize,
> + Data
> + );
> + if (EFI_ERROR (Status)) {
> + NameSize = StrSize (VariableName);
> + SetVariableStatus = AllocatePool (sizeof (EDKII_SET_VARIABLE_STATUS) +
> NameSize + DataSize);
> + if (SetVariableStatus != NULL) {
> + CopyGuid (&SetVariableStatus->Guid, VendorGuid);
> + SetVariableStatus->NameSize = NameSize;
> + SetVariableStatus->DataSize = DataSize;
> + SetVariableStatus->SetStatus = Status;
> + SetVariableStatus->Attributes = Attributes;
> + CopyMem (SetVariableStatus + 1, VariableName, NameSize);
> + if ((Data != NULL) && (DataSize != 0)) {
> + CopyMem (((UINT8 *) (SetVariableStatus + 1)) + NameSize, Data,
> DataSize);
> + }
> +
> + REPORT_STATUS_CODE_EX (
> + EFI_ERROR_CODE,
> + PcdGet32 (PcdErrorCodeSetVariable),
> + 0,
> + NULL,
> + &gEdkiiStatusCodeDataTypeVariableGuid,
> + SetVariableStatus,
> + sizeof (EDKII_SET_VARIABLE_STATUS) + NameSize + DataSize
> + );
> +
> + FreePool (SetVariableStatus);
> + }
> + }
> +
> + return Status;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/DevicePath.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/DevicePath.c
> new file mode 100644
> index 0000000000..a0b9da880d
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/DevicePath.c
> @@ -0,0 +1,27 @@
> +/** @file
> + BDS internal function define the default device path string, it can be
> + replaced by platform device path.
> +
> +Copyright (c) 2004 - 2013, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "InternalBdsLib.h"
> +
> +/**
> + This function converts an input device structure to a Unicode string.
> +
> + @param DevPath A pointer to the device path structure.
> +
> + @return A new allocated Unicode string that represents the device path.
> +
> +**/
> +CHAR16 *
> +EFIAPI
> +DevicePathToStr (
> + IN EFI_DEVICE_PATH_PROTOCOL *DevPath
> + )
> +{
> + return ConvertDevicePathToText (DevPath, TRUE, TRUE);
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/GenericBdsLib.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/GenericBdsLib.inf
> new file mode 100644
> index 0000000000..e3c8a6fa27
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/GenericBdsLib.inf
> @@ -0,0 +1,142 @@
> +## @file
> +# General BDS library.
> +#
> +# General BDS defines and produce general interfaces for platform BDS
> driver including:
> +# 1) BDS boot policy interface;
> +# 2) BDS boot device connect interface;
> +# 3) BDS Misc interfaces for mainting boot variable, ouput string, etc.
> +#
> +# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = GenericBdsLib
> + MODULE_UNI_FILE = GenericBdsLib.uni
> + FILE_GUID = e405ec31-ccaa-4dd4-83e8-0aec01703f7e
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = GenericBdsLib|DXE_DRIVER
> DXE_RUNTIME_DRIVER UEFI_APPLICATION
> + CONSTRUCTOR = GenericBdsLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + DevicePath.c
> + BdsConnect.c
> + BdsMisc.c
> + BdsConsole.c
> + BdsBoot.c
> + InternalBdsLib.h
> + String.h
> + String.c
> + GenericBdsStrings.uni
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
> + ShellPkg/ShellPkg.dec
> +
> +[LibraryClasses]
> + DevicePathLib
> + PeCoffGetEntryPointLib
> + BaseLib
> + HobLib
> + UefiRuntimeServicesTableLib
> + DxeServicesTableLib
> + MemoryAllocationLib
> + UefiLib
> + UefiBootServicesTableLib
> + BaseMemoryLib
> + DebugLib
> + PrintLib
> + PcdLib
> + PerformanceLib
> + TimerLib
> + DxeServicesLib
> + HiiLib
> + ReportStatusCodeLib
> + NetLib
> + BmpSupportLib
> +
> +[Guids]
> + ## SOMETIMES_CONSUMES ## HOB # The hob holding memory type
> information
> + ## SOMETIMES_CONSUMES ## SystemTable # The identifier of memory
> type information type in system table
> + ## SOMETIMES_CONSUMES ## Variable:L"MemoryTypeInformation"
> + ## SOMETIMES_PRODUCES ## Variable:L"MemoryTypeInformation"
> + gEfiMemoryTypeInformationGuid
> + ## SOMETIMES_CONSUMES ## Variable:L"BootXXXX" # Boot option
> variable
> + ## SOMETIMES_PRODUCES ## Variable:L"BootXXXX" # Boot option
> variable
> + ## SOMETIMES_CONSUMES ## Variable:L"DriverXXXX" # Driver load
> option.
> + ## SOMETIMES_PRODUCES ## Variable:L"DriverXXXX" # Driver load
> option.
> + ## SOMETIMES_CONSUMES ## Variable:L"BootNext" # Next Boot
> Option
> + ## SOMETIMES_PRODUCES ## Variable:L"BootNext" # Next Boot Option
> + ## SOMETIMES_CONSUMES ## Variable:L"BootOrder" # The boot option
> array
> + ## SOMETIMES_PRODUCES ## Variable:L"BootOrder" # The boot option
> array
> + ## SOMETIMES_CONSUMES ## Variable:L"DriverOrder" # The driver order
> list
> + ## SOMETIMES_CONSUMES ## Variable:L"ConIn" # The device path of
> console in device
> + ## SOMETIMES_PRODUCES ## Variable:L"ConIn" # The device path of
> console in device
> + ## SOMETIMES_CONSUMES ## Variable:L"ConOut" # The device path
> of console out device
> + ## SOMETIMES_PRODUCES ## Variable:L"ConOut" # The device path of
> console out device
> + ## SOMETIMES_CONSUMES ## Variable:L"ErrOut" # The device path of
> error out device
> + ## SOMETIMES_PRODUCES ## Variable:L"ErrOut" # The device path of
> error out device
> + ## SOMETIMES_PRODUCES ## Variable:L"BootCurrent" # The boot option
> of current boot
> + ## SOMETIMES_PRODUCES ## Variable:L"BootNext" # The number of
> next boot option
> + gEfiGlobalVariableGuid
> + gEfiFileInfoGuid ## SOMETIMES_CONSUMES ## GUID
> + gLastEnumLangGuid ## SOMETIMES_PRODUCES ##
> Variable:L"LastEnumLang" # Platform language at last time enumeration.
> + gHdBootDevicePathVariablGuid ## SOMETIMES_PRODUCES ##
> Variable:L"HDDP" # The device path of Boot file on Hard device.
> + gBdsLibStringPackageGuid ## CONSUMES ## HII # HII String
> PackageList Guid
> + ## SOMETIMES_PRODUCES ## Variable:L"LegacyDevOrder"
> + ## SOMETIMES_CONSUMES ## Variable:L"LegacyDevOrder"
> + gEfiLegacyDevOrderVariableGuid
> + gEdkiiStatusCodeDataTypeVariableGuid ## SOMETIMES_CONSUMES
> ## GUID
> + gUefiShellFileGuid
> +
> +[Protocols]
> + gEfiSimpleFileSystemProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiLoadFileProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiSimpleTextOutProtocolGuid ## CONSUMES
> + gEfiPciIoProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiLoadedImageProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiSimpleNetworkProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiDebugPortProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiSimpleTextInProtocolGuid ## CONSUMES
> + gEfiBlockIoProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiFirmwareVolume2ProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiLegacyBiosProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiCpuArchProtocolGuid ## CONSUMES
> + gEfiDevicePathProtocolGuid ## CONSUMES
> + gEfiAcpiS3SaveProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiGraphicsOutputProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiUgaDrawProtocolGuid
> |gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport ##
> SOMETIMES_CONSUMES
> + gEfiOEMBadgingProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiHiiFontProtocolGuid ## CONSUMES
> + gEfiUserManagerProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiUsbIoProtocolGuid ## SOMETIMES_CONSUMES
> + gEfiBootLogoProtocolGuid ## SOMETIMES_CONSUMES
> +
> +[FeaturePcd]
> + gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport ##
> CONSUMES
> + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootlogoOnlyEnable
> ## CONSUMES
> +
> +[Pcd]
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationC
> hange ## SOMETIMES_CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeOsLoaderLoad ##
> SOMETIMES_CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeOsLoaderStart ##
> SOMETIMES_CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdErrorCodeSetVariable ##
> CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdTestKeyUsed ##
> CONSUMES
> +
> +#
> +# [BootMode]
> +# RECOVERY_FULL ## SOMETIMES_CONSUMES # Memory Type
> Information variable
> +#
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/GenericBdsLib.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/GenericBdsLib.uni
> new file mode 100644
> index 0000000000..c853d3409e
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/GenericBdsLib.uni
> @@ -0,0 +1,19 @@
> +// /** @file
> +// General BDS library.
> +//
> +// General BDS defines and produce general interfaces for platform BDS
> driver including:
> +// 1) BDS boot policy interface;
> +// 2) BDS boot device connect interface;
> +// 3) BDS Misc interfaces for mainting boot variable, ouput string, etc.
> +//
> +// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// **/
> +
> +
> +#string STR_MODULE_ABSTRACT #language en-US "General BDS
> library"
> +
> +#string STR_MODULE_DESCRIPTION #language en-US "General BDS
> defines and produces general interfaces for a platform BDS driver including: 1)
> BDS boot policy interface; 2) BDS boot device connect interface; 3) BDS Misc
> interfaces for maintaining boot variable, output string, etc."
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/GenericBdsStrings.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/GenericBdsStrings.uni
> new file mode 100644
> index 0000000000..59a75e548b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/GenericBdsStrings.uni
> @@ -0,0 +1,30 @@
> +///** @file
> +//
> +// String definitions for Boot Option description.
> +//
> +// Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//**/
> +
> +/=#
> +
> +#langdef en-US "English"
> +#langdef fr-FR "Français"
> +
> +#string STR_DESCRIPTION_FLOPPY #language en-US "EFI Floppy"
> + #language fr-FR "fr-FR: EFI Floppy"
> +#string STR_DESCRIPTION_CD_DVD #language en-US "EFI
> DVD/CDROM"
> + #language fr-FR "fr-FR: EFI DVD/CDROM"
> +#string STR_DESCRIPTION_HARDDRIVE #language en-US "EFI Hard Drive"
> + #language fr-FR "fr-FR: EFI Hard Drive"
> +#string STR_DESCRIPTION_USB #language en-US "EFI USB Device"
> + #language fr-FR "fr-FR: EFI USB Device"
> +#string STR_DESCRIPTION_SCSI #language en-US "EFI SCSI Device"
> + #language fr-FR "fr-FR: EFI SCSI Device"
> +#string STR_DESCRIPTION_MISC #language en-US "EFI Misc Device"
> + #language fr-FR "fr-FR: EFI Misc Device"
> +#string STR_DESCRIPTION_NETWORK #language en-US "EFI Network "
> + #language fr-FR "fr-FR: EFI Network "
> +#string STR_DESCRIPTION_NON_BLOCK #language en-US "EFI Non-Block
> Boot Device"
> + #language fr-FR "fr-FR: EFI Non-Block Boot Device"
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/InternalBdsLib.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/InternalBdsLib.h
> new file mode 100644
> index 0000000000..025f06572b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/InternalBdsLib.h
> @@ -0,0 +1,173 @@
> +/** @file
> + BDS library definition, include the file and data structure
> +
> +Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _INTERNAL_BDS_LIB_H_
> +#define _INTERNAL_BDS_LIB_H_
> +
> +#include <FrameworkDxe.h>
> +
> +#include <IndustryStandard/Pci.h>
> +#include <IndustryStandard/PeImage.h>
> +
> +#include <Protocol/BlockIo.h>
> +#include <Protocol/LoadedImage.h>
> +#include <Protocol/Cpu.h>
> +#include <Protocol/SimpleFileSystem.h>
> +#include <Protocol/LoadFile.h>
> +#include <Protocol/DebugPort.h>
> +#include <Protocol/DevicePath.h>
> +#include <Protocol/SimpleTextIn.h>
> +#include <Protocol/LegacyBios.h>
> +#include <Protocol/SimpleTextOut.h>
> +#include <Protocol/SimpleNetwork.h>
> +#include <Protocol/FirmwareVolume2.h>
> +#include <Protocol/PciIo.h>
> +#include <Protocol/AcpiS3Save.h>
> +#include <Protocol/OEMBadging.h>
> +#include <Protocol/GraphicsOutput.h>
> +#include <Protocol/UgaDraw.h>
> +#include <Protocol/HiiFont.h>
> +#include <Protocol/HiiImage.h>
> +#include <Protocol/UsbIo.h>
> +#include <Protocol/BootLogo.h>
> +
> +#include <Guid/MemoryTypeInformation.h>
> +#include <Guid/FileInfo.h>
> +#include <Guid/GlobalVariable.h>
> +#include <Guid/PcAnsi.h>
> +#include <Guid/BdsLibHii.h>
> +#include <Guid/HdBootVariable.h>
> +#include <Guid/LastEnumLang.h>
> +#include <Guid/LegacyDevOrder.h>
> +#include <Guid/StatusCodeDataTypeVariable.h>
> +
> +#include <Library/PrintLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/DxeServicesTableLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/PerformanceLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PeCoffGetEntryPointLib.h>
> +#include <Library/GenericBdsLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DxeServicesLib.h>
> +#include <Library/ReportStatusCodeLib.h>
> +#include <Library/BmpSupportLib.h>
> +
> +#if !defined (EFI_REMOVABLE_MEDIA_FILE_NAME)
> + #if defined (MDE_CPU_EBC)
> + //
> + // Uefi specification only defines the default boot file name for IA32,
> X64
> + // and IPF processor, so need define boot file name for EBC architecture
> here.
> + //
> + #define EFI_REMOVABLE_MEDIA_FILE_NAME
> L"\\EFI\\BOOT\\BOOTEBC.EFI"
> + #else
> + #error "Can not determine the default boot file name for unknown
> processor type!"
> + #endif
> +#endif
> +
> +/**
> + Get the headers (dos, image, optional header) from an image
> +
> + @param Device SimpleFileSystem device handle
> + @param FileName File name for the image
> + @param DosHeader Pointer to dos header
> + @param Hdr The buffer in which to return the PE32, PE32+, or TE
> header.
> +
> + @retval EFI_SUCCESS Successfully get the machine type.
> + @retval EFI_NOT_FOUND The file is not found.
> + @retval EFI_LOAD_ERROR File is not a valid image file.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +BdsLibGetImageHeader (
> + IN EFI_HANDLE Device,
> + IN CHAR16 *FileName,
> + OUT EFI_IMAGE_DOS_HEADER *DosHeader,
> + OUT EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr
> + );
> +
> +/**
> + This routine adjust the memory information for different memory type
> and
> + save them into the variables for next boot.
> +**/
> +VOID
> +BdsSetMemoryTypeInformationVariable (
> + VOID
> + );
> +
> +/**
> + Validate the EFI Boot#### or Driver#### variable (VendorGuid/Name)
> +
> + @param Variable Boot#### variable data.
> + @param VariableSize Returns the size of the EFI variable that was
> read
> +
> + @retval TRUE The variable data is correct.
> + @retval FALSE The variable data is corrupted.
> +
> +**/
> +BOOLEAN
> +ValidateOption (
> + UINT8 *Variable,
> + UINTN VariableSize
> + );
> +
> +/**
> + Set the variable and report the error through status code upon failure.
> +
> + @param VariableName A Null-terminated string that is the name of
> the vendor's variable.
> + Each VariableName is unique for each VendorGuid.
> VariableName must
> + contain 1 or more characters. If VariableName is an empty
> string,
> + then EFI_INVALID_PARAMETER is returned.
> + @param VendorGuid A unique identifier for the vendor.
> + @param Attributes Attributes bitmask to set for the variable.
> + @param DataSize The size in bytes of the Data buffer. Unless the
> EFI_VARIABLE_APPEND_WRITE,
> + EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS, or
> +
> EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS attribute is
> set, a size of zero
> + causes the variable to be deleted. When the
> EFI_VARIABLE_APPEND_WRITE attribute is
> + set, then a SetVariable() call with a DataSize of zero will not
> cause any change to
> + the variable value (the timestamp associated with the
> variable may be updated however
> + even if no new data value is provided,see the description
> of the
> + EFI_VARIABLE_AUTHENTICATION_2 descriptor below. In
> this case the DataSize will not
> + be zero since the EFI_VARIABLE_AUTHENTICATION_2
> descriptor will be populated).
> + @param Data The contents for the variable.
> +
> + @retval EFI_SUCCESS The firmware has successfully stored the
> variable and its data as
> + defined by the Attributes.
> + @retval EFI_INVALID_PARAMETER An invalid combination of attribute bits,
> name, and GUID was supplied, or the
> + DataSize exceeds the maximum allowed.
> + @retval EFI_INVALID_PARAMETER VariableName is an empty string.
> + @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold
> the variable and its data.
> + @retval EFI_DEVICE_ERROR The variable could not be retrieved due to
> a hardware error.
> + @retval EFI_WRITE_PROTECTED The variable in question is read-only.
> + @retval EFI_WRITE_PROTECTED The variable in question cannot be
> deleted.
> + @retval EFI_SECURITY_VIOLATION The variable could not be written due
> to EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS
> + or
> EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACESS being set, but
> the AuthInfo
> + does NOT pass the validation check carried out by the
> firmware.
> +
> + @retval EFI_NOT_FOUND The variable trying to be updated or
> deleted was not found.
> +**/
> +EFI_STATUS
> +SetVariableAndReportStatusCodeOnError (
> + IN CHAR16 *VariableName,
> + IN EFI_GUID *VendorGuid,
> + IN UINT32 Attributes,
> + IN UINTN DataSize,
> + IN VOID *Data
> + );
> +
> +#endif // _BDS_LIB_H_
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/String.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/String.c
> new file mode 100644
> index 0000000000..f36860d5a1
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/String.c
> @@ -0,0 +1,26 @@
> +/** @file
> + String support
> +
> +Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#include "String.h"
> +
> +/**
> + Get string by string id from HII Interface
> +
> +
> + @param Id String ID.
> +
> + @retval CHAR16 * String from ID.
> + @retval NULL If error occurs.
> +
> +**/
> +CHAR16 *
> +BdsLibGetStringById (
> + IN EFI_STRING_ID Id
> + )
> +{
> + return HiiGetString (gBdsLibStringPackHandle, Id, NULL);
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/String.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/String.h
> new file mode 100644
> index 0000000000..53cabe64a9
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Li
> brary/GenericBdsLib/String.h
> @@ -0,0 +1,42 @@
> +/** @file
> + String support
> +
> +Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _STRING_H_
> +#define _STRING_H_
> +
> +#include <Library/HiiLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +extern EFI_HII_HANDLE gBdsLibStringPackHandle;
> +
> +//
> +// This is the VFR compiler generated header file which defines the
> +// string identifiers.
> +//
> +
> +extern UINT8 GenericBdsLibStrings[];
> +
> +/**
> + Get string by string id from HII Interface
> +
> +
> + @param Id String ID.
> +
> + @retval CHAR16 * String from ID.
> + @retval NULL If error occurs.
> +
> +**/
> +CHAR16 *
> +BdsLibGetStringById (
> + IN EFI_STRING_ID Id
> + );
> +
> +#endif // _STRING_H_
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/BoardPciPlatform.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/BoardPciPlatform.c
> new file mode 100644
> index 0000000000..0372c175a6
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/BoardPciPlatform.c
> @@ -0,0 +1,55 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + BoardPciPlatform.c
> +
> +Abstract:
> +
> +Revision History:
> +--*/
> +
> +
> +#include "PciPlatform.h"
> +#include "PchRegs.h"
> +#include "VlvAccess.h"
> +
> +#define R_INTEL_LAN_VENDOR_ID 0x00
> +#define V_INTEL_LAN_VENDOR_ID 0x8086 // INTEL 82574 Gbe
> Controller Vendor ID
> +#define R_INTEL_LAN_DEVICE_ID 0x02
> +#define V_INTEL_LAN_DEVICE_ID 0x153E // INTEL 82574 Gbe
> Controller Device ID
> +
> +//
> +// Global variables for Option ROMs
> +//
> +
> +#define ONBOARD_VIDEO_OPTION_ROM_FILE_GUID \
> +{ 0xF2FE1FAA, 0xF04A, 0x4ba1, 0xAE, 0x73, 0xD1, 0x84, 0x6A, 0x6C, 0xD6,
> 0xD8 }
> +
> +#define PXE_UNDI_OPTION_ROM_INTELPXE_GUID \
> +{0x49F2C48B, 0x4D8E, 0x4238, 0x8D, 0x82, 0x9B, 0x27, 0xF4, 0x38, 0x44, 0xB0}
> +
> +#define SATA_AHCI_ROM_GUID \
> + {0x592bfc62, 0xd817, 0x4d1a, 0x86, 0xf8, 0x33, 0x33, 0x4c, 0x9e, 0x90, 0xd8}
> +
> +#define NULL_ROM_FILE_GUID \
> +{ 0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
> +
> +PCI_OPTION_ROM_TABLE mPciOptionRomTable[] = {
> + { ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, 0, 0, 0x02, 0, IGD_VID,
> IGD_DID_VLV_A0, 0},
> + { ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, 0, 0, 0x02, 0, IGD_VID,
> IGD_DID, 0}, // Desktop/Mobile IGD
> + { ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, 0, 0, 0x02, 0, IGD_VID,
> IGD_DID_II, 0}, // Desktop/Mobile IGD
> + { ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, 0, 0, 0x02, 0, IGD_VID,
> IGD_DID_QS, 0},
> + { NULL_ROM_FILE_GUID, 0, 0, 0, 0, 0xffff, 0xffff, 0}
> +};
> +
> +UINTN mSizeOptionRomTable =
> sizeof(mPciOptionRomTable)/sizeof(PCI_OPTION_ROM_TABLE);
> +
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c
> new file mode 100644
> index 0000000000..b135e2646c
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c
> @@ -0,0 +1,367 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + PciPlatform.c
> +
> +Abstract:
> +--*/
> +
> +
> +#include "PciPlatform.h"
> +#include "PchRegs.h"
> +#include "PchAccess.h"
> +#include "VlvCommonDefinitions.h"
> +#include "PlatformBootMode.h"
> +
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Protocol/CpuIo.h>
> +#include <Protocol/PciIo.h>
> +#include <Guid/SetupVariable.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include "SetupMode.h"
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Library/DebugLib.h>
> +#include <Protocol/FirmwareVolume2.h>
> +#include <Library/HobLib.h>
> +#include <IndustryStandard/Pci22.h>
> +
> +extern PCI_OPTION_ROM_TABLE mPciOptionRomTable[];
> +extern UINTN mSizeOptionRomTable;
> +
> +EFI_PCI_PLATFORM_PROTOCOL mPciPlatform = {
> + PhaseNotify,
> + PlatformPrepController,
> + GetPlatformPolicy,
> + GetPciRom
> +};
> +
> +EFI_HANDLE mPciPlatformHandle = NULL;
> +
> +
> +SYSTEM_CONFIGURATION mSystemConfiguration;
> +
> +EFI_STATUS
> +GetRawImage (
> + IN EFI_GUID *NameGuid,
> + IN OUT VOID **Buffer,
> + IN OUT UINTN *Size
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE *HandleBuffer;
> + UINTN HandleCount;
> + UINTN Index;
> + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
> + UINT32 AuthenticationStatus;
> +
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiFirmwareVolume2ProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> + if (EFI_ERROR (Status) || HandleCount == 0) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // Find desired image in all Fvs
> + //
> + for (Index = 0; Index < HandleCount; Index++) {
> + Status = gBS->HandleProtocol(
> + HandleBuffer[Index],
> + &gEfiFirmwareVolume2ProtocolGuid,
> + (VOID **) &Fv
> + );
> +
> + if ( EFI_ERROR ( Status ) ) {
> + return EFI_LOAD_ERROR;
> + }
> +
> + //
> + // Try a raw file
> + //
> + *Buffer = NULL;
> + *Size = 0;
> + Status = Fv->ReadSection (
> + Fv,
> + NameGuid,
> + EFI_SECTION_RAW,
> + 0,
> + Buffer,
> + Size,
> + &AuthenticationStatus
> + );
> +
> + if ( !EFI_ERROR ( Status )) {
> + break;
> + }
> + }
> +
> + if ( Index >= HandleCount ) {
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +PhaseNotify (
> + IN EFI_PCI_PLATFORM_PROTOCOL *This,
> + IN EFI_HANDLE HostBridge,
> + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,
> + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
> + )
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformPrepController (
> + IN EFI_PCI_PLATFORM_PROTOCOL *This,
> + IN EFI_HANDLE HostBridge,
> + IN EFI_HANDLE RootBridge,
> + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
> + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,
> + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
> + )
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +GetPlatformPolicy (
> + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
> + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy
> + )
> +{
> + *PciPolicy = EFI_RESERVE_VGA_IO_ALIAS;
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + GetPciRom from platform specific location for specific PCI device
> +
> + @param This Protocol instance
> + @param PciHandle Identify the specific PCI devic
> + @param RomImage Returns the ROM Image memory location
> + @param RomSize Returns Rom Image size
> +
> + @retval EFI_SUCCESS
> + @retval EFI_NOT_FOUND
> + @retval EFI_OUT_OF_RESOURCES
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetPciRom (
> + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
> + IN EFI_HANDLE PciHandle,
> + OUT VOID **RomImage,
> + OUT UINTN *RomSize
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PCI_IO_PROTOCOL *PciIo;
> + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
> + UINTN Segment;
> + UINTN Bus;
> + UINTN Device;
> + UINTN Function;
> + UINT16 VendorId;
> + UINT16 DeviceId;
> + UINT16 DeviceClass;
> + UINTN TableIndex;
> + UINT8 Data8;
> + BOOLEAN MfgMode;
> + EFI_PLATFORM_SETUP_ID *BootModeBuffer;
> +
> + EFI_PEI_HOB_POINTERS GuidHob;
> +
> + MfgMode = FALSE;
> +
> +//
> +// Check if system is in manufacturing mode.
> +//
> + GuidHob.Raw = GetHobList ();
> + if (GuidHob.Raw == NULL) {
> + return EFI_NOT_FOUND;
> + }
> +
> + if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformBootModeGuid,
> GuidHob.Raw)) != NULL) {
> + BootModeBuffer = GET_GUID_HOB_DATA (GuidHob.Guid);
> + if (!CompareMem (&BootModeBuffer->SetupName,
> MANUFACTURE_SETUP_NAME,
> + StrSize (MANUFACTURE_SETUP_NAME)))
> + {
> + //
> + // System is in manufacturing mode.
> + //
> + MfgMode = TRUE;
> + }
> + }
> +
> + Status = gBS->HandleProtocol (
> + PciHandle,
> + &gEfiPciIoProtocolGuid,
> + (void **)&PciIo
> + );
> + if (EFI_ERROR (Status)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + Status = gBS->LocateProtocol (
> + &gEfiPciRootBridgeIoProtocolGuid,
> + NULL,
> + (void **)&PciRootBridgeIo
> + );
> +
> + if (EFI_ERROR (Status)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 0x0A, 1, &DeviceClass);
> +
> + PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Function);
> +
> + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 0, 1, &VendorId);
> +
> + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 2, 1, &DeviceId);
> +
> + //
> + // WA for PCIe SATA card (SYBA SY-PEX400-40)
> + //
> + if ((VendorId == 0x1B21) && (DeviceId == 0x0612)) {
> + Data8 = 0x07;
> + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 4, 1, &Data8);
> + }
> +
> + //
> + // Do not run RAID or AHCI Option ROM if IDE
> + //
> + if ( (DeviceClass == ((PCI_CLASS_MASS_STORAGE << 8 ) |
> PCI_CLASS_MASS_STORAGE_IDE)) ) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // Run PXE ROM only if Boot network is enabled and not in MFG mode
> + //
> + if (DeviceClass == ((PCI_CLASS_NETWORK << 8 ) |
> PCI_CLASS_NETWORK_ETHERNET)) {
> + if (((mSystemConfiguration.BootNetwork == 0) && (MfgMode ==
> FALSE )) || (mSystemConfiguration.FastBoot == 1)) {
> + return EFI_NOT_FOUND;
> + }
> + }
> +
> + //
> + // Loop through table of Onboard option rom descriptions
> + //
> + for (TableIndex = 0; mPciOptionRomTable[TableIndex].VendorId != 0xffff;
> TableIndex++) {
> +
> + //
> + // See if the PCI device specified by PciHandle matches at device in
> mPciOptionRomTable
> + //
> + if (VendorId != mPciOptionRomTable[TableIndex].VendorId ||
> + DeviceId != mPciOptionRomTable[TableIndex].DeviceId ||
> + ((DeviceClass == ((PCI_CLASS_NETWORK << 8 ) |
> PCI_CLASS_NETWORK_ETHERNET)) &&
> + (mPciOptionRomTable[TableIndex].Flag !=
> mSystemConfiguration.BootNetwork)) ) {
> + continue;
> + }
> +
> + Status = GetRawImage(
> + &mPciOptionRomTable[TableIndex].FileName,
> + RomImage,
> + RomSize
> + );
> +
> + if ((VendorId == IGD_VID) && (DeviceId == IGD_DID_VLV_A0)) {
> + *(UINT16 *)(((UINTN) *RomImage) + OPROM_DID_OFFSET) =
> IGD_DID_VLV_A0;
> + }
> +
> + if ((VendorId == IGD_VID) && (DeviceId == IGD_DID_II)) {
> + *(UINT16 *)(((UINTN) *RomImage) + OPROM_DID_OFFSET) =
> IGD_DID_II;
> + }
> +
> + if ((VendorId == IGD_VID) && (DeviceId == IGD_DID_0BE4)) {
> + *(UINT16 *)(((UINTN) *RomImage) + OPROM_DID_OFFSET) =
> IGD_DID_0BE4;
> + }
> +
> + if ((VendorId == IGD_VID) && (DeviceId == IGD_DID_QS)) {
> + *(UINT16 *)(((UINTN) *RomImage) + OPROM_DID_OFFSET) =
> IGD_DID_QS;
> + }
> +
> +
> + if (EFI_ERROR (Status)) {
> + continue;
> + }
> + return EFI_SUCCESS;
> + }
> +
> + return EFI_NOT_FOUND;
> +}
> +
> +/**
> +
> + @param (Standard EFI Image entry - EFI_IMAGE_ENTRY_POINT)
> +
> + @retval EFI_STATUS
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PciPlatformDriverEntry (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + UINTN VarSize;
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"Setup",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + //
> + // Install on a new handle
> + //
> + Status = gBS->InstallProtocolInterface (
> + &mPciPlatformHandle,
> + &gEfiPciPlatformProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + &mPciPlatform
> + );
> +
> + return Status;
> +}
> +
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.h
> new file mode 100644
> index 0000000000..cd846eae75
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.h
> @@ -0,0 +1,83 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + PciPlatform.h
> +
> +Abstract:
> +
> +--*/
> +#ifndef PCI_PLATFORM_H_
> +#define PCI_PLATFORM_H_
> +
> +
> +#include <PiDxe.h>
> +#include "Platform.h"
> +
> +//
> +// Produced Protocols
> +//
> +#include <Protocol/PciPlatform.h>
> +
> +#define IGD_DID_II 0x0BE1
> +#define IGD_DID_0BE4 0x0BE4
> +#define IGD_DID_VLV_A0 0x0F31
> +#define OPROM_DID_OFFSET 0x46
> +
> +typedef struct {
> + EFI_GUID FileName;
> + UINTN Segment;
> + UINTN Bus;
> + UINTN Device;
> + UINTN Function;
> + UINT16 VendorId;
> + UINT16 DeviceId;
> + UINT8 Flag;
> +} PCI_OPTION_ROM_TABLE;
> +
> +EFI_STATUS
> +EFIAPI
> +PhaseNotify (
> + IN EFI_PCI_PLATFORM_PROTOCOL *This,
> + IN EFI_HANDLE HostBridge,
> + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,
> + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
> + );
> +
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformPrepController (
> + IN EFI_PCI_PLATFORM_PROTOCOL *This,
> + IN EFI_HANDLE HostBridge,
> + IN EFI_HANDLE RootBridge,
> + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
> + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,
> + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +GetPlatformPolicy (
> + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
> + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +GetPciRom (
> + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
> + IN EFI_HANDLE PciHandle,
> + OUT VOID **RomImage,
> + OUT UINTN *RomSize
> + );
> +
> +#endif
> +
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf
> new file mode 100644
> index 0000000000..a0837917d8
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf
> @@ -0,0 +1,65 @@
> +#/*++
> +#
> +# Copyright (c) 2003 - 2018, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +
> +#
> +# Module Name:
> +#
> +# PciPlatform.inf
> +#
> +# Abstract:
> +#
> +# Component description file for PciPlatform module.
> +#
> +--*/
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PciPlatform
> + FILE_GUID = E2441B64-7EF4-41fe-B3A3-8CAA7F8D3017
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PciPlatformDriverEntry
> +
> +[sources.common]
> + BoardPciPlatform.c
> + PciPlatform.c
> + PciPlatform.h
> +
> +[Guids]
> + gEfiNormalSetupGuid
> + gEfiPlatformBootModeGuid
> +
> +[Protocols]
> + gEfiPciPlatformProtocolGuid
> + gEfiCpuIoProtocolGuid
> + gEfiFirmwareVolume2ProtocolGuid
> + gEfiPciRootBridgeIoProtocolGuid
> + gEfiPciIoProtocolGuid
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> +
> +[LibraryClasses]
> + HobLib
> + UefiDriverEntryPoint
> + BaseLib
> + BaseMemoryLib
> + UefiDriverEntryPoint
> + UefiBootServicesTableLib
> + UefiRuntimeServicesTableLib
> + DxeServicesTableLib
> +
> +[BuildOptions]
> +
> +[Depex]
> + gEfiVariableArchProtocolGuid AND
> + gEfiVariableWriteArchProtocolGuid
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsule.dsc
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsule.dsc
> new file mode 100644
> index 0000000000..524bb74e2a
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsule.dsc
> @@ -0,0 +1,39 @@
> +#/** @file
> +# Platform capsule description.
> +#
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#**/
> +
> +[Defines]
> + PLATFORM_NAME = Vlv2TbltDevicePkg
> + PLATFORM_GUID = EE87F258-6ECC-4415-B1D8-23771BEE26E7
> + PLATFORM_VERSION = 0.1
> + FLASH_DEFINITION = Vlv2TbltDevicePkg/PlatformCapsule.fdf
> + OUTPUT_DIRECTORY = Build/Vlv2TbltDevicePkg
> + SUPPORTED_ARCHITECTURES = IA32|X64
> + BUILD_TARGETS = DEBUG|RELEASE
> + SKUID_IDENTIFIER = DEFAULT
> + POSTBUILD =
> Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/GenCapsuleAll.bat
> +
> +#########################################################
> ##########################################
> +#
> +# Components Section - list of the modules and components that will be
> processed by compilation
> +# tools and the EDK II tools to generate PE32/PE32+/Coff image
> files.
> +#
> +# Note: The EDK II DSC file is not used to specify how compiled binary
> images get placed
> +# into firmware volume images. This section is just a list of modules to
> compile from
> +# source into UEFI-compliant binaries.
> +# It is the FDF file that contains information on combining binary files into
> firmware
> +# volume images, whose concept is beyond UEFI and is described in PI
> specification.
> +# Binary modules do not need to be listed in this section, as they should
> be
> +# specified in the FDF file. For example: Shell binary, FAT binary (Fat.efi),
> +# Logo (Logo.bmp), and etc.
> +# There may also be modules listed in this section that are not required
> in the FDF file,
> +# When a module listed here is excluded from FDF file, then UEFI-
> compliant binary will be
> +# generated for it, but the binary will not be put into any firmware
> volume.
> +#
> +#########################################################
> ##########################################
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsule.fdf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsule.fdf
> new file mode 100644
> index 0000000000..43dd987eaf
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsule.fdf
> @@ -0,0 +1,52 @@
> +## @file
> +# FDF file of Platform capsule.
> +#
> +# Copyright (c) 2016 Intel Corporation.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[FV.SystemFirmwareUpdateCargo]
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> +FILE RAW = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 { #
> PcdEdkiiSystemFirmwareFileGuid
> +
> $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/F
> V/Vlv.ROM
> + }
> +
> +FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { #
> gEdkiiSystemFmpCapsuleConfigFileGuid
> +
> Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpdateConfig/System
> FirmwareUpdateConfig.ini
> + }
> +
> +[FmpPayload.FmpPayloadSystemFirmwareRsa2048]
> +IMAGE_HEADER_INIT_VERSION = 0x02
> +IMAGE_TYPE_ID = 4096267b-da0a-42eb-b5eb-fef31d207cb4 #
> PcdSystemFmpCapsuleImageTypeIdGuid
> +IMAGE_INDEX = 0x1
> +HARDWARE_INSTANCE = 0x0
> +MONOTONIC_COUNT = 0x2
> +CERTIFICATE_GUID = A7717414-C616-4977-9420-844712A735BF #
> RSA2048SHA256
> +
> +FILE DATA =
> $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/F
> V/SYSTEMFIRMWAREUPDATECARGO.Fv
> +
> +[Capsule.Vlv2Rec]
> +CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a #
> gEfiFmpCapsuleGuid
> +CAPSULE_FLAGS = PersistAcrossReset,InitiateReset
> +CAPSULE_HEADER_SIZE = 0x20
> +CAPSULE_HEADER_INIT_VERSION = 0x1
> +
> +FMP_PAYLOAD = FmpPayloadSystemFirmwareRsa2048
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsuleGcc.dsc
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsuleGcc.dsc
> new file mode 100644
> index 0000000000..1856ac349b
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsuleGcc.dsc
> @@ -0,0 +1,38 @@
> +#/** @file
> +# Platform capsule description.
> +#
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + PLATFORM_NAME = Vlv2TbltDevicePkg
> + PLATFORM_GUID = EE87F258-6ECC-4415-B1D8-23771BEE26E7
> + PLATFORM_VERSION = 0.1
> + FLASH_DEFINITION = Vlv2TbltDevicePkg/PlatformCapsuleGcc.fdf
> + OUTPUT_DIRECTORY = Build/Vlv2TbltDevicePkg
> + SUPPORTED_ARCHITECTURES = IA32|X64
> + BUILD_TARGETS = DEBUG|RELEASE
> + SKUID_IDENTIFIER = DEFAULT
> + POSTBUILD =
> Vlv2TbltDevicePkg/Feature/Capsule/GenerateCapsule/GenCapsuleAll.sh
> +
> +#########################################################
> ##########################################
> +#
> +# Components Section - list of the modules and components that will be
> processed by compilation
> +# tools and the EDK II tools to generate PE32/PE32+/Coff image
> files.
> +#
> +# Note: The EDK II DSC file is not used to specify how compiled binary
> images get placed
> +# into firmware volume images. This section is just a list of modules to
> compile from
> +# source into UEFI-compliant binaries.
> +# It is the FDF file that contains information on combining binary files into
> firmware
> +# volume images, whose concept is beyond UEFI and is described in PI
> specification.
> +# Binary modules do not need to be listed in this section, as they should
> be
> +# specified in the FDF file. For example: Shell binary, FAT binary (Fat.efi),
> +# Logo (Logo.bmp), and etc.
> +# There may also be modules listed in this section that are not required
> in the FDF file,
> +# When a module listed here is excluded from FDF file, then UEFI-
> compliant binary will be
> +# generated for it, but the binary will not be put into any firmware
> volume.
> +#
> +#########################################################
> ##########################################
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsuleGcc.fdf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsuleGcc.fdf
> new file mode 100644
> index 0000000000..7917be3d68
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCapsuleGcc.fdf
> @@ -0,0 +1,52 @@
> +## @file
> +# FDF file of Platform capsule.
> +#
> +# Copyright (c) 2016 Intel Corporation.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[FV.SystemFirmwareUpdateCargo]
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> +FILE RAW = AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215 { #
> PcdEdkiiSystemFirmwareFileGuid
> +
> $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/F
> V/Vlv.ROM
> + }
> +
> +FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { #
> gEdkiiSystemFmpCapsuleConfigFileGuid
> +
> Vlv2TbltDevicePkg/Feature/Capsule/SystemFirmwareUpdateConfig/System
> FirmwareUpdateConfigGcc.ini
> + }
> +
> +[FmpPayload.FmpPayloadSystemFirmwareRsa2048]
> +IMAGE_HEADER_INIT_VERSION = 0x02
> +IMAGE_TYPE_ID = 4096267b-da0a-42eb-b5eb-fef31d207cb4 #
> PcdSystemFmpCapsuleImageTypeIdGuid
> +IMAGE_INDEX = 0x1
> +HARDWARE_INSTANCE = 0x0
> +MONOTONIC_COUNT = 0x2
> +CERTIFICATE_GUID = A7717414-C616-4977-9420-844712A735BF #
> RSA2048SHA256
> +
> +FILE DATA =
> $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/F
> V/SYSTEMFIRMWAREUPDATECARGO.Fv
> +
> +[Capsule.Vlv2Rec]
> +CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a #
> gEfiFmpCapsuleGuid
> +CAPSULE_FLAGS = PersistAcrossReset,InitiateReset
> +CAPSULE_HEADER_SIZE = 0x20
> +CAPSULE_HEADER_INIT_VERSION = 0x1
> +
> +FMP_PAYLOAD = FmpPayloadSystemFirmwareRsa2048
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoD
> xe.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoD
> xe.c
> new file mode 100644
> index 0000000000..d35a158181
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoD
> xe.c
> @@ -0,0 +1,60 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + PlatformCpuInfoDxe.c
> +
> +Abstract:
> + Platform Cpu Info driver to public platform related HOB data
> +
> +--*/
> +
> +#include "PlatformCpuInfoDxe.h"
> +
> +CHAR16 EfiPlatformCpuInfoVariable[] = L"PlatformCpuInfo";
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformCpuInfoInit (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PLATFORM_CPU_INFO *PlatformCpuInfoPtr;
> + EFI_PEI_HOB_POINTERS GuidHob;
> +
> + //
> + // Get Platform Cpu Info HOB
> + //
> + GuidHob.Raw = GetHobList ();
> + while ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformCpuInfoGuid,
> GuidHob.Raw)) != NULL) {
> + PlatformCpuInfoPtr = GET_GUID_HOB_DATA (GuidHob.Guid);
> + GuidHob.Raw = GET_NEXT_HOB (GuidHob);
> +
> + //
> + // Write the Platform CPU Info to volatile memory for runtime purposes.
> + // This must be done in its own driver because SetVariable protocol is
> dependent on chipset,
> + // which is dependent on CpuIo, PlatformInfo, and Metronome.
> + //
> + Status = gRT->SetVariable(
> + EfiPlatformCpuInfoVariable,
> + &gEfiVlv2VariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS,
> + sizeof(EFI_PLATFORM_CPU_INFO),
> + PlatformCpuInfoPtr
> + );
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoD
> xe.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoD
> xe.h
> new file mode 100644
> index 0000000000..b13611f4f8
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoD
> xe.h
> @@ -0,0 +1,29 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> + PlatformCpuInfoDxe.h
> +
> +Abstract:
> + Platform Cpu Info Driver.
> +
> +--*/
> +
> +#ifndef _PLATFORM_CPU_INFO_DRIVER_H_
> +#define _PLATFORM_CPU_INFO_DRIVER_H_
> +
> +#include "PiDxe.h"
> +#include "Library/HobLib.h"
> +#include "Guid/GlobalVariable.h"
> +#include "Guid/AcpiVariableCompatibility.h"
> +#include "Guid/PlatformCpuInfo.h"
> +#include "Library/UefiRuntimeServicesTableLib.h"
> +#include <Guid/Vlv2Variable.h>
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoD
> xe.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoD
> xe.inf
> new file mode 100644
> index 0000000000..f2ade1b105
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoD
> xe.inf
> @@ -0,0 +1,55 @@
> +#/*++
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +#
> +# Module Name:
> +#
> +# PlatformCpuInfoDxe.inf
> +#
> +# Abstract:
> +#
> +#
> +--*/
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformCpuInfoDxe
> + FILE_GUID = 025F738B-4EBD-4d55-B728-5F421B601F20
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PlatformCpuInfoInit
> +
> +[Sources]
> + PlatformCpuInfoDxe.c
> + PlatformCpuInfoDxe.h
> +
> +[Guids]
> + gEfiPlatformCpuInfoGuid
> + gEfiVlv2VariableGuid
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2SocBinPkg/Vlv2SocBinPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
> +
> +[LibraryClasses]
> + HobLib
> + UefiRuntimeServicesTableLib
> + UefiDriverEntryPoint
> +
> +[BuildOptions]
> + MSFT:*_*_*_CC_FLAGS = /Od /GL-
> + INTEL:*_*_*_CC_FLAGS = /Od /GL-
> +
> +[Depex]
> + gEfiVariableArchProtocolGuid AND
> + gEfiVariableWriteArchProtocolGuid
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/AzaliaVerbTable.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/AzaliaVerbTable.h
> new file mode 100644
> index 0000000000..331d0cbede
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/AzaliaVerbTable.h
> @@ -0,0 +1,247 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +--*/
> +
> +UINT32 mAzaliaVerbTableData12[] = {
> + //
> + // Audio Verb Table - 0x80862805
> + //
> + // Pin Widget 5 - PORT B
> + 0x20471C10,
> + 0x20471D00,
> + 0x20471E56,
> + 0x20471F18,
> +
> + // Pin Widget 6 - PORT C
> + 0x20571C20,
> + 0x20571D00,
> + 0x20571E56,
> + 0x20571F18,
> +
> + // Pin Widget 7 - PORT D
> + 0x20671C30,
> + 0x20671D00,
> + 0x20671E56,
> + 0x20671F58
> +};
> +
> +
> +PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = {
> + {
> + //
> + // VerbTable:
> + // Revision ID = 0xFF, support all steps
> + // Codec Verb Table For AZALIA
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0880
> + //
> + {
> + 0x10EC0880, // Vendor ID/Device ID
> + 0x0000, // SubSystem ID
> + 0xFF, // Revision ID
> + 0x01, // Front panel support (1=yes, 2=no)
> + 0x000A, // Number of Rear Jacks = 10
> + 0x0002 // Number of Front Jacks = 2
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + },
> + {
> + //
> + // Revision ID >= 0x03
> + // Codec Verb Table For AZALIA
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x434D4980
> + //
> + {
> + 0x434D4980, // Vendor ID/Device ID
> + 0x0000, // SubSystem ID
> + 0x00, // Revision ID
> + 0x01, // Front panel support (1=yes, 2=no)
> + 0x0009, // Number of Rear Jacks = 9
> + 0x0002 // Number of Front Jacks = 2
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + },
> + {
> + //
> + // Lawndale Azalia Audio Codec Verb Table
> + // Revision ID = 0x00
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x11D41984
> + //
> + {
> + 0x11D41984, // Vendor ID/Device ID
> + 0x0000, // SubSystem ID
> + 0x04, // Revision ID
> + 0x01, // Front panel support (1=yes, 2=no)
> + 0x0009, // Number of Rear Jacks = 9
> + 0x0002 // Number of Front Jacks = 2
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + },
> + {
> + //
> + // VerbTable:
> + // Revision ID = 0xFF, support all steps
> + // Codec Verb Table For AZALIA
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x11D41986
> + //
> + {
> + 0x11D41986, // Vendor ID/Device ID
> + 0x0001, // SubSystem ID
> + 0xFF, // Revision ID
> + 0x01, // Front panel support (1=yes, 2=no)
> + 0x000A, // Number of Rear Jacks = 8
> + 0x0002 // Number of Front Jacks = 2
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + },
> + {
> + //
> + // VerbTable: (for Slim River, FFDS3)
> + // Revision ID = 0x00
> + // Codec Verb Table For AZALIA
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0272
> + //
> + {
> + 0x10EC0272, // Vendor ID/Device ID
> + 0x0000, // SubSystem ID
> + 0x00, // Revision ID
> + 0x01, // Front panel support (1=yes, 2=no)
> + 0x000E, // Number of Rear Jacks
> + 0x0002 // Number of Front Jacks
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + },
> + {
> + //
> + // VerbTable: (for Buffalo Trail)
> + // Revision ID = 0x00
> + // Codec Verb Table For AZALIA
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0269
> + //
> + {
> + 0x10EC0269, // Vendor ID/Device ID
> + 0x0000, // SubSystem ID
> + 0x00, // Revision ID
> + 0x01, // Front panel support (1=yes, 2=no)
> + 0x000A, // Number of Rear Jacks
> + 0x0002 // Number of Front Jacks
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + },
> + {
> + //
> + // VerbTable: (RealTek ALC888)
> + // Revision ID = 0xFF
> + // Codec Verb Table For Redfort
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0888
> + //
> + {
> + 0x10EC0888, // Vendor ID/Device ID
> + 0x0000, // SubSystem ID
> + 0xFF, // Revision ID
> + 0x01, // Front panel support (1=yes, 2=no)
> + 0x000B, // Number of Rear Jacks
> + 0x0002 // Number of Front Jacks
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + },
> + {
> + //
> + // VerbTable: (RealTek ALC885)
> + // Revision ID = 0xFF
> + // Codec Verb Table For Redfort
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0885
> + //
> + {
> + 0x10EC0885, // Vendor ID/Device ID
> + 0x0000, // SubSystem ID
> + 0xFF, // Revision ID
> + 0x01, // Front panel support (1=yes, 2=no)
> + 0x000B, // Number of Rear Jacks
> + 0x0002 // Number of Front Jacks
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + },
> + {
> + //
> + // VerbTable: (IDT 92HD81)
> + // Revision ID = 0xFF
> + // Codec Vendor: 0x111D7605
> + //
> + {
> + 0x111D76d5, // Vendor ID/Device ID
> + 0x0000, // SubSystem ID
> + 0xFF, // Revision ID
> + 0x01, // Front panel support (1=yes, 2=no)
> + 0x0008, // Number of Rear Jacks
> + 0x0002 // Number of Front Jacks
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + },
> + {
> + //
> + // VerbTable: (Intel VLV HDMI)
> + // Revision ID = 0xFF
> + // Codec Verb Table For EmeraldLake/LosLunas
> + // Codec Vendor: 0x80862804
> + //
> + {
> + 0x80862882, // Vendor ID/Device ID
> + 0x0000, // SubSystem ID
> + 0xFF, // Revision ID
> + 0x02, // Front panel support (1=yes, 2=no)
> + 0x0003, // Number of Rear Jacks
> + 0x0000 // Number of Front Jacks
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + },
> + {
> + //
> + // VerbTable: (RealTek ALC262)
> + // Revision ID = 0xFF, support all steps
> + // Codec Verb Table For AZALIA
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0262
> + //
> + {
> + 0x10EC0262, // Vendor ID/Device ID
> + 0x0000, // SubSystem ID
> + 0xFF, // Revision ID
> + 0x01, // Front panel support (1=yes, 2=no)
> + 0x000B, // Number of Rear Jacks = 11
> + 0x0002 // Number of Front Jacks = 2
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + },
> + {
> + //
> + // VerbTable: (RealTek ALC282)
> + // Revision ID = 0xff
> + // Codec Verb Table For Azalia on SharkBay-WhiteBluff refresh and
> Haswell ULT FFRD Harris Beach, WTM1, WTM2iCRB
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0282
> + //
> + {
> + 0x10EC0282, // Vendor ID/Device ID
> + 0x0000, // SubSystem ID
> + 0xff, // Revision ID
> + 0x01, // Front panel support (1=yes, 2=no)
> + 0x000C, // Number of Rear Jacks, 0x0010 for Harris Beach, 0x000B for
> WTM1 & WTM2iCRB
> + 0x0002 // Number of Front Jacks
> + },
> + 0 // Pointer to verb table data, need to be inited in the code.
> + }
> +};
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/BoardId.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/BoardId.c
> new file mode 100644
> index 0000000000..7d774568e3
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/BoardId.c
> @@ -0,0 +1,223 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + BoardId.c
> +
> +Abstract:
> +
> + Initialization for the board ID.
> +
> + This code should be common across a chipset family of products.
> +
> +
> +
> +--*/
> +
> +#include "PchRegs.h"
> +#include "PlatformDxe.h"
> +#include <Guid/IdccData.h>
> +#include <Guid/EfiVpdData.h>
> +#include <Protocol/DataHub.h>
> +
> +
> +extern EFI_GUID mPlatformDriverGuid;
> +
> +//
> +// Global module data
> +//
> +UINT32 mBoardId;
> +UINT8 mBoardIdIndex;
> +EFI_BOARD_FEATURES mBoardFeatures;
> +UINT16 mSubsystemDeviceId;
> +UINT16 mSubsystemAudioDeviceId;
> +CHAR8 BoardAaNumber[7];
> +BOOLEAN mFoundAANum;
> +
> +/**
> +
> + Write the boardid variable if it does not already exist.
> +
> +**/
> +VOID
> +InitializeBoardId (
> + )
> +{
> +
> + UINT32 BoardIdBufferSize;
> + EFI_IDCC_BOARD_FORM_FACTOR IdccBoardFormFactor;
> + EFI_DATA_HUB_PROTOCOL *DataHub;
> + EFI_STATUS Status;
> + DMI_DATA DmiDataVariable;
> + UINTN Size;
> +#if defined(DUPLICATE_AA_NO_BASE_ADDR)
> + CHAR8
> DuplicateAaNoAscii[sizeof(DmiDataVariable.BaseBoardVersion)];
> + UINTN iter;
> +#endif
> +#if defined(GPIO_BOARD_ID_SUPPORT) && GPIO_BOARD_ID_SUPPORT !=
> 0
> + UINT8 Data8;
> +#endif
> +
> + //
> + // Update data from the updatable DMI data area
> + //
> + Size = sizeof (DMI_DATA);
> + SetMem(&DmiDataVariable, Size, 0xFF);
> + Status = gRT->GetVariable (
> + DMI_DATA_NAME,
> + &gDmiDataGuid,
> + NULL,
> + &Size,
> + &DmiDataVariable
> + );
> +
> +#if defined(DUPLICATE_AA_NO_BASE_ADDR)
> + //
> + // Get AA# from flash descriptor region
> + //
> + EfiSetMem(DuplicateAaNoAscii, sizeof(DuplicateAaNoAscii), 0xFF);
> + FlashRead((UINT8 *)(UINTN)DUPLICATE_AA_NO_BASE_ADDR,
> + (UINT8 *)DuplicateAaNoAscii,
> + sizeof(DuplicateAaNoAscii));
> +
> + //
> + // Validate AA# read from VPD
> + //
> + for (iter = 0; iter < sizeof(DuplicateAaNoAscii); iter++) {
> + if ((DuplicateAaNoAscii[iter] != 0xFF) &&
> + (DuplicateAaNoAscii[iter] != DmiDataVariable.BaseBoardVersion[iter]))
> {
> + DmiDataVariable.BaseBoardVersion[iter] = DuplicateAaNoAscii[iter];
> + }
> + }
> +
> + Status = EFI_SUCCESS;
> +#endif
> +
> + mFoundAANum = FALSE;
> +
> + //
> + // No variable...no copy
> + //
> + if (EFI_ERROR (Status)) {
> + mBoardIdIndex = 0; // If we can't find the BoardId in the table, use the
> first entry
> + } else {
> + //
> + // This is the correct method of checking for AA#.
> + //
> + CopyMem(&BoardAaNumber,
> ((((UINT8*)&DmiDataVariable.BaseBoardVersion)+2)), 6);
> + BoardAaNumber[6] = 0;
> + for (mBoardIdIndex = 0; mBoardIdIndex < mBoardIdDecodeTableSize;
> mBoardIdIndex++) {
> + if (AsciiStrnCmp(mBoardIdDecodeTable[mBoardIdIndex].AaNumber,
> BoardAaNumber, 6) == 0) {
> + mFoundAANum = TRUE;
> + break;
> + }
> + }
> +
> + if(!mFoundAANum) {
> + //
> + // Add check for AA#'s that is programmed without the AA as leading
> chars.
> + //
> + CopyMem(&BoardAaNumber,
> (((UINT8*)&DmiDataVariable.BaseBoardVersion)), 6);
> + BoardAaNumber[6] = 0;
> + for (mBoardIdIndex = 0; mBoardIdIndex < mBoardIdDecodeTableSize;
> mBoardIdIndex++) {
> + if (AsciiStrnCmp(mBoardIdDecodeTable[mBoardIdIndex].AaNumber,
> BoardAaNumber, 6) == 0) {
> + mFoundAANum = TRUE;
> + break;
> + }
> + }
> + }
> + }
> +
> +#if defined(GPIO_BOARD_ID_SUPPORT) && GPIO_BOARD_ID_SUPPORT !=
> 0
> + //
> + // If we can't find the BoardAA# in the table, find BoardId
> + //
> + if (mFoundAANum != TRUE) {
> + //
> + // BoardID BIT Location
> + // 0 GPIO33 (ICH)
> + // 1 GPIO34 (ICH)
> + //
> + Data8 = IoRead8(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2);
> +
> + //
> + // BoardId[0]
> + //
> + mBoardId = (UINT32)((Data8 >> 1) & BIT0);
> + //
> + // BoardId[1]
> + //
> + mBoardId |= (UINT32)((Data8 >> 1) & BIT1);
> +
> + for (mBoardIdIndex = 0; mBoardIdIndex < mBoardIdDecodeTableSize;
> mBoardIdIndex++) {
> + if (mBoardIdDecodeTable[mBoardIdIndex].BoardId == mBoardId) {
> + break;
> + }
> + }
> +#endif
> + if (mBoardIdIndex == mBoardIdDecodeTableSize) {
> + mBoardIdIndex = 0; // If we can't find the BoardId in the table, use the
> first entry
> + }
> +#if defined(GPIO_BOARD_ID_SUPPORT) && GPIO_BOARD_ID_SUPPORT !=
> 0
> + }
> +#endif
> +
> + mBoardFeatures = mBoardIdDecodeTable[mBoardIdIndex].Features;
> + mSubsystemDeviceId =
> mBoardIdDecodeTable[mBoardIdIndex].SubsystemDeviceId;
> + mSubsystemAudioDeviceId =
> mBoardIdDecodeTable[mBoardIdIndex].AudioSubsystemDeviceId;
> +
> + //
> + // Set the BoardFeatures variable
> + //
> + BoardIdBufferSize = sizeof (mBoardFeatures);
> + gRT->SetVariable (
> + BOARD_FEATURES_NAME,
> + &gEfiBoardFeaturesGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> + EFI_VARIABLE_RUNTIME_ACCESS,
> + BoardIdBufferSize,
> + &mBoardFeatures
> + );
> +
> + //
> + // Get the Data Hub protocol
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiDataHubProtocolGuid,
> + NULL,
> + (VOID **) &DataHub
> + );
> + if (!(EFI_ERROR(Status))) {
> + //
> + // Fill out data
> + //
> + IdccBoardFormFactor.IdccHeader.Type =
> EFI_IDCC_BOARD_FORM_FACTOR_TYPE;
> + IdccBoardFormFactor.IdccHeader.RecordLength =
> sizeof(EFI_IDCC_BOARD_FORM_FACTOR);
> + if ((mBoardFeatures & B_BOARD_FEATURES_FORM_FACTOR_ATX) ||
> (mBoardFeatures & B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX)) {
> + IdccBoardFormFactor.BoardFormFactor = ATX_FORM_FACTOR; // ATX
> + } else {
> + IdccBoardFormFactor.BoardFormFactor = BTX_FORM_FACTOR; // BTX
> + }
> +
> + //
> + // Publish the Board Form Factor value for IDCC
> + //
> + Status = DataHub->LogData (
> + DataHub,
> + &gIdccDataHubGuid,
> + &mPlatformDriverGuid,
> + EFI_DATA_RECORD_CLASS_DATA,
> + &IdccBoardFormFactor,
> + sizeof(EFI_IDCC_BOARD_FORM_FACTOR)
> + );
> + }
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.c
> new file mode 100644
> index 0000000000..d4bf5df690
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.c
> @@ -0,0 +1,129 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + BoardIdDecode.c
> +
> +Abstract:
> +
> +--*/
> +
> +#include "PchRegs.h"
> +#include "PlatformDxe.h"
> +#include "Platform.h"
> +
> +
> +//
> +// Define macros to build data structure signatures from characters.
> +//
> +#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8))
> +#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) |
> (EFI_SIGNATURE_16 (C, D) << 16))
> +#define EFI_SIGNATURE_64(A, B, C, D, E, F, G, H) \
> + (EFI_SIGNATURE_32 (A, B, C, D) | ((UINT64) (EFI_SIGNATURE_32 (E, F, G,
> H)) << 32))
> +
> +BOARD_ID_DECODE mBoardIdDecodeTable[] = {
> + //
> + // Board ID, Board Features bitmap, Subsystem Device ID
> + // This is a dummy entry that has to exist. Do not delete, just make a
> generic entry that fit for product.
> + //
> + {
> + MW_ITX_MPCIE_LVDS_LOEM_AA,
> + MW_ITX_MPCIE_LVDS_LOEM_ID,
> + B_BOARD_FEATURES_FORM_FACTOR_ATX |
> + B_BOARD_FEATURES_SIO_COM2 |
> + B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
> + V_BOARD_FEATURES_SLEEP_S3 |
> + B_BOARD_FEATURES_PS2WAKEFROMS5 |
> + B_BOARD_FEATURES_LVDS |
> + B_BOARD_FEATURES_VERB_TABLE1,
> + V_DEFAULT_SUBSYSTEM_DEVICE_ID,
> + 0xD625,
> + EFI_SIGNATURE_64('M','W','P','N','T','1','0','N')
> + },
> +
> + {
> + MW_ITX_MPCIE_LVDS_CHANNEL_AA,
> + MW_ITX_MPCIE_LVDS_CHANNEL_ID,
> + B_BOARD_FEATURES_FORM_FACTOR_ATX |
> + B_BOARD_FEATURES_SIO_COM2 |
> + B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
> + V_BOARD_FEATURES_SLEEP_S3 |
> + B_BOARD_FEATURES_PS2WAKEFROMS5 |
> + B_BOARD_FEATURES_LVDS |
> + B_BOARD_FEATURES_VERB_TABLE1,
> + V_DEFAULT_SUBSYSTEM_DEVICE_ID,
> + 0xD625,
> + EFI_SIGNATURE_64('M','W','P','N','T','1','0','N')
> + },
> +
> + {
> + MW_ITX_MPCIE_CHANNEL_AA,
> + MW_ITX_MPCIE_CHANNEL_ID,
> + B_BOARD_FEATURES_FORM_FACTOR_ATX |
> + B_BOARD_FEATURES_SIO_COM2 |
> + B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
> + V_BOARD_FEATURES_SLEEP_S3 |
> + B_BOARD_FEATURES_PS2WAKEFROMS5 |
> + B_BOARD_FEATURES_VERB_TABLE1,
> + V_DEFAULT_SUBSYSTEM_DEVICE_ID,
> + 0xD625,
> + EFI_SIGNATURE_64('M','W','P','N','T','1','0','N')
> + },
> +
> + {
> + KT_ITX_MPCIE_LVDS_LOEM_AA,
> + KT_ITX_MPCIE_LVDS_LOEM_ID,
> + B_BOARD_FEATURES_FORM_FACTOR_ATX |
> + B_BOARD_FEATURES_SIO_COM2 |
> + B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
> + V_BOARD_FEATURES_SLEEP_S3 |
> + B_BOARD_FEATURES_PS2WAKEFROMS5 |
> + B_BOARD_FEATURES_LVDS |
> + B_BOARD_FEATURES_VERB_TABLE2,
> + V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT,
> + 0xD626,
> + EFI_SIGNATURE_64('K','T','P','N','T','1','0','N')
> + },
> +
> + {
> + KT_ITX_CHANNEL_AA,
> + KT_ITX_CHANNEL_ID,
> + B_BOARD_FEATURES_FORM_FACTOR_ATX |
> + B_BOARD_FEATURES_SIO_COM2 |
> + B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
> + V_BOARD_FEATURES_SLEEP_S3 |
> + B_BOARD_FEATURES_PS2WAKEFROMS5 |
> + B_BOARD_FEATURES_NO_MINIPCIE |
> + B_BOARD_FEATURES_VERB_TABLE2,
> + V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT,
> + 0xD626,
> + EFI_SIGNATURE_64('K','T','P','N','T','1','0','N')
> + },
> +
> + {
> + KT_ITX_LOEM_AA,
> + KT_ITX_LOEM_ID,
> + B_BOARD_FEATURES_FORM_FACTOR_ATX |
> + B_BOARD_FEATURES_SIO_COM2 |
> + B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
> + V_BOARD_FEATURES_SLEEP_S3 |
> + B_BOARD_FEATURES_PS2WAKEFROMS5 |
> + B_BOARD_FEATURES_NO_MINIPCIE |
> + B_BOARD_FEATURES_VERB_TABLE2,
> + V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT,
> + 0xD626,
> + EFI_SIGNATURE_64('K','T','P','N','T','1','0','N')
> + }
> +};
> +
> +UINTN mBoardIdDecodeTableSize = sizeof (mBoardIdDecodeTable) /
> + sizeof (mBoardIdDecodeTable[0]);
> +
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.h
> new file mode 100644
> index 0000000000..8068768a3a
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.h
> @@ -0,0 +1,61 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + BoardIdDecode.h
> +
> +Abstract:
> +
> + Header file for Platform Initialization Driver.
> +
> +Revision History
> +
> +++*/
> +
> +//
> +// Board AA# and Board ID
> +//
> +#define DEFAULT_BOARD_AA "FFFFFF"
> +
> +//
> +// Mount Washington (LVDS) LOEM
> +//
> +#define MW_ITX_MPCIE_LVDS_LOEM_AA "E93081"
> +#define MW_ITX_MPCIE_LVDS_LOEM_ID 3
> +
> +//
> +// Mount Washington (LVDS) Channel
> +//
> +#define MW_ITX_MPCIE_LVDS_CHANNEL_AA "E93080"
> +#define MW_ITX_MPCIE_LVDS_CHANNEL_ID 3
> +
> +//
> +// Mount Washington Channel
> +//
> +#define MW_ITX_MPCIE_CHANNEL_AA "E93082"
> +#define MW_ITX_MPCIE_CHANNEL_ID 1
> +
> +//
> +// Kinston (mPCIe + LVDS) LOEM
> +//
> +#define KT_ITX_MPCIE_LVDS_LOEM_AA "E93085"
> +#define KT_ITX_MPCIE_LVDS_LOEM_ID 2
> +
> +//
> +// Kinston (LVDS) Channel
> +//
> +#define KT_ITX_CHANNEL_AA "E93083"
> +#define KT_ITX_CHANNEL_ID 0
> +
> +//
> +// Kinston LOEM
> +//
> +#define KT_ITX_LOEM_AA "E93084"
> +#define KT_ITX_LOEM_ID 0
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/ClockControl.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/ClockControl.c
> new file mode 100644
> index 0000000000..1669f0357f
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/ClockControl.c
> @@ -0,0 +1,202 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + ClockControl.c
> +
> +Abstract:
> +
> + Sets platform/SKU specific clock routing information.
> +
> +
> +
> +--*/
> +
> +#include "PlatformDxe.h"
> +#include <Protocol/CK505ClockPlatformInfo.h>
> +
> +//
> +// Default clock routing informtion (All On)
> +//
> +EFI_CLOCK_PLATFORM_INFO mDefClockPolicy = {NULL, 0, NULL, 0, NULL, 0};
> +
> +//
> +// Clock Settings
> +//
> +// Static clock table.
> +// This should be used to define any clock settings that are static
> +// (Always On or Always Off). Dynamic clocks should be set to enabled
> +// in this table.
> +//
> +EFI_STATIC_SIGNALS mAtxStaticClocks[] = {
> + {SrcClk8, Enabled, All},
> + {SrcClk7, Enabled, All},
> + {SrcClk6, Enabled, All},
> + {SrcClk5, Enabled, All},
> + {SrcClk4, Enabled, All},
> + {SrcClk3, Enabled, All},
> + {SrcClk2, Enabled, All},
> + {SrcClk1, Enabled, All},
> + {SrcClk0, Enabled, All},
> + {Ref0, Enabled, All},
> + {Dot96, Enabled, All},
> + {Usb48, Enabled, All},
> + {PciClkF5, Enabled, All},
> + {PciClk0, Enabled, All},
> + {PciClk2, Enabled, All},
> + {PciClk3, Enabled, All},
> + {PciClk4, Disabled, All},
> + {Cr_B, EnabledWithSwitch, All},
> +};
> +
> +//
> +// ClockSxInfo Table
> +// This is a list of clocks that need to be set to a known state when the
> +// system enters S4 or S5.
> +//
> +EFI_STATIC_SIGNALS mAtxSxClocks[] = {
> + {SaveClockConfiguration, Disabled, All}
> +};
> +
> +//
> +// ATX settings structure
> +//
> +EFI_CLOCK_PLATFORM_INFO mAtxClockSettings = {
> + mAtxStaticClocks,
> + sizeof(mAtxStaticClocks) / sizeof(mAtxStaticClocks[0]),
> + mAtxSxClocks,
> + sizeof(mAtxSxClocks) / sizeof(mAtxSxClocks[0])
> +};
> +
> +#if defined( RVP_SUPPORT ) && RVP_SUPPORT
> +//
> +// RVP Clock Settings
> +//
> +// Static clock table.
> +// This should be used to define any clock settings that are static
> +// (Always On or Always Off). Dynamic clocks should be set to enabled
> +// in this table.
> +//
> +//UPSD_TBD Check with Jan if any porting required.
> +//
> +EFI_STATIC_SIGNALS mRvpStaticClocks[] = {
> + {SrcClk11, Enabled, All}, // Not used/not present but leave coding
> enabled
> + {SrcClk10, Enabled, All}, // Not used/not present but leave coding
> enabled
> + {SrcClk9, Enabled, All}, // Not used/not present but leave coding
> enabled
> + {SrcClk8, Enabled, All}, // ICHSATAII
> + {SrcClk7, Enabled, All}, // DPL_REFSSCLKIN
> + {SrcClk6, Enabled, All}, // 100M_MCH
> + {SrcClk5, Enabled, All}, // Mini-PCIe //TODO PNV: Need to check ICH
> GPIO38:
> + // 0: turn on; 1: turn off
> + {SrcClk4, Enabled, All}, // ICHSATA
> + {SrcClk3, Enabled, All}, // 100M_ICH
> + {SrcClk2, Enabled, All}, // 100M_LAN
> + {SrcClk1, Enabled, All}, // 25M_LAN
> + {SrcClk0, Enabled, All}, // 96M_DREF
> + {Ref0, Enabled, All},
> + {Dot96, Enabled, All},
> + {Usb48, Enabled, All},
> + {PciClkF5, Enabled, All}, // 33M_ICH
> + {PciClk0, Enabled, All}, // 33M_RISER
> + {PciClk1, Enabled, All}, // 33M_RISER
> + {PciClk2, Enabled, All}, // VDD_Clock
> + {PciClk3, Enabled, All}, // 33M_S1
> + {PciClk4, Enabled, All}, // 33M_PA
> +};
> +
> +//
> +// Dynamic clock table
> +// This is used to determine if a clock should be left on or turned off based
> +// on the presence of a device. The bridge information is used so the bus
> +// number for the device to be detected can be found.
> +//
> +
> +//
> +// ClockSxInfo Table
> +// This is a list of clocks that need to be set to a known state when the
> +// system enters S4 or S5.
> +//
> +EFI_STATIC_SIGNALS mRvpSxClocks[] = {
> + {SaveClockConfiguration, Disabled, All}
> +};
> +
> +//
> +// RVP settings structure
> +//
> +EFI_CLOCK_PLATFORM_INFO mRvpClockSettings = {
> + mRvpStaticClocks,
> + sizeof(mRvpStaticClocks) / sizeof(mRvpStaticClocks[0]),
> + 0, // No clocks will be turned off mRvpDynamicClocks,
> + 0, // No clocks will be turned off sizeof(mRvpDynamicClocks) /
> sizeof(mRvpDynamicClocks[0]),
> + mRvpSxClocks,
> + sizeof(mRvpSxClocks) / sizeof(mRvpSxClocks[0])
> +};
> +#endif
> +
> +VOID
> +InitializeClockRouting(
> + )
> +{
> + EFI_STATUS Status;
> + UINTN BoardIdVarSize;
> + EFI_BOARD_FEATURES BoardIdVar;
> + EFI_CLOCK_PLATFORM_INFO *ClockPolicy;
> + EFI_HANDLE Handle;
> +
> + ClockPolicy = &mDefClockPolicy;
> +
> + //
> + // Do modifications based on board type
> + //
> + BoardIdVarSize = sizeof (EFI_BOARD_FEATURES);
> + Status = gRT->GetVariable (
> + BOARD_FEATURES_NAME,
> + &gEfiBoardFeaturesGuid,
> + NULL,
> + &BoardIdVarSize,
> + &BoardIdVar
> + );
> + if (!EFI_ERROR (Status)) {
> +
> +#if defined( RVP_SUPPORT ) && RVP_SUPPORT
> + if (BoardIdVar & B_BOARD_FEATURES_RVP) {
> + ClockPolicy = &mRvpClockSettings;
> + }
> +#else
> +
> + //
> + // Isolate board type information
> + //
> + BoardIdVar = BoardIdVar & (B_BOARD_FEATURES_FORM_FACTOR_ATX |
> + B_BOARD_FEATURES_FORM_FACTOR_BTX |
> + B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX |
> + B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX);
> +
> + if (BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_ATX ||
> + BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX) {
> + ClockPolicy = &mAtxClockSettings;
> + }
> +
> +#endif
> +
> + }
> +
> + Handle = NULL;
> + Status = gBS->InstallProtocolInterface (
> + &Handle,
> + &gEfiCk505ClockPlatformInfoGuid,
> + EFI_NATIVE_INTERFACE,
> + ClockPolicy
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> +}
> +
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Configuration.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Configuration.h
> new file mode 100644
> index 0000000000..23e03111c9
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Configuration.h
> @@ -0,0 +1,692 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + Configuration.h
> +
> +Abstract:
> +
> + Driver configuration include file
> +
> +
> +--*/
> +
> +#ifndef _CONFIGURATION_H
> +#define _CONFIGURATION_H
> +
> +#define EFI_NON_DEVICE_CLASS 0x00
> +#define EFI_DISK_DEVICE_CLASS 0x01
> +#define EFI_VIDEO_DEVICE_CLASS 0x02
> +#define EFI_NETWORK_DEVICE_CLASS 0x04
> +#define EFI_INPUT_DEVICE_CLASS 0x08
> +#define EFI_ON_BOARD_DEVICE_CLASS 0x10
> +#define EFI_OTHER_DEVICE_CLASS 0x20
> +
> +//
> +// Processor labels
> +//
> +#define PROCESSOR_HT_MODE 0x0100
> +#define PROCESSOR_FSB_MULTIPLIER 0x0101
> +#define PROCESSOR_MULTIPLIER_OVERRIDE_CONTROL 0x0211
> +
> +//
> +// Memory labels
> +//
> +#define MEMORY_SLOT1_SPEED 0x0200
> +#define MEMORY_SLOT2_SPEED 0x0201
> +#define MEMORY_SLOT3_SPEED 0x0202
> +#define MEMORY_SLOT4_SPEED 0x0203
> +#define END_MEMORY_SLOT_SPEED 0x020F
> +#define PERFORMANCE_MEMORY_PROFILE_CONTROL 0x0210
> +#define UCLK_RATIO_CONTROL 0x0212
> +
> +//
> +// Language label
> +//
> +#define FRONT_PAGE_ITEM_LANGUAGE 0x300
> +
> +//
> +// Boot Labels
> +//
> +#define BOOT_DEVICE_PRIORITY_BEGIN 0x0400
> +#define BOOT_DEVICE_PRIORITY_END 0x0401
> +#define BOOT_OPTICAL_DEVICE_BEGIN 0x0410
> +#define BOOT_OPTICAL_DEVICE_END 0x0411
> +#define BOOT_REMOVABLE_DEVICE_BEGIN 0x0420
> +#define BOOT_REMOVABLE_DEVICE_END 0x0421
> +#define BOOT_PXE_DEVICE_BEGIN 0x0430
> +#define BOOT_PXE_DEVICE_END 0x0431
> +#define BOOT_MENU_TYPE_BEGIN 0x0440
> +#define BOOT_MENU_TYPE_END 0x0441
> +#define BOOT_USB_DEVICE_BEGIN 0x0450
> +#define BOOT_USB_DEVICE_END 0x0451
> +#define BOOT_USB_FIRST_BEGIN 0x0460
> +#define BOOT_USB_FIRST_END 0x0461
> +#define BOOT_UEFI_BEGIN 0x0470
> +#define BOOT_UEFI_END 0x0471
> +#define BOOT_USB_UNAVAILABLE_BEGIN 0x0480
> +#define BOOT_USB_UNAVAILABLE_END 0x0481
> +#define BOOT_CD_UNAVAILABLE_BEGIN 0x0490
> +#define BOOT_CD_UNAVAILABLE_END 0x0491
> +#define BOOT_FDD_UNAVAILABLE_BEGIN 0x04A0
> +#define BOOT_FDD_UNAVAILABLE_END 0x04A1
> +#define BOOT_DEVICE_PRIORITY_DEFAULT_BEGIN 0x04B0
> +#define BOOT_DEVICE_PRIORITY_DEFAULT_END 0x04B1
> +#define BOOT_USB_OPT_LABEL_BEGIN 0x04C0
> +#define BOOT_USB_OPT_LABEL_END 0x04C1
> +
> +#define VAR_EQ_ADMIN_NAME 0x0041 // A
> +#define VAR_EQ_ADMIN_DECIMAL_NAME L"65"
> +#define VAR_EQ_VIEW_ONLY_NAME 0x0042 // B
> +#define VAR_EQ_VIEW_ONLY_DECIMAL_NAME L"66"
> +#define VAR_EQ_CONFIG_MODE_NAME 0x0043 // C
> +#define VAR_EQ_CONFIG_MODE_DECIMAL_NAME L"67"
> +#define VAR_EQ_CPU_EE_NAME 0x0045 // E
> +#define VAR_EQ_CPU_EE_DECIMAL_NAME L"69"
> +#define VAR_EQ_FLOPPY_MODE_NAME 0x0046 // F
> +#define VAR_EQ_FLOPPY_MODE_DECIMAL_NAME L"70"
> +#define VAR_EQ_HT_MODE_NAME 0x0048 // H
> +#define VAR_EQ_HT_MODE_DECIMAL_NAME L"72"
> +#define VAR_EQ_AHCI_MODE_NAME 0x0049 // I
> +#define VAR_EQ_AHCI_MODE_DECIMAL_NAME L"73"
> +#define VAR_EQ_CPU_LOCK_NAME 0x004C // L
> +#define VAR_EQ_CPU_LOCK_DECIMAL_NAME L"76"
> +#define VAR_EQ_NX_MODE_NAME 0x004E // N
> +#define VAR_EQ_NX_MODE_DECIMAL_NAME L"78"
> +#define VAR_EQ_RAID_MODE_NAME 0x0052 // R
> +#define VAR_EQ_RAID_MODE_DECIMAL_NAME L"82"
> +#define VAR_EQ_1394_MODE_NAME 0x0054 // T
> +#define VAR_EQ_1394_MODE_DECIMAL_NAME L"84"
> +#define VAR_EQ_USER_NAME 0x0055 // U
> +#define VAR_EQ_USER_DECIMAL_NAME L"85"
> +#define VAR_EQ_VIDEO_MODE_NAME 0x0056 // V
> +#define VAR_EQ_VIDEO_MODE_DECIMAL_NAME L"86"
> +#define VAR_EQ_LEGACY_FP_AUDIO_NAME 0x0057 // W
> +#define VAR_EQ_LEGACY_FP_AUDIO_DECIMAL_NAME L"87"
> +#define VAR_EQ_EM64T_CAPABLE_NAME 0x0058 // X
> +#define VAR_EQ_EM64T_CAPABLE_DECIMAL_NAME L"88"
> +#define VAR_EQ_BOARD_FORMFACTOR_NAME 0x0059 // Y
> +#define VAR_EQ_BOARD_FORMFACTOR_DECIMAL_NAME L"89"
> +#define VAR_EQ_UNCON_CPU_NAME 0x005B // ??
> +#define VAR_EQ_UNCON_CPU_DECIMAL_NAME L"91"
> +#define VAR_EQ_VAR_HIDE_NAME 0x005C // ??
> +#define VAR_EQ_VAR_HIDE_DECIMAL_NAME L"92"
> +#define VAR_EQ_ENERGY_LAKE_NAME 0x005D // ??
> +#define VAR_EQ_ENERGY_LAKE_DECIMAL_NAME L"93"
> +#define VAR_EQ_TPM_MODE_NAME 0x005E // ^
> +#define VAR_EQ_TPM_MODE_DECIMAL_NAME L"94"
> +#define VAR_EQ_DISCRETE_SATA_NAME 0x005F // ??
> +#define VAR_EQ_DISCRETE_SATA_DECIMAL_NAME L"95"
> +#define VAR_EQ_ROEM_SKU_NAME 0x0060 // ??
> +#define VAR_EQ_ROEM_SKU_DECIMAL_NAME L"96"
> +#define VAR_EQ_AMTSOL_MODE_NAME 0x0061 // ??
> +#define VAR_EQ_AMTSOL_MODE_DECIMAL_NAME L"97"
> +#define VAR_EQ_NO_PEG_MODE_NAME 0x0062 // ??
> +#define VAR_EQ_NO_PEG_MODE_DECIMAL_NAME L"98"
> +#define VAR_EQ_SINGLE_PROCESSOR_MODE_NAME 0x0063 // ??
> +#define VAR_EQ_SINGLE_PROCESSOR_MODE_DECIMAL_NAME L"99"
> +#define VAR_EQ_FLOPPY_HIDE_NAME 0x0064 // ??
> +#define VAR_EQ_FLOPPY_HIDE_DECIMAL_NAME L"100"
> +#define VAR_EQ_SERIAL_HIDE_NAME 0x0065 // ??
> +#define VAR_EQ_SERIAL_HIDE_DECIMAL_NAME L"101"
> +#define VAR_EQ_GV3_CAPABLE_NAME 0x0066 // f
> +#define VAR_EQ_GV3_CAPABLE_DECIMAL_NAME L"102"
> +#define VAR_EQ_2_MEMORY_NAME 0x0067 // ??
> +#define VAR_EQ_2_MEMORY_DECIMAL_NAME L"103"
> +#define VAR_EQ_2_SATA_NAME 0x0068 // ??
> +#define VAR_EQ_2_SATA_DECIMAL_NAME L"104"
> +#define VAR_EQ_NEC_SKU_NAME 0x0069 // ??
> +#define VAR_EQ_NEC_SKU_DECIMAL_NAME L"105"
> +#define VAR_EQ_AMT_MODE_NAME 0x006A // ??
> +#define VAR_EQ_AMT_MODE_DECIMAL_NAME L"106"
> +#define VAR_EQ_LCLX_SKU_NAME 0x006B // ??
> +#define VAR_EQ_LCLX_SKU_DECIMAL_NAME L"107"
> +#define VAR_EQ_VT_NAME 0x006C
> +#define VAR_EQ_VT_DECIMAL_NAME L"108"
> +#define VAR_EQ_LT_NAME 0x006D
> +#define VAR_EQ_LT_DECIMAL_NAME L"109"
> +#define VAR_EQ_ITK_BIOS_MOD_NAME 0x006E // ??
> +#define VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME L"110"
> +#define VAR_EQ_HPET_NAME 0x006F
> +#define VAR_EQ_HPET_DECIMAL_NAME L"111"
> +#define VAR_EQ_ADMIN_INSTALLED_NAME 0x0070 // ??
> +#define VAR_EQ_ADMIN_INSTALLED_DECIMAL_NAME L"112"
> +#define VAR_EQ_USER_INSTALLED_NAME 0x0071 // ??
> +#define VAR_EQ_USER_INSTALLED_DECIMAL_NAME L"113"
> +#define VAR_EQ_CPU_CMP_NAME 0x0072
> +#define VAR_EQ_CPU_CMP_DECIMAL_NAME L"114"
> +#define VAR_EQ_LAN_MAC_ADDR_NAME 0x0073 // ??
> +#define VAR_EQ_LAN_MAC_ADDR_DECIMAL_NAME L"115"
> +#define VAR_EQ_PARALLEL_HIDE_NAME 0x0074 // ??
> +#define VAR_EQ_PARALLEL_HIDE_DECIMAL_NAME L"116"
> +#define VAR_EQ_AFSC_SETUP_NAME 0x0075
> +#define VAR_EQ_AFSC_SETUP_DECIMAL_NAME L"117"
> +#define VAR_EQ_MINICARD_MODE_NAME 0x0076 //
> +#define VAR_EQ_MINICARD_MODE_DECIMAL_NAME L"118"
> +#define VAR_EQ_VIDEO_IGD_NAME 0x0077 //
> +#define VAR_EQ_VIDEO_IGD_DECIMAL_NAME L"119"
> +#define VAR_EQ_ALWAYS_ENABLE_LAN_NAME 0x0078 //
> +#define VAR_EQ_ALWAYS_ENABLE_LAN_DECIMAL_NAME L"120"
> +#define VAR_EQ_LEGACY_FREE_NAME 0x0079 //
> +#define VAR_EQ_LEGACY_FREE_DECIMAL_NAME L"121"
> +#define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_NAME
> 0x007A
> +#define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_DECIMAL_NAME
> L"122"
> +#define VAR_EQ_CPU_FSB_NAME 0x007B //
> +#define VAR_EQ_CPU_FSB_DECIMAL_NAME L"123"
> +#define VAR_EQ_SATA0_DEVICE_NAME 0x007C //
> +#define VAR_EQ_SATA0_DVICE_DECIMAL_NAME L"124"
> +#define VAR_EQ_SATA1_DEVICE_NAME 0x007D //
> +#define VAR_EQ_SATA1_DVICE_DECIMAL_NAME L"125"
> +#define VAR_EQ_SATA2_DEVICE_NAME 0x007E //
> +#define VAR_EQ_SATA2_DVICE_DECIMAL_NAME L"126"
> +#define VAR_EQ_SATA3_DEVICE_NAME 0x007F //
> +#define VAR_EQ_SATA3_DVICE_DECIMAL_NAME L"127"
> +#define VAR_EQ_SATA4_DEVICE_NAME 0x0080 //
> +#define VAR_EQ_SATA4_DVICE_DECIMAL_NAME L"128"
> +#define VAR_EQ_SATA5_DEVICE_NAME 0x0081 //
> +#define VAR_EQ_SATA5_DVICE_DECIMAL_NAME L"129"
> +#define VAR_EQ_TPM_STATUS_NAME 0x0082 // To indicate if
> TPM is enabled
> +#define VAR_EQ_TPM_STATUS_DECIMAL_NAME L"130"
> +#define VAR_EQ_HECETA6E_PECI_CPU_NAME 0x0083
> +#define VAR_EQ_HECETA6E_PECI_CPU_DECIMAL_NAME L"131"
> +#define VAR_EQ_USB_2_NAME 0x0084 //
> +#define VAR_EQ_USB_2_DECIMAL_NAME L"132"
> +#define VAR_EQ_RVP_NAME 0x0085 //
> +#define VAR_EQ_RVP_DECIMAL_NAME L"133"
> +#define VAR_EQ_ECIR_NAME 0x0086
> +#define VAR_EQ_ECIR_DECIMAL_NAME L"134"
> +#define VAR_EQ_WAKONS5KB_NAME 0x0087
> +#define VAR_EQ_WAKONS5KB_DECIMAL_NAME L"135"
> +#define VAR_EQ_HDAUDIOLINKBP_NAME 0x0088
> +#define VAR_EQ_HDAUDIOLINKBP_DECIMAL_NAME L"136"
> +#define VAR_EQ_FINGERPRINT_NAME 0x0089
> +#define VAR_EQ_FINGERPRINT_DECIMAL_NAME L"137"
> +#define VAR_EQ_BLUETOOTH_NAME 0x008A
> +#define VAR_EQ_BLUETOOTH_DECIMAL_NAME L"138"
> +#define VAR_EQ_WLAN_NAME 0x008B
> +#define VAR_EQ_WLAN_DECIMAL_NAME L"139"
> +#define VAR_EQ_1_PATA_NAME 0x008C
> +#define VAR_EQ_1_PATA_DECIMAL_NAME L"140"
> +#define VAR_EQ_ACTIVE_PROCESSOR_CORE_NAME 0x008D
> +#define VAR_EQ_ACTIVE_PROCESSOR_CORE_DECIMAL_NAME L"141"
> +#define VAR_EQ_TURBO_MODE_CAP_NAME 0x008E
> +#define VAR_EQ_TURBO_MODE_CAP_DECIMAL_NAME L"142"
> +#define VAR_EQ_XE_MODE_CAP_NAME 0x008F
> +#define VAR_EQ_XE_MODE_CAP_DECIMAL_NAME L"143"
> +#define VAR_EQ_NPI_QPI_VOLTAGE_NAME 0x0090
> +#define VAR_EQ_NPI_QPI_VOLTAGE_DECIMAL_NAME L"144"
> +#define VAR_EQ_PRE_PROD_NON_XE_NAME 0x0091
> +#define VAR_EQ_PRE_PROD_NON_XE_DECIMAL_NAME L"145"
> +#define VAR_EQ_2_C0_MEMORY_NAME 0x0092 // ??
> +#define VAR_EQ_2_C0_MEMORY_DECIMAL_NAME L"146"
> +#define VAR_EQ_LVDS_NAME 0x0093
> +#define VAR_EQ_LVDS_DECIMAL_NAME L"147"
> +#define VAR_EQ_USB_OPTION_SHOW_NAME 0x0094
> +#define VAR_EQ_USB_OPTION_SHOW_DECIMAL_NAME L"148"
> +#define VAR_EQ_HDD_MASTER_INSTALLED_NAME 0x0095
> +#define VAR_EQ_HDD_MASTER_INSTALLED_DECIMAL_NAME L"149"
> +#define VAR_EQ_HDD_USER_INSTALLED_NAME 0x0096
> +#define VAR_EQ_HDD_USER_INSTALLED_DECIMAL_NAME L"150"
> +#define VAR_EQ_PS2_HIDE_NAME 0x0097 // ??
> +#define VAR_EQ_PS2_HIDE_DECIMAL_NAME L"151"
> +#define VAR_EQ_VIDEO_SLOT_NAME 0x0098
> +#define VAR_EQ_VIDEO_SLOT_DECIMAL_NAME L"152"
> +#define VAR_EQ_HDMI_SLOT_NAME 0x0099
> +#define VAR_EQ_HDMI_SLOT_DECIMAL_NAME L"153"
> +#define VAR_EQ_SERIAL2_HIDE_NAME 0x009a
> +#define VAR_EQ_SERIAL2_HIDE_DECIMAL_NAME L"154"
> +
> +
> +#define VAR_EQ_LVDS_WARNING_HIDE_NAME 0x009e
> +#define VAR_EQ_LVDS_WARNING_HIDE_DECIMAL_NAME L"158"
> +
> +
> +#define VAR_EQ_MSATA_HIDE_NAME 0x009f
> +#define VAR_EQ_MSATA_HIDE_DECIMAL_NAME L"159"
> +
> +
> +#define VAR_EQ_PCI_SLOT1_NAME 0x00a0
> +#define VAR_EQ_PCI_SLOT1_DECIMAL_NAME L"160"
> +#define VAR_EQ_PCI_SLOT2_NAME 0x00a1
> +#define VAR_EQ_PCI_SLOT2_DECIMAL_NAME L"161"
> +
> +//
> +// Generic Form Ids
> +//
> +#define ROOT_FORM_ID 1
> +
> +//
> +// Advance Page. Do not have to be sequential but have to be unique
> +//
> +#define CONFIGURATION_ROOT_FORM_ID 2
> +#define BOOT_CONFIGURATION_ID 3
> +#define ONBOARDDEVICE_CONFIGURATION_ID 4
> +#define DRIVE_CONFIGURATION_ID 5
> +#define FLOPPY_CONFIGURATION_ID 6
> +#define EVENT_LOG_CONFIGURATION_ID 7
> +#define VIDEO_CONFIGURATION_ID 8
> +#define USB_CONFIGURATION_ID 9
> +#define HARDWARE_MONITOR_CONFIGURATION_ID 10
> +#define VIEW_EVENT_LOG_CONFIGURATION_ID 11
> +#define MEMORY_OVERRIDE_ID 12
> +#define CHIPSET_CONFIGURATION_ID 13
> +#define BURN_IN_MODE_ID 14
> +#define PCI_EXPRESS_ID 15
> +#define MANAGEMENT_CONFIGURATION_ID 16
> +#define CPU_CONFIGURATION_ID 17
> +#define PCI_CONFIGURATION_ID 18
> +#define SECURITY_CONFIGURATION_ID 19
> +#define ZIP_CONFIGURATION_ID 20
> +#define AFSC_FAN_CONTROL_ID 21
> +#define VFR_FORMID_CSI 22
> +#define VFR_FORMID_MEMORY 23
> +#define VFR_FORMID_IOH 24
> +#define VFR_FORMID_CPU_CSI 25
> +#define VFR_FORMID_IOH_CONFIG 26
> +#define VFR_FORMID_VTD 27
> +#define VFR_FORMID_PCIE_P0 28
> +#define VFR_FORMID_PCIE_P1 29
> +#define VFR_FORMID_PCIE_P2 30
> +#define VFR_FORMID_PCIE_P3 31
> +#define VFR_FORMID_PCIE_P4 32
> +#define VFR_FORMID_PCIE_P5 33
> +#define VFR_FORMID_PCIE_P6 34
> +#define VFR_FORMID_PCIE_P7 35
> +#define VFR_FORMID_PCIE_P8 36
> +#define VFR_FORMID_PCIE_P9 37
> +#define VFR_FORMID_PCIE_P10 38
> +#define VFR_FID_SKT0 39
> +#define VFR_FID_IOH0 40
> +#define VFR_FID_IOH_DEV_HIDE 41
> +#define PROCESSOR_OVERRIDES_FORM_ID 42
> +#define BUS_OVERRIDES_FORM_ID 43
> +#define REF_OVERRIDES_FORM_ID 44
> +#define MEMORY_INFORMATION_ID 45
> +#define LVDS_WARNING_ID 46
> +#define LVDS_CONFIGURATION_ID 47
> +#define PCI_SLOT_CONFIGURATION_ID 48
> +#define HECETA_CONFIGURATION_ID 49
> +#define LVDS_EXPERT_CONFIGURATION_ID 50
> +#define PCI_SLOT_7_ID 51
> +#define PCI_SLOT_6_ID 52
> +#define PCI_SLOT_5_ID 53
> +#define PCI_SLOT_4_ID 54
> +#define PCI_SLOT_3_ID 55
> +#define PCI_SLOT_2_ID 56
> +#define PCI_SLOT_1_ID 57
> +#define BOOT_DISPLAY_ID 58
> +#define CPU_PWR_CONFIGURATION_ID 59
> +
> +#define FSC_CONFIGURATION_ID 60
> +#define FSC_CPU_TEMPERATURE_FORM_ID 61
> +#define FSC_VTT_VOLTAGE_FORM_ID 62
> +#define FSC_FEATURES_CONTROL_ID 63
> +#define FSC_FAN_CONFIGURATION_ID 64
> +#define FSC_PROCESSOR_FAN_CONFIGURATION_ID 65
> +#define FSC_FRONT_FAN_CONFIGURATION_ID 66
> +#define FSC_REAR_FAN_CONFIGURATION_ID 67
> +#define FSC_AUX_FAN_CONFIGURATION_ID 68
> +#define FSC_12_VOLTAGE_FORM_ID 69
> +#define FSC_5_VOLTAGE_FORM_ID 70
> +#define FSC_3P3_VOLTAGE_FORM_ID 71
> +#define FSC_2P5_VOLTAGE_FORM_ID 72
> +#define FSC_VCC_VOLTAGE_FORM_ID 73
> +#define FSC_PCH_TEMPERATURE_FORM_ID 74
> +#define FSC_MEM_TEMPERATURE_FORM_ID 75
> +#define FSC_VR_TEMPERATURE_FORM_ID 76
> +#define FSC_3P3STANDBY_VOLTAGE_FORM_ID 77
> +#define FSC_5BACKUP_VOLTAGE_FORM_ID 78
> +#define ROOT_MAIN_FORM_ID 79
> +#define ROOT_BOOT_FORM_ID 80
> +#define ROOT_MAINTENANCE_ID 81
> +#define ROOT_POWER_FORM_ID 82
> +#define ROOT_SECURITY_FORM_ID 83
> +#define ROOT_PERFORMANCE_FORM_ID 84
> +#define ROOT_SYSTEM_SETUP_FORM_ID 85
> +
> +#define ADDITIONAL_SYSTEM_INFO_FORM_ID 86
> +
> +#define THERMAL_CONFIG_FORM_ID 87
> +
> +#define PCI_SLOT_CONFIG_LABEL_ID_1 0x300A
> +#define PCI_SLOT_CONFIG_LABEL_ID_2 0x300B
> +#define PCI_SLOT_CONFIG_LABEL_ID_3 0x300C
> +#define PCI_SLOT_CONFIG_LABEL_ID_4 0x300D
> +#define PCI_SLOT_CONFIG_LABEL_ID_5 0x300E
> +#define PCI_SLOT_CONFIG_LABEL_ID_6 0x300F
> +#define PCI_SLOT_CONFIG_LABEL_ID_7 0x3010
> +#define PCI_SLOT_CONFIG_LABEL_ID_8 0x3011
> +
> +//
> +// Advance Hardware Monitor Callback Keys. Do not have to be sequential
> but have to be unique
> +//
> +#define CONFIGURATION_HARDWARE_CALLBACK_KEY 0x2000
> +#define ADVANCE_VIDEO_CALLBACK_KEY 0x2001
> +#define CONFIGURATION_FSC_CALLBACK_KEY 0x2002
> +#define CONFIGURATION_RESTORE_FAN_CONTROL_CALLBACK_KEY
> 0x2003
> +#define CONFIGURATION_LVDS_CALLBACK_KEY 0x2004
> +#define CONFIGURATION_PREDEFINED_EDID_CALLBACK_KEY 0x2005
> +#define ADVANCE_LVDS_CALLBACK_KEY 0x2010
> +
> +//
> +// Main Callback Keys. Do not have to be sequential but have to be unique
> +//
> +#define MAIN_LANGUAGE_CALLBACK_KEY 0x3000
> +
> +//
> +// Power Hardware Monitor Callback Keys. Do not have to be sequential but
> have to be unique
> +//
> +#define POWER_HARDWARE_CALLBACK_KEY 0x4000
> +
> +//
> +// Performance Callback Keys. Do not have to be sequential but have to be
> unique
> +//
> +#define PROCESSOR_OVERRIDES_CALLBACK_KEY 0x5000
> +#define PERFORMANCE_CALLBACK_KEY 0x5001
> +#define BUS_OVERRIDES_CALLBACK_KEY 0x5002
> +#define MEMORY_CFG_CALLBACK_KEY 0x5003
> +#define PERFORMANCE_STATUS_CALLBACK_KEY 0x5004
> +#define MEMORY_RATIO_CALLBACK_KEY 0x5005
> +#define MEMORY_MODE_CALLBACK_KEY 0x5006
> +
> +//
> +// Security Callback Keys. Do not have to be sequential but have to be
> unique
> +//
> +#define SECURITY_SUPERVISOR_CALLBACK_KEY 0x1000
> +#define SECURITY_USER_CALLBACK_KEY 0x1001
> +#define SECURITY_CLEAR_ALL_CALLBACK_KEY 0x1002
> +#define SECURITY_CLEAR_USER_CALLBACK_KEY 0x1004
> +#define SECURITY_RESET_AMT_CALLBACK_KEY 0x1008
> +#define SECURITY_CHANGE_VT_CALLBACK_KEY 0x1010
> +#define SECURITY_MASTER_HDD_CALLBACK_KEY 0x1020
> +#define SECURITY_USER_HDD_CALLBACK_KEY 0x1040
> +
> +//
> +// Boot Callback Keys. Do not have to be sequential but have to be unique
> +//
> +#define BOOT_HYPERBOOT_CALLBACK_KEY 0x6003
> +#define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE 0x6004
> +#define BOOT_HYPERBOOT_CALLBACK_KEY_USB 0x6005
> +#define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE_USB_OPT 0x6006
> +
> +//
> +// IDCC/Setup FSB Frequency Override Range
> +//
> +#define EFI_IDCC_FSB_MIN 133
> +#define EFI_IDCC_FSB_MAX 240
> +#define EFI_IDCC_FSB_STEP 1
> +
> +//
> +// Reference voltage
> +//
> +#define EFI_REF_DAC_MIN 0
> +#define EFI_REF_DAC_MAX 255
> +#define EFI_GTLREF_DEF 170
> +#define EFI_DDRREF_DEF 128
> +#define EFI_DIMMREF_DEF 128
> +
> +//
> +// Setup FSB Frequency Override Range
> +//
> +#define EFI_FSB_MIN 133
> +#define EFI_FSB_MAX 240
> +#define EFI_FSB_STEP 1
> +#define EFI_FSB_AUTOMATIC 0
> +#define EFI_FSB_MANUAL 1
> +#define FSB_FREQ_ENTRY_COUNT ((EFI_FSB_MAX -
> EFI_FSB_MIN)/EFI_FSB_STEP) + 1
> +#define FSB_FREQ_ENTRY_TYPE UINT16_TYPE
> +
> +//
> +// Setup processor multiplier range
> +//
> +#define EFI_PROC_MULT_MIN 5
> +#define EFI_PROC_MULT_MAX 40
> +#define EFI_PROC_MULT_STEP 1
> +#define EFI_PROC_AUTOMATIC 0
> +#define EFI_PROC_MANUAL 1
> +#define PROC_MULT_ENTRY_COUNT ((EFI_PROC_MULT_MAX -
> EFI_PROC_MULT_MIN)/EFI_PROC_MULT_STEP) + 1
> +#define PROC_MULT_ENTRY_TYPE UINT8_TYPE
> +
> +//
> +// PCI Express Definitions
> +//
> +#define EFI_PCIE_FREQ_DEF 0x0
> +
> +#define PCIE_FREQ_ENTRY_TYPE UINT8_TYPE
> +#define PCIE_FREQ_ENTRY_7 0x7
> +#define PCIE_FREQ_ENTRY_6 0x6
> +#define PCIE_FREQ_ENTRY_5 0x5
> +#define PCIE_FREQ_ENTRY_4 0x4
> +#define PCIE_FREQ_ENTRY_3 0x3
> +#define PCIE_FREQ_ENTRY_2 0x2
> +#define PCIE_FREQ_ENTRY_1 0x1
> +#define PCIE_FREQ_ENTRY_0 0x0
> +
> +#define PCIE_FREQ_TRANSLATION_TABLE_ENTRIES 8
> +#define PCIE_FREQ_TRANSLATION_TABLE { PCIE_FREQ_ENTRY_0, \
> + PCIE_FREQ_ENTRY_1, \
> + PCIE_FREQ_ENTRY_2, \
> + PCIE_FREQ_ENTRY_3, \
> + PCIE_FREQ_ENTRY_4, \
> + PCIE_FREQ_ENTRY_5, \
> + PCIE_FREQ_ENTRY_6, \
> + PCIE_FREQ_ENTRY_7 }
> +
> +
> +#define PCIE_FREQ_PRECISION 2
> +#define PCIE_FREQ_VALUE_7 10924
> +#define PCIE_FREQ_VALUE_6 10792
> +#define PCIE_FREQ_VALUE_5 10660
> +#define PCIE_FREQ_VALUE_4 10528
> +#define PCIE_FREQ_VALUE_3 10396
> +#define PCIE_FREQ_VALUE_2 10264
> +#define PCIE_FREQ_VALUE_1 10132
> +#define PCIE_FREQ_VALUE_0 10000
> +
> +#define PCIE_FREQ_VALUES { PCIE_FREQ_VALUE_0, \
> + PCIE_FREQ_VALUE_1, \
> + PCIE_FREQ_VALUE_2, \
> + PCIE_FREQ_VALUE_3, \
> + PCIE_FREQ_VALUE_4, \
> + PCIE_FREQ_VALUE_5, \
> + PCIE_FREQ_VALUE_6, \
> + PCIE_FREQ_VALUE_7 }
> +
> +//
> +// Memory Frequency Definitions
> +//
> +#define MEMORY_REF_FREQ_ENTRY_DEF 0x08
> +
> +#define MEMORY_REF_FREQ_ENTRY_TYPE UINT8_TYPE
> +#define MEMORY_REF_FREQ_ENTRY_3 0x04
> +#define MEMORY_REF_FREQ_ENTRY_2 0x00
> +#define MEMORY_REF_FREQ_ENTRY_1 0x02
> +#define MEMORY_REF_FREQ_ENTRY_0 0x01
> +
> +#define MEMORY_REF_FREQ_TRANSLATION_TABLE_ENTRIES 4
> +#define MEMORY_REF_FREQ_TRANSLATION_TABLE
> { MEMORY_REF_FREQ_ENTRY_0, \
> + MEMORY_REF_FREQ_ENTRY_1, \
> + MEMORY_REF_FREQ_ENTRY_2, \
> + MEMORY_REF_FREQ_ENTRY_3 }
> +
> +#define MEMORY_REF_FREQ_PRECISION 0
> +#define MEMORY_REF_FREQ_VALUE_3 333
> +#define MEMORY_REF_FREQ_VALUE_2 267
> +#define MEMORY_REF_FREQ_VALUE_1 200
> +#define MEMORY_REF_FREQ_VALUE_0 133
> +
> +#define MEMORY_REF_FREQ_VALUES { MEMORY_REF_FREQ_VALUE_0,
> \
> + MEMORY_REF_FREQ_VALUE_1, \
> + MEMORY_REF_FREQ_VALUE_2, \
> + MEMORY_REF_FREQ_VALUE_3 }
> +
> +
> +//
> +// Memory Reference Frequency Definitions
> +//
> +
> +#define MEMORY_FREQ_ENTRY_TYPE UINT8_TYPE
> +#define MEMORY_FREQ_ENTRY_3 0x4
> +#define MEMORY_FREQ_ENTRY_2 0x3
> +#define MEMORY_FREQ_ENTRY_1 0x2
> +#define MEMORY_FREQ_ENTRY_0 0x1
> +
> +#define MEMORY_FREQ_TRANSLATION_TABLE_ENTRIES 4
> +#define MEMORY_FREQ_TRANSLATION_TABLE
> { MEMORY_FREQ_ENTRY_0, \
> + MEMORY_FREQ_ENTRY_1, \
> + MEMORY_FREQ_ENTRY_2, \
> + MEMORY_FREQ_ENTRY_3 }
> +
> +
> +#define MEMORY_FREQ_MULT_PRECISION 2
> +#define MEMORY_FREQ_MULT_333MHZ_VALUE_3 240
> +#define MEMORY_FREQ_MULT_333MHZ_VALUE_2 200
> +#define MEMORY_FREQ_MULT_333MHZ_VALUE_1 160
> +#define MEMORY_FREQ_MULT_333MHZ_VALUE_0 120
> +
> +#define MEMORY_FREQ_MULT_266MHZ_VALUE_3 300
> +#define MEMORY_FREQ_MULT_266MHZ_VALUE_2 250
> +#define MEMORY_FREQ_MULT_266MHZ_VALUE_1 200
> +#define MEMORY_FREQ_MULT_266MHZ_VALUE_0 150
> +
> +#define MEMORY_FREQ_MULT_200MHZ_VALUE_3 400
> +#define MEMORY_FREQ_MULT_200MHZ_VALUE_2 333
> +#define MEMORY_FREQ_MULT_200MHZ_VALUE_1 267
> +#define MEMORY_FREQ_MULT_200MHZ_VALUE_0 200
> +
> +#define MEMORY_FREQ_MULT_133MHZ_VALUE_3 600
> +#define MEMORY_FREQ_MULT_133MHZ_VALUE_2 500
> +#define MEMORY_FREQ_MULT_133MHZ_VALUE_1 400
> +#define MEMORY_FREQ_MULT_133MHZ_VALUE_0 300
> +
> +#define MEMORY_FREQ_MULT_333MHZ_VALUES
> { MEMORY_FREQ_MULT_333MHZ_VALUE_0, \
> + MEMORY_FREQ_MULT_333MHZ_VALUE_1, \
> + MEMORY_FREQ_MULT_333MHZ_VALUE_2, \
> + MEMORY_FREQ_MULT_333MHZ_VALUE_3 }
> +
> +#define MEMORY_FREQ_MULT_266MHZ_VALUES
> { MEMORY_FREQ_MULT_266MHZ_VALUE_0, \
> + MEMORY_FREQ_MULT_266MHZ_VALUE_1, \
> + MEMORY_FREQ_MULT_266MHZ_VALUE_2, \
> + MEMORY_FREQ_MULT_266MHZ_VALUE_3 }
> +
> +#define MEMORY_FREQ_MULT_200MHZ_VALUES
> { MEMORY_FREQ_MULT_200MHZ_VALUE_0, \
> + MEMORY_FREQ_MULT_200MHZ_VALUE_1, \
> + MEMORY_FREQ_MULT_200MHZ_VALUE_2, \
> + MEMORY_FREQ_MULT_200MHZ_VALUE_3 }
> +
> +#define MEMORY_FREQ_MULT_133MHZ_VALUES
> { MEMORY_FREQ_MULT_133MHZ_VALUE_0, \
> + MEMORY_FREQ_MULT_133MHZ_VALUE_1, \
> + MEMORY_FREQ_MULT_133MHZ_VALUE_2, \
> + MEMORY_FREQ_MULT_133MHZ_VALUE_3 }
> +
> +//
> +// CAS Memory Timing Definitions
> +//
> +
> +#define MEMORY_TCL_ENTRY_TYPE UINT8_TYPE
> +#define MEMORY_TCL_ENTRY_3 0x2
> +#define MEMORY_TCL_ENTRY_2 0x1
> +#define MEMORY_TCL_ENTRY_1 0x0
> +#define MEMORY_TCL_ENTRY_0 0x3
> +
> +#define MEMORY_TCL_TRANSLATION_TABLE_ENTRIES 4
> +#define MEMORY_TCL_TRANSLATION_TABLE { MEMORY_TCL_ENTRY_0,
> \
> + MEMORY_TCL_ENTRY_1, \
> + MEMORY_TCL_ENTRY_2, \
> + MEMORY_TCL_ENTRY_3 }
> +
> +
> +#define MEMORY_TCL_PRECISION 0
> +#define MEMORY_TCL_VALUE_3 3
> +#define MEMORY_TCL_VALUE_2 4
> +#define MEMORY_TCL_VALUE_1 5
> +#define MEMORY_TCL_VALUE_0 6
> +
> +#define MEMORY_TCL_VALUES { MEMORY_TCL_VALUE_0, \
> + MEMORY_TCL_VALUE_1, \
> + MEMORY_TCL_VALUE_2, \
> + MEMORY_TCL_VALUE_3 }
> +
> +
> +//
> +// TRCD Memory Timing Definitions
> +//
> +
> +#define MEMORY_TRCD_ENTRY_TYPE UINT8_TYPE
> +#define MEMORY_TRCD_ENTRY_3 0x0
> +#define MEMORY_TRCD_ENTRY_2 0x1
> +#define MEMORY_TRCD_ENTRY_1 0x2
> +#define MEMORY_TRCD_ENTRY_0 0x3
> +
> +#define MEMORY_TRCD_TRANSLATION_TABLE_ENTRIES 4
> +#define MEMORY_TRCD_TRANSLATION_TABLE
> { MEMORY_TRCD_ENTRY_0, \
> + MEMORY_TRCD_ENTRY_1, \
> + MEMORY_TRCD_ENTRY_2, \
> + MEMORY_TRCD_ENTRY_3 }
> +
> +
> +#define MEMORY_TRCD_PRECISION 0
> +#define MEMORY_TRCD_VALUE_3 2
> +#define MEMORY_TRCD_VALUE_2 3
> +#define MEMORY_TRCD_VALUE_1 4
> +#define MEMORY_TRCD_VALUE_0 5
> +
> +#define MEMORY_TRCD_VALUES { MEMORY_TRCD_VALUE_0, \
> + MEMORY_TRCD_VALUE_1, \
> + MEMORY_TRCD_VALUE_2, \
> + MEMORY_TRCD_VALUE_3 }
> +
> +
> +//
> +// TRP Memory Timing Definitions
> +//
> +
> +#define MEMORY_TRP_ENTRY_TYPE UINT8_TYPE
> +#define MEMORY_TRP_ENTRY_3 0x0
> +#define MEMORY_TRP_ENTRY_2 0x1
> +#define MEMORY_TRP_ENTRY_1 0x2
> +#define MEMORY_TRP_ENTRY_0 0x3
> +
> +#define MEMORY_TRP_TRANSLATION_TABLE_ENTRIES 4
> +#define MEMORY_TRP_TRANSLATION_TABLE { MEMORY_TRP_ENTRY_0,
> \
> + MEMORY_TRP_ENTRY_1, \
> + MEMORY_TRP_ENTRY_2, \
> + MEMORY_TRP_ENTRY_3 }
> +
> +
> +#define MEMORY_TRP_PRECISION 0
> +#define MEMORY_TRP_VALUE_3 2
> +#define MEMORY_TRP_VALUE_2 3
> +#define MEMORY_TRP_VALUE_1 4
> +#define MEMORY_TRP_VALUE_0 5
> +
> +#define MEMORY_TRP_VALUES { MEMORY_TRP_VALUE_0, \
> + MEMORY_TRP_VALUE_1, \
> + MEMORY_TRP_VALUE_2, \
> + MEMORY_TRP_VALUE_3 }
> +
> +
> +//
> +// TRAS Memory Timing Definitions
> +//
> +#define MEMORY_TRAS_MIN 4
> +#define MEMORY_TRAS_MAX 18
> +#define MEMORY_TRAS_STEP 1
> +#define MEMORY_TRAS_DEFAULT 13
> +#define MEMORY_TRAS_COUNT ((MEMORY_TRAS_MAX -
> MEMORY_TRAS_MIN)/MEMORY_TRAS_STEP) + 1
> +#define MEMORY_TRAS_TYPE UINT8_TYPE
> +
> +//
> +// Uncore Multiplier Definitions
> +//
> +#define UCLK_RATIO_MIN 12
> +#define UCLK_RATIO_MAX 30
> +#define UCLK_RATIO_DEFAULT 20
> +
> +#endif // #ifndef _CONFIGURATION_H
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/ExI.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/ExI.c
> new file mode 100644
> index 0000000000..ad667b0bd8
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/ExI.c
> @@ -0,0 +1,89 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + ExI.c
> +
> +Abstract:
> +
> + ExI configuration based on setup option
> +
> +
> +--*/
> +
> +
> +#include "PlatformDxe.h"
> +
> +#define PchLpcPciCfg32(Register) MmioRead32 (MmPciAddress (0,
> DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0,
> Register))
> +
> +//
> +// Procedure: GetPmcBase
> +//
> +// Description: This function read content of B:D:F 0:31:0, offset 44h (for
> +// PmcBase)
> +//
> +// Input: None
> +//
> +// Output: 32 bit PmcBase
> +//
> +UINT32
> +GetPmcBase (
> + VOID
> + )
> +{
> + return (PchLpcPciCfg32 (R_PCH_LPC_PMC_BASE) &
> B_PCH_LPC_PMC_BASE_BAR);
> +}
> +
> +/**
> + Configure ExI.
> +
> + @param ImageHandle Pointer to the loaded image protocol for this
> driver
> + @param SystemTable Pointer to the EFI System Table
> +
> + @retval EFI_SUCCESS The driver initializes correctly.
> +**/
> +VOID
> +InitExI (
> + )
> +{
> + EFI_STATUS Status;
> +
> + SYSTEM_CONFIGURATION SystemConfiguration;
> + UINTN VarSize;
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> +
> + Status = gRT->GetVariable(
> + L"Setup",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> +
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + if (SystemConfiguration.ExISupport == 1) {
> + MmioOr32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1),
> (UINT32) BIT0+BIT1+BIT2);
> + } else if (SystemConfiguration.ExISupport == 0) {
> + MmioAnd32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1),
> ~((UINT32) BIT0+BIT1+BIT2)); //clear bit 0,1,2
> + }
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IchPlatformPolicy.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IchPlatformPolicy.c
> new file mode 100644
> index 0000000000..fc19635f99
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IchPlatformPolicy.c
> @@ -0,0 +1,484 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +
> +Module Name:
> +
> +
> + PchPlatformPolicy.c
> +
> +Abstract:
> +
> +
> +--*/
> +
> +#include "PlatformDxe.h"
> +#include <Protocol/PchPlatformPolicy.h>
> +#include <Protocol/VlvPlatformPolicy.h>
> +#include <Library/PchPlatformLib.h>
> +
> +#include "AzaliaVerbTable.h"
> +#include "Protocol/GlobalNvsArea.h"
> +#include "Protocol/DxePchPolicyUpdateProtocol.h"
> +
> +#define MOBILE_PLATFORM 1
> +#define DESKTOP_PLATFORM 2
> +
> +EFI_GUID gDxePchPolicyUpdateProtocolGuid =
> DXE_PCH_POLICY_UPDATE_PROTOCOL_GUID;
> +DXE_PCH_POLICY_UPDATE_PROTOCOL mDxePchPolicyUpdate = { 0 };
> +
> +/**
> +
> + Updates the feature policies according to the setup variable.
> +
> + @retval VOID
> +
> +**/
> +VOID
> +InitPchPlatformPolicy (
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfo
> + )
> +{
> + DXE_PCH_PLATFORM_POLICY_PROTOCOL *DxePlatformPchPolicy;
> + EFI_STATUS Status;
> + EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
> + UINT8 PortIndex;
> + EFI_HANDLE Handle;
> + PCH_STEPPING SocStepping = PchA0;
> + BOOLEAN ModifyVariable;
> +
> + ModifyVariable = FALSE;
> + DEBUG ((EFI_D_INFO, "InitPchPlatformPolicy() - Start\n"));
> +
> + Status = gBS->LocateProtocol (&gDxePchPlatformPolicyProtocolGuid,
> NULL, (VOID **) &DxePlatformPchPolicy);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Locate the Global NVS Protocol.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiGlobalNvsAreaProtocolGuid,
> + NULL,
> + (VOID **) &GlobalNvsArea
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Update system information
> + //
> + DxePlatformPchPolicy->Revision =
> DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_12;
> +
> + //
> + // General initialization
> + //
> + DxePlatformPchPolicy->BusNumber = 0;
> +
> + //
> + // VLV BIOS Spec Section 3.6 Flash Security Recommendation,
> + // Intel strongly recommends that BIOS sets the BIOS Interface Lock Down
> bit. Enabling this bit
> + // will mitigate malicious software attempts to replace the system BIOS
> option ROM with its own code.
> + // We always enable this as a platform policy.
> + //
> + DxePlatformPchPolicy->LockDownConfig->BiosInterface =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->LockDownConfig->BiosLock =
> mSystemConfiguration.SpiRwProtect;
> +
> + //
> + // DeviceEnables
> + //
> + DxePlatformPchPolicy->DeviceEnabling->Lan = mSystemConfiguration.Lan;
> + DxePlatformPchPolicy->DeviceEnabling->Azalia =
> mSystemConfiguration.PchAzalia;
> + DxePlatformPchPolicy->DeviceEnabling->Sata =
> mSystemConfiguration.Sata;
> + DxePlatformPchPolicy->DeviceEnabling->Smbus =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->DeviceEnabling->LpeEnabled =
> mSystemConfiguration.Lpe;
> +
> + DxePlatformPchPolicy->UsbConfig->Ehci1Usbr =
> PCH_DEVICE_DISABLE;
> +
> + DxePlatformPchPolicy->UsbConfig->UsbXhciLpmSupport
> =mSystemConfiguration.UsbXhciLpmSupport;
> +
> + //
> + // Disable FFRD PR0 USB port2 for power saving since PR0 uses non-POR
> WWAN (but enable on PR0.3/PR0.5/PR1)
> + //
> + if ((PlatformInfo->BoardId == BOARD_ID_BL_FFRD) && (PlatformInfo-
> >BoardRev == PR0))
> + if (mSystemConfiguration.PchUsbPort[2] !=0) {
> + mSystemConfiguration.PchUsbPort[2]=0;
> + ModifyVariable = TRUE;
> + }
> +
> +
> + if (ModifyVariable) {
> + Status = gRT->SetVariable (
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + sizeof(SYSTEM_CONFIGURATION),
> + &mSystemConfiguration
> + );
> + }
> +
> + SocStepping = PchStepping();
> + if (mSystemConfiguration.UsbAutoMode == 1) { // auto mode is enabled
> + if (PchA0 == SocStepping) {
> + //
> + // For A0, EHCI is enabled as default.
> + //
> + mSystemConfiguration.PchUsb20 = 1;
> + mSystemConfiguration.PchUsb30Mode = 0;
> + mSystemConfiguration.UsbXhciSupport = 0;
> + DEBUG ((EFI_D_INFO, "EHCI is enabled as default. SOC 0x%x\n",
> SocStepping));
> + } else {
> + //
> + // For A1 and later, XHCI is enabled as default.
> + //
> + mSystemConfiguration.PchUsb20 = 0;
> + mSystemConfiguration.PchUsb30Mode = 1;
> + mSystemConfiguration.UsbXhciSupport = 1;
> + DEBUG ((EFI_D_INFO, "XHCI is enabled as default. SOC 0x%x\n",
> SocStepping));
> + }
> + //
> + //overwrite the setting
> + //
> + Status = gRT->SetVariable(
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + sizeof(SYSTEM_CONFIGURATION),
> + &mSystemConfiguration
> + );
> + }
> +
> + //
> + // USB Device 29 configuration
> + //
> + DxePlatformPchPolicy->UsbConfig->Usb20Settings[0].Enable =
> mSystemConfiguration.PchUsb20;
> + DxePlatformPchPolicy->UsbConfig->UsbPerPortCtl =
> mSystemConfiguration.PchUsbPerPortCtl;
> + if (mSystemConfiguration.PchUsbPerPortCtl != PCH_DEVICE_DISABLE) {
> + for (PortIndex = 0; PortIndex < PCH_USB_MAX_PHYSICAL_PORTS;
> PortIndex++) {
> + DxePlatformPchPolicy->UsbConfig->PortSettings[PortIndex].Enable =
> mSystemConfiguration.PchUsbPort[PortIndex];
> + }
> + }
> +
> + DxePlatformPchPolicy->UsbConfig->EhciDebug =
> mSystemConfiguration.PchEhciDebug;
> +
> + //
> + // xHCI (USB 3.0) related settings from setup variable
> + //
> + DxePlatformPchPolicy->UsbConfig->Usb30Settings.XhciStreams =
> mSystemConfiguration.PchUsb30Streams;
> +
> + DxePlatformPchPolicy->UsbConfig->Usb30Settings.Mode =
> mSystemConfiguration.PchUsb30Mode;
> +
> + //
> + // Remove XHCI Pre-Boot Driver setup option selection from end-user
> view and automate loading of USB 3.0 BIOS driver based on XhciMode
> selection
> + //
> + switch (mSystemConfiguration.PchUsb30Mode) {
> + case 0: // Disabled
> + DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 0;
> + break;
> + case 1: // Enabled
> + DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 1;
> + break;
> + case 2: // Auto
> + DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 0;
> + break;
> + case 3: // Smart Auto
> + DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 1;
> + break;
> + default:
> + DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport =
> mSystemConfiguration.UsbXhciSupport;
> + break;
> + }
> +
> +
> +
> + DxePlatformPchPolicy->UsbConfig->UsbOtgSettings.Enable =
> mSystemConfiguration.PchUsbOtg;
> +
> + DxePlatformPchPolicy->UsbConfig->PortSettings[0].Dock =
> PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->UsbConfig->PortSettings[1].Dock =
> PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->UsbConfig->PortSettings[2].Dock =
> PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->UsbConfig->PortSettings[3].Dock =
> PCH_DEVICE_DISABLE;
> +
> + DxePlatformPchPolicy->UsbConfig->PortSettings[0].Panel =
> PCH_USB_FRONT_PANEL;
> + DxePlatformPchPolicy->UsbConfig->PortSettings[1].Panel =
> PCH_USB_FRONT_PANEL;
> + DxePlatformPchPolicy->UsbConfig->PortSettings[2].Panel =
> PCH_USB_BACK_PANEL;
> + DxePlatformPchPolicy->UsbConfig->PortSettings[3].Panel =
> PCH_USB_BACK_PANEL;
> +
> + //
> + //
> + // Enable USB Topology control and program the topology setting for every
> USB port
> + // See Platform Design Guide for description of topologies
> + //
> + //
> + // Port 0: ~5.3", Port 1: ~4.9", Port 2: ~4.7", Port 3: ~8.0"
> + //
> + DxePlatformPchPolicy->UsbConfig->Usb20PortLength[0] = 0x53;
> + DxePlatformPchPolicy->UsbConfig->Usb20PortLength[1] = 0x49;
> + DxePlatformPchPolicy->UsbConfig->Usb20PortLength[2] = 0x47;
> + DxePlatformPchPolicy->UsbConfig->Usb20PortLength[3] = 0x80;
> +
> + DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[0] =
> PchUsbOverCurrentPin0;
> + DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[1] =
> PchUsbOverCurrentPin0;
> + DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[2] =
> PchUsbOverCurrentPin1;
> + DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[3] =
> PchUsbOverCurrentPin1;
> +
> + DxePlatformPchPolicy->UsbConfig->Usb30OverCurrentPins[0] =
> PchUsbOverCurrentPinSkip;//PchUsbOverCurrentPin0;
> +
> + DxePlatformPchPolicy->EhciPllCfgEnable =
> mSystemConfiguration.EhciPllCfgEnable;
> + DEBUG ((EFI_D_INFO, "InitPchPlatformPolicy() DxePlatformPchPolicy-
> >EhciPllCfgEnable = 0x%x \n",DxePlatformPchPolicy->EhciPllCfgEnable));
> + DxePlatformPchPolicy->PciExpressConfig->PcieDynamicGating
> = mSystemConfiguration.PcieDynamicGating;
> + for (PortIndex = 0; PortIndex < PCH_PCIE_MAX_ROOT_PORTS;
> PortIndex++) {
> + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].Enable
> = mSystemConfiguration.IchPciExp[PortIndex];
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].SlotImplemented = PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].FunctionNumber = PortIndex;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].PhysicalSlotNumber = PortIndex;
> + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].Aspm
> = 4;
> + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].PmSci
> = PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].ExtSync
> = PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].HotPlug
> = PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].AdvancedErrorReporting = PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].UnsupportedRequestReport =
> PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].FatalErrorReport = PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].NoFatalErrorReport = PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].CorrectableErrorReport = PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].PmeInterrupt = 0;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].SystemErrorOnFatalError = PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].SystemErrorOnNonFatalError =
> PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].SystemErrorOnCorrectableError =
> PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->PciExpressConfig-
> >RootPort[PortIndex].CompletionTimeout =
> PchPciECompletionTO_Default;
> + }
> +
> + //
> + // SATA configuration
> + //
> + for (PortIndex = 0; PortIndex < PCH_AHCI_MAX_PORTS; PortIndex++) {
> + if (mSystemConfiguration.SataType == 0) {
> + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->LegacyMode =
> PCH_DEVICE_ENABLE;
> + } else {
> + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->LegacyMode =
> PCH_DEVICE_DISABLE;
> + }
> + if(mSystemConfiguration.Sata == 1){
> + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable =
> PCH_DEVICE_ENABLE;
> + } else {
> + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable =
> PCH_DEVICE_DISABLE;
> + }
> + if(0 == PortIndex){
> + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].HotPlug =
> PCH_DEVICE_DISABLE;
> + } else if(1 == PortIndex){
> + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].HotPlug =
> PCH_DEVICE_DISABLE;
> + }
> +
> + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].SpinUp =
> PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].MechSw
> = PCH_DEVICE_DISABLE;
> + }
> + DxePlatformPchPolicy->SataConfig->RaidAlternateId =
> PCH_DEVICE_DISABLE;
> + DxePlatformPchPolicy->SataConfig->Raid0 =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->Raid1 =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->Raid10 =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->Raid5 =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->Irrt =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->OromUiBanner =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->HddUnlock =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->LedLocate =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->IrrtOnly =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->SalpSupport =
> PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->SataConfig->TestMode =
> mSystemConfiguration.SataTestMode;
> +
> + //
> + // AzaliaConfig
> + //
> + DxePlatformPchPolicy->AzaliaConfig->Pme =
> mSystemConfiguration.AzaliaPme;
> + DxePlatformPchPolicy->AzaliaConfig->HdmiCodec =
> mSystemConfiguration.HdmiCodec;
> + DxePlatformPchPolicy->AzaliaConfig->DS =
> mSystemConfiguration.AzaliaDs;
> + DxePlatformPchPolicy->AzaliaConfig->AzaliaVCi =
> mSystemConfiguration.AzaliaVCiEnable;
> +
> + //
> + // Set LPSS configuration according to setup value.
> + //
> + DxePlatformPchPolicy->LpssConfig->LpssPciModeEnabled =
> mSystemConfiguration.LpssPciModeEnabled;
> +
> + DxePlatformPchPolicy->LpssConfig->Dma1Enabled =
> mSystemConfiguration.LpssDma1Enabled;
> + DxePlatformPchPolicy->LpssConfig->I2C0Enabled =
> mSystemConfiguration.LpssI2C0Enabled;
> + DxePlatformPchPolicy->LpssConfig->I2C1Enabled =
> mSystemConfiguration.LpssI2C1Enabled;
> + DxePlatformPchPolicy->LpssConfig->I2C2Enabled =
> mSystemConfiguration.LpssI2C2Enabled;
> + DxePlatformPchPolicy->LpssConfig->I2C3Enabled =
> mSystemConfiguration.LpssI2C3Enabled;
> + DxePlatformPchPolicy->LpssConfig->I2C4Enabled =
> mSystemConfiguration.LpssI2C4Enabled;
> + DxePlatformPchPolicy->LpssConfig->I2C5Enabled =
> mSystemConfiguration.LpssI2C5Enabled;
> + DxePlatformPchPolicy->LpssConfig->I2C6Enabled =
> mSystemConfiguration.LpssI2C6Enabled;
> +
> + DxePlatformPchPolicy->LpssConfig->Dma0Enabled =
> mSystemConfiguration.LpssDma0Enabled;;
> + DxePlatformPchPolicy->LpssConfig->Pwm0Enabled =
> mSystemConfiguration.LpssPwm0Enabled;
> + DxePlatformPchPolicy->LpssConfig->Pwm1Enabled =
> mSystemConfiguration.LpssPwm1Enabled;
> + DxePlatformPchPolicy->LpssConfig->Hsuart0Enabled =
> mSystemConfiguration.LpssHsuart0Enabled;
> + DxePlatformPchPolicy->LpssConfig->Hsuart1Enabled =
> mSystemConfiguration.LpssHsuart1Enabled;
> + DxePlatformPchPolicy->LpssConfig->SpiEnabled =
> mSystemConfiguration.LpssSpiEnabled;
> +
> + //
> + // Set SCC configuration according to setup value.
> + //
> + DxePlatformPchPolicy->SccConfig->SdioEnabled =
> mSystemConfiguration.LpssSdioEnabled;
> + DxePlatformPchPolicy->SccConfig->SdcardEnabled = TRUE;
> + DxePlatformPchPolicy->SccConfig->SdCardSDR25Enabled =
> mSystemConfiguration.LpssSdCardSDR25Enabled;
> + DxePlatformPchPolicy->SccConfig->SdCardDDR50Enabled =
> mSystemConfiguration.LpssSdCardDDR50Enabled;
> + DxePlatformPchPolicy->SccConfig->HsiEnabled =
> mSystemConfiguration.LpssMipiHsi;
> +
> + if (mSystemConfiguration.eMMCBootMode== 1) {// Auto detection mode
> + //
> + // Silicon Stepping
> + //
> + switch (PchStepping()) {
> + case PchA0: // A0 and A1
> + case PchA1:
> + DEBUG ((EFI_D_ERROR, "Auto Detect: SOC A0/A1: SCC eMMC 4.41
> Configuration\n"));
> + DxePlatformPchPolicy->SccConfig->eMMCEnabled = 1;
> + DxePlatformPchPolicy->SccConfig->eMMC45Enabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = 0;
> + break;
> + case PchB0: // B0 and later
> + default:
> + DEBUG ((EFI_D_ERROR, "Auto Detect: SOC B0 and later: SCC eMMC 4.5
> Configuration\n"));
> + DxePlatformPchPolicy->SccConfig->eMMCEnabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45Enabled =
> mSystemConfiguration.LpsseMMC45Enabled;
> + DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled =
> mSystemConfiguration.LpsseMMC45DDR50Enabled;
> + DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled =
> mSystemConfiguration.LpsseMMC45HS200Enabled;
> + DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue =
> mSystemConfiguration.LpsseMMC45RetuneTimerValue;
> + break;
> + }
> + } else if (mSystemConfiguration.eMMCBootMode == 2) { // eMMC 4.41
> + DEBUG ((EFI_D_ERROR, "Force to SCC eMMC 4.41 Configuration\n"));
> + DxePlatformPchPolicy->SccConfig->eMMCEnabled = 1;
> + DxePlatformPchPolicy->SccConfig->eMMC45Enabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = 0;
> +
> + } else if (mSystemConfiguration.eMMCBootMode == 3) { // eMMC 4.5
> + DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 Configuration\n"));
> + DxePlatformPchPolicy->SccConfig->eMMCEnabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45Enabled =
> mSystemConfiguration.LpsseMMC45Enabled;
> + DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled =
> mSystemConfiguration.LpsseMMC45DDR50Enabled;
> + DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled =
> mSystemConfiguration.LpsseMMC45HS200Enabled;
> + DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue =
> mSystemConfiguration.LpsseMMC45RetuneTimerValue;
> +
> + } else { // Disable eMMC controllers
> + DEBUG ((EFI_D_ERROR, "Disable eMMC controllers\n"));
> + DxePlatformPchPolicy->SccConfig->eMMCEnabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45Enabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled = 0;
> + DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = 0;
> + }
> +
> + //
> + // Reserved SMBus Address
> + //
> + DxePlatformPchPolicy->SmbusConfig->NumRsvdSmbusAddresses = 4;
> + DxePlatformPchPolicy->SmbusConfig->RsvdSmbusAddressTable =
> mSmbusRsvdAddresses;
> +
> + //
> + // MiscPm Configuration
> + //
> + DxePlatformPchPolicy->MiscPmConfig->WakeConfig.WolEnableOverride
> = mSystemConfiguration.WakeOnLanS5;
> + DxePlatformPchPolicy->MiscPmConfig->SlpLanLowDc =
> mSystemConfiguration.SlpLanLowDc;
> + DxePlatformPchPolicy->MiscPmConfig-
> >PowerResetStatusClear.MeWakeSts = PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->MiscPmConfig-
> >PowerResetStatusClear.MeHrstColdSts = PCH_DEVICE_ENABLE;
> + DxePlatformPchPolicy->MiscPmConfig-
> >PowerResetStatusClear.MeHrstWarmSts = PCH_DEVICE_ENABLE;
> +
> + //
> + // Enable / disable serial IRQ according to setup value.
> + //
> + DxePlatformPchPolicy->SerialIrqConfig->SirqEnable =
> PCH_DEVICE_ENABLE;
> +
> + //
> + // Set Serial IRQ Mode Select according to setup value.
> + //
> + DxePlatformPchPolicy->SerialIrqConfig->SirqMode = PchQuietMode;
> +
> + //
> + // Program the default Sub System Vendor Device Id
> + //
> + DxePlatformPchPolicy->DefaultSvidSid->SubSystemVendorId =
> V_PCH_INTEL_VENDOR_ID;
> + DxePlatformPchPolicy->DefaultSvidSid->SubSystemId =
> V_PCH_DEFAULT_SID;
> +
> + mAzaliaVerbTable[9].VerbTableData = mAzaliaVerbTableData12;
> +
> + DxePlatformPchPolicy->AzaliaConfig->AzaliaVerbTableNum = sizeof
> (mAzaliaVerbTable) / sizeof (PCH_AZALIA_VERB_TABLE);
> + DxePlatformPchPolicy->AzaliaConfig->AzaliaVerbTable =
> mAzaliaVerbTable;
> + DxePlatformPchPolicy->AzaliaConfig->ResetWaitTimer = 300;
> +
> + DxePlatformPchPolicy->IdleReserve = mSystemConfiguration.IdleReserve;
> + DxePlatformPchPolicy->AcpiHWRed = PCH_DEVICE_DISABLE;
> +
> + //
> + // Install DxePchPolicyUpdateProtocol
> + //
> + Handle = NULL;
> +
> + mDxePchPolicyUpdate.Revision =
> DXE_PCH_POLICY_UPDATE_PROTOCOL_REVISION_1;
> +
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Handle,
> + &gDxePchPolicyUpdateProtocolGuid,
> + &mDxePchPolicyUpdate,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + DEBUG ((EFI_D_INFO, "InitPchPlatformPolicy() - End\n"));
> +}
> +
> +
> +DXE_VLV_PLATFORM_POLICY_PROTOCOL mDxePlatformVlvPolicy;
> +
> +VOID
> +InitVlvPlatformPolicy (
> + )
> +{
> + DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformVlvPolicy;
> + EFI_STATUS Status;
> + EFI_HANDLE Handle;
> +
> + ZeroMem (&mDxePlatformVlvPolicy,
> sizeof(DXE_VLV_PLATFORM_POLICY_PROTOCOL));
> +
> + DxePlatformVlvPolicy = &mDxePlatformVlvPolicy;
> +
> +
> + DxePlatformVlvPolicy->GraphicReserve00 =
> mSystemConfiguration.GraphicReserve00;
> + DxePlatformVlvPolicy->PavpMode = mSystemConfiguration.PavpMode;
> + DxePlatformVlvPolicy->GraphicReserve01 = 1;
> + DxePlatformVlvPolicy->GraphicReserve02 =
> mSystemConfiguration.GraphicReserve02;
> + DxePlatformVlvPolicy->GraphicReserve03 = 1;
> + DxePlatformVlvPolicy->GraphicReserve04 = 0;
> + DxePlatformVlvPolicy->GraphicReserve05 =
> mSystemConfiguration.GraphicReserve05;
> + DxePlatformVlvPolicy->IgdPanelFeatures.PFITStatus =
> mSystemConfiguration.PanelScaling;
> +
> + DxePlatformVlvPolicy->IgdPanelFeatures.LidStatus = 1;
> + DxePlatformVlvPolicy->IdleReserve = mSystemConfiguration.IdleReserve;
> +
> + DxePlatformVlvPolicy->GraphicReserve06 = 1;
> +
> + if ( (mSystemConfiguration.Lpe == 1) || mSystemConfiguration.Lpe == 2) {
> + DxePlatformVlvPolicy ->AudioTypeSupport = LPE_AUDIO ;
> + } else if ( mSystemConfiguration.PchAzalia == 1 ) {
> + DxePlatformVlvPolicy ->AudioTypeSupport = HD_AUDIO;
> + } else {
> + DxePlatformVlvPolicy ->AudioTypeSupport = NO_AUDIO;
> + }
> +
> + Handle = NULL;
> + Status = gBS->InstallProtocolInterface (
> + &Handle,
> + &gDxeVlvPlatformPolicyGuid,
> + EFI_NATIVE_INTERFACE,
> + DxePlatformVlvPolicy
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c
> new file mode 100644
> index 0000000000..cac61bffd0
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c
> @@ -0,0 +1,134 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + IchRegTable.c
> +
> +Abstract:
> +
> + Register initialization table for Ich.
> +
> +
> +
> +--*/
> +
> +#include <Library/EfiRegTableLib.h>
> +#include "PlatformDxe.h"
> +extern EFI_PLATFORM_INFO_HOB mPlatformInfo;
> +
> +#define R_EFI_PCI_SVID 0x2C
> +
> +EFI_REG_TABLE mSubsystemIdRegs [] = {
> +
> + //
> + // Program SVID and SID for PCI devices.
> + // Combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE in order to
> boost performance
> + //
> + PCI_WRITE (
> + MC_BUS, MC_DEV, MC_FUN, R_EFI_PCI_SVID, EfiPciWidthUint32,
> + V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
> + ),
> +
> + PCI_WRITE (
> + IGD_BUS, IGD_DEV, IGD_FUN_0, R_EFI_PCI_SVID, EfiPciWidthUint32,
> + V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
> + ),
> +
> + PCI_WRITE(
> + DEFAULT_PCI_BUS_NUMBER_PCH, 0, 0, R_EFI_PCI_SVID,
> EfiPciWidthUint32,
> + V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
> + ),
> + PCI_WRITE (
> + DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC,
> PCI_FUNCTION_NUMBER_PCH_LPC, R_PCH_LPC_SS, EfiPciWidthUint32,
> + V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
> + ),
> + PCI_WRITE (
> + DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA,
> PCI_FUNCTION_NUMBER_PCH_SATA, R_PCH_SATA_SS, EfiPciWidthUint32,
> + V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
> + ),
> + PCI_WRITE (
> + DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS,
> PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_SVID,
> EfiPciWidthUint32,
> + V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
> + ),
> + PCI_WRITE (
> + DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_USB,
> PCI_FUNCTION_NUMBER_PCH_EHCI, R_PCH_EHCI_SVID, EfiPciWidthUint32,
> + V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
> + ),
> + PCI_WRITE (
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
> PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, R_PCH_PCIE_SVID,
> EfiPciWidthUint32,
> + V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
> + ),
> + PCI_WRITE (
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
> PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, R_PCH_PCIE_SVID,
> EfiPciWidthUint32,
> + V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
> + ),
> + PCI_WRITE (
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
> PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, R_PCH_PCIE_SVID,
> EfiPciWidthUint32,
> + V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
> + ),
> + PCI_WRITE (
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
> PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, R_PCH_PCIE_SVID,
> EfiPciWidthUint32,
> + V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
> + ),
> + TERMINATE_TABLE
> +};
> +
> +/**
> + Updates the mSubsystemIdRegs table, and processes it. This should
> program
> + the Subsystem Vendor and Device IDs.
> +
> + @retval Returns VOID
> +
> +**/
> +VOID
> +InitializeSubsystemIds (
> + )
> +{
> +
> + EFI_REG_TABLE *RegTablePtr;
> + UINT32 SubsystemVidDid;
> +
> + SubsystemVidDid = mPlatformInfo.SsidSvid;
> +
> + RegTablePtr = mSubsystemIdRegs;
> +
> + //
> + // While we are not at the end of the table
> + //
> + while (RegTablePtr->Generic.OpCode != OP_TERMINATE_TABLE) {
> + //
> + // If the data to write is the original SSID
> + //
> + if (RegTablePtr->PciWrite.Data ==
> + ((V_PCH_DEFAULT_SID << 16) |
> + V_PCH_INTEL_VENDOR_ID)
> + ) {
> +
> + //
> + // Then overwrite it to use the alternate SSID
> + //
> + RegTablePtr->PciWrite.Data = SubsystemVidDid;
> + }
> +
> + //
> + // Go to next table entry
> + //
> + RegTablePtr++;
> + }
> +
> + RegTablePtr = mSubsystemIdRegs;
> +
> +
> + //
> + // Program the SSVID/SSDID
> + //
> + ProcessRegTablePci (mSubsystemIdRegs, mPciRootBridgeIo, NULL);
> +
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IchTcoReset.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IchTcoReset.c
> new file mode 100644
> index 0000000000..5b7822deda
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IchTcoReset.c
> @@ -0,0 +1,211 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + IchTcoReset.c
> +
> +Abstract:
> + Implements the programming of events in TCO Reset
> +
> +
> +--*/
> +
> +#include "PlatformDxe.h"
> +#include <Protocol/TcoReset.h>
> +#include <Protocol/HwWatchdogTimer.h>
> +
> +
> +EFI_STATUS
> +EFIAPI
> +EnableTcoReset (
> + IN UINT32 *RcrbGcsSaveValue
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +DisableTcoReset (
> + OUT UINT32 RcrbGcsRestoreValue
> + );
> +
> +EFI_TCO_RESET_PROTOCOL mTcoResetProtocol = {
> + EnableTcoReset,
> + DisableTcoReset
> +};
> +
> +/**
> +
> + Enables the TCO timer to reset the system in case of a system hang. This is
> + used when writing the clock registers.
> +
> + @param RcrbGcsSaveValue This is the value of the RCRB GCS register
> before it is
> + changed by this procedure. This will be used to restore
> + the settings of this register in PpiDisableTcoReset.
> +
> + @retval EFI_STATUS
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +EnableTcoReset (
> + IN UINT32 *RcrbGcsSaveValue
> + )
> +{
> + UINT16 TmpWord;
> + UINT16 AcpiBase;
> + EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL *WatchdogTimerProtocol;
> + EFI_STATUS Status;
> + UINTN PbtnDisableInterval = 4; //Default value
> +
> + //
> + // Get Watchdog Timer protocol.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiWatchdogTimerDriverProtocolGuid,
> + NULL,
> + (VOID **)&WatchdogTimerProtocol
> + );
> +
> + //
> + // If the protocol is present, shut off the Timer as we enter BDS
> + //
> + if (!EFI_ERROR(Status)) {
> + WatchdogTimerProtocol->RestartWatchdogTimer();
> + WatchdogTimerProtocol->AllowKnownReset(TRUE);
> + }
> +
> + if (*RcrbGcsSaveValue == 0) {
> + PbtnDisableInterval = PcdGet32(PcdPBTNDisableInterval);
> + } else {
> + PbtnDisableInterval = *RcrbGcsSaveValue * 10 / 6;
> + }
> +
> + //
> + // Read ACPI Base Address
> + //
> + AcpiBase = PchLpcPciCfg16(R_PCH_LPC_ACPI_BASE) &
> B_PCH_LPC_ACPI_BASE_BAR;
> +
> + //
> + // Stop TCO if not already stopped
> + //
> + TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);
> + TmpWord |= B_PCH_TCO_CNT_TMR_HLT;
> + IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);
> +
> + //
> + // Clear second TCO status
> + //
> + IoWrite32(AcpiBase + R_PCH_TCO_STS, B_PCH_TCO_STS_SECOND_TO);
> +
> + //
> + // Enable reboot on TCO timeout
> + //
> + *RcrbGcsSaveValue = MmioRead32 (PMC_BASE_ADDRESS +
> R_PCH_PMC_PM_CFG);
> + MmioAnd8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG, (UINT8)
> ~B_PCH_PMC_PM_CFG_NO_REBOOT);
> +
> + //
> + // Set TCO reload value (interval *.6s)
> + //
> + IoWrite32(AcpiBase + R_PCH_TCO_TMR,
> (UINT32)(PbtnDisableInterval<<16));
> +
> + //
> + // Force TCO to load new value
> + //
> + IoWrite8(AcpiBase + R_PCH_TCO_RLD, 4);
> +
> + //
> + // Clear second TCO status
> + //
> + IoWrite32(AcpiBase + R_PCH_TCO_STS, B_PCH_TCO_STS_SECOND_TO);
> +
> + //
> + // Start TCO timer running
> + //
> + TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);
> + TmpWord &= ~(B_PCH_TCO_CNT_TMR_HLT);
> + IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Disables the TCO timer. This is used after writing the clock registers.
> +
> + @param RcrbGcsRestoreValue Value saved in PpiEnableTcoReset so that
> it can
> + restored.
> +
> + @retval EFI_STATUS
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +DisableTcoReset (
> + OUT UINT32 RcrbGcsRestoreValue
> + )
> +{
> + UINT16 TmpWord;
> + UINT16 AcpiBase;
> + EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL *WatchdogTimerProtocol;
> + EFI_STATUS Status;
> +
> + //
> + // Read ACPI Base Address
> + //
> + AcpiBase = PchLpcPciCfg16(R_PCH_LPC_ACPI_BASE) &
> B_PCH_LPC_ACPI_BASE_BAR;
> +
> + //
> + // Stop the TCO timer
> + //
> + TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);
> + TmpWord |= B_PCH_TCO_CNT_TMR_HLT;
> + IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);
> +
> + //
> + // Get Watchdog Timer protocol.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiWatchdogTimerDriverProtocolGuid,
> + NULL,
> + (VOID **)&WatchdogTimerProtocol
> + );
> +
> + //
> + // If the protocol is present, shut off the Timer as we enter BDS
> + //
> + if (!EFI_ERROR(Status)) {
> + WatchdogTimerProtocol->AllowKnownReset(FALSE);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +
> + Updates the feature policies according to the setup variable.
> +
> + @retval Returns VOID
> +
> +**/
> +VOID
> +InitTcoReset (
> + )
> +{
> + EFI_HANDLE Handle;
> + EFI_STATUS Status;
> +
> + Handle = NULL;
> + Status = gBS->InstallProtocolInterface (
> + &Handle,
> + &gEfiTcoResetProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + &mTcoResetProtocol
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IdccInfo.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IdccInfo.c
> new file mode 100644
> index 0000000000..3b3e4b4c82
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/IdccInfo.c
> @@ -0,0 +1,72 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + IdccInfo.c
> +
> +Abstract:
> +
> + Platform information used by IDCC.
> +
> +Revision History
> +
> +--*/
> +
> +#include "PlatformDxe.h"
> +
> +#include <Guid/IdccData.h>
> +
> +extern EFI_GUID mPlatformDriverGuid;
> +
> +
> +EFI_STATUS
> +WriteIdccInfo (
> + )
> +{
> + EFI_STATUS Status;
> + EFI_DATA_HUB_PROTOCOL *DataHub;
> + UINT8 Ratio;
> + EFI_IDCC_PROCESSOR_RATIO ProcRatio;
> +
> + //
> + // Locate the data hub protocol
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiDataHubProtocolGuid,
> + NULL,
> + (VOID **) &DataHub
> + );
> +
> + //
> + // Find processor actual ratio
> + //
> + Ratio = 15; //Temporary - some dummy value.
> +
> + //
> + // Fill in IDCC Type 5 structure
> + //
> + ProcRatio.IdccHeader.Type = EFI_IDCC_PROC_RATIO_TYPE;
> + ProcRatio.IdccHeader.RecordLength =
> sizeof(EFI_IDCC_PROCESSOR_RATIO);
> + ProcRatio.ProcessorRatio = Ratio;
> +
> + //
> + // Write data to the data hub
> + //
> + Status = DataHub->LogData (
> + DataHub,
> + &gIdccDataHubGuid,
> + &mPlatformDriverGuid,
> + EFI_DATA_RECORD_CLASS_DATA,
> + &ProcRatio,
> + sizeof(EFI_IDCC_PROCESSOR_RATIO)
> + );
> +
> + return Status;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.c
> new file mode 100644
> index 0000000000..09e7fe3113
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.c
> @@ -0,0 +1,161 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + LegacySpeaker.c
> +
> +Abstract:
> +
> + This file implements DXE for Legacy Speaker.
> +
> +--*/
> +
> +#include "LegacySpeaker.h"
> +
> +/**
> +
> + This function will enable the speaker to generate beep
> +
> + @retval EFI_STATUS
> +
> +**/
> +EFI_STATUS
> +TurnOnSpeaker (
> + )
> +{
> + UINT8 Data;
> + Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);
> + Data |= 0x03;
> + IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +
> + This function will stop beep from speaker.
> +
> + @retval Status
> +
> +**/
> +EFI_STATUS
> +TurnOffSpeaker (
> + )
> +{
> + UINT8 Data;
> +
> + Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);
> + Data &= 0xFC;
> + IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Generate beep sound based upon number of beeps and duration of the
> beep
> +
> + @param NumberOfBeeps Number of beeps which user want to produce
> + @param BeepDuration Duration for speaker gate need to be enabled
> + @param TimeInterval Interval between each beep
> +
> + @retval Does not return if the reset takes place.
> + EFI_INVALID_PARAMETER If ResetType is invalid.
> +
> +**/
> +EFI_STATUS
> +OutputBeep (
> + IN UINTN NumberOfBeep,
> + IN UINTN BeepDuration,
> + IN UINTN TimeInterval
> + )
> +{
> + UINTN Num;
> +
> + for (Num=0; Num < NumberOfBeep; Num++) {
> + TurnOnSpeaker ();
> + //
> + // wait some time,at least 120us
> + //
> + gBS->Stall (BeepDuration);
> + TurnOffSpeaker();
> + gBS->Stall (TimeInterval);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function will program the speaker tone frequency. The value should
> be with 64k
> + boundary since it takes only 16 bit value which gets programmed in two
> step IO opearattion
> +
> + @param Frequency A value which should be 16 bit only.
> +
> + @retval EFI_SUCESS
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +ProgramToneFrequency (
> + IN EFI_SPEAKER_IF_PROTOCOL * This,
> + IN UINT16 Frequency
> + )
> +{
> + UINT8 Data;
> +
> + Data = 0xB6;
> + IoWrite8(EFI_TIMER_CONTROL_PORT, Data);
> +
> + Data = (UINT8)(Frequency & 0x00FF);
> + IoWrite8(EFI_TIMER_2_PORT, Data);
> + Data = (UINT8)((Frequency & 0xFF00) >> 8);
> + IoWrite8(EFI_TIMER_2_PORT, Data);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function will generate the beep for specified duration.
> +
> + @param NumberOfBeeps Number of beeps which user want to produce
> + @param BeepDuration Duration for speaker gate need to be enabled
> + @param TimeInterval Interval between each beep
> +
> + @retval EFI_STATUS
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +GenerateBeepTone (
> + IN EFI_SPEAKER_IF_PROTOCOL * This,
> + IN UINTN NumberOfBeeps,
> + IN UINTN BeepDuration,
> + IN UINTN TimeInterval
> + )
> +{
> +
> + if ((NumberOfBeeps == 1) && (BeepDuration == 0) && (TimeInterval == 0))
> {
> + TurnOnSpeaker ();
> + return EFI_SUCCESS;
> + }
> +
> + if ((NumberOfBeeps == 0) && (BeepDuration == 0) && (TimeInterval == 0))
> {
> + TurnOffSpeaker ();
> + return EFI_SUCCESS;
> + }
> +
> + if (BeepDuration == 0) {
> + BeepDuration = EFI_DEFAULT_SHORT_BEEP_DURATION;
> + }
> +
> + if (TimeInterval == 0) {
> + TimeInterval = EFI_DEFAULT_BEEP_TIME_INTERVAL;
> + }
> +
> + OutputBeep (NumberOfBeeps, BeepDuration, TimeInterval);
> + return EFI_SUCCESS;
> +
> +
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.h
> new file mode 100644
> index 0000000000..0ab39b78fa
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.h
> @@ -0,0 +1,69 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + LegacySpeaker.h
> +
> +Abstract:
> +
> + Speaker enabling related data
> +
> +--*/
> +
> +#ifndef _DXE_LEGACY_SPEAKER_H
> +#define _DXE_LEGACY_SPEAKER_H
> +
> +#include "PlatformDxe.h"
> +
> +//
> +// Speaker Related Port Information
> +//
> +#define EFI_TIMER_COUNTER_PORT 0x40
> +#define EFI_TIMER_CONTROL_PORT 0x43
> +#define EFI_TIMER_2_PORT 0x42
> +#define EFI_SPEAKER_CONTROL_PORT 0x61
> +
> +#define EFI_SPEAKER_OFF_MASK 0xFC
> +
> +#define EFI_DEFAULT_BEEP_FREQUENCY 0x500
> +
> +//
> +// Default Intervals/Beep Duration
> +//
> +#define EFI_DEFAULT_LONG_BEEP_DURATION 0x70000
> +#define EFI_DEFAULT_SHORT_BEEP_DURATION 0x50000
> +#define EFI_DEFAULT_BEEP_TIME_INTERVAL 0x20000
> +
> +
> +EFI_STATUS
> +EFIAPI
> +ProgramToneFrequency (
> + IN EFI_SPEAKER_IF_PROTOCOL * This,
> + IN UINT16 Frequency
> + );
> +
> +
> +EFI_STATUS
> +EFIAPI
> +GenerateBeepTone (
> + IN EFI_SPEAKER_IF_PROTOCOL * This,
> + IN UINTN NumberOfBeeps,
> + IN UINTN BeepDuration,
> + IN UINTN TimeInterval
> + );
> +
> +EFI_STATUS
> +TurnOnSpeaker (
> + );
> +
> +EFI_STATUS
> +TurnOffSpeaker (
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.c
> new file mode 100644
> index 0000000000..af466ce96d
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.c
> @@ -0,0 +1,582 @@
> +/*++
> + This file contains 'Framework Code' and is licensed as such
> + under the terms of your license agreement with Intel or your
> + vendor. This file may not be modified, except as allowed by
> + additional terms of your license agreement.
> +--*/
> +/*++
> +
> +Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + Observable.c
> +
> +Abstract:
> +
> + The following contains all of the implementation for the Observable
> protocol. The
> + protocol uses the observer design pattern to provide a way to publish
> events and
> + to subscribe to those events so that a callback will be performed at the
> time of
> + the event. The observables and subscribers are maintained by the static
> tree,
> + mObservableDb. The difference between this protocol and the existing
> event protocol
> + that exists within the EFI framework is that this protocol allows for
> parameters
> + to be passed to the subscribed callbacks that can contain up to date
> context.
> +
> +--*/
> +
> +#include "Observable.h"
> +
> +static OBS_TREE* mObservableDb = NULL;
> +static EFI_HANDLE mObservableHandle = NULL;
> +static OBS_OBSERVABLE_PROTOCOL mObservable = {
> + AddObservable,
> + RemoveObservable,
> + Subscribe,
> + Unsubscribe,
> + Publish,
> + RemoveAllObservables
> +};
> +
> +/** Install observable protocol.
> + *
> + * Install interface and initialize the observable protocol.
> + *
> + * @param VOID No parameters.
> + *
> + * @return EFI_SUCCESS Successfully installed and initialized the protocol.
> + **/
> +EFI_STATUS
> +InitializeObservableProtocol(
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> +
> + //
> + // Install protocol.
> + //
> + Status = gBS->InstallProtocolInterface (
> + &mObservableHandle,
> + &gObservableProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + &mObservable
> + );
> +
> + return Status;
> +}
> +
> +/** Deletes a subscriber
> + *
> + * This function removes the subscriber pointed to by Head.
> + *
> + * @param OBS_TREE* Head Points to the current subscriber.
> + *
> + * @return OBS_TREE* Returns the tree after successfully removing the
> subscriber.
> + **/
> +OBS_LEAF*
> +DeleteSubscriber(
> + OBS_LEAF* Head
> + )
> +{
> + OBS_LEAF* Temp;
> +
> + if (Head) {
> + Temp = Head;
> + Head = Head->Next;
> + gBS->FreePool(Temp);
> + }
> +
> + return Head;
> +}
> +
> +/** Finds and deletes all subscribers
> + *
> + * This function iterates recursively through the existing subscribers and
> delets them all.
> + *
> + * @param OBS_TREE* Head Points to the current subscriber.
> + *
> + * @return OBS_TREE* Returns the tree after successfully removing the
> subscribers.
> + **/
> +OBS_LEAF*
> +DeleteAllSubscribers(
> + OBS_LEAF* Head
> + )
> +{
> + if (Head) {
> + if (Head->Next) {
> + //
> + // We aren't at the end of the list yet.
> + //
> + Head->Next = DeleteAllSubscribers(Head->Next);
> + }
> +
> + //
> + // At the end, so delete the subscriber.
> + //
> + Head = DeleteSubscriber(Head);
> + }
> +
> + return Head;
> +}
> +
> +/** Deletes an observable
> + *
> + * This function removes the observable pointed to by Head.
> + *
> + * @param OBS_TREE* Head Points to the current observable.
> + *
> + * @return OBS_TREE* Returns the tree after successfully removing the
> observable.
> + **/
> +OBS_TREE*
> +DeleteObservable(
> + OBS_TREE* Head
> + )
> +{
> + OBS_TREE* Temp;
> +
> + if (Head) {
> + Temp = Head;
> + Head = Head->Next;
> + gBS->FreePool(Temp);
> + }
> +
> + return Head;
> +}
> +
> +/** Finds and deletes all observables
> + *
> + * This function iterates recursively through the existing observables
> database and, starting with
> + * the last most observable, deletes all of its subscribers, then deletes the
> observable itself.
> + *
> + * @param OBS_TREE* Head Points to the current observable.
> + *
> + * @return OBS_TREE* Returns the tree after successfully removing the
> observables.
> + **/
> +OBS_TREE*
> +DeleteAllObservables(
> + OBS_TREE* Head
> + )
> +{
> + if (Head) {
> + if (Head->Next) {
> + //
> + // We aren't at the end of the list yet.
> + //
> + Head->Next = DeleteAllObservables(Head->Next);
> + }
> +
> + //
> + // This is the end of the list of observables.
> + //
> + Head->Leaf = DeleteAllSubscribers(Head->Leaf);
> +
> + //
> + // Subscribers are deleted, so now delete the observable.
> + //
> + Head = DeleteObservable(Head);
> + }
> +
> + return Head;
> +}
> +
> +/** Finds and deletes observable
> + *
> + * This function iterates recursively through the existing observable
> database in order to find the one
> + * specified by ReferenceGuid so that it can be deleted. If the requested
> observable is found, before it
> + * is deleted, all of the subscribers that are listening to this observable are
> deleted.
> + *
> + * @param OBS_TREE* Head Points to the current observable.
> + * EFI_GUID ReferenceGuid Corresponds to the observable that
> we're looking for.
> + *
> + * @return OBS_TREE* Returns the tree after successfully removing (or
> not finding) the observable.
> + **/
> +OBS_TREE*
> +FindAndDeleteObservable(
> + OBS_TREE* Head,
> + EFI_GUID ReferenceGuid
> + )
> +{
> + if (Head) {
> + if (CompareMem(&(Head->ObservableGuid), &ReferenceGuid,
> sizeof(ReferenceGuid)) == 0) {
> + //
> + // We found the observable. Delete all of it's subscribers, first.
> + //
> + Head->Leaf = DeleteAllSubscribers(Head->Leaf);
> + //
> + // Now we can safely remove the observable.
> + //
> + Head = DeleteObservable(Head);
> + } else {
> + //
> + // Not found. Keep searching.
> + //
> + Head->Next = FindAndDeleteObservable(Head->Next, ReferenceGuid);
> + }
> + }
> +
> + return Head;
> +}
> +
> +/** Finds and deletes subscriber
> + *
> + * This function iterates recursively through the existing subscribers that are
> listening to the
> + * observable that was found when this function was called.
> + *
> + * @param OBS_TREE* Head Points to the current subscriber.
> + * OBS_CALLBACK CallbackInterface This is the subscriber that is
> requested be removed.
> + *
> + * @return OBS_TREE* Returns the tree after successfully removing (or
> not finding) the subscriber.
> + **/
> +OBS_LEAF*
> +_FindAndDeleteSubscriber(
> + OBS_LEAF* Head,
> + OBS_CALLBACK CallbackInterface
> + )
> +{
> + if (Head) {
> + if (Head->Observer == CallbackInterface) {
> + //
> + // Found it. Now let's delete it.
> + //
> + Head = DeleteSubscriber(Head);
> + } else {
> + //
> + // Not found. Keep searching.
> + //
> + Head->Next = _FindAndDeleteSubscriber(Head->Next,
> CallbackInterface);
> + }
> + }
> +
> + return Head;
> +}
> +
> +/** Finds and deletes subscriber
> + *
> + * This function iterates recursively through the existing observables
> database until it either finds
> + * a matching guid or reaches the end of the list. After finding a match, it
> calls a helper function,
> + * _FindAndDeleteSubscriber. At this point, all responsibility for finding and
> deleting the subscriber
> + * lies on the helper function.
> + *
> + * @param OBS_TREE* Head Points to the current observable.
> + * EFI_GUID ReferenceGuid Corresponds to the observable that
> we're looking for.
> + * OBS_CALLBACK CallbackInterface This is the subscriber that is
> requested be removed.
> + *
> + * @return OBS_TREE* Returns the tree after successfully removing (or
> not finding) the subscriber.
> + **/
> +OBS_TREE*
> +FindAndDeleteSubscriber(
> + IN OUT OBS_TREE* Head,
> + IN EFI_GUID ReferenceGuid,
> + IN OBS_CALLBACK CallbackInterface
> + )
> +{
> + if (Head) {
> + if (CompareMem(&(Head->ObservableGuid), &ReferenceGuid,
> sizeof(ReferenceGuid)) == 0) {
> + //
> + // We found the observer that matches ReferenceGuid. Find and delete
> the subscriber that is
> + // listening to it.
> + //
> + Head->Leaf = _FindAndDeleteSubscriber(Head->Leaf, CallbackInterface);
> + } else {
> + //
> + // Not found. Keep searching.
> + //
> + Head->Next = FindAndDeleteSubscriber(Head->Next, ReferenceGuid,
> CallbackInterface);
> + }
> + }
> +
> + return Head;
> +}
> +
> +/** Remove all observables.
> + *
> + * Remove all observable guids and all interfaces subscribed to them.
> + *
> + * @param VOID No parameters.
> + *
> + * @return EFI_SUCCESS Successfully removed all observables and
> subscribed interfaces.
> + **/
> +EFI_STATUS
> +EFIAPI
> +RemoveAllObservables(
> + VOID
> + )
> +{
> + mObservableDb = DeleteAllObservables(mObservableDb);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/** Subscribe an interface with an observable guid.
> + *
> + * Use this to register a callback function with a guid. The function provided
> by CallbackInterface will be executed
> + * whenever the appropriate observable instance specified by
> ReferenceGuid calls Publish.
> + *
> + * @param EFI_GUID ReferenceGuid The observable guid that
> the callback interface will subscribe to.
> + * OBS_CASLLBACK CallbackInterface A pointer to the function
> that is subscribing to the observable.
> + *
> + * @return EFI_SUCCESS Successfully subscribed the interface to the
> observable guid.
> + * EFI_NOT_FOUND No match could be found between the
> provided guid and existing observables.
> + * EFI_OUT_OF_RESOURCES Could not subscribe to this observer due
> to resource limitations.
> + * EFI_INVALID_PARAMETER Interface is already subscribed to this
> observer.
> + **/
> +EFI_STATUS
> +EFIAPI
> +Subscribe (
> + IN EFI_GUID ReferenceGuid,
> + IN OBS_CALLBACK CallbackInterface
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + OBS_TREE* TempTree = NULL;
> + OBS_LEAF* Last = NULL;
> + OBS_LEAF* TempLeaf = NULL;
> + OBS_LEAF* NewLeaf = NULL;
> + BOOLEAN Found = FALSE;
> +
> + if (mObservableDb != NULL) {
> + //
> + // Find the observable guid that we're looking for.
> + //
> + for (TempTree = mObservableDb; TempTree != NULL; TempTree =
> TempTree->Next) {
> + if (CompareMem(&(TempTree->ObservableGuid), &ReferenceGuid,
> sizeof(ReferenceGuid)) == 0) {
> + Found = TRUE;
> + break;
> + }
> + }
> + if (Found) {
> + //
> + // Prepare to add a new leaf.
> + //
> + NewLeaf = AllocateZeroPool(sizeof(OBS_LEAF));
> + if (!NewLeaf) {
> + Status = EFI_OUT_OF_RESOURCES;
> + } else {
> + NewLeaf->Next = NULL;
> + NewLeaf->Observer = CallbackInterface;
> + //
> + // Go to the end of the list of observers.
> + //
> + if (TempTree->Leaf != NULL) {
> + //
> + // First check to see if this is a duplicate observer.
> + //
> + Found = FALSE;
> + TempLeaf = TempTree->Leaf;
> + do {
> + Last = TempLeaf;
> + if (TempLeaf->Observer == CallbackInterface) {
> + //
> + // It is, so let's abort this process.
> + //
> + Found = TRUE;
> + break;
> + }
> + TempLeaf = TempLeaf->Next;
> + } while (TempLeaf != NULL);
> + TempLeaf = Last;
> +
> + //
> + // Check for duplicates.
> + //
> + if (Found) {
> + gBS->FreePool(NewLeaf);
> + Status = EFI_INVALID_PARAMETER;
> + } else {
> + //
> + // At this point, TempLeaf->Next will be the end of the list.
> + //
> + TempLeaf->Next = NewLeaf;
> + }
> + } else {
> + //
> + // There are no observers listening to this guid. Start a new list.
> + //
> + TempTree->Leaf = NewLeaf;
> + }
> + }
> + } else {
> + Status = EFI_NOT_FOUND;
> + }
> + } else {
> + Status = EFI_NOT_FOUND;
> + }
> +
> + return Status;
> +}
> +
> +/** Unsubscribe an interface with an observable guid.
> + *
> + * Use this to remove an interface from the callback list associated with an
> observable guid.
> + *
> + * @param EFI_GUID ReferenceGuid The observable guid to
> unsubscribe the interface from.
> + * OBS_NOTIFY_INTERFACE NotifyCallback A pointer to the interface
> that is being unsubscribed.
> + *
> + * @return EFI_SUCCESS Successfully unsubscribed the interface from
> the observable guid.
> + **/
> +EFI_STATUS
> +EFIAPI
> +Unsubscribe (
> + IN EFI_GUID ReferenceGuid,
> + IN OBS_CALLBACK CallbackInterface
> + )
> +{
> + mObservableDb = FindAndDeleteSubscriber(mObservableDb,
> ReferenceGuid, CallbackInterface);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/** Notify observing functions.
> + *
> + * Use this to notify all functions who are subscribed to the guid specified by
> ReferenceGuid.
> + *
> + * @param EFI_GUID ReferenceGuid The observable guid that
> contains the the list of interfaces to be notified.
> + * VOID* Data Parameter context to be passed to the
> notification function.
> + *
> + * @return EFI_SUCCESS Successfully notified all observers listening to
> this guid.
> + * EFI_NOT_FOUND No match could be found between the provided
> guid and existing observables.
> + **/
> +EFI_STATUS
> +EFIAPI
> +Publish (
> + IN EFI_GUID ReferenceGuid,
> + IN OUT VOID* Data
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + OBS_TREE* TempTree = NULL;
> + OBS_LEAF* TempLeaf = NULL;
> + BOOLEAN Found = FALSE;
> +
> + if (mObservableDb != NULL) {
> + //
> + // Find the observable guid that we're looking for.
> + //
> + for (TempTree = mObservableDb; TempTree != NULL; TempTree =
> TempTree->Next) {
> + if (CompareMem(&(TempTree->ObservableGuid), &ReferenceGuid,
> sizeof(ReferenceGuid)) == 0) {
> + Found = TRUE;
> + break;
> + }
> + }
> + if (Found) {
> + //
> + // Notify every listener by performing each provided callback.
> + //
> + for (TempLeaf = TempTree->Leaf; TempLeaf != NULL; TempLeaf =
> TempLeaf->Next) {
> + if (TempLeaf->Observer != NULL) {
> + //
> + // Execute the callback.
> + //
> + TempLeaf->Observer(Data);
> + }
> + }
> + } else {
> + Status = EFI_NOT_FOUND;
> + }
> + } else {
> + Status = EFI_NOT_FOUND;
> + }
> +
> + return Status;
> +}
> +
> +/** Creates a new observable.
> + *
> + * Create a new observable that can be observed with the use of Subscribe
> function.
> + *
> + * @param EFI_GUID ReferenceGuid The observable guid to add.
> + *
> + * @return EFI_SUCCESS Successfully added observable.
> + * EFI_INVALID_PARAMETER Observable already exists.
> + **/
> +EFI_STATUS
> +EFIAPI
> +AddObservable (
> + IN EFI_GUID ReferenceGuid
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + OBS_TREE* TempTree = NULL;
> + OBS_TREE* Last = NULL;
> + OBS_TREE* NewTree = NULL;
> + BOOLEAN Found = FALSE;
> +
> + if (mObservableDb != NULL) {
> + if (mObservableDb->Next != NULL) {
> + //
> + // Iterate to the end of the observable list while checking to see if we
> aren't creating a duplicate.
> + //
> + TempTree = mObservableDb->Next;
> + do {
> + Last = TempTree;
> + if (CompareMem(&(TempTree->ObservableGuid), &ReferenceGuid,
> sizeof(ReferenceGuid)) == 0) {
> + Found = TRUE;
> + break;
> + }
> + TempTree = TempTree->Next;
> + } while (TempTree != NULL);
> + TempTree = Last;
> + } else {
> + TempTree = mObservableDb;
> + }
> + if (Found) {
> + //
> + // Duplicate, so reject the parameter.
> + //
> + Status = EFI_INVALID_PARAMETER;
> + } else {
> + //
> + // TempTree->Next is our target. Prepare to add a new tree link.
> + //
> + NewTree = AllocateZeroPool(sizeof(OBS_TREE));
> + if (NewTree) {
> + NewTree->Next = NULL;
> + NewTree->Leaf = NULL;
> + CopyMem(&(NewTree->ObservableGuid), &ReferenceGuid,
> sizeof(ReferenceGuid));
> + TempTree->Next = NewTree;
> + } else {
> + Status = EFI_OUT_OF_RESOURCES;
> + }
> + }
> + } else {
> + //
> + // mObservableDb has not been created yet. Let's do that.
> + //
> + NewTree = AllocateZeroPool(sizeof(OBS_TREE));
> + if (NewTree) {
> + NewTree->Next = NULL;
> + NewTree->Leaf = NULL;
> + CopyMem(&(NewTree->ObservableGuid), &ReferenceGuid,
> sizeof(ReferenceGuid));
> + mObservableDb = NewTree;
> + } else {
> + Status = EFI_OUT_OF_RESOURCES;
> + }
> + }
> +
> + return Status;
> +}
> +
> +/** Remove an observable.
> + *
> + * Remove an observable so that it can no longer be subscribed to. In
> addition, unsubscribe any functions
> + * that are subscribed to this guid.
> + *
> + * @param EFI_GUID ReferenceGuid The observable guid to
> remove.
> + *
> + * @return EFI_SUCCESS Successfully removed observable.
> + **/
> +EFI_STATUS
> +EFIAPI
> +RemoveObservable (
> + IN EFI_GUID ReferenceGuid
> + )
> +{
> + mObservableDb = FindAndDeleteObservable(mObservableDb,
> ReferenceGuid);
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.h
> new file mode 100644
> index 0000000000..f46efe0f1b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.h
> @@ -0,0 +1,137 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + Observable.h
> +
> +Abstract:
> +
> + Prototypes for Observable protocol implementation
> +--*/
> +
> +#ifndef _OBSERVABLE_H_
> +#define _OBSERVABLE_H_
> +#include "PlatformDxe.h"
> +#include "Protocol/Observable.h"
> +
> +//
> +// Prototypes
> +//
> +
> +/** Install observable protocol.
> + *
> + * Install interface and initialize the observable protocol.
> + *
> + * @param VOID No parameters.
> + *
> + * @return EFI_SUCCESS Successfully installed and initialized the protocol.
> + **/
> +EFI_STATUS
> +InitializeObservableProtocol(
> + VOID
> + );
> +
> +/** Remove all observables.
> + *
> + * Remove all observable guids and all interfaces subscribed to them.
> + *
> + * @param VOID No parameters.
> + *
> + * @return EFI_SUCCESS Successfully removed all observables and
> subscribed interfaces.
> + **/
> +EFI_STATUS
> +EFIAPI
> +RemoveAllObservables(
> + VOID
> + );
> +
> +/** Subscribe an interface with an observable guid.
> + *
> + * Use this to register a callback function with a guid. The function provided
> by CallbackInterface will be executed
> + * whenever the appropriate observable instance specified by
> ReferenceGuid calls Publish.
> + *
> + * @param EFI_GUID ReferenceGuid The observable guid that
> the callback interface will subscribe to.
> + * OBS_CALLBACK CallbackInterface A pointer to the function that
> is subscribing to the observable.
> + *
> + * @return EFI_SUCCESS Successfully subscribed the interface to the
> observable guid.
> + * EFI_NOT_FOUND No match could be found between the
> provided guid and existing observables.
> + * EFI_OUT_OF_RESOURCES Could not subscribe to this observer due
> to resource limitations.
> + * EFI_INVALID_PARAMETER Interface is already subscribed to this
> observer.
> + **/
> +EFI_STATUS
> +EFIAPI
> +Subscribe (
> + IN EFI_GUID ReferenceGuid,
> + IN OBS_CALLBACK CallbackInterface
> + );
> +
> +/** Unsubscribe an interface with an observable guid.
> + *
> + * Use this to remove an interface from the callback list associated with an
> observable guid.
> + *
> + * @param EFI_GUID ReferenceGuid The observable guid to
> unsubscribe the interface from.
> + * OBS_CALLBACK CallbackInterface A pointer to the interface that
> is being unsubscribed.
> + *
> + * @return EFI_SUCCESS Successfully unsubscribed the interface from
> the observable guid.
> + **/
> +EFI_STATUS
> +EFIAPI
> +Unsubscribe (
> + IN EFI_GUID ReferenceGuid,
> + IN OBS_CALLBACK CallbackInterface
> + );
> +
> +/** Notify observing functions.
> + *
> + * Use this to notify all functions who are subscribed to the guid specified by
> ReferenceGuid.
> + *
> + * @param EFI_GUID ReferenceGuid The observable guid that
> contains the list of interfaces to be notified.
> + * VOID* Data Parameter context to be passed to the
> subscribed function.
> + *
> + * @return EFI_SUCCESS Successfully notified all observers listening to
> this guid.
> + * EFI_NOT_FOUND No match could be found between the provided
> guid and existing observables.
> + **/
> +EFI_STATUS
> +EFIAPI
> +Publish (
> + IN EFI_GUID ReferenceGuid,
> + IN OUT VOID* Data
> + );
> +
> +/** Creates a new observable.
> + *
> + * Create a new observable that can be observed with the use of Subscribe
> function.
> + *
> + * @param EFI_GUID ReferenceGuid The observable guid to add.
> + *
> + * @return EFI_SUCCESS Successfully added observable.
> + * EFI_INVALID_PARAMETER Observable already exists.
> + **/
> +EFI_STATUS
> +EFIAPI
> +AddObservable (
> + IN EFI_GUID ReferenceGuid
> + );
> +
> +/** Remove an observable.
> + *
> + * Remove an observable so that it can no longer be subscribed to. In
> addition, unsubscribe any functions
> + * that are subscribed to this guid.
> + *
> + * @param EFI_GUID ReferenceGuid The observable guid to
> remove.
> + *
> + * @return EFI_SUCCESS Successfully removed observable.
> + **/
> +EFI_STATUS
> +EFIAPI
> +RemoveObservable (
> + IN EFI_GUID ReferenceGuid
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PciBus.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PciBus.h
> new file mode 100644
> index 0000000000..40c0d99392
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PciBus.h
> @@ -0,0 +1,379 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +
> +#ifndef _EFI_PCI_BUS_H_
> +#define _EFI_PCI_BUS_H_
> +
> +#include <PiDxe.h>
> +
> +#include <Protocol/LoadedImage.h>
> +#include <Protocol/PciHostBridgeResourceAllocation.h>
> +#include <Protocol/PciIo.h>
> +#include <Protocol/LoadFile2.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include <Protocol/PciHotPlugRequest.h>
> +#include <Protocol/DevicePath.h>
> +#include <Protocol/PciPlatform.h>
> +#include <Protocol/PciHotPlugInit.h>
> +#include <Protocol/Decompress.h>
> +#include <Protocol/BusSpecificDriverOverride.h>
> +#include <Protocol/IncompatiblePciDeviceSupport.h>
> +#include <Protocol/PciOverride.h>
> +#include <Protocol/PciEnumerationComplete.h>
> +
> +#include <Library/DebugLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/BaseLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/ReportStatusCodeLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PeCoffLib.h>
> +
> +#include <IndustryStandard/Pci.h>
> +#include <IndustryStandard/PeImage.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
> +typedef struct _PCI_BAR PCI_BAR;
> +
> +#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) +
> ((UINT32)Device << 3) + (UINT32)Function)
> +#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)
> +
> +#define EFI_PCI_IOV_POLICY_ARI 0x0001
> +#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
> +#define EFI_PCI_IOV_POLICY_MRIOV 0x0004
> +
> +typedef enum {
> + PciBarTypeUnknown = 0,
> + PciBarTypeIo16,
> + PciBarTypeIo32,
> + PciBarTypeMem32,
> + PciBarTypePMem32,
> + PciBarTypeMem64,
> + PciBarTypePMem64,
> + PciBarTypeIo,
> + PciBarTypeMem,
> + PciBarTypeMaxType
> +} PCI_BAR_TYPE;
> +
> +
> +#define VGABASE1 0x3B0
> +#define VGALIMIT1 0x3BB
> +
> +#define VGABASE2 0x3C0
> +#define VGALIMIT2 0x3DF
> +
> +#define ISABASE 0x100
> +#define ISALIMIT 0x3FF
> +
> +//
> +// PCI BAR parameters
> +//
> +struct _PCI_BAR {
> + UINT64 BaseAddress;
> + UINT64 Length;
> + UINT64 Alignment;
> + PCI_BAR_TYPE BarType;
> + BOOLEAN Prefetchable;
> + UINT8 MemType;
> + UINT16 Offset;
> +};
> +
> +//
> +// defined in PCI Card Specification, 8.0
> +//
> +#define PCI_CARD_MEMORY_BASE_0 0x1C
> +#define PCI_CARD_MEMORY_LIMIT_0 0x20
> +#define PCI_CARD_MEMORY_BASE_1 0x24
> +#define PCI_CARD_MEMORY_LIMIT_1 0x28
> +#define PCI_CARD_IO_BASE_0_LOWER 0x2C
> +#define PCI_CARD_IO_BASE_0_UPPER 0x2E
> +#define PCI_CARD_IO_LIMIT_0_LOWER 0x30
> +#define PCI_CARD_IO_LIMIT_0_UPPER 0x32
> +#define PCI_CARD_IO_BASE_1_LOWER 0x34
> +#define PCI_CARD_IO_BASE_1_UPPER 0x36
> +#define PCI_CARD_IO_LIMIT_1_LOWER 0x38
> +#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
> +#define PCI_CARD_BRIDGE_CONTROL 0x3E
> +
> +#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
> +#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
> +
> +#define PPB_BAR_0 0
> +#define PPB_BAR_1 1
> +#define PPB_IO_RANGE 2
> +#define PPB_MEM32_RANGE 3
> +#define PPB_PMEM32_RANGE 4
> +#define PPB_PMEM64_RANGE 5
> +#define PPB_MEM64_RANGE 0xFF
> +
> +#define P2C_BAR_0 0
> +#define P2C_MEM_1 1
> +#define P2C_MEM_2 2
> +#define P2C_IO_1 3
> +#define P2C_IO_2 4
> +
> +#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
> +#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
> +#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
> +#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
> +#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
> +#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
> +#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
> +
> +#define PCI_MAX_HOST_BRIDGE_NUM 0x0010
> +
> +//
> +// Define option for attribute
> +//
> +#define EFI_SET_SUPPORTS 0
> +#define EFI_SET_ATTRIBUTES 1
> +
> +#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
> +
> +struct _PCI_IO_DEVICE {
> + UINT32 Signature;
> + EFI_HANDLE Handle;
> + EFI_PCI_IO_PROTOCOL PciIo;
> + LIST_ENTRY Link;
> +
> + EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath;
> + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
> + EFI_LOAD_FILE2_PROTOCOL LoadFile2;
> +
> + //
> + // PCI configuration space header type
> + //
> + PCI_TYPE00 Pci;
> +
> + //
> + // Bus number, Device number, Function number
> + //
> + UINT8 BusNumber;
> + UINT8 DeviceNumber;
> + UINT8 FunctionNumber;
> +
> + //
> + // BAR for this PCI Device
> + //
> + PCI_BAR PciBar[PCI_MAX_BAR];
> +
> + //
> + // The bridge device this pci device is subject to
> + //
> + PCI_IO_DEVICE *Parent;
> +
> + //
> + // A linked list for children Pci Device if it is bridge device
> + //
> + LIST_ENTRY ChildList;
> +
> + //
> + // TRUE if the PCI bus driver creates the handle for this PCI device
> + //
> + BOOLEAN Registered;
> +
> + //
> + // TRUE if the PCI bus driver successfully allocates the resource required by
> + // this PCI device
> + //
> + BOOLEAN Allocated;
> +
> + //
> + // The attribute this PCI device currently set
> + //
> + UINT64 Attributes;
> +
> + //
> + // The attributes this PCI device actually supports
> + //
> + UINT64 Supports;
> +
> + //
> + // The resource decode the bridge supports
> + //
> + UINT32 Decodes;
> +
> + //
> + // TRUE if the ROM image is from the PCI Option ROM BAR
> + //
> + BOOLEAN EmbeddedRom;
> +
> + //
> + // The OptionRom Size
> + //
> + UINT64 RomSize;
> +
> + //
> + // The OptionRom Size
> + //
> + UINT64 RomBase;
> +
> + //
> + // TRUE if all OpROM (in device or in platform specific position) have been
> processed
> + //
> + BOOLEAN AllOpRomProcessed;
> +
> + //
> + // TRUE if there is any EFI driver in the OptionRom
> + //
> + BOOLEAN BusOverride;
> +
> + //
> + // A list tracking reserved resource on a bridge device
> + //
> + LIST_ENTRY ReservedResourceList;
> +
> + //
> + // A list tracking image handle of platform specific overriding driver
> + //
> + LIST_ENTRY OptionRomDriverList;
> +
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
> *ResourcePaddingDescriptors;
> + EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;
> +
> + BOOLEAN IsPciExp;
> +
> + //
> + // For SR-IOV
> + //
> + UINT8 PciExpressCapabilityOffset;
> + UINT32 AriCapabilityOffset;
> + UINT32 SrIovCapabilityOffset;
> + UINT32 MrIovCapabilityOffset;
> + PCI_BAR VfPciBar[PCI_MAX_BAR];
> + UINT32 SystemPageSize;
> + UINT16 InitialVFs;
> + UINT16 ReservedBusNum;
> +
> + //
> + // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
> + // but some chipsets support non-standard I/O window alignments less
> than 4K.
> + // This field is used to support this case.
> + //
> + UINT16 BridgeIoAlignment;
> +};
> +
> +#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
> + CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
> +
> +#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
> + CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
> +
> +#define PCI_IO_DEVICE_FROM_LINK(a) \
> + CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
> +
> +#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
> + CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
> +
> +
> +
> +//
> +// Global Variables
> +//
> +extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
> *gEfiIncompatiblePciDeviceSupport;
> +extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
> +extern EFI_COMPONENT_NAME_PROTOCOL
> gPciBusComponentName;
> +extern EFI_COMPONENT_NAME2_PROTOCOL
> gPciBusComponentName2;
> +extern BOOLEAN gFullEnumeration;
> +extern UINTN gPciHostBridgeNumber;
> +extern EFI_HANDLE
> gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
> +extern UINT64 gAllOne;
> +extern UINT64 gAllZero;
> +extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
> +extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
> +extern BOOLEAN mReserveIsaAliases;
> +extern BOOLEAN mReserveVgaAliases;
> +
> +/**
> + Macro that checks whether device is a GFX device.
> +
> + @param _p Specified device.
> +
> + @retval TRUE Device is a GFX device.
> + @retval FALSE Device is not a GFX device.
> +
> +**/
> +#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY,
> PCI_CLASS_DISPLAY_OTHER)
> +
> +/**
> + Test to see if this driver supports ControllerHandle. Any ControllerHandle
> + than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be
> supported.
> +
> + @param This Protocol instance pointer.
> + @param Controller Handle of device to test.
> + @param RemainingDevicePath Optional parameter use to pick a specific
> child
> + device to start.
> +
> + @retval EFI_SUCCESS This driver supports this device.
> + @retval EFI_ALREADY_STARTED This driver is already running on this
> device.
> + @retval other This driver does not support this device.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PciBusDriverBindingSupported (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE Controller,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
> + );
> +
> +/**
> + Start this driver on ControllerHandle and enumerate Pci bus and start
> + all device under PCI bus.
> +
> + @param This Protocol instance pointer.
> + @param Controller Handle of device to bind driver to.
> + @param RemainingDevicePath Optional parameter use to pick a specific
> child
> + device to start.
> +
> + @retval EFI_SUCCESS This driver is added to ControllerHandle.
> + @retval EFI_ALREADY_STARTED This driver is already running on
> ControllerHandle.
> + @retval other This driver does not support this device.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PciBusDriverBindingStart (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE Controller,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
> + );
> +
> +/**
> + Stop this driver on ControllerHandle. Support stopping any child handles
> + created by this driver.
> +
> + @param This Protocol instance pointer.
> + @param Controller Handle of device to stop driver on.
> + @param NumberOfChildren Number of Handles in ChildHandleBuffer. If
> number of
> + children is zero stop the entire bus driver.
> + @param ChildHandleBuffer List of Child Handles to Stop.
> +
> + @retval EFI_SUCCESS This driver is removed ControllerHandle.
> + @retval other This driver was not removed from this device.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PciBusDriverBindingStop (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE Controller,
> + IN UINTN NumberOfChildren,
> + IN EFI_HANDLE *ChildHandleBuffer
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c
> new file mode 100644
> index 0000000000..582d8627cd
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c
> @@ -0,0 +1,506 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + PciDevice.c
> +
> +Abstract:
> +
> + Platform Initialization Driver.
> +
> +Revision History
> +
> +--*/
> +
> +#include "PlatformDxe.h"
> +#include "Library/DxeServicesTableLib.h"
> +#include "PciBus.h"
> +#include "Guid/PciLanInfo.h"
> +
> +extern VOID *mPciLanInfo;
> +extern UINTN mPciLanCount;
> +
> +extern EFI_HANDLE mImageHandle;
> +extern SYSTEM_CONFIGURATION mSystemConfiguration;
> +
> +
> +VOID *mPciRegistration;
> +#define NCR_VENDOR_ID 0x1000
> +#define ATI_VENDOR_ID 0x1002
> +#define INTEL_VENDOR_ID 0x8086
> +#define ATI_RV423_ID 0x5548
> +#define ATI_RV423_ID2 0x5d57
> +#define ATI_RV380_ID 0x3e50
> +#define ATI_RV370_ID 0x5b60
> +#define SI_VENDOR_ID 0x1095
> +#define SI_SISATA_ID 0x3114
> +#define SI_SIRAID_PCIUNL 0x40
> +#define INTEL_82573E_IDER 0x108D
> +
> +typedef struct {
> + UINT8 ClassCode;
> + UINT8 SubClassCode;
> + UINT16 VendorId;
> + UINT16 DeviceId;
> +} BAD_DEVICE_TABLE;
> +
> +BAD_DEVICE_TABLE BadDeviceTable[] = {
> +
> {(UINT8)PCI_CLASS_MASS_STORAGE,(UINT8)PCI_CLASS_MASS_STORAGE_S
> CSI,(UINT16)NCR_VENDOR_ID, (UINT16)0xffff}, // Any NCR cards
> +
> {(UINT8)PCI_CLASS_MASS_STORAGE,(UINT8)PCI_CLASS_MASS_STORAGE_I
> DE,(UINT16)INTEL_VENDOR_ID, (UINT16)INTEL_82573E_IDER}, // Intel
> i82573E Tekoa GBit Lan IDE-R
> + {(UINT8)0xff,(UINT8)0xff,(UINT16)0xffff,(UINT16)0xffff}
> + };
> +
> +EFI_STATUS
> +PciBusDriverHook (
> + )
> +{
> + EFI_STATUS Status;
> + EFI_EVENT FilterEvent;
> +
> + //
> + // Register for callback to PCI I/O protocol
> + //
> + Status = gBS->CreateEvent (
> + EVT_NOTIFY_SIGNAL,
> + TPL_CALLBACK,
> + PciBusEvent,
> + NULL,
> + &FilterEvent
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // Register for protocol notifications on this event
> + //
> + Status = gBS->RegisterProtocolNotify (
> + &gEfiPciIoProtocolGuid,
> + FilterEvent,
> + &mPciRegistration
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return EFI_SUCCESS;
> +}
> +
> +VOID
> +InitBadBars(
> + IN EFI_PCI_IO_PROTOCOL *PciIo,
> + IN UINT16 VendorId,
> + IN UINT16 DeviceId
> + )
> +{
> +
> + UINT64 BaseAddress = 0;
> + UINT64 TempBaseAddress = 0;
> + UINT8 RevId = 0;
> + UINT32 Bar;
> + UINT64 IoSize;
> + UINT64 MemSize;
> + UINTN MemSizeBits;
> +
> + switch ( VendorId) {
> + case ATI_VENDOR_ID:
> + //
> + // ATI fix-ups. At this time all ATI cards in BadDeviceTable
> + // have same problem in that OPROM BAR needs to be increased.
> + //
> + Bar = 0x30 ;
> + //
> + // Get original BAR address
> + //
> + PciIo->Pci.Read (
> + PciIo,
> + EfiPciIoWidthUint32,
> + Bar,
> + 1,
> + (VOID *) &BaseAddress
> + );
> + //
> + // Find BAR size
> + //
> + TempBaseAddress = 0xffffffff;
> + PciIo->Pci.Write (
> + PciIo,
> + EfiPciIoWidthUint32,
> + Bar,
> + 1,
> + (VOID *) &TempBaseAddress
> + );
> + PciIo->Pci.Read (
> + PciIo,
> + EfiPciIoWidthUint32,
> + Bar,
> + 1,
> + (VOID *) &TempBaseAddress
> + );
> + TempBaseAddress &= 0xfffffffe;
> + MemSize = 1;
> + while ((TempBaseAddress & 0x01) == 0) {
> + TempBaseAddress = TempBaseAddress >> 1;
> + MemSize = MemSize << 1;
> + }
> +
> + //
> + // Free up allocated memory memory and re-allocate with increased size.
> + //
> + gDS->FreeMemorySpace (
> + BaseAddress,
> + MemSize
> + );
> + //
> + // Force new alignment
> + //
> + MemSize = 0x8000000;
> + MemSizeBits = 28;
> +
> + gDS->AllocateMemorySpace (
> + EfiGcdAllocateAnySearchBottomUp,
> + EfiGcdMemoryTypeMemoryMappedIo,
> + MemSizeBits, // Alignment
> + MemSize,
> + &BaseAddress,
> + mImageHandle,
> + NULL
> + );
> + PciIo->Pci.Write (
> + PciIo,
> + EfiPciIoWidthUint32,
> + Bar,
> + 1,
> + (VOID *) &BaseAddress
> + );
> +
> + break;
> + case NCR_VENDOR_ID:
> +#define MIN_NCR_IO_SIZE 0x800
> +#define NCR_GRAN 11 // 2**11 = 0x800
> + //
> + // NCR SCSI cards like 8250S lie about IO needed. Assign as least 0x80.
> + //
> + for (Bar = 0x10; Bar < 0x28; Bar+= 4) {
> +
> + PciIo->Pci.Read (
> + PciIo,
> + EfiPciIoWidthUint32,
> + Bar,
> + 1,
> + (VOID *) &BaseAddress
> + );
> + if (BaseAddress && 0x01) {
> + TempBaseAddress = 0xffffffff;
> + PciIo->Pci.Write (
> + PciIo,
> + EfiPciIoWidthUint32,
> + Bar,
> + 1,
> + (VOID *) &TempBaseAddress
> + );
> + TempBaseAddress &= 0xfffffffc;
> + IoSize = 1;
> + while ((TempBaseAddress & 0x01) == 0) {
> + TempBaseAddress = TempBaseAddress >> 1;
> + IoSize = IoSize << 1;
> + }
> + if (IoSize < MIN_NCR_IO_SIZE) {
> + gDS->FreeIoSpace (
> + BaseAddress,
> + IoSize
> + );
> +
> + gDS->AllocateIoSpace (
> + EfiGcdAllocateAnySearchTopDown,
> + EfiGcdIoTypeIo,
> + NCR_GRAN, // Alignment
> + MIN_NCR_IO_SIZE,
> + &BaseAddress,
> + mImageHandle,
> + NULL
> + );
> + TempBaseAddress = BaseAddress + 1;
> + PciIo->Pci.Write (
> + PciIo,
> + EfiPciIoWidthUint32,
> + Bar,
> + 1,
> + (VOID *) &TempBaseAddress
> + );
> + }
> + }
> + }
> +
> + break;
> +
> + case INTEL_VENDOR_ID:
> + if (DeviceId == INTEL_82573E_IDER) {
> + //
> + // Tekoa i82573E IDE-R fix-ups. At this time A2 step and earlier parts do
> not
> + // support any BARs except BAR0. Other BARS will actualy map to BAR0
> so disable
> + // them all for Control Blocks and Bus mastering ops as well as
> Secondary IDE
> + // Controller.
> + // All Tekoa A2 or earlier step chips for now.
> + //
> + PciIo->Pci.Read (
> + PciIo,
> + EfiPciIoWidthUint8,
> + PCI_REVISION_ID_OFFSET,
> + 1,
> + &RevId
> + );
> + if (RevId <= 0x02) {
> + for (Bar = 0x14; Bar < 0x24; Bar+= 4) {
> + //
> + // Maybe want to clean this up a bit later but for now just clear out
> the secondary
> + // Bars don't worry aboyut freeing up thge allocs.
> + //
> + TempBaseAddress = 0x0;
> + PciIo->Pci.Write (
> + PciIo,
> + EfiPciIoWidthUint32,
> + Bar,
> + 1,
> + (VOID *) &TempBaseAddress
> + );
> + } // end for
> + }
> + else
> + {
> + //
> + //Tekoa A3 or above:
> + //Clear bus master base address (PCI register 0x20)
> + //since Tekoa does not fully support IDE Bus Mastering
> + //
> + TempBaseAddress = 0x0;
> + PciIo->Pci.Write (
> + PciIo,
> + EfiPciIoWidthUint32,
> + 0x20,
> + 1,
> + (VOID *) &TempBaseAddress
> + );
> + }
> + }
> + break;
> +
> + default:
> + break;
> + }
> + return;
> +}
> +
> +VOID
> +ProgramPciLatency(
> + IN EFI_PCI_IO_PROTOCOL *PciIo
> + )
> +{
> + //
> + // Program Master Latency Timer
> + //
> + if (mSystemConfiguration.PciLatency != 0) {
> + PciIo->Pci.Write (
> + PciIo,
> + EfiPciIoWidthUint8,
> + PCI_LATENCY_TIMER_OFFSET,
> + 1,
> + &mSystemConfiguration.PciLatency
> + );
> + }
> + return;
> +}
> +
> +/**
> +During S5 shutdown, we need to program PME in all LAN devices.
> +Here we identify LAN devices and save their bus/dev/func.
> +
> +**/
> +VOID
> +SavePciLanAddress(
> + IN EFI_PCI_IO_PROTOCOL *PciIo
> + )
> +{
> + EFI_STATUS Status;
> + UINTN PciSegment,
> + PciBus,
> + PciDevice,
> + PciFunction;
> + VOID *NewBuffer;
> + PCI_LAN_INFO *x;
> +
> + Status = PciIo->GetLocation (
> + PciIo,
> + &PciSegment,
> + &PciBus,
> + &PciDevice,
> + &PciFunction
> + );
> + if (EFI_ERROR (Status)) {
> + return;
> + }
> +
> + mPciLanCount ++;
> + Status = gBS->AllocatePool (
> + EfiBootServicesData,
> + mPciLanCount * sizeof(PCI_LAN_INFO),
> + &NewBuffer
> + );
> + if (EFI_ERROR (Status)) {
> + return;
> + }
> +
> + if (mPciLanCount > 1) {
> + //
> + // copy old data into new, larger buffer
> + //
> + gBS->CopyMem (
> + NewBuffer,
> + mPciLanInfo,
> + (mPciLanCount - 1) * sizeof(PCI_LAN_INFO)
> + );
> +
> + //
> + // free the old memory buffer
> + //
> + gBS->FreePool (mPciLanInfo);
> +
> + }
> +
> + //
> + // init the new entry
> + //
> + x = (PCI_LAN_INFO *)NewBuffer + (mPciLanCount - 1);
> + x->PciBus = (UINT8)PciBus;
> + x->PciDevice = (UINT8)PciDevice;
> + x->PciFunction = (UINT8)PciFunction;
> +
> + mPciLanInfo = NewBuffer;
> +
> + return;
> +}
> +
> +/**
> + @param Event the event that is signaled.
> + @param Context not used here.
> +
> +
> +**/
> +VOID
> +EFIAPI
> +PciBusEvent (
> + IN EFI_EVENT Event,
> + IN VOID* Context
> + )
> +{
> +
> + EFI_STATUS Status;
> + UINTN BufferSize;
> + EFI_HANDLE Handle;
> + EFI_PCI_IO_PROTOCOL *PciIo;
> + PCI_IO_DEVICE *PciIoDevice;
> + UINT64 Supports;
> + UINTN Index;
> + UINT8 mCacheLineSize = 0x10;
> +
> + while (TRUE) {
> + BufferSize = sizeof (EFI_HANDLE);
> + Status = gBS->LocateHandle (
> + ByRegisterNotify,
> + NULL,
> + mPciRegistration,
> + &BufferSize,
> + &Handle
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + // If no more notification events exist
> + //
> + return;
> + }
> +
> + Status = gBS->HandleProtocol (
> + Handle,
> + &gEfiPciIoProtocolGuid,
> + (void **)&PciIo
> + );
> +
> + PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
> +
> + //
> + // Enable I/O for bridge so port 0x80 codes will come out
> + //
> + if (PciIoDevice->Pci.Hdr.VendorId == V_PCH_INTEL_VENDOR_ID)
> + {
> + Status = PciIo->Attributes(
> + PciIo,
> + EfiPciIoAttributeOperationSupported,
> + 0,
> + &Supports
> + );
> + Supports &= EFI_PCI_DEVICE_ENABLE;
> + Status = PciIo->Attributes (
> + PciIo,
> + EfiPciIoAttributeOperationEnable,
> + Supports,
> + NULL
> + );
> + break;
> + }
> +
> + //
> + // Program PCI Latency Timer
> + //
> + ProgramPciLatency(PciIo);
> +
> + //
> + // Program Cache Line Size to 64 bytes (0x10 DWORDs)
> + //
> + Status = PciIo->Pci.Write (
> + PciIo,
> + EfiPciIoWidthUint8,
> + PCI_CACHELINE_SIZE_OFFSET,
> + 1,
> + &mCacheLineSize
> + );
> +
> + //
> + // If PCI LAN device, save bus/dev/func info
> + // so we can program PME during S5 shutdown
> + //
> + if (PciIoDevice->Pci.Hdr.ClassCode[2] == PCI_CLASS_NETWORK) {
> + SavePciLanAddress(PciIo);
> + break;
> + }
> +
> + //
> + // Workaround for cards with bad BARs
> + //
> + Index = 0;
> + while (BadDeviceTable[Index].ClassCode != 0xff) {
> + if (BadDeviceTable[Index].DeviceId == 0xffff) {
> + if ((PciIoDevice->Pci.Hdr.ClassCode[2] ==
> BadDeviceTable[Index].ClassCode) &&
> + (PciIoDevice->Pci.Hdr.ClassCode[1] ==
> BadDeviceTable[Index].SubClassCode) &&
> + (PciIoDevice->Pci.Hdr.VendorId == BadDeviceTable[Index].VendorId))
> {
> +
> InitBadBars(PciIo,BadDeviceTable[Index].VendorId,BadDeviceTable[Index].D
> eviceId);
> + }
> + } else {
> + if ((PciIoDevice->Pci.Hdr.ClassCode[2] ==
> BadDeviceTable[Index].ClassCode) &&
> + (PciIoDevice->Pci.Hdr.ClassCode[1] ==
> BadDeviceTable[Index].SubClassCode) &&
> + (PciIoDevice->Pci.Hdr.VendorId == BadDeviceTable[Index].VendorId)
> &&
> + (PciIoDevice->Pci.Hdr.DeviceId == BadDeviceTable[Index].DeviceId))
> {
> +
> +
> InitBadBars(PciIo,BadDeviceTable[Index].VendorId,BadDeviceTable[Index].D
> eviceId);
> + }
> + }
> + ++Index;
> + }
> + break;
> + }
> +
> + return;
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Platform.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Platform.c
> new file mode 100644
> index 0000000000..2a4a0b92e1
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Platform.c
> @@ -0,0 +1,1820 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
> +
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +
> +Module Name:
> +
> +
> + Platform.c
> +
> +Abstract:
> +
> + Platform Initialization Driver.
> +
> +
> +--*/
> +
> +#include "PlatformDxe.h"
> +#include "Platform.h"
> +#include "PchCommonDefinitions.h"
> +#include <Protocol/UsbPolicy.h>
> +#include <Protocol/PchPlatformPolicy.h>
> +#include <Protocol/TpmMp.h>
> +#include <Protocol/CpuIo2.h>
> +#include <Library/S3BootScriptLib.h>
> +#include <Guid/PciLanInfo.h>
> +#include <Guid/ItkData.h>
> +#include <Library/PciLib.h>
> +#include <PlatformBootMode.h>
> +#include <Guid/EventGroup.h>
> +#include <Guid/Vlv2Variable.h>
> +#include <Protocol/GlobalNvsArea.h>
> +#include <Protocol/IgdOpRegion.h>
> +#include <Library/PcdLib.h>
> +#include <Protocol/VariableLock.h>
> +
> +
> +//
> +// VLV2 GPIO GROUP OFFSET
> +//
> +#define GPIO_SCORE_OFFSET 0x0000
> +#define GPIO_NCORE_OFFSET 0x1000
> +#define GPIO_SSUS_OFFSET 0x2000
> +
> +typedef struct {
> + UINT32 offset;
> + UINT32 val;
> +} CFIO_PNP_INIT;
> +
> +GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[]
> =
> +{
> +// Pad Name GPIO Number Used As GPO Default Function#
> INT Capable Interrupt Type PULL H/L MMIO Offset
> + GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47
> " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),
> + GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48
> " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
> +};
> +
> +
> +EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;
> +EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;
> +SYSTEM_CONFIGURATION mSystemConfiguration;
> +SYSTEM_PASSWORDS mSystemPassword;
> +EFI_HANDLE mImageHandle;
> +BOOLEAN mMfgMode = FALSE;
> +VOID *mDxePlatformStringPack;
> +UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;
> +extern CHAR16 gItkDataVarName[];
> +
> +
> +EFI_PLATFORM_INFO_HOB mPlatformInfo;
> +EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
> +EFI_EVENT mReadyToBootEvent;
> +
> +UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
> +UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) /
> sizeof( mSmbusRsvdAddresses[0] );
> +UINT32 mSubsystemVidDid;
> +UINT32 mSubsystemAudioVidDid;
> +
> +UINTN mPciLanCount = 0;
> +VOID *mPciLanInfo = NULL;
> +UINTN SpiBase;
> +
> +static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {
> + ProgramToneFrequency,
> + GenerateBeepTone
> +};
> +
> +EFI_USB_POLICY_PROTOCOL mUsbPolicyData = {0};
> +
> +
> +CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =
> +{
> + {0x410 ,0x20038e10},
> //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0
> + {0x470 ,0x20038e10},
> //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0
> + {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0
> + {0x450 ,0x20038e10},
> //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0
> + {0x480 ,0x20038e10},
> //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0
> + {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0
> + {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0
> + {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0
> + {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0
> + {0x418 ,0x00000006},
> //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val
> + {0x478 ,0x00000006},
> //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val
> + {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val
> + {0x458 ,0x00000006},
> //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val
> + {0x488 ,0x00000006},
> //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val
> + {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val
> + {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val
> + {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val
> + {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val
> +};
> +
> +VOID
> +EfiOrMem (
> + IN VOID *Destination,
> + IN VOID *Source,
> + IN UINTN Length
> + );
> +
> +#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) &&
> (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
> +STATIC
> +VOID
> +InitFirmwareId();
> +#endif
> +
> +
> +VOID
> +InitializeClockRouting(
> + );
> +
> +VOID
> +InitializeSlotInfo (
> + );
> +
> +#if defined(SENSOR_INFO_VAR_SUPPORT) &&
> SENSOR_INFO_VAR_SUPPORT != 0
> +VOID
> +InitializeSensorInfoVariable (
> + );
> +#endif
> +
> +VOID
> +InitTcoReset (
> + );
> +
> +VOID
> +InitExI ();
> +
> +VOID
> +InitItk();
> +
> +VOID
> +InitPlatformBootMode();
> +
> +VOID
> +InitMfgAndConfigModeStateVar();
> +
> +VOID
> +InitPchPlatformPolicy (
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfo
> + );
> +
> +VOID
> +InitVlvPlatformPolicy (
> + );
> +
> +VOID
> +InitSioPlatformPolicy(
> + );
> +
> +VOID
> +PchInitBeforeBoot(
> + );
> +
> +VOID
> +UpdateDVMTSetup(
> + );
> +
> +VOID
> +InitPlatformUsbPolicy (
> + VOID
> + );
> +
> +VOID
> +InitRC6Policy(
> + VOID
> + );
> +
> +
> +EFI_STATUS
> +EFIAPI
> +SaveSetupRecoveryVar(
> + VOID
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + UINTN SizeOfNvStore = 0;
> + UINTN SizeOfSetupVar = 0;
> + SYSTEM_CONFIGURATION *SetupData = NULL;
> + SYSTEM_CONFIGURATION *RecoveryNvData = NULL;
> + EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock = NULL;
> +
> +
> + DEBUG ((EFI_D_INFO, "SaveSetupRecoveryVar() Entry \n"));
> + SizeOfNvStore = sizeof(SYSTEM_CONFIGURATION);
> + RecoveryNvData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
> + if (NULL == RecoveryNvData) {
> + Status = EFI_OUT_OF_RESOURCES;
> + goto Exit;
> + }
> +
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &SizeOfNvStore,
> + RecoveryNvData
> + );
> +
> + if (EFI_ERROR (Status)) {
> + // Don't find the "SetupRecovery" variable.
> + // have to copy "Setup" variable to "SetupRecovery" variable.
> + SetupData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
> + if (NULL == SetupData) {
> + Status = EFI_OUT_OF_RESOURCES;
> + goto Exit;
> + }
> + SizeOfSetupVar = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + NULL,
> + &SizeOfSetupVar,
> + SetupData
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gRT->SetVariable (
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + sizeof(SYSTEM_CONFIGURATION),
> + SetupData
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL,
> (VOID **) &VariableLock);
> + if (!EFI_ERROR (Status)) {
> + Status = VariableLock->RequestToLock (VariableLock, L"SetupRecovery",
> &gEfiNormalSetupGuid);
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + }
> +
> +Exit:
> + if (RecoveryNvData)
> + FreePool (RecoveryNvData);
> + if (SetupData)
> + FreePool (SetupData);
> +
> + return Status;
> +
> +}
> +
> +
> +VOID
> +TristateLpcGpioConfig (
> + IN UINT32 Gpio_Mmio_Offset,
> + IN UINT32 Gpio_Pin_Num,
> + GPIO_CONF_PAD_INIT* Gpio_Conf_Data
> + )
> +
> +{
> + UINT32 index;
> + UINT32 mmio_conf0;
> + UINT32 mmio_padval;
> + PAD_CONF0 conf0_val;
> + PAD_VAL pad_val;
> +
> + //
> + // GPIO WELL -- Memory base registers
> + //
> +
> + //
> + // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
> + // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
> + //
> +
> + for(index=0; index < Gpio_Pin_Num; index++)
> + {
> + //
> + // Calculate the MMIO Address for specific GPIO pin CONF0 register
> pointed by index.
> + //
> + mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset +
> R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
> + mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset +
> R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
> +
> +#ifdef EFI_DEBUG
> + DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
> +
> +#endif
> + DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull
> Up/Down = %d, MMIO Base = 0x%08x, ",
> + Gpio_Conf_Data[index].usage,
> + Gpio_Conf_Data[index].func,
> + Gpio_Conf_Data[index].int_type,
> + Gpio_Conf_Data[index].pull,
> + mmio_conf0));
> +
> + //
> + // Step 1: PadVal Programming
> + //
> + pad_val.dw = MmioRead32(mmio_padval);
> +
> + //
> + // Config PAD_VAL only for GPIO (Non-Native) Pin
> + //
> + if(Native != Gpio_Conf_Data[index].usage)
> + {
> + pad_val.dw &= ~0x6; // Clear bits 1:2
> + pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2
> according to PadVal
> +
> + //
> + // set GPO default value
> + //
> + if(Gpio_Conf_Data[index].usage == GPO &&
> Gpio_Conf_Data[index].gpod4 != NA)
> + {
> + pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
> + }
> + }
> +
> +
> + DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
> +
> + MmioWrite32(mmio_padval, pad_val.dw);
> +
> + //
> + // Step 2: CONF0 Programming
> + // Read GPIO default CONF0 value, which is assumed to be default value
> after reset.
> + //
> + conf0_val.dw = MmioRead32(mmio_conf0);
> +
> + //
> + // Set Function #
> + //
> + conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
> +
> + if(GPO == Gpio_Conf_Data[index].usage)
> + {
> + //
> + // If used as GPO, then internal pull need to be disabled
> + //
> + conf0_val.r.Pull_assign = 0; // Non-pull
> + }
> + else
> + {
> + //
> + // Set PullUp / PullDown
> + //
> + if(P_20K_H == Gpio_Conf_Data[index].pull)
> + {
> + conf0_val.r.Pull_assign = 0x1; // PullUp
> + conf0_val.r.Pull_strength = 0x2;// 20K
> + }
> + else if(P_20K_L == Gpio_Conf_Data[index].pull)
> + {
> + conf0_val.r.Pull_assign = 0x2; // PullDown
> + conf0_val.r.Pull_strength = 0x2;// 20K
> + }
> + else if(P_NONE == Gpio_Conf_Data[index].pull)
> + {
> + conf0_val.r.Pull_assign = 0; // Non-pull
> + }
> + else
> + {
> + ASSERT(FALSE); // Invalid value
> + }
> + }
> +
> + //
> + // Set INT Trigger Type
> + //
> + conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
> +
> + //
> + // Set INT Trigger Type
> + //
> + if(TRIG_ == Gpio_Conf_Data[index].int_type)
> + {
> + //
> + // Interrupt not capable, clear bits 27:24
> + //
> + }
> + else
> + {
> + conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
> + }
> +
> + DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
> +
> + //
> + // Write back the targeted GPIO config value according to platform (board)
> GPIO setting
> + //
> + MmioWrite32 (mmio_conf0, conf0_val.dw);
> + }
> +
> + // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
> + // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
> + //
> +}
> +
> +VOID
> +EFIAPI
> +SpiBiosProtectionFunction(
> + EFI_EVENT Event,
> + VOID *Context
> + )
> +{
> +
> + UINTN mPciD31F0RegBase;
> + UINTN BiosFlaLower0;
> + UINTN BiosFlaLimit0;
> + UINTN BiosFlaLower1;
> + UINTN BiosFlaLimit1;
> +
> +
> + BiosFlaLower0 = PcdGet32(PcdFlashMicroCodeAddress)-
> PcdGet32(PcdFlashAreaBaseAddress);
> + BiosFlaLimit0 = PcdGet32(PcdFlashMicroCodeSize)-1;
> + #ifdef MINNOW2_FSP_BUILD
> + BiosFlaLower1 = PcdGet32(PcdFlashFvFspBase)-
> PcdGet32(PcdFlashAreaBaseAddress);
> + BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-
> PcdGet32(PcdFlashFvFspBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
> + #else
> + BiosFlaLower1 = PcdGet32(PcdFlashFvMainBase)-
> PcdGet32(PcdFlashAreaBaseAddress);
> + BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-
> PcdGet32(PcdFlashFvMainBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
> + #endif
> +
> +
> + mPciD31F0RegBase = MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + 0
> + );
> + SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE)
> & B_PCH_LPC_SPI_BASE_BAR;
> +
> + //
> + //Set SMM_BWP, WPD and LE bit
> + //
> + MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)
> B_PCH_SPI_BCR_SMM_BWP);
> + MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR),
> (UINT8)(~B_PCH_SPI_BCR_BIOSWE));
> + MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)
> B_PCH_SPI_BCR_BLE);
> +
> + //
> + //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them
> set already.
> + //
> + if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) &
> B_PCH_SPI_HSFS_FLOCKDN) != 0 ||
> + (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)&
> B_PCH_SPI_IND_LOCK_PR0) != 0) {
> + //
> + //Already locked. we could take no action here
> + //
> + DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring
> PR0.\n"));
> + return;
> + }
> +
> + //
> + //Set PR0
> + //
> + MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
> + B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
> +
> (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL
> _MASK&(BiosFlaLimit0>>12)<<16));
> +
> + //
> + //Set PR1
> + //
> +
> + MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1),
> + B_PCH_SPI_PR1_RPE|B_PCH_SPI_PR1_WPE|\
> +
> (B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL
> _MASK&(BiosFlaLimit1>>12)<<16));
> +
> + //
> + //Lock down PRx
> + //
> + MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16)
> (B_PCH_SPI_HSFS_FLOCKDN));
> +
> + //
> + // Verify if it's really locked.
> + //
> + if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) &
> B_PCH_SPI_HSFS_FLOCKDN) == 0) {
> + DEBUG((EFI_D_ERROR, "Failed to lock down PRx.\n"));
> + }
> + return;
> +
> +}
> +
> +VOID
> +EFIAPI
> +InitPciDevPME (
> + EFI_EVENT Event,
> + VOID *Context
> + )
> +{
> + UINTN VarSize;
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + gRT->GetVariable(
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> +
> + //
> + //Program HDA PME_EN
> + //
> + PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);
> +
> + //
> + //Program SATA PME_EN
> + //
> + PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);
> +
> + DEBUG ((EFI_D_INFO, "InitPciDevPME
> mSystemConfiguration.EhciPllCfgEnable = 0x%x
> \n",mSystemConfiguration.EhciPllCfgEnable));
> + if (mSystemConfiguration.EhciPllCfgEnable != 1) {
> + //
> + //Program EHCI PME_EN
> + //
> + PchMmPci32Or (
> + 0,
> + 0,
> + PCI_DEVICE_NUMBER_PCH_USB,
> + PCI_FUNCTION_NUMBER_PCH_EHCI,
> + R_PCH_EHCI_PWR_CNTL_STS,
> + B_PCH_EHCI_PWR_CNTL_STS_PME_EN
> + );
> + }
> + {
> + UINTN EhciPciMmBase;
> + UINT32 Buffer32 = 0;
> +
> + EhciPciMmBase = MmPciAddress (0,
> + 0,
> + PCI_DEVICE_NUMBER_PCH_USB,
> + PCI_FUNCTION_NUMBER_PCH_EHCI,
> + 0
> + );
> + DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x
> \n",EhciPciMmBase));
> + Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);
> + DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm()
> R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));
> + }
> +}
> +
> +VOID
> +EFIAPI
> +InitThermalZone (
> + EFI_EVENT Event,
> + VOID *Context
> + )
> +{
> + UINTN VarSize;
> + EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + gRT->GetVariable(
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + gBS->LocateProtocol (
> + &gEfiGlobalNvsAreaProtocolGuid,
> + NULL,
> + (void **)&GlobalNvsArea
> + );
> + GlobalNvsArea->Area->CriticalThermalTripPoint =
> mSystemConfiguration.CriticalThermalTripPoint;
> + GlobalNvsArea->Area->PassiveThermalTripPoint =
> mSystemConfiguration.PassiveThermalTripPoint;
> +}
> +#if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
> +
> +#endif
> +
> +
> +EFI_STATUS
> +EFIAPI
> +TristateLpcGpioS0i3Config (
> + UINT32 Gpio_Mmio_Offset,
> + UINT32 Gpio_Pin_Num,
> + CFIO_PNP_INIT* Gpio_Conf_Data
> + )
> +{
> +
> + UINT32 index;
> + UINT32 mmio_reg;
> + UINT32 mmio_val;
> +
> + DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));
> +
> + for(index=0; index < Gpio_Pin_Num; index++)
> + {
> + mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset +
> Gpio_Conf_Data[index].offset;
> +
> + MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);
> + mmio_val = 0;
> + mmio_val = MmioRead32(mmio_reg);
> +
> + DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n",
> mmio_reg, mmio_val));
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;
> +
> +/**
> + Event Notification during exit boot service to enabel ACPI mode
> +
> + Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
> +
> + Clear all ACPI event status and disable all ACPI events
> + Disable PM sources except power button
> + Clear status bits
> +
> + Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real
> Time Clock Alarm")
> +
> + Update EC to disable SMI and enable SCI
> +
> + Enable SCI
> +
> + Enable PME_B0_EN in GPE0a_EN
> +
> + @param Event - EFI Event Handle
> + @param Context - Pointer to Notify Context
> +
> + @retval Nothing
> +
> +**/
> +VOID
> +EFIAPI
> +EnableAcpiCallback (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + UINT32 RegData32;
> + UINT16 Pm1Cnt;
> + UINT16 AcpiBase;
> + UINT32 Gpe0aEn;
> +
> + AcpiBase = MmioRead16 (
> + PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE
> + ) & B_PCH_LPC_ACPI_BASE_BAR;
> +
> + DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));
> +
> + //
> + // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
> + //
> + RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);
> + RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR |
> B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);
> + IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);
> +
> + RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);
> + RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;
> + IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);
> +
> + //
> + // Disable PM sources except power button
> + // power button is enabled only for PCAT. Disabled it on Tablet platform
> + //
> +
> + IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN,
> B_PCH_ACPI_PM1_EN_PWRBTN);
> + IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);
> +
> + //
> + // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real
> Time Clock Alarm")
> + // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS
> RAM is no longer Valid
> + //
> + IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
> + IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);
> +
> + RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);
> + RegData32 &= ~(BIT7);
> + IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);
> +
> + //
> + // Enable SCI
> + //
> + Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);
> + Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
> + IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
> +
> + IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE
> +
> + //
> + // Enable PME_B0_EN in GPE0a_EN
> + // Caution: Enable PME_B0_EN must be placed after enabling SCI.
> + // Otherwise, USB PME could not be handled as SMI event since no
> handler is there.
> + //
> + Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);
> + Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;
> + IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);
> +
> +}
> +
> +/**
> +
> + Routine Description:
> +
> + This is the standard EFI driver point for the Driver. This
> + driver is responsible for setting up any platform specific policy or
> + initialization information.
> +
> + @param ImageHandle Handle for the image of this driver.
> + @param SystemTable Pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS Policy decisions set.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializePlatform (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + UINTN VarSize;
> + EFI_HANDLE Handle = NULL;
> + EFI_EVENT mEfiExitBootServicesEvent;
> + EFI_EVENT RtcEvent;
> + VOID *RtcCallbackReg = NULL;
> +
> + mImageHandle = ImageHandle;
> +
> + Status = gBS->InstallProtocolInterface (
> + &Handle,
> + &gEfiSpeakerInterfaceProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + &mSpeakerInterface
> + );
> +
> + Status = gBS->LocateProtocol (
> + &gEfiPciRootBridgeIoProtocolGuid,
> + NULL,
> + (VOID **) &mPciRootBridgeIo
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + VarSize = sizeof(EFI_PLATFORM_INFO_HOB);
> + Status = gRT->GetVariable(
> + L"PlatformInfo",
> + &gEfiVlv2VariableGuid,
> + NULL,
> + &VarSize,
> + &mPlatformInfo
> + );
> +
> + //
> + // Initialize Product Board ID variable
> + //
> + InitMfgAndConfigModeStateVar();
> + InitPlatformBootMode();
> +
> + //
> + // Install Observable protocol
> + //
> + InitializeObservableProtocol();
> +
> + Status = SaveSetupRecoveryVar();
> + if (EFI_ERROR (Status)) {
> + DEBUG ((EFI_D_ERROR, "InitializePlatform() Save SetupRecovery variable
> failed \n"));
> + }
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + Status = gRT->SetVariable (
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + sizeof(SYSTEM_CONFIGURATION),
> + &mSystemConfiguration
> + );
> + }
> +
> + Status = EfiCreateEventReadyToBootEx (
> + TPL_CALLBACK,
> + ReadyToBootFunction,
> + NULL,
> + &mReadyToBootEvent
> + );
> +
> + //
> + // Create a ReadyToBoot Event to run the PME init process
> + //
> + Status = EfiCreateEventReadyToBootEx (
> + TPL_CALLBACK,
> + InitPciDevPME,
> + NULL,
> + &mReadyToBootEvent
> + );
> + //
> + // Create a ReadyToBoot Event to run enable PR0/PR1 and lock
> down,unlock variable region
> + //
> + if(mSystemConfiguration.SpiRwProtect==1) {
> + Status = EfiCreateEventReadyToBootEx (
> + TPL_CALLBACK,
> + SpiBiosProtectionFunction,
> + NULL,
> + &mReadyToBootEvent
> + );
> + }
> + //
> + // Create a ReadyToBoot Event to run the thermalzone init process
> + //
> + Status = EfiCreateEventReadyToBootEx (
> + TPL_CALLBACK,
> + InitThermalZone,
> + NULL,
> + &mReadyToBootEvent
> + );
> +
> + ReportStatusCodeEx (
> + EFI_PROGRESS_CODE,
> + EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,
> + 0,
> + &gEfiCallerIdGuid,
> + NULL,
> + NULL,
> + 0
> + );
> +
> +#if defined(SENSOR_INFO_VAR_SUPPORT) &&
> SENSOR_INFO_VAR_SUPPORT != 0
> + //
> + // Initialize Sensor Info variable
> + //
> + InitializeSensorInfoVariable();
> +#endif
> + InitPchPlatformPolicy(&mPlatformInfo);
> + InitVlvPlatformPolicy();
> +
> + //
> + // Add usb policy
> + //
> + InitPlatformUsbPolicy();
> + InitSioPlatformPolicy();
> + InitializeClockRouting();
> + InitializeSlotInfo();
> + InitTcoReset();
> +
> + //
> + //Init ExI
> + //
> + InitExI();
> +
> + ReportStatusCodeEx (
> + EFI_PROGRESS_CODE,
> + EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,
> + 0,
> + &gEfiCallerIdGuid,
> + NULL,
> + NULL,
> + 0
> + );
> +
> + //
> + // Install PCI Bus Driver Hook
> + //
> + PciBusDriverHook();
> +
> + InitItk();
> +
> + ReportStatusCodeEx (
> + EFI_PROGRESS_CODE,
> + EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,
> + 0,
> + &gEfiCallerIdGuid,
> + NULL,
> + NULL,
> + 0
> + );
> +
> +
> + //
> + // Initialize Password States and Callbacks
> + //
> + PchInitBeforeBoot();
> +
> +#if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
> +
> +#endif
> +
> +#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) &&
> (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
> + //
> + // Re-write Firmware ID if it is changed
> + //
> + InitFirmwareId();
> +#endif
> +
> + ReportStatusCodeEx (
> + EFI_PROGRESS_CODE,
> + EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,
> + 0,
> + &gEfiCallerIdGuid,
> + NULL,
> + NULL,
> + 0
> + );
> +
> +
> + Status = gBS->CreateEventEx (
> + EVT_NOTIFY_SIGNAL,
> + TPL_NOTIFY,
> + EnableAcpiCallback,
> + NULL,
> + &gEfiEventExitBootServicesGuid,
> + &mEfiExitBootServicesEvent
> + );
> +
> + //
> + // Adjust RTC deafult time to be BIOS-built time.
> + //
> + Status = gBS->CreateEvent (
> + EVT_NOTIFY_SIGNAL,
> + TPL_CALLBACK,
> + AdjustDefaultRtcTimeCallback,
> + NULL,
> + &RtcEvent
> + );
> + if (!EFI_ERROR (Status)) {
> + Status = gBS->RegisterProtocolNotify (
> + &gExitPmAuthProtocolGuid,
> + RtcEvent,
> + &RtcCallbackReg
> + );
> +
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Source Or Destination with Length bytes.
> +
> + @param[in] Destination Target memory
> + @param[in] Source Source memory
> + @param[in] Length Number of bytes
> +
> + @retval None
> +
> +**/
> +VOID
> +EfiOrMem (
> + IN VOID *Destination,
> + IN VOID *Source,
> + IN UINTN Length
> + )
> +{
> + CHAR8 *Destination8;
> + CHAR8 *Source8;
> +
> + if (Source < Destination) {
> + Destination8 = (CHAR8 *) Destination + Length - 1;
> + Source8 = (CHAR8 *) Source + Length - 1;
> + while (Length--) {
> + *(Destination8--) |= *(Source8--);
> + }
> + } else {
> + Destination8 = (CHAR8 *) Destination;
> + Source8 = (CHAR8 *) Source;
> + while (Length--) {
> + *(Destination8++) |= *(Source8++);
> + }
> + }
> +}
> +
> +VOID
> +PchInitBeforeBoot()
> +{
> + //
> + // Saved SPI Opcode menu to fix EFI variable unable to write after S3
> resume.
> + //
> + S3BootScriptSaveMemWrite (
> + EfiBootScriptWidthUint32,
> + (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),
> + 1,
> + (VOID *)(UINTN)(SPI_BASE_ADDRESS +
> (R_PCH_SPI_OPMENU0)));
> +
> + S3BootScriptSaveMemWrite (
> + EfiBootScriptWidthUint32,
> + (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),
> + 1,
> + (VOID *)(UINTN)(SPI_BASE_ADDRESS +
> (R_PCH_SPI_OPMENU1)));
> +
> + S3BootScriptSaveMemWrite (
> + EfiBootScriptWidthUint16,
> + (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),
> + 1,
> + (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));
> +
> + S3BootScriptSaveMemWrite (
> + EfiBootScriptWidthUint16,
> + (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),
> + 1,
> + (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));
> +
> + //
> + // Saved MTPMC_1 for S3 resume.
> + //
> + S3BootScriptSaveMemWrite (
> + EfiBootScriptWidthUint32,
> + (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),
> + 1,
> + (VOID *)(UINTN)(PMC_BASE_ADDRESS +
> R_PCH_PMC_MTPMC1));
> + return;
> +}
> +
> +VOID
> +EFIAPI
> +ReadyToBootFunction (
> + EFI_EVENT Event,
> + VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> + EFI_ISA_ACPI_PROTOCOL *IsaAcpi;
> + EFI_ISA_ACPI_DEVICE_ID IsaDevice;
> + UINTN Size;
> + UINT16 State;
> + EFI_TPM_MP_DRIVER_PROTOCOL *TpmMpDriver;
> + EFI_CPU_IO_PROTOCOL *CpuIo;
> + UINT8 Data;
> + UINT8 ReceiveBuffer [64];
> + UINT32 ReceiveBufferSize;
> +
> + UINT8 TpmForceClearCommand [] = {0x00, 0xC1,
> + 0x00, 0x00, 0x00, 0x0A,
> + 0x00, 0x00, 0x00, 0x5D};
> + UINT8 TpmPhysicalPresenceCommand [] = {0x00, 0xC1,
> + 0x00, 0x00, 0x00, 0x0C,
> + 0x40, 0x00, 0x00, 0x0A,
> + 0x00, 0x00};
> + UINT8 TpmPhysicalDisableCommand [] = {0x00, 0xC1,
> + 0x00, 0x00, 0x00, 0x0A,
> + 0x00, 0x00, 0x00, 0x70};
> + UINT8 TpmPhysicalEnableCommand [] = {0x00, 0xC1,
> + 0x00, 0x00, 0x00, 0x0A,
> + 0x00, 0x00, 0x00, 0x6F};
> + UINT8 TpmPhysicalSetDeactivatedCommand [] = {0x00, 0xC1,
> + 0x00, 0x00, 0x00, 0x0B,
> + 0x00, 0x00, 0x00, 0x72,
> + 0x00};
> + UINT8 TpmSetOwnerInstallCommand [] = {0x00, 0xC1,
> + 0x00, 0x00, 0x00, 0x0B,
> + 0x00, 0x00, 0x00, 0x71,
> + 0x00};
> +
> + Size = sizeof(UINT16);
> + Status = gRT->GetVariable (
> + VAR_EQ_FLOPPY_MODE_DECIMAL_NAME,
> + &gEfiNormalSetupGuid,
> + NULL,
> + &Size,
> + &State
> + );
> +
> + //
> + // Disable Floppy Controller if needed
> + //
> + Status = gBS->LocateProtocol (&gEfiIsaAcpiProtocolGuid, NULL, (VOID **)
> &IsaAcpi);
> + if (!EFI_ERROR(Status) && (State == 0x00)) {
> + IsaDevice.HID = EISA_PNP_ID(0x604);
> + IsaDevice.UID = 0;
> + Status = IsaAcpi->EnableDevice(IsaAcpi, &IsaDevice, FALSE);
> + }
> +
> + //
> + // save LAN info to a variable
> + //
> + if (NULL != mPciLanInfo) {
> + gRT->SetVariable (
> + L"PciLanInfo",
> + &gEfiPciLanInfoGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
> + mPciLanCount * sizeof(PCI_LAN_INFO),
> + mPciLanInfo
> + );
> + }
> +
> + if (NULL != mPciLanInfo) {
> + gBS->FreePool (mPciLanInfo);
> + mPciLanInfo = NULL;
> + }
> +
> +
> + //
> + // Handle ACPI OS TPM requests here
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiCpuIoProtocolGuid,
> + NULL,
> + (VOID **)&CpuIo
> + );
> + Status = gBS->LocateProtocol (
> + &gEfiTpmMpDriverProtocolGuid,
> + NULL,
> + (VOID **)&TpmMpDriver
> + );
> + if (!EFI_ERROR (Status))
> + {
> + Data = ReadCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST);
> +
> + //
> + // Clear pending ACPI TPM request indicator
> + //
> + WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0x00);
> + if (Data != 0)
> + {
> + WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, Data);
> +
> + //
> + // Assert Physical Presence for these commands
> + //
> + TpmPhysicalPresenceCommand [11] = 0x20;
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver, TpmPhysicalPresenceCommand,
> + sizeof (TpmPhysicalPresenceCommand),
> + ReceiveBuffer, &ReceiveBufferSize
> + );
> + //
> + // PF PhysicalPresence = TRUE
> + //
> + TpmPhysicalPresenceCommand [11] = 0x08;
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver, TpmPhysicalPresenceCommand,
> + sizeof (TpmPhysicalPresenceCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + if (Data == 0x01)
> + {
> + //
> + // TPM_PhysicalEnable
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver, TpmPhysicalEnableCommand,
> + sizeof (TpmPhysicalEnableCommand),
> + ReceiveBuffer, &ReceiveBufferSize
> + );
> + }
> + if (Data == 0x02)
> + {
> + //
> + // TPM_PhysicalDisable
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver, TpmPhysicalDisableCommand,
> + sizeof (TpmPhysicalDisableCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + }
> + if (Data == 0x03)
> + {
> + //
> + // TPM_PhysicalSetDeactivated=FALSE
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + TpmPhysicalSetDeactivatedCommand [10] = 0x00;
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalSetDeactivatedCommand,
> + sizeof (TpmPhysicalSetDeactivatedCommand),
> + ReceiveBuffer, &ReceiveBufferSize
> + );
> + gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);
> + }
> + if (Data == 0x04)
> + {
> + //
> + // TPM_PhysicalSetDeactivated=TRUE
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + TpmPhysicalSetDeactivatedCommand [10] = 0x01;
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalSetDeactivatedCommand,
> + sizeof (TpmPhysicalSetDeactivatedCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + gRT->ResetSystem (
> + EfiResetWarm,
> + EFI_SUCCESS,
> + 0,
> + NULL
> + );
> + }
> + if (Data == 0x05)
> + {
> + //
> + // TPM_ForceClear
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmForceClearCommand,
> + sizeof (TpmForceClearCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + gRT->ResetSystem (
> + EfiResetWarm,
> + EFI_SUCCESS,
> + 0,
> + NULL
> + );
> + }
> + if (Data == 0x06)
> + {
> + //
> + // TPM_PhysicalEnable
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalEnableCommand,
> + sizeof (TpmPhysicalEnableCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + //
> + // TPM_PhysicalSetDeactivated=FALSE
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + TpmPhysicalSetDeactivatedCommand [10] = 0x00;
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalSetDeactivatedCommand,
> + sizeof (TpmPhysicalSetDeactivatedCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + gRT->ResetSystem (
> + EfiResetWarm,
> + EFI_SUCCESS,
> + 0,
> + NULL
> + );
> + }
> + if (Data == 0x07)
> + {
> + //
> + // TPM_PhysicalSetDeactivated=TRUE
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + TpmPhysicalSetDeactivatedCommand [10] = 0x01;
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalSetDeactivatedCommand,
> + sizeof (TpmPhysicalSetDeactivatedCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + //
> + // TPM_PhysicalDisable
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalDisableCommand,
> + sizeof (TpmPhysicalDisableCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + gRT->ResetSystem (
> + EfiResetWarm,
> + EFI_SUCCESS,
> + 0,
> + NULL
> + );
> + }
> + if (Data == 0x08)
> + {
> + //
> + // TPM_SetOwnerInstall=TRUE
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + TpmSetOwnerInstallCommand [10] = 0x01;
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmSetOwnerInstallCommand,
> + sizeof (TpmSetOwnerInstallCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + }
> + if (Data == 0x09)
> + {
> + //
> + // TPM_SetOwnerInstall=FALSE
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + TpmSetOwnerInstallCommand [10] = 0x00;
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmSetOwnerInstallCommand,
> + sizeof (TpmSetOwnerInstallCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + }
> + if (Data == 0x0A)
> + {
> + //
> + // TPM_PhysicalEnable
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalEnableCommand,
> + sizeof (TpmPhysicalEnableCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + //
> + // TPM_PhysicalSetDeactivated=FALSE
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + TpmPhysicalSetDeactivatedCommand [10] = 0x00;
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalSetDeactivatedCommand,
> + sizeof (TpmPhysicalSetDeactivatedCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + //
> + // Do TPM_SetOwnerInstall=TRUE on next reboot
> + //
> +
> + WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0xF0);
> +
> + gRT->ResetSystem (
> + EfiResetWarm,
> + EFI_SUCCESS,
> + 0,
> + NULL
> + );
> + }
> + if (Data == 0x0B)
> + {
> + //
> + // TPM_SetOwnerInstall=FALSE
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + TpmSetOwnerInstallCommand [10] = 0x00;
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmSetOwnerInstallCommand,
> + sizeof (TpmSetOwnerInstallCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + //
> + // TPM_PhysicalSetDeactivated=TRUE
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + TpmPhysicalSetDeactivatedCommand [10] = 0x01;
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalSetDeactivatedCommand,
> + sizeof (TpmPhysicalSetDeactivatedCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + //
> + // TPM_PhysicalDisable
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalDisableCommand,
> + sizeof (TpmPhysicalDisableCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + gRT->ResetSystem (
> + EfiResetWarm,
> + EFI_SUCCESS,
> + 0,
> + NULL
> + );
> + }
> + if (Data == 0x0E)
> + {
> + //
> + // TPM_ForceClear
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmForceClearCommand,
> + sizeof (TpmForceClearCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + //
> + // TPM_PhysicalEnable
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalEnableCommand,
> + sizeof (TpmPhysicalEnableCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + //
> + // TPM_PhysicalSetDeactivated=FALSE
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + TpmPhysicalSetDeactivatedCommand [10] = 0x00;
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalSetDeactivatedCommand,
> + sizeof (TpmPhysicalSetDeactivatedCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + gRT->ResetSystem (
> + EfiResetWarm,
> + EFI_SUCCESS,
> + 0,
> + NULL
> + );
> + }
> + if (Data == 0xF0)
> + {
> + //
> + // Second part of ACPI TPM request 0x0A: OEM custom
> TPM_SetOwnerInstall=TRUE
> + //
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + TpmSetOwnerInstallCommand [10] = 0x01;
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmSetOwnerInstallCommand,
> + sizeof (TpmSetOwnerInstallCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, 0x0A);
> + }
> + //
> + // Deassert Physical Presence
> + //
> + TpmPhysicalPresenceCommand [11] = 0x10;
> + ReceiveBufferSize = sizeof(ReceiveBuffer);
> + Status = TpmMpDriver->Transmit (
> + TpmMpDriver,
> + TpmPhysicalPresenceCommand,
> + sizeof (TpmPhysicalPresenceCommand),
> + ReceiveBuffer,
> + &ReceiveBufferSize
> + );
> + }
> + }
> +
> + return;
> +}
> +
> +/**
> +
> + Initializes manufacturing and config mode setting.
> +
> +**/
> +VOID
> +InitMfgAndConfigModeStateVar()
> +{
> + EFI_PLATFORM_SETUP_ID *BootModeBuffer;
> + VOID *HobList;
> +
> +
> + HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
> + if (HobList != NULL) {
> + BootModeBuffer = GET_GUID_HOB_DATA (HobList);
> +
> + //
> + // Check if in Manufacturing mode
> + //
> + if ( !CompareMem (
> + &BootModeBuffer->SetupName,
> + MANUFACTURE_SETUP_NAME,
> + StrSize (MANUFACTURE_SETUP_NAME)
> + ) ) {
> + mMfgMode = TRUE;
> + }
> +
> +
> +
> + }
> +
> +}
> +
> +/**
> +
> + Initializes manufacturing and config mode setting.
> +
> +**/
> +VOID
> +InitPlatformBootMode()
> +{
> + EFI_PLATFORM_SETUP_ID *BootModeBuffer;
> + VOID *HobList;
> +
> + HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
> + if (HobList != NULL) {
> + BootModeBuffer = GET_GUID_HOB_DATA (HobList);
> + mPlatformBootMode = BootModeBuffer->PlatformBootMode;
> + }
> +}
> +
> +/**
> +
> + Initializes ITK.
> +
> +**/
> +VOID
> +InitItk(
> + )
> +{
> + EFI_STATUS Status;
> + UINT16 ItkModBiosState;
> + UINT8 Value;
> + UINTN DataSize;
> + UINT32 Attributes;
> +
> + //
> + // Setup local variable according to ITK variable
> + //
> + //
> + // Read ItkBiosModVar to determine if BIOS has been modified by ITK
> + // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has
> not been modified by ITK modified
> + // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS
> has not been modified by ITK
> + //
> + DataSize = sizeof (Value);
> + Status = gRT->GetVariable (
> + ITK_BIOS_MOD_VAR_NAME,
> + &gItkDataVarGuid,
> + &Attributes,
> + &DataSize,
> + &Value
> + );
> + if (Status == EFI_NOT_FOUND) {
> + //
> + // Variable not found, hasn't been initialized, intialize to 0
> + //
> + Value=0x00;
> + //
> + // Write variable to flash.
> + //
> + gRT->SetVariable (
> + ITK_BIOS_MOD_VAR_NAME,
> + &gItkDataVarGuid,
> + EFI_VARIABLE_RUNTIME_ACCESS |
> + EFI_VARIABLE_NON_VOLATILE |
> + EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + sizeof (Value),
> + &Value
> + );
> +
> +}
> + if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {
> + if (Value == 0x00) {
> + ItkModBiosState = 0x00;
> + } else {
> + ItkModBiosState = 0x01;
> + }
> + gRT->SetVariable (
> + VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,
> + &gEfiNormalSetupGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + 2,
> + (void *)&ItkModBiosState
> + );
> + }
> +}
> +
> +#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) &&
> (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
> +
> +/**
> +
> + Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.
> +
> +**/
> +STATIC
> +VOID
> +InitFirmwareId(
> + )
> +{
> + EFI_STATUS Status;
> + CHAR16 FirmwareIdNameWithPassword[] =
> FIRMWARE_ID_NAME_WITH_PASSWORD;
> +
> + //
> + // First try writing the variable without a password in case we are
> + // upgrading from a BIOS without password protection on the FirmwareId
> + //
> + Status = gRT->SetVariable(
> + (CHAR16 *)&gFirmwareIdName,
> + &gFirmwareIdGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS |
> + EFI_VARIABLE_RUNTIME_ACCESS,
> + sizeof( FIRMWARE_ID ) - 1,
> + FIRMWARE_ID
> + );
> +
> + if (Status == EFI_INVALID_PARAMETER) {
> +
> + //
> + // Since setting the firmware id without the password failed,
> + // a password must be required.
> + //
> + Status = gRT->SetVariable(
> + (CHAR16 *)&FirmwareIdNameWithPassword,
> + &gFirmwareIdGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS |
> + EFI_VARIABLE_RUNTIME_ACCESS,
> + sizeof( FIRMWARE_ID ) - 1,
> + FIRMWARE_ID
> + );
> + }
> +}
> +#endif
> +
> +VOID
> +UpdateDVMTSetup(
> + )
> +{
> + //
> + // Workaround to support IIA bug.
> + // IIA request to change option value to 4, 5 and 7 relatively
> + // instead of 1, 2, and 3 which follow Lakeport Specs.
> + // Check option value, temporary hardcode GraphicsDriverMemorySize
> + // Option value to fulfill IIA requirment. So that user no need to
> + // load default and update setupvariable after update BIOS.
> + // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.
> + // *This is for broadwater and above product only.
> + //
> +
> + SYSTEM_CONFIGURATION SystemConfiguration;
> + UINTN VarSize;
> + EFI_STATUS Status;
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> +
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + if((SystemConfiguration.GraphicsDriverMemorySize < 4)
> && !EFI_ERROR(Status) ) {
> + switch (SystemConfiguration.GraphicsDriverMemorySize){
> + case 1:
> + SystemConfiguration.GraphicsDriverMemorySize = 4;
> + break;
> + case 2:
> + SystemConfiguration.GraphicsDriverMemorySize = 5;
> + break;
> + case 3:
> + SystemConfiguration.GraphicsDriverMemorySize = 7;
> + break;
> + default:
> + break;
> + }
> +
> + Status = gRT->SetVariable (
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + sizeof(SYSTEM_CONFIGURATION),
> + &SystemConfiguration
> + );
> + }
> +}
> +
> +VOID
> +InitPlatformUsbPolicy (
> + VOID
> + )
> +
> +{
> + EFI_HANDLE Handle;
> + EFI_STATUS Status;
> +
> + Handle = NULL;
> +
> + mUsbPolicyData.Version =
> (UINT8)USB_POLICY_PROTOCOL_REVISION_2;
> + mUsbPolicyData.UsbMassStorageEmulationType =
> mSystemConfiguration.UsbBIOSINT13DeviceEmulation;
> + if(mUsbPolicyData.UsbMassStorageEmulationType == 3) {
> + mUsbPolicyData.UsbEmulationSize =
> mSystemConfiguration.UsbBIOSINT13DeviceEmulationSize;
> + } else {
> + mUsbPolicyData.UsbEmulationSize = 0;
> + }
> + mUsbPolicyData.UsbZipEmulationType =
> mSystemConfiguration.UsbZipEmulation;
> + mUsbPolicyData.UsbOperationMode = HIGH_SPEED;
> +
> + //
> + // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP
> + //
> + mUsbPolicyData.USBPeriodSupport = LEGACY_PERIOD_UN_SUPP;
> +
> + //
> + // Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP
> + //
> + mUsbPolicyData.LegacyFreeSupport = LEGACY_FREE_UN_SUPP;
> +
> + //
> + // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00
> + //
> + mUsbPolicyData.CodeBase = (UINT8)ICBD_CODE_BASE;
> +
> + //
> + // Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,
> + // default is Ich acpibase =0x040. acpitimerreg=0x08.
> + mUsbPolicyData.LpcAcpiBase = 0x40;
> + mUsbPolicyData.AcpiTimerReg = 0x08;
> +
> + //
> + // Set for reduce usb post time
> + //
> + mUsbPolicyData.UsbTimeTue = 0x00;
> + mUsbPolicyData.InternelHubExist = 0x00; //TigerPoint doesn't have
> RMH
> + mUsbPolicyData.EnumWaitPortStableStall = 100;
> +
> +
> + Status = gBS->InstallProtocolInterface (
> + &Handle,
> + &gUsbPolicyGuid,
> + EFI_NATIVE_INTERFACE,
> + &mUsbPolicyData
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> +}
> +
> +UINT8
> +ReadCmosBank1Byte (
> + IN EFI_CPU_IO_PROTOCOL *CpuIo,
> + IN UINT8 Index
> + )
> +{
> + UINT8 Data;
> +
> + CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);
> + CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);
> + return Data;
> +}
> +
> +VOID
> +WriteCmosBank1Byte (
> + IN EFI_CPU_IO_PROTOCOL *CpuIo,
> + IN UINT8 Index,
> + IN UINT8 Data
> + )
> +{
> + CpuIo->Io.Write (
> + CpuIo,
> + EfiCpuIoWidthUint8,
> + 0x72,
> + 1,
> + &Index
> + );
> + CpuIo->Io.Write (
> + CpuIo,
> + EfiCpuIoWidthUint8,
> + 0x73,
> + 1,
> + &Data
> + );
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.h
> new file mode 100644
> index 0000000000..8f5df3257e
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.h
> @@ -0,0 +1,722 @@
> +/*++
> +
> + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +Module Name:
> +
> + PlatformDxe.h
> +
> +Abstract:
> +
> + Header file for Platform Initialization Driver.
> +
> +
> +
> +++*/
> +
> +#ifndef _PLATFORM_DRIVER_H
> +#define _PLATFORM_DRIVER_H
> +
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/PcdLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/ReportStatusCodeLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/EfiRegTableLib.h>
> +#include <Library/Tpm2CommandLib.h>
> +#include <Library/Tpm2DeviceLib.h>
> +#include <Library/BaseCryptLib.h>
> +#include <Library/BiosIdLib.h>
> +#include <Protocol/GlobalNvsArea.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include <Protocol/IsaAcpi.h>
> +#include <Framework/FrameworkInternalFormRepresentation.h>
> +#include <Protocol/FrameworkHii.h>
> +#include <Protocol/FrameworkFormCallback.h>
> +#include <Protocol/CpuIo.h>
> +#include <Protocol/BootScriptSave.h>
> +#include <Framework/BootScript.h>
> +#include <Guid/GlobalVariable.h>
> +#include <Guid/BoardFeatures.h>
> +#include <Guid/DataHubRecords.h>
> +#include <Protocol/DataHub.h>
> +#include <Protocol/PciIo.h>
> +#include <Protocol/Speaker.h>
> +#include <Protocol/ExitPmAuth.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Guid/SetupVariable.h>
> +#include <Guid/PlatformInfo.h>
> +#include "Configuration.h"
> +#define _EFI_H_ //skip efi.h
> +#include "PchAccess.h"
> +#include "VlvAccess.h"
> +#include "BoardIdDecode.h"
> +#include "PlatformBaseAddresses.h"
> +#include "SetupMode.h"
> +#include "PlatformBootMode.h"
> +#include "CpuType.h"
> +
> +#define PCAT_RTC_ADDRESS_REGISTER 0x74
> +#define PCAT_RTC_DATA_REGISTER 0x75
> +
> +#define RTC_ADDRESS_SECOND_ALARM 0x01
> +#define RTC_ADDRESS_MINUTE_ALARM 0x03
> +#define RTC_ADDRESS_HOUR_ALARM 0x05
> +
> +#define RTC_ADDRESS_REGISTER_A 0x0A
> +#define RTC_ADDRESS_REGISTER_B 0x0B
> +#define RTC_ADDRESS_REGISTER_C 0x0C
> +#define RTC_ADDRESS_REGISTER_D 0x0D
> +
> +#define B_RTC_ALARM_INT_ENABLE 0x20
> +#define B_RTC_ALARM_INT_STATUS 0x20
> +
> +#define B_RTC_DATE_ALARM_MASK 0x3F
> +
> +//
> +// Default CPU Alternate Duty Cycle (255=100%, 0=0%)
> +//
> +#define DEF_CPU_ALT_DUTY_CYCLE 0xFF
> +
> +#define MAX_ONBOARD_SATA_DEVICE 2
> +
> +#define DXE_DEVICE_ENABLED 1
> +#define DXE_DEVICE_DISABLED 0
> +
> +#define AZALIA_MAX_LOOP_TIME 0x10000
> +
> +//
> +// Platform driver GUID
> +//
> +#define EFI_PLATFORM_DRIVER_GUID \
> + { 0x056E7324, 0xA718, 0x465b, 0x9A, 0x84, 0x22, 0x8F, 0x06, 0x64, 0x2B,
> 0x4F }
> +
> +#define PASSWORD_MAX_SIZE 20
> +#define PLATFORM_NORMAL_MODE 0x01
> +#define PLATFORM_SAFE_MODE 0x02
> +#define PLATFORM_RECOVERY_MODE 0x04
> +#define PLATFORM_MANUFACTURING_MODE 0x08
> +#define PLATFORM_BACK_TO_BIOS_MODE 0x10
> +
> +#define EFI_OEM_SPECIFIC 0x8000
> +#define EFI_CU_PLATFORM_DXE_INIT (EFI_OEM_SPECIFIC |
> 0x00000011)
> +#define EFI_CU_PLATFORM_DXE_STEP1 (EFI_OEM_SPECIFIC |
> 0x00000012)
> +#define EFI_CU_PLATFORM_DXE_STEP2 (EFI_OEM_SPECIFIC |
> 0x00000013)
> +#define EFI_CU_PLATFORM_DXE_STEP3 (EFI_OEM_SPECIFIC |
> 0x00000014)
> +#define EFI_CU_PLATFORM_DXE_STEP4 (EFI_OEM_SPECIFIC |
> 0x00000015)
> +#define EFI_CU_PLATFORM_DXE_INIT_DONE (EFI_OEM_SPECIFIC |
> 0x00000016)
> +
> +
> +#define EFI_SECTION_STRING 0x1C
> +#define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
> +#define PREFIX_BLANK 0x04
> +
> +#pragma pack(1)
> +
> +typedef UINT64 EFI_BOARD_FEATURES;
> +
> +//
> +//BUGBUG: should remove these EDK hii definition once Hii transtion is
> done
> +//
> +typedef UINT16 STRING_REF;
> +typedef UINT16 EFI_FORM_LABEL;
> +
> +typedef enum {
> + EfiUserPassword,
> + EfiAdminPassword
> +} EFI_PASSWORD_TYPE;
> +
> +typedef struct {
> + CHAR16 TempPassword[PASSWORD_MAX_SIZE];
> + CHAR16 EncodedPassword[PASSWORD_MAX_SIZE];
> + VOID *PasswordLocation;
> + EFI_PASSWORD_TYPE PasswordType;
> +} EFI_PASSWORD_DATA;
> +
> +typedef struct {
> + CHAR8 AaNumber[7];
> + UINT8 BoardId;
> + EFI_BOARD_FEATURES Features;
> + UINT16 SubsystemDeviceId;
> + UINT16 AudioSubsystemDeviceId;
> + UINT64 AcpiOemTableId;
> +} BOARD_ID_DECODE;
> +
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_FORM_ROUTINE) (
> + SYSTEM_CONFIGURATION *SetupBuffer
> + );
> +
> +typedef struct{
> + UINT16 DeviceNumber;
> + UINT16 FunctionNumber;
> +}PCI_DEVICE_FUNC_INFO;
> +
> +typedef struct{
> + CHAR16 PortNumber[4];
> + STRING_REF SataDeviceInfoStringId;
> +}SATA_DEVICE_STRING_INFO;
> +
> +typedef struct {
> + UINT16 Signature;
> + UINT8 Size;
> + UINT32 EntryPoint;
> + UINT8 Reserve[17];
> + UINT16 PciDataOff;
> + UINT16 ExpansionOff;
> +} PNP_OPTION_ROM_HEADER;
> +
> +typedef struct {
> + UINT32 Signature;
> + UINT8 Revision;
> + UINT8 Length;
> + UINT16 NextHeader;
> + UINT8 Reserve;
> + UINT8 CheckSum;
> + UINT32 DeviceId;
> + UINT16 ManufactureStrOff;
> + UINT16 ProductStrOff;
> +} PNP_EXPANSION_HEADER;
> +
> +typedef struct {
> + BOOLEAN Enable;
> + UINT8 VerbTableNum;
> + UINT16 CodecSSID;
> + EFI_PHYSICAL_ADDRESS HDABar;
> + EFI_PHYSICAL_ADDRESS UpperHDABar;
> + UINT8 SDIPresent;
> + BOOLEAN Pme;
> + BOOLEAN LegacyFrontPanelAudio;
> + BOOLEAN HighDefinitionFrontPanelAudio;
> +} EFI_AZALIA_S3;
> +
> +//
> +//following structs are from R8. Remove them once R8->R9 transition is
> done
> +//
> +typedef struct {
> + CHAR16 *OptionString; // Passed in string to generate a token for in a
> truly dynamic form creation
> + STRING_REF StringToken; // This is used when creating a single op-code
> without generating a StringToken (have one already)
> + UINT16 Value;
> + UINT8 Flags;
> + UINT16 Key;
> +} IFR_OPTION;
> +
> +
> +
> +typedef struct {
> + UINT8 Number;
> + UINT32 HorizontalResolution;
> + UINT32 VerticalResolution;
> +} PANEL_RESOLUTION;
> +
> +#pragma pack()
> +
> +//
> +// Prototypes
> +//
> +EFI_STATUS
> +EFIAPI
> +EfiMain (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + );
> +
> +EFI_STATUS
> +ProcessEventLog (
> + );
> +
> +EFI_STATUS
> +FindDataRecords (
> + );
> +
> +EFI_STATUS
> +ProcessPasswords(
> + );
> +
> +VOID
> +MemorySetup(
> + );
> +
> +
> +UINTN
> +EfiValueToString (
> + IN OUT CHAR16 *Buffer,
> + IN INT64 Value,
> + IN UINTN Flags,
> + IN UINTN Width
> + );
> +
> +VOID
> +EFIAPI
> +ReadyToBootFunction (
> + EFI_EVENT Event,
> + VOID *Context
> + );
> +
> +VOID
> +InstallHiiDataAndGetSettings(
> + IN EFI_HII_STRING_PACK *StringPack,
> + //
> + ... // 0 or more of => IN EFI_HII_IFR_PACK *IfrPack,
> + // Terminate list with NULL
> + //
> + );
> +
> +EFI_STATUS
> +ReadOrInitSetupVariable(
> + IN UINTN RequiredVariableSize,
> + IN UINTN RequiredPasswordSize,
> + IN VOID *DefaultData,
> + IN VOID *MfgDefaultData,
> + OUT VOID *SetupVariableData,
> + OUT VOID *SystemPassword
> + );
> +
> +VOID
> +EfiLogicalOrMem(
> + IN VOID *Destination,
> + IN VOID *Source,
> + IN UINTN Length
> + );
> +
> +EFI_STATUS
> +GetStringFromToken (
> + IN EFI_GUID *ProducerGuid,
> + IN STRING_REF Token,
> + OUT CHAR16 **String
> + );
> +
> +UINT32
> +ConvertBase2ToRaw (
> + IN EFI_EXP_BASE2_DATA *Data);
> +
> +UINT32
> +ConvertBase10ToRaw (
> + IN EFI_EXP_BASE10_DATA *Data);
> +
> +CHAR16 *
> +GetStringById (
> + IN STRING_REF Id,
> + EFI_HII_HANDLE StringPackHandle
> + );
> +
> +VOID
> +EFIAPI
> +SetupDataFilter (
> + IN EFI_EVENT Event,
> + IN VOID* Context
> + );
> +
> +VOID
> +EFIAPI
> +IdeDataFilter (
> + IN EFI_EVENT Event,
> + IN VOID* Context
> + );
> +
> +VOID
> +EFIAPI
> +UpdateAhciRaidDiskInfo (
> + IN EFI_EVENT Event,
> + IN VOID* Context
> + );
> +
> +VOID
> +EFIAPI
> +EventLogFilter (
> + IN EFI_EVENT Event,
> + IN VOID* Context
> + );
> +
> +VOID
> +SwapEntries (
> + IN CHAR8 *Data
> + );
> +
> +VOID
> +AsciiToUnicode (
> + IN CHAR8 *AsciiString,
> + IN CHAR16 *UnicodeString
> + );
> +
> +UINT16
> +ConfigModeStateGet();
> +
> +VOID
> +SetSkus();
> +
> +VOID
> +CPUSetupItems();
> +
> +EFI_STATUS
> +SecurityDriverCallback (
> + IN EFI_FORM_CALLBACK_PROTOCOL *This,
> + IN UINT16 KeyValue,
> + IN EFI_IFR_DATA_ARRAY *Data,
> + OUT EFI_HII_CALLBACK_PACKET **Packet
> + );
> +
> +VOID
> +SetPasswordState (
> + );
> +
> +VOID
> +EncodePassword (
> + IN CHAR16 *Password
> + );
> +
> +VOID
> +EFIAPI
> +PciBusEvent (
> + IN EFI_EVENT Event,
> + IN VOID* Context
> + );
> +VOID
> +AsfInitialize(
> + );
> +
> +VOID
> +InitializeAsf (
> + );
> +
> +UINT8
> +ReadCmosBank1Byte (
> + IN EFI_CPU_IO_PROTOCOL *CpuIo,
> + IN UINT8 Index
> + );
> +
> +VOID
> +WriteCmosBank1Byte (
> + IN EFI_CPU_IO_PROTOCOL *CpuIo,
> + IN UINT8 Index,
> + IN UINT8 Data
> + );
> +
> +VOID
> +InitializeBoardId (
> + );
> +
> +EFI_STATUS
> +InstallBootCallbackRoutine(
> + );
> +
> +EFI_STATUS
> +InstallConfigurationCallbackRoutine(
> + );
> +
> +EFI_STATUS
> +InstallPerformanceCallbackRoutine(
> + );
> +
> +EFI_STATUS
> +InstallSecurityCallbackRoutine (
> + );
> +
> +EFI_STATUS
> +InstallMainCallbackRoutine (
> + );
> +
> +EFI_STATUS
> +MemoryConfigurationUpdate (
> + UINT16 *Key,
> + EFI_FORM_LABEL *Label,
> + UINT16 *OpcodeCount,
> + UINT8 **OpcodeData,
> + EFI_FORM_ROUTINE *Routine
> + );
> +
> +EFI_STATUS
> +MemoryConfigurationCallbackRoutine (
> + SYSTEM_CONFIGURATION *SetupBuffer
> + );
> +
> +EFI_STATUS
> +MemoryConfigurationCalculateSpeed(
> + SYSTEM_CONFIGURATION *SetupBuffer
> + );
> +
> +VOID
> +UpdateMemoryString(
> + IN STRING_REF TokenToUpdate,
> + IN CHAR16 *NewString
> + );
> +
> +VOID
> +InitFeaturePolicy (
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfo
> + );
> +
> +VOID
> +InitializeSetupVarHide (
> + );
> +
> +VOID
> +PreparePCIePCISlotInformation(
> + VOID
> + );
> +
> +
> +EFI_STATUS
> +BootConfigurationUpdate (
> + IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +EFI_STATUS
> +InitializeBootConfiguration(
> + VOID
> + );
> +
> +UINT16
> +GetStringSize(
> + IN CHAR16 *ThisString
> + );
> +
> +UINT16
> +GetDriveCount (
> + IN STRING_REF *BootMap
> + );
> +
> +CHAR16 *
> +GetBootString (
> + IN STRING_REF Id,
> + OUT UINTN *Length
> + );
> +
> +EFI_STATUS
> +BootCfgCreateTwoOptionOneOf(
> + IN UINT16 QuestionId,
> + IN EFI_FORM_LABEL Label,
> + IN STRING_REF OptionPrompt,
> + IN STRING_REF OptionHelp,
> + IN STRING_REF OptionOneString,
> + IN STRING_REF OptionTwoString,
> + IN UINT8 OptionOneFlags,
> + IN UINT8 OptionTwoFlags,
> + IN UINT16 KeyValueOne,
> + IN UINT16 KeyValueTwo
> + );
> +
> +EFI_STATUS
> +ReplaceOpcodeWithText(
> + IN STRING_REF OptionPrompt,
> + IN STRING_REF OptionHelp,
> + IN STRING_REF OptionOneString,
> + IN EFI_FORM_LABEL Label
> + );
> +
> +EFI_STATUS
> +CreateDriveBootOrderOpcode(
> + IN VOID *Data,
> + IN STRING_REF *BootMap,
> + IN EFI_FORM_LABEL Label,
> + IN UINT16 QuestionId,
> + IN STRING_REF OptionOneString,
> + IN STRING_REF OptionTwoString
> + );
> +
> +VOID
> +SetHyperBootCfgFlags(
> + IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +VOID
> +GetHyperBootCfgFlags(
> + IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +VOID
> +PrepareBootCfgForHyperBoot(
> + IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +BOOLEAN
> +BootCfgChanged(
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +EFI_STATUS
> +InsertOpcodeAtIndex(
> + IN SYSTEM_CONFIGURATION *SystemConfiguration,
> + IN OUT IFR_OPTION *OptionList,
> + IN IFR_OPTION IfrOption,
> + IN UINT16 OptionCount
> + );
> +
> +VOID
> +ConfigureBootOrderStrings(
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +VOID
> +InitializeAllBootStrings(
> + VOID
> + );
> +
> +VOID
> +SaveUsbCfgSettings(
> + IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +VOID
> +RestoreUsbCfgSettings(
> + IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +EFI_STATUS
> +UpdateBootDevicePriority(
> + IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +EFI_STATUS
> +DisableHyperBoot(
> + IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +BOOLEAN
> +CheckForUserPassword(
> + VOID
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +HyperBootPasswordCallback(
> + IN OUT VOID* Data
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +HyperBootF9Callback (
> + IN VOID* Data
> + );
> +
> +EFI_STATUS
> +InstallHiiEvents(
> + VOID
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +ProgramToneFrequency (
> + IN EFI_SPEAKER_IF_PROTOCOL *This,
> + IN UINT16 Frequency
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +GenerateBeepTone (
> + IN EFI_SPEAKER_IF_PROTOCOL *This,
> + IN UINTN NumberOfBeeps,
> + IN UINTN BeepDuration,
> + IN UINTN TimeInterval
> + );
> +
> +EFI_STATUS
> +InitializeObservableProtocol();
> +
> +EFI_STATUS
> +PciBusDriverHook();
> +
> +VOID
> +EFIAPI
> +AdjustDefaultRtcTimeCallback (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + );
> +
> +typedef struct _GOP_DISPLAY_BRIGHTNESS_PROTOCOL
> GOP_DISPLAY_BRIGHTNESS_PROTOCOL;
> +
> +typedef
> +EFI_STATUS
> +(EFIAPI *GET_MAXIMUM_BRIGHTNESS_LEVEL) (
> + IN GOP_DISPLAY_BRIGHTNESS_PROTOCOL *This,
> + OUT UINT32 *MaxBrightnessLevel
> + );
> +
> +
> +typedef
> +EFI_STATUS
> +(EFIAPI *GET_CURRENT_BRIGHTNESS_LEVEL) (
> + IN GOP_DISPLAY_BRIGHTNESS_PROTOCOL *This,
> + OUT UINT32 *MaxBrightnessLevel
> + );
> +
> +typedef
> +EFI_STATUS
> +(EFIAPI *SET_BRIGHTNESS_LEVEL) (
> + IN GOP_DISPLAY_BRIGHTNESS_PROTOCOL *This,
> + IN UINT32 BrightnessLevel
> + );
> +
> +struct _GOP_DISPLAY_BRIGHTNESS_PROTOCOL {
> + UINT32 Revision;
> + GET_MAXIMUM_BRIGHTNESS_LEVEL GetMaxBrightnessLevel;
> + GET_CURRENT_BRIGHTNESS_LEVEL GetCurrentBrightnessLevel;
> + SET_BRIGHTNESS_LEVEL SetBrightnessLevel;
> +};
> +
> +//
> +// Global externs
> +//
> +extern UINT8 MaintenanceBin[];
> +extern UINT8 MainBin[];
> +extern UINT8 ConfigurationBin[];
> +extern UINT8 MemoryConfigurationBin[];
> +extern UINT8 PerformanceBin[];
> +extern UINT8 SecurityBin[];
> +extern UINT8 BootBin[];
> +extern UINT8 PowerBin[];
> +extern UINT8 SystemSetupBin[];
> +
> +extern VOID *mDxePlatformStringPack;
> +extern EFI_HII_PROTOCOL *mHii;
> +extern SYSTEM_CONFIGURATION mSystemConfiguration;
> +extern FRAMEWORK_EFI_HII_HANDLE mMaintenanceHiiHandle;
> +extern FRAMEWORK_EFI_HII_HANDLE mMainHiiHandle;
> +extern FRAMEWORK_EFI_HII_HANDLE mConfigurationHiiHandle;
> +extern FRAMEWORK_EFI_HII_HANDLE mPerformanceHiiHandle;
> +extern FRAMEWORK_EFI_HII_HANDLE mPowerHiiHandle;
> +extern FRAMEWORK_EFI_HII_HANDLE mBootHiiHandle;
> +extern FRAMEWORK_EFI_HII_HANDLE mSecurityHiiHandle;
> +
> +extern SYSTEM_PASSWORDS mSystemPassword;
> +extern EFI_PASSWORD_DATA mAdminPassword;
> +extern EFI_PASSWORD_DATA mUserPassword;
> +
> +extern EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
> +
> +//
> +//extern EFI_REG_TABLE mSubsystemIdRegs[];
> +//
> +extern UINT32 mSubsystemVidDid;
> +extern UINT32 mSubsystemAudioVidDid;
> +
> +extern UINT8 mBoardIdIndex;
> +extern BOOLEAN mFoundAANum;
> +extern EFI_BOARD_FEATURES mBoardFeatures;
> +extern UINT16 mSubsystemDeviceId;
> +extern UINT16 mSubsystemAudioDeviceId;
> +extern BOARD_ID_DECODE mBoardIdDecodeTable[];
> +extern UINTN mBoardIdDecodeTableSize;
> +
> +extern UINT8 mSmbusRsvdAddresses[];
> +extern UINT8 mNumberSmbusAddress;
> +extern BOOLEAN mMfgMode;
> +extern UINT32 mPlatformBootMode;
> +extern CHAR8 BoardAaNumber[];
> +
> +extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf
> new file mode 100644
> index 0000000000..4d1949d05d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf
> @@ -0,0 +1,149 @@
> +## @file
> +#
> +# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +# Module Name:
> +#
> +# PlatformBB.inf
> +#
> +# Abstract:
> +#
> +# Component description file for platform DXE driver
> +# ------------------------------------------------------------------------------
> +# Rev Date<MM/DD/YYYY> Name Description
> +# ------------------------------------------------------------------------------
> +# R01 <04/22/2011> LB Update code for SIO83627UHG support.
> +# ------------------------------------------------------------------------------
> +#
> +##
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformDxe
> + FILE_GUID = 056E7324-A718-465b-9A84-228F06642B4F
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + PI_SPECIFICATION_VERSION = 0x0001000A
> + ENTRY_POINT = InitializePlatform
> +
> +[sources.common]
> + BoardId.c
> + BoardIdDecode.c
> + ClockControl.c
> + Platform.c
> + IchRegTable.c
> + IdccInfo.c
> + SioPlatformPolicy.c
> + IchPlatformPolicy.c
> + PciDevice.c
> + SlotConfig.c
> + IchTcoReset.c
> + SensorVar.c
> + LegacySpeaker.c
> + Observable/Observable.c
> + ExI.c
> + Rtc.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + SecurityPkg/SecurityPkg.dec
> + CryptoPkg/CryptoPkg.dec
> + IntelFspWrapperPkg/IntelFspWrapperPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + MemoryAllocationLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> + UefiRuntimeServicesTableLib
> + DxeServicesTableLib
> + PchPlatformLib
> +
> + DebugLib
> + HiiLib
> + PrintLib
> + UefiLib
> + S3BootScriptLib
> + ReportStatusCodeLib
> + EfiRegTableLib
> + BiosIdLib
> + BaseCryptLib
> +
> +[Guids]
> + gEfiBiosIdGuid
> + gEfiPlatformBootModeGuid
> + gEfiBoardFeaturesGuid
> + gItkDataVarGuid
> + gDmiDataGuid
> + gIdccDataHubGuid
> + gEfiPciLanInfoGuid
> + gEfiNormalSetupGuid
> + gEfiGlobalVariableGuid
> + gEfiEventExitBootServicesGuid
> + gEfiVlv2VariableGuid
> + gEfiSecureBootEnableDisableGuid
> +
> +[Protocols]
> + gEfiPciRootBridgeIoProtocolGuid # CONSUMES ## GUID
> + gEfiVariableArchProtocolGuid
> + gEfiVariableWriteArchProtocolGuid
> + gEfiHiiConfigAccessProtocolGuid
> + gEfiBootScriptSaveProtocolGuid
> + gEfiCpuIoProtocolGuid
> + gEfiDevicePathProtocolGuid
> + gEfiDiskInfoProtocolGuid
> + gEfiPs2PolicyProtocolGuid
> + gEfiIsaAcpiProtocolGuid
> + gEfiDataHubProtocolGuid
> + gEfiPciIoProtocolGuid
> + gDxePchPlatformPolicyProtocolGuid
> + gEfiTpmMpDriverProtocolGuid
> + gEfiLpcWpce791PolicyProtocolGuid
> + gUsbPolicyGuid
> + gEfiSpeakerInterfaceProtocolGuid
> + gDxeVlvPlatformPolicyGuid
> + gEfiSmbiosSlotPopulationGuid
> + gObservableProtocolGuid
> + gEfiCk505ClockPlatformInfoGuid
> + gEfiLpcWpc83627PolicyProtocolGuid
> + gEfiTcoResetProtocolGuid
> + gEfiWatchdogTimerDriverProtocolGuid
> + gEfiPlatformIdeInitProtocolGuid
> + gEfiGlobalNvsAreaProtocolGuid
> + gEfiCpuIo2ProtocolGuid
> + gIgdOpRegionProtocolGuid
> + gExitPmAuthProtocolGuid
> + gEdkiiVariableLockProtocolGuid
> +
> +[Pcd.common]
> + gPlatformModuleTokenSpaceGuid.PcdPBTNDisableInterval
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> + gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress
> + gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress
> + gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFastPS2Detection
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize
> + gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase
> +
> +
> +[Depex]
> + gEfiPciRootBridgeIoProtocolGuid AND
> + gEfiVariableArchProtocolGuid AND
> + gEfiVariableWriteArchProtocolGuid AND
> + gEfiBootScriptSaveProtocolGuid AND
> + gEfiCpuIoProtocolGuid AND
> + gDxePchPlatformPolicyProtocolGuid AND
> + gEfiGlobalNvsAreaProtocolGuid
> +
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Rtc.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Rtc.c
> new file mode 100644
> index 0000000000..f7be592960
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/Rtc.c
> @@ -0,0 +1,154 @@
> +/** @file
> + Adjust Default System Time.
> +
> + Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +--*/
> +
> +#include <PlatformDxe.h>
> +
> +//
> +// Date and time initial values.
> +// They are used if the RTC values are invalid during driver initialization
> +//
> +#define RTC_INIT_SECOND 0
> +#define RTC_INIT_MINUTE 0
> +#define RTC_INIT_HOUR 0
> +
> +CHAR16 mBiosReleaseDate[20];
> +
> +/**
> + Convert a single character to number.
> + It assumes the input Char is in the scope of L'0' ~ L'9' and L'A' ~ L'F'
> +
> + @param Char The input char which need to change to a hex number.
> +
> +**/
> +UINTN
> +CharToUint (
> + IN CHAR16 Char
> + )
> +{
> + if ((Char >= L'0') && (Char <= L'9')) {
> + return (UINTN) (Char - L'0');
> + }
> +
> + if ((Char >= L'A') && (Char <= L'F')) {
> + return (UINTN) (Char - L'A' + 0xA);
> + }
> +
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + See if YEAR field of a variable of EFI_TIME type is correct.
> +
> + @param Time The time to be checked.
> +
> + @retval EFI_INVALID_PARAMETER Some fields of Time are not correct.
> + @retval EFI_SUCCESS Time is a valid EFI_TIME variable.
> +
> +**/
> +EFI_STATUS
> +CheckRtcTimeFields (
> + IN EFI_TIME *Time
> + )
> +{
> + UINT16 YearBuilt;
> +
> + YearBuilt = (UINT16)(CharToUint(mBiosReleaseDate[8])*10 +
> CharToUint(mBiosReleaseDate[9]) + 2000);
> +
> + if ((Time->Year) < YearBuilt) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + ExitPmAuth Protocol notification event handler, which set initial system
> time to be
> + the time when BIOS was built.
> +
> + @param[in] Event Event whose notification function is being invoked.
> + @param[in] Context Pointer to the notification function's context.
> +
> +**/
> +VOID
> +EFIAPI
> +AdjustDefaultRtcTimeCallback (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> + EFI_TIME EfiTime;
> + CHAR16 BiosVersion[60];
> + CHAR16 BiosReleaseTime[20];
> + //
> + // Get BIOS built time from Bios-ID.
> + //
> +
> + SetMem(BiosVersion, sizeof(BiosVersion), 0);
> + SetMem(mBiosReleaseDate, sizeof(mBiosReleaseDate), 0);
> + SetMem(BiosReleaseTime, sizeof(BiosReleaseTime), 0);
> +
> + Status = GetBiosVersionDateTime (BiosVersion, mBiosReleaseDate,
> BiosReleaseTime);
> + ASSERT_EFI_ERROR(Status);
> + if (EFI_ERROR (Status)) {
> + return;
> + }
> +
> + //
> + // Get current RTC time.
> + //
> + Status = gRT->GetTime (&EfiTime, NULL);
> +
> + //
> + // Validate RTC time fields
> + //
> + Status = CheckRtcTimeFields (&EfiTime);
> +
> + if (EFI_ERROR (Status)) {
> + //
> + // Date such as Dec 28th of 2015
> + //
> + // Month
> + // BiosReleaseDate[0] = '1';
> + // BiosReleaseDate[1] = '2';
> + //
> + // Day
> + // BiosReleaseDate[3] = '2';
> + // BiosReleaseDate[4] = '8';
> + //
> + //
> + // Year
> + //
> + // BiosReleaseDate[6] = '2';
> + // BiosReleaseDate[7] = '0';
> + // BiosReleaseDate[8] = '1'
> + // BiosReleaseDate[9] = '5';
> +
> + EfiTime.Second = RTC_INIT_SECOND;
> + EfiTime.Minute = RTC_INIT_MINUTE;
> + EfiTime.Hour = RTC_INIT_HOUR;
> + EfiTime.Day = (UINT8)(CharToUint(mBiosReleaseDate[3])*10 +
> CharToUint(mBiosReleaseDate[4]));
> + EfiTime.Month = (UINT8)(CharToUint(mBiosReleaseDate[0])*10 +
> CharToUint(mBiosReleaseDate[1]));
> + EfiTime.Year = (UINT16)(CharToUint(mBiosReleaseDate[8])*10 +
> CharToUint(mBiosReleaseDate[9]) + 2000);
> + EfiTime.Nanosecond = 0;
> + EfiTime.TimeZone = EFI_UNSPECIFIED_TIMEZONE;
> + EfiTime.Daylight = 1;
> +
> + DEBUG ((EFI_D_INFO, "Day:%d Month:%d Year:%d \n",
> (UINT32)EfiTime.Day, (UINT32)EfiTime.Month, (UINT32)EfiTime.Year));
> +
> + //
> + // Reset time value according to new RTC configuration
> + //
> + Status = gRT->SetTime (&EfiTime);
> + ASSERT_EFI_ERROR(Status);
> + }
> +
> + return;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SensorVar.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SensorVar.c
> new file mode 100644
> index 0000000000..5d13e99443
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SensorVar.c
> @@ -0,0 +1,112 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + SensorVar.c
> +
> +Abstract:
> +
> + Initialization for the Sensor Info variable.
> +
> +Revision History
> +
> +--*/
> +
> +#include "PlatformDxe.h"
> +#include "Guid/SensorInfoVariable.h"
> +
> +//
> +// Sensor Information (board specific)
> +//
> +
> +#define TEMPERATURE_SENSORS_COUNT 4
> +#define VOLTAGE_SENSORS_COUNT 6
> +#define FAN_SENSORS_COUNT 4
> +#define FAN_CONTROLLERS_COUNT 3
> +
> +TYPEDEF_TEMP_SENSOR_SECTION(TEMPERATURE_SENSORS_COUNT);
> +TYPEDEF_VOLT_SENSOR_SECTION(VOLTAGE_SENSORS_COUNT);
> +TYPEDEF_FAN_SENSOR_SECTION(FAN_SENSORS_COUNT);
> +TYPEDEF_FAN_CONTROLLER_SECTION(FAN_CONTROLLERS_COUNT);
> +TYPEDEF_SENSOR_INFO_VAR;
> +
> +SENSOR_INFO_VAR mSensorInfoData =
> +{
> + //
> + // Temperature Sensors
> + //
> + TEMPERATURE_SENSORS_COUNT,
> + {
> + { 0, 3, CPU_CORE_TEMPERATURE, TRUE },
> + { 0, 1, MOTHERBOARD_AMBIENT_TEMPERATURE, FALSE },
> + { 0, 2, VR_TEMPERATURE, FALSE },
> + { 0, 0, IOH_TEMPERATURE, FALSE }
> + },
> +
> + //
> + // Voltage Sensors
> + //
> + VOLTAGE_SENSORS_COUNT,
> + {
> + { 0, 0, PLUS_12_VOLTS },
> + { 0, 1, PLUS_5_VOLTS },
> + { 0, 2, PLUS_3P3_VOLTS },
> + { 0, 3, MCH_VCC_VOLTAGE },
> + { 0, 4, CPU_1_VCCP_VOLTAGE },
> + { 0, 5, CPU_VTT_VOLTAGE }
> + },
> +
> + //
> + // Fan Speed Sensors
> + //
> + FAN_SENSORS_COUNT,
> + {
> + { 0, 0, CPU_COOLING_FAN, FAN_4WIRE, 0 },
> + { 0, 1, AUX_COOLING_FAN, FAN_4WIRE, 1 },
> + { 0, 2, CHASSIS_INLET_FAN, FAN_3WIRE_VOLTAGE, 1 },
> + { 0, 3, CHASSIS_OUTLET_FAN, FAN_3WIRE_VOLTAGE, 2 }
> + },
> +
> + //
> + // Fan Speed Controllers
> + //
> + FAN_CONTROLLERS_COUNT,
> + {
> + { 0, 0, CPU_COOLING_FAN, { 0, 0xff, 0xff, 0xff } },
> + { 0, 1, CHASSIS_COOLING_FAN, { 1, 2, 0xff, 0xff } },
> + { 0, 2, CHASSIS_COOLING_FAN, { 3, 0xff, 0xff, 0xff } }
> + }
> +};
> +
> +/**
> +
> + Write the Sensor Info variable if it does not already exist.
> +
> +**/
> +VOID
> +InitializeSensorInfoVariable (
> + )
> +{
> + //
> + // Set the Sensor Info variable. If it already exists and the data matches,
> + // the variable driver will simply return without writing; otherwise, the
> + // driver will write the variable.
> + //
> + gRT->SetVariable (
> + gEfiSensorInfoVarNameWithPassword,
> + &gEfiSensorInfoVarGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> + EFI_VARIABLE_RUNTIME_ACCESS,
> + sizeof (SENSOR_INFO_VAR),
> + &mSensorInfoData
> + );
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SioPlatformPolicy.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SioPlatformPolicy.c
> new file mode 100644
> index 0000000000..32bee75f95
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SioPlatformPolicy.c
> @@ -0,0 +1,82 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + SioPlatformPolicy.c
> +
> +Abstract:
> +
> + Sio Platform Policy Setting.
> +
> +
> +--*/
> +
> +#include "PlatformDxe.h"
> +#include <Protocol/LpcWpc83627Policy.h>
> +
> +
> +EFI_WPC83627_POLICY_PROTOCOL mSio83627PolicyData = {
> + { EFI_WPC83627_COM1_ENABLE, // Com1
> + EFI_WPC83627_LPT1_ENABLE, // Lpt1
> + EFI_WPC83627_FDD_DISABLE, // Floppy
> + EFI_WPC83627_FDD_WRITE_ENABLE, // FloppyWriteProtect
> + EFI_WPC83627_RESERVED_DEFAULT, // Port80
> + EFI_WPC83627_ECIR_DISABLE, // CIR
> + EFI_WPC83627_PS2_KBC_ENABLE, // Ps2Keyboard
> + EFI_WPC83627_RESERVED_DEFAULT, // Ps2Mouse
> + EFI_WPC83627_COM2_ENABLE, // Com2
> + EFI_WPC83627_COM3_ENABLE, // Com3
> + EFI_WPC83627_COM4_ENABLE, // Com4
> + EFI_WPC83627_RESERVED_DEFAULT, // Dac
> + 0x00 // Rsvd
> + },
> + LptModeEcp, // LptMode
> +};
> +
> +/**
> +
> + Publish the platform SIO policy setting.
> +
> + @retval EFI_SUCCESS
> +
> +**/
> +VOID
> +InitSioPlatformPolicy(
> + )
> +{
> +
> + EFI_HANDLE Handle;
> + EFI_STATUS Status;
> +
> + Handle = NULL;
> +
> + if((mSystemConfiguration.Serial) || (mBoardFeatures &
> B_BOARD_FEATURES_SIO_NO_COM1)) {
> + mSio83627PolicyData.DeviceEnables.Com1 =
> EFI_WPC83627_COM1_DISABLE;
> + }
> +
> + if((mSystemConfiguration.Serial2) || ((mBoardFeatures &
> B_BOARD_FEATURES_SIO_COM2)==0)) {
> + mSio83627PolicyData.DeviceEnables.Com2 =
> EFI_WPC83627_COM2_DISABLE;
> + }
> +
> + mSio83627PolicyData.LptMode = mSystemConfiguration.ParallelMode;
> + if((!mSystemConfiguration.Parallel) || (mBoardFeatures &
> B_BOARD_FEATURES_SIO_NO_PARALLEL)) {
> + mSio83627PolicyData.DeviceEnables.Lpt1 = EFI_WPC83627_LPT1_DISABLE;
> + }
> +
> + Status = gBS->InstallProtocolInterface (
> + &Handle,
> + &gEfiLpcWpc83627PolicyProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + &mSio83627PolicyData
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.c
> new file mode 100644
> index 0000000000..f9b53ead95
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.c
> @@ -0,0 +1,148 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + SlotConfig.c
> +
> +Abstract:
> +
> + Sets platform/SKU specific expansion slot information.
> +
> +
> +
> +--*/
> +#include "SlotConfig.h"
> +
> +//
> +// Implementation
> +//
> +VOID
> +InitializeSlotInfo (
> + )
> +{
> + UINT16 BusSaveState;
> + UINT16 Vendor;
> + UINT8 CurrentBus;
> + UINTN i;
> + UINTN j;
> + EFI_HANDLE Handle;
> + EFI_STATUS Status;
> + BOOLEAN RunNext;
> +
> + //
> + // Loop through the slot table and see if any slots have cards in them
> + //
> + for (i = 0; i < mSlotBridgeTableSize; i++) {
> + //
> + // Initialize variable
> + //
> + RunNext = FALSE;
> +
> + //
> + // Hide mini PCIe slots per SKU
> + //
> + for (j = 0; j < mSlotInformation.NumberOfEntries; j++) {
> + if (mSlotInformation.SlotEntries[j].SmbiosSlotId ==
> mSlotBridgeTable[i].SmbiosSlotId) {
> + if ((mSlotInformation.SlotEntries[j].SmbiosSlotId == 0x02) &&
> + (mBoardFeatures & B_BOARD_FEATURES_NO_MINIPCIE)
> + ) {
> + mSlotInformation.SlotEntries[j].Disabled = TRUE;
> + RunNext = TRUE;
> + }
> + break;
> + }
> + }
> +
> + if (RunNext) {
> + //
> + // Skip slot device detection since the slot is disabled.
> + //
> + continue;
> + }
> +
> + //
> + // Check to see if the bridge has a bus number and assign one if not
> + //
> + BusSaveState = MmPci16 (
> + 0,
> + mSlotBridgeTable[i].Bus,
> + mSlotBridgeTable[i].Dev,
> + mSlotBridgeTable[i].Function,
> + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
> + );
> + if (BusSaveState == 0) {
> + //
> + // Assign temp bus number
> + //
> + MmPci16 (
> + 0,
> + mSlotBridgeTable[i].Bus,
> + mSlotBridgeTable[i].Dev,
> + mSlotBridgeTable[i].Function,
> + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
> + ) = DEF_BUS_CONFIG;
> + CurrentBus = DEF_BUS;
> + } else if (BusSaveState == 0xFFFF) {
> + //
> + // Bridge is disabled so continue with next entry in the table
> + //
> + continue;
> + } else {
> + //
> + // Use existing bus number
> + //
> + CurrentBus = (UINT8) BusSaveState & 0xFF;
> + }
> +
> + //
> + // Check to see if a device is behind the bridge
> + //
> + Vendor = MmPci16 (
> + 0,
> + CurrentBus,
> + mSlotBridgeTable[i].TargetDevice,
> + 0,
> + 0
> + );
> + if (Vendor != 0xFFFF) {
> + //
> + // Device found so make sure the slot is marked that way
> + //
> + for (j = 0; j < mSlotInformation.NumberOfEntries; j++) {
> + if (mSlotInformation.SlotEntries[j].SmbiosSlotId ==
> mSlotBridgeTable[i].SmbiosSlotId) {
> + mSlotInformation.SlotEntries[j].InUse = TRUE;
> + break;
> + }
> + }
> + }
> +
> + //
> + // Restore previous bus information
> + //
> + if (BusSaveState == 0) {
> + MmPci16 (
> + 0,
> + mSlotBridgeTable[i].Bus,
> + mSlotBridgeTable[i].Dev,
> + mSlotBridgeTable[i].Function,
> + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
> + ) = 0;
> + }
> + }
> +
> + Handle = NULL;
> + Status = gBS->InstallProtocolInterface (
> + &Handle,
> + &gEfiSmbiosSlotPopulationGuid,
> + EFI_NATIVE_INTERFACE,
> + &mSlotInformation
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.h
> new file mode 100644
> index 0000000000..738798261b
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.h
> @@ -0,0 +1,80 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + SlotConfig.c
> +
> +Abstract:
> +
> + Sets platform/SKU specific expansion slot information.
> +
> +
> +
> +
> +--*/
> +
> +#include "PlatformDxe.h"
> +#include <Protocol/SmbiosSlotPopulation.h>
> +#include <IndustryStandard/Pci22.h>
> +
> +
> +//
> +// Default bus number for the bridge
> +//
> +#define DEF_BUS_CONFIG 0x0101
> +#define DEF_BUS 0x01
> +
> +//
> +// Data structures for slot information
> +//
> +typedef struct {
> + UINT16 SmbiosSlotId;
> + UINT8 Bus;
> + UINT8 Dev;
> + UINT8 Function;
> + UINT8 TargetDevice;
> +} EFI_PCI_SLOT_BRIDGE_INFO;
> +
> +//
> +// Product specific bridge to slot routing information
> +//
> +EFI_PCI_SLOT_BRIDGE_INFO mSlotBridgeTable[] = {
> + {
> + 0x01, //PCIe x1 ICH (Bridge B0:D28:F1)
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
> + PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2,
> + 0
> + }
> +};
> +
> +UINTN mSlotBridgeTableSize =
> + sizeof(mSlotBridgeTable) / sizeof(EFI_PCI_SLOT_BRIDGE_INFO);
> +
> +//
> +// Slot entry table for IBX RVP
> +//
> +EFI_SMBIOS_SLOT_ENTRY mSlotEntries[] = {
> + {0x06, FALSE, TRUE}, // PCIe x16 Slot 1 (NOT USED)
> + {0x04, FALSE, TRUE}, // PCIe x16 Slot 2 (NOT USED)
> + {0x03, FALSE, TRUE}, // PCIe x4 Slot (NOT USED)
> + {0x02, FALSE, FALSE}, // Mini PCIe x1 Slot
> + {0x15, FALSE, TRUE}, // PCIe x1 Slot 2 (NOT USED)
> + {0x16, FALSE, TRUE}, // PCIe x1 Slot 3 (NOT USED)
> + {0x07, FALSE, FALSE}, // PCI Slot 1
> + {0x18, FALSE, TRUE}, // PCI Slot 2 (NOT USED)
> + {0x17, FALSE, TRUE}, // PCI Slot 3 (NOT USED)
> +};
> +
> +EFI_SMBIOS_SLOT_POPULATION_INFO mSlotInformation = {
> + sizeof(mSlotEntries) / sizeof(EFI_SMBIOS_SLOT_ENTRY),
> + mSlotEntries
> +};
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.c
> new file mode 100644
> index 0000000000..3900603d68
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.c
> @@ -0,0 +1,201 @@
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +--*/
> +
> +/** @file
> +**/
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Protocol/FirmwareVolume2.h>
> +#include <Protocol/PlatformGopPolicy.h>
> +
> +#include <Guid/SetupVariable.h>
> +#include <SetupMode.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +
> +PLATFORM_GOP_POLICY_PROTOCOL mPlatformGOPPolicy;
> +
> +//
> +// Function implementations
> +//
> +
> +/**
> + The function will execute with as the platform policy, and gives
> + the Platform Lid Status. IBV/OEM can customize this code for their specific
> + policy action.
> +
> + @param CurrentLidStatus Gives the current LID Status
> +
> + @retval EFI_SUCCESS.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetPlatformLidStatus (
> + OUT LID_STATUS *CurrentLidStatus
> +)
> +{
> + *CurrentLidStatus = LidOpen;
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + The function will execute and gives the Video Bios Table Size and Address.
> +
> + @param VbtAddress Gives the Physical Address of Video BIOS Table
> +
> + @param VbtSize Gives the Size of Video BIOS Table
> +
> + @retval EFI_STATUS.
> +
> +**/
> +
> +EFI_STATUS
> +EFIAPI
> +GetVbtData (
> + OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
> + OUT UINT32 *VbtSize
> +)
> +{
> + EFI_STATUS Status;
> + UINTN FvProtocolCount;
> + EFI_HANDLE *FvHandles;
> + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
> + UINTN Index;
> + UINT32 AuthenticationStatus;
> +
> + UINT8 *Buffer;
> + UINTN VbtBufferSize;
> +
> + Buffer = 0;
> + FvHandles = NULL;
> +
> + if (VbtAddress == NULL || VbtSize == NULL){
> + return EFI_INVALID_PARAMETER;
> + }
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiFirmwareVolume2ProtocolGuid,
> + NULL,
> + &FvProtocolCount,
> + &FvHandles
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + for (Index = 0; Index < FvProtocolCount; Index++) {
> + Status = gBS->HandleProtocol (
> + FvHandles[Index],
> + &gEfiFirmwareVolume2ProtocolGuid,
> + (VOID **) &Fv
> + );
> + VbtBufferSize = 0;
> + Status = Fv->ReadSection (
> + Fv,
> + &gBmpImageGuid,
> + EFI_SECTION_RAW,
> + 0,
> + (void **)&Buffer,
> + &VbtBufferSize,
> + &AuthenticationStatus
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + *VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
> + *VbtSize = (UINT32)VbtBufferSize;
> + Status = EFI_SUCCESS;
> + break;
> + }
> + }
> + } else {
> + Status = EFI_NOT_FOUND;
> + }
> +
> + if (FvHandles != NULL) {
> + gBS->FreePool (FvHandles);
> + FvHandles = NULL;
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Entry point for the Platform GOP Policy Driver.
> +
> + @param ImageHandle Image handle of this driver.
> + @param SystemTable Global system service table.
> +
> + @retval EFI_SUCCESS Initialization complete.
> + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to
> initialize the driver.
> +
> +**/
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformGOPPolicyEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + SYSTEM_CONFIGURATION SystemConfiguration;
> + UINTN VarSize;
> +
> +
> + gBS = SystemTable->BootServices;
> +
> + gBS->SetMem (
> + &mPlatformGOPPolicy,
> + sizeof (PLATFORM_GOP_POLICY_PROTOCOL),
> + 0
> + );
> +
> + mPlatformGOPPolicy.Revision =
> PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01;
> + mPlatformGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus;
> + mPlatformGOPPolicy.GetVbtData = GetVbtData;
> +
> + //
> + // Install protocol to allow access to this Policy.
> + //
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"Setup",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + if (SystemConfiguration.GOPEnable == 1)
> + {
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &ImageHandle,
> + &gPlatformGOPPolicyGuid,
> + &mPlatformGOPPolicy,
> + NULL
> + );
> + }
> +
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.i
> nf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.i
> nf
> new file mode 100644
> index 0000000000..948793f719
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.i
> nf
> @@ -0,0 +1,51 @@
> +#
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +##
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformGOPPolicy
> + FILE_GUID = 9737D7CA-D869-45e5-A5EF-75D9438688DE
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PlatformGOPPolicyEntryPoint
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32
> +#
> +
> +[Sources.common]
> + PlatformGopPolicy.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + UefiDriverEntryPoint
> + UefiRuntimeServicesTableLib
> +# DxeKscLib
> +
> +[Guids]
> + gBmpImageGuid
> + gEfiNormalSetupGuid
> +
> +[Protocols]
> + gEfiCpuIoProtocolGuid
> + gEfiFirmwareVolume2ProtocolGuid
> + gPlatformGOPPolicyGuid
> +
> +[Depex]
> + gEfiCpuIoProtocolGuid AND gEfiVariableArchProtocolGuid
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.c
> new file mode 100644
> index 0000000000..fc784034cd
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.c
> @@ -0,0 +1,169 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + PlatformInfoDxe.c
> +
> +Abstract:
> + Platform Info driver to public platform related HOB data
> +
> +--*/
> +
> +#include "PlatformInfoDxe.h"
> +
> +/**
> + Entry point for the driver.
> +
> + This routine get the platform HOB data from PEI and publish
> + as Platform Info variable that can be accessed during boot service and
> + runtime.
> +
> + @param ImageHandle Image Handle.
> + @param SystemTable EFI System Table.
> +
> + @retval Status Function execution status.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PlatformInfoInit (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PLATFORM_INFO_HOB *PlatformInfoHobPtr;
> + EFI_PEI_HOB_POINTERS GuidHob;
> + EFI_PLATFORM_INFO_HOB TmpHob;
> + UINTN VarSize;
> + EFI_OS_SELECTION_HOB *OsSlectionHobPtr;
> + UINT8 Selection;
> + SYSTEM_CONFIGURATION SystemConfiguration;
> + UINT8 *LpssDataHobPtr;
> + UINT8 *LpssDataVarPtr;
> + UINTN i;
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> +
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + VarSize = sizeof(Selection);
> + Status = gRT->GetVariable(
> + L"OsSelection",
> + &gOsSelectionVariableGuid,
> + NULL,
> + &VarSize,
> + &Selection
> + );
> +
> + if (EFI_ERROR(Status)) {
> + Selection = SystemConfiguration.ReservedO;
> + Status = gRT->SetVariable (
> + L"OsSelection",
> + &gOsSelectionVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + sizeof(Selection),
> + &Selection
> + );
> + }
> +
> + GuidHob.Raw = GetHobList ();
> + if (GuidHob.Raw != NULL) {
> + if ((GuidHob.Raw = GetNextGuidHob (&gOsSelectionVariableGuid,
> GuidHob.Raw)) != NULL) {
> + OsSlectionHobPtr = GET_GUID_HOB_DATA (GuidHob.Guid);
> +
> + if (OsSlectionHobPtr->OsSelectionChanged) {
> + SystemConfiguration.ReservedO = OsSlectionHobPtr->OsSelection;
> +
> + //
> + // Load Audio default configuration
> + //
> + SystemConfiguration.Lpe = OsSlectionHobPtr->Lpe;
> + SystemConfiguration.PchAzalia = OsSlectionHobPtr->PchAzalia;
> +
> + //
> + // Load LPSS and SCC default configurations
> + //
> + LpssDataHobPtr = &OsSlectionHobPtr->LpssData.LpssPciModeEnabled;
> + LpssDataVarPtr = &SystemConfiguration.LpssPciModeEnabled;
> + for (i = 0; i < sizeof(EFI_PLATFORM_LPSS_DATA); i++) {
> + *LpssDataVarPtr = *LpssDataHobPtr;
> + LpssDataVarPtr++;
> + LpssDataHobPtr++;
> + }
> +
> + SystemConfiguration.GOPEnable = TRUE;
> +
> + Status = gRT->SetVariable (
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_NON_VOLATILE,
> + sizeof(SYSTEM_CONFIGURATION),
> + &SystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> + }
> + }
> +
> + GuidHob.Raw = GetHobList ();
> + if (GuidHob.Raw == NULL) {
> + return EFI_NOT_FOUND;
> + }
> +
> + if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid,
> GuidHob.Raw)) != NULL) {
> + PlatformInfoHobPtr = GET_GUID_HOB_DATA (GuidHob.Guid);
> + VarSize = sizeof(EFI_PLATFORM_INFO_HOB);
> + Status = gRT->GetVariable(
> + L"PlatformInfo",
> + &gEfiVlv2VariableGuid,
> + NULL,
> + &VarSize,
> + &TmpHob
> + );
> +
> + if (EFI_ERROR(Status) || CompareMem (&TmpHob, PlatformInfoHobPtr,
> VarSize)) {
> +
> + //
> + // Write the Platform Info to volatile memory
> + //
> + Status = gRT->SetVariable(
> + L"PlatformInfo",
> + &gEfiVlv2VariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_NON_VOLATILE,
> + sizeof(EFI_PLATFORM_INFO_HOB),
> + PlatformInfoHobPtr
> + );
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.h
> new file mode 100644
> index 0000000000..615b32bb08
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.h
> @@ -0,0 +1,30 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> + PlatformInfoDxe.h
> +
> +Abstract:
> + Platform Info Driver.
> +
> +--*/
> +
> +#ifndef _PLATFORM_INFO_DRIVER_H_
> +#define _PLATFORM_INFO_DRIVER_H_
> +
> +#include <PiDxe.h>
> +#include <Library/HobLib.h>
> +#include <Guid/PlatformInfo.h>
> +#include <Guid/GlobalVariable.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Guid/Vlv2Variable.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <SetupMode.h>
> +#include <Guid/OsSelection.h>
> +#include <Guid/SetupVariable.h>
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.inf
> new file mode 100644
> index 0000000000..ae3c2bf41b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.inf
> @@ -0,0 +1,52 @@
> +#
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +# Module Name:
> +#
> +# PlatformInfoDxe.inf
> +#
> +# Abstract:
> +#
> +#
> +--*/
> +
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformInfoDxe
> + FILE_GUID = 025F738B-4EBD-4d55-B728-5F421B601F1F
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PlatformInfoInit
> +
> +[sources]
> + PlatformInfoDxe.c
> + PlatformInfoDxe.h
> +
> +[Guids]
> + gEfiAcpiVariableGuid # ALWAYS_CONSUMED
> + gEfiPlatformInfoGuid # ALWAYS_CONSUMED
> + gEfiVlv2VariableGuid
> + gEfiNormalSetupGuid
> + gOsSelectionVariableGuid
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + HobLib
> + UefiRuntimeServicesTableLib
> + UefiDriverEntryPoint
> + BaseMemoryLib
> +
> +[Depex]
> + gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c
> new file mode 100644
> index 0000000000..c906562c7e
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c
> @@ -0,0 +1,434 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + BootMode.c
> +
> +Abstract:
> +
> + EFI PEIM to provide the platform support functionality on the Thurley.
> +
> +
> +--*/
> +
> +#include "PlatformEarlyInit.h"
> +
> +
> +#define NORMALMODE 0
> +#define RECOVERYMODE 1
> +#define SAFEMODE 2
> +#define MANUFACTURINGMODE 3
> +
> +#define GPIO_SSUS_OFFSET 0x2000
> +#define PMU_PWRBTN_B_OFFSET 0x88
> +
> +EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = {
> + (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gEfiPeiBootInRecoveryModePpiGuid,
> + NULL
> +};
> +
> +/**
> + Return the setting of the Bios configuration jumper
> +
> + @param VOID
> +
> + @retval RECOVERYMODE jumper set to recovery mode
> + @retval SAFEMODE jumper set to config mode
> + @retval NORMALMODE jumper in normal mode
> +
> +**/
> +UINTN
> +GetConfigJumper(
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + )
> +{
> + //
> + // Do the Forced recovery detection based on logic chart above
> + //
> + if (IsRecoveryJumper(PeiServices, PlatformInfoHob)) {
> + return RECOVERYMODE;
> + } else {
> + return NORMALMODE;
> + }
> +}
> +
> +BOOLEAN
> +CheckIfRecoveryMode(
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + )
> +{
> + if (GetConfigJumper(PeiServices, PlatformInfoHob) == RECOVERYMODE) {
> + return TRUE;
> + }
> + return FALSE;
> +}
> +
> +BOOLEAN
> +CheckIfSafeMode(
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + )
> +{
> + if (GetConfigJumper(PeiServices, PlatformInfoHob) == SAFEMODE) {
> + return TRUE;
> + }
> + return FALSE;
> +}
> +
> +BOOLEAN
> +CheckIfManufacturingMode (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
> + UINT32 Attributes;
> + UINTN DataSize;
> + CHAR16 VarName[] = MFGMODE_VARIABLE_NAME;
> + UINT8 MfgMode;
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (void **)&Variable
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Check if SW MMJ mode
> + //
> + Attributes = (EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS);
> + DataSize = sizeof (MFG_MODE_VAR);
> +
> + Status = Variable->GetVariable (
> + Variable,
> + VarName,
> + &gMfgModeVariableGuid,
> + &Attributes,
> + &DataSize,
> + &MfgMode
> + );
> + if (!(EFI_ERROR (Status))) {
> + return TRUE;
> + }
> + return FALSE;
> +}
> +
> +EFI_STATUS
> +UpdateBootMode (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + )
> +{
> + EFI_STATUS Status;
> + EFI_BOOT_MODE BootMode;
> + UINT16 SleepType;
> + CHAR16 *strBootMode;
> + PEI_CAPSULE_PPI *Capsule;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
> + SYSTEM_CONFIGURATION SystemConfiguration;
> + UINTN VarSize;
> + volatile UINT32 GpioValue;
> + BOOLEAN IsFirstBoot;
> + UINT32 Data32;
> +
> + Status = (*PeiServices)->GetBootMode(
> + PeiServices,
> + &BootMode
> + );
> + ASSERT_EFI_ERROR (Status);
> + if (BootMode == BOOT_IN_RECOVERY_MODE){
> + return Status;
> + }
> + GetWakeupEventAndSaveToHob (PeiServices);
> +
> + //
> + // Let's assume things are OK if not told otherwise
> + //
> + BootMode = BOOT_WITH_FULL_CONFIGURATION;
> +
> + //
> + // When this boot is WDT reset, the system needs booting with
> CrashDump function eanbled.
> + //
> + Data32 = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_TCO_STS);
> +
> + //
> + // Check Power Button, click the power button, the system will boot in fast
> boot mode,
> + // if it is pressed and hold for a second, it will boot in
> FullConfiguration/setup mode.
> + //
> + GpioValue = MmioRead32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET +
> PMU_PWRBTN_B_OFFSET); // The value of GPIOS_16 (PMU_PWRBTN_B)
> + if (((GpioValue & BIT0) != 0)&&((Data32 &
> B_PCH_TCO_STS_SECOND_TO) != B_PCH_TCO_STS_SECOND_TO)){
> + IsFirstBoot = PcdGetBool(PcdBootState);
> + if (!IsFirstBoot){
> + VarSize = sizeof (SYSTEM_CONFIGURATION);
> + ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (void **)&Variable
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Use normal setup default from NVRAM variable,
> + // the Platform Mode (manufacturing/safe/normal) is handle in
> PeiGetVariable.
> + //
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = Variable->GetVariable (
> + Variable,
> + L"Setup",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = Variable->GetVariable(
> + Variable,
> + L"SetupRecovery",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + if (SystemConfiguration.FastBoot == 1) {
> + BootMode = BOOT_WITH_MINIMAL_CONFIGURATION;
> + }
> + }
> + }
> +
> + //
> + // Check if we need to boot in forced recovery mode
> + //
> + if (CheckIfRecoveryMode(PeiServices, PlatformInfoHob)) {
> + BootMode = BOOT_IN_RECOVERY_MODE;
> + }
> +
> + if (BootMode == BOOT_IN_RECOVERY_MODE) {
> + Status = (*PeiServices)->InstallPpi (
> + PeiServices,
> + &mPpiListRecoveryBootMode
> + );
> + ASSERT_EFI_ERROR (Status);
> + } else {
> + if (GetSleepTypeAfterWakeup (PeiServices, &SleepType)) {
> + switch (SleepType) {
> + case V_PCH_ACPI_PM1_CNT_S3:
> + BootMode = BOOT_ON_S3_RESUME;
> +
> + //
> + // Determine if we're in capsule update mode
> + //
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gPeiCapsulePpiGuid,
> + 0,
> + NULL,
> + (void **)&Capsule
> + );
> +
> + if (Status == EFI_SUCCESS) {
> + if (Capsule->CheckCapsuleUpdate ((EFI_PEI_SERVICES**)PeiServices)
> == EFI_SUCCESS) {
> + BootMode = BOOT_ON_FLASH_UPDATE;
> + }
> + }
> +
> + break;
> +
> + case V_PCH_ACPI_PM1_CNT_S4:
> + BootMode = BOOT_ON_S4_RESUME;
> + break;
> +
> + case V_PCH_ACPI_PM1_CNT_S5:
> + BootMode = BOOT_ON_S5_RESUME;
> + break;
> + } // switch (SleepType)
> + }
> +
> + //
> + // Check for Safe Mode
> + //
> + }
> +
> + switch (BootMode) {
> + case BOOT_WITH_FULL_CONFIGURATION:
> + strBootMode = L"BOOT_WITH_FULL_CONFIGURATION";
> + break;
> + case BOOT_WITH_MINIMAL_CONFIGURATION:
> + strBootMode = L"BOOT_WITH_MINIMAL_CONFIGURATION";
> + break;
> + case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:
> + strBootMode = L"BOOT_ASSUMING_NO_CONFIGURATION_CHANGES";
> + break;
> + case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:
> + strBootMode =
> L"BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS";
> + break;
> + case BOOT_WITH_DEFAULT_SETTINGS:
> + strBootMode = L"BOOT_WITH_DEFAULT_SETTINGS";
> + break;
> + case BOOT_ON_S4_RESUME:
> + strBootMode = L"BOOT_ON_S4_RESUME";
> + break;
> + case BOOT_ON_S5_RESUME:
> + strBootMode = L"BOOT_ON_S5_RESUME";
> + break;
> + case BOOT_ON_S2_RESUME:
> + strBootMode = L"BOOT_ON_S2_RESUME";
> + break;
> + case BOOT_ON_S3_RESUME:
> + strBootMode = L"BOOT_ON_S3_RESUME";
> + break;
> + case BOOT_ON_FLASH_UPDATE:
> + strBootMode = L"BOOT_ON_FLASH_UPDATE";
> + break;
> + case BOOT_IN_RECOVERY_MODE:
> + strBootMode = L"BOOT_IN_RECOVERY_MODE";
> + break;
> + default:
> + strBootMode = L"Unknown boot mode";
> + } // switch (BootMode)
> +
> + DEBUG ((EFI_D_ERROR, "Setting BootMode to %s\n", strBootMode));
> + Status = (*PeiServices)->SetBootMode(
> + PeiServices,
> + BootMode
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> +/**
> + Get sleep type after wakeup
> +
> + @param PeiServices Pointer to the PEI Service Table.
> + @param SleepType Sleep type to be returned.
> +
> + @retval TRUE A wake event occured without power failure.
> + @retval FALSE Power failure occured or not a wakeup.
> +
> +**/
> +BOOLEAN
> +GetSleepTypeAfterWakeup (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + OUT UINT16 *SleepType
> + )
> +{
> + UINT16 Pm1Sts;
> + UINT16 Pm1Cnt;
> + UINT16 GenPmCon1;
> + GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS +
> R_PCH_PMC_GEN_PMCON_1);
> +
> + //
> + // Read the ACPI registers
> + //
> + Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
> + Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);
> +
> + if ((GenPmCon1 & (B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR |
> B_PCH_PMC_GEN_PMCON_GEN_RST_STS)) ||
> + (Pm1Sts & B_PCH_ACPI_PM1_STS_PRBTNOR)) {
> + //
> + // If power failure indicator, then don't attempt s3 resume.
> + // Clear PM1_CNT of S3 and set it to S5 as we just had a power failure, and
> memory has
> + // lost already. This is to make sure no one will use PM1_CNT to check for
> S3 after
> + // power failure.
> + //
> + if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) ==
> V_PCH_ACPI_PM1_CNT_S3) {
> + Pm1Cnt = ((Pm1Cnt & ~B_PCH_ACPI_PM1_CNT_SLP_TYP) |
> V_PCH_ACPI_PM1_CNT_S5);
> + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
> + }
> + //
> + // Clear Wake Status (WAK_STS)
> + //
> + IoWrite16 ((ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS),
> B_PCH_ACPI_PM1_STS_WAK);
> + }
> + //
> + // Get sleep type if a wake event occurred and there is no power failure
> + //
> + if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) ==
> V_PCH_ACPI_PM1_CNT_S3) {
> + *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
> + return TRUE;
> + } else if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) ==
> V_PCH_ACPI_PM1_CNT_S4){
> + *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
> + return TRUE;
> + }
> + return FALSE;
> +}
> +
> +VOID
> +SetPlatformBootMode (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + )
> +{
> + EFI_PLATFORM_SETUP_ID PlatformSetupId;
> +
> + ZeroMem(&PlatformSetupId, sizeof (EFI_PLATFORM_SETUP_ID));
> +
> + CopyMem (&PlatformSetupId.SetupGuid,
> + &gEfiNormalSetupGuid,
> + sizeof (EFI_GUID));
> +
> + if (CheckIfRecoveryMode(PeiServices, PlatformInfoHob)) {
> + //
> + // Recovery mode
> + //
> + CopyMem (&PlatformSetupId.SetupName,
> + &NORMAL_SETUP_NAME,
> + StrSize (NORMAL_SETUP_NAME));
> + PlatformSetupId.PlatformBootMode = PLATFORM_RECOVERY_MODE;
> + } else if (CheckIfSafeMode(PeiServices, PlatformInfoHob)) {
> + //
> + // Safe mode also called config mode or maintenace mode.
> + //
> + CopyMem (&PlatformSetupId.SetupName,
> + &NORMAL_SETUP_NAME,
> + StrSize (NORMAL_SETUP_NAME));
> + PlatformSetupId.PlatformBootMode = PLATFORM_SAFE_MODE;
> +
> + } else if(0) { // else if (CheckIfManufacturingMode(PeiServices)) {
> + //
> + // Manufacturing mode
> + //
> + CopyMem (&PlatformSetupId.SetupName,
> + MANUFACTURE_SETUP_NAME,
> + StrSize (MANUFACTURE_SETUP_NAME));
> + PlatformSetupId.PlatformBootMode =
> PLATFORM_MANUFACTURING_MODE;
> +
> + } else {
> + //
> + // Default to normal mode.
> + //
> + CopyMem (&PlatformSetupId.SetupName,
> + &NORMAL_SETUP_NAME,
> + StrSize (NORMAL_SETUP_NAME));
> + PlatformSetupId.PlatformBootMode = PLATFORM_NORMAL_MODE;
> + }
> +
> + BuildGuidDataHob (
> + &gEfiPlatformBootModeGuid,
> + &PlatformSetupId,
> + sizeof (EFI_PLATFORM_SETUP_ID)
> + );
> + return;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c
> new file mode 100644
> index 0000000000..a3a3d5cbc9
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c
> @@ -0,0 +1,44 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + CpuInitPeim.c
> +
> +Abstract:
> +
> + Functions for LpcSio initilization
> + It is needed for early onboard LAN controller disable/enable in platform
> setup.
> +
> +--*/
> +
> +#include "PlatformEarlyInit.h"
> +
> +
> +EFI_STATUS
> +PlatformCpuInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration,
> + IN EFI_PLATFORM_CPU_INFO *PlatformCpuInfo
> + )
> +{
> + BOOLEAN ResetRequired;
> +
> + //
> + // Variable initialization
> + //
> + ResetRequired = FALSE;
> +
> +
> + if (ResetRequired) {
> + CpuOnlyReset(PeiServices);
> + }
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c
> new file mode 100644
> index 0000000000..3fda6313d0
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c
> @@ -0,0 +1,319 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + Dimm.c
> +
> +Abstract:
> +
> + PPI for reading SPD modules on DIMMs.
> +
> +--*/
> +
> +
> +//
> +// Header Files
> +//
> +#include "Platformearlyinit.h"
> +
> +#define DIMM_SOCKETS 4 // Total number of DIMM sockets allowed on
> + // the platform
> +#define DIMM_SEGMENTS 1 // Total number of Segments Per DIMM.
> +#define MEMORY_CHANNELS 2 // Total number of memory channels
> + // populated on the system board
> +//
> +// Prototypes
> +//
> +
> +EFI_STATUS
> +EFIAPI
> +GetDimmState (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN PEI_PLATFORM_DIMM_PPI *This,
> + IN UINT8 Dimm,
> + OUT PEI_PLATFORM_DIMM_STATE *State
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +SetDimmState (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN PEI_PLATFORM_DIMM_PPI *This,
> + IN UINT8 Dimm,
> + IN PEI_PLATFORM_DIMM_STATE *State
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +ReadSpd (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN PEI_PLATFORM_DIMM_PPI *This,
> + IN UINT8 Dimm,
> + IN UINT8 Offset,
> + IN UINTN Count,
> + IN OUT UINT8 *Buffer
> + );
> +
> +static PEI_PLATFORM_DIMM_PPI mGchDimmPpi = {
> + DIMM_SOCKETS,
> + DIMM_SEGMENTS,
> + MEMORY_CHANNELS,
> + GetDimmState,
> + SetDimmState,
> + ReadSpd
> +};
> +
> +static EFI_PEI_PPI_DESCRIPTOR mPpiPlatformDimm = {
> + (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gPeiPlatformDimmPpiGuid,
> + &mGchDimmPpi
> +};
> +
> +
> +//
> +// Functions
> +//
> +
> +/**
> + This function returns the current state of a single DIMM. Present indicates
> + that the DIMM slot is physically populated. Disabled indicates that the
> DIMM
> + should not be used.
> +
> + @param PeiServices PEI services table pointer
> + @param This PPI pointer
> + @param Dimm DIMM to read from
> + @param State Pointer to a return buffer to be updated with the
> current state
> + of the DIMM
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetDimmState (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN PEI_PLATFORM_DIMM_PPI *This,
> + IN UINT8 Dimm,
> + OUT PEI_PLATFORM_DIMM_STATE *State
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 Buffer;
> +
> + PEI_ASSERT (PeiServices, (Dimm < This->DimmSockets));
> +
> + //
> + // A failure here does not necessarily mean that no DIMM is present.
> + // Read a single byte. All we care about is the return status.
> + //
> + Status = ReadSpd (
> + PeiServices,
> + This,
> + Dimm,
> + 0,
> + 1,
> + &Buffer
> + );
> +
> + if (EFI_ERROR (Status)) {
> + State->Present = 0;
> + } else {
> + State->Present = 1;
> + }
> +
> + //
> + // BUGBUG: Update to check platform variable when it is available
> + //
> + State->Disabled = 0;
> + State->Reserved = 0;
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +
> + This function updates the state of a single DIMM.
> +
> + @param PeiServices PEI services table pointer
> + @param This PPI pointer
> + @param Dimm DIMM to set state for
> + @param State Pointer to the state information to set.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> + @retval EFI_UNSUPPORTED The function is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SetDimmState (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN PEI_PLATFORM_DIMM_PPI *This,
> + IN UINT8 Dimm,
> + IN PEI_PLATFORM_DIMM_STATE *State
> + )
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + This function reads SPD information from a DIMM.
> +
> + PeiServices PEI services table pointer
> + This PPI pointer
> + Dimm DIMM to read from
> + Offset Offset in DIMM
> + Count Number of bytes
> + Buffer Return buffer
> +
> + @param EFI_SUCCESS The function completed successfully.
> + @param EFI_DEVICE_ERROR The DIMM being accessed reported a
> device error,
> + does not have an SPD module, or is not installed in
> + the system.
> + @retval EFI_TIMEOUT Time out trying to read the SPD module.
> + @retval EFI_INVALID_PARAMETER A parameter was outside the legal
> limits.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +ReadSpd (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN PEI_PLATFORM_DIMM_PPI *This,
> + IN UINT8 Dimm,
> + IN UINT8 Offset,
> + IN UINTN Count,
> + IN OUT UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + PEI_SMBUS_PPI *Smbus;
> + UINTN Index;
> + UINTN Index1;
> + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
> + EFI_SMBUS_DEVICE_COMMAND Command;
> + UINTN Length;
> +
> + Status = (**PeiServices).LocatePpi (
> + PeiServices,
> + &gPeiSmbusPpiGuid, // GUID
> + 0, // INSTANCE
> + NULL, // EFI_PEI_PPI_DESCRIPTOR
> + &Smbus // PPI
> + );
> + ASSERT_PEI_ERROR (PeiServices, Status);
> +
> + switch (Dimm) {
> + case 0:
> + SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_A_1 >> 1;
> + break;
> + case 1:
> + SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_A_2 >> 1;
> + break;
> + case 2:
> + SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_B_1 >> 1;
> + break;
> + case 3:
> + SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_B_2 >> 1;
> + break;
> + default:
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Index = Count % 4;
> + if (Index != 0) {
> + //
> + // read the first serveral bytes to speed up following reading
> + //
> + for (Index1 = 0; Index1 < Index; Index1++) {
> + Length = 1;
> + Command = Offset + Index1;
> + Status = Smbus->Execute (
> + PeiServices,
> + Smbus,
> + SlaveAddress,
> + Command,
> + EfiSmbusReadByte,
> + FALSE,
> + &Length,
> + &Buffer[Index1]
> + );
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> + }
> + }
> +
> + //
> + // Now collect all the remaining bytes on 4 bytes block
> + //
> + for (; Index < Count; Index += 2) {
> + Command = Index + Offset;
> + Length = 2;
> + Status = Smbus->Execute (
> + PeiServices,
> + Smbus,
> + SlaveAddress,
> + Command,
> + EfiSmbusReadWord,
> + FALSE,
> + &Length,
> + &Buffer[Index]
> + );
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + Index += 2;
> + Command = Index + Offset;
> + Length = 2;
> + Status = Smbus->Execute (
> + PeiServices,
> + Smbus,
> + SlaveAddress,
> + Command,
> + EfiSmbusReadWord,
> + FALSE,
> + &Length,
> + &Buffer[Index]
> + );
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function initializes the PEIM. It simply installs the DIMM PPI.
> +
> + @param FfsHeader Not used by this function
> + @param PeiServices Pointer to PEI services table
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeimInitializeDimm (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *SmbusPpi
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = (**PeiServices).InstallPpi (
> + PeiServices,
> + &mPpiPlatformDimm
> + );
> + ASSERT_PEI_ERROR (PeiServices, Status);
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c
> new file mode 100644
> index 0000000000..f32eaac479
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c
> @@ -0,0 +1,143 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +Module Name:
> +
> + FlashMap.c
> +
> +Abstract:
> +
> + Build GUIDed HOBs for platform specific flash map.
> +
> +--*/
> +
> +#include "Efi.h"
> +#include "Pei.h"
> +#include "PeiLib.h"
> +#include "PeiLib.h"
> +#include "EfiFlashMap.h"
> +#include EFI_PROTOCOL_CONSUMER (FirmwareVolumeBlock)
> +#include EFI_GUID_DEFINITION (FlashMapHob)
> +#include EFI_GUID_DEFINITION (SystemNvDataGuid)
> +#include EFI_GUID_DEFINITION (FirmwareFileSystem)
> +
> +EFI_GUID mFvBlockGuid =
> EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID;
> +EFI_GUID mFfsGuid =
> EFI_FIRMWARE_FILE_SYSTEM_GUID;
> +EFI_GUID mSystemDataGuid =
> EFI_SYSTEM_NV_DATA_HOB_GUID;
> +
> +static EFI_FLASH_AREA_DATA mFlashAreaData[] = {
> + //
> + // Variable area
> + //
> + { FixedPcdGet32 (PcdFlashNvStorageVariableBase),
> + FixedPcdGet32 (PcdFlashNvStorageVariableSize),
> + EFI_FLASH_AREA_SUBFV | EFI_FLASH_AREA_MEMMAPPED_FV,
> + EFI_FLASH_AREA_EFI_VARIABLES },
> +
> + //
> + // Boot block 2nd part
> + //
> + { FixedPcdGet32 (PcdFlashFvRecovery2Base),
> + FixedPcdGet32 (PcdFlashFvRecovery2Size),
> + EFI_FLASH_AREA_SUBFV | EFI_FLASH_AREA_MEMMAPPED_FV,
> + EFI_FLASH_AREA_FTW_BACKUP },
> +
> + //
> + // Recovery FV
> + //
> + { FixedPcdGet32 (PcdFlashFvRecoveryBase),
> + FixedPcdGet32 (PcdFlashFvRecoverySize),
> + EFI_FLASH_AREA_FV | EFI_FLASH_AREA_MEMMAPPED_FV,
> + EFI_FLASH_AREA_RECOVERY_BIOS },
> +
> + //
> + // Main FV
> + //
> + { FixedPcdGet32 (PcdFlashFvMainBase),
> + FixedPcdGet32 (PcdFlashFvMainSize),
> + EFI_FLASH_AREA_FV | EFI_FLASH_AREA_MEMMAPPED_FV,
> + EFI_FLASH_AREA_MAIN_BIOS }
> +
> +};
> +
> +#define NUM_FLASH_AREA_DATA (ARRAY_SIZE (mFlashAreaData))
> +
> +/**
> + Build GUID HOBs for platform specific flash map.
> +
> + @param FfsHeader Pointer this FFS file header.
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval EFI_SUCCESS Guid HOBs for platform flash map is built.
> + @retval Otherwise Failed to build the Guid HOB data.
> +
> +**/
> +EFI_STATUS
> +PeimInitializeFlashMap (
> + IN EFI_FFS_FILE_HEADER *FfsHeader,
> + IN EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + UINTN Index;
> + EFI_FLASH_AREA_HOB_DATA FlashHobData;
> +
> + //
> + // Build flash area entries as GUIDed HOBs.
> + //
> + for (Index = 0; Index < NUM_FLASH_AREA_DATA; Index++) {
> + ZeroMem(&FlashHobData, sizeof (EFI_FLASH_AREA_HOB_DATA));
> +
> + FlashHobData.AreaType = mFlashAreaData[Index].AreaType;
> + FlashHobData.NumberOfEntries = 1;
> + FlashHobData.SubAreaData.Attributes =
> mFlashAreaData[Index].Attributes;
> + FlashHobData.SubAreaData.Base = (EFI_PHYSICAL_ADDRESS) (UINTN)
> mFlashAreaData[Index].Base;
> + FlashHobData.SubAreaData.Length = (EFI_PHYSICAL_ADDRESS) (UINTN)
> mFlashAreaData[Index].Length;
> +
> + switch (FlashHobData.AreaType) {
> + case EFI_FLASH_AREA_RECOVERY_BIOS:
> + case EFI_FLASH_AREA_MAIN_BIOS:
> + CopyMem (
> + &FlashHobData.AreaTypeGuid,
> + &mFfsGuid,
> + sizeof (EFI_GUID)
> + );
> + CopyMem (
> + &FlashHobData.SubAreaData.FileSystem,
> + &mFvBlockGuid,
> + sizeof (EFI_GUID)
> + );
> + break;
> +
> + case EFI_FLASH_AREA_GUID_DEFINED:
> + CopyMem (
> + &FlashHobData.AreaTypeGuid,
> + &mSystemDataGuid,
> + sizeof (EFI_GUID)
> + );
> + CopyMem (
> + &FlashHobData.SubAreaData.FileSystem,
> + &mFvBlockGuid,
> + sizeof (EFI_GUID)
> + );
> + break;
> +
> + default:
> + break;
> + }
> +
> + PeiBuildHobGuidData(PeiServices,
> + &gEfiFlashMapHobGuid,
> + &FlashHobData,
> + sizeof (EFI_FLASH_AREA_HOB_DATA)
> + );
> + }
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c
> new file mode 100644
> index 0000000000..6711f54863
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c
> @@ -0,0 +1,168 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + LegacySpeaker.c
> +
> +Abstract:
> +
> + This file implements PEIM for Legacy Speaker. This file is valid for platforms
> both
> + on IA32 and Itanium Product Family
> +
> +--*/
> +
> +#include "PlatformEarlyInit.h"
> +
> +EFI_STATUS
> +OutputBeep (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINTN NumberOfBeep,
> + IN UINTN BeepDuration,
> + IN UINTN TimerInterval
> + );
> +
> +/**
> + This function will enable the speaker to generate beep
> +
> + @param PeiServices PeiServices to locate PPI
> +
> + @retval EFI_STATUS
> +
> +**/
> +EFI_STATUS
> +TurnOnSpeaker (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + UINT8 Data;
> + Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);
> + Data |= 0x03;
> + IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function will stop beep from speaker.
> +
> + @param PeiServices PeiServices to locate PPI
> +
> + @retval Status
> +
> +**/
> +EFI_STATUS
> +TurnOffSpeaker (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + UINT8 Data;
> +
> + Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);
> + Data &= 0xFC;
> + IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);
> + return EFI_SUCCESS;
> +}
> +
> +
> +EFI_STATUS
> +OutputBeep (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINTN NumberOfBeep,
> + IN UINTN BeepDuration,
> + IN UINTN TimeInterval
> + )
> +{
> + UINTN Num;
> + EFI_PEI_STALL_PPI* StallPpi;
> +
> + (**PeiServices).LocatePpi (PeiServices, &gEfiPeiStallPpiGuid, 0, NULL,
> (void **)&StallPpi);
> +
> + for (Num=0; Num < NumberOfBeep; Num++) {
> + TurnOnSpeaker (PeiServices);
> + StallPpi->Stall(PeiServices, StallPpi, BeepDuration);
> + TurnOffSpeaker(PeiServices);
> + StallPpi->Stall(PeiServices, StallPpi, TimeInterval);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function will program the speaker tone frequency. The value should
> be with 64k
> + boundary since it takes only 16 bit value which gets programmed in two
> step IO opearattion
> +
> + Frequency - A value which should be 16 bit only.
> +
> + EFI_SUCESS
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +ProgramToneFrequency (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINT16 Frequency
> + )
> +{
> + UINT8 Data;
> +
> + Data = 0xB6;
> + IoWrite8(EFI_TIMER_CONTROL_PORT, Data);
> +
> + Data = (UINT8)(Frequency & 0x00FF);
> + IoWrite8(EFI_TIMER_2_PORT, Data);
> + Data = (UINT8)((Frequency & 0xFF00) >> 8);
> + IoWrite8(EFI_TIMER_2_PORT, Data);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function will generate the beep for specified duration.
> +
> + @param PeiServices PeiServices to locate various PPIs
> + @param NumberOfBeeps Number of beeps which user want to
> produce
> + @param BeepDuration Duration for speaker gate need to be enabled
> + @param TimeInterval Interval between each beep
> +
> + @retval EFI_STATUS
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +GenerateBeepTone (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINTN NumberOfBeeps,
> + IN UINTN BeepDuration,
> + IN UINTN TimeInterval
> + )
> +{
> +
> + if ((NumberOfBeeps == 1) && (BeepDuration == 0) && (TimeInterval == 0))
> {
> + TurnOnSpeaker (PeiServices);
> + return EFI_SUCCESS;
> + }
> +
> + if ((NumberOfBeeps == 0) && (BeepDuration == 0) && (TimeInterval == 0))
> {
> + TurnOffSpeaker (PeiServices);
> + return EFI_SUCCESS;
> + }
> +
> + if (BeepDuration == 0) {
> + BeepDuration = EFI_DEFAULT_SHORT_BEEP_DURATION;
> + }
> +
> + if (TimeInterval == 0) {
> + TimeInterval = EFI_DEFAULT_BEEP_TIME_INTERVAL;
> + }
> +
> + OutputBeep (PeiServices, NumberOfBeeps, BeepDuration, TimeInterval);
> + return EFI_SUCCESS;
> +
> +
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h
> new file mode 100644
> index 0000000000..dee022bf9b
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h
> @@ -0,0 +1,71 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + LegacySpeaker.h
> +
> +Abstract:
> +
> + Speaker enabling related data
> +
> +--*/
> +
> +#ifndef _PEI_LEGACY_SPEAKER_H
> +#define _PEI_LEGACY_SPEAKER_H
> +
> +
> +//
> +// Speaker Related Port Information
> +//
> +#define EFI_TIMER_COUNTER_PORT 0x40
> +#define EFI_TIMER_CONTROL_PORT 0x43
> +#define EFI_TIMER_2_PORT 0x42
> +#define EFI_SPEAKER_CONTROL_PORT 0x61
> +
> +#define EFI_SPEAKER_OFF_MASK 0xFC
> +
> +#define EFI_DEFAULT_BEEP_FREQUENCY 0x500
> +
> +//
> +// Default Intervals/Beep Duration
> +//
> +#define EFI_DEFAULT_LONG_BEEP_DURATION 0x70000
> +#define EFI_DEFAULT_SHORT_BEEP_DURATION 0x50000
> +#define EFI_DEFAULT_BEEP_TIME_INTERVAL 0x20000
> +
> +
> +EFI_STATUS
> +EFIAPI
> +ProgramToneFrequency (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINT16 Frequency
> + );
> +
> +
> +EFI_STATUS
> +EFIAPI
> +GenerateBeepTone (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINTN NumberOfBeeps,
> + IN UINTN BeepDuration,
> + IN UINTN TimeInterval
> + );
> +
> +EFI_STATUS
> +TurnOnSpeaker (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +EFI_STATUS
> +TurnOffSpeaker (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c
> new file mode 100644
> index 0000000000..7d1a20c104
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c
> @@ -0,0 +1,72 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + MchInit.c
> +
> +Abstract:
> +
> +
> +--*/
> +
> +
> +#include "PlatformEarlyInit.h"
> +
> +#define PSE_PAGE_SIZE 0x400000 // 4MB
> +
> +extern BOOLEAN ImageInMemory;
> +
> +
> +VOID
> +EfiCommonLibEnablePsePaging (
> + IN UINT32 PDBR
> + );
> +
> +VOID
> +EfiCommonLibDisablePsePaging (
> + );
> +
> +/**
> +
> + Initialize the MCH Thermal Sensor
> +
> +**/
> +VOID
> +InitMchThermalSensor()
> +{
> +}
> +
> +/**
> +
> + Programs and enables the CRID for MCH and ICH
> +
> +**/
> +VOID
> +ProgramMchCRID(
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> +}
> +
> +/**
> +
> + Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal
> inversion registers
> +
> +**/
> +VOID
> +MchInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> +
> + return;
> +}
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c
> new file mode 100644
> index 0000000000..070848ed1e
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c
> @@ -0,0 +1,338 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + MemoryCallback.c
> +
> +Abstract:
> +
> + EFI 2.0 PEIM to provide the platform support functionality on the
> Bridgeport.
> +
> +--*/
> +
> +#include "PlatformEarlyInit.h"
> +
> +
> +VOID
> +UpdateDefaultSetupValue (
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfo
> + )
> +{
> +return;
> +}
> +
> +/**
> + PEI termination callback.
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param NotifyDescriptor Not uesed.
> + @param Ppi Not uesed.
> +
> + @retval EFI_SUCCESS If the interface could be successfully
> + installed.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +EndOfPeiPpiNotifyCallback (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> + )
> +{
> + EFI_STATUS Status;
> + UINT64 LowUncableBase;
> + EFI_PLATFORM_INFO_HOB *PlatformInfo;
> + UINT32 HecBaseHigh;
> + EFI_BOOT_MODE BootMode;
> + EFI_PEI_HOB_POINTERS Hob;
> +
> + Status = (*PeiServices)->GetBootMode(
> + PeiServices,
> + &BootMode
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Set the some PCI and chipset range as UC
> + // And align to 1M at leaset
> + //
> + Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
> + ASSERT (Hob.Raw != NULL);
> + PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
> +
> + UpdateDefaultSetupValue (PlatformInfo);
> +
> + DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo-
> >MemData.MemTolm));
> + DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo-
> >PciData.PciExpressBase));
> + DEBUG (
> + (EFI_D_ERROR,
> + "PCIE BASE: %lX Size : %X\n",
> + PlatformInfo->PciData.PciExpressBase,
> + PlatformInfo->PciData.PciExpressSize)
> + );
> + DEBUG (
> + (EFI_D_ERROR,
> + "PCI32 BASE: %X Limit: %X\n",
> + PlatformInfo->PciData.PciResourceMem32Base,
> + PlatformInfo->PciData.PciResourceMem32Limit)
> + );
> + DEBUG (
> + (EFI_D_ERROR,
> + "PCI64 BASE: %lX Limit: %lX\n",
> + PlatformInfo->PciData.PciResourceMem64Base,
> + PlatformInfo->PciData.PciResourceMem64Limit)
> + );
> + DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", PlatformInfo-
> >MemData.MemMir0, PlatformInfo->MemData.MemMir1));
> +
> + LowUncableBase = PlatformInfo->MemData.MemMaxTolm;
> + LowUncableBase &= (0x0FFF00000);
> +
> + if (BootMode != BOOT_ON_S3_RESUME) {
> + //
> + // In BIOS, HECBASE will be always below 4GB
> + //
> + HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo-
> >PciData.PciExpressBase, 28);
> + ASSERT (HecBaseHigh < 16);
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Install Firmware Volume Hob's once there is main memory
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param NotifyDescriptor Notify that this module published.
> + @param Ppi PPI that was installed.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +MemoryDiscoveredPpiNotifyCallback (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> + )
> +{
> + EFI_STATUS Status;
> + EFI_BOOT_MODE BootMode;
> + EFI_CPUID_REGISTER FeatureInfo;
> + UINT8 CpuAddressWidth;
> + UINT16 Pm1Cnt;
> + EFI_PEI_HOB_POINTERS Hob;
> + EFI_PLATFORM_INFO_HOB *PlatformInfo;
> + UINT32 RootComplexBar;
> + UINT32 PmcBase;
> + UINT32 IoBase;
> + UINT32 IlbBase;
> + UINT32 SpiBase;
> + UINT32 MphyBase;
> +
> + //
> + // Get Platform Info HOB
> + //
> + Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
> + ASSERT (Hob.Raw != NULL);
> + PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
> +
> + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
> +
> + //
> + // Check if user wants to turn off in PEI phase
> + //
> + if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode !=
> BOOT_ON_FLASH_UPDATE)) {
> + CheckPowerOffNow();
> + } else {
> + Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);
> + Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;
> + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
> + }
> +
> + #ifndef MINNOW2_FSP_BUILD
> + //
> + // Set PEI cache mode here
> + //
> + SetPeiCacheMode (PeiServices);
> + #endif
> +
> + //
> + // Pulish memory tyoe info
> + //
> + PublishMemoryTypeInfo ();
> +
> + //
> + // Work done if on a S3 resume
> + //
> + if (BootMode == BOOT_ON_S3_RESUME) {
> + //
> + //Program the side band packet register to send a sideband message to
> Punit
> + //To indicate that DRAM has been initialized and PUNIT FW base address
> in memory.
> + //
> + return EFI_SUCCESS;
> + }
> +
> + RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) &
> B_PCH_LPC_RCBA_BAR;
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + RootComplexBar,
> + 0x1000
> + );
> + DEBUG ((EFI_D_INFO, "RootComplexBar : 0x%x\n", RootComplexBar));
> +
> + PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) &
> B_PCH_LPC_PMC_BASE_BAR;
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + PmcBase,
> + 0x1000
> + );
> + DEBUG ((EFI_D_INFO, "PmcBase : 0x%x\n", PmcBase));
> +
> + IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) &
> B_PCH_LPC_IO_BASE_BAR;
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + IoBase,
> + 0x4000
> + );
> + DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase));
> +
> + IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) &
> B_PCH_LPC_ILB_BASE_BAR;
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + IlbBase,
> + 0x1000
> + );
> + DEBUG ((EFI_D_INFO, "IlbBase : 0x%x\n", IlbBase));
> +
> + SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) &
> B_PCH_LPC_SPI_BASE_BAR;
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + SpiBase,
> + 0x1000
> + );
> + DEBUG ((EFI_D_INFO, "SpiBase : 0x%x\n", SpiBase));
> +
> + MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH,
> PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) &
> B_PCH_LPC_MPHY_BASE_BAR;
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + MphyBase,
> + 0x100000
> + );
> + DEBUG ((EFI_D_INFO, "MphyBase : 0x%x\n", MphyBase));
> +
> + //
> + // Local APIC
> + //
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + LOCAL_APIC_ADDRESS,
> + 0x1000
> + );
> + DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n",
> LOCAL_APIC_ADDRESS));
> +
> + //
> + // IO APIC
> + //
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + IO_APIC_ADDRESS,
> + 0x1000
> + );
> + DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS : 0x%x\n",
> IO_APIC_ADDRESS));
> +
> + //
> + // Adding the PCIE Express area to the E820 memory table as type 2
> memory.
> + //
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + PlatformInfo->PciData.PciExpressBase,
> + PlatformInfo->PciData.PciExpressSize
> + );
> + DEBUG ((EFI_D_INFO, "PciExpressBase : 0x%x\n", PlatformInfo-
> >PciData.PciExpressBase));
> +
> + //
> + // Adding the Flashpart to the E820 memory table as type 2 memory.
> + //
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_FIRMWARE_DEVICE,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + FixedPcdGet32 (PcdFlashAreaBaseAddress),
> + FixedPcdGet32 (PcdFlashAreaSize)
> + );
> + DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32
> (PcdFlashAreaBaseAddress)));
> +
> + //
> + // Create a CPU hand-off information
> + //
> + CpuAddressWidth = 32;
> + AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax,
> &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
> + if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {
> + AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax,
> &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
> + CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);
> + }
> +
> + BuildCpuHob(CpuAddressWidth, 16);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +
> +}
> +
> +
> +EFI_STATUS
> +ValidateFvHeader (
> + IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader
> + )
> +{
> + UINT16 *Ptr;
> + UINT16 HeaderLength;
> + UINT16 Checksum;
> +
> + //
> + // Verify the header revision, header signature, length
> + // Length of FvBlock cannot be 2**64-1
> + // HeaderLength cannot be an odd number
> + //
> + if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||
> + (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
> + (FwVolHeader->FvLength == ((UINT64) -1)) ||
> + ((FwVolHeader->HeaderLength & 0x01) != 0)
> + ) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // Verify the header checksum
> + //
> + HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2);
> + Ptr = (UINT16 *) FwVolHeader;
> + Checksum = 0;
> + while (HeaderLength > 0) {
> + Checksum = *Ptr++;
> + HeaderLength--;
> + }
> +
> + if (Checksum != 0) {
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c
> new file mode 100644
> index 0000000000..e6189b7713
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c
> @@ -0,0 +1,408 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + MemoryPeim.c
> +
> +Abstract:
> +
> + Tiano PEIM to provide the platform support functionality.
> + This file implements the Platform Memory Range PPI
> +
> +--*/
> +
> +#include "PlatformEarlyInit.h"
> +
> +//
> +// Need min. of 48MB PEI phase
> +//
> +#define PEI_MIN_MEMORY_SIZE (6 * 0x800000)
> +#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)
> +
> +//
> +// This is the memory needed for PEI to start up DXE.
> +//
> +// Over-estimating this size will lead to higher fragmentation
> +// of main memory. Under-estimation of this will cause catastrophic
> +// failure of PEI to load DXE. Generally, the failure may only be
> +// realized during capsule updates.
> +//
> +#define PRERESERVED_PEI_MEMORY ( \
> + EFI_SIZE_TO_PAGES (3 * 0x800000) /* PEI Core memory based stack
> */ \
> + )
> +
> +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] =
> {
> + { EfiACPIReclaimMemory, 0x40 }, // 0x40 pages = 256k for ASL
> + { EfiACPIMemoryNVS, 0x100 }, // 0x100 pages = 1 MB for S3, SMM,
> HII, etc
> + { EfiReservedMemoryType, 0x600 }, // 48k for BIOS Reserved
> + { EfiMemoryMappedIO, 0 },
> + { EfiMemoryMappedIOPortSpace, 0 },
> + { EfiPalCode, 0 },
> + { EfiRuntimeServicesCode, 0x200 },
> + { EfiRuntimeServicesData, 0x100 },
> + { EfiLoaderCode, 0x100 },
> + { EfiLoaderData, 0x100 },
> + { EfiBootServicesCode, 0x800 },
> + { EfiBootServicesData, 0x2500},
> + { EfiConventionalMemory, 0 },
> + { EfiUnusableMemory, 0 },
> + { EfiMaxMemoryType, 0 }
> +};
> +
> +STATIC
> +EFI_STATUS
> +GetMemorySize (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + OUT UINT64 *LowMemoryLength,
> + OUT UINT64 *HighMemoryLength
> + );
> +
> +
> +/**
> + Initializes the valid address mask for MTRRs.
> +
> + This function initializes the valid bits mask and valid address mask for
> MTRRs.
> +
> +**/
> +UINT64
> +InitializeAddressMtrrMask (
> + VOID
> + )
> +{
> + UINT32 RegEax;
> + UINT8 PhysicalAddressBits;
> + UINT64 ValidMtrrBitsMask;
> +
> + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
> +
> + if (RegEax >= 0x80000008) {
> + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
> +
> + PhysicalAddressBits = (UINT8) RegEax;
> + } else {
> + PhysicalAddressBits = 36;
> + }
> +
> + ValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
> + return (ValidMtrrBitsMask & 0xfffffffffffff000ULL);
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +SetPeiCacheMode (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> + PEI_CACHE_PPI *CachePpi;
> +
> + EFI_BOOT_MODE BootMode;
> + UINT64 MemoryLength;
> + UINT64 MemOverflow;
> + UINT64 MemoryLengthUc;
> + UINT64 MaxMemoryLength;
> + UINT64 LowMemoryLength;
> + UINT64 HighMemoryLength;
> + UINT8 Index;
> + MTRR_SETTINGS MtrrSetting;
> + UINT64 ValidMtrrAddressMask;
> +
> + //
> + // Load Cache PPI
> + //
> + Status = (**PeiServices).LocatePpi (
> + PeiServices,
> + &gPeiCachePpiGuid, // GUID
> + 0, // Instance
> + NULL, // EFI_PEI_PPI_DESCRIPTOR
> + (void **)&CachePpi // PPI
> + );
> + if (!EFI_ERROR(Status)) {
> + //
> + // Clear the CAR Settings (Default Cache Type => UC)
> + //
> + DEBUG ((EFI_D_INFO, "Reset cache attribute and disable CAR. \n"));
> + CachePpi->ResetCache(
> + (EFI_PEI_SERVICES**)PeiServices,
> + CachePpi
> + );
> + }
> +
> +
> + //
> + // Variable initialization
> + //
> + LowMemoryLength = 0;
> + HighMemoryLength = 0;
> + MemoryLengthUc = 0;
> +
> + Status = (*PeiServices)->GetBootMode (
> + PeiServices,
> + &BootMode
> + );
> +
> + ValidMtrrAddressMask = InitializeAddressMtrrMask ();
> +
> + //
> + // Determine memory usage
> + //
> + GetMemorySize (
> + PeiServices,
> + &LowMemoryLength,
> + &HighMemoryLength
> + );
> +
> + LowMemoryLength = (EFI_PHYSICAL_ADDRESS)MmPci32( 0, 0, 2, 0, 0x70);
> + LowMemoryLength &= 0xFFF00000ULL;
> +
> + MaxMemoryLength = LowMemoryLength;
> +
> + //
> + // Round up to nearest 256MB with high memory and 64MB w/o high
> memory
> + //
> + if (HighMemoryLength != 0 ) {
> + MemOverflow = (LowMemoryLength & 0x0fffffff);
> + if (MemOverflow != 0) {
> + MaxMemoryLength = LowMemoryLength + (0x10000000 -
> MemOverflow);
> + }
> + } else {
> + MemOverflow = (LowMemoryLength & 0x03ffffff);
> + if (MemOverflow != 0) {
> + MaxMemoryLength = LowMemoryLength + (0x4000000 - MemOverflow);
> + }
> + }
> +
> + ZeroMem (&MtrrSetting, sizeof(MTRR_SETTINGS));
> + for (Index = 0; Index < 2; Index++) {
> + MtrrSetting.Fixed.Mtrr[Index]=0x0606060606060606;
> + }
> + for (Index = 2; Index < 11; Index++) {
> + MtrrSetting.Fixed.Mtrr[Index]=0x0505050505050505;
> + }
> +
> + //
> + // Cache the flash area to improve the boot performance in PEI phase
> + //
> + Index = 0;
> + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)
> &MtrrSetting.Variables.Mtrr[0].Base)->Uint64 = FixedPcdGet32
> (PcdFlashAreaBaseAddress);
> + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)
> &MtrrSetting.Variables.Mtrr[0].Base)->Bits.Type = CacheWriteProtected;
> + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *)
> &MtrrSetting.Variables.Mtrr[0].Mask)->Uint64 = (~((UINT64)(FixedPcdGet32
> (PcdFlashAreaSize) - 1))) & ValidMtrrAddressMask;
> + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *)
> &MtrrSetting.Variables.Mtrr[0].Mask)->Bits.V = 1;
> +
> + Index ++;
> +
> + MemOverflow =0;
> + while (MaxMemoryLength > MemOverflow){
> + MemoryLength = MaxMemoryLength - MemOverflow;
> + MemoryLength = GetPowerOfTwo64 (MemoryLength);
> +
> + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Base)->Uint64 = MemOverflow &
> ValidMtrrAddressMask;
> + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Base)->Bits.Type = CacheWriteBack;
> + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Mask)->Uint64 = (~(MemoryLength - 1))
> & ValidMtrrAddressMask;
> + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Mask)->Bits.V = 1;
> +
> + MemOverflow += MemoryLength;
> + Index++;
> + }
> +
> + MemoryLength = LowMemoryLength;
> +
> + while (MaxMemoryLength != MemoryLength) {
> + MemoryLengthUc = GetPowerOfTwo64 (MaxMemoryLength -
> MemoryLength);
> +
> + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Base)->Uint64 = (MaxMemoryLength -
> MemoryLengthUc) & ValidMtrrAddressMask;
> + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Base)->Bits.Type = CacheUncacheable;
> + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Mask)->Uint64 = (~(MemoryLengthUc -
> 1)) & ValidMtrrAddressMask;
> + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Mask)->Bits.V = 1;
> +
> + MaxMemoryLength -= MemoryLengthUc;
> + Index++;
> + }
> +
> + MemOverflow =0x100000000;
> + while (HighMemoryLength > 0) {
> +
> + MemoryLength = HighMemoryLength;
> + MemoryLength = GetPowerOfTwo64 (MemoryLength);
> + if (MemoryLength > MemOverflow){
> + MemoryLength = MemOverflow;
> + }
> +
> + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Base)->Uint64 = MemOverflow &
> ValidMtrrAddressMask;
> + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Base)->Bits.Type = CacheWriteBack;
> + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Mask)->Uint64 = (~(MemoryLength - 1))
> & ValidMtrrAddressMask;
> + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *)
> &MtrrSetting.Variables.Mtrr[Index].Mask)->Bits.V = 1;
> +
> + MemOverflow += MemoryLength;
> + HighMemoryLength -= MemoryLength;
> + Index++;
> + }
> +
> +
> + for (Index = 0; Index < MTRR_NUMBER_OF_VARIABLE_MTRR; Index++) {
> + if (MtrrSetting.Variables.Mtrr[Index].Base == 0){
> + break;
> + }
> + DEBUG ((EFI_D_INFO, "Base=%lx,
> Mask=%lx\n",MtrrSetting.Variables.Mtrr[Index].Base ,MtrrSetting.Variables.
> Mtrr[Index].Mask));
> + }
> +
> + //
> + // set FE/E bits for IA32_MTRR_DEF_TYPE
> + //
> + MtrrSetting.MtrrDefType |= 3 <<10;
> +
> + MtrrSetAllMtrrs(&MtrrSetting);
> + //
> + // Dump MTRR Setting
> + //
> + MtrrDebugPrintAllMtrrs ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +SetDxeCacheMode (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + //
> + // This is not needed for now.
> + //
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +GetMemorySize (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + OUT UINT64 *LowMemoryLength,
> + OUT UINT64 *HighMemoryLength
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_HOB_POINTERS Hob;
> +
> + *HighMemoryLength = 0;
> + *LowMemoryLength = 0x100000;
> +
> + //
> + // Get the HOB list for processing
> + //
> + Status = (*PeiServices)->GetHobList (PeiServices, (void **)&Hob.Raw);
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + //
> + // Collect memory ranges
> + //
> + while (!END_OF_HOB_LIST (Hob)) {
> + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
> + if (Hob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_SYSTEM_MEMORY) {
> + //
> + // Need memory above 1MB to be collected here
> + //
> + if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 &&
> + Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS)
> 0x100000000) {
> + *LowMemoryLength += (UINT64) (Hob.ResourceDescriptor-
> >ResourceLength);
> + } else if (Hob.ResourceDescriptor->PhysicalStart >=
> (EFI_PHYSICAL_ADDRESS) 0x100000000) {
> + *HighMemoryLength += (UINT64) (Hob.ResourceDescriptor-
> >ResourceLength);
> + }
> + }
> + }
> + Hob.Raw = GET_NEXT_HOB (Hob);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Publish Memory Type Information.
> +
> + @param NULL
> +
> + @retval EFI_SUCCESS Success.
> + @retval Others Errors have occurred.
> +**/
> +
> +EFI_STATUS
> +EFIAPI
> +PublishMemoryTypeInfo (
> + void
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
> + UINTN DataSize;
> + EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType
> + 1];
> +
> + Status = PeiServicesLocatePpi (
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (void **)&Variable
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG((EFI_D_ERROR, "WARNING: Locating Pei variable failed 0x%x \n",
> Status));
> + DEBUG((EFI_D_ERROR, "Build Hob from default\n"));
> + //
> + // Build the default GUID'd HOB for DXE
> + //
> + BuildGuidDataHob (
> + &gEfiMemoryTypeInformationGuid,
> + mDefaultMemoryTypeInformation,
> + sizeof (mDefaultMemoryTypeInformation)
> + );
> +
> + return Status;
> + }
> +
> +
> + DataSize = sizeof (MemoryData);
> +
> + //
> + // This variable is saved in BDS stage. Now read it back
> + //
> + Status = Variable->GetVariable (
> + Variable,
> + EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
> + &gEfiMemoryTypeInformationGuid,
> + NULL,
> + &DataSize,
> + &MemoryData
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + //build default
> + //
> + DEBUG((EFI_D_ERROR, "Build Hob from default\n"));
> + BuildGuidDataHob (
> + &gEfiMemoryTypeInformationGuid,
> + mDefaultMemoryTypeInformation,
> + sizeof (mDefaultMemoryTypeInformation)
> + );
> +
> + } else {
> + //
> + // Build the GUID'd HOB for DXE from variable
> + //
> + DEBUG((EFI_D_ERROR, "Build Hob from variable \n"));
> + BuildGuidDataHob (
> + &gEfiMemoryTypeInformationGuid,
> + MemoryData,
> + DataSize
> + );
> + }
> +
> + return Status;
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
> new file mode 100644
> index 0000000000..38b17156f4
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
> @@ -0,0 +1,808 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + PchInitPeim.c
> +
> +Abstract:
> +
> + Do Early PCH platform initialization.
> +
> +
> +--*/
> +
> +#include "PlatformEarlyInit.h"
> +#include "Ppi/PchPlatformPolicy.h"
> +#include "PchRegs.h"
> +#include <Ppi/PchUsbPolicy.h>
> +#include "Ppi/PchInit.h"
> +#include <Library/PcdLib.h>
> +
> +EFI_GUID gPchPlatformPolicyPpiGuid =
> PCH_PLATFORM_POLICY_PPI_GUID;
> +
> +#define MC_PMSTS_OFFSET 0xC
> +
> +#define DEFAULT_BUS_INFO 0x2020
> +
> +
> +#define PCI_LPC_BASE (0x8000F800)
> +#define PCI_LPC_REG(x) (PCI_LPC_BASE + (x))
> +#define PCIEX_BASE_ADDRESS 0xE0000000
> +#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32)
> (31 << 15)
> +
> +VOID
> +PchPolicySetupInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +VOID
> +PchInitInterrupt (
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +EFI_STATUS
> +InstallPeiPchUsbPolicy (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +#ifndef __GNUC__
> +#pragma warning (push)
> +#pragma warning (disable : 4245)
> +#pragma warning (pop)
> +#endif
> +
> +UINT8
> +ReadCmosBank1Byte (
> + IN UINT8 Address
> + )
> +{
> + UINT8 Data;
> +
> + IoWrite8(R_PCH_RTC_EXT_INDEX, Address);
> + Data = IoRead8 (R_PCH_RTC_EXT_TARGET);
> + return Data;
> +}
> +
> +VOID
> +WriteCmosBank1Byte (
> + IN UINT8 Address,
> + IN UINT8 Data
> + )
> +{
> + IoWrite8(R_PCH_RTC_EXT_INDEX, Address);
> + IoWrite8(R_PCH_RTC_EXT_TARGET, Data);
> +}
> +
> +/**
> + Turn off system if needed.
> +
> + @param PeiServices Pointer to PEI Services
> + @param CpuIo Pointer to CPU I/O Protocol
> +
> + @retval None.
> +
> +**/
> +VOID
> +CheckPowerOffNow (
> + VOID
> + )
> +{
> + UINT16 Pm1Sts;
> +
> + //
> + // Read and check the ACPI registers
> + //
> + Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
> + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) ==
> B_PCH_ACPI_PM1_STS_PWRBTN) {
> + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS,
> B_PCH_ACPI_PM1_STS_PWRBTN);
> + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT,
> V_PCH_ACPI_PM1_CNT_S5);
> + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT,
> V_PCH_ACPI_PM1_CNT_S5 + B_PCH_ACPI_PM1_CNT_SLP_EN);
> +
> + //
> + // Should not return
> + //
> + CpuDeadLoop();
> + }
> +}
> +
> +VOID
> +ClearPowerState (
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> + UINT8 Data8;
> + UINT16 Data16;
> + UINT32 Data32;
> +
> + //
> + // Check for PowerState option for AC power loss and program the chipset
> + //
> +
> + //
> + // Clear PWROK (Set to Clear)
> + //
> + MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1,
> B_PCH_PMC_GEN_PMCON_PWROK_FLR);
> +
> + //
> + // Clear Power Failure Bit (Set to Clear)
> + //
> + // TODO: Check if it is OK to clear here
> + //
> +
> + MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1,
> B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR);
> +
> + //
> + // Clear the GPE and PM enable
> + //
> + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_EN, (UINT16) 0x00);
> + IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_EN, (UINT32)
> 0x00);
> +
> + //
> + // Halt the TCO timer
> + //
> + Data16 = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT);
> + Data16 |= B_PCH_TCO_CNT_TMR_HLT;
> + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT, Data16);
> +
> + //
> + // if NMI_NOW_STS is set
> + // NMI NOW bit is "Write '1' to clear"
> + //
> + Data8 = MmioRead8(ILB_BASE_ADDRESS + R_PCH_ILB_GNMI);
> + if ((Data8 & B_PCH_ILB_GNMI_NMINS) == B_PCH_ILB_GNMI_NMINS) {
> + MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_GNMI,
> B_PCH_ILB_GNMI_NMIN);
> + }
> +
> + //
> + // Before we clear the TO status bit here we need to save the results in a
> CMOS bit for later use.
> + //
> + Data32 = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_TCO_STS);
> + if ((Data32 & B_PCH_TCO_STS_SECOND_TO) ==
> B_PCH_TCO_STS_SECOND_TO)
> + {
> +#if (defined(HW_WATCHDOG_TIMER_SUPPORT) &&
> (HW_WATCHDOG_TIMER_SUPPORT != 0))
> + WriteCmosBank1Byte (
> + EFI_CMOS_PERFORMANCE_FLAGS,
> + ReadCmosBank1Byte (EFI_CMOS_PERFORMANCE_FLAGS) |
> B_CMOS_TCO_WDT_RESET
> + );
> +#endif
> + }
> +}
> +
> +/*++
> +
> + Clear any SMI status or wake status left over from boot.
> +
> +**/
> +VOID
> +ClearSmiAndWake (
> + VOID
> + )
> +{
> + UINT16 Pm1Sts;
> + UINT32 Gpe0Sts;
> + UINT32 SmiSts;
> +
> + //
> + // Read the ACPI registers
> + //
> + Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
> + Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);
> + SmiSts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS);
> +
> + //
> + // Register Wake up reason for S4. This information is used to notify
> + // WinXp of wake up reason because S4 wake up path doesn't keep SCI.
> + // This is important for Viiv(Quick resume) platform.
> + //
> +
> + //
> + // First Clear CMOS S4 Wake up flag.
> + //
> + WriteCmosBank1Byte(CMOS_S4_WAKEUP_FLAG_ADDRESS, 0);
> +
> + //
> + // Check wake up reason and set CMOS accordingly. Currently checks
> + // Power button, USB, PS/2.
> + // Note : PS/2 wake up is using GPI13 (IO_PME). This must be changed
> depending
> + // on board design.
> + //
> + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) || (Gpe0Sts &
> (B_PCH_ACPI_GPE0a_STS_CORE_GPIO |
> B_PCH_ACPI_GPE0a_STS_SUS_GPIO))) {
> + WriteCmosBank1Byte(CMOS_S4_WAKEUP_FLAG_ADDRESS, 1);
> + }
> +
> + //
> + // Clear any SMI or wake state from the boot
> + //
> + Pm1Sts = (B_PCH_ACPI_PM1_STS_PRBTNOR |
> B_PCH_ACPI_PM1_STS_PWRBTN);
> +
> + Gpe0Sts |=
> + (
> + B_PCH_ACPI_GPE0a_STS_CORE_GPIO |
> + B_PCH_ACPI_GPE0a_STS_SUS_GPIO |
> + B_PCH_ACPI_GPE0a_STS_PME_B0 |
> + B_PCH_ACPI_GPE0a_STS_BATLOW |
> + B_PCH_ACPI_GPE0a_STS_PCI_EXP |
> + B_PCH_ACPI_GPE0a_STS_GUNIT_SCI |
> + B_PCH_ACPI_GPE0a_STS_PUNIT_SCI |
> + B_PCH_ACPI_GPE0a_STS_SWGPE |
> + B_PCH_ACPI_GPE0a_STS_HOT_PLUG
> + );
> +
> + SmiSts |=
> + (
> + B_PCH_SMI_STS_SMBUS |
> + B_PCH_SMI_STS_PERIODIC |
> + B_PCH_SMI_STS_TCO |
> + B_PCH_SMI_STS_SWSMI_TMR |
> + B_PCH_SMI_STS_APM |
> + B_PCH_SMI_STS_ON_SLP_EN |
> + B_PCH_SMI_STS_BIOS
> + );
> +
> + //
> + // Write them back
> + //
> + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, Pm1Sts);
> + IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS, Gpe0Sts);
> + IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS, SmiSts);
> +}
> +
> +/**
> + Issue PCI-E Secondary Bus Reset
> +
> + @param Bus Bus number of the bridge
> + @param Dev Devices number of the bridge
> + @param Fun Function number of the bridge
> +
> + @retval EFI_SUCCESS
> +
> +**/
> +EFI_STATUS
> +PcieSecondaryBusReset (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINT8 Bus,
> + IN UINT8 Dev,
> + IN UINT8 Fun
> + )
> +{
> + EFI_PEI_STALL_PPI *PeiStall;
> + EFI_STATUS Status;
> +
> + Status = (**PeiServices).LocatePpi (
> + PeiServices,
> + &gEfiPeiStallPpiGuid,
> + 0,
> + NULL,
> + (void **)&PeiStall
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Issue secondary bus reset
> + //
> + MmPci16Or(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET,
> EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS);
> +
> + //
> + // Wait 1ms
> + //
> + PeiStall->Stall (PeiServices, PeiStall, 1000);
> +
> +
> + //
> + // Clear the reset bit
> + // Note: The PCIe spec suggests 100ms delay between clearing this bit and
> accessing
> + // the device's config space. Since we will not access the config space until
> we enter DXE
> + // we don't put delay expressly here.
> + //
> + MmPci16And(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET,
> ~(EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS));
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Provide hard reset PPI service.
> + To generate full hard reset, write 0x0E to ICH RESET_GENERATOR_PORT
> (0xCF9).
> +
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval Not return System reset occured.
> + @retval EFI_DEVICE_ERROR Device error, could not reset the system.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +IchReset (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + IoWrite8 (
> + R_PCH_RST_CNT,
> + V_PCH_RST_CNT_HARDSTARTSTATE
> + );
> +
> + IoWrite8 (
> + R_PCH_RST_CNT,
> + V_PCH_RST_CNT_HARDRESET
> + );
> +
> + //
> + // System reset occured, should never reach at this line.
> + //
> + ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
> + CpuDeadLoop();
> +
> + return EFI_DEVICE_ERROR;
> +}
> +
> +VOID
> +PchPlatformLpcInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> + EFI_BOOT_MODE BootMode;
> + UINT8 Data8;
> + UINT16 Data16;
> +
> + (*PeiServices)->GetBootMode(PeiServices, &BootMode);
> +
> + if ((BootMode != BOOT_ON_S3_RESUME)) {
> +
> + //
> + // Clear all pending SMI. On S3 clear power button enable so it wll not
> generate an SMI
> + //
> + ClearSmiAndWake ();
> + }
> +
> + ClearPowerState (SystemConfiguration);
> +
> + //
> + // Need to set and clear SET bit (RTC_REGB Bit 7) as requested by the ICH
> EDS
> + // early in POST after each power up directly after coin-cell battery
> insertion.
> + // This is to avoid the UIP bit (RTC_REGA Bit 7) from stuck at "1".
> + // The UIP bit status may be polled by software (i.e ME FW) during POST.
> + //
> + if (MmioRead8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1) &
> B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) {
> + //
> + // Set and clear SET bit in RTC_REGB
> + //
> + IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERB);
> + Data8 = IoRead8(R_PCH_RTC_TARGET);
> + Data8 |= B_PCH_RTC_REGISTERB_SET;
> + IoWrite8(R_PCH_RTC_TARGET, Data8);
> +
> + IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERB);
> + Data8 &= (~B_PCH_RTC_REGISTERB_SET);
> + IoWrite8(R_PCH_RTC_TARGET, Data8);
> +
> + //
> + // Clear the UIP bit in RTC_REGA
> + //
> + IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERA);
> + IoWrite8(R_PCH_RTC_TARGET, 0x00);
> + }
> +
> + //
> + // Disable SERR NMI and IOCHK# NMI in port 61
> + //
> + Data8 = IoRead8 (R_PCH_NMI_SC);
> + IoWrite8(R_PCH_NMI_SC, (UINT8) (Data8 |
> B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN));
> +
> + //
> + // Enable Bus Master, I/O, Mem, and SERR on LPC bridge
> + //
> + Data16 = PchLpcPciCfg16 (R_PCH_LPC_COMMAND);
> + MmioWrite16 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_COMMAND
> + ),
> + (Data16 |
> + B_PCH_LPC_COMMAND_IOSE |
> + B_PCH_LPC_COMMAND_MSE |
> + B_PCH_LPC_COMMAND_BME |
> + B_PCH_LPC_COMMAND_SERR_EN)
> + );
> +
> + //
> + // Set Stretch S4 to 1-2s per marketing request.
> + // Note: This register is powered by RTC well.
> + //
> + MmioAndThenOr8 (
> + PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1 ,
> + (UINT8) (~B_PCH_PMC_GEN_PMCON_SLP_S4_MAW),
> + (UINT8) (B_PCH_PMC_GEN_PMCON_SLP_S4_ASE |
> V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_4S)
> + );
> +
> +}
> +
> +#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3
> Enable
> +
> +VOID
> +UARTInit (
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> + if (0) { // for fix cr4 issue
> + //
> + // Program and enable PMC Base.
> + //
> + IoWrite32 (0xCF8, PCI_LPC_REG(R_PCH_LPC_PMC_BASE));
> + IoWrite32 (0xCFC, (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));
> +
> + if( (SystemConfiguration->PcuUart1 == 1) &&
> + (SystemConfiguration->LpssHsuart0Enabled == 0)){
> + //
> + // Enable COM1 for debug message output.
> + //
> + MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1,
> BIT24);
> +
> + //
> + //Enable internal UART3 port(COM1)
> + //
> + MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8)
> V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);
> + MmioOr32 (IO_BASE_ADDRESS + 0x0520, 0x01); // UART3_RXD-L
> + MmioOr32 (IO_BASE_ADDRESS + 0x0530, 0x01); // UART3_TXD-0
> + MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8)
> B_PCH_LPC_UART_CTRL_COM1_EN);
> + } else {
> + //
> + //Disable UART3(COM1)
> + //
> + MmioAnd8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8)
> ~V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);
> + MmioAnd32 (IO_BASE_ADDRESS + 0x0520, ~(UINT32)0x07);
> + MmioAnd32 (IO_BASE_ADDRESS + 0x0530, ~(UINT32)0x07);
> + MmioAnd8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8)
> ~B_PCH_LPC_UART_CTRL_COM1_EN);
> +
> +
> + if (SystemConfiguration->LpssHsuart0Enabled == 1){
> + //
> + //Valleyview BIOS Specification Vol2,17.2
> + //LPSS_UART1 �C set each pad PAD_CONF0.Func_Pin_Mux to function
> 1:
> + //
> + MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07);
> + MmioOr8 (IO_BASE_ADDRESS + 0x0090, 0x01);
> + MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07);
> + MmioOr8 (IO_BASE_ADDRESS + 0x00D0, 0x01);
> +
> + }
> + }
> +
> +
> + DEBUG ((EFI_D_ERROR, "EnableInternalUart\n"));
> + } else {
> + //
> + // If SIO UART interface selected
> + //Disable internal UART port(COM1)
> + //
> + if (0) {; // For fix CR4 issue
> + MmioAnd8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8)
> ~V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);
> + MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07);
> + MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07);
> + MmioAnd8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8)
> ~B_PCH_LPC_UART_CTRL_COM1_EN);
> +
> + }
> + }
> +}
> +
> +VOID
> +IchRcrbInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> + EFI_BOOT_MODE BootMode;
> +
> + (*PeiServices)->GetBootMode(PeiServices, &BootMode);
> +
> + //
> + // If not recovery or flash update boot path. set the BIOS interface lock
> down bit.
> + // It locks the top swap bit and BIOS boot strap bits from being changed.
> + //
> + if ((BootMode != BOOT_IN_RECOVERY_MODE) && (BootMode !=
> BOOT_ON_FLASH_UPDATE)) {
> + MmioOr8 (RCBA_BASE_ADDRESS + R_PCH_RCRB_GCS,
> B_PCH_RCRB_GCS_BILD);
> + }
> +
> + //
> + // Disable the Watchdog timer expiration from causing a system reset
> + //
> + MmioOr8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG,
> B_PCH_PMC_PM_CFG_NO_REBOOT);
> +
> + //
> + // Initial RCBA according to the PeiRCBA table
> + //
> + if ((BootMode == BOOT_ON_S3_RESUME)) {
> + //
> + // We are resuming from S3
> + // Enable HPET if enabled in Setup
> + // ICH Config register Offset 0x3404 bit 7 (Enable) = 1,
> + // Bit 1:0 (Mem I/O address) = 0 (0xFED00000)
> + //
> + MmioOr8 (R_PCH_PCH_HPET + R_PCH_PCH_HPET_GCFG,
> B_PCH_PCH_HPET_GCFG_EN);
> +
> + }
> +
> +}
> +
> +
> +EFI_STATUS
> +PlatformPchInit (
> + IN SYSTEM_CONFIGURATION *SystemConfiguration,
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINT16 PlatformType
> + )
> +{
> + EFI_STATUS Status;
> + EFI_BOOT_MODE BootMode;
> +
> + Status = PeiServicesGetBootMode (&BootMode);
> + ASSERT_EFI_ERROR (Status);
> +
> + IchRcrbInit (PeiServices, SystemConfiguration);
> +
> + if (BootMode == BOOT_IN_RECOVERY_MODE) {
> + InstallPeiPchUsbPolicy(PeiServices);
> + }
> +
> + //
> + // PCH Policy Initialization based on Setup variable.
> + //
> + PchPolicySetupInit (PeiServices, SystemConfiguration);
> +
> + UARTInit(SystemConfiguration);
> +
> + PchPlatformLpcInit (PeiServices, SystemConfiguration);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +
> + Returns the state of A16 inversion
> +
> + @retval TRUE A16 is inverted
> + @retval FALSE A16 is not inverted
> +
> +**/
> +BOOLEAN
> +IsA16Inverted (
> + )
> +{
> + UINT8 Data;
> + Data = MmioRead8 (RCBA_BASE_ADDRESS + R_PCH_RCRB_GCS);
> + return (Data & B_PCH_RCRB_GCS_TS) ? TRUE : FALSE;
> +}
> +
> +VOID
> +PchPolicySetupInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_PPI_DESCRIPTOR *PchPlatformPolicyPpiDesc;
> + PCH_PLATFORM_POLICY_PPI *PchPlatformPolicyPpi;
> + PCH_HPET_CONFIG *HpetConfig;
> + PCH_PCIE_CONFIG *PcieConfig;
> + UINT8 Index;
> + PCH_IOAPIC_CONFIG *IoApicConfig;
> + PCH_LPSS_CONFIG *LpssConfig;
> + UINT32 SpiHsfsReg;
> + UINT32 SpiFdodReg;
> +
> +//
> +// Disable codec ALC-262
> +//
> + UINT32 IoBase;
> +
> + //
> + // Install Pch Platform Policy PPI. As we depend on Pch Init PPI so we are
> executed after
> + // PchInit PEIM. Thus we can insure PCH Initialization is performed when
> we install the Pch Platform Policy PPI,
> + // as PchInit PEIM registered a notification function on our policy PPI.
> + //
> + // --cr-- For better code structure / modularity, we should use a
> notification function on Pch Init PPI to perform
> + // actions that depend on PchInit PEIM's initialization.
> + //
> + //Todo: confirm if we need update to
> PCH_PLATFORM_POLICY_PPI_REVISION_5
> + //
> + DEBUG ((EFI_D_ERROR, "PchPolicySetupInit() - Start\n"));
> +
> + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof
> (EFI_PEI_PPI_DESCRIPTOR), (void **)&PchPlatformPolicyPpiDesc);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof
> (PCH_PLATFORM_POLICY_PPI), (void **)&PchPlatformPolicyPpi);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof
> (PCH_HPET_CONFIG), (void **)&HpetConfig);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof
> (PCH_PCIE_CONFIG), (void **)&PcieConfig);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof
> (PCH_IOAPIC_CONFIG), (void **)&IoApicConfig);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof
> (PCH_LPSS_CONFIG), (void **)&LpssConfig);
> + ASSERT_EFI_ERROR (Status);
> +
> + PchPlatformPolicyPpi->Revision =
> PCH_PLATFORM_POLICY_PPI_REVISION_1;
> + PchPlatformPolicyPpi->BusNumber =
> DEFAULT_PCI_BUS_NUMBER_PCH;
> + PchPlatformPolicyPpi->SpiBase = SPI_BASE_ADDRESS;
> + PchPlatformPolicyPpi->PmcBase = PMC_BASE_ADDRESS;
> + PchPlatformPolicyPpi->IoBase = IO_BASE_ADDRESS;
> + PchPlatformPolicyPpi->IlbBase = ILB_BASE_ADDRESS;
> + PchPlatformPolicyPpi->PUnitBase = PUNIT_BASE_ADDRESS;
> + PchPlatformPolicyPpi->MphyBase = MPHY_BASE_ADDRESS;
> + PchPlatformPolicyPpi->Rcba = RCBA_BASE_ADDRESS;
> + PchPlatformPolicyPpi->AcpiBase = ACPI_BASE_ADDRESS;
> + PchPlatformPolicyPpi->GpioBase = GPIO_BASE_ADDRESS;
> + PchPlatformPolicyPpi->SataMode = SystemConfiguration-
> >SataType;
> + PchPlatformPolicyPpi->EnableRmh = SystemConfiguration-
> >PchUsbRmh;
> +
> + PchPlatformPolicyPpi->EhciPllCfgEnable = SystemConfiguration-
> >EhciPllCfgEnable;
> +
> +
> + PchPlatformPolicyPpi->HpetConfig = HpetConfig;
> + PchPlatformPolicyPpi->PcieConfig = PcieConfig;
> + PchPlatformPolicyPpi->IoApicConfig = IoApicConfig;
> +
> + PchPlatformPolicyPpi->HpetConfig->Enable = SystemConfiguration-
> >Hpet;
> + PchPlatformPolicyPpi->HpetConfig->Base = HPET_BASE_ADDRESS;
> + PchPlatformPolicyPpi->IoApicConfig->IoApicId = 0x01;
> +
> + //
> + // Set LPSS configuration according to setup value.
> + //
> + PchPlatformPolicyPpi->LpssConfig->LpssPciModeEnabled =
> SystemConfiguration->LpssPciModeEnabled;
> +
> + PchPlatformPolicyPpi->LpssConfig->Dma1Enabled =
> SystemConfiguration->LpssDma1Enabled;
> + PchPlatformPolicyPpi->LpssConfig->I2C0Enabled = SystemConfiguration-
> >LpssI2C0Enabled;
> + PchPlatformPolicyPpi->LpssConfig->I2C1Enabled = SystemConfiguration-
> >LpssI2C1Enabled;
> + PchPlatformPolicyPpi->LpssConfig->I2C2Enabled = SystemConfiguration-
> >LpssI2C2Enabled;
> + PchPlatformPolicyPpi->LpssConfig->I2C3Enabled = SystemConfiguration-
> >LpssI2C3Enabled;
> + PchPlatformPolicyPpi->LpssConfig->I2C4Enabled = SystemConfiguration-
> >LpssI2C4Enabled;
> + PchPlatformPolicyPpi->LpssConfig->I2C5Enabled = SystemConfiguration-
> >LpssI2C5Enabled;
> + PchPlatformPolicyPpi->LpssConfig->I2C6Enabled = SystemConfiguration-
> >LpssI2C6Enabled;
> +
> + PchPlatformPolicyPpi->LpssConfig->Dma0Enabled =
> SystemConfiguration->LpssDma0Enabled;;
> + PchPlatformPolicyPpi->LpssConfig->Pwm0Enabled =
> SystemConfiguration->LpssPwm0Enabled;
> + PchPlatformPolicyPpi->LpssConfig->Pwm1Enabled =
> SystemConfiguration->LpssPwm1Enabled;
> + PchPlatformPolicyPpi->LpssConfig->Hsuart0Enabled =
> SystemConfiguration->LpssHsuart0Enabled;
> + PchPlatformPolicyPpi->LpssConfig->Hsuart1Enabled =
> SystemConfiguration->LpssHsuart1Enabled;
> + PchPlatformPolicyPpi->LpssConfig->SpiEnabled = SystemConfiguration-
> >LpssSpiEnabled;
> +
> +
> + for (Index = 0; Index < PCH_PCIE_MAX_ROOT_PORTS; Index++) {
> + PchPlatformPolicyPpi->PcieConfig->PcieSpeed[Index] =
> SystemConfiguration->PcieRootPortSpeed[Index];
> + }
> +
> + SpiHsfsReg = MmioRead32 (SPI_BASE_ADDRESS + R_PCH_SPI_HSFS);
> + if ((SpiHsfsReg & B_PCH_SPI_HSFS_FDV) == B_PCH_SPI_HSFS_FDV) {
> + MmioWrite32 (SPI_BASE_ADDRESS + R_PCH_SPI_FDOC,
> V_PCH_SPI_FDOC_FDSS_FSDM);
> + SpiFdodReg = MmioRead32 (SPI_BASE_ADDRESS + R_PCH_SPI_FDOD);
> + if (SpiFdodReg == V_PCH_SPI_FDBAR_FLVALSIG) {
> + }
> + //
> + // Disable codec ALC-262
> + //
> + if (SystemConfiguration->DisableCodec262 == 1) {
> + IoBase = MmioRead32 (MmPciAddress (0,
> + PchPlatformPolicyPpi->BusNumber,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + 0
> + ) + R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR;
> + MmioAnd32 ((UINTN) (IoBase + 0x270), (UINT32) (~0x07));
> + }
> + }
> +
> + PchPlatformPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
> + PchPlatformPolicyPpiDesc->Guid = &gPchPlatformPolicyPpiGuid;
> + PchPlatformPolicyPpiDesc->Ppi = PchPlatformPolicyPpi;
> +
> + //
> + // Install PCH Platform Policy PPI
> + //
> + Status = (**PeiServices).InstallPpi (
> + PeiServices,
> + PchPlatformPolicyPpiDesc
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + DEBUG ((EFI_D_ERROR, "PchPolicySetupInit() - End\n"));
> +}
> +
> +EFI_STATUS
> +InstallPeiPchUsbPolicy (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> +
> + EFI_PEI_PPI_DESCRIPTOR *PeiPchUsbPolicyPpiDesc;
> + PCH_USB_POLICY_PPI *PeiPchUsbPolicyPpi;
> + PCH_USB_CONFIG *UsbConfig;
> +
> + DEBUG ((EFI_D_INFO, "InstallPeiPchUsbPolicy...\n"));
> +
> + //
> + // Allocate descriptor and PPI structures. Since these are dynamically
> updated
> + // we cannot do a global variable PPI.
> + //
> + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof
> (EFI_PEI_PPI_DESCRIPTOR), (void **)&PeiPchUsbPolicyPpiDesc);
> +
> +
> + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof
> (PCH_USB_POLICY_PPI), (void **)&PeiPchUsbPolicyPpi);
> +
> +
> +
> + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof
> (PCH_USB_CONFIG), (void **)&UsbConfig);
> +
> +
> + //
> + // Initiate PCH USB policy.
> + //
> + PeiPchUsbPolicyPpi->Revision = PCH_USB_POLICY_PPI_REVISION_1;
> + UsbConfig->Usb20Settings[0].Enable = PCH_DEVICE_ENABLE;
> + UsbConfig->UsbPerPortCtl = PCH_DEVICE_DISABLE;
> + UsbConfig->Ehci1Usbr = PCH_DEVICE_DISABLE;
> +
> + UsbConfig->Usb20OverCurrentPins[0] = PchUsbOverCurrentPin0;
> +
> + UsbConfig->Usb20OverCurrentPins[1] = PchUsbOverCurrentPin0;
> +
> + UsbConfig->Usb20OverCurrentPins[2] = PchUsbOverCurrentPin1;
> +
> + UsbConfig->Usb20OverCurrentPins[3] = PchUsbOverCurrentPin1;
> +
> +
> + //
> + // Enable USB Topology control and program the topology setting for every
> USB port
> + // See Platform Design Guide for description of topologies
> + //
> + //
> + // Port 0: ~10.9", Port 1: ~10.1", Port 2: ~11.2", Port 3: ~11.5", Port 4: ~3.7",
> Port 5: ~2.7", Port 6: ~4.1"
> + // Port 7: ~4.5", Port 8: ~10.7", Port 9: ~10.5", Port 10: ~4.2", Port 11: ~4.3",
> Port 12: ~3.1", Port 13: ~2.9"
> + //
> +
> + //
> + // Port 0: ~3.5", Port 1: ~4.1", Port 2: ~4.6", Port 3: ~4.6", Port 4: ~12.5",
> Port 5: ~12", Port 6: ~5.1"
> + // Port 7: ~5.1", Port 8: ~4.1", Port 9: ~4.1", Port 10: ~14.5", Port 11: ~12.8",
> Port 12: ~12.9", Port 13: ~14.6"
> + //
> + UsbConfig->Usb20PortLength[0] = 0x53;
> + UsbConfig->Usb20PortLength[1] = 0x49;
> + UsbConfig->Usb20PortLength[2] = 0x47;
> + UsbConfig->Usb20PortLength[3] = 0x80;
> +
> + PeiPchUsbPolicyPpi->Mode = EHCI_MODE;
> +
> + PeiPchUsbPolicyPpi->EhciMemBaseAddr =
> PcdGet32(PcdPeiIchEhciControllerMemoryBaseAddress);
> +
> + PeiPchUsbPolicyPpi->EhciMemLength = (UINT32) 0x400 *
> PchEhciControllerMax;
> +
> + PeiPchUsbPolicyPpi->XhciMemBaseAddr = 0;
> +
> + PeiPchUsbPolicyPpi->UsbConfig = UsbConfig;
> +
> + PeiPchUsbPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
> +
> + PeiPchUsbPolicyPpiDesc->Guid = &gPchUsbPolicyPpiGuid;
> +
> + PeiPchUsbPolicyPpiDesc->Ppi = PeiPchUsbPolicyPpi;
> +
> + //
> + // Install PCH USB Policy PPI
> + //
> + Status = (**PeiServices).InstallPpi (PeiServices, PeiPchUsbPolicyPpiDesc);
> +
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c
> new file mode 100644
> index 0000000000..a359c95920
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c
> @@ -0,0 +1,1195 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + PlatformEarlyInit.c
> +
> +Abstract:
> +
> + Do platform specific PEI stage initializations.
> +
> +--*/
> +
> +
> +#include "PlatformEarlyInit.h"
> +
> +#ifdef __GNUC__
> +#pragma GCC push_options
> +#pragma GCC optimize ("O0")
> +#else
> +#pragma optimize ("", off)
> +#endif
> +
> +
> +
> +static EFI_PEI_STALL_PPI mStallPpi = {
> + PEI_STALL_RESOLUTION,
> + Stall
> +};
> +
> +static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = {
> + EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> + &gEfiPeiStallPpiGuid,
> + &mStallPpi
> +};
> +
> +//
> +// The reserved SMBus addresses are defined in PlatformDxe.h file.
> +//
> +static UINT8 mSmbusRsvdAddresses[] =
> PLATFORM_SMBUS_RSVD_ADDRESSES;
> +static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi = {
> + SMBUS_BASE_ADDRESS,
> + SMBUS_BUS_DEV_FUNC,
> + PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,
> + mSmbusRsvdAddresses
> +};
> +
> +static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi = {
> + EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> + &gPeiSmbusPolicyPpiGuid,
> + &mSmbusPolicyPpi
> +};
> +static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi = {
> + ProgramToneFrequency,
> + GenerateBeepTone
> +};
> +
> +static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi = {
> + EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> + &gPeiSpeakerInterfacePpiGuid,
> + &mSpeakerInterfacePpi
> +};
> +
> +static EFI_PEI_RESET_PPI mResetPpi = { IchReset };
> +
> +
> +static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi = {
> + (EFI_PEI_FIND_FV_FINDFV)FindFv
> +};
> +
> +static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gEfiPeiMasterBootModePpiGuid,
> + NULL
> + },
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gEfiPeiResetPpiGuid,
> + &mResetPpi
> + },
> + {
> + (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gEfiFindFvPpiGuid,
> + &mEfiFindFvPpi
> + }
> +};
> +
> +static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,
> + &gEfiEndOfPeiSignalPpiGuid,
> + (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback
> + },
> + {
> + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK|
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gEfiPeiMemoryDiscoveredPpiGuid,
> + (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback
> + }
> +
> +};
> +
> +
> +/**
> +
> + Parse the status registers for figuring out the wake-up event and save it
> into
> + an GUID HOB which will be referenced later. However, modification is
> required
> + to meet the chipset register definition and the practical hardware design.
> Thus,
> + this is just an example.
> +
> +
> + @param PeiServices pointer to the PEI Service Table
> + @param EFI_SUCCESS Always return Success
> +
> + @retval None
> +
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetWakeupEventAndSaveToHob (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + UINT16 Pm1Sts;
> + UINTN Gpe0Sts;
> + UINTN WakeEventData;
> +
> + //
> + // Read the ACPI registers
> + //
> + Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
> + Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);
> +
> + //
> + // Figure out the wake-up event
> + //
> + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {
> + WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
> + } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {
> + WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;
> + } else if (Gpe0Sts != 0) {
> + WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;
> + } else {
> + WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;
> + }
> +
> + DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));
> + DEBUG ((EFI_D_ERROR, "ACPI Wake Event Data: %02x\n",
> WakeEventData));
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +GetSetupVariable (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> + UINTN VariableSize;
> + EFI_STATUS Status;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
> +
> + VariableSize = sizeof (SYSTEM_CONFIGURATION);
> + ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (void **)&Variable
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Use normal setup default from NVRAM variable,
> + // the Platform Mode (manufacturing/safe/normal) is handle in
> PeiGetVariable.
> + //
> + VariableSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = Variable->GetVariable (
> + Variable,
> + L"Setup",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VariableSize,
> + SystemConfiguration
> + );
> + if (EFI_ERROR (Status) || VariableSize != sizeof(SYSTEM_CONFIGURATION))
> {
> + //The setup variable is corrupted
> + VariableSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = Variable->GetVariable(
> + Variable,
> + L"SetupRecovery",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VariableSize,
> + SystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> + return Status;
> +}
> +
> +EFI_STATUS
> +VlvPolicyInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_PPI_DESCRIPTOR *mVlvPolicyPpiDesc;
> + VLV_POLICY_PPI *mVlvPolicyPpi;
> +
> + Status = (*PeiServices)->AllocatePool(
> + PeiServices,
> + sizeof (EFI_PEI_PPI_DESCRIPTOR),
> + (void **)&mVlvPolicyPpiDesc
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = (*PeiServices)->AllocatePool(
> + PeiServices,
> + sizeof (VLV_POLICY_PPI),
> + (void **)&mVlvPolicyPpi
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Initialize PPI
> + //
> + (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof
> (VLV_POLICY_PPI), 0);
> + mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
> + mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid;
> + mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi;
> + mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration-
> >PrimaryVideoAdaptor;
> + mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration-
> >IgdDvmt50PreAlloc;
> + mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration-
> >IgdApertureSize;
> + mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize;
> + if (SystemConfiguration->PrimaryVideoAdaptor != 2) {
> + mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd;
> + } else {
> + mVlvPolicyPpi->GtConfig.InternalGraphics = 0;
> + }
> +
> +
> + mVlvPolicyPpi->GtConfig.IgdTurboEn = 1;
> +
> +
> + mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot;
> + mVlvPolicyPpi->PlatformData.DynSR = 1;
> + DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n",
> SystemConfiguration->ISPEn));
> + mVlvPolicyPpi->ISPEn = SystemConfiguration->ISPEn;
> + DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n",
> SystemConfiguration->ISPDevSel));
> + mVlvPolicyPpi->ISPPciDevConfig = SystemConfiguration->ISPDevSel;
> + if (SystemConfiguration->ISPEn == 0) {
> + mVlvPolicyPpi->ISPPciDevConfig = 0;
> + DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n",
> mVlvPolicyPpi->ISPPciDevConfig));
> + }
> + Status = (*PeiServices)->InstallPpi(
> + PeiServices,
> + mVlvPolicyPpiDesc
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +EFI_STATUS
> +ConfigureSoCGpio (
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> +
> + DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n"));
> + if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode
> + DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n"));
> +
> + //
> + //Silicon Steppings
> + //
> + switch (PchStepping()) {
> + case PchA0: // SOC A0 and A1
> + case PchA1:
> + DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO
> Configuration\n"));
> + SystemConfiguration->LpsseMMCEnabled = 1;
> + SystemConfiguration->LpsseMMC45Enabled = 0;
> + break;
> + case PchB0: // SOC B0 and later
> + default:
> + DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO
> Configuration\n"));
> + SystemConfiguration->LpsseMMCEnabled = 0;
> + SystemConfiguration->LpsseMMC45Enabled = 1;
> + break;
> + }
> + } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41
> + DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n"));
> + SystemConfiguration->LpsseMMCEnabled = 1;
> + SystemConfiguration->LpsseMMC45Enabled = 0;
> + } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5
> + DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n"));
> + SystemConfiguration->LpsseMMCEnabled = 0;
> + SystemConfiguration->LpsseMMC45Enabled = 1;
> +
> + } else { // Disable eMMC controllers
> + DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n"));
> + SystemConfiguration->LpsseMMCEnabled = 0;
> + SystemConfiguration->LpsseMMC45Enabled = 0;
> + }
> +
> + /*
> + 20.1.1 EMMC
> + SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0
> + SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390
> + SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0
> + SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400
> + SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0
> + SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360
> + MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380
> + MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0
> + MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370
> + MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0
> + MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330
> + */
> + if (SystemConfiguration->LpsseMMCEnabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01);
> + }
> +
> + /*
> + eMMC 4.5 controller
> + SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0
> + SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390
> + SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0
> + SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400
> + SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0
> + SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360
> + MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380
> + MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0
> + MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370
> + MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0
> + MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330
> + */
> + if (SystemConfiguration->LpsseMMC45Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03);
> +
> + }
> +
> +//
> +// Change GPIOC_0 setting to allow MMIO access under Android.
> +//
> + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,
> + (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) &
> (UINT32)~BIT0));
> + DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n"));
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +MeasuredBootInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> + if (SystemConfiguration->MeasuredBootEnable) {
> + PcdSetBool (PcdMeasuredBootEnable, TRUE);
> + } else {
> + PcdSetBool (PcdMeasuredBootEnable, FALSE);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +EFI_STATUS
> +ConfigureLpssAndSccGpio (
> + IN SYSTEM_CONFIGURATION *SystemConfiguration,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfo
> + )
> +{
> + /*One time configuration to each GPIO controller PSB_CONF register
> should be done before starting pad configuration:
> + GPIO SCORE - write 0x01001002 to IOBASE + 0x0700
> + GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00
> + GPIO SSUS - write 0x01001002 to IOBASE + 0x1700
> + */
> + DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n"));
> +
> + /*
> + 19.1.1 PWM0
> + PWM0 - write 0x2003CD01 to IOBASE + 0x00A0
> + 19.1.2 PWM1
> + PWM0 - write 0x2003CD01 to IOBASE + 0x00B0
> + */
> + if (SystemConfiguration->LpssPwm0Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01);
> + } else if (SystemConfiguration->LpssPwm0Enabled== 0) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00);
> + }
> +
> + if (SystemConfiguration->LpssPwm1Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01);
> + } else if (SystemConfiguration->LpssPwm1Enabled== 0) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00);
> + }
> +
> + /*
> + 19.1.3 UART1
> + UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020
> + UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010
> + UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000
> + UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040
> + */
> + if (SystemConfiguration->LpssHsuart0Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81);
> + if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) {
> + DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n"));
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80);
> + } else {
> + DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n"));
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD
> 4752617 0x2003CC81
> + }
> + } else if (SystemConfiguration->LpssHsuart0Enabled== 0) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80);
> + }
> +
> +
> + /*
> + 19.1.4 UART2
> + UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090
> + UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080
> + UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060
> + UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070
> + */
> + if (SystemConfiguration->LpssHsuart1Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81);
> +
> + if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) {
> + DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n"));
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); //
> UART2_RTS_B
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); //
> UART2_CTS_B
> + } else {
> + DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n"));
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD
> 4752617 0x2003CC81
> + }
> + } else if (SystemConfiguration->LpssHsuart1Enabled== 0) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80);
> + }
> +
> + /*
> + 19.1.5 SPI
> + SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110
> + SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100
> + SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130
> + SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120
> + */
> + if (SystemConfiguration->LpssSpiEnabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81);
> + } else if (SystemConfiguration->LpssSpiEnabled== 0) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80);
> + }
> +
> + /*
> + 19.1.6 I2C0
> + I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210
> + I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200
> + */
> + if (SystemConfiguration->LpssI2C0Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881);
> + }
> + /*
> + 19.1.7 I2C1
> + I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0
> + I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0
> + */
> +
> + if (SystemConfiguration->LpssI2C1Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881);
> + }
> + /*
> + 19.1.8 I2C2
> + I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0
> + I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0
> + */
> + if (SystemConfiguration->LpssI2C2Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881);
> + }
> + /*
> + 19.1.9 I2C3
> + I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190
> + I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0
> + */
> + if (SystemConfiguration->LpssI2C3Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881);
> + }
> + /*
> + 19.1.10 I2C4
> + I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0
> + I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170
> + */
> + if (SystemConfiguration->LpssI2C4Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881);
> + }
> + /*
> + 19.1.11 I2C5
> + I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150
> + I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140
> + */
> + //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.
> + if (SystemConfiguration->LpssI2C5Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881);
> + } else if(SystemConfiguration->LpssI2C5Enabled== 0) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880);
> + }
> + /*
> + 19.1.12 I2C6
> + I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180
> + I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160
> + */
> + if (SystemConfiguration->LpssI2C6Enabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881);
> + } else if (SystemConfiguration->LpssI2C6Enabled== 0) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880);
> + }
> +
> +
> + /*
> + 20.1.2 SDIO
> + SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320
> + SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300
> + SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350
> + SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0
> + SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340
> + SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310
> + */
> + if (SystemConfiguration->LpssSdioEnabled== 1) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81);
> + }
> +
> + /*
> + 20.1.3 SD Card
> + SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0
> + SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0
> + SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0
> + SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0
> + SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0
> + SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290
> + SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0
> + SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0
> + SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690
> + SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160
> + */
> + if (SystemConfiguration->LpssSdcardEnabled == 1) {
> + if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo-
> >BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) {
> + MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD
> + MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81);
> + MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7
> set to WP Pin
> + }
> + }
> +
> +
> + DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n"));
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +ConfigureLpeGpio (
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> + DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n"));
> +
> + if (SystemConfiguration->PchAzalia == 0) {
> + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7),
> (UINT32) (0x01));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7),
> (UINT32) (0x01));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7),
> (UINT32) (0x01));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7),
> (UINT32) (0x01));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7),
> (UINT32) (0x01));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7),
> (UINT32) (0x01));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7),
> (UINT32) (0x01));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7),
> (UINT32) (0x01));
> + }
> +
> + DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n"));
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +ConfigureSciSmiGpioRout (
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfo)
> +{
> + UINT32 GPI_Routing;
> +
> + GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS +
> R_PCH_PMC_GPI_ROUT);
> +
> + //
> + // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0
> to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
> + //
> + if(PlatformInfo->BoardRev == 3) {
> + GPI_Routing = GPI_Routing & 0xfffc3ffc;
> + GPI_Routing = GPI_Routing | 0x00024002;
> + }
> +
> + //
> + // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS
> 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
> + //
> + else {
> + GPI_Routing = GPI_Routing & 0x3fff3ffc;
> + GPI_Routing = GPI_Routing | 0x80004002;
> + }
> + MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT),
> GPI_Routing);
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +ConfigureMipiCsi (
> + VOID)
> +{
> + //
> + //Configure the platform clock for MIPI-CSI usage
> + //PLT_CLK0
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7),
> (UINT32) (0x01));
> +
> + //
> + //PLT_CLK1
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7),
> (UINT32) (0x01));
> +
> + //
> + //PLT_CLK2
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7),
> (UINT32) (0x01));
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +ConfigureUSBULPI (
> + VOID)
> +{
> + //
> + //Configure USB ULPI
> + //USB_ULPI_0_CLK
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330,
> (UINT32)~(0x187), (UINT32) (0x101));
> +
> + //
> + //USB_ULPI_0_DATA0
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380,
> (UINT32)~(0x187), (UINT32) (0x101));
> +
> + //
> + //USB_ULPI_0_DATA1
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360,
> (UINT32)~(0x187), (UINT32) (0x101));
> +
> + //
> + //USB_ULPI_0_DATA2
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310,
> (UINT32)~(0x187), (UINT32) (0x101));
> +
> + //
> + //USB_ULPI_0_DATA3
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370,
> (UINT32)~(0x187), (UINT32) (0x101));
> +
> + //
> + //USB_ULPI_0_DATA4
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300,
> (UINT32)~(0x187), (UINT32) (0x101));
> +
> + //
> + //USB_ULPI_0_DATA5
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390,
> (UINT32)~(0x187), (UINT32) (0x101));
> +
> + //
> + //USB_ULPI_0_DATA6
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320,
> (UINT32)~(0x187), (UINT32) (0x101));
> +
> + //
> + //USB_ULPI_0_DATA7
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0,
> (UINT32)~(0x187), (UINT32) (0x101));
> +
> + //
> + //USB_ULPI_0_DIR
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340,
> (UINT32)~(0x187), (UINT32) (0x81));
> +
> + //
> + //USB_ULPI_0_NXT
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350,
> (UINT32)~(0x187), (UINT32) (0x101));
> +
> + //
> + //USB_ULPI_0_STP
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0,
> (UINT32)~(0x187), (UINT32) (0x81));
> +
> + //
> + //USB_ULPI_0_REFCLK
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288,
> (UINT32)~(0x7), (UINT32) (GPI));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280,
> (UINT32)~(0x187), (UINT32) (0x101));
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +DisableRTD3 (
> + VOID)
> +{
> + //
> + //Disable RTD3
> + //
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210,
> (UINT32)~(0x0f000007), (UINT32) (0x00));
> + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0,
> (UINT32)~(0x0f000007), (UINT32) (0x00));
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Platform specific initializations in stage1.
> +
> + @param FfsHeader Pointer to the PEIM FFS file header.
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval EFI_SUCCESS Operation completed successfully.
> + @retval Otherwise Platform initialization failed.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PlatformEarlyInitEntry (
> +
> + IN EFI_PEI_FILE_HANDLE FileHandle,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> + SYSTEM_CONFIGURATION SystemConfiguration;
> + EFI_PLATFORM_INFO_HOB *PlatformInfo;
> + EFI_PEI_HOB_POINTERS Hob;
> + EFI_PLATFORM_CPU_INFO PlatformCpuInfo;
> + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock;
> + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *NewDescriptorBlock;
> + UINTN Index;
> + UINTN MaxIndex;
> + UINT64 Base;
> + UINT64 Size;
> + UINT64 NewSize;
> +
> + //
> + // Make sure base and size of the SMRAM region is aligned
> + //
> + Hob.Raw = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid);
> + if (Hob.Raw != NULL) {
> + DescriptorBlock = GET_GUID_HOB_DATA (Hob.Raw);
> + DEBUG ((DEBUG_INFO, "SMM PEI SMRAM Memory Reserved HOB\n"));
> + for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions;
> Index++) {
> + DEBUG((DEBUG_INFO, " SMRAM Descriptor[%02x]: Start=%016lx
> Size=%016lx State=%02x\n",
> + Index,
> + DescriptorBlock->Descriptor[Index].PhysicalStart,
> + DescriptorBlock->Descriptor[Index].PhysicalSize,
> + DescriptorBlock->Descriptor[Index].RegionState
> + ));
> + }
> +
> + //
> + // Find the largest usable range of SMRAM between 1MB and 4GB
> + //
> + for (Index = 0, MaxIndex = 0, Size = 0; Index < DescriptorBlock-
> >NumberOfSmmReservedRegions; Index++) {
> + //
> + // Skip any SMRAM region that is already allocated, needs testing, or
> needs ECC initialization
> + //
> + if ((DescriptorBlock->Descriptor[Index].RegionState & (EFI_ALLOCATED |
> EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
> + continue;
> + }
> + //
> + // Skip any SMRAM region below 1MB
> + //
> + if (DescriptorBlock->Descriptor[Index].CpuStart < BASE_1MB) {
> + continue;
> + }
> + //
> + // Skip any SMRAM region that is above 4GB or crosses the 4GB
> boundary
> + //
> + if ((DescriptorBlock->Descriptor[Index].CpuStart + DescriptorBlock-
> >Descriptor[Index].PhysicalSize) >= BASE_4GB) {
> + continue;
> + }
> + //
> + // Cache the largest SMRAM region index
> + //
> + if (DescriptorBlock->Descriptor[Index].PhysicalSize >= DescriptorBlock-
> >Descriptor[MaxIndex].PhysicalSize) {
> + MaxIndex = Index;
> + }
> + }
> +
> + //
> + // Find the extent of the contiguous SMRAM region that surrounds the
> largest usable SMRAM range
> + //
> + Base = DescriptorBlock->Descriptor[MaxIndex].CpuStart;
> + Size = DescriptorBlock->Descriptor[MaxIndex].PhysicalSize;
> + for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions;
> Index++) {
> + if (DescriptorBlock->Descriptor[Index].CpuStart < Base &&
> + Base == (DescriptorBlock->Descriptor[Index].CpuStart +
> DescriptorBlock->Descriptor[Index].PhysicalSize)) {
> + Base = DescriptorBlock->Descriptor[Index].CpuStart;
> + Size += DescriptorBlock->Descriptor[Index].PhysicalSize;
> + } else if ((Base + Size) == DescriptorBlock->Descriptor[Index].CpuStart) {
> + Size += DescriptorBlock->Descriptor[Index].PhysicalSize;
> + }
> + }
> +
> + //
> + // Round SMRAM region up to nearest power of 2 that is at least 4KB
> + //
> + NewSize = MAX (LShiftU64 (1, HighBitSet64 (Size - 1) + 1), SIZE_4KB);
> + if ((Base & ~(NewSize - 1)) != Base) {
> + //
> + // SMRAM region Base Address has smaller alignment than SMRAM
> region Size
> + // This is not compatible with SMRR settings
> + //
> + DEBUG((DEBUG_ERROR, "ERROR: SMRAM Region Size has larger
> alignment than SMRAM Region Base\n"));
> + DEBUG((DEBUG_ERROR, " SMRAM Region Base=%016lx Size=%016lx\n",
> Base, NewSize));
> + ASSERT (FALSE);
> + } else if (Size != NewSize) {
> + //
> + // See if the size difference can be added to an adjacent descriptor that
> is already allocated
> + //
> + for (Index = 0; Index < DescriptorBlock-
> >NumberOfSmmReservedRegions; Index++) {
> + if ((DescriptorBlock->Descriptor[Index].CpuStart + DescriptorBlock-
> >Descriptor[Index].PhysicalSize) == (Base + Size)) {
> + if (((DescriptorBlock->Descriptor[Index].RegionState) &
> EFI_ALLOCATED) != 0) {
> + DescriptorBlock->Descriptor[Index].PhysicalSize += (NewSize - Size);
> + Size = NewSize;
> + break;
> + }
> + }
> + }
> +
> + if (Size != NewSize) {
> + //
> + // Add an allocated descriptor to the SMM PEI SMRAM Memory
> Reserved HOB to accomodate the larger size.
> + //
> + Index = DescriptorBlock->NumberOfSmmReservedRegions;
> + NewDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK
> *)BuildGuidHob (
> + &gEfiSmmPeiSmramMemoryReserveGuid,
> + sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + ((Index + 1) * sizeof
> (EFI_SMRAM_DESCRIPTOR))
> + );
> + ASSERT (NewDescriptorBlock != NULL);
> +
> + //
> + // Copy old EFI_SMRAM_HOB_DESCRIPTOR_BLOCK to new allocated
> region
> + //
> + CopyMem (
> + NewDescriptorBlock,
> + DescriptorBlock,
> + sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + (Index * sizeof
> (EFI_SMRAM_DESCRIPTOR))
> + );
> +
> + //
> + // Make sure last descriptor in NewDescriptorBlock contains last
> descriptor from DescriptorBlock
> + //
> + CopyMem (
> + &NewDescriptorBlock->Descriptor[Index],
> + &NewDescriptorBlock->Descriptor[Index - 1],
> + sizeof (EFI_SMRAM_DESCRIPTOR)
> + );
> +
> + //
> + // Fill next to last descriptor with an allocated descriptor that aligns the
> total size of SMRAM
> + //
> + NewDescriptorBlock->Descriptor[Index - 1].CpuStart = Base + Size;
> + NewDescriptorBlock->Descriptor[Index - 1].PhysicalStart = Base + Size;
> + NewDescriptorBlock->Descriptor[Index - 1].PhysicalSize = NewSize -
> Size;
> + NewDescriptorBlock->Descriptor[Index - 1].RegionState =
> DescriptorBlock->Descriptor[MaxIndex].RegionState | EFI_ALLOCATED;
> + NewDescriptorBlock->NumberOfSmmReservedRegions++;
> +
> + //
> + // Invalidate the original gEfiSmmPeiSmramMemoryReserveGuid HOB
> + //
> + ZeroMem (&Hob.Guid->Name, sizeof (&Hob.Guid->Name));
> + }
> +
> + Hob.Raw = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid);
> + DescriptorBlock = GET_GUID_HOB_DATA (Hob.Raw);
> + DEBUG ((DEBUG_INFO, "SMM PEI SMRAM Memory Reserved HOB -
> Updated\n"));
> + for (Index = 0; Index < DescriptorBlock-
> >NumberOfSmmReservedRegions; Index++) {
> + DEBUG((DEBUG_INFO, " SMRAM Descriptor[%02x]: Start=%016lx
> Size=%016lx State=%02x\n",
> + Index,
> + DescriptorBlock->Descriptor[Index].PhysicalStart,
> + DescriptorBlock->Descriptor[Index].PhysicalSize,
> + DescriptorBlock->Descriptor[Index].RegionState
> + ));
> + }
> + }
> + }
> +
> + //
> + // Initialize SmbusPolicy PPI
> + //
> + Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Initialize Stall PPIs
> + //
> + Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Initialize platform PPIs
> + //
> + Status = (*PeiServices)->InstallPpi (PeiServices,
> &mInstallSpeakerInterfacePpi);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Variable initialization
> + //
> + ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));
> +
> + //
> + // Set the some PCI and chipset range as UC
> + // And align to 1M at leaset
> + //
> + Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
> + ASSERT (Hob.Raw != NULL);
> + PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
> +
> + //
> + // Initialize PlatformInfo HOB
> + //
> + MultiPlatformInfoInit(PeiServices, PlatformInfo);
> +
> + //
> + // Do basic MCH init
> + //
> + MchInit (PeiServices);
> +
> + //
> + // Set the new boot mode
> + //
> + Status = UpdateBootMode (PeiServices, PlatformInfo);
> + ASSERT_EFI_ERROR (Status);
> +
> + SetPlatformBootMode (PeiServices, PlatformInfo);
> +
> + //
> + // Get setup variable. This can only be done after BootMode is updated
> + //
> + GetSetupVariable (PeiServices, &SystemConfiguration);
> +
> + CheckOsSelection(PeiServices, &SystemConfiguration);
> +
> + //
> + // Update PlatformInfo HOB according to setup variable
> + //
> + PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration);
> +
> + InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration);
> +
> + //
> + // Initialize VlvPolicy PPI
> + //
> + Status = VlvPolicyInit (PeiServices, &SystemConfiguration);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Soc specific GPIO setting
> + //
> + ConfigureSoCGpio(&SystemConfiguration);
> +
> + //
> + // Baylake Board specific.
> + //
> + if (PlatformInfo->BoardId == BOARD_ID_BL_RVP ||
> + PlatformInfo->BoardId == BOARD_ID_BL_FFRD ||
> + PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 ||
> + PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ||
> + PlatformInfo->BoardId == BOARD_ID_BL_STHI ||
> + PlatformInfo->BoardId == BOARD_ID_BB_RVP ||
> + PlatformInfo->BoardId == BOARD_ID_BS_RVP ||
> + PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||
> + PlatformInfo->BoardId == BOARD_ID_MINNOW2_TURBOT||
> + PlatformInfo->BoardId == BOARD_ID_CVH) {
> + ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);
> +
> + }
> +
> +
> + //
> + // Configure LPE
> + // Alpine Valley and Bayley Bay board specific
> + //
> + ConfigureLpeGpio(&SystemConfiguration);
> +
> + //
> + // Bayley Bay Board specific.
> + //
> + ConfigureSciSmiGpioRout(PlatformInfo);
> + if (SystemConfiguration.LpssI2C3Enabled == 1) {
> + ConfigureMipiCsi();
> + }
> +
> +
> + //
> + // Do basic CPU init
> + //
> + Status = PlatformCpuInit (PeiServices, &SystemConfiguration,
> &PlatformCpuInfo);
> +
> + //
> + // Perform basic SSA related platform initialization
> + //
> + PlatformSsaInit (&SystemConfiguration,PeiServices);
> +
> +
> + //
> + // Do basic PCH init
> + //
> + Status = PlatformPchInit (&SystemConfiguration, PeiServices,
> PlatformInfo->PlatformType);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Initialize platform PPIs
> + //
> + Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);
> + ASSERT_EFI_ERROR (Status);
> +
> + if (PlatformInfo->BoardId != BOARD_ID_CVH) {
> + InstallPlatformClocksNotify (PeiServices);
> + InstallPlatformSysCtrlGPIONotify(PeiServices);
> + }
> +
> + //
> + // Initialize platform PPIs
> + //
> + Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Initialize Measured Boot
> + //
> + Status = MeasuredBootInit (PeiServices, &SystemConfiguration);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> +/**
> +
> + Return the mainblockcompact Fv.
> +
> + @param FvNumber Our enumeration of the firmware volumes we care
> about.
> +
> + @param FvAddress Base Address of the memory containing the firmware
> volume
> +
> + @retval EFI_SUCCESS
> + @retval EFI_NOT_FOUND
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FindFv (
> + IN EFI_PEI_FIND_FV_PPI *This,
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT UINT8 *FvNumber,
> + OUT EFI_FIRMWARE_VOLUME_HEADER **FVAddress
> + )
> +{
> + //
> + // At present, we only have one Fv to search
> + //
> + if (*FvNumber == 0) {
> + *FvNumber = 1;
> + *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER
> *)(UINTN)FixedPcdGet32 (PcdFlashFvMainBase);
> + return EFI_SUCCESS;
> + }
> + else if (*FvNumber == 1) {
> + *FvNumber = 2;
> + *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER
> *)(UINTN)FixedPcdGet32 (PcdFlashFvRecovery2Base);
> + return EFI_SUCCESS;
> + }
> + else { // Not the one Fv we care about
> + return EFI_NOT_FOUND;
> + }
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +CpuOnlyReset (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> +// MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)
> +#ifdef __GNUC__
> + __asm__
> + (
> + "xorl %ecx, %ecx\n"
> + "1:hlt; hlt; hlt\n"
> + "jmp 1b\n"
> + );
> +#else
> + _asm {
> + xor ecx, ecx
> + HltLoop:
> + hlt
> + hlt
> + hlt
> + loop HltLoop
> + }
> +#endif
> + //
> + // If we get here we need to mark it as a failure.
> + //
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +#ifdef __GNUC__
> +#pragma GCC pop_options
> +#else
> +#pragma optimize ("", on)
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h
> new file mode 100644
> index 0000000000..29749277d7
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h
> @@ -0,0 +1,1499 @@
> +/*++
> +
> + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + PlatformEarlyInit.h
> +
> +Abstract:
> +
> + Platform Early Stage header file
> +
> +
> +
> +--*/
> +
> +/*++
> + This file contains an 'Intel Peripheral Driver' and is
> + licensed for Intel CPUs and chipsets under the terms of your
> + license agreement with Intel or your vendor. This file may
> + be modified by the user, subject to additional terms of the
> + license agreement
> +--*/
> +
> +#ifndef _EFI_PLATFORM_EARLY_INIT_H_
> +#define _EFI_PLATFORM_EARLY_INIT_H_
> +
> +#define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
> +#include <FrameworkPei.h>
> +#include "PlatformBaseAddresses.h"
> +#include "PchAccess.h"
> +#include "VlvAccess.h"
> +#include "SetupMode.h"
> +#include "PlatformBootMode.h"
> +#include "Platform.h"
> +#include "LegacySpeaker.h"
> +
> +#include <Ppi/Stall.h>
> +#include <Guid/PlatformInfo.h>
> +#include <Guid/SetupVariable.h>
> +#include <Ppi/AtaController.h>
> +#include <Ppi/FindFv.h>
> +#include <Ppi/BootInRecoveryMode.h>
> +#include <Ppi/ReadOnlyVariable2.h>
> +#include <Ppi/Capsule.h>
> +#include <Guid/EfiVpdData.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/MtrrLib.h>
> +#include <Library/CpuIA32.h>
> +
> +#include <IndustryStandard/Pci22.h>
> +#include <Ppi/Speaker.h>
> +#include <Guid/FirmwareFileSystem.h>
> +#include <Guid/MemoryTypeInformation.h>
> +#include <Ppi/Cache.h>
> +#include <Ppi/Smbus.h>
> +#include <Library/PchPlatformLib.h>
> +#include <Ppi/SmbusPolicy.h>
> +#include <Ppi/Reset.h>
> +#include <Ppi/EndOfPeiPhase.h>
> +#include <Ppi/MemoryDiscovered.h>
> +#include <Ppi/VlvPolicy.h>
> +#include <Guid/GlobalVariable.h>
> +#include <Ppi/RecoveryModule.h>
> +#include <Ppi/DeviceRecoveryModule.h>
> +#include <Guid/Capsule.h>
> +#include <Guid/RecoveryDevice.h>
> +#include <Ppi/MasterBootMode.h>
> +#include <Guid/PlatformCpuInfo.h>
> +#include <Guid/OsSelection.h>
> +#include <Guid/SmramMemoryReserve.h>
> +#include <Register/Msr.h>
> +
> +#define SMC_LAN_ON 0x46
> +#define SMC_LAN_OFF 0x47
> +#define SMC_DEEP_S3_STS 0xB2
> +
> +
> +
> +
> +//
> +// Wake Event Types
> +//
> +#define SMBIOS_WAKEUP_TYPE_RESERVED 0x00
> +#define SMBIOS_WAKEUP_TYPE_OTHERS 0x01
> +#define SMBIOS_WAKEUP_TYPE_UNKNOWN 0x02
> +#define SMBIOS_WAKEUP_TYPE_APM_TIMER 0x03
> +#define SMBIOS_WAKEUP_TYPE_MODEM_RING 0x04
> +#define SMBIOS_WAKEUP_TYPE_LAN_REMOTE 0x05
> +#define SMBIOS_WAKEUP_TYPE_POWER_SWITCH 0x06
> +#define SMBIOS_WAKEUP_TYPE_PCI_PME 0x07
> +#define SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED 0x08
> +
> +#define EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE 0x80000008
> +
> +//
> +// Defines for stall ppi
> +//
> +#define PEI_STALL_RESOLUTION 1
> +
> +//
> +// Used in PEI memory test routines
> +//
> +#define MEMORY_TEST_COVER_SPAN 0x40000
> +#define MEMORY_TEST_PATTERN 0x5A5A5A5A
> +
> +#define EFI_LOW_BEEP_FREQUENCY 0x31B
> +#define EFI_HIGH_BEEP_FREQUENCY 0x254
> +
> +//
> +// General Purpose Constants
> +//
> +#define ICH_ACPI_TIMER_MAX_VALUE 0x1000000 //The timer is 24 bit
> overflow
> +
> +
> +
> +//
> +//
> +// GPIO Register Settings for ValleyFalls (Tablet)
> +//
> +//
> +// IO Space configyuration registers
> +// Field Descriptions:
> +// USE: Defines the pin's usage model: GPIO (G) or Native (N) mode.
> +// I/O: Defines whether GPIOs are inputs (I) or outputs (O).
> +// (Note: Only meaningful for pins used as GPIOs.)
> +// LVL: This field gives you the initial value for "output" GPIO's.
> +// (Note: The output level is dependent upon whether the pin is
> inverted.)
> +// TPE: Defines whether Trigger Positive Edge Enable.
> +// TNE: Defines whether Trigger Negative Edge Enable.
> +// WAKE_EN: only support in SUS community
> +// (Note: Only affects the level sent to the GPE logic and does not
> +// affect the level read through the GPIO registers.)
> +//
> +//
> +// Memory spcae configuration registers
> +//
> +// Field Descriptions:
> +// PAD releated:
> +// PAD_CONF0
> +// PAD_CONF1
> +// PAD_VAL
> +// PAD_DFT
> +//
> +// Notes:
> +// 1. N = Native , G = GPIO , I = Input, O = Output, - = BOTH/NOT SURE
> +//
> +// Signal UsedAs USE I/O LVL TPE TNE PCONF0
> PCONF1 PVAL PDFT
> +// -----------------------------------------------------------------------------------------
> --------------------------------
> +// GPIO0 UART1_RXD-L N I - - - cd29h - -
> -
> +// GPIO1 UART1_TXD-0 N O - - - cd29h - -
> -
> +// *GPIO2 UART1_RTS_B-1 N I - - - cca9h - -
> -
> +// *GPIO3 UART1_CTS_B-H N O - - - cca9h -
> - -
> +
> +// GPIO4 I2C1_SDA-OD-O N - - - - cca9h - -
> -
> +// GPIO5 I2C1_SCL-OD-O N - - - - cca9h - -
> -
> +// GPIO6 I2S_SYSCLK-0 N O - - - 8d51h - -
> -
> +// GPIO7 I2S_L_R-0 (SP) N O - - - 8cd1h - -
> -
> +// GPIO8 I2S_DATA_OUT-0 N O - - - 8cd1h -
> - -
> +// GPIO9 I2S_SDATA_IN-L N I - - - 8cd1h - -
> -
> +
> +// GPIO10 PCM_CLK-0 N O - - - 8d51h - -
> -
> +// GPIO11 PCM_FSYNC-0 (SP) N O - - - 8cd1h -
> - -
> +// GPIO12 PCM_DATA_OUT-0 (SP) N O - - - 8cd1h -
> - -
> +// GPIO13 PCM_DATA_IN-L N I - - - 8d51h -
> - -
> +
> +// GPIO14 SATA_GP0 N - - - - - - - -
> +// GPIO15 I2C2_SDA-OD-O/I N - - - - ccaah - -
> -
> +
> +// GPIO16 SATA_LEDN N O - - - - - - -
> +// GPIO17 UART2_RTS_B-1 N I - - - cd2ah - -
> -
> +// GPIO18 UART2_CTS_B-H N O - - - ccaah -
> - -
> +// GPIO19 UART2_RXD-H N I - - - ccaah - -
> -
> +
> +// GPIO20 I2C2_SCL-OD-O/I N - - - - ccaah - -
> -
> +// GPIO21 **PCIE_CLKREQ4B N - - - - - - -
> -
> +// GPIO22 UART2_TXD-0 N O - - - ccaah - -
> -
> +// GPIO23 FLEX_CLK_SE1 N - - - - - - - -
> +
> +// GPIO24 SPI0_SCK-0 N O - - - 8d02h - -
> -
> +// GPIO25 SPI0_CS-1 N O - - - 8d02h - - -
> +// GPIO26 SPI0_MOSI-0 N O - - - 8d02h - -
> -
> +// GPIO27 SPI0_MISO-L N I - - - 8d02h - -
> -
> +
> +// GPIO28 UART3_RXD-L N I - - - - - - -
> +// GPIO29 UART3_TXD-0 N O - - - - - - -
> +// GPIO30 UART4_RXD-L N I - - - - - - -
> +// GPIO31 UART4_TXD-0 N O - - - - - - -
> +
> +// GPIO32 SDMMC1_CLK N - - - - 208d51h -
> - -
> +// GPIO33 SDMMC1_D0 N - - - - 8cd1h - -
> -
> +// GPIO34 SDMMC1_D1 N - - - - 8cd1h - -
> -
> +// GPIO35 SDMMC1_D2 N - - - - 8cd1h - -
> -
> +// GPIO36 SDMMC1_D3_CD_B N - - - - 8cd1h -
> - -
> +// GPIO37 MMC1_D4_SD_WE N - - - - 8cd1h -
> - -
> +// GPIO38 MMC1_D5 N - - - - 8cd1h - -
> -
> +// GPIO39 MMC1_D6 N - - - - 8cd1h - -
> -
> +// GPIO40 MMC1_D7 N - - - - 8cd1h - -
> -
> +// GPIO41 SDMMC1_CMD N - - - - 8cd1h -
> - -
> +// GPIO42 MMC1_RESET_B N - - - - 208d51h -
> - -
> +
> +// GPIO43 SDMMC2_CLK N - - - - 208d51h -
> - -
> +// GPIO44 SDMMC2_D0 N - - - - 8cd1h - -
> -
> +// GPIO45 SDMMC2_D1 N - - - - 8cd1h - -
> -
> +// GPIO46 SDMMC2_D2 N - - - - 8cd1h - -
> -
> +// GPIO47 SDMMC2_D3_CD_B N - - - - 8cd1h -
> - -
> +// GPIO48 SDMMC2_CMD N - - - - 8cd1h -
> - -
> +
> +// GPIO49 SDMMC3_CLK N - - - - 8d51h - -
> -
> +// GPIO50 SDMMC3_D0 N - - - - 8cd1h - -
> -
> +// GPIO51 SDMMC3_D1 N - - - - 8cd1h - -
> -
> +// GPIO52 SDMMC3_D2 N - - - - 8cd1h - -
> -
> +// GPIO53 SDMMC3_D3 N - - - - 8cd1h - -
> -
> +// GPIO54 SDMMC3_CD_B N - - - - cca9h -
> - -
> +// GPIO55 SDMMC3_CMD N - - - - 8cd1h -
> - -
> +// GPIO56 SDMMC3_1P8_EN N - - - - cd29h -
> - -
> +
> +// GPIO57 LPC_AD0 N - - - - - - - -
> +// GPIO58 LPC_AD1 N - - - - - - - -
> +// GPIO59 LPC_AD2 N - - - - - - - -
> +// GPIO60 LPC_AD3 N - - - - - - - -
> +// GPIO61 LPC_FRAMEB N O - - - - - - -
> +// GPIO62 LPC_CLKOUT0 N O - - - - - - -
> +// GPIO63 LPC_CLKOUT1 N O - - - - - - -
> +// GPIO64 LPC_CLKRUNB N - - - - - - - -
> +
> +// GPIO65 SMB_DATA N - - - - - - - -
> +// GPIO66 SMB_CLK N - - - - - - - -
> +// GPIO67 SMB_ALERTB N - - - - - - - -
> +
> +// GPIO68 ILB_SEIRQ N - - - - - - - -
> +// GPIO69 SPKR N O - - - - - - -
> +
> +//SUS WELL
> +
> +//GPIO_SUS0 BT_WAKEUP_VLV N O - - - CCA8h
> - - -
> +//GPIO_SUS1 BT_CLOCK_REQ N O - - - CCA8h
> - - -
> +//GPIO_SUS2 WIFI_PWR_EN N O - - - CCA8h
> - - -
> +//GPIO_SUS3 SD_CARD_PWR_EN N O - - - CD28h
> - - -
> +//GPIO_SUS4 GPIO_SUS4 N O - - - CD28h -
> - -
> +//GPIO_SUS5 GPIO_SUS5 N O - - - CD28h -
> - -
> +//GPIO_SUS6 SUSPWRDNACK N O - - - 8850h
> - - -
> +//GPIO_SUS7 PMU_SLP_DDRVTT_B N O - - - 8850h
> - - -
> +//GPIO_SUS8 PMU_WAKE_B N O - - - CCA8h
> - - -
> +//GPIO_SUS9 PMU_PWRBTN_B N O - - - CCA8h
> - - -
> +//GPIO_SUS10 PMU_WAKE_LAN_B N O - - -
> CCA8h - - -
> +//GPIO_SUS11 SUS_STAT_B N O - - - C828h -
> - -
> +//GPIO_SUS12 GPIO_SUS12 N O - - - C828h -
> - -
> +//GPIO_SUS13 USB_OC0_B-20K,H N O - - - CCA8h
> - - -
> +//GPIO_SUS14 GPIO_SUS14 N O - - - CCA8h -
> - -
> +//GPIO_SUS15 SPI_CS1_B-20K,H N O - - - 8C80h
> - - -
> +//GPIO_SUS16 PMU_SUSCLK N O - - - C828h -
> - -
> +//
> +
> +
> +#define VF_TAB_GPIO_USE_SEL_VAL_0_31 0x00000000
> +#define VF_TAB_GPIO_USE_SEL_VAL_32_63 0x00000000
> +#define VF_TAB_GPIO_USE_SEL_VAL_64_70 0x00000000
> +#define VF_TAB_GPIO_USE_SEL_VAL_SUS 0x00000000
> +
> +//
> +//1010 --00 0100 01-- 0101 --0- 0001 1010
> +//
> +#define VF_TAB_GPIO_IO_SEL_VAL_0_31 0x00000000 // BIT30 | BIT28 |
> BIT27 | BIT19 | BIT17 | BIT13 | BIT9 | BIT2 | BIT0
> +#define VF_TAB_GPIO_IO_SEL_VAL_32_63 0x00000000
> +#define VF_TAB_GPIO_IO_SEL_VAL_64_70 0x00000000
> +#define VF_TAB_GPIO_IO_SEL_VAL_SUS 0x00000000
> +
> +
> +#define VF_TAB_GPIO_LVL_VAL_0_31 0x00000000
> +#define VF_TAB_GPIO_LVL_VAL_32_63 0x00000000
> +#define VF_TAB_GPIO_LVL_VAL_64_70 0x00000000
> +#define VF_TAB_GPIO_LVL_VAL_SUS 0x00000000
> +
> +#define VF_TAB_GPIO_TPE_VAL_0_31 0x00000000
> +#define VF_TAB_GPIO_TPE_VAL_SUS 0x00000000
> +
> +#define VF_TAB_GPIO_TNE_VAL_0_31 0x00000000
> +#define VF_TAB_GPIO_TNE_VAL_SUS 0x00000000
> +
> +#define VF_TAB_GPIO_TS_VAL_0_31 0x00000000
> +#define VF_TAB_GPIO_TS_VAL_SUS 0x00000000
> +
> +
> +//
> +// Memory space registers
> +//
> +
> +//
> +// CONF0
> +//
> +#define VF_TAB_PAD_CONF0_GPIO0 0xcd29
> +#define VF_TAB_PAD_CONF0_GPIO1 0xcd29
> +#define VF_TAB_PAD_CONF0_GPIO2 0xcca9
> +#define VF_TAB_PAD_CONF0_GPIO3 0xcca9
> +#define VF_TAB_PAD_CONF0_GPIO4 0xcca9
> +#define VF_TAB_PAD_CONF0_GPIO5 0xcca9
> +#define VF_TAB_PAD_CONF0_GPIO6 0x8d51
> +#define VF_TAB_PAD_CONF0_GPIO7 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO8 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO9 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO10 0x8d51
> +#define VF_TAB_PAD_CONF0_GPIO11 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO12 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO13 0x8d51
> +#define VF_TAB_PAD_CONF0_GPIO14 0xCCA8
> +#define VF_TAB_PAD_CONF0_GPIO15 0xccaa
> +#define VF_TAB_PAD_CONF0_GPIO16 0xC828
> +#define VF_TAB_PAD_CONF0_GPIO17 0xcd2a
> +#define VF_TAB_PAD_CONF0_GPIO18 0xccaa
> +#define VF_TAB_PAD_CONF0_GPIO19 0xccaa
> +#define VF_TAB_PAD_CONF0_GPIO20 0xccaa
> +#define VF_TAB_PAD_CONF0_GPIO21 0xCCA9
> +#define VF_TAB_PAD_CONF0_GPIO22 0xccaa
> +#define VF_TAB_PAD_CONF0_GPIO23 0xCD2A
> +#define VF_TAB_PAD_CONF0_GPIO24 0x8d02
> +#define VF_TAB_PAD_CONF0_GPIO25 0x8d02
> +#define VF_TAB_PAD_CONF0_GPIO26 0x8d02
> +#define VF_TAB_PAD_CONF0_GPIO27 0x8d02
> +#define VF_TAB_PAD_CONF0_GPIO28 0x8D02
> +#define VF_TAB_PAD_CONF0_GPIO29 0x8D02
> +#define VF_TAB_PAD_CONF0_GPIO30 0x8D00
> +#define VF_TAB_PAD_CONF0_GPIO31 0xCD2A
> +#define VF_TAB_PAD_CONF0_GPIO32 0x208d51
> +#define VF_TAB_PAD_CONF0_GPIO33 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO34 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO35 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO36 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO37 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO38 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO39 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO40 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO41 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO42 0x208d51
> +#define VF_TAB_PAD_CONF0_GPIO43 0x208d51
> +#define VF_TAB_PAD_CONF0_GPIO44 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO45 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO46 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO47 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO48 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO49 0x8d51
> +#define VF_TAB_PAD_CONF0_GPIO50 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO51 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO52 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO53 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO54 0xcca9
> +#define VF_TAB_PAD_CONF0_GPIO55 0x8cd1
> +#define VF_TAB_PAD_CONF0_GPIO56 0xcd29
> +#define VF_TAB_PAD_CONF0_GPIO57 0x8C80
> +#define VF_TAB_PAD_CONF0_GPIO58 0x8C80
> +#define VF_TAB_PAD_CONF0_GPIO59 0x8C80
> +#define VF_TAB_PAD_CONF0_GPIO60 0x8C80
> +#define VF_TAB_PAD_CONF0_GPIO61 0x8800
> +#define VF_TAB_PAD_CONF0_GPIO62 0x8D00
> +#define VF_TAB_PAD_CONF0_GPIO63 0x8800
> +#define VF_TAB_PAD_CONF0_GPIO64 0x8800
> +#define VF_TAB_PAD_CONF0_GPIO65 0xC828
> +#define VF_TAB_PAD_CONF0_GPIO66 0xC828
> +#define VF_TAB_PAD_CONF0_GPIO67 0xC828
> +#define VF_TAB_PAD_CONF0_GPIO68 0xCCA8
> +#define VF_TAB_PAD_CONF0_GPIO69 0xC828
> +#define VF_TAB_PAD_CONF0_GPIO70 0xCCA8
> +
> +
> +
> +//
> +// PAD_CONF1
> +//
> +#define VF_TAB_PAD_CONF1_GPIO0 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO1 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO2 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO3 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO4 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO5 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO6 0x1F000F
> +#define VF_TAB_PAD_CONF1_GPIO7 0x1F000F
> +#define VF_TAB_PAD_CONF1_GPIO8 0x1F000F
> +#define VF_TAB_PAD_CONF1_GPIO9 0x1F000F
> +#define VF_TAB_PAD_CONF1_GPIO10 0x1F000F
> +#define VF_TAB_PAD_CONF1_GPIO11 0x1F000F
> +#define VF_TAB_PAD_CONF1_GPIO12 0x1F000F
> +#define VF_TAB_PAD_CONF1_GPIO13 0x1F000F
> +#define VF_TAB_PAD_CONF1_GPIO14 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO15 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO16 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO17 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO18 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO19 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO20 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO21 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO22 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO23 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO24 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO25 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO26 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO27 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO28 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO29 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO30 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO31 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO32 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO33 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO34 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO35 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO36 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO37 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO38 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO39 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO40 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO41 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO42 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO43 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO44 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO45 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO46 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO47 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO48 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO49 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO50 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO51 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO52 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO53 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO54 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO55 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO56 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO57 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO58 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO59 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO60 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO61 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO62 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO63 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO64 0x00000
> +#define VF_TAB_PAD_CONF1_GPIO65 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO66 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO67 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO68 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO69 0x20002
> +#define VF_TAB_PAD_CONF1_GPIO70 0x20002
> +
> +
> +//
> +// PAD_VAL
> +//
> +#define VF_TAB_PAD_VAL_GPIO0 0x2
> +#define VF_TAB_PAD_VAL_GPIO1 0x2
> +#define VF_TAB_PAD_VAL_GPIO2 0x2
> +#define VF_TAB_PAD_VAL_GPIO3 0x2
> +#define VF_TAB_PAD_VAL_GPIO4 0x2
> +#define VF_TAB_PAD_VAL_GPIO5 0x2
> +#define VF_TAB_PAD_VAL_GPIO6 0x2
> +#define VF_TAB_PAD_VAL_GPIO7 0x2
> +#define VF_TAB_PAD_VAL_GPIO8 0x2
> +#define VF_TAB_PAD_VAL_GPIO9 0x2
> +#define VF_TAB_PAD_VAL_GPIO10 0x2
> +#define VF_TAB_PAD_VAL_GPIO11 0x2
> +#define VF_TAB_PAD_VAL_GPIO12 0x2
> +#define VF_TAB_PAD_VAL_GPIO13 0x2
> +#define VF_TAB_PAD_VAL_GPIO14 0x2
> +#define VF_TAB_PAD_VAL_GPIO15 0x2
> +#define VF_TAB_PAD_VAL_GPIO16 0x4
> +#define VF_TAB_PAD_VAL_GPIO17 0x2
> +#define VF_TAB_PAD_VAL_GPIO18 0x2
> +#define VF_TAB_PAD_VAL_GPIO19 0x2
> +#define VF_TAB_PAD_VAL_GPIO20 0x2
> +#define VF_TAB_PAD_VAL_GPIO21 0x2
> +#define VF_TAB_PAD_VAL_GPIO22 0x2
> +#define VF_TAB_PAD_VAL_GPIO23 0x2
> +#define VF_TAB_PAD_VAL_GPIO24 0x2
> +#define VF_TAB_PAD_VAL_GPIO25 0x2
> +#define VF_TAB_PAD_VAL_GPIO26 0x2
> +#define VF_TAB_PAD_VAL_GPIO27 0x2
> +#define VF_TAB_PAD_VAL_GPIO28 0x2
> +#define VF_TAB_PAD_VAL_GPIO29 0x2
> +#define VF_TAB_PAD_VAL_GPIO30 0x2
> +#define VF_TAB_PAD_VAL_GPIO31 0x2
> +#define VF_TAB_PAD_VAL_GPIO32 0x2
> +#define VF_TAB_PAD_VAL_GPIO33 0x2
> +#define VF_TAB_PAD_VAL_GPIO34 0x2
> +#define VF_TAB_PAD_VAL_GPIO35 0x2
> +#define VF_TAB_PAD_VAL_GPIO36 0x2
> +#define VF_TAB_PAD_VAL_GPIO37 0x2
> +#define VF_TAB_PAD_VAL_GPIO38 0x2
> +#define VF_TAB_PAD_VAL_GPIO39 0x2
> +#define VF_TAB_PAD_VAL_GPIO40 0x2
> +#define VF_TAB_PAD_VAL_GPIO41 0x2
> +#define VF_TAB_PAD_VAL_GPIO42 0x2
> +#define VF_TAB_PAD_VAL_GPIO43 0x2
> +#define VF_TAB_PAD_VAL_GPIO44 0x2
> +#define VF_TAB_PAD_VAL_GPIO45 0x2
> +#define VF_TAB_PAD_VAL_GPIO46 0x2
> +#define VF_TAB_PAD_VAL_GPIO47 0x2
> +#define VF_TAB_PAD_VAL_GPIO48 0x2
> +#define VF_TAB_PAD_VAL_GPIO49 0x2
> +#define VF_TAB_PAD_VAL_GPIO50 0x2
> +#define VF_TAB_PAD_VAL_GPIO51 0x2
> +#define VF_TAB_PAD_VAL_GPIO52 0x2
> +#define VF_TAB_PAD_VAL_GPIO53 0x2
> +#define VF_TAB_PAD_VAL_GPIO54 0x2
> +#define VF_TAB_PAD_VAL_GPIO55 0x2
> +#define VF_TAB_PAD_VAL_GPIO56 0x2
> +#define VF_TAB_PAD_VAL_GPIO57 0x2
> +#define VF_TAB_PAD_VAL_GPIO58 0x2
> +#define VF_TAB_PAD_VAL_GPIO59 0x2
> +#define VF_TAB_PAD_VAL_GPIO60 0x2
> +#define VF_TAB_PAD_VAL_GPIO61 0x4
> +#define VF_TAB_PAD_VAL_GPIO62 0x2
> +#define VF_TAB_PAD_VAL_GPIO63 0x2
> +#define VF_TAB_PAD_VAL_GPIO64 0x2
> +#define VF_TAB_PAD_VAL_GPIO65 0x2
> +#define VF_TAB_PAD_VAL_GPIO66 0x2
> +#define VF_TAB_PAD_VAL_GPIO67 0x0
> +#define VF_TAB_PAD_VAL_GPIO68 0x2
> +#define VF_TAB_PAD_VAL_GPIO69 0x4
> +#define VF_TAB_PAD_VAL_GPIO70 0x2
> +
> +
> +//
> +// PAD_DFT
> +//
> +#define VF_TAB_PAD_DFT_GPIO0 0xC
> +#define VF_TAB_PAD_DFT_GPIO1 0xC
> +#define VF_TAB_PAD_DFT_GPIO2 0xC
> +#define VF_TAB_PAD_DFT_GPIO3 0xC
> +#define VF_TAB_PAD_DFT_GPIO4 0xC
> +#define VF_TAB_PAD_DFT_GPIO5 0xC
> +#define VF_TAB_PAD_DFT_GPIO6 0xC
> +#define VF_TAB_PAD_DFT_GPIO7 0xC
> +#define VF_TAB_PAD_DFT_GPIO8 0xC
> +#define VF_TAB_PAD_DFT_GPIO9 0xC
> +#define VF_TAB_PAD_DFT_GPIO10 0xC
> +#define VF_TAB_PAD_DFT_GPIO11 0xC
> +#define VF_TAB_PAD_DFT_GPIO12 0xC
> +#define VF_TAB_PAD_DFT_GPIO13 0xC
> +#define VF_TAB_PAD_DFT_GPIO14 0xC
> +#define VF_TAB_PAD_DFT_GPIO15 0xC
> +#define VF_TAB_PAD_DFT_GPIO16 0xC
> +#define VF_TAB_PAD_DFT_GPIO17 0xC
> +#define VF_TAB_PAD_DFT_GPIO18 0xC
> +#define VF_TAB_PAD_DFT_GPIO19 0xC
> +#define VF_TAB_PAD_DFT_GPIO20 0xC
> +#define VF_TAB_PAD_DFT_GPIO21 0xC
> +#define VF_TAB_PAD_DFT_GPIO22 0xC
> +#define VF_TAB_PAD_DFT_GPIO23 0xC
> +#define VF_TAB_PAD_DFT_GPIO24 0xC
> +#define VF_TAB_PAD_DFT_GPIO25 0xC
> +#define VF_TAB_PAD_DFT_GPIO26 0xC
> +#define VF_TAB_PAD_DFT_GPIO27 0xC
> +#define VF_TAB_PAD_DFT_GPIO28 0xC
> +#define VF_TAB_PAD_DFT_GPIO29 0xC
> +#define VF_TAB_PAD_DFT_GPIO30 0xC
> +#define VF_TAB_PAD_DFT_GPIO31 0xC
> +#define VF_TAB_PAD_DFT_GPIO32 0xC
> +#define VF_TAB_PAD_DFT_GPIO33 0xC
> +#define VF_TAB_PAD_DFT_GPIO34 0xC
> +#define VF_TAB_PAD_DFT_GPIO35 0xC
> +#define VF_TAB_PAD_DFT_GPIO36 0xC
> +#define VF_TAB_PAD_DFT_GPIO37 0xC
> +#define VF_TAB_PAD_DFT_GPIO38 0xC
> +#define VF_TAB_PAD_DFT_GPIO39 0xC
> +#define VF_TAB_PAD_DFT_GPIO40 0xC
> +#define VF_TAB_PAD_DFT_GPIO41 0xC
> +#define VF_TAB_PAD_DFT_GPIO42 0xC
> +#define VF_TAB_PAD_DFT_GPIO43 0xC
> +#define VF_TAB_PAD_DFT_GPIO44 0xC
> +#define VF_TAB_PAD_DFT_GPIO45 0xC
> +#define VF_TAB_PAD_DFT_GPIO46 0xC
> +#define VF_TAB_PAD_DFT_GPIO47 0xC
> +#define VF_TAB_PAD_DFT_GPIO48 0xC
> +#define VF_TAB_PAD_DFT_GPIO49 0xC
> +#define VF_TAB_PAD_DFT_GPIO50 0xC
> +#define VF_TAB_PAD_DFT_GPIO51 0xC
> +#define VF_TAB_PAD_DFT_GPIO52 0xC
> +#define VF_TAB_PAD_DFT_GPIO53 0xC
> +#define VF_TAB_PAD_DFT_GPIO54 0xC
> +#define VF_TAB_PAD_DFT_GPIO55 0xC
> +#define VF_TAB_PAD_DFT_GPIO56 0xC
> +#define VF_TAB_PAD_DFT_GPIO57 0xC
> +#define VF_TAB_PAD_DFT_GPIO58 0xC
> +#define VF_TAB_PAD_DFT_GPIO59 0xC
> +#define VF_TAB_PAD_DFT_GPIO60 0xC
> +#define VF_TAB_PAD_DFT_GPIO61 0xC
> +#define VF_TAB_PAD_DFT_GPIO62 0xC
> +#define VF_TAB_PAD_DFT_GPIO63 0xC
> +#define VF_TAB_PAD_DFT_GPIO64 0xC
> +#define VF_TAB_PAD_DFT_GPIO65 0xC
> +#define VF_TAB_PAD_DFT_GPIO66 0xC
> +#define VF_TAB_PAD_DFT_GPIO67 0xC
> +#define VF_TAB_PAD_DFT_GPIO68 0xC
> +#define VF_TAB_PAD_DFT_GPIO69 0xC
> +#define VF_TAB_PAD_DFT_GPIO70 0xC
> +
> +
> +//
> +//SUS WELL
> +//
> +
> +//
> +// CONF0
> +//
> +#define VF_TAB_PAD_CONF0_GPIO_SUS0 0xCCA8
> +#define VF_TAB_PAD_CONF0_GPIO_SUS1 0xCCA8
> +#define VF_TAB_PAD_CONF0_GPIO_SUS2 0xCCA8
> +#define VF_TAB_PAD_CONF0_GPIO_SUS3 0xCD28
> +#define VF_TAB_PAD_CONF0_GPIO_SUS4 0xCD28
> +#define VF_TAB_PAD_CONF0_GPIO_SUS5 0xCD28
> +#define VF_TAB_PAD_CONF0_GPIO_SUS6 0x8850
> +#define VF_TAB_PAD_CONF0_GPIO_SUS7 0x8850
> +#define VF_TAB_PAD_CONF0_GPIO_SUS8 0xCCA8
> +#define VF_TAB_PAD_CONF0_GPIO_SUS9 0xCCA8
> +#define VF_TAB_PAD_CONF0_GPIO_SUS10 0xCCA8
> +#define VF_TAB_PAD_CONF0_GPIO_SUS11 0xC828
> +#define VF_TAB_PAD_CONF0_GPIO_SUS12 0xC828
> +#define VF_TAB_PAD_CONF0_GPIO_SUS13 0xCCA8
> +#define VF_TAB_PAD_CONF0_GPIO_SUS14 0xCCA8
> +#define VF_TAB_PAD_CONF0_GPIO_SUS15 0x8C80
> +#define VF_TAB_PAD_CONF0_GPIO_SUS16 0xC828
> +
> +//
> +// CONF1
> +//
> +#define VF_TAB_PAD_CONF1_GPIO_SUS0 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS1 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS2 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS3 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS4 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS5 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS6 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS7 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS8 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS9 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS10 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS11 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS12 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS13 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS14 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS15 0
> +#define VF_TAB_PAD_CONF1_GPIO_SUS16 0
> +
> +//
> +// PAD_VAL
> +//
> +#define VF_TAB_PAD_VAL_GPIO_SUS0 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS1 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS2 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS3 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS4 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS5 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS6 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS7 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS8 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS9 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS10 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS11 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS12 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS13 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS14 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS15 0
> +#define VF_TAB_PAD_VAL_GPIO_SUS16 0
> +
> +//
> +// PAD_DFT
> +//
> +#define VF_TAB_PAD_DFT_GPIO_SUS0 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS1 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS2 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS3 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS4 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS5 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS6 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS7 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS8 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS9 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS10 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS11 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS12 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS13 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS14 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS15 0
> +#define VF_TAB_PAD_DFT_GPIO_SUS16 0
> +
> +
> +//
> +//
> +// GPIO Register Settings for ValleyFalls (Netbook)
> +//
> +//
> +// IO Space configyuration registers
> +// Field Descriptions:
> +// USE: Defines the pin's usage model: GPIO (G) or Native (N) mode.
> +// I/O: Defines whether GPIOs are inputs (I) or outputs (O).
> +// (Note: Only meaningful for pins used as GPIOs.)
> +// LVL: This field gives you the initial value for "output" GPIO's.
> +// (Note: The output level is dependent upon whether the pin is
> inverted.)
> +// TPE: Defines whether Trigger Positive Edge Enable.
> +// TNE: Defines whether Trigger Negative Edge Enable.
> +// WAKE_EN: only support in SUS community
> +// (Note: Only affects the level sent to the GPE logic and does not
> +// affect the level read through the GPIO registers.)
> +//
> +//
> +// Memory spcae configuration registers
> +//
> +// Field Descriptions:
> +// PAD releated:
> +// PAD_CONF0
> +// PAD_CONF1
> +// PAD_VAL
> +// PAD_DFT
> +//
> +// Notes:
> +// 1. N = Native , G = GPIO , I = Input, O = Output, - = BOTH/NOT SURE
> +//
> +// Signal UsedAs USE I/O LVL TPE TNE PCONF0
> PCONF1 PVAL PDFT
> +// -----------------------------------------------------------------------------------------
> --------------------------------
> +// GPIO0 UART1_RXD-L N I - - - cd29h - -
> -
> +// GPIO1 UART1_TXD-0 N O - - - cd29h - -
> -
> +// *GPIO2 UART1_RTS_B-1 N I - - - cca9h - -
> -
> +// *GPIO3 UART1_CTS_B-H N O - - - cca9h -
> - -
> +
> +// GPIO4 NMI_B-H G - - - - cca9h - - -
> +// GPIO5 GPIO_D5 G - - - - cca9h - - -
> +// GPIO6 GPIO_D6 G O - - - 8d51h - - -
> +// GPIO7 GPIO_D7 G O - - - 8cd1h - - -
> +// GPIO8 GPIO_D8 G O - - - 8cd1h - - -
> +// GPIO9 GPIO_D9 G I - - - 8cd1h - - -
> +
> +// GPIO10 GPIO_D10 G O - - - 8d51h - -
> -
> +// GPIO11 GPIO_D11 G O - - - 8cd1h - - -
> +// GPIO12 GPIO_D12 G O - - - 8cd1h - - -
> +// GPIO13 GPIO_D13 G I - - - 8d51h - - -
> +
> +// GPIO14 SATA_GP0 N - - - - - - - -
> +// GPIO15 SATA_GP1-L N - - - - ccaah - - -
> +
> +// GPIO16 SATA_LEDN-OD-O N O - - - - - -
> -
> +// GPIO17 PCIE_CLKREQ0B-20K,H N I - - - cd2ah -
> - -
> +// GPIO18 PCIE_CLKREQ1B-20K,H N O - - - ccaah -
> - -
> +// GPIO19 PCIE_CLKREQ2B-20K,H N I - - - ccaah -
> - -
> +// GPIO20 PCIE_CLKREQ3B-20K,H N - - - - ccaah -
> - -
> +// GPIO21 PCIE_CLKREQ4B-20K,H N - - - - - - -
> -
> +// GPIO22 FLEX_CLK_SE0-20K,L N O - - - ccaah -
> - -
> +// GPIO23 FLEX_CLK_SE1-20K,L N - - - - - - -
> -
> +
> +// GPIO24 HDA_RSTB N O - - - 8d02h - -
> -
> +// GPIO25 HDA_SYNC N O - - - 8d02h - -
> -
> +// GPIO26 HDA_CLK N O - - - 8d02h - - -
> +// GPIO27 HDA_SDO N I - - - 8d02h - - -
> +// GPIO28 HDA_SDI0 N I - - - - - - -
> +// GPIO29 HDA_SDI1 N O - - - - - - -
> +// GPIO30 HDA_DOCKRSTB N I - - - - - - -
> +// GPIO31 HDA_DOCKENB N O - - - - - -
> -
> +
> +// GPIO32 SDMMC1_CLK N - - - - 208d51h -
> - -
> +// GPIO33 SDMMC1_D0 N - - - - 8cd1h - -
> -
> +// GPIO34 SDMMC1_D1 N - - - - 8cd1h - -
> -
> +// GPIO35 SDMMC1_D2 N - - - - 8cd1h - -
> -
> +// GPIO36 SDMMC1_D3_CD_B N - - - - 8cd1h -
> - -
> +// GPIO37 MMC1_D4_SD_WE N - - - - 8cd1h -
> - -
> +// GPIO38 MMC1_D5 N - - - - 8cd1h - -
> -
> +// GPIO39 MMC1_D6 N - - - - 8cd1h - -
> -
> +// GPIO40 MMC1_D7 N - - - - 8cd1h - -
> -
> +// GPIO41 SDMMC1_CMD N - - - - 8cd1h -
> - -
> +// GPIO42 MMC1_RESET_B N - - - - 208d51h -
> - -
> +
> +// GPIO43 SDMMC2_CLK N - - - - 208d51h -
> - -
> +// GPIO44 SDMMC2_D0 N - - - - 8cd1h - -
> -
> +// GPIO45 SDMMC2_D1 N - - - - 8cd1h - -
> -
> +// GPIO46 SDMMC2_D2 N - - - - 8cd1h - -
> -
> +// GPIO47 SDMMC2_D3_CD_B N - - - - 8cd1h -
> - -
> +// GPIO48 SDMMC2_CMD N - - - - 8cd1h -
> - -
> +
> +// GPIO49 SDMMC3_CLK N - - - - 8d51h - -
> -
> +// GPIO50 SDMMC3_D0 N - - - - 8cd1h - -
> -
> +// GPIO51 SDMMC3_D1 N - - - - 8cd1h - -
> -
> +// GPIO52 SDMMC3_D2 N - - - - 8cd1h - -
> -
> +// GPIO53 SDMMC3_D3 N - - - - 8cd1h - -
> -
> +// GPIO54 SDMMC3_CD_B N - - - - cca9h -
> - -
> +// GPIO55 SDMMC3_CMD N - - - - 8cd1h -
> - -
> +// GPIO56 SDMMC3_1P8_EN N - - - - cd29h -
> - -
> +
> +// GPIO57 LPC_AD0 N - - - - - - - -
> +// GPIO58 LPC_AD1 N - - - - - - - -
> +// GPIO59 LPC_AD2 N - - - - - - - -
> +// GPIO60 LPC_AD3 N - - - - - - - -
> +// GPIO61 LPC_FRAMEB N O - - - - - - -
> +// GPIO62 LPC_CLKOUT0 N O - - - - - - -
> +// GPIO63 LPC_CLKOUT1 N O - - - - - - -
> +// GPIO64 LPC_CLKRUNB N - - - - - - - -
> +
> +// GPIO65 SMB_DATA N - - - - - - - -
> +// GPIO66 SMB_CLK N - - - - - - - -
> +// GPIO67 SMB_ALERTB N - - - - - - - -
> +
> +// GPIO68 ILB_SEIRQ N - - - - - - - -
> +// GPIO69 SPKR N O - - - - - - -
> +
> +//SUS WELL
> +
> +
> +//GPIO_SUS0 GPIO_SUS0 N O - - - CCA8h -
> - -
> +//GPIO_SUS1 GPIO_SUS1 N O - - - CCA8h -
> - -
> +//GPIO_SUS2 GPIO_SUS2 N O - - - CCA8h -
> - -
> +//GPIO_SUS3 GPIO_SUS3 N O - - - CD28h -
> - -
> +//GPIO_SUS4 GPIO_SUS4 N O - - - CD28h -
> - -
> +//GPIO_SUS5 GPIO_SUS5 N O - - - CD28h -
> - -
> +//GPIO_SUS6 SUSPWRDNACK-0 N O - - - 8850h
> - - -
> +//GPIO_SUS7 PMU_SLP_DDRVTT_B-0 N O - - -
> 8850h - - -
> +//GPIO_SUS8 PMU_WAKE_B-20K,H N O - - -
> CCA8h - - -
> +//GPIO_SUS9 PMU_PWRBTN_B-20K,H N O - - -
> CCA8h - - -
> +//GPIO_SUS10 PMU_WAKE_LAN_B-20K,H N O - - -
> CCA8h - - -
> +//GPIO_SUS11 SUS_STAT_B-1 N O - - - C828h
> - - -
> +//GPIO_SUS12 PMU_SUSCLK-0 N O - - - C828h
> - - -
> +//GPIO_SUS13 USB_OC0_B-20K,H N O - - - CCA8h
> - - -
> +//GPIO_SUS14 USB_OC1_B-20K,H N O - - - CCA8h
> - - -
> +//GPIO_SUS15 SPI_CS1_B-20K,H N O - - - 8C80h
> - - -
> +//GPIO_SUS16 SPI_CS1_B-20K,H N O - - - C828h
> - - -
> +//
> +
> +#define VF_NET_GPIO_USE_SEL_VAL_0_31 0x00000000
> +#define VF_NET_GPIO_USE_SEL_VAL_32_63 0x00000000
> +#define VF_NET_GPIO_USE_SEL_VAL_64_70 0x00000000
> +#define VF_NET_GPIO_USE_SEL_VAL_SUS 0x00000000
> +
> +//
> +//1010 --00 0100 01-- 0101 --0- 0001 1010
> +//
> +#define VF_NET_GPIO_IO_SEL_VAL_0_31 0x00000000 // BIT30 | BIT28 |
> BIT27 | BIT19 | BIT17 | BIT13 | BIT9 | BIT2 | BIT0
> +#define VF_NET_GPIO_IO_SEL_VAL_32_63 0x00000000
> +#define VF_NET_GPIO_IO_SEL_VAL_64_70 0x00000000
> +#define VF_NET_GPIO_IO_SEL_VAL_SUS 0x00000000
> +
> +
> +#define VF_NET_GPIO_LVL_VAL_0_31 0x00000000
> +#define VF_NET_GPIO_LVL_VAL_32_63 0x00000000
> +#define VF_NET_GPIO_LVL_VAL_64_70 0x00000000
> +#define VF_NET_GPIO_LVL_VAL_SUS 0x00000000
> +
> +#define VF_NET_GPIO_TPE_VAL_0_31 0x00000000
> +#define VF_NET_GPIO_TPE_VAL_SUS 0x00000000
> +
> +#define VF_NET_GPIO_TNE_VAL_0_31 0x00000000
> +#define VF_NET_GPIO_TNE_VAL_SUS 0x00000000
> +
> +#define VF_NET_GPIO_TS_VAL_0_31 0x00000000
> +#define VF_NET_GPIO_TS_VAL_SUS 0x00000000
> +
> +
> +//
> +// Memory space registers
> +//
> +
> +
> +//
> +// CONF0
> +//
> +#define VF_NET_PAD_CONF0_GPIO0 0xcd29
> +#define VF_NET_PAD_CONF0_GPIO1 0xcd29
> +#define VF_NET_PAD_CONF0_GPIO2 0xcca9
> +#define VF_NET_PAD_CONF0_GPIO3 0xcca9
> +#define VF_NET_PAD_CONF0_GPIO4 0xcca8
> +#define VF_NET_PAD_CONF0_GPIO5 0xcca8
> +#define VF_NET_PAD_CONF0_GPIO6 0x8d50
> +#define VF_NET_PAD_CONF0_GPIO7 0x8cd0
> +#define VF_NET_PAD_CONF0_GPIO8 0x8cd0
> +#define VF_NET_PAD_CONF0_GPIO9 0x8cd0
> +#define VF_NET_PAD_CONF0_GPIO10 0x8d50
> +#define VF_NET_PAD_CONF0_GPIO11 0x8cd0
> +#define VF_NET_PAD_CONF0_GPIO12 0x8cd0
> +#define VF_NET_PAD_CONF0_GPIO13 0x8d50
> +#define VF_NET_PAD_CONF0_GPIO14 0xCCA8
> +#define VF_NET_PAD_CONF0_GPIO15 0xccaa
> +#define VF_NET_PAD_CONF0_GPIO16 0xC828
> +#define VF_NET_PAD_CONF0_GPIO17 0xcd2a
> +#define VF_NET_PAD_CONF0_GPIO18 0xccaa
> +#define VF_NET_PAD_CONF0_GPIO19 0xccaa
> +#define VF_NET_PAD_CONF0_GPIO20 0xccaa
> +#define VF_NET_PAD_CONF0_GPIO21 0xCCA9
> +#define VF_NET_PAD_CONF0_GPIO22 0xccaa
> +#define VF_NET_PAD_CONF0_GPIO23 0xCD2A
> +#define VF_NET_PAD_CONF0_GPIO24 0x8d02
> +#define VF_NET_PAD_CONF0_GPIO25 0x8d02
> +#define VF_NET_PAD_CONF0_GPIO26 0x8d02
> +#define VF_NET_PAD_CONF0_GPIO27 0x8d02
> +#define VF_NET_PAD_CONF0_GPIO28 0x8D02
> +#define VF_NET_PAD_CONF0_GPIO29 0x8D02
> +#define VF_NET_PAD_CONF0_GPIO30 0x8D00
> +#define VF_NET_PAD_CONF0_GPIO31 0xCD2A
> +#define VF_NET_PAD_CONF0_GPIO32 0x208d51
> +#define VF_NET_PAD_CONF0_GPIO33 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO34 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO35 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO36 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO37 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO38 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO39 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO40 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO41 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO42 0x208d51
> +#define VF_NET_PAD_CONF0_GPIO43 0x208d51
> +#define VF_NET_PAD_CONF0_GPIO44 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO45 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO46 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO47 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO48 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO49 0x8d51
> +#define VF_NET_PAD_CONF0_GPIO50 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO51 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO52 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO53 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO54 0xcca9
> +#define VF_NET_PAD_CONF0_GPIO55 0x8cd1
> +#define VF_NET_PAD_CONF0_GPIO56 0xcd29
> +#define VF_NET_PAD_CONF0_GPIO57 0x8C80
> +#define VF_NET_PAD_CONF0_GPIO58 0x8C80
> +#define VF_NET_PAD_CONF0_GPIO59 0x8C80
> +#define VF_NET_PAD_CONF0_GPIO60 0x8C80
> +#define VF_NET_PAD_CONF0_GPIO61 0x8800
> +#define VF_NET_PAD_CONF0_GPIO62 0x8D00
> +#define VF_NET_PAD_CONF0_GPIO63 0x8800
> +#define VF_NET_PAD_CONF0_GPIO64 0x8800
> +#define VF_NET_PAD_CONF0_GPIO65 0xC828
> +#define VF_NET_PAD_CONF0_GPIO66 0xC828
> +#define VF_NET_PAD_CONF0_GPIO67 0xC828
> +#define VF_NET_PAD_CONF0_GPIO68 0xCCA8
> +#define VF_NET_PAD_CONF0_GPIO69 0xC828
> +#define VF_NET_PAD_CONF0_GPIO70 0xCCA8
> +
> +
> +
> +
> +//
> +// PAD_CONF1
> +//
> +#define VF_NET_PAD_CONF1_GPIO0 0x20002
> +#define VF_NET_PAD_CONF1_GPIO1 0x20002
> +#define VF_NET_PAD_CONF1_GPIO2 0x20002
> +#define VF_NET_PAD_CONF1_GPIO3 0x20002
> +#define VF_NET_PAD_CONF1_GPIO4 0x20002
> +#define VF_NET_PAD_CONF1_GPIO5 0x20002
> +#define VF_NET_PAD_CONF1_GPIO6 0x1F000F
> +#define VF_NET_PAD_CONF1_GPIO7 0x1F000F
> +#define VF_NET_PAD_CONF1_GPIO8 0x1F000F
> +#define VF_NET_PAD_CONF1_GPIO9 0x1F000F
> +#define VF_NET_PAD_CONF1_GPIO10 0x1F000F
> +#define VF_NET_PAD_CONF1_GPIO11 0x1F000F
> +#define VF_NET_PAD_CONF1_GPIO12 0x1F000F
> +#define VF_NET_PAD_CONF1_GPIO13 0x1F000F
> +#define VF_NET_PAD_CONF1_GPIO14 0x20002
> +#define VF_NET_PAD_CONF1_GPIO15 0x20002
> +#define VF_NET_PAD_CONF1_GPIO16 0x20002
> +#define VF_NET_PAD_CONF1_GPIO17 0x20002
> +#define VF_NET_PAD_CONF1_GPIO18 0x20002
> +#define VF_NET_PAD_CONF1_GPIO19 0x20002
> +#define VF_NET_PAD_CONF1_GPIO20 0x20002
> +#define VF_NET_PAD_CONF1_GPIO21 0x20002
> +#define VF_NET_PAD_CONF1_GPIO22 0x20002
> +#define VF_NET_PAD_CONF1_GPIO23 0x20002
> +#define VF_NET_PAD_CONF1_GPIO24 0x00000
> +#define VF_NET_PAD_CONF1_GPIO25 0x00000
> +#define VF_NET_PAD_CONF1_GPIO26 0x00000
> +#define VF_NET_PAD_CONF1_GPIO27 0x00000
> +#define VF_NET_PAD_CONF1_GPIO28 0x00000
> +#define VF_NET_PAD_CONF1_GPIO29 0x00000
> +#define VF_NET_PAD_CONF1_GPIO30 0x00000
> +#define VF_NET_PAD_CONF1_GPIO31 0x20002
> +#define VF_NET_PAD_CONF1_GPIO32 0x00000
> +#define VF_NET_PAD_CONF1_GPIO33 0x00000
> +#define VF_NET_PAD_CONF1_GPIO34 0x00000
> +#define VF_NET_PAD_CONF1_GPIO35 0x00000
> +#define VF_NET_PAD_CONF1_GPIO36 0x00000
> +#define VF_NET_PAD_CONF1_GPIO37 0x00000
> +#define VF_NET_PAD_CONF1_GPIO38 0x00000
> +#define VF_NET_PAD_CONF1_GPIO39 0x00000
> +#define VF_NET_PAD_CONF1_GPIO40 0x00000
> +#define VF_NET_PAD_CONF1_GPIO41 0x00000
> +#define VF_NET_PAD_CONF1_GPIO42 0x00000
> +#define VF_NET_PAD_CONF1_GPIO43 0x00000
> +#define VF_NET_PAD_CONF1_GPIO44 0x00000
> +#define VF_NET_PAD_CONF1_GPIO45 0x00000
> +#define VF_NET_PAD_CONF1_GPIO46 0x00000
> +#define VF_NET_PAD_CONF1_GPIO47 0x00000
> +#define VF_NET_PAD_CONF1_GPIO48 0x00000
> +#define VF_NET_PAD_CONF1_GPIO49 0x00000
> +#define VF_NET_PAD_CONF1_GPIO50 0x00000
> +#define VF_NET_PAD_CONF1_GPIO51 0x00000
> +#define VF_NET_PAD_CONF1_GPIO52 0x00000
> +#define VF_NET_PAD_CONF1_GPIO53 0x00000
> +#define VF_NET_PAD_CONF1_GPIO54 0x20002
> +#define VF_NET_PAD_CONF1_GPIO55 0x00000
> +#define VF_NET_PAD_CONF1_GPIO56 0x20002
> +#define VF_NET_PAD_CONF1_GPIO57 0x00000
> +#define VF_NET_PAD_CONF1_GPIO58 0x00000
> +#define VF_NET_PAD_CONF1_GPIO59 0x00000
> +#define VF_NET_PAD_CONF1_GPIO60 0x00000
> +#define VF_NET_PAD_CONF1_GPIO61 0x00000
> +#define VF_NET_PAD_CONF1_GPIO62 0x00000
> +#define VF_NET_PAD_CONF1_GPIO63 0x00000
> +#define VF_NET_PAD_CONF1_GPIO64 0x00000
> +#define VF_NET_PAD_CONF1_GPIO65 0x20002
> +#define VF_NET_PAD_CONF1_GPIO66 0x20002
> +#define VF_NET_PAD_CONF1_GPIO67 0x20002
> +#define VF_NET_PAD_CONF1_GPIO68 0x20002
> +#define VF_NET_PAD_CONF1_GPIO69 0x20002
> +#define VF_NET_PAD_CONF1_GPIO70 0x20002
> +
> +
> +
> +//
> +// PAD_VAL
> +//
> +#define VF_NET_PAD_VAL_GPIO0 0x2
> +#define VF_NET_PAD_VAL_GPIO1 0x2
> +#define VF_NET_PAD_VAL_GPIO2 0x2
> +#define VF_NET_PAD_VAL_GPIO3 0x2
> +#define VF_NET_PAD_VAL_GPIO4 0x2
> +#define VF_NET_PAD_VAL_GPIO5 0x2
> +#define VF_NET_PAD_VAL_GPIO6 0x2
> +#define VF_NET_PAD_VAL_GPIO7 0x2
> +#define VF_NET_PAD_VAL_GPIO8 0x2
> +#define VF_NET_PAD_VAL_GPIO9 0x2
> +#define VF_NET_PAD_VAL_GPIO10 0x2
> +#define VF_NET_PAD_VAL_GPIO11 0x2
> +#define VF_NET_PAD_VAL_GPIO12 0x2
> +#define VF_NET_PAD_VAL_GPIO13 0x2
> +#define VF_NET_PAD_VAL_GPIO14 0x2
> +#define VF_NET_PAD_VAL_GPIO15 0x2
> +#define VF_NET_PAD_VAL_GPIO16 0x4
> +#define VF_NET_PAD_VAL_GPIO17 0x2
> +#define VF_NET_PAD_VAL_GPIO18 0x2
> +#define VF_NET_PAD_VAL_GPIO19 0x2
> +#define VF_NET_PAD_VAL_GPIO20 0x2
> +#define VF_NET_PAD_VAL_GPIO21 0x2
> +#define VF_NET_PAD_VAL_GPIO22 0x2
> +#define VF_NET_PAD_VAL_GPIO23 0x2
> +#define VF_NET_PAD_VAL_GPIO24 0x2
> +#define VF_NET_PAD_VAL_GPIO25 0x2
> +#define VF_NET_PAD_VAL_GPIO26 0x2
> +#define VF_NET_PAD_VAL_GPIO27 0x2
> +#define VF_NET_PAD_VAL_GPIO28 0x2
> +#define VF_NET_PAD_VAL_GPIO29 0x2
> +#define VF_NET_PAD_VAL_GPIO30 0x2
> +#define VF_NET_PAD_VAL_GPIO31 0x2
> +#define VF_NET_PAD_VAL_GPIO32 0x2
> +#define VF_NET_PAD_VAL_GPIO33 0x2
> +#define VF_NET_PAD_VAL_GPIO34 0x2
> +#define VF_NET_PAD_VAL_GPIO35 0x2
> +#define VF_NET_PAD_VAL_GPIO36 0x2
> +#define VF_NET_PAD_VAL_GPIO37 0x2
> +#define VF_NET_PAD_VAL_GPIO38 0x2
> +#define VF_NET_PAD_VAL_GPIO39 0x2
> +#define VF_NET_PAD_VAL_GPIO40 0x2
> +#define VF_NET_PAD_VAL_GPIO41 0x2
> +#define VF_NET_PAD_VAL_GPIO42 0x2
> +#define VF_NET_PAD_VAL_GPIO43 0x2
> +#define VF_NET_PAD_VAL_GPIO44 0x2
> +#define VF_NET_PAD_VAL_GPIO45 0x2
> +#define VF_NET_PAD_VAL_GPIO46 0x2
> +#define VF_NET_PAD_VAL_GPIO47 0x2
> +#define VF_NET_PAD_VAL_GPIO48 0x2
> +#define VF_NET_PAD_VAL_GPIO49 0x2
> +#define VF_NET_PAD_VAL_GPIO50 0x2
> +#define VF_NET_PAD_VAL_GPIO51 0x2
> +#define VF_NET_PAD_VAL_GPIO52 0x2
> +#define VF_NET_PAD_VAL_GPIO53 0x2
> +#define VF_NET_PAD_VAL_GPIO54 0x2
> +#define VF_NET_PAD_VAL_GPIO55 0x2
> +#define VF_NET_PAD_VAL_GPIO56 0x2
> +#define VF_NET_PAD_VAL_GPIO57 0x2
> +#define VF_NET_PAD_VAL_GPIO58 0x2
> +#define VF_NET_PAD_VAL_GPIO59 0x2
> +#define VF_NET_PAD_VAL_GPIO60 0x2
> +#define VF_NET_PAD_VAL_GPIO61 0x4
> +#define VF_NET_PAD_VAL_GPIO62 0x2
> +#define VF_NET_PAD_VAL_GPIO63 0x2
> +#define VF_NET_PAD_VAL_GPIO64 0x2
> +#define VF_NET_PAD_VAL_GPIO65 0x2
> +#define VF_NET_PAD_VAL_GPIO66 0x2
> +#define VF_NET_PAD_VAL_GPIO67 0x0
> +#define VF_NET_PAD_VAL_GPIO68 0x2
> +#define VF_NET_PAD_VAL_GPIO69 0x4
> +#define VF_NET_PAD_VAL_GPIO70 0x2
> +
> +
> +//
> +// PAD_DFT
> +//
> +#define VF_NET_PAD_DFT_GPIO0 0xC
> +#define VF_NET_PAD_DFT_GPIO1 0xC
> +#define VF_NET_PAD_DFT_GPIO2 0xC
> +#define VF_NET_PAD_DFT_GPIO3 0xC
> +#define VF_NET_PAD_DFT_GPIO4 0xC
> +#define VF_NET_PAD_DFT_GPIO5 0xC
> +#define VF_NET_PAD_DFT_GPIO6 0xC
> +#define VF_NET_PAD_DFT_GPIO7 0xC
> +#define VF_NET_PAD_DFT_GPIO8 0xC
> +#define VF_NET_PAD_DFT_GPIO9 0xC
> +#define VF_NET_PAD_DFT_GPIO10 0xC
> +#define VF_NET_PAD_DFT_GPIO11 0xC
> +#define VF_NET_PAD_DFT_GPIO12 0xC
> +#define VF_NET_PAD_DFT_GPIO13 0xC
> +#define VF_NET_PAD_DFT_GPIO14 0xC
> +#define VF_NET_PAD_DFT_GPIO15 0xC
> +#define VF_NET_PAD_DFT_GPIO16 0xC
> +#define VF_NET_PAD_DFT_GPIO17 0xC
> +#define VF_NET_PAD_DFT_GPIO18 0xC
> +#define VF_NET_PAD_DFT_GPIO19 0xC
> +#define VF_NET_PAD_DFT_GPIO20 0xC
> +#define VF_NET_PAD_DFT_GPIO21 0xC
> +#define VF_NET_PAD_DFT_GPIO22 0xC
> +#define VF_NET_PAD_DFT_GPIO23 0xC
> +#define VF_NET_PAD_DFT_GPIO24 0xC
> +#define VF_NET_PAD_DFT_GPIO25 0xC
> +#define VF_NET_PAD_DFT_GPIO26 0xC
> +#define VF_NET_PAD_DFT_GPIO27 0xC
> +#define VF_NET_PAD_DFT_GPIO28 0xC
> +#define VF_NET_PAD_DFT_GPIO29 0xC
> +#define VF_NET_PAD_DFT_GPIO30 0xC
> +#define VF_NET_PAD_DFT_GPIO31 0xC
> +#define VF_NET_PAD_DFT_GPIO32 0xC
> +#define VF_NET_PAD_DFT_GPIO33 0xC
> +#define VF_NET_PAD_DFT_GPIO34 0xC
> +#define VF_NET_PAD_DFT_GPIO35 0xC
> +#define VF_NET_PAD_DFT_GPIO36 0xC
> +#define VF_NET_PAD_DFT_GPIO37 0xC
> +#define VF_NET_PAD_DFT_GPIO38 0xC
> +#define VF_NET_PAD_DFT_GPIO39 0xC
> +#define VF_NET_PAD_DFT_GPIO40 0xC
> +#define VF_NET_PAD_DFT_GPIO41 0xC
> +#define VF_NET_PAD_DFT_GPIO42 0xC
> +#define VF_NET_PAD_DFT_GPIO43 0xC
> +#define VF_NET_PAD_DFT_GPIO44 0xC
> +#define VF_NET_PAD_DFT_GPIO45 0xC
> +#define VF_NET_PAD_DFT_GPIO46 0xC
> +#define VF_NET_PAD_DFT_GPIO47 0xC
> +#define VF_NET_PAD_DFT_GPIO48 0xC
> +#define VF_NET_PAD_DFT_GPIO49 0xC
> +#define VF_NET_PAD_DFT_GPIO50 0xC
> +#define VF_NET_PAD_DFT_GPIO51 0xC
> +#define VF_NET_PAD_DFT_GPIO52 0xC
> +#define VF_NET_PAD_DFT_GPIO53 0xC
> +#define VF_NET_PAD_DFT_GPIO54 0xC
> +#define VF_NET_PAD_DFT_GPIO55 0xC
> +#define VF_NET_PAD_DFT_GPIO56 0xC
> +#define VF_NET_PAD_DFT_GPIO57 0xC
> +#define VF_NET_PAD_DFT_GPIO58 0xC
> +#define VF_NET_PAD_DFT_GPIO59 0xC
> +#define VF_NET_PAD_DFT_GPIO60 0xC
> +#define VF_NET_PAD_DFT_GPIO61 0xC
> +#define VF_NET_PAD_DFT_GPIO62 0xC
> +#define VF_NET_PAD_DFT_GPIO63 0xC
> +#define VF_NET_PAD_DFT_GPIO64 0xC
> +#define VF_NET_PAD_DFT_GPIO65 0xC
> +#define VF_NET_PAD_DFT_GPIO66 0xC
> +#define VF_NET_PAD_DFT_GPIO67 0xC
> +#define VF_NET_PAD_DFT_GPIO68 0xC
> +#define VF_NET_PAD_DFT_GPIO69 0xC
> +#define VF_NET_PAD_DFT_GPIO70 0xC
> +
> +//
> +// PCONF0
> +//
> +#define VF_NET_PAD_CONF0_GPIO_SUS0 0xCCA8
> +#define VF_NET_PAD_CONF0_GPIO_SUS1 0xCCA8
> +#define VF_NET_PAD_CONF0_GPIO_SUS2 0xCCA8
> +#define VF_NET_PAD_CONF0_GPIO_SUS3 0xCD28
> +#define VF_NET_PAD_CONF0_GPIO_SUS4 0xCD28
> +#define VF_NET_PAD_CONF0_GPIO_SUS5 0xCD28
> +#define VF_NET_PAD_CONF0_GPIO_SUS6 0x8850
> +#define VF_NET_PAD_CONF0_GPIO_SUS7 0x8850
> +#define VF_NET_PAD_CONF0_GPIO_SUS8 0xCCA8
> +#define VF_NET_PAD_CONF0_GPIO_SUS9 0xCCA8
> +#define VF_NET_PAD_CONF0_GPIO_SUS10 0xCCA8
> +#define VF_NET_PAD_CONF0_GPIO_SUS11 0xC828
> +#define VF_NET_PAD_CONF0_GPIO_SUS12 0xC828
> +#define VF_NET_PAD_CONF0_GPIO_SUS13 0xCCA8
> +#define VF_NET_PAD_CONF0_GPIO_SUS14 0xCCA8
> +#define VF_NET_PAD_CONF0_GPIO_SUS15 0x8C80
> +#define VF_NET_PAD_CONF0_GPIO_SUS16 0xC828
> +
> +//
> +// PCONF1
> +//
> +#define VF_NET_PAD_CONF1_GPIO_SUS0 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS1 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS2 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS3 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS4 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS5 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS6 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS7 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS8 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS9 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS10 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS11 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS12 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS13 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS14 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS15 0
> +#define VF_NET_PAD_CONF1_GPIO_SUS16 0
> +
> +
> +#define VF_NET_PAD_VAL_GPIO_SUS0 0
> +#define VF_NET_PAD_VAL_GPIO_SUS1 0
> +#define VF_NET_PAD_VAL_GPIO_SUS2 0
> +#define VF_NET_PAD_VAL_GPIO_SUS3 0
> +#define VF_NET_PAD_VAL_GPIO_SUS4 0
> +#define VF_NET_PAD_VAL_GPIO_SUS5 0
> +#define VF_NET_PAD_VAL_GPIO_SUS6 0
> +#define VF_NET_PAD_VAL_GPIO_SUS7 0
> +#define VF_NET_PAD_VAL_GPIO_SUS8 0
> +#define VF_NET_PAD_VAL_GPIO_SUS9 0
> +#define VF_NET_PAD_VAL_GPIO_SUS10 0
> +#define VF_NET_PAD_VAL_GPIO_SUS11 0
> +#define VF_NET_PAD_VAL_GPIO_SUS12 0
> +#define VF_NET_PAD_VAL_GPIO_SUS13 0
> +#define VF_NET_PAD_VAL_GPIO_SUS14 0
> +#define VF_NET_PAD_VAL_GPIO_SUS15 0
> +#define VF_NET_PAD_VAL_GPIO_SUS16 0
> +
> +
> +#define VF_NET_PAD_DFT_GPIO_SUS0 0
> +#define VF_NET_PAD_DFT_GPIO_SUS1 0
> +#define VF_NET_PAD_DFT_GPIO_SUS2 0
> +#define VF_NET_PAD_DFT_GPIO_SUS3 0
> +#define VF_NET_PAD_DFT_GPIO_SUS4 0
> +#define VF_NET_PAD_DFT_GPIO_SUS5 0
> +#define VF_NET_PAD_DFT_GPIO_SUS6 0
> +#define VF_NET_PAD_DFT_GPIO_SUS7 0
> +#define VF_NET_PAD_DFT_GPIO_SUS8 0
> +#define VF_NET_PAD_DFT_GPIO_SUS9 0
> +#define VF_NET_PAD_DFT_GPIO_SUS10 0
> +#define VF_NET_PAD_DFT_GPIO_SUS11 0
> +#define VF_NET_PAD_DFT_GPIO_SUS12 0
> +#define VF_NET_PAD_DFT_GPIO_SUS13 0
> +#define VF_NET_PAD_DFT_GPIO_SUS14 0
> +#define VF_NET_PAD_DFT_GPIO_SUS15 0
> +#define VF_NET_PAD_DFT_GPIO_SUS16 0
> +
> +
> +//
> +// Function Prototypes
> +//
> +EFI_STATUS
> +PlatformPchInit (
> + IN SYSTEM_CONFIGURATION *SystemConfiguration,
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINT16 PlatformType
> + );
> +
> +EFI_STATUS
> +PlatformCpuInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration,
> + IN EFI_PLATFORM_CPU_INFO *PlatformCpuInfo
> + );
> +
> +EFI_STATUS
> +PeimInitializeFlashMap (
> + IN EFI_FFS_FILE_HEADER *FfsHeader,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +EFI_STATUS
> +PeimInstallFlashMapPpi (
> + IN EFI_FFS_FILE_HEADER *FfsHeader,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +IchReset (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +;
> +
> +BOOLEAN
> +GetSleepTypeAfterWakeup (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + OUT UINT16 *SleepType
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +GetWakeupEventAndSaveToHob (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +;
> +
> +EFI_STATUS
> +EFIAPI
> +MemoryDiscoveredPpiNotifyCallback (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> + )
> +;
> +
> +EFI_STATUS
> +EFIAPI
> +PeiGetVariable (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN CHAR16 *VariableName,
> + IN EFI_GUID * VendorGuid,
> + OUT UINT32 *Attributes OPTIONAL,
> + IN OUT UINTN *DataSize,
> + OUT VOID *Data
> + )
> +;
> +
> +EFI_STATUS
> +EFIAPI
> +PeiGetNextVariableName (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT UINTN *VariableNameSize,
> + IN OUT CHAR16 *VariableName,
> + IN OUT EFI_GUID *VendorGuid
> + )
> +;
> +
> +EFI_STATUS
> +UpdateBootMode (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +EndOfPeiPpiNotifyCallback (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +PeimInitializeRecovery (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +;
> +
> +VOID
> +CheckPowerOffNow (
> + VOID
> + );
> +
> +VOID
> +IchGpioInit (
> + IN UINT16 PlatformType,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +EFI_STATUS
> +PcieSecondaryBusReset (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN UINT8 Bus,
> + IN UINT8 Dev,
> + IN UINT8 Fun
> + );
> +
> +VOID
> +SetPlatformBootMode (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + );
> +
> +BOOLEAN
> +CheckIfJumperSetForRecovery(
> + VOID
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FindFv (
> + IN EFI_PEI_FIND_FV_PPI *This,
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT UINT8 *FvNumber,
> + OUT EFI_FIRMWARE_VOLUME_HEADER **FVAddress
> + );
> +
> +BOOLEAN
> +IsA16Inverted (
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +CpuOnlyReset (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +InitLan (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *Buffer
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +Stall (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN CONST EFI_PEI_STALL_PPI *This,
> + IN UINTN Microseconds
> + );
> +
> +EFI_STATUS
> +MultiPlatformInfoInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + );
> +
> +BOOLEAN
> +IsRecoveryJumper (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> +);
> +
> +EFI_STATUS
> +CheckOsSelection (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +EFI_STATUS
> +PlatformInfoUpdate (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + );
> +
> +VOID
> +PlatformSsaInit (
> +IN SYSTEM_CONFIGURATION *SystemConfiguration,
> +IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +EFI_STATUS
> +InitializePlatform (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> +);
> +
> +VOID
> +MchInit (
> +IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +
> +EFI_STATUS
> +EFIAPI
> +SetPeiCacheMode (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +SetDxeCacheMode (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +EFI_STATUS
> +GPIO_initialization (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *SmbusPpi
> + );
> +
> +
> +BOOLEAN
> +IsRtcUipAlwaysSet (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +
> +
> +EFI_STATUS
> +InitPchUsb (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +PublishMemoryTypeInfo (
> + void
> + );
> +
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c
> new file mode 100644
> index 0000000000..c6948d99d5
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c
> @@ -0,0 +1,181 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + PlatformInfoInit.c
> +
> +Abstract:
> + Platform Info Driver.
> +
> +--*/
> +
> +#include "PlatformEarlyInit.h"
> +
> +#define LEN_64M 0x4000000
> +
> +//
> +// Default PCI32 resource size
> +//
> +#define RES_MEM32_MIN_LEN 0x38000000
> +
> +#define RES_IO_BASE 0x0D00
> +#define RES_IO_LIMIT 0xFFFF
> +
> +#define MemoryCeilingVariable L"MemCeil."
> +
> +EFI_STATUS
> +CheckOsSelection (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
> + UINTN VariableSize;
> + EFI_OS_SELECTION_HOB *OsSelectionHob;
> + UINT8 OsSelection;
> + UINT8 *LpssDataHobPtr;
> + UINT8 *LpssDataVarPtr;
> + UINTN i;
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (void **)&Variable
> + );
> + if (!EFI_ERROR(Status)) {
> + VariableSize = sizeof (OsSelection);
> + Status = Variable->GetVariable (
> + Variable,
> + L"OsSelection",
> + &gOsSelectionVariableGuid,
> + NULL,
> + &VariableSize,
> + &OsSelection
> + );
> +
> + if (!EFI_ERROR(Status) && (SystemConfiguration->ReservedO !=
> OsSelection)) {
> + //
> + // Build HOB for OsSelection
> + //
> + OsSelectionHob = BuildGuidHob (&gOsSelectionVariableGuid, sizeof
> (EFI_OS_SELECTION_HOB));
> + ASSERT (OsSelectionHob != NULL);
> +
> + OsSelectionHob->OsSelectionChanged = TRUE;
> + OsSelectionHob->OsSelection = OsSelection;
> + SystemConfiguration->ReservedO = OsSelectionHob->OsSelection;
> +
> + //
> + // Load LPSS and SCC default configurations
> + //
> + OsSelectionHob->LpssData.LpsseMMCEnabled = FALSE;
> + OsSelectionHob->LpssData.LpssSdioEnabled = TRUE;
> + OsSelectionHob->LpssData.LpssSdcardEnabled = TRUE;
> + OsSelectionHob->LpssData.LpssSdCardSDR25Enabled = FALSE;
> + OsSelectionHob->LpssData.LpssSdCardDDR50Enabled = TRUE;
> + OsSelectionHob->LpssData.LpssMipiHsi = FALSE;
> + OsSelectionHob->LpssData.LpsseMMC45Enabled = TRUE;
> + OsSelectionHob->LpssData.LpsseMMC45DDR50Enabled = TRUE;
> + OsSelectionHob->LpssData.LpsseMMC45HS200Enabled = FALSE;
> + OsSelectionHob->LpssData.LpsseMMC45RetuneTimerValue = 8;
> + OsSelectionHob->LpssData.eMMCBootMode = 1; // Auto
> Detect
> +
> +
> + SystemConfiguration->Lpe = OsSelectionHob->Lpe;
> + SystemConfiguration->PchAzalia = SystemConfiguration->PchAzalia;
> + LpssDataHobPtr = &OsSelectionHob->LpssData.LpssPciModeEnabled;
> + LpssDataVarPtr = &SystemConfiguration->LpssPciModeEnabled;
> +
> + for (i = 0; i < sizeof(EFI_PLATFORM_LPSS_DATA); i++) {
> + *LpssDataVarPtr = *LpssDataHobPtr;
> + LpssDataVarPtr++;
> + LpssDataHobPtr++;
> + }
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +EFI_STATUS
> +PlatformInfoUpdate (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
> + UINTN VariableSize;
> + UINT32 MemoryCeiling;
> +
> + //
> + // Checking PCI32 resource from previous boot to determine the memory
> ceiling
> + //
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (void **)&Variable
> + );
> + if (!EFI_ERROR(Status)) {
> + //
> + // Get the memory ceiling
> + //
> + VariableSize = sizeof(MemoryCeiling);
> + Status = Variable->GetVariable (
> + Variable,
> + MemoryCeilingVariable,
> + &gEfiGlobalVariableGuid,
> + NULL,
> + &VariableSize,
> + &MemoryCeiling
> + );
> + if(!EFI_ERROR(Status)) {
> + //
> + // Set the new PCI32 resource Base if the variable available
> + //
> + PlatformInfoHob->PciData.PciResourceMem32Base = MemoryCeiling;
> + PlatformInfoHob->MemData.MemMaxTolm = MemoryCeiling;
> + PlatformInfoHob->MemData.MemTolm = MemoryCeiling;
> +
> + //
> + // Platform PCI MMIO Size in unit of 1MB
> + //
> + PlatformInfoHob->MemData.MmioSize = 0x1000 -
> (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Initialize the platform related info hob according to the
> + pre-determine value or setup option
> +
> + @retval EFI_SUCCESS Memory initialization completed successfully.
> + @retval Others All other error conditions encountered result in an
> ASSERT.
> +**/
> +EFI_STATUS
> +InitializePlatform (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob,
> + IN SYSTEM_CONFIGURATION *SystemConfiguration
> +)
> +{
> +//
> +// -- cchew10 need to update here.
> +//
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf
> new file mode 100644
> index 0000000000..54277b1e8b
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf
> @@ -0,0 +1,117 @@
> +#
> +#
> +# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#
> +# Module Name:
> +#
> +# PlatformEarlyInit.inf
> +#
> +# Abstract:
> +#
> +# Component description file for PlatformEarlyInit module
> +#
> +#--*/
> +
> +[defines]
> +INF_VERSION = 0x00010005
> +BASE_NAME = PlatformEarlyInit
> +FILE_GUID = 0A5EA2E1-BE0B-44a0-
> A775-F429C9A018A0
> +MODULE_TYPE = PEIM
> +VERSION_STRING = 1.0
> +PI_SPECIFICATION_VERSION = 0x0001000A
> +ENTRY_POINT = PlatformEarlyInitEntry
> +
> +[sources.common]
> + BootMode.c
> + CpuInitPeim.c
> + PchInitPeim.c
> + MchInit.c
> + MemoryCallback.c
> + MemoryPeim.c
> + PlatformEarlyInit.c
> + PlatformEarlyInit.h
> + PlatformInfoInit.c
> + LegacySpeaker.c
> + LegacySpeaker.h
> + Stall.c
> + PlatformSsaInitPeim.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + Vlv2SocBinPkg/Vlv2SocBinPkg.dec
> + UefiCpuPkg/UefiCpuPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
> +
> +[LibraryClasses]
> + PeimEntryPoint
> + DebugLib
> + HobLib
> + IoLib
> +# PeiKscLib
> + MultiPlatformLib
> + PcdLib
> + PchPlatformLib
> + MtrrLib
> +
> +[Ppis]
> + gEfiPeiStallPpiGuid
> + gPeiSpeakerInterfacePpiGuid
> + gEfiPeiMemoryDiscoveredPpiGuid
> + gVlvPolicyPpiGuid
> + gEfiPeiReadOnlyVariable2PpiGuid
> + gEfiPeiResetPpiGuid
> + gEfiEndOfPeiSignalPpiGuid
> + gPeiSmbusPolicyPpiGuid
> + gEfiFindFvPpiGuid
> + gPeiCapsulePpiGuid
> + gEfiPeiBootInRecoveryModePpiGuid
> + gEfiPeiRecoveryModulePpiGuid
> + gEfiPeiDeviceRecoveryModulePpiGuid
> + gPeiCachePpiGuid
> + gEfiPeiMasterBootModePpiGuid
> + gEfiPeiSmbusPpiGuid
> + gPchInitPpiGuid
> + gPchUsbPolicyPpiGuid
> +
> +[Guids]
> + gEfiSetupVariableGuid
> + gEfiPlatformInfoGuid
> + gEfiPlatformBootModeGuid
> + gEfiPlatformCpuInfoGuid
> + gEfiGlobalVariableGuid
> + gRecoveryOnFatFloppyDiskGuid
> + gRecoveryOnFatUsbDiskGuid
> + gRecoveryOnFatIdeDiskGuid
> + gRecoveryOnDataCdGuid
> + gMfgModeVariableGuid
> + gEfiNormalSetupGuid
> + gEfiMemoryTypeInformationGuid
> + gOsSelectionVariableGuid
> + gEfiSmmPeiSmramMemoryReserveGuid
> +
> +[Pcd.common]
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> + gEfiIchTokenSpaceGuid.PcdPeiIchEhciControllerMemoryBaseAddress
> +
> + gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress
> + gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size
> +
> +[Pcd]
> + gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable
> + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState
> +
> +[Depex]
> + gEfiPeiReadOnlyVariable2PpiGuid AND gPeiCachePpiGuid
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c
> new file mode 100644
> index 0000000000..4ffa3a20a2
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c
> @@ -0,0 +1,58 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + PlatformSsaInitPeim.c
> +
> +Abstract:
> +
> +
> +--*/
> +
> +#include "PlatformEarlyInit.h"
> +
> +/**
> + Perform SSA related platform initialization.
> +
> +**/
> +VOID
> +PlatformSsaInit (
> + IN SYSTEM_CONFIGURATION *SystemConfiguration,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> +
> + DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Start\n"));
> + DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - SystemConfiguration-
> >ISPDevSel 0x%x\n",SystemConfiguration->ISPDevSel));
> + if(SystemConfiguration->ISPDevSel == 0x02)
> + {
> + //
> + // Device 3 Interrupt Route
> + //
> + MmioWrite16 (
> + (ILB_BASE_ADDRESS + R_PCH_ILB_D3IR),
> + V_PCH_ILB_DXXIR_IAR_PIRQH // For IUNIT
> + );
> + MmioRead16(ILB_BASE_ADDRESS + R_PCH_ILB_D3IR); // Read Posted
> Writes Register
> + DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Device 3 Interrupt Route
> Done\n"));
> + }
> +
> + //
> + // Device 2 Interrupt Route
> + //
> + MmioWrite16 (
> + (ILB_BASE_ADDRESS + R_PCH_ILB_D2IR),
> + V_PCH_ILB_DXXIR_IAR_PIRQA // For IGD
> + );
> + MmioRead16(ILB_BASE_ADDRESS + R_PCH_ILB_D2IR); // Read Posted
> Writes Register
> + DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Device 2 Interrupt Route
> Done\n"));
> +
> + return;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c
> new file mode 100644
> index 0000000000..53cd2c6c0c
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c
> @@ -0,0 +1,361 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + Recovery.c
> +
> +Abstract:
> +
> + Tiano PEIM to provide the platform recovery functionality.
> +
> +--*/
> +
> +#include "PlatformEarlyInit.h"
> +
> +#define PEI_FVMAIN_COMPACT_GUID \
> + {0x4A538818, 0x5AE0, 0x4eb2, 0xB2, 0xEB, 0x48, 0x8b, 0x23, 0x65, 0x70,
> 0x22};
> +
> +EFI_GUID FvMainCompactFileGuid = PEI_FVMAIN_COMPACT_GUID;
> +
> +//
> +// Required Service
> +//
> +EFI_STATUS
> +EFIAPI
> +PlatformRecoveryModule (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_RECOVERY_MODULE_PPI *This
> + );
> +
> +//
> +// Module globals
> +//
> +
> +typedef struct {
> + EFI_GUID CapsuleGuid;
> + UINT32 HeaderSize;
> + UINT32 Flags;
> + UINT32 CapsuleImageSize;
> + UINT32 SequenceNumber;
> + EFI_GUID InstanceId;
> + UINT32 OffsetToSplitInformation;
> + UINT32 OffsetToCapsuleBody;
> + UINT32 OffsetToOemDefinedHeader;
> + UINT32 OffsetToAuthorInformation;
> + UINT32 OffsetToRevisionInformation;
> + UINT32 OffsetToShortDescription;
> + UINT32 OffsetToLongDescription;
> + UINT32 OffsetToApplicableDevices;
> +} OLD_EFI_CAPSULE_HEADER;
> +
> +
> +static EFI_PEI_RECOVERY_MODULE_PPI mRecoveryPpi = {
> + PlatformRecoveryModule
> +};
> +
> +static EFI_PEI_PPI_DESCRIPTOR mRecoveryPpiList = {
> + (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gEfiPeiRecoveryModulePpiGuid,
> + &mRecoveryPpi
> +};
> +
> +/**
> + Provide the functionality of the Recovery Module.
> +
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval Status EFI_SUCCESS if the interface could be successfully
> + installed
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeimInitializeRecovery (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = (*PeiServices)->InstallPpi (
> + PeiServices,
> + &mRecoveryPpiList
> + );
> +
> + return Status;
> +}
> +
> +/**
> + Provide the functionality of the Ea Recovery Module.
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param This Pointer to PEI_RECOVERY_MODULE_INTERFACE.
> +
> + @retval EFI_SUCCESS If the interface could be successfully
> + installed.
> + @retval EFI_UNSUPPORTED Not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PlatformRecoveryModule (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_RECOVERY_MODULE_PPI *This
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *DeviceRecoveryModule;
> + UINTN NumberOfImageProviders;
> + BOOLEAN ProviderAvailable;
> + UINTN NumberRecoveryCapsules;
> + UINTN RecoveryCapsuleSize;
> + EFI_GUID DeviceId;
> + BOOLEAN ImageFound;
> + EFI_PHYSICAL_ADDRESS Address;
> + VOID *Buffer;
> + OLD_EFI_CAPSULE_HEADER *CapsuleHeader;
> + EFI_PEI_HOB_POINTERS Hob;
> + EFI_PEI_HOB_POINTERS HobOld;
> + EFI_HOB_CAPSULE_VOLUME *CapsuleHob;
> + BOOLEAN HobUpdate;
> + EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
> + UINTN Index;
> + BOOLEAN FoundFvMain;
> + BOOLEAN FoundCapsule;
> + static EFI_GUID mEfiCapsuleHeaderGuid = EFI_CAPSULE_GUID;
> + EFI_PEI_STALL_PPI *StallPpi;
> +
> + (*PeiServices)->ReportStatusCode (
> + PeiServices,
> + EFI_PROGRESS_CODE,
> + EFI_SOFTWARE_PEI_MODULE |
> EFI_SW_PEIM_PC_RECOVERY_BEGIN,
> + 0,
> + NULL,
> + NULL
> + );
> +
> + Status = (**PeiServices).LocatePpi (
> + PeiServices,
> + &gEfiPeiStallPpiGuid,
> + 0,
> + NULL,
> + &StallPpi
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + StallPpi->Stall(
> + PeiServices,
> + StallPpi,
> + 5000000
> + );
> +
> +
> + Index = 0;
> +
> + Status = EFI_SUCCESS;
> + HobUpdate = FALSE;
> +
> + ProviderAvailable = TRUE;
> + ImageFound = FALSE;
> + NumberOfImageProviders = 0;
> +
> + DeviceRecoveryModule = NULL;
> +
> + FoundCapsule = FALSE;
> + FoundFvMain = FALSE;
> +
> + DEBUG ((EFI_D_ERROR | EFI_D_LOAD, "Recovery Entry\n"));
> +
> + //
> + // Search the platform for some recovery capsule if the DXE IPL
> + // discovered a recovery condition and has requested a load.
> + //
> + while (ProviderAvailable == TRUE) {
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gEfiPeiDeviceRecoveryModulePpiGuid,
> + Index,
> + NULL,
> + &DeviceRecoveryModule
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Device Recovery PPI located\n"));
> + NumberOfImageProviders++;
> +
> + Status = DeviceRecoveryModule->GetNumberRecoveryCapsules (
> + (EFI_PEI_SERVICES**)PeiServices,
> + DeviceRecoveryModule,
> + &NumberRecoveryCapsules
> + );
> +
> + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Number Of Recovery
> Capsules: %d\n", NumberRecoveryCapsules));
> +
> + if (NumberRecoveryCapsules == 0) {
> + Index++;
> + } else {
> + break;
> + }
> + } else {
> + ProviderAvailable = FALSE;
> + }
> + }
> +
> + //
> + // If there is an image provider, get the capsule ID
> + //
> + if (ProviderAvailable) {
> + RecoveryCapsuleSize = 0;
> +
> + Status = DeviceRecoveryModule->GetRecoveryCapsuleInfo (
> + (EFI_PEI_SERVICES**)PeiServices,
> + DeviceRecoveryModule,
> + 0,
> + &RecoveryCapsuleSize,
> + &DeviceId
> + );
> +
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Capsule Size: %d\n",
> RecoveryCapsuleSize));
> +
> + //
> + // Only support the 2 capsule types known
> + // Future enhancement is to rank-order the selection
> + //
> + if ((!CompareGuid (&DeviceId, &gRecoveryOnFatIdeDiskGuid)) &&
> + (!CompareGuid (&DeviceId, &gRecoveryOnFatFloppyDiskGuid)) &&
> + (!CompareGuid (&DeviceId, &gRecoveryOnDataCdGuid)) &&
> + (!CompareGuid (&DeviceId, &gRecoveryOnFatUsbDiskGuid))
> + ) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + Buffer = NULL;
> + Status = (*PeiServices)->AllocatePages (
> + PeiServices,
> + EfiBootServicesCode,
> + (RecoveryCapsuleSize - 1) / 0x1000 + 1,
> + &Address
> + );
> +
> + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "AllocatePage Returns: %r\n",
> Status));
> +
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + Buffer = (UINT8 *) (UINTN) Address;
> +
> + (*PeiServices)->ReportStatusCode (
> + PeiServices,
> + EFI_PROGRESS_CODE,
> + EFI_SOFTWARE_PEI_MODULE |
> EFI_SW_PEIM_PC_CAPSULE_LOAD,
> + 0,
> + NULL,
> + NULL
> + );
> +
> + Status = DeviceRecoveryModule->LoadRecoveryCapsule (
> + (EFI_PEI_SERVICES**)PeiServices,
> + DeviceRecoveryModule,
> + 0,
> + Buffer
> + );
> +
> + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "LoadRecoveryCapsule
> Returns: %r\n", Status));
> +
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Update FV Hob if found
> + //
> + Status = (*PeiServices)->GetHobList (PeiServices, &Hob.Raw);
> + HobOld.Raw = Hob.Raw;
> + while (!END_OF_HOB_LIST (Hob)) {
> + if (Hob.Header->HobType == EFI_HOB_TYPE_FV) {
> + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob FV Length: %x\n",
> Hob.FirmwareVolume->Length));
> + //
> + // BUGBUG Why is it a FV hob if it is greater than 0x50000?
> + //
> + if (Hob.FirmwareVolume->Length > 0x50000) {
> + HobUpdate = TRUE;
> + //
> + // This looks like the Hob we are interested in
> + //
> + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob Updated\n"));
> + Hob.FirmwareVolume->BaseAddress = (UINTN) Buffer;
> + Hob.FirmwareVolume->Length = RecoveryCapsuleSize;
> + }
> + }
> + Hob.Raw = GET_NEXT_HOB (Hob);
> + }
> +
> + FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)Buffer;
> + CapsuleHeader = (OLD_EFI_CAPSULE_HEADER *)Buffer;
> +
> + //
> + // Check if top of file is a capsule
> + //
> + if (CompareGuid ((EFI_GUID *)CapsuleHeader,
> &mEfiCapsuleHeaderGuid)) {
> + FoundCapsule = TRUE;
> + } else if (FvHeader->Signature == EFI_FVH_SIGNATURE) {
> + //
> + // Assume the Firmware volume is a "FVMAIN" image
> + //
> + FoundFvMain = TRUE;
> + }
> +
> + if (FoundFvMain) {
> + //
> + // build FV Hob if it is not built before
> + //
> + if (!HobUpdate) {
> + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "FV Hob is not found, Build FV Hob
> then..\n"));
> +
> + BuildFvHob (
> + (UINTN)FvHeader,
> + FvHeader->FvLength
> + );
> + }
> + }
> +
> + if (FoundCapsule) {
> + //
> + // Build capsule hob
> + //
> + Status = (*PeiServices)->CreateHob (
> + PeiServices,
> + EFI_HOB_TYPE_CV,
> + sizeof (EFI_HOB_CAPSULE_VOLUME),
> + &CapsuleHob
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + CapsuleHob->BaseAddress = (UINT64)((UINTN)CapsuleHeader +
> (UINTN)CapsuleHeader->OffsetToCapsuleBody);
> + CapsuleHob->Length = (UINT64)((UINTN)CapsuleHeader-
> >CapsuleImageSize -(UINTN)CapsuleHeader->OffsetToCapsuleBody);
> + (*PeiServices)->ReportStatusCode (
> + PeiServices,
> + EFI_PROGRESS_CODE,
> + EFI_SOFTWARE_PEI_MODULE |
> EFI_SW_PEIM_PC_CAPSULE_START,
> + 0,
> + NULL,
> + NULL
> + );
> + }
> + }
> + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Module Returning: %r\n",
> Status));
> + return Status;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/Stall.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/Stall.c
> new file mode 100644
> index 0000000000..d9c24c0194
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformInitPei/Stall.c
> @@ -0,0 +1,91 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +Module Name:
> +
> + Stall.c
> +
> +Abstract:
> +
> + Produce Stall Ppi.
> +
> +--*/
> +
> +
> +#include "PlatformEarlyInit.h"
> +
> +
> +/**
> +
> + Waits for at least the given number of microseconds.
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param This PPI instance structure.
> + @param Microseconds Desired length of time to wait.
> +
> + @retval EFI_SUCCESS If the desired amount of time was passed.
> +
> +*/
> +EFI_STATUS
> +EFIAPI
> +Stall (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN CONST EFI_PEI_STALL_PPI *This,
> + IN UINTN Microseconds
> + )
> +{
> + UINTN Ticks;
> + UINTN Counts;
> + UINT32 CurrentTick;
> + UINT32 OriginalTick;
> + UINT32 RemainingTick;
> +
> + if (Microseconds == 0) {
> + return EFI_SUCCESS;
> + }
> +
> + OriginalTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR);
> + OriginalTick &= (V_PCH_ACPI_PM1_TMR_MAX_VAL - 1);
> + CurrentTick = OriginalTick;
> +
> + //
> + // The timer frequency is 3.579545MHz, so 1 ms corresponds to 3.58 clocks
> + //
> + Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
> +
> + //
> + // The loops needed for timer overflow
> + //
> + Counts = (UINTN)RShiftU64((UINT64)Ticks, 24);
> +
> + //
> + // Remaining clocks within one loop
> + //
> + RemainingTick = Ticks & 0xFFFFFF;
> +
> + //
> + // Do not intend to use TMROF_STS bit of register PM1_STS, because this
> add extra
> + // one I/O operation, and may generate SMI
> + //
> + while (Counts != 0) {
> + CurrentTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR)
> & B_PCH_ACPI_PM1_TMR_VAL;
> + if (CurrentTick <= OriginalTick) {
> + Counts--;
> + }
> + OriginalTick = CurrentTick;
> + }
> +
> + while ((RemainingTick > CurrentTick) && (OriginalTick <= CurrentTick)) {
> + OriginalTick = CurrentTick;
> + CurrentTick = IoRead32 (ACPI_BASE_ADDRESS +
> R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL;
> + }
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c
> new file mode 100644
> index 0000000000..9fdcb620a3
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/BootMode.c
> @@ -0,0 +1,346 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +
> + BootMode.c
> +
> +Abstract:
> +
> + EFI PEIM to provide the platform support functionality on the Thurley.
> +
> +
> +--*/
> +#include "CommonHeader.h"
> +#include "Platform.h"
> +#include "PlatformBaseAddresses.h"
> +#include "PchAccess.h"
> +#include "PlatformBootMode.h"
> +#include <Guid/SetupVariable.h>
> +
> +//
> +// Priority of our boot modes, highest priority first
> +//
> +EFI_BOOT_MODE mBootModePriority[] = {
> + BOOT_IN_RECOVERY_MODE,
> + BOOT_WITH_DEFAULT_SETTINGS,
> + BOOT_ON_FLASH_UPDATE,
> + BOOT_ON_S2_RESUME,
> + BOOT_ON_S3_RESUME,
> + BOOT_ON_S4_RESUME,
> + BOOT_WITH_MINIMAL_CONFIGURATION,
> + BOOT_ASSUMING_NO_CONFIGURATION_CHANGES,
> + BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS,
> + BOOT_WITH_FULL_CONFIGURATION,
> + BOOT_ON_S5_RESUME
> +};
> +
> +EFI_PEI_NOTIFY_DESCRIPTOR mCapsuleNotifyList[1] = {
> + {
> + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gPeiCapsulePpiGuid,
> + CapsulePpiNotifyCallback
> + }
> +};
> +
> +BOOLEAN
> +GetSleepTypeAfterWakeup (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + OUT UINT16 *SleepType
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +CapsulePpiNotifyCallback (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> + )
> +{
> + EFI_STATUS Status;
> + EFI_BOOT_MODE BootMode;
> + PEI_CAPSULE_PPI *Capsule;
> +
> + Status = (*PeiServices)->GetBootMode((const EFI_PEI_SERVICES
> **)PeiServices, &BootMode);
> + ASSERT_EFI_ERROR (Status);
> +
> + if (BootMode == BOOT_ON_S3_RESUME) {
> + //
> + // Determine if we're in capsule update mode
> + //
> + Status = (*PeiServices)->LocatePpi ((const EFI_PEI_SERVICES
> **)PeiServices,
> + &gPeiCapsulePpiGuid,
> + 0,
> + NULL,
> + (VOID **)&Capsule
> + );
> +
> + if (Status == EFI_SUCCESS) {
> + if (Capsule->CheckCapsuleUpdate ((EFI_PEI_SERVICES**)PeiServices)
> == EFI_SUCCESS) {
> + BootMode = BOOT_ON_FLASH_UPDATE;
> + Status = (*PeiServices)->SetBootMode((const EFI_PEI_SERVICES
> **)PeiServices, BootMode);
> + ASSERT_EFI_ERROR (Status);
> + }
> + }
> + }
> +
> + return Status;
> +}
> +
> +#ifdef NOCS_S3_SUPPORT
> +EFI_STATUS
> +UpdateBootMode (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> + EFI_BOOT_MODE BootMode;
> + UINT16 SleepType;
> + CHAR16 *strBootMode;
> +
> + Status = (*PeiServices)->GetBootMode(PeiServices, &BootMode);
> + ASSERT_EFI_ERROR (Status);
> + if (BootMode == BOOT_IN_RECOVERY_MODE){
> + return Status;
> + }
> +
> + //
> + // Let's assume things are OK if not told otherwise
> + //
> + BootMode = BOOT_WITH_FULL_CONFIGURATION;
> +
> + if (GetSleepTypeAfterWakeup (PeiServices, &SleepType)) {
> + switch (SleepType) {
> + case V_PCH_ACPI_PM1_CNT_S3:
> + BootMode = BOOT_ON_S3_RESUME;
> + Status = (*PeiServices)->NotifyPpi (PeiServices,
> &mCapsuleNotifyList[0]);
> + ASSERT_EFI_ERROR (Status);
> + break;
> +
> + case V_PCH_ACPI_PM1_CNT_S4:
> + BootMode = BOOT_ON_S4_RESUME;
> + break;
> +
> + case V_PCH_ACPI_PM1_CNT_S5:
> + BootMode = BOOT_ON_S5_RESUME;
> + break;
> + } // switch (SleepType)
> + }
> +
> + if (IsFastBootEnabled (PeiServices)) {
> + DEBUG ((EFI_D_INFO, "Prioritizing Boot mode to
> BOOT_WITH_MINIMAL_CONFIGURATION\n"));
> + PrioritizeBootMode (&BootMode,
> BOOT_WITH_MINIMAL_CONFIGURATION);
> + }
> +
> + switch (BootMode) {
> + case BOOT_WITH_FULL_CONFIGURATION:
> + strBootMode = L"BOOT_WITH_FULL_CONFIGURATION";
> + break;
> + case BOOT_WITH_MINIMAL_CONFIGURATION:
> + strBootMode = L"BOOT_WITH_MINIMAL_CONFIGURATION";
> + break;
> + case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:
> + strBootMode = L"BOOT_ASSUMING_NO_CONFIGURATION_CHANGES";
> + break;
> + case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:
> + strBootMode =
> L"BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS";
> + break;
> + case BOOT_WITH_DEFAULT_SETTINGS:
> + strBootMode = L"BOOT_WITH_DEFAULT_SETTINGS";
> + break;
> + case BOOT_ON_S4_RESUME:
> + strBootMode = L"BOOT_ON_S4_RESUME";
> + break;
> + case BOOT_ON_S5_RESUME:
> + strBootMode = L"BOOT_ON_S5_RESUME";
> + break;
> + case BOOT_ON_S2_RESUME:
> + strBootMode = L"BOOT_ON_S2_RESUME";
> + break;
> + case BOOT_ON_S3_RESUME:
> + strBootMode = L"BOOT_ON_S3_RESUME";
> +
> + break;
> + case BOOT_ON_FLASH_UPDATE:
> + strBootMode = L"BOOT_ON_FLASH_UPDATE";
> + break;
> + case BOOT_IN_RECOVERY_MODE:
> + strBootMode = L"BOOT_IN_RECOVERY_MODE";
> + break;
> + default:
> + strBootMode = L"Unknown boot mode";
> + } // switch (BootMode)
> +
> + DEBUG ((EFI_D_ERROR, "Setting BootMode to %s\n", strBootMode));
> + Status = (*PeiServices)->SetBootMode(PeiServices, BootMode);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +#endif
> +
> +/**
> + Get sleep type after wakeup
> +
> + @param PeiServices Pointer to the PEI Service Table.
> + @param SleepType Sleep type to be returned.
> +
> + @retval TRUE A wake event occured without power failure.
> + @retval FALSE Power failure occured or not a wakeup.
> +
> +**/
> +BOOLEAN
> +GetSleepTypeAfterWakeup (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + OUT UINT16 *SleepType
> + )
> +{
> + UINT16 Pm1Sts;
> + UINT16 Pm1Cnt;
> + UINT16 GenPmCon1;
> + //
> + // VLV BIOS Specification 0.6.2 - Section 18.4, "Power Failure
> Consideration"
> + //
> + // When the SUS_PWR_FLR bit is set, it indicates the SUS well power is lost.
> + // This bit is in the SUS Well and defaults to 1�b1 based on RSMRST#
> assertion (not cleared by any type of reset).
> + // System BIOS should follow cold boot path if SUS_PWR_FLR (PBASE +
> 0x20[14]),
> + // GEN_RST_STS (PBASE + 0x20[9]) or PWRBTNOR_STS (ABASE + 0x00[11])
> is set to 1�b1
> + // regardless of the value in the SLP_TYP (ABASE + 0x04[12:10]) field.
> + //
> + GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS +
> R_PCH_PMC_GEN_PMCON_1);
> +
> + //
> + // Read the ACPI registers
> + //
> + Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
> + Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);
> +
> + if ((GenPmCon1 & (B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR |
> B_PCH_PMC_GEN_PMCON_GEN_RST_STS)) ||
> + (Pm1Sts & B_PCH_ACPI_PM1_STS_PRBTNOR)) {
> + //
> + // If power failure indicator, then don't attempt s3 resume.
> + // Clear PM1_CNT of S3 and set it to S5 as we just had a power failure, and
> memory has
> + // lost already. This is to make sure no one will use PM1_CNT to check for
> S3 after
> + // power failure.
> + //
> + if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) ==
> V_PCH_ACPI_PM1_CNT_S3) {
> + Pm1Cnt = ((Pm1Cnt & ~B_PCH_ACPI_PM1_CNT_SLP_TYP) |
> V_PCH_ACPI_PM1_CNT_S5);
> + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
> + }
> + //
> + // Clear Wake Status (WAK_STS)
> + //
> + }
> + //
> + // Get sleep type if a wake event occurred and there is no power failure
> + //
> + if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) ==
> V_PCH_ACPI_PM1_CNT_S3) {
> + *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
> + return TRUE;
> + } else if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) ==
> V_PCH_ACPI_PM1_CNT_S4) {
> + *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
> + return TRUE;
> + }
> + return FALSE;
> +}
> +
> +BOOLEAN
> +EFIAPI
> +IsFastBootEnabled (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;
> + UINTN VarSize;
> + SYSTEM_CONFIGURATION SystemConfiguration;
> + BOOLEAN FastBootEnabledStatus;
> +
> + FastBootEnabledStatus = FALSE;
> + Status = (**PeiServices).LocatePpi (
> + PeiServices,
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (void **)&PeiReadOnlyVarPpi
> + );
> + if (Status == EFI_SUCCESS) {
> + VarSize = sizeof (SYSTEM_CONFIGURATION);
> + Status = PeiReadOnlyVarPpi->GetVariable (
> + PeiReadOnlyVarPpi,
> + PLATFORM_SETUP_VARIABLE_NAME,
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VarSize,
> + &SystemConfiguration
> + );
> + if (Status == EFI_SUCCESS) {
> + if (SystemConfiguration.FastBoot != 0) {
> + FastBootEnabledStatus = TRUE;
> + }
> + }
> + }
> +
> + return FastBootEnabledStatus;
> +}
> +
> +/**
> + Given the current boot mode, and a proposed new boot mode, determine
> + which has priority. If the new boot mode has higher priority, then
> + make it the current boot mode.
> +
> + @param CurrentBootMode pointer to current planned boot mode
> + @param NewBootMode proposed boot mode
> +
> + @retval EFI_NOT_FOUND if either boot mode is not recognized
> + @retval EFI_SUCCESS if both boot mode values were recognized and
> + were processed.
> +**/
> +EFI_STATUS
> +PrioritizeBootMode (
> + IN OUT EFI_BOOT_MODE *CurrentBootMode,
> + IN EFI_BOOT_MODE NewBootMode
> + )
> +{
> + UINT32 CurrentIndex;
> + UINT32 NewIndex;
> +
> + //
> + // Find the position of the current boot mode in our priority array
> + //
> + for ( CurrentIndex = 0;
> + CurrentIndex < ARRAY_SIZE (mBootModePriority);
> + CurrentIndex++) {
> + if (mBootModePriority[CurrentIndex] == *CurrentBootMode) {
> + break;
> + }
> + }
> + if (CurrentIndex >= ARRAY_SIZE (mBootModePriority)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // Find the position of the new boot mode in our priority array
> + //
> + for ( NewIndex = 0;
> + NewIndex < ARRAY_SIZE (mBootModePriority);
> + NewIndex++) {
> + if (mBootModePriority[NewIndex] == NewBootMode) {
> + //
> + // If this new boot mode occurs before the current boot mode in the
> + // priority array, then take it.
> + //
> + if (NewIndex < CurrentIndex) {
> + *CurrentBootMode = NewBootMode;
> + }
> + return EFI_SUCCESS;
> + }
> + }
> + return EFI_NOT_FOUND;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/CommonHeader.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/CommonHeader.h
> new file mode 100644
> index 0000000000..283993b44c
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/CommonHeader.h
> @@ -0,0 +1,60 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#ifndef __COMMON_HEADER_H_
> +#define __COMMON_HEADER_H_
> +
> +
> +
> +#include <FrameworkPei.h>
> +
> +#include <IndustryStandard/SmBus.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Ppi/AtaController.h>
> +#include <Guid/Capsule.h>
> +#include <Ppi/Cache.h>
> +#include <Ppi/MasterBootMode.h>
> +#include <Guid/MemoryTypeInformation.h>
> +#include <Guid/RecoveryDevice.h>
> +#include <Ppi/ReadOnlyVariable2.h>
> +#include <Ppi/FvLoadFile.h>
> +#include <Ppi/DeviceRecoveryModule.h>
> +#include <Ppi/Capsule.h>
> +#include <Ppi/Reset.h>
> +#include <Ppi/Stall.h>
> +#include <Ppi/BootInRecoveryMode.h>
> +#include <Guid/FirmwareFileSystem2.h>
> +#include <Ppi/MemoryDiscovered.h>
> +#include <Ppi/RecoveryModule.h>
> +#include <Ppi/Smbus2.h>
> +#include <Ppi/FirmwareVolumeInfo.h>
> +#include <Ppi/EndOfPeiPhase.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PeimEntryPoint.h>
> +#include <Library/BaseLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PciCf8Lib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PciLib.h>
> +#include <Library/ReportStatusCodeLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/SmbusLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/ResetSystemLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PerformanceLib.h>
> +#include <Library/CacheMaintenanceLib.h>
> +#include <Library/MtrrLib.h>
> +
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/MemoryCallback.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/MemoryCallback.c
> new file mode 100644
> index 0000000000..7dcc2c3ce9
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/MemoryCallback.c
> @@ -0,0 +1,154 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> + This file includes a memory call back function notified when MRC is done,
> + following action is performed in this file,
> + 1. ICH initialization after MRC.
> + 2. SIO initialization.
> + 3. Install ResetSystem and FinvFv PPI.
> + 4. Set MTRR for PEI
> + 5. Create FV HOB and Flash HOB
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +#include "Platform.h"
> +#include <Ppi/Cache.h>
> +#include <Library/BaseCryptLib.h>
> +#include <Library/PciLib.h>
> +#include "VlvAccess.h"
> +
> +
> +EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode[] = {
> +{ (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gEfiPeiBootInRecoveryModePpiGuid,
> + NULL
> +}
> +};
> +
> +#if 0
> +STATIC
> +EFI_STATUS
> +GetMemorySize (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + OUT UINT64 *LowMemoryLength,
> + OUT UINT64 *HighMemoryLength
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_HOB_POINTERS Hob;
> +
> + *HighMemoryLength = 0;
> + *LowMemoryLength = 0x100000;
> + //
> + // Get the HOB list for processing
> + //
> + Status = (*PeiServices)->GetHobList (PeiServices, (void **)&Hob.Raw);
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + //
> + // Collect memory ranges
> + //
> + while (!END_OF_HOB_LIST (Hob)) {
> + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
> + if (Hob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_SYSTEM_MEMORY) {
> + //
> + // Need memory above 1MB to be collected here
> + //
> + if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 &&
> + Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS)
> 0x100000000) {
> + *LowMemoryLength += (UINT64) (Hob.ResourceDescriptor-
> >ResourceLength);
> + } else if (Hob.ResourceDescriptor->PhysicalStart >=
> (EFI_PHYSICAL_ADDRESS) 0x100000000) {
> + *HighMemoryLength += (UINT64) (Hob.ResourceDescriptor-
> >ResourceLength);
> + }
> + }
> + }
> + Hob.Raw = GET_NEXT_HOB (Hob);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +#endif
> +/**
> + This function will be called when MRC is done.
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param NotifyDescriptor Information about the notify event..
> + @param Ppi The notify context.
> +
> + @retval EFI_SUCCESS If the function completed successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +MemoryDiscoveredPpiNotifyCallback (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> + )
> +{
> +
> + EFI_BOOT_MODE BootMode;
> + UINT32 Pages;
> + VOID* Memory;
> + UINTN Size;
> +
> + //
> + // Allocate LM memory and configure PDM if enabled by user.
> + // ConfigureLM(PeiServices);
> + //
> + (*PeiServices)->GetBootMode (
> + (const EFI_PEI_SERVICES **)PeiServices,
> + &BootMode
> + );
> +
> + if (BootMode != BOOT_ON_S3_RESUME) {
> + Size = (PcdGet32 (PcdFlashFvRecovery2Base) - PcdGet32
> (PcdFlashFvMainBase)) + FixedPcdGet32(PcdFlashFvRecovery2Size);
> + Pages= Size/0x1000;
> +
> + Memory = AllocatePages ( Pages );
> + CopyMem(Memory , (VOID *) FixedPcdGet32(PcdFlashFvMainBase) ,
> Size);
> +
> + //
> + // We don't verify just load
> + //
> + PeiServicesInstallFvInfoPpi (
> + NULL,
> + (VOID *) ((UINTN) Memory + (PcdGet32 (PcdFlashFvRecovery2Base) -
> PcdGet32 (PcdFlashFvMainBase))),
> + PcdGet32 (PcdFlashFvRecovery2Size),
> + NULL,
> + NULL
> + );
> +
> + PeiServicesInstallFvInfoPpi (
> + NULL,
> + (VOID *) Memory,
> + PcdGet32 (PcdFlashFvMainSize),
> + NULL,
> + NULL
> + );
> +
> + }
> +
> + if (BootMode == BOOT_ON_S3_RESUME) {
> + PeiServicesInstallFvInfoPpi (
> + NULL,
> + (VOID *) (UINTN) (PcdGet32 (PcdFlashFvRecovery2Base)),
> + PcdGet32 (PcdFlashFvRecovery2Size),
> + NULL,
> + NULL
> + );
> + }
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/Platform.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/Platform.c
> new file mode 100644
> index 0000000000..eba1dfff30
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/Platform.c
> @@ -0,0 +1,1198 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> +**/
> +
> +#include "CommonHeader.h"
> +
> +#include "Platform.h"
> +#include <Library/PciCf8Lib.h>
> +#include "PlatformBaseAddresses.h"
> +#include "PchAccess.h"
> +#include <Guid/PlatformInfo.h>
> +#include "PchCommonDefinitions.h"
> +#include <Ppi/MfgMemoryTest.h>
> +#include <Guid/SetupVariable.h>
> +#include <Guid/Vlv2Variable.h>
> +#include <Ppi/fTPMPolicy.h>
> +
> +//
> +// Start::Alpine Valley platform
> +//
> +enum {
> + SMBUS_READ_BYTE,
> + SMBUS_WRITE_BYTE,
> + SMBUS_READ_BLOCK,
> + SMBUS_WRITE_BLOCK
> +};
> +
> +#define EC_BASE 0xE0000000
> +
> +//
> +// DEVICE 0 (Memroy Controller Hub)
> +//
> +#define MC_BUS 0x00
> +#define MC_DEV 0x00
> +#define MC_FUN 0x00
> +#define MC_DEV_FUN (MC_DEV << 3)
> +#define MC_BUS_DEV_FUN ((MC_BUS << 8) + MC_DEV_FUN)
> +
> +//
> +// SysCtl SMBus address and block size
> +//
> +#define AV_SC_SMBUS_ADDRESS 0x60
> +#define AV_SC_BYTE_LEN 1
> +#define AV_SC_BLOCK_LEN 4
> +#define AV_SC_SMBUS_WRCMD 1
> +#define AV_SC_SMBUS_RDCMD 0
> +
> +//
> +// SysCtl registers offset
> +//
> +#define AV_SC_REG_PLATFORM_ID 24 // 0x18
> +#define AV_SC_REG_BOARD_ID 28 // 0x1C
> +#define AV_SC_REG_FAB_ID 32 // 0x20
> +#define AV_SC_REG_ECO_ID 68 // 0x44
> +#define AV_SC_REG_DDR_DAUGHTER_CARD_ID 144 // 0x90
> +#define AV_SC_REG_SODIMM_CONFIG 36
> +
> +//
> +// ID values
> +//
> +#define AV_SC_PLATFORM_ID_TABLET 0
> +#define AV_SC_PLATFORM_ID_NETBOOK 2
> +#define AV_SC_PLATFORM_ID_INTERPOSER 3 // Configuration TBD
> +#define AV_SC_BOARD_ID_AV_SVP 1492
> +
> +#define BUS_TRIES 3 // How many times to retry on Bus Errors
> +
> +#define GTT_SIZE_1MB 1
> +#define GTT_SIZE_2MB 2
> +
> +#define PciCfg16Read( PciExpressBase, Bus, Device, Function, Register ) \
> + MmioRead16(PciExpressBase + \
> + (UINTN)(Bus << 20) + \
> + (UINTN)(Device << 15) + \
> + (UINTN)(Function << 12) + \
> + (UINTN)(Register))
> +#define PciCfg16Write( PciExpressBase, Bus, Device, Function, Register,
> Data ) \
> + MmioWrite16(PciExpressBase + \
> + (UINTN)(Bus << 20) + \
> + (UINTN)(Device << 15) + \
> + (UINTN)(Function << 12) + \
> + (UINTN)(Register), \
> + (UINT16)Data)
> +
> +
> +//
> +//Memory Test Manufacturing mode
> +//
> +UINT32 DataPatternForMemoryTest[] = {
> + 0x55555555, 0xAAAAAAAA, 0x55555510, 0x555555EF, 0x55555510,
> 0x555555EF, 0x55555510, 0x555555EF,
> + 0x55555555, 0xAAAAAAAA, 0x55551055, 0x5555EF55, 0x55551055,
> 0x5555EF55, 0x55551055, 0x5555EF55,
> + 0x55555555, 0xAAAAAAAA, 0x55105555, 0x55EF5555, 0x55105555,
> 0x55EF5555, 0x55105555, 0x55EF5555,
> + 0x55555555, 0xAAAAAAAA, 0x10555555, 0xEF555555, 0x10555555,
> 0xEF555555, 0x10555555, 0xEF555555
> +};
> +#define DATA_PATTERN_ARRAY_SIZE (sizeof(DataPatternForMemoryTest)
> / sizeof(UINT32))
> +
> +//
> +//Memory Test Manufacturing mode
> +//
> +//
> +// The global indicator, the FvFileLoader callback will modify it to TRUE after
> loading PEIM into memory
> +//
> +BOOLEAN ImageInMemory = FALSE;
> +
> +EFI_STATUS
> +EFIAPI
> +Stall (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN CONST EFI_PEI_STALL_PPI *This,
> + IN UINTN Microseconds
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +MfgMemoryTest (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN PEI_MFG_MEMORY_TEST_PPI *This,
> + IN UINT32 BeginAddress,
> + IN UINT32 MemoryLength
> + );
> +
> +static EFI_PEI_STALL_PPI mStallPpi = {
> + PEI_STALL_RESOLUTION,
> + Stall
> +};
> +
> +static PEI_MFG_MEMORY_TEST_PPI mPeiMfgMemoryTestPpi = {
> + MfgMemoryTest
> +};
> +
> +static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gEfiPeiStallPpiGuid,
> + &mStallPpi
> + },
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> + &gPeiMfgMemoryTestPpiGuid,
> + &mPeiMfgMemoryTestPpi
> + }
> + };
> +
> +EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[1] = {
> + {
> + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gEfiPeiMemoryDiscoveredPpiGuid,
> + MemoryDiscoveredPpiNotifyCallback
> + }
> +};
> +
> +EFI_STATUS
> +EFIAPI
> +InstallMonoStatusCode (
> + IN EFI_FFS_FILE_HEADER *FfsHeader,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +
> +EFI_STATUS
> +ReadPlatformIds (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + );
> +
> +//
> +// Start::Alpine Valley platform
> +//
> +EFI_STATUS
> +PeiSmbusExec (
> + UINT16 SmbusBase,
> + UINT8 SlvAddr,
> + UINT8 Operation,
> + UINT8 Offset,
> + UINT8 *Length,
> + UINT8 *Buffer
> + );
> +
> +
> +/**
> +
> + Detemine Turbot board
> + @return 0: Not Turbot board
> + 1: Turbot board
> +
> +**/
> +UINT32
> +DetermineTurbotBoard (
> + void
> + )
> +{
> + UINTN PciD31F0RegBase = 0;
> + UINT32 GpioValue = 0;
> + UINT32 TmpVal = 0;
> + UINT32 MmioConf0 = 0;
> + UINT32 MmioPadval = 0;
> + UINT32 PConf0Offset = 0x200; //GPIO_S5_4 pad_conf0 register offset
> + UINT32 PValueOffset = 0x208; //GPIO_S5_4 pad_value register offset
> + UINT32 SSUSOffset = 0x2000;
> + UINT32 IoBase = 0;
> +
> + DEBUG ((EFI_D_ERROR, "DetermineTurbotBoard() Entry\n"));
> + PciD31F0RegBase = MmPciAddress (0,
> + 0,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + 0
> + );
> + IoBase = MmioRead32 (PciD31F0RegBase + R_PCH_LPC_IO_BASE) &
> B_PCH_LPC_IO_BASE_BAR;
> +
> + MmioConf0 = IoBase + SSUSOffset + PConf0Offset;
> + MmioPadval = IoBase + SSUSOffset + PValueOffset;
> + //0xFED0E200/0xFED0E208 is pad_Conf/pad_val register address of
> GPIO_S5_4
> + DEBUG ((EFI_D_ERROR, "MmioConf0[0x%x], MmioPadval[0x%x]\n",
> MmioConf0, MmioPadval));
> +
> + MmioWrite32 (MmioConf0, 0x2003CC00);
> +
> + TmpVal = MmioRead32 (MmioPadval);
> + TmpVal &= ~0x6; //Clear bit 1:2
> + TmpVal |= 0x2; // Set the pin as GPI
> + MmioWrite32 (MmioPadval, TmpVal);
> +
> + GpioValue = MmioRead32 (MmioPadval);
> +
> + DEBUG ((EFI_D_ERROR, "Gpio_S5_4 value is 0x%x\n", GpioValue));
> + return (GpioValue & 0x1);
> +}
> +
> +
> +
> +EFI_STATUS
> +FtpmPolicyInit (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN SYSTEM_CONFIGURATION *pSystemConfiguration
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_PPI_DESCRIPTOR *mFtpmPolicyPpiDesc;
> + SEC_FTPM_POLICY_PPI *mFtpmPolicyPpi;
> +
> +
> + DEBUG((EFI_D_INFO, "FtpmPolicyInit Entry \n"));
> +
> + if (NULL == PeiServices || NULL == pSystemConfiguration) {
> + DEBUG((EFI_D_ERROR, "Input error. \n"));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Status = (*PeiServices)->AllocatePool(
> + PeiServices,
> + sizeof (EFI_PEI_PPI_DESCRIPTOR),
> + (void **)&mFtpmPolicyPpiDesc
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = (*PeiServices)->AllocatePool(
> + PeiServices,
> + sizeof (SEC_FTPM_POLICY_PPI),
> + (void **)&mFtpmPolicyPpi
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Initialize PPI
> + //
> + (*PeiServices)->SetMem ((VOID *)mFtpmPolicyPpi, sizeof
> (SEC_FTPM_POLICY_PPI), 0);
> + mFtpmPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
> + mFtpmPolicyPpiDesc->Guid = &gSeCfTPMPolicyPpiGuid;
> + mFtpmPolicyPpiDesc->Ppi = mFtpmPolicyPpi;
> +
> +
> + DEBUG((EFI_D_INFO, "pSystemConfiguration->fTPM = 0x%x \n",
> pSystemConfiguration->fTPM));
> + if(pSystemConfiguration->fTPM == 1) {
> + mFtpmPolicyPpi->fTPMEnable = TRUE;
> + } else {
> + mFtpmPolicyPpi->fTPMEnable = FALSE;
> + }
> +
> + Status = (*PeiServices)->InstallPpi(
> + PeiServices,
> + mFtpmPolicyPpiDesc
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + DEBUG((EFI_D_INFO, "FtpmPolicyInit done \n"));
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + This routine attempts to acquire the SMBus
> +
> + @retval FAILURE as failed
> + @retval SUCCESS as passed
> +
> +**/
> +EFI_STATUS
> +AcquireBus (
> + UINT16 SmbusBase
> + )
> +{
> + UINT8 StsReg;
> +
> + StsReg = 0;
> + StsReg = (UINT8)IoRead8(SmbusBase + R_PCH_SMBUS_HSTS);
> + if (StsReg & B_PCH_SMBUS_IUS) {
> + return EFI_DEVICE_ERROR;
> + } else if (StsReg & B_PCH_SMBUS_HBSY) {
> + //
> + // Clear Status Register and exit
> + //
> + // Wait for HSTS.HBSY to be clear
> + //
> + do { StsReg = (UINT8) IoRead8(SmbusBase+R_PCH_SMBUS_HSTS); }
> while ((StsReg & B_PCH_SMBUS_HBSY) != 0);
> +
> + //
> + // Clear all status bits
> + //
> + IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, 0xFE);
> + return EFI_SUCCESS;
> + } else {
> + //
> + // Clear out any odd status information (Will Not Clear In Use)
> + //
> + IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, StsReg);
> + return EFI_SUCCESS;
> + }
> +}
> +//
> +// End::Alpine Valley platform
> +//
> +
> +/**
> + This function checks the memory range in PEI.
> +
> + @param PeiServices Pointer to PEI Services.
> + @param This Pei memory test PPI pointer.
> + @param BeginAddress Beginning of the memory address to be checked.
> + @param MemoryLength Bytes of memory range to be checked.
> + @param Operation Type of memory check operation to be performed.
> + @param ErrorAddress Return the address of the error memory address.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use this
> range of memory.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +MfgMemoryTest (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN PEI_MFG_MEMORY_TEST_PPI *This,
> + IN UINT32 BeginAddress,
> + IN UINT32 MemoryLength
> + )
> +{
> + UINT32 i;
> + UINT32 memAddr;
> + UINT32 readData;
> + UINT32 xorData;
> + UINT32 TestFlag = 0;
> + memAddr = BeginAddress;
> +
> + //
> + //Output Message for MFG
> + //
> + DEBUG ((EFI_D_ERROR, "MFGMODE SET\n"));
> +
> + //
> + //Writting the pattern in defined location.
> + //
> + while (memAddr < (BeginAddress+MemoryLength)) {
> + for (i = 0; i < DATA_PATTERN_ARRAY_SIZE; i++) {
> + if (memAddr > (BeginAddress+MemoryLength -4)) {
> + memAddr = memAddr + 4;
> + break;
> + }
> + *((volatile UINT32*) memAddr) = DataPatternForMemoryTest[i];
> + memAddr = memAddr + 4;
> + }
> + }
> +
> + //
> + //Verify the pattern.
> + //
> + memAddr = BeginAddress;
> + while (memAddr < (BeginAddress+MemoryLength)) {
> + for (i = 0; i < DATA_PATTERN_ARRAY_SIZE; i++) {
> + if (memAddr > (BeginAddress+MemoryLength -4)) {
> + memAddr = memAddr + 4;
> + break;
> + }
> + readData = *((volatile UINT32*) memAddr);
> + xorData = readData ^ DataPatternForMemoryTest[i];
> +
> + //
> + // If xorData is nonzero, this particular memAddr has a failure.
> + //
> + if (xorData != 0x00000000) {
> + DEBUG ((EFI_D_ERROR, "Expected value....: %x\n",
> DataPatternForMemoryTest[i]));
> + DEBUG ((EFI_D_ERROR, "ReadData value....: %x\n", readData));
> + DEBUG ((EFI_D_ERROR, "Pattern failure at....: %x\n", memAddr));
> + TestFlag = 1;
> + }
> + memAddr = memAddr + 4;
> + }
> + }
> + if (TestFlag) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + //
> + //Output Message for MFG
> + //
> + DEBUG ((EFI_D_ERROR, "MFGMODE MEMORY TEST PASSED\n"));
> + return EFI_SUCCESS;
> +}
> +
> +BOOLEAN
> +IsRtcUipAlwaysSet (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> +
> + EFI_PEI_STALL_PPI *StallPpi;
> + UINTN Count;
> +
> + (**PeiServices).LocatePpi (PeiServices, &gEfiPeiStallPpiGuid, 0, NULL,
> (void **)&StallPpi);
> +
> + for (Count = 0; Count < 500; Count++) { // Maximum waiting approximates
> to 1.5 seconds (= 3 msec * 500)
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERA);
> + if ((IoRead8 (R_PCH_RTC_TARGET2) & B_PCH_RTC_REGISTERA_UIP) == 0)
> {
> + return FALSE;
> + }
> +
> + StallPpi->Stall (PeiServices, StallPpi, 3000);
> + }
> +
> + return TRUE;
> +}
> +
> +EFI_STATUS
> +RtcPowerFailureHandler (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> +
> + UINT16 DataUint16;
> + UINT8 DataUint8;
> + BOOLEAN RtcUipIsAlwaysSet;
> + DataUint16 = MmioRead16 (PMC_BASE_ADDRESS +
> R_PCH_PMC_GEN_PMCON_1);
> + RtcUipIsAlwaysSet = IsRtcUipAlwaysSet (PeiServices);
> + if ((DataUint16 & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) ||
> (RtcUipIsAlwaysSet)) {
> + //
> + // Execute the sequence below. This will ensure that the RTC state
> machine has been initialized.
> + //
> + // Step 1.
> + // BIOS clears this bit by writing a '0' to it.
> + //
> + if (DataUint16 & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) {
> + //
> + // Set to invalid date in order to reset the time to
> + // BIOS build time later in the boot (SBRUN.c file).
> + //
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_YEAR);
> + IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_MONTH);
> + IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_DAYOFMONTH);
> + IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_DAYOFWEEK);
> + IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);
> +
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_SECONDSALARM);
> + IoWrite8 (R_PCH_RTC_TARGET2, 0x00);
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_MINUTESALARM);
> + IoWrite8 (R_PCH_RTC_TARGET2, 0x00);
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_HOURSALARM);
> + IoWrite8 (R_PCH_RTC_TARGET2, 0x00);
> + }
> +
> + //
> + // Step 2.
> + // Set RTC Register 0Ah[6:4] to '110' or '111'.
> + //
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERA);
> + IoWrite8 (R_PCH_RTC_TARGET2, (V_PCH_RTC_REGISTERA_DV_DIV_RST1
> | V_PCH_RTC_REGISTERA_RS_976P5US));
> +
> + //
> + // Step 3.
> + // Set RTC Register 0Bh[7].
> + //
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);
> + DataUint8 = (IoRead8 (R_PCH_RTC_TARGET2) |
> B_PCH_RTC_REGISTERB_SET);
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);
> + IoWrite8 (R_PCH_RTC_TARGET2, DataUint8);
> +
> + //
> + // Step 4.
> + // Set RTC Register 0Ah[6:4] to '010'.
> + //
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERA);
> + IoWrite8 (R_PCH_RTC_TARGET2,
> (V_PCH_RTC_REGISTERA_DV_NORM_OP |
> V_PCH_RTC_REGISTERA_RS_976P5US));
> +
> + //
> + // Step 5.
> + // Clear RTC Register 0Bh[7].
> + //
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);
> + DataUint8 = (IoRead8 (R_PCH_RTC_TARGET2) &
> (UINT8)~B_PCH_RTC_REGISTERB_SET);
> + IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);
> + IoWrite8 (R_PCH_RTC_TARGET2, DataUint8);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +VOID
> +PchBaseInit (
> + VOID
> + )
> +{
> + //
> + // Program ACPI Power Management I/O Space Base Address
> + //
> + MmioWrite16 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_ACPI_BASE
> + ),
> + (UINT16)((ACPI_BASE_ADDRESS & B_PCH_LPC_ACPI_BASE_BAR) |
> B_PCH_LPC_ACPI_BASE_EN)
> + );
> +
> + //
> + // Program GPIO Base Address
> + //
> + MmioWrite16 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_GPIO_BASE
> + ),
> + (UINT16)((GPIO_BASE_ADDRESS & B_PCH_LPC_GPIO_BASE_BAR) |
> B_PCH_LPC_GPIO_BASE_EN)
> + );
> +
> + //
> + // Set PMC Base Address
> + //
> + MmioWrite32 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_PMC_BASE
> + ),
> + (UINT32)((PMC_BASE_ADDRESS & B_PCH_LPC_PMC_BASE_BAR) |
> B_PCH_LPC_PMC_BASE_EN)
> + );
> +
> + //
> + // Set IO Base Address
> + //
> + MmioWrite32 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_IO_BASE
> + ),
> + (UINT32)((IO_BASE_ADDRESS & B_PCH_LPC_IO_BASE_BAR) |
> B_PCH_LPC_IO_BASE_EN)
> + );
> +
> + //
> + // Set ILB Base Address
> + //
> + MmioWrite32 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_ILB_BASE
> + ),
> + (UINT32)((ILB_BASE_ADDRESS & B_PCH_LPC_ILB_BASE_BAR) |
> B_PCH_LPC_ILB_BASE_EN)
> + );
> +
> + //
> + // Set PUnit Base Address
> + //
> + MmioWrite32 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_PUNIT_BASE
> + ),
> + (UINT32)((PUNIT_BASE_ADDRESS & B_PCH_LPC_PUNIT_BASE_BAR) |
> B_PCH_LPC_PUNIT_BASE_EN)
> + );
> +
> + //
> + // Set SPI Base Address
> + //
> + MmioWrite32 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_SPI_BASE
> + ),
> + (UINT32)((SPI_BASE_ADDRESS & B_PCH_LPC_SPI_BASE_BAR) |
> B_PCH_LPC_SPI_BASE_EN)
> + );
> +
> + //
> + // Set Root Complex Base Address
> + //
> + MmioWrite32 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_RCBA
> + ),
> + (UINT32)((RCBA_BASE_ADDRESS & B_PCH_LPC_RCBA_BAR) |
> B_PCH_LPC_RCBA_EN)
> + );
> +
> + //
> + // Set MPHY Base Address
> + //
> + MmioWrite32 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_MPHY_BASE
> + ),
> + (UINT32)((MPHY_BASE_ADDRESS & B_PCH_LPC_MPHY_BASE_BAR) |
> B_PCH_LPC_MPHY_BASE_EN)
> + );
> + MmioWrite16 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_SMBUS,
> + PCI_FUNCTION_NUMBER_PCH_SMBUS,
> + R_PCH_SMBUS_BASE
> + ),
> + (UINT16)(SMBUS_BASE_ADDRESS & B_PCH_SMBUS_BASE_BAR)
> + );
> +
> + MmioOr8 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_SMBUS,
> + PCI_FUNCTION_NUMBER_PCH_SMBUS,
> + R_PCH_SMBUS_PCICMD
> + ),
> + B_PCH_SMBUS_PCICMD_IOSE
> + );
> +
> +}
> +
> +/**
> + This is the entrypoint of PEIM
> +
> + @param FileHandle Handle of the file being invoked.
> + @param PeiServices Describes the list of possible PEI Services.
> +
> + @retval EFI_SUCCESS if it completed successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiInitPlatform (
> + IN EFI_PEI_FILE_HANDLE FileHandle,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + UINTN SmbusRegBase;
> + EFI_PLATFORM_INFO_HOB PlatformInfo;
> + EFI_STATUS Status= EFI_SUCCESS;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable = NULL;
> + UINTN VariableSize;
> + SYSTEM_CONFIGURATION SystemConfiguration;
> + UINT32 GGC = 0;
> +
> + EFI_PEI_PPI_DESCRIPTOR *mVlvMmioPolicyPpiDesc;
> + VLV_MMIO_POLICY_PPI *mVlvMmioPolicyPpi;
> +
> + ZeroMem (&PlatformInfo, sizeof(PlatformInfo));
> +
> + Status = InstallMonoStatusCode(FileHandle, PeiServices);
> + ASSERT_EFI_ERROR (Status);
> +
> +
> + //
> + // Initialize Stall PPIs
> + //
> + Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi[0]);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = (*PeiServices)->NotifyPpi (PeiServices,
> &mMemoryDiscoveredNotifyList[0]);
> + ASSERT_EFI_ERROR (Status);
> + SmbusRegBase = PchPciDeviceMmBase (
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_SMBUS,
> + PCI_FUNCTION_NUMBER_PCH_SMBUS
> + );
> + //
> + // Since PEI has no PCI enumerator, set the BAR & I/O space enable
> ourselves
> + //
> + MmioAndThenOr32 (SmbusRegBase + R_PCH_SMBUS_BASE,
> B_PCH_SMBUS_BASE_BAR, SMBUS_BASE_ADDRESS);
> +
> + MmioOr8 (SmbusRegBase + R_PCH_SMBUS_PCICMD,
> B_PCH_SMBUS_PCICMD_IOSE);
> +
> + PchBaseInit();
> +
> + //
> + //Todo: confirm if we need program 8254
> + //
> + // Setting 8254
> + // Program timer 1 as refresh timer
> + //
> + IoWrite8 (0x43, 0x54);
> + IoWrite8 (0x41, 0x12);
> +
> + //
> + // RTC power failure handling
> + //
> + RtcPowerFailureHandler (PeiServices);
> +
> +
> + PchMmPci32( 0, 0, 2, 0, 0x50) = 0x210;
> +
> + VariableSize = sizeof (SYSTEM_CONFIGURATION);
> + ZeroMem (&SystemConfiguration, VariableSize);
> +
> + //
> + // Obtain variable services
> + //
> + Status = (*PeiServices)->LocatePpi(
> + PeiServices,
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (void **)&Variable
> + );
> + ASSERT_EFI_ERROR(Status);
> + Status = Variable->GetVariable (
> + Variable,
> + L"Setup",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VariableSize,
> + &SystemConfiguration
> + );
> + if (EFI_ERROR (Status) || VariableSize != sizeof(SYSTEM_CONFIGURATION))
> {
> + //The setup variable is corrupted
> + VariableSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = Variable->GetVariable(
> + Variable,
> + L"SetupRecovery",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VariableSize,
> + &SystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + if (EFI_ERROR (Status)) {
> + GGC = ((2 << 3) | 0x200);
> + PciCfg16Write(EC_BASE, 0, 2, 0, 0x50, GGC);
> + GGC = PciCfg16Read(EC_BASE, 0, 2, 0, 0x50);
> + DEBUG((EFI_D_INFO , "GGC: 0x%08x GMSsize:0x%08x\n", GGC, (GGC &
> (BIT7|BIT6|BIT5|BIT4|BIT3))>>3));
> + } else {
> + if (SystemConfiguration.Igd == 1 &&
> SystemConfiguration.PrimaryVideoAdaptor != 2) {
> + GGC = (SystemConfiguration.IgdDvmt50PreAlloc << 3) |
> + (SystemConfiguration.GTTSize == GTT_SIZE_1MB ? 0x100: 0x200);
> + PciCfg16Write(EC_BASE, 0, 2, 0, 0x50, GGC);
> + GGC = PciCfg16Read(EC_BASE, 0, 2, 0, 0x50);
> + DEBUG((EFI_D_INFO , "GGC: 0x%08x GMSsize:0x%08x\n", GGC, (GGC &
> (BIT7|BIT6|BIT5|BIT4|BIT3))>>3));
> + }
> + }
> +
> + //
> + // Initialize PlatformInfo HOB
> + //
> + Status = ReadPlatformIds(PeiServices, &PlatformInfo);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // 0 -> Disable , 1 -> Enable
> + //
> + if(SystemConfiguration.CfioPnpSettings == 1) {
> + DEBUG((EFI_D_INFO, "CheckCfioPnpSettings: CFIO Pnp Settings
> Enabled\n"));
> + PlatformInfo.CfioEnabled = 1;
> + } else {
> + DEBUG((EFI_D_INFO, "CheckCfioPnpSettings: CFIO Pnp Settings
> Disabled\n"));
> + PlatformInfo.CfioEnabled = 0;
> + }
> +
> + //
> + // Build HOB for PlatformInfo
> + //
> + BuildGuidDataHob (
> + &gEfiPlatformInfoGuid,
> + &PlatformInfo,
> + sizeof (EFI_PLATFORM_INFO_HOB)
> + );
> +
> +
> +#ifdef FTPM_ENABLE
> + Status = FtpmPolicyInit(PeiServices, &SystemConfiguration);
> + if (EFI_ERROR (Status)) {
> + DEBUG((EFI_D_ERROR, "fTPM init failed.\n"));
> + }
> +#endif
> +
> +
> + //
> + // Set the new boot mode for MRC
> + //
> +#ifdef NOCS_S3_SUPPORT
> + Status = UpdateBootMode (PeiServices);
> + ASSERT_EFI_ERROR (Status);
> +#endif
> +
> + DEBUG((EFI_D_INFO, "Setup MMIO size ... \n\n"));
> +
> + //
> + // Setup MMIO size
> + //
> + Status = (*PeiServices)->AllocatePool(
> + PeiServices,
> + sizeof (EFI_PEI_PPI_DESCRIPTOR),
> + (void **)&mVlvMmioPolicyPpiDesc
> + );
> + ASSERT_EFI_ERROR (Status);
> + Status = (*PeiServices)->AllocatePool(
> + PeiServices,
> + sizeof (VLV_MMIO_POLICY_PPI),
> + (void **)&mVlvMmioPolicyPpi
> + );
> + ASSERT_EFI_ERROR (Status);
> + (*PeiServices)->SetMem (
> + (VOID *)mVlvMmioPolicyPpi,
> + sizeof (VLV_MMIO_POLICY_PPI),
> + 0
> + );
> + mVlvMmioPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
> + mVlvMmioPolicyPpiDesc->Guid = &gVlvMmioPolicyPpiGuid;
> + mVlvMmioPolicyPpiDesc->Ppi = mVlvMmioPolicyPpi;
> + switch (SystemConfiguration.MmioSize) {
> + case 0: // 768MB
> + mVlvMmioPolicyPpi->MmioSize = 0x300;
> + break;
> + case 1: // 1GB
> + mVlvMmioPolicyPpi->MmioSize = 0x400;
> + break;
> + case 2: // 1.25GB
> + mVlvMmioPolicyPpi->MmioSize = 0x500;
> + break;
> + case 3: // 1.5GB
> + mVlvMmioPolicyPpi->MmioSize = 0x600;
> + break;
> + case 4: // 2GB
> + mVlvMmioPolicyPpi->MmioSize = 0x800;
> + break;
> + default:
> + mVlvMmioPolicyPpi->MmioSize = 0x800;
> + break;
> + }
> + Status = (*PeiServices)->InstallPpi(
> + PeiServices,
> + mVlvMmioPolicyPpiDesc
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> +EFI_STATUS
> +ReadPlatformIds (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
> + )
> +{
> + {
> + EFI_STATUS Status = EFI_SUCCESS;
> + UINT8 FabId = 0;
> + UINTN DataSize;
> + EFI_PLATFORM_INFO_HOB TmpHob;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVar;
> + UINT32 CompatibleBoard = 0;
> +
> + Status = (**PeiServices).LocatePpi (
> + PeiServices,
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (void **)&PeiVar
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + DataSize = sizeof (EFI_PLATFORM_INFO_HOB);
> + Status = PeiVar->GetVariable (
> + PeiVar,
> + L"PlatformInfo",
> + &gEfiVlv2VariableGuid,
> + NULL,
> + &DataSize,
> + &TmpHob
> + );
> +
> + if (Status == EFI_SUCCESS) {
> + PlatformInfoHob->BoardId = TmpHob.BoardId;
> + PlatformInfoHob->MemCfgID = TmpHob.MemCfgID;
> + PlatformInfoHob->BoardRev = TmpHob.BoardRev;
> + PlatformInfoHob->PlatformFlavor = TmpHob.PlatformFlavor;
> + return Status;
> + }
> +
> + CompatibleBoard = DetermineTurbotBoard();
> + if (1 == CompatibleBoard) {
> + PlatformInfoHob->BoardId = BOARD_ID_MINNOW2_TURBOT;
> + DEBUG ((EFI_D_INFO, "I'm MinnowBoard Turbot!\n"));
> + } else {
> + PlatformInfoHob->BoardId = BOARD_ID_MINNOW2;
> + DEBUG ((EFI_D_INFO, "I'm MinnowBoard Max!\n"));
> + }
> +
> +
> + PlatformInfoHob->MemCfgID = 0;
> + PlatformInfoHob->BoardRev = FabId + 1; // FabId = 0 means FAB1
> (BoardRev = 1), FabId = 1 means FAB2 (BoardRev = 2)...
> + PlatformInfoHob->PlatformFlavor = FlavorMobile;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +//
> +// Start::Alpine Valley platform
> +//
> +/**
> + This routine reads SysCtl registers
> +
> + @param SmbusBase SMBUS Base Address
> + @param SlvAddr Targeted Smbus Slave device address
> + @param Operation Which SMBus protocol will be used
> + @param Offset Offset of the register
> + @param Length Number of bytes
> + @param Buffer Buffer contains values read from registers
> +
> + @retval SUCCESS as passed
> + @retval Others as failed
> +
> +**/
> +EFI_STATUS
> +PeiSmbusExec (
> + UINT16 SmbusBase,
> + UINT8 SlvAddr,
> + UINT8 Operation,
> + UINT8 Offset,
> + UINT8 *Length,
> + UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status=EFI_SUCCESS;
> + UINT8 AuxcReg;
> + UINT8 SmbusOperation = 0;
> + UINT8 StsReg;
> + UINT8 SlvAddrReg;
> + UINT8 HostCmdReg;
> + UINT8 BlockCount = 0;
> + BOOLEAN BufferTooSmall;
> + UINT8 Index;
> + UINT8 *CallBuffer;
> + UINT8 RetryCount = BUS_TRIES;
> +
> + //
> + // MrcSmbusExec supports byte and block read.
> + // Only allow Byte or block access
> + //
> + if (!((*Length == AV_SC_BYTE_LEN) || (*Length == AV_SC_BLOCK_LEN)))
> {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // See if its ok to use the bus based upon INUSE_STS bit.
> + //
> + Status = AcquireBus (SmbusBase);
> + ASSERT_EFI_ERROR(Status);
> +
> + CallBuffer = Buffer;
> +
> + //
> + //SmbStatus Bits of interest
> + //[6] = IUS (In Use Status)
> + //[4] = FAIL
> + //[3] = BERR (Bus Error = transaction collision)
> + //[2] = DERR (Device Error = Illegal Command Field, Unclaimed Cycle, Host
> Device Timeout, CRC Error)
> + //[1] = INTR (Successful completion of last command)
> + //[0] = HOST BUSY
> + //
> + //
> + // This is the main operation loop. If the operation results in a Smbus
> + // collision with another master on the bus, it attempts the requested
> + // transaction again at least BUS_TRIES attempts.
> + //
> + while (RetryCount--) {
> + //
> + // Operation Specifics (pre-execution)
> + //
> + Status = EFI_SUCCESS;
> + SlvAddrReg = SlvAddr;
> + HostCmdReg = Offset;
> + AuxcReg = 0;
> +
> + switch (Operation) {
> +
> + case SMBUS_WRITE_BYTE:
> + IoWrite8 (SmbusBase+R_PCH_SMBUS_HD0, CallBuffer[0]);
> + SmbusOperation = V_PCH_SMBUS_SMB_CMD_BYTE_DATA;
> + break;
> +
> + case SMBUS_READ_BYTE:
> + SmbusOperation = V_PCH_SMBUS_SMB_CMD_BYTE_DATA;
> + SlvAddrReg |= B_PCH_SMBUS_RW_SEL_READ;
> + if (*Length < 1) {
> + Status = EFI_INVALID_PARAMETER;
> + }
> + *Length = 1;
> + break;
> +
> + case SMBUS_WRITE_BLOCK:
> + SmbusOperation = V_PCH_SMBUS_SMB_CMD_BLOCK;
> + IoWrite8 (SmbusBase+R_PCH_SMBUS_HD0, *(UINT8 *) Length);
> + BlockCount = (UINT8) (*Length);
> + if ((*Length < 1) || (*Length > 32)) {
> + Status = EFI_INVALID_PARAMETER;
> + break;
> + }
> + AuxcReg |= B_PCH_SMBUS_E32B;
> + break;
> +
> + case SMBUS_READ_BLOCK:
> + SmbusOperation = V_PCH_SMBUS_SMB_CMD_BLOCK;
> + SlvAddrReg |= B_PCH_SMBUS_RW_SEL_READ;
> + if ((*Length < 1) || (*Length > 32)) {
> + Status = EFI_INVALID_PARAMETER;
> + break;
> + }
> + AuxcReg |= B_PCH_SMBUS_E32B;
> + break;
> +
> + default:
> + Status = EFI_INVALID_PARAMETER;
> + break;
> + }
> +
> + //
> + // Set Auxiliary Control register
> + //
> + IoWrite8 (SmbusBase+R_PCH_SMBUS_AUXC, AuxcReg);
> +
> + //
> + // Reset the pointer of the internal buffer
> + //
> + IoRead8 (SmbusBase+R_PCH_SMBUS_HCTL);
> +
> + //
> + // Now that the 32 byte buffer is turned on, we can write th block data
> + // into it
> + //
> + if (Operation == SMBUS_WRITE_BLOCK) {
> + for (Index = 0; Index < BlockCount; Index++) {
> + //
> + // Write next byte
> + //
> + IoWrite8 (SmbusBase+R_PCH_SMBUS_HBD, CallBuffer[Index]);
> + }
> + }
> +
> + //
> + // Set SMBus slave address for the device to read
> + //
> + IoWrite8(SmbusBase+R_PCH_SMBUS_TSA, SlvAddrReg);
> +
> + //
> + //
> + // Set Command register for the offset to read
> + //
> + IoWrite8(SmbusBase+R_PCH_SMBUS_HCMD, HostCmdReg );
> +
> + //
> + // Set Control Register to Set "operation command" protocol and start bit
> + //
> + IoWrite8(SmbusBase+R_PCH_SMBUS_HCTL, (UINT8) (SmbusOperation +
> B_PCH_SMBUS_START));
> +
> + //
> + // Wait for IO to complete
> + //
> + do { StsReg = (UINT8) IoRead8(SmbusBase+0); } while ((StsReg &
> (BIT4|BIT3|BIT2|BIT1)) == 0);
> +
> + if (StsReg & B_PCH_SMBUS_DERR) {
> + Status = EFI_DEVICE_ERROR;
> + break;
> + } else if (StsReg & B_PCH_SMBUS_BERR) {
> + //
> + // Clear the Bus Error for another try
> + //
> + Status = EFI_DEVICE_ERROR;
> + IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BERR);
> +
> + //
> + // Clear Status Registers
> + //
> + IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
> + IoWrite8(SmbusBase+R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);
> +
> + continue;
> + }
> +
> + //
> + // successfull completion
> + // Operation Specifics (post-execution)
> + //
> + switch (Operation) {
> +
> + case SMBUS_READ_BYTE:
> + CallBuffer[0] = (UINT8)(IoRead8 (SmbusBase+R_PCH_SMBUS_HD0));
> + break;
> +
> + case SMBUS_WRITE_BLOCK:
> + IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS,
> B_PCH_SMBUS_BYTE_DONE_STS);
> + break;
> +
> + case SMBUS_READ_BLOCK:
> + BufferTooSmall = FALSE;
> +
> + //
> + // Find out how many bytes will be in the block
> + //
> + BlockCount = (UINT8)(IoRead8 (SmbusBase+R_PCH_SMBUS_HD0));
> + if (*Length < BlockCount) {
> + BufferTooSmall = TRUE;
> + } else {
> + for (Index = 0; Index < BlockCount; Index++) {
> + //
> + // Read the byte
> + //
> + CallBuffer[Index] = (UINT8)IoRead8
> (SmbusBase+R_PCH_SMBUS_HBD);
> + }
> + }
> +
> + *Length = BlockCount;
> + if (BufferTooSmall) {
> + Status = EFI_BUFFER_TOO_SMALL;
> + }
> + break;
> +
> + default:
> + break;
> + };
> +
> + if ((StsReg & B_PCH_SMBUS_BERR) && (Status == EFI_SUCCESS)) {
> + //
> + // Clear the Bus Error for another try
> + //
> + Status = EFI_DEVICE_ERROR;
> + IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BERR);
> +
> + continue;
> + } else {
> + break;
> + }
> + }
> +
> + //
> + // Clear Status Registers and exit
> + //
> + IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
> + IoWrite8(SmbusBase+R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);
> + IoWrite8(SmbusBase+R_PCH_SMBUS_AUXC, 0);
> + return Status;
> +}
> +//
> +// End::Alpine Valley platform
> +//
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/Platform.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/Platform.h
> new file mode 100644
> index 0000000000..e1817b28c6
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/Platform.h
> @@ -0,0 +1,213 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +**/
> +
> +
> +#ifndef __PEI_PLATFORM_H__
> +#define __PEI_PLATFORM_H__
> +
> +#define PEI_STALL_RESOLUTION 1
> +#define STALL_PEIM_SIGNATURE SIGNATURE_32('p','p','u','s')
> +
> +typedef struct {
> + UINT32 Signature;
> + EFI_FFS_FILE_HEADER *FfsHeader;
> + EFI_PEI_NOTIFY_DESCRIPTOR StallNotify;
> +} STALL_CALLBACK_STATE_INFORMATION;
> +
> +#define STALL_PEIM_FROM_THIS(a) CR (a,
> STALL_CALLBACK_STATE_INFORMATION, StallNotify,
> STALL_PEIM_SIGNATURE)
> +
> +#ifdef NOCS_S3_SUPPORT
> +
> +/**
> + Peform the boot mode determination logic
> + If the box is closed, then
> + 1. If it's first time to boot, it's boot with full config .
> + 2. If the ChassisIntrution is selected, force to be a boot with full config
> + 3. Otherwise it's boot with no change.
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param BootMode The detected boot mode.
> +
> + @retval EFI_SUCCESS if the boot mode could be set
> +**/
> +EFI_STATUS
> +UpdateBootMode (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +#endif
> +
> +/**
> + This function reset the entire platform, including all processor and devices,
> and
> + reboots the system.
> +
> + Declaration of this function goes to
> MdeModulePkg/Include/Library/ResetSystemLib.h
> +
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval EFI_SUCCESS if it completed successfully.
> +**/
> +// EFI_STATUS
> +// EFIAPI
> +// ResetSystem (
> + // IN CONST EFI_PEI_SERVICES **PeiServices
> + // );
> +
> +/**
> + This function will be called when MRC is done.
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param NotifyDescriptor Information about the notify event..
> + @param Ppi The notify context.
> +
> + @retval EFI_SUCCESS If the function completed successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +MemoryDiscoveredPpiNotifyCallback (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> + );
> +
> +/**
> + This is the callback function notified by FvFileLoader PPI, it depends on
> FvFileLoader PPI to load
> + the PEIM into memory.
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param NotifyDescriptor The context of notification.
> + @param Ppi The notify PPI.
> +
> + @retval EFI_SUCCESS if it completed successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvFileLoaderPpiNotifyCallback (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> + );
> +
> +/**
> + This function provides a blocking stall for reset at least the given number of
> microseconds
> + stipulated in the final argument.
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param this Pointer to the local data for the interface.
> + @param Microseconds number of microseconds for which to stall.
> +
> + @retval EFI_SUCCESS the function provided at least the required stall.
> +**/
> +EFI_STATUS
> +EFIAPI
> +Stall (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN CONST EFI_PEI_STALL_PPI *This,
> + IN UINTN Microseconds
> + );
> +
> +/**
> + This function initialize recovery functionality by installing the recovery PPI.
> +
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval EFI_SUCCESS If the interface could be successfully installed.
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeRecovery (
> + IN EFI_PEI_SERVICES **PeiServices
> + );
> +
> +/**
> + This function
> + 1. Calling MRC to initialize memory.
> + 2. Install EFI Memory.
> + 3. Capsule coalesce if capsule boot mode.
> + 4. Create HOB of system memory.
> +
> + @param PeiServices Pointer to the PEI Service Table
> +
> + @retval EFI_SUCCESS If it completes successfully.
> +
> +**/
> +EFI_STATUS
> +MemoryInit (
> + IN EFI_PEI_SERVICES **PeiServices
> + );
> +
> +/**
> + This function provides the implementation of AtaController PPI Enable
> Channel function.
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param this Pointer to the local data for the interface.
> + @param ChannelMask This parameter is used to specify primary or slavery
> IDE channel.
> +
> + @retval EFI_SUCCESS Procedure returned successfully.
> +**/
> +EFI_STATUS
> +EnableAtaChannel (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN PEI_ATA_CONTROLLER_PPI *This,
> + IN UINT8 ChannelMask
> + );
> +
> +/**
> + This function provides the implementation of AtaController PPI Get IDE
> channel Register Base Address
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param this Pointer to the local data for the interface.
> + @param IdeRegsBaseAddr Pointer to IDE_REGS_BASE_ADDR struct,
> which is used to record
> + IDE Command and Control regeisters Base Address.
> +
> + @retval EFI_SUCCESS Procedure returned successfully.
> +**/
> +EFI_STATUS
> +GetIdeRegsBaseAddr (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN PEI_ATA_CONTROLLER_PPI *This,
> + IN IDE_REGS_BASE_ADDR *IdeRegsBaseAddr
> + );
> +
> +/**
> + This function provides the implementation to properly setup both LM &
> PDM functionality.
> +
> + @param PeiServices General purpose services available to every PEIM.
> +
> + @retval EFI_SUCCESS Procedure returned successfully.
> +
> +**/
> +EFI_STATUS
> +ConfigureLM(
> + IN EFI_PEI_SERVICES **PeiServices
> + );
> +
> +#include <Ppi/VlvMmioPolicy.h>
> +
> +BOOLEAN
> +EFIAPI
> +IsFastBootEnabled (
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + );
> +
> +EFI_STATUS
> +PrioritizeBootMode (
> + IN OUT EFI_BOOT_MODE *CurrentBootMode,
> + IN EFI_BOOT_MODE NewBootMode
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +CapsulePpiNotifyCallback (
> + IN EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> + );
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/PlatformPei.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/PlatformPei.inf
> new file mode 100644
> index 0000000000..c976273ce3
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/PlatformPei.inf
> @@ -0,0 +1,129 @@
> +#
> +#
> +# Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +# This PEIM includes 3 parts, pre memory initialization, MRC
> +# wrapper and post memory initialization.
> +# On pre memory, following action is performed,
> +# 1. Initizluize GMCH.
> +# 2. Detect boot mode.
> +# 3. Detect video adapter to determine whether we need pre allocated
> +# memory.
> +#
> +# After that MRC wrapper calls MRC to initialize memory and install a PPI
> +# notify to do post memory
> +# initialization. MRC wrapper performance following actions,
> +# 1. Install EFI Memory.
> +# 2. Capsule coalesce if capsule boot mode.
> +# 3. Create HOB of system memory.
> +# Note: MRC supports 3 kinds of chipsets including Lakeport, Glenwood
> and Mukilteo,
> +# so please don't define MACRO MUKILTEO_SUPPORT on Lakeport here.
> +#
> +# On post memory, following action is performed,
> +# 1. TC initialization after MRC.
> +# 2. SIO initialization.
> +# 3. Install ResetSystem and FinvFv PPI, relocate Stall to memory on
> +# recovery boot mode.
> +# 4. Set MTRR for PEI
> +# 5. Create FV HOB and Flash HOB
> +# 6. Install RecoveryModule and AtaController PPI if on recovery boot
> mode.
> +#
> +# This PEIM does not have any register access directly, it depends on
> +# IntelTCLib, TCAccess libraries to access Chipset
> +# registers.
> +#
> +# Platform.c - Provide main flow and entrypoint of PEIM.
> +# MemoryCallback.c - Includes a memory call back function notified when
> +# MRC is done.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformPeim
> + FILE_GUID = 9618C0DC-50A4-496c-994F-7241F282ED01
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PeiInitPlatform
> + PI_SPECIFICATION_VERSION = 0x0001000A
> +
> +[sources.common]
> + Platform.c
> + Platform.h
> + MemoryCallback.c
> + CommonHeader.h
> + Stall.c
> + BootMode.c
> +
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + Vlv2SocBinPkg/Vlv2SocBinPkg.dec
> + UefiCpuPkg/UefiCpuPkg.dec
> + CryptoPkg/CryptoPkg.dec
> +
> +[LibraryClasses]
> + PeimEntryPoint
> + DebugLib
> + HobLib
> + IoLib
> + MultiPlatformLib
> + MtrrLib
> + PerformanceLib
> + MonoStatusCodeLib
> + BaseCryptLib
> + PciLib
> +
> +[Ppis]
> + gEfiPeiStallPpiGuid
> + gPeiSpeakerInterfacePpiGuid
> + gEfiPeiMemoryDiscoveredPpiGuid
> + gVlvPolicyPpiGuid
> + gEfiPeiReadOnlyVariable2PpiGuid
> + gEfiPeiResetPpiGuid
> + gEfiEndOfPeiSignalPpiGuid
> + gEfiFindFvPpiGuid
> + gPeiCapsulePpiGuid
> + gEfiPeiBootInRecoveryModePpiGuid
> + gEfiPeiRecoveryModulePpiGuid
> + gEfiPeiDeviceRecoveryModulePpiGuid
> + gPeiCachePpiGuid
> + gEfiPeiMasterBootModePpiGuid
> + gEfiPeiSmbusPpiGuid
> + gPeiMfgMemoryTestPpiGuid
> + gPeiSha256HashPpiGuid
> + gVlvMmioPolicyPpiGuid
> + gSeCfTPMPolicyPpiGuid
> +
> +[Guids]
> + gEfiSetupVariableGuid
> + gEfiPlatformInfoGuid
> + gEfiPlatformBootModeGuid
> + gEfiPlatformCpuInfoGuid
> + gEfiGlobalVariableGuid
> + gRecoveryOnFatFloppyDiskGuid
> + gRecoveryOnFatUsbDiskGuid
> + gRecoveryOnFatIdeDiskGuid
> + gRecoveryOnDataCdGuid
> + gMfgModeVariableGuid
> + gEfiNormalSetupGuid
> + gEfiVlv2VariableGuid
> +
> +[Pcd.common]
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base
> + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> + gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress
> + gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize
> +[Depex]
> + TRUE
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/Stall.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/Stall.c
> new file mode 100644
> index 0000000000..5e68f803db
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPei/Stall.c
> @@ -0,0 +1,90 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + Stall.c
> +
> +Abstract:
> +
> + Produce Stall Ppi.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +#include "PlatformBaseAddresses.h"
> +#include "PchRegs.h"
> +
> +/**
> + Waits for at least the given number of microseconds.
> +
> + @param PeiServices General purpose services available to every PEIM.
> + @param This PPI instance structure.
> + @param Microseconds Desired length of time to wait.
> +
> + @retval EFI_SUCCESS If the desired amount of time was passed.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +Stall (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN CONST EFI_PEI_STALL_PPI *This,
> + IN UINTN Microseconds
> + )
> +{
> + UINTN Ticks;
> + UINTN Counts;
> + UINT32 CurrentTick;
> + UINT32 OriginalTick;
> + UINT32 RemainingTick;
> +
> + if (Microseconds == 0) {
> + return EFI_SUCCESS;
> + }
> +
> + OriginalTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR);
> + OriginalTick &= (V_PCH_ACPI_PM1_TMR_MAX_VAL - 1);
> + CurrentTick = OriginalTick;
> +
> + //
> + // The timer frequency is 3.579545MHz, so 1 ms corresponds to 3.58 clocks
> + //
> + Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
> +
> + //
> + // The loops needed for timer overflow
> + //
> + Counts = (UINTN)RShiftU64((UINT64)Ticks, 24);
> +
> + //
> + // Remaining clocks within one loop
> + //
> + RemainingTick = Ticks & 0xFFFFFF;
> +
> + //
> + // Do not intend to use TMROF_STS bit of register PM1_STS, because this
> add extra
> + // one I/O operation, and may generate SMI
> + //
> + while (Counts != 0) {
> + CurrentTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR)
> & B_PCH_ACPI_PM1_TMR_VAL;
> + if (CurrentTick <= OriginalTick) {
> + Counts--;
> + }
> + OriginalTick = CurrentTick;
> + }
> +
> + while ((RemainingTick > CurrentTick) && (OriginalTick <= CurrentTick)) {
> + OriginalTick = CurrentTick;
> + CurrentTick = IoRead32 (ACPI_BASE_ADDRESS +
> R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL;
> + }
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkg.dec
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkg.dec
> new file mode 100644
> index 0000000000..4653f63a66
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkg.dec
> @@ -0,0 +1,211 @@
> +#/** @file
> +# Platform Package
> +#
> +# This package provides platform specific modules.
> +# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
> +#
> +
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
> +
> +#
> +#
> +#**/
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
> + PACKAGE_NAME = PlatformPkg
> + PACKAGE_GUID = 463B3B00-0D18-4a5f-90C0-D5B851D2574B
> + PACKAGE_VERSION = 0.1
> +
> +[Includes]
> + .
> + Include
> + Include/Library
> +
> +[Ppis]
> + gPeiSpeakerInterfacePpiGuid = { 0x30ac275e, 0xbb30, 0x4b84, { 0xa1, 0xcd,
> 0x0a, 0xf1, 0x32, 0x2c, 0x89, 0xc0 }}
> + gPeiUsbControllerPpiGuid = { 0x3BC1F6DE, 0x693E, 0x4547, { 0xA3, 0x00,
> 0x21, 0x82, 0x3C, 0xA4, 0x20, 0xB2 }}
> + gPeiMfgMemoryTestPpiGuid = { 0xab294a92, 0xeaf5, 0x4cf3, { 0xab,
> 0x2b, 0x2d, 0x4b, 0xed, 0x4d, 0xb6, 0x3d }}
> + gPeiSha256HashPpiGuid = { 0x950e191b, 0x8524, 0x4f51, { 0x80, 0xa1,
> 0x5c, 0x4f, 0x1b, 0x03, 0xf3, 0x5c }}
> +
> +[Guids]
> + gEfiPlatformBootModeGuid = { 0xce845704, 0x1683, 0x4d38, { 0xa4,
> 0xf9, 0x7d, 0x0b, 0x50, 0x77, 0x57, 0x93 } }
> + gEfiPlatformInfoGuid = { 0x1e2acc41, 0xe26a, 0x483d, { 0xaf, 0xc7,
> 0xa0, 0x56, 0xc3, 0x4e, 0x08, 0x7b } }
> + gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c,
> 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 } }
> + gPlatformModuleTokenSpaceGuid = { 0x69d13bf0, 0xaf91, 0x4d96,
> { 0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0 } }
> + gEfiSerialPortTokenSpaceGuid = { 0x5fad2389, 0x2bc7, 0x4bd2, { 0x83,
> 0xd3, 0x42, 0x9f, 0xb6, 0xae, 0xa3, 0x3f } }
> + gEfiIchTokenSpaceGuid = { 0xe38c11e3, 0x968f, 0x47b8, { 0xac,
> 0xef, 0xac, 0xc0, 0x69, 0x3d, 0xb9, 0xff } }
> + gEfiPchTokenSpaceGuid = { 0x89a1b278, 0xa1a1, 0x4df7, { 0xb1,
> 0x37, 0xde, 0x5a, 0xd7, 0xc4, 0x79, 0x13 } }
> + gEfiSioVariableGuid = { 0x560bf58a, 0x1e0d, 0x4d7e, { 0x95, 0x3f,
> 0x29, 0x80, 0xa2, 0x61, 0xe0, 0x31 } }
> + gProcessorProducerGuid = { 0x1bf06aea, 0x5bec, 0x4a8d, { 0x95,
> 0x76, 0x74, 0x9b, 0x09, 0x56, 0x2d, 0x30 } }
> + gEfiPowerOnHobGuid = { 0x0468a601, 0xc535, 0x46fd, { 0xa9,
> 0x5d, 0xbb, 0xab, 0x99, 0x1b, 0x17, 0x8c } }
> + gEfiPlatformCpuInfoGuid = { 0xbb9c7ab7, 0xb8d9, 0x4bf3, { 0x9c,
> 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc } }
> + gEfiBiosIdGuid = { 0xC3E36D09, 0x8294, 0x4b97, { 0xA8, 0x57,
> 0xD5, 0x28, 0x8F, 0xE3, 0x3E, 0x28 } }
> + gEfiPlatformBootModeGuid = { 0xce845704, 0x1683, 0x4d38, { 0xa4,
> 0xf9, 0x7d, 0x0b, 0x50, 0x77, 0x57, 0x93 } }
> + gEfiBoardFeaturesGuid = { 0x94b9e8ae, 0x8877, 0x479a, { 0x98,
> 0x42, 0xf5, 0x97, 0x4b, 0x82, 0xce, 0xd3 } }
> + gItkDataVarGuid = { 0x3812723d, 0x7e48, 0x4e29, { 0xbc, 0x27,
> 0xf5, 0xa3, 0x9a, 0xc9, 0x4e, 0xf1 } }
> + gDmiDataGuid = { 0x70e56c5e, 0x280c, 0x44b0, { 0xa4, 0x97,
> 0x09, 0x68, 0x1a, 0xbc, 0x37, 0x5e } }
> + gIdccDataHubGuid = { 0x788e1d9f, 0x1eab, 0x47d2, { 0xa2, 0xf3,
> 0x78, 0xca, 0xe8, 0x7d, 0x60, 0x12 } }
> + gEfiSetupVariableGuid = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1,
> 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } }
> + gEfiPlatformInfoGuid = { 0x1e2acc41, 0xe26a, 0x483d, { 0xaf, 0xc7,
> 0xa0, 0x56, 0xc3, 0x4e, 0x08, 0x7b } }
> + gMfgModeVariableGuid = { 0xEF14FD78, 0x0793, 0x4e2b, { 0xAC,
> 0x6D, 0x06, 0x28, 0x47, 0xE0, 0x17, 0x91 } }
> + gEfiAcpiTableStorageGuid = { 0x7e374e25, 0x8e01, 0x4fee, { 0x87,
> 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd } }
> + gACPIOSFRMfgStringVariableGuid = { 0x72234213, 0x0fd7, 0x48a1,
> { 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x07, 0xfb, 0xcd } }
> + gACPIOSFRRefDataBlockVariableGuid = { 0x72234213, 0x0fd7, 0x48a1,
> { 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x07, 0xfb, 0xcd } }
> + gACPIOSFRModelStringVariableGuid = { 0xca1bcad9, 0xe021, 0x4547,
> { 0xa1, 0xb0, 0x5b, 0x22, 0xc7, 0xf6, 0x87, 0xf4 } }
> + gEfiAcpiTableStorageGuid = { 0x7e374e25, 0x8e01, 0x4fee, { 0x87,
> 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd } }
> + gEfiPciLanInfoGuid = { 0x0d9a1427, 0xe02a, 0x437d, { 0x92, 0x6b,
> 0xaa, 0x52, 0x1f, 0xd7, 0x22, 0xba } }
> + gEfiNormalSetupGuid = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1,
> 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } }
> + gFirmwareIdGuid = { 0x5e559c23, 0x1faa, 0x4ae1, { 0x8d, 0x4a,
> 0xc6, 0xcf, 0x02, 0x6c, 0x76, 0x6f } }
> + gBmpImageGuid = { 0x878AC2CC, 0x5343, 0x46F2, { 0xB5, 0x63,
> 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } }
> + gOsSelectionVariableGuid = { 0x86843f56, 0x675d, 0x40a5, { 0x95,
> 0x30, 0xbc, 0x85, 0x83, 0x72, 0xf1, 0x03 } }
> +
> +[Protocols]
> + gEfiActiveBiosProtocolGuid = { 0xebbe2d1b, 0x1647, 0x4bda, { 0xab,
> 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a } }
> + gEfiPlatformCpuProtocolGuid = { 0xbd26cdc9, 0xa092, 0x462a, { 0x87,
> 0x7a, 0x5a, 0xb6, 0xad, 0xce, 0x48, 0x12 } }
> + gDxePchPlatformPolicyProtocolGuid = { 0x4b0165a9, 0x61d6, 0x4e23,
> { 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 } }
> + gEfiTpmMpDriverProtocolGuid = { 0xde161cfe, 0x1e60, 0x42a1, { 0x8c,
> 0xc3, 0xee, 0x7e, 0xf0, 0x73, 0x52, 0x12 } }
> + gEfiLpcWpce791PolicyProtocolGuid = { 0xab2bee2f, 0xc1a6, 0x4399,
> { 0x85, 0x3d, 0xc0, 0x7c, 0x77, 0x4f, 0xfd, 0x0d } }
> + gUsbPolicyGuid = { 0xf617b358, 0x12cf, 0x414a, { 0xa0, 0x69,
> 0x60, 0x67, 0x7b, 0xda, 0x13, 0xb4 } }
> + gEfiSpeakerInterfaceProtocolGuid = { 0x400b4476, 0x3081, 0x11d6,
> { 0x87, 0xed, 0x00, 0x06, 0x29, 0x45, 0xc3, 0xb9 } }
> + gDxeVlvPlatformPolicyGuid = { 0x5bab88ba, 0xe0e2, 0x4674, { 0xb6,
> 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c, 0xd6 } }
> + gEfiSmbiosSlotPopulationGuid = { 0xef7bf7d6, 0xf8ff, 0x4a76, { 0x82,
> 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 } }
> + gObservableProtocolGuid = { 0xe227c522, 0xd5fe, 0x4a53, { 0x87,
> 0xb1, 0x0f, 0xbe, 0x57, 0x0f, 0x98, 0xe9 } }
> + gEfiCk505ClockPlatformInfoGuid = { 0x3c485ea4, 0x449a, 0x46ce,
> { 0xbb, 0x08, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e } }
> + gEfiLpcWpc83627PolicyProtocolGuid = { 0xd3ecc567, 0x9fd5, 0x44c1,
> { 0x86, 0xcf, 0x5d, 0xa7, 0xa2, 0x4f, 0x4b, 0x5d } }
> + gEfiTcoResetProtocolGuid = { 0xa6a79162, 0xe325, 0x4c30, { 0xbc,
> 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3 } }
> + gEfiWatchdogTimerDriverProtocolGuid = { 0xd5b06d16, 0x2ea1, 0x4def,
> { 0x98, 0xd0, 0xa0, 0x5d, 0x40, 0x72, 0x84, 0x17 } }
> + gEfiPlatformIdeInitProtocolGuid = { 0x377c66a3, 0x8fe7, 0x4ee8, { 0x85,
> 0xb8, 0xf1, 0xa2, 0x82, 0x56, 0x9e, 0x3b } }
> + gEfiPciPlatformProtocolGuid = { 0x07d75280, 0x27d4, 0x4d69, { 0x90,
> 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41 } }
> + gEnhancedSpeedstepProtocolGuid = { 0x91a1ddcf, 0x5374, 0x4939,
> { 0x89, 0x51, 0xd7, 0x29, 0x3f, 0x1a, 0x78, 0x6f } }
> + gEfiAcpiSupportProtocolGuid = { 0xdbff9d55, 0x89b7, 0x46da, { 0xbd,
> 0xdf, 0x67, 0x7d, 0x3d, 0xc0, 0x24, 0x1d } }
> + gEfiAcpiS3SaveProtocolGuid = { 0x125f2de1, 0xfb85, 0x440c, { 0xa5,
> 0x4c, 0x4d, 0x99, 0x35, 0x8a, 0x8d, 0x38 } }
> + gEfiCpuIoProtocolGuid = { 0xB0732526, 0x38C8, 0x4b40, { 0x88,
> 0x77, 0x61, 0xC7, 0xB0, 0x6A, 0xAC, 0x45 } }
> + gPlatformGOPPolicyGuid = { 0xec2e931b, 0x3281, 0x48a5, { 0x81,
> 0x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d } }
> + gEfiGopDisplayBrightnessProtocolGuid = { 0x6ff23f1d, 0x877c, 0x4b1b,
> { 0x93, 0xfc, 0xf1, 0x42, 0xb2, 0xee, 0xa6, 0xa7 } }
> + gEfiUsbKeyboardConnectGuid = { 0xad9c4381, 0x1ede, 0x430c,
> { 0x8d, 0x42, 0x23, 0x76, 0x7c, 0x46, 0x5d, 0x52 } }
> +
> +
> +[PcdsFixedAtBuild]
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageBase|0xFFF60000|UIN
> T32|0x20000007
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageSize|0x00010000|UIN
> T32|0x20000008
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageEventLogBase|0xFFF6
> C000|UINT32|0x30000007
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageEventLogSize|0x00002
> 000|UINT32|0x30000008
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|0xFFF80000|UI
> NT32|0x20000004
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize|0x00080000|UI
> NT32|0x20000005
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashFvShellBase|0xFFF50000|UINT32
> |0x20000009
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashFvShellSize|0x00000000|UINT32
> |0x20000010
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|0xFF800000|UINT3
> 2|0x20000001
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize|0x00500000|UINT32
> |0x20000002
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|U
> INT32|0x10000001
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0
> x10000002
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashTestMenuBase|0xFF000000|UIN
> T32|0x20000011
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashTestMenuSize|0x00010000|UINT
> 32|0x20000012
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|0xFFFA0000|
> UINT32|0x20000013
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size|0x00040000|UI
> NT32|0x20000014
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|0xFFF90000|
> UINT32|0x20000015
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize|0x00002000|UIN
> T32|0x20000016
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashMicroCode2Address|0xFFF92000
> |UINT32|0x20000017
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashMicroCode2Size|0x0000C800|UI
> NT32|0x20000018
> +
> gPlatformModuleTokenSpaceGuid.PcdIFWISigBaseAddress|0x0F00|UINT32|
> 0x20000019
> +
> gPlatformModuleTokenSpaceGuid.PcdPBTNDisableInterval|0x01F4|UINT32|
> 0x2000001A
> +
> gPlatformModuleTokenSpaceGuid.PcdTouchAttributes|2|UINT32|0x200000
> 20
> +
> gPlatformModuleTokenSpaceGuid.PcdTouchCIDString|"I2C05\\S004A"|VOID
> *|0x20000021
> + gPlatformModuleTokenSpaceGuid.PcdFullIconFile |{ 0x69, 0x00,
> 0x39, 0x82, 0x30, 0xa6, 0x4b, 0x4c, 0x85, 0xfc, 0x95, 0xe9, 0x49, 0xc9, 0xf0,
> 0x76 }|VOID*|0x20000022
> + gPlatformModuleTokenSpaceGuid.PcdSimpleIconFile |{ 0x4b, 0xf7,
> 0xee, 0x4b, 0x30, 0xa3, 0x49, 0x67, 0xa4, 0xad, 0xa4, 0xb1, 0xca, 0xe4, 0x4b,
> 0x0d }|VOID*|0x20000023
> + gPlatformModuleTokenSpaceGuid.PcdCapitalLetterKeyboardFile|{ 0x82,
> 0x38, 0x75, 0xd8, 0x83, 0xa2, 0x4c, 0x37, 0xb6, 0xea, 0x04, 0xac, 0xc3, 0x06,
> 0x0f, 0x07 }|VOID*|0x20000024
> + gPlatformModuleTokenSpaceGuid.PcdSmallLetterKeyboardFile |{ 0x4c,
> 0x66, 0x39, 0xa2, 0x09, 0x0e, 0x4d, 0xc9, 0x9f, 0x55, 0x0f, 0xcb, 0x72, 0x60,
> 0x26, 0x11 }|VOID*|0x20000025
> + gPlatformModuleTokenSpaceGuid.PcdDigitKeyboardFile |{ 0x3f, 0xfe,
> 0x2c, 0x17, 0x92, 0x5d, 0x49, 0x7d, 0x87, 0x0a, 0x46, 0x14, 0xe4, 0x58, 0xd8,
> 0x5e }|VOID*|0x20000026
> + gPlatformModuleTokenSpaceGuid.PcdSimpleKeyboardFile |{ 0x5c,
> 0xd4, 0xfc, 0x98, 0xbf, 0x79, 0x41, 0x10, 0xa2, 0xd3, 0x87, 0xbe, 0x82, 0xd0,
> 0x90, 0x52 }|VOID*|0x20000027
> +
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashSpidOffset|0x1000|UINT32|0x20
> 00002A
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashSpidSize|0x00001000|UINT32|0x
> 2000002B
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashEmOffset|0x3000|UINT32|0x200
> 0002C
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashEmSize|0x1000|UINT32|0x20000
> 02D
> +
> +
> gEfiSerialPortTokenSpaceGuid.PcdSerialRegisterBase|0x3f8|UINT64|0x00000
> 001
> +
> gEfiSerialPortTokenSpaceGuid.PcdSerialBoudRate|115200|UINT32|0x000000
> 02
> +
> +
> gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress|0x400|UINT16|0x00
> 00000B
> +
> + ## FFS filename to find the shell application.
> + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6,
> 0x7A, 0xC5, 0x15, 0x05, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E,
> 0x37 }|VOID*|0x40000004
> +
> +
> gEfiIchTokenSpaceGuid.PcdPeiIchUhciControllerIoPortBaseAddress|0x4000|
> UINT16|0x30000017
> +
> gEfiIchTokenSpaceGuid.PcdPeiIchEhciControllerMemoryBaseAddress|0xFC0
> 00000|UINT32|0x30000019
> +
> +
> +
> gPlatformModuleTokenSpaceGuid.PcdRamLogBaseAddress|0x20000|UINT3
> 2|0x00000013
> +
> gPlatformModuleTokenSpaceGuid.PcdRamLogBaseLength|0x80000|UINT32
> |0x00000014
> +
> gPlatformModuleTokenSpaceGuid.PcdRamLogBaseCarAddress|0xFEF86000|
> UINT32|0x00000015
> +
> gPlatformModuleTokenSpaceGuid.PcdRamLogBaseCarLength|0x2000|UINT3
> 2|0x00000016
> +
> +
> + #Pcd for Flash Update tool
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashChipBase|0xFF800000|UINT32|0
> x40000001
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashChipSize|0x00800000|UINT32|0x
> 40000002
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase|0xFF800000|UIN
> T32|0x40000003
> +
> gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize|0x00001000|UINT
> 32|0x40000004
> +
> gPlatformModuleTokenSpaceGuid.PcdTxeRomBase|0xFF801000|UINT32|0x
> 40000009
> +
> gPlatformModuleTokenSpaceGuid.PcdTxeRomSize|0x003FF000|UINT32|0x4
> 000000A
> +
> gPlatformModuleTokenSpaceGuid.PcdBiosRomBase|0xFFC00000|UINT32|0x
> 4000000B
> +
> gPlatformModuleTokenSpaceGuid.PcdBiosRomSize|0x00400000|UINT32|0x
> 4000000C
> +
> + # PCDs for System Firmware FMP instance
> +
> gPlatformModuleTokenSpaceGuid.PcdSystemFirmwareFmpLowestSupporte
> dVersion|0x00000000|UINT32|0x40000100
> +
> gPlatformModuleTokenSpaceGuid.PcdSystemFirmwareFmpVersion|0x00000
> 000|UINT32|0x40000101
> +
> gPlatformModuleTokenSpaceGuid.PcdSystemFirmwareFmpVersionString|""
> |VOID*|0x40000102
> +
> +[PcdsFeatureFlag]
> + ## This PCD specifies whether StatusCode is reported via ISA Serial port.
> +
> gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|TRUE|BOOLEAN|
> 0x00000020
> +
> + ## This PCD specifies whether StatusCode is reported via USB Serial port.
> +
> gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|TRUE|BOOLEAN
> |0x00000021
> +
> + ## This PCD specifies whether StatusCode is reported via RAM.
> +
> gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|FALSE|BOOLEAN|0x0
> 0000022
> +
> + ## Platform BDS PCD to control whether to dispatch additional option rom,
> e.g.: PXE, AHCI
> +
> gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|TRUE|B
> OOLEAN|0x00000024
> +
> + #new added feature for BIOS usb recovery
> +
> gEfiIchTokenSpaceGuid.PcdEhciRecoveryEnabled|TRUE|BOOLEAN|0x000000
> 26
> +
> +[PcdsDynamic,PcdsDynamicEx]
> +
> gPlatformModuleTokenSpaceGuid.PcdInConfigMode|FALSE|BOOLEAN|0x80
> 000001
> +
> gPlatformModuleTokenSpaceGuid.PcdConnectUSBKeyboardonWaitForKeyS
> troke|FALSE|BOOLEAN|0x80000002
> +
> gPlatformModuleTokenSpaceGuid.PcdEnableWatchdogSwSmiInputValue|0|
> UINT8|0x80000003
> +#
> +#device firmware update support
> +#
> +#I2C and SPI support
> +[Protocols]
> +
> + gEfiMmioDeviceProtocolGuid = { 0x24486226, 0xf8c2, 0x41f5, { 0xb9, 0xdd,
> 0x78, 0x3e, 0x9e, 0x56, 0xde, 0xa0 } }
> + gEfiI2cBusConfigurationManagementProtocolGuid = { 0x75032015, 0xd156,
> 0x423e, { 0xbf, 0xa3, 0x7a, 0x65, 0xab, 0xa4, 0x71, 0x5 } }
> + gEfiI2cAcpiProtocolGuid = { 0xf30c2915, 0x5782, 0x4e6a, { 0xa8, 0x46, 0x5,
> 0xba, 0xbc, 0xe7, 0xb6, 0xa0 } }
> + gEfiI2cMasterProtocolGuid = { 0x578c315a, 0x68cf, 0x4e81, { 0xb5, 0xc6,
> 0x22, 0xdb, 0x40, 0xd0, 0x10, 0xbc } }
> + gEfiI2cHostProtocolGuid = { 0x70b221af, 0xfdff, 0x4fde, { 0x99, 0x68, 0x1a,
> 0xf6, 0x23, 0xa9, 0x56, 0xd9 } }
> + gEfiI2cBusProtocolGuid = { 0x9fa1b225, 0x3346, 0x461b, { 0xa0, 0x69, 0xed,
> 0x1, 0xb6, 0x73, 0xd2, 0x40 } }
> + gEfiI2cSlaveProtocolGuid = { 0xf2c1910e, 0xf5c9, 0x4b72, { 0xb2, 0x43, 0x6d,
> 0x59, 0x9, 0x6a, 0x79, 0xf0 } }
> +
> +# gEfiSpiAcpiProtocolGuid = { 0x9f49a879, 0x3d71, 0x42b3, { 0xa0, 0xad,
> 0xdd, 0xb1, 0xf3, 0x30, 0x10, 0xa3 } }
> +# gEfiSpiHostProtocolGuid = { 0x951b65e5, 0x8872, 0x41ed, { 0xad, 0x1d,
> 0xd5, 0x68, 0x1f, 0x4a, 0xf0, 0x33 } }
> +# gEfiSpiBusProtocolGuid = { 0x137b3044, 0xf6d7, 0x473e, { 0xa6, 0x25, 0x9f,
> 0xb9, 0x25, 0x5, 0xc1, 0x80 } }
> +
> +# gLpssDummyProtocolGuid = { 0xaf4cc162, 0xd41c, 0x455a, { 0xab, 0x45,
> 0x6d, 0xbc, 0xc1, 0xcd, 0x32, 0xf3 } }
> + gEfiSpiProtocolGuid = { 0x1156efc6, 0xea32, 0x4396, { 0xb5, 0xd5,
> 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 }}
> + gEfiGpioOperationProtocolGuid = { 0x38DDFE8F, 0x8991, 0x44AA, { 0x98,
> 0x89, 0x83, 0xF4, 0x91, 0x84, 0x65, 0xB0 }}
> + gEfiEsrtOperationProtocolGuid = { 0x4549AB47, 0x6E60, 0x4293, { 0xB9,
> 0x1D, 0x31, 0xB6, 0x10, 0xAD, 0x80, 0x56 }}
> +
> +[Guids]
> + gEfiFwDisplayCapsuleGuid = { 0x3b8c8162, 0x188c, 0x46a4, { 0xae, 0xc9,
> 0xbe, 0x43, 0xf1, 0xd6, 0x56, 0x97 } }
> + gEfiFirmwareClassGuid = { 0xb122a262, 0x3551, 0x4f48, { 0x88, 0x92,
> 0x55, 0xf6, 0xc0, 0x61, 0x42, 0x90 } }
> + gEfiDFUVerGuid = { 0x0dc73aed, 0xcbf6, 0x4a25, { 0xa6, 0x8d, 0x59,
> 0xc8, 0x0f, 0x44, 0xc7, 0xc3 } }
> + gEfiEsrtTableGuid = { 0xb122a263, 0x3661, 0x4f68, { 0x99, 0x29, 0x78,
> 0xf8, 0xb0, 0xd6, 0x21, 0x80 } }
> + gEfiCapsuleCrashLogVarGuid = { 0xf3ff1468, 0x04ba, 0x4966, { 0x9f, 0xb2,
> 0xe4, 0xa7, 0x90, 0x05, 0x46, 0x50 } }
> + gEfiCapsuleCrashGuid = { 0x0e1d2972, 0x65af, 0x4ac1, { 0xbf, 0xa3,
> 0xce, 0xf4, 0xab, 0x0c, 0x38, 0xfe } }
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkg.fdf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkg.fdf
> new file mode 100644
> index 0000000000..098602b9d8
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkg.fdf
> @@ -0,0 +1,1073 @@
> +#/** @file
> +# FDF file of Platform.
> +#
> +# Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#**/
> +
> +[Defines]
> +DEFINE FLASH_BASE = 0xFFC00000 #The base address of the 4Mb
> FLASH Device.
> +DEFINE FLASH_SIZE = 0x00400000 #The flash size in bytes of the 4Mb
> FLASH Device.
> +DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 4Mb
> FLASH Device.
> +DEFINE FLASH_NUM_BLOCKS = 0x400 #The number of blocks in 4Mb
> FLASH Device.
> +DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
> +DEFINE FLASH_AREA_SIZE = 0x00800000
> +
> +DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
> +DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00040000
> +DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFC00000
> +
> +DEFINE FLASH_REGION_VPD_OFFSET = 0x00040000
> +DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
> +
> +DEFINE
> FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET =
> 0x0007E000
> +DEFINE
> FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE =
> 0x00002000
> +
> +
> +DEFINE
> FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET =
> 0x00080000
> +DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE
> = 0x00040000
> +
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x000C0000
> +DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
> +DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFCC0000
> +
> +DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x00108000
> +DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
> +DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFD08000
> +
> +!endif
> +
> +DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00110000
> +DEFINE FLASH_REGION_FVMAIN_SIZE = 0x00210000
> +
> +DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x00320000
> +DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x00070000
> +
> +DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x00390000
> +DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x00070000
> +
> +#########################################################
> #######################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +#########################################################
> #######################
> +[FD.Vlv]
> +BaseAddress =
> $(FLASH_BASE)|gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddre
> ss #The base address of the 3Mb FLASH Device.
> +Size =
> $(FLASH_SIZE)|gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize
> #The flash size in bytes of the 3Mb FLASH Device.
> +ErasePolarity = 1
> +BlockSize = $(FLASH_BLOCK_SIZE) #The block size in bytes of the 3Mb
> FLASH Device.
> +NumBlocks = $(FLASH_NUM_BLOCKS) #The number of blocks in 3Mb
> FLASH Device.
> +
> +#
> +#Flash location override based on actual flash map
> +#
> +SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress =
> $(FLASH_AREA_BASE_ADDRESS)
> +SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize =
> $(FLASH_AREA_SIZE)
> +
> +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(FLASH_REGION_VLVMICROCODE_BASE) + 0x60
> +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(FLASH_REGION_VLVMICROCODE_SIZE) - 0x60
> +
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +# put below PCD value setting into dsc file
> +#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress
> = $(FLASH_REGION_VLVMICROCODE_BASE)
> +#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
> = $(FLASH_REGION_VLVMICROCODE_SIZE)
> +#SET gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset =
> 0x60
> +#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =
> $(FLASH_AREA_BASE_ADDRESS)
> +#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize =
> $(FLASH_AREA_SIZE)
> +#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase =
> $(FLASH_REGION_FSPBIN_BASE)
> +#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize =
> $(FLASH_REGION_FSPBIN_SIZE)
> +
> +!endif
> +#########################################################
> #######################
> +#
> +# Following are lists of FD Region layout which correspond to the locations
> of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required)
> followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with
> the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +# Fv Size can be adjusted; FVMAIN_COMPACT can be reduced to 0x120000,
> and FV_RECOVERY can be enlarged to 0x80000
> +#
> +#########################################################
> #######################
> + #
> + # CPU Microcodes
> + #
> +
> +$(FLASH_REGION_VLVMICROCODE_OFFSET)|$(FLASH_REGION_VLVMICR
> OCODE_SIZE)
> +gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|gPlatform
> ModuleTokenSpaceGuid.PcdFlashMicroCodeSize
> +FV = MICROCODE_FV
> +$(FLASH_REGION_VPD_OFFSET)|$(FLASH_REGION_VPD_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfi
> MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> + ## This is the EFI_FIRMWARE_VOLUME_HEADER
> + # ZeroVector []
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # FileSystemGuid: gEfiSystemNvDataFvGuid =
> + # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F,
> 0x50 }}
> + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> + # FvLength: 0x80000
> + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
> + #Signature "_FVH" #Attributes
> + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
> + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
> + 0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02,
> + #Blockmap[0]: 7 Blocks * 0x10000 Bytes / Block
> + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
> + #Blockmap[1]: End
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + ## This is the VARIABLE_STORE_HEADER
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + #Signature: gEfiAuthenticatedVariableGuid =
> + # { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77,
> 0x92 }}
> + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
> + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
> +!else
> + #Signature: gEfiVariableGuid =
> + # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe,
> 0x7d }}
> + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
> + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
> +!endif
> + #Size: 0x3E000
> (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48
> (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x03DFB8
> + # This can speed up the Variable Dispatch a bit.
> + 0xB8, 0xDF, 0x03, 0x00,
> + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1:
> UINT32
> + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +
> +$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET
> )|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|g
> EfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =
> gEdkiiWorkingBlockSignatureGuid =
> + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b,
> 0x95 }}
> + 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
> + 0xA0, 0xCE, 0x65, 0x0, 0xFD, 0x9F, 0x1B, 0x95,
> +
> + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
> + 0xE2, 0x33, 0xF2, 0x3, 0xFE, 0xFF, 0xFF, 0xFF,
> + # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER)
> = 0x1FE0
> + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET)|$(
> FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfi
> MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +
> + $(FLASH_REGION_FSPBIN_OFFSET)|$(FLASH_REGION_FSPBIN_SIZE)
> +
> gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|gFspWrapperTokenSpace
> Guid.PcdFlashFvFspSize
> + FILE = Vlv2SocBinPkg/FspBinary/FvFsp.bin
> +
> +
> +
> $(FLASH_REGION_AZALIABIN_OFFSET)|$(FLASH_REGION_AZALIABIN_SIZE)
> + FILE = Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin
> +
> +!endif
> +
> + #
> + # Main Block
> + #
> +$(FLASH_REGION_FVMAIN_OFFSET)|$(FLASH_REGION_FVMAIN_SIZE)
> +gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|gPlatformModule
> TokenSpaceGuid.PcdFlashFvMainSize
> +FV = FVMAIN_COMPACT
> +
> + #
> + # FV Recovery#2
> + #
> +$(FLASH_REGION_FV_RECOVERY2_OFFSET)|$(FLASH_REGION_FV_RECOV
> ERY2_SIZE)
> +gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|gPlatformM
> oduleTokenSpaceGuid.PcdFlashFvRecovery2Size
> +FV = FVRECOVERY2
> +
> + #
> + # FV Recovery
> + #
> +$(FLASH_REGION_FV_RECOVERY_OFFSET)|$(FLASH_REGION_FV_RECOVE
> RY_SIZE)
> +gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|gPlatformMo
> duleTokenSpaceGuid.PcdFlashFvRecoverySize
> +FV = FVRECOVERY
> +
> +#########################################################
> #######################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed
> within a flash
> +# device file. This section also defines order the components and modules
> are positioned
> +# within the image. The [FV] section consists of define statements, set
> statements and
> +# module statements.
> +#
> +#########################################################
> #######################
> +[FV.MICROCODE_FV]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = FALSE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> +FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
> +
> $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITEC
> TURE)/MicrocodeUpdates.bin
> +}
> +
> +!if $(RECOVERY_ENABLE)
> +[FV.FVRECOVERY_COMPONENTS]
> +FvAlignment = 16 #FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chUsb.inf
> +INF MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf
> +INF MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf
> +INF MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf
> +INF FatPkg/FatPei/FatPei.inf
> +INF MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf
> +INF
> SignedCapsulePkg/Universal/RecoveryModuleLoadPei/RecoveryModuleLoa
> dPei.inf
> +!endif
> +
> +#########################################################
> #######################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed
> within a flash
> +# device file. This section also defines order the components and modules
> are positioned
> +# within the image. The [FV] section consists of define statements, set
> statements and
> +# module statements.
> +#
> +#########################################################
> #######################
> +[FV.FVRECOVERY2]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16 #FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092
> +
> +
> +
> +INF $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf
> +
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chSmbusArpDisabled.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Vl
> vInitPeim.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chInitPeim.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chSpiPeim.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> eiSmmAccess.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> eiSmmControl.inf
> +INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/M
> pS3.inf
> +!endif
> +
> +# INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Pi
> SmmCommunicationPei.inf
> +!if $(TPM_ENABLED) == TRUE
> +INF SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf
> +INF SecurityPkg/Tcg/TcgPei/TcgPei.inf
> +INF SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
> +!endif
> +!if $(FTPM_ENABLE) == TRUE
> +INF SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf #use PCD config
> +!endif
> +INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +
> +!if $(ACPI50_ENABLE) == TRUE
> + INF
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/Firmwa
> rePerformancePei.inf
> +!endif
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +INF
> MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCode
> RouterPei.inf
> +!endif
> +
> +!if $(RECOVERY_ENABLE)
> +FILE FV_IMAGE = 1E9D7604-EF45-46a0-BD8A-71AC78C17AC1 {
> + SECTION PEI_DEPEX_EXP = {gEfiPeiMemoryDiscoveredPpiGuid AND
> gEfiPeiBootInRecoveryModePpiGuid}
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF { # LZMA
> COMPRESS GUID
> + SECTION FV_IMAGE = FVRECOVERY_COMPONENTS
> + }
> +}
> +!endif
> +
> +[FV.FVRECOVERY]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16 #FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270091
> +
> +
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +INF IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf
> +!else
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/S
> ecCore.inf
> +!endif
> +
> +INF MdeModulePkg/Core/Pei/PeiMain.inf
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +INF Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
> +INF IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
> +!endif
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/C
> puPeim.inf
> +INF
> MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> +INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> +
> +INF $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf
> +
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/S
> eCUma.inf
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fT
> PMInitPeim.inf
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> + INF SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf
> +!endif
> +
> +
> +!if $(CAPSULE_ENABLE) == TRUE
> +INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
> +!if $(DXE_ARCHITECTURE) == "X64"
> +INF MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf
> +!endif
> +!endif
> +
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> +!if $(PCIESC_ENABLE) == TRUE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chEarlyInitPeim.inf
> +!endif
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/M
> emoryInit.inf
> +!endif
> +
> +INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> +
> +[FV.FVMAIN]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
> +
> +APRIORI DXE {
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> + INF
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportSt
> atusCodeRouterRuntimeDxe.inf
> + INF
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHan
> dlerRuntimeDxe.inf
> + }
> +
> +FILE FREEFORM = C3E36D09-8294-4b97-A857-D5288FE33E28 {
> + SECTION RAW =
> $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITEC
> TURE)/BiosId.bin
> + }
> +
> + #
> + # EDK II Related Platform codes
> + #
> +
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> + INF IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
> + !endif
> +
> +INF MdeModulePkg/Core/Dxe/DxeMain.inf
> +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +!if $(ACPI50_ENABLE) == TRUE
> +INF
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/Firmw
> arePerformanceDxe.inf
> +INF
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/Firm
> warePerformanceSmm.inf
> +!endif
> +
> +
> +INF IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
> +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
> +INF
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportSt
> atusCodeRouterRuntimeDxe.inf
> +INF
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHan
> dlerRuntimeDxe.inf
> +INF
> MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCod
> eRouterSmm.inf
> +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> +INF UefiCpuPkg/CpuDxe/CpuDxe.inf
> +INF $(PLATFORM_PACKAGE)/Metronome/Metronome.inf
> +INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
> +!if $(ARCH) == IA32
> +INF USE=IA32 MdeModulePkg/Logo/Logo.inf
> +!else
> +INF USE=X64 MdeModulePkg/Logo/Logo.inf
> +!endif
> +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> +INF
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.in
> f
> +INF
> IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.i
> nf
> +
> +INF
> MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.i
> nf
> +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
> +INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
> +INF
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.i
> nf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSpiSmm.inf
> +!if $(SECURE_BOOT_ENABLE)
> +INF
> SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfi
> gDxe.inf
> +!endif
> +
> +INF
> MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +
> +INF
> MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCoun
> terRuntimeDxe.inf
> +INF
> PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime
> Dxe.inf
> +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> +INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf
> +
> +
> +INF $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf
> +
> +!if $(DATAHUB_ENABLE) == TRUE
> +INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf
> +!endif
> +INF
> IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandl
> erDxe/DatahubStatusCodeHandlerDxe.inf
> +INF
> MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryT
> estDxe.inf
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/Dptf.inf
> +
> + #
> + # EDK II Related Silicon codes
> + #
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchS3SupportDxe.inf
> +
> +!if $(USE_HPET_TIMER) == TRUE
> +INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
> +!else
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmartTimer.inf
> +!endif
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmmControl.inf
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSmbusDxe.inf
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/IntelPchLegacyInterrupt.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchReset.inf
> +
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchInitDxe.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchInitSmm.inf
> +!endif
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSmiDispatcher.inf
> +!if $(PCIESC_ENABLE) == TRUE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchPcieSmm.inf
> +!endif
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSpiRuntime.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchPolicyInitDxe.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchBiosWriteProtect.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmmAccess.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PciHostBridge.inf
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/VlvInitDxe.inf
> +!else
> +INF
> IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.i
> nf
> +INF Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf
> +!endif
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> + !if $(SEC_ENABLE) == TRUE
> + INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/HeciDrv.inf
> + INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SeCPolicyInitDxe.inf
> + !endif
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> +INF SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf
> +INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf
> +INF RuleOverride = DRIVER_ACPITABLE
> SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
> +!endif
> +!if $(FTPM_ENABLE) == TRUE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/T
> pm2DeviceSeCPei.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/Tpm2DeviceSeCDxe.inf
> +INF SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf
> +INF SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/FtpmSmm.inf
> +!endif
> +
> +#
> +# EDK II Related Platform codes
> +#
> +INF $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf
> +INF $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf
> +INF $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
> +INF $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf
> +INF $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf
> +INF $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PlatformCpuPolicy.inf
> +INF $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf
> +INF
> $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHand
> lerSmm.inf
> +!if $(GOP_DRIVER_ENABLE) == TRUE
> + INF $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf
> + FILE DRIVER = FF0C8745-3270-4439-B74F-3E45F8C77064 {
> + SECTION DXE_DEPEX_EXP = {gPlatformGOPPolicyGuid}
> + SECTION PE32 =
> Vlv2SocBinPkg/GOP/7.2.1011/RELEASE_VS2008x86/$(DXE_ARCHITECTURE)/I
> ntelGopDriver.efi
> + SECTION UI = "IntelGopDriver"
> +}
> +!endif
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PnpDxe.inf
> + #
> + # SMM
> + #
> +INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
> +INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
> +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
> +
> +INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
> +INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
> +INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
> +INF
> $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmS
> wDispatch2OnSmmSwDispatchThunk.inf
> +
> +#
> +# Remove the following two SMM binary modules that prevent platform
> from booting to UEFI Shell
> +#
> +#INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PowerManagement2.inf
> +#INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/DigitalThermalSensor.inf
> +
> + #
> + # ACPI
> + #
> +INF
> MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutor
> Dxe.inf
> +INF $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf
> +INF
> IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDx
> e.inf
> +INF RuleOverride = ACPITABLE2
> Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTable
> s/PowerManagementAcpiTables.inf
> +
> +INF RuleOverride = ACPITABLE
> $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf
> +
> +INF $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf
> +
> +INF
> MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraph
> icsResourceTableDxe.inf
> +
> + #
> + # PCI
> + #
> +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/ISPDxe.inf
> +
> +
> +#
> +# ISA
> +#
> +INF $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf
> +INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
> +INF IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf
> +!if $(SOURCE_DEBUG_ENABLE) != TRUE
> +INF IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
> +!endif
> +#INF IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
> +#INF
> IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
> +
> +#
> +# SDIO
> +#
> +#INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MmcHost.inf
> +#INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MmcMediaDevice.inf
> +#
> +# IDE/SCSI/AHCI
> +#
> +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> +
> +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> +
> +INF
> MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> +!if $(SATA_ENABLE) == TRUE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SataController.inf
> +#
> +
> +#
> +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +!if $(SCSI_ENABLE) == TRUE
> +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +!endif
> +#
> +!endif
> +# Console
> +#
> +INF
> MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> +INF
> MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleD
> xe.inf
> +INF
> IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.in
> f
> +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + #
> + # USB
> + #
> +!if $(USB_ENABLE) == TRUE
> +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> +INF
> MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> +INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
> +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> +!endif
> +
> +
> + #
> + # SMBIOS
> + #
> +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
> +INF $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmbiosMemory.inf
> +
> +
> +#
> +# FAT file system
> +#
> +INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> +#
> +# UEFI Shell
> +#
> +INF ShellPkg/Application/Shell/Shell.inf
> +
> +#
> +# dp command
> +#
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +INF
> ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf
> +!endif
> +
> +!if $(GOP_DRIVER_ENABLE) == TRUE
> +FILE FREEFORM = 878AC2CC-5343-46F2-B563-51F89DAF56BA {
> + SECTION RAW = Vlv2SocBinPkg/GOP/7.2.1011/VBT/MNW2/Vbt.bin
> + SECTION UI = "IntelGopVbt"
> +}
> +!endif
> +
> +#
> +# Network Modules
> +#
> +!if $(NETWORK_ENABLE) == TRUE
> + FILE DRIVER = 22DE1691-D65D-456a-993E-A253DD1F308C {
> + SECTION PE32 =
> Vlv2SocBinPkg/UNDI/RtkUndiDxe/$(DXE_ARCHITECTURE)/RtkUndiDxe.efi
> + SECTION UI = "UNDI"
> + }
> + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + INF NetworkPkg/TcpDxe/TcpDxe.inf
> + !if $(NETWORK_IP6_ENABLE) == TRUE
> + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + !endif
> + !if $(NETWORK_VLAN_ENABLE) == TRUE
> + INF
> MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + !endif
> + !if $(NETWORK_ISCSI_ENABLE) == TRUE
> + INF NetworkPkg/IScsiDxe/IScsiDxe.inf
> + !endif
> +!endif
> +
> +!if $(CAPSULE_ENABLE)
> +INF MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf
> +
> +#
> +# Minnow Max System Firmware FMP
> +#
> +INF FILE_GUID = $(FMP_MINNOW_MAX_SYSTEM)
> FmpDevicePkg/FmpDxe/FmpDxe.inf
> +
> +#
> +# Sample Device FMP
> +#
> +INF FILE_GUID = $(FMP_GREEN_SAMPLE_DEVICE)
> FmpDevicePkg/FmpDxe/FmpDxe.inf
> +INF FILE_GUID = $(FMP_BLUE_SAMPLE_DEVICE)
> FmpDevicePkg/FmpDxe/FmpDxe.inf
> +INF FILE_GUID = $(FMP_RED_SAMPLE_DEVICE)
> FmpDevicePkg/FmpDxe/FmpDxe.inf
> +
> +!endif
> +
> +!if $(MICOCODE_CAPSULE_ENABLE)
> +INF
> IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdateDx
> e.inf
> +!endif
> +
> +!if $(RECOVERY_ENABLE)
> +FILE FREEFORM =
> PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiRsa2048Sha256TestPubli
> cKeyFileGuid) {
> + SECTION RAW =
> BaseTools/Source/Python/Rsa2048Sha256Sign/TestSigningPublicKey.bin
> + SECTION UI = "Rsa2048Sha256TestSigningPublicKey"
> + }
> +!endif
> +
> +[FV.FVMAIN_COMPACT]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> +
> +
> +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> +!if $(LZMA_ENABLE) == TRUE
> +# LZMA Compress
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> +!else
> +!if $(DXE_COMPRESS_ENABLE) == TRUE
> +# Tiano Compress
> + SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779
> PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> +!else
> +# No Compress
> + SECTION COMPRESS PI_NONE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> +!endif
> +!endif
> + }
> +
> +[FV.SETUP_DATA]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +#NumBlocks = 0x10
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> +#########################################################
> #######################
> +#
> +# Rules are use with the [FV] section's module INF type to define
> +# how an FFS file is created for a given INF file. The following Rule are the
> default
> +# rules for the different module type. User can add the customized rules to
> define the
> +# content of the FFS file.
> +#
> +#########################################################
> #######################
> +[Rule.Common.SEC]
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> + PE32 PE32 Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + RAW BIN Align = 16 |.com
> + }
> +
> +[Rule.Common.SEC.BINARY]
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> + PE32 PE32 Align = 8 |.efi
> + RAW BIN Align = 16 |.com
> + }
> +
> +[Rule.Common.PEI_CORE]
> + FILE PEI_CORE = $(NAMED_GUID) {
> + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.PEIM]
> + FILE PEIM = $(NAMED_GUID) {
> + PEI_DEPEX PEI_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.PEIM.BINARY]
> + FILE PEIM = $(NAMED_GUID) {
> + PEI_DEPEX PEI_DEPEX Optional |.depex
> + PE32 PE32 Align = Auto |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.PEIM.BIOSID]
> + FILE PEIM = $(NAMED_GUID) {
> + RAW BIN BiosId.bin
> + PEI_DEPEX PEI_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.USER_DEFINED.APINIT]
> + FILE RAW = $(NAMED_GUID) Fixed Align=4K {
> + RAW SEC_BIN |.com
> + }
> +#cjia 2011-07-21
> +[Rule.Common.USER_DEFINED.LEGACY16]
> + FILE FREEFORM = $(NAMED_GUID) {
> + UI STRING="$(MODULE_NAME)" Optional
> + RAW BIN |.bin
> + }
> +#cjia
> +
> +[Rule.Common.USER_DEFINED.ASM16]
> + FILE FREEFORM = $(NAMED_GUID) {
> + UI STRING="$(MODULE_NAME)" Optional
> + RAW BIN |.com
> + }
> +
> +[Rule.Common.DXE_CORE]
> + FILE DXE_CORE = $(NAMED_GUID) {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_DRIVER.BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_DRIVER.NATIVE_BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.de
> pex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_DRIVER.BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_DRIVER.DRIVER_ACPITABLE]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + RAW ACPI Optional |.acpi
> + RAW ASL Optional |.aml
> + }
> +
> +[Rule.Common.DXE_RUNTIME_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_RUNTIME_DRIVER.BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_SMM_DRIVER]
> + FILE SMM = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_SMM_DRIVER.BINARY]
> + FILE SMM = $(NAMED_GUID) {
> + SMM_DEPEX SMM_DEPEX |.depex
> + PE32 PE32 |.efi
> + RAW BIN Optional |.aml
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_SMM_DRIVER.DRIVER_ACPITABLE]
> + FILE SMM = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + RAW ACPI Optional |.acpi
> + RAW ASL Optional |.aml
> + }
> +
> +[Rule.Common.SMM_CORE]
> + FILE SMM_CORE = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.SMM_CORE.BINARY]
> + FILE SMM_CORE = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_APPLICATION]
> + FILE APPLICATION = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_APPLICATION.UI]
> + FILE APPLICATION = $(NAMED_GUID) {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="Enter Setup"
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.USER_DEFINED]
> + FILE FREEFORM = $(NAMED_GUID) {
> + UI STRING="$(MODULE_NAME)" Optional
> + RAW BIN |.bin
> + }
> +
> +[Rule.Common.USER_DEFINED.BINARY]
> + FILE FREEFORM = $(NAMED_GUID) {
> + UI STRING="$(MODULE_NAME)" Optional
> + RAW BIN |.bin
> + }
> +
> +[Rule.Common.USER_DEFINED.ACPITABLE]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW ACPI Optional |.acpi
> + RAW ASL Optional |.aml
> + }
> +
> +[Rule.Common.USER_DEFINED.ACPITABLE2]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW ASL Optional |.aml
> + }
> +
> +[Rule.Common.ACPITABLE]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW ACPI Optional |.acpi
> + RAW ASL Optional |.aml
> + }
> +
> +[Rule.Common.PEIM.FMP_IMAGE_DESC]
> + FILE PEIM = $(NAMED_GUID) {
> + RAW BIN |.acpi
> + PEI_DEPEX PEI_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgConfig.dsc
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgConfig.dsc
> new file mode 100644
> index 0000000000..6d556c1be2
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgConfig.dsc
> @@ -0,0 +1,107 @@
> +#/** @file
> +# platform configuration file.
> +#
> +# Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#**/
> +
> +#
> +# TRUE is ENABLE. FASLE is DISABLE.
> +#
> +
> +#
> +# FSP selection
> +#
> +DEFINE MINNOW2_FSP_BUILD = FALSE
> +
> +
> +DEFINE SCSI_ENABLE = TRUE
> +
> +
> +#
> +# To enable extra configuration for clk gen
> +#
> +DEFINE CLKGEN_CONFIG_EXTRA_ENABLE=TRUE
> +
> +#
> +# Feature selection
> +#
> +
> +#
> +# Select system timer which is used to produce Timer Arch Protocol:
> +# TRUE - HPET timer is used.
> +# FALSE - 8254 timer is used.
> +#
> +DEFINE USE_HPET_TIMER = TRUE
> +
> +
> +#
> +# Feature selection
> +#
> +
> +DEFINE TPM_ENABLED = FALSE
> +
> +DEFINE ACPI50_ENABLE = TRUE
> +DEFINE PERFORMANCE_ENABLE = FALSE
> +
> +
> +DEFINE LFMA_ENABLE = FALSE # Load module at fixed address
> feature
> +DEFINE DXE_COMPRESS_ENABLE = TRUE
> +DEFINE DXE_CRC32_SECTION_ENABLE = TRUE
> +DEFINE SSE2_ENABLE = FALSE
> +
> +DEFINE SECURE_BOOT_ENABLE = TRUE
> +DEFINE USER_IDENTIFICATION_ENABLE = FALSE
> +DEFINE VARIABLE_INFO_ENABLE = FALSE
> +DEFINE S3_ENABLE = TRUE
> +DEFINE CAPSULE_ENABLE = TRUE
> +DEFINE CAPSULE_RESET_ENABLE = TRUE
> +DEFINE RECOVERY_ENABLE = FALSE
> +DEFINE MICOCODE_CAPSULE_ENABLE = TRUE
> +
> +DEFINE GOP_DRIVER_ENABLE = TRUE
> +DEFINE DATAHUB_ENABLE = TRUE
> +DEFINE DATAHUB_STATUS_CODE_ENABLE = TRUE
> +DEFINE USB_ENABLE = TRUE
> +
> +DEFINE ISA_SERIAL_STATUS_CODE_ENABLE = TRUE
> +DEFINE USB_SERIAL_STATUS_CODE_ENABLE = FALSE
> +DEFINE RAM_SERIAL_STATUS_CODE_ENABLE = FALSE
> +
> +DEFINE ENBDT_S3_SUPPORT = TRUE
> +
> +DEFINE LZMA_ENABLE = TRUE
> +DEFINE S4_ENABLE = TRUE
> +DEFINE NETWORK_ENABLE = TRUE
> +DEFINE NETWORK_IP6_ENABLE = TRUE
> +DEFINE NETWORK_ISCSI_ENABLE = FALSE
> +DEFINE NETWORK_VLAN_ENABLE = FALSE
> +
> +DEFINE SATA_ENABLE = TRUE
> +DEFINE PCIESC_ENABLE = TRUE
> +
> +#
> +# Enable source level debug default
> +#
> +DEFINE SOURCE_DEBUG_ENABLE = FALSE
> +
> +#
> +# Capsule Pubic Certificate. Default is EDK_TEST. Options are:
> +# SAMPLE_DEVELOPMENT - Only signtool
> SAMPLE_DEVELOPMENT
> +# SAMPLE_DEVELOPMENT_SAMPLE_PRODUCTION - Both signtool
> SAMPLE_DEVELOPMENT and SAMPLE_PRODUCTION
> +# EDKII_TEST - Only openssl EDK II test certificate
> +# NEW_ROOT - Only openssl new VLV2 certificate
> +#
> +DEFINE CAPSULE_PKCS7_CERT = EDKII_TEST
> +
> +#
> +# Define ESRT GUIDs for Firmware Management Protocol instances
> +#
> +DEFINE FMP_MINNOW_MAX_SYSTEM = 4096267b-da0a-42eb-b5eb-
> fef31d207cb4
> +DEFINE FMP_RED_SAMPLE_DEVICE = 72E2945A-00DA-448E-9AA7-
> 075AD840F9D4
> +DEFINE FMP_BLUE_SAMPLE_DEVICE = 149DA854-7D19-4FAA-A91E-
> 862EA1324BE6
> +DEFINE FMP_GREEN_SAMPLE_DEVICE = 79179BFD-704D-4C90-9E02-
> 0AB8D968C18A
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf
> new file mode 100644
> index 0000000000..1ba6124a69
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf
> @@ -0,0 +1,1033 @@
> +#/** @file
> +# FDF file of Platform.
> +#
> +# Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#**/
> +
> +[Defines]
> +DEFINE FLASH_BASE = 0xFFC00000 #The base address of the 4Mb
> FLASH Device.
> +DEFINE FLASH_SIZE = 0x00400000 #The flash size in bytes of the 4Mb
> FLASH Device.
> +DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 4Mb
> FLASH Device.
> +DEFINE FLASH_NUM_BLOCKS = 0x400 #The number of blocks in 4Mb
> FLASH Device.
> +DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
> +DEFINE FLASH_AREA_SIZE = 0x00800000
> +
> +DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
> +DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00040000
> +DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFC00000
> +
> +DEFINE FLASH_REGION_VPD_OFFSET = 0x00040000
> +DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
> +
> +DEFINE
> FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET =
> 0x0007E000
> +DEFINE
> FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE =
> 0x00002000
> +
> +
> +DEFINE
> FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET =
> 0x00080000
> +DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE
> = 0x00040000
> +
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x000C0000
> +DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
> +DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFCC0000
> +
> +DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x00108000
> +DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
> +DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFD08000
> +
> +!endif
> +
> +DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00110000
> +DEFINE FLASH_REGION_FVMAIN_SIZE = 0x00215000
> +
> +DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x00325000
> +DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0006B000
> +
> +DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x00390000
> +DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x00070000
> +
> +#########################################################
> #######################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +#########################################################
> #######################
> +[FD.Vlv]
> +BaseAddress =
> $(FLASH_BASE)|gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddre
> ss #The base address of the 3Mb FLASH Device.
> +Size =
> $(FLASH_SIZE)|gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize
> #The flash size in bytes of the 3Mb FLASH Device.
> +ErasePolarity = 1
> +BlockSize = $(FLASH_BLOCK_SIZE) #The block size in bytes of the 3Mb
> FLASH Device.
> +NumBlocks = $(FLASH_NUM_BLOCKS) #The number of blocks in 3Mb
> FLASH Device.
> +
> +#
> +#Flash location override based on actual flash map
> +#
> +SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress =
> $(FLASH_AREA_BASE_ADDRESS)
> +SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize =
> $(FLASH_AREA_SIZE)
> +
> +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(FLASH_REGION_VLVMICROCODE_BASE) + 0x60
> +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(FLASH_REGION_VLVMICROCODE_SIZE) - 0x60
> +
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +# put below PCD value setting into dsc file
> +#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress
> = $(FLASH_REGION_VLVMICROCODE_BASE)
> +#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
> = $(FLASH_REGION_VLVMICROCODE_SIZE)
> +#SET gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset =
> 0x60
> +#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =
> $(FLASH_AREA_BASE_ADDRESS)
> +#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize =
> $(FLASH_AREA_SIZE)
> +#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase =
> $(FLASH_REGION_FSPBIN_BASE)
> +#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize =
> $(FLASH_REGION_FSPBIN_SIZE)
> +
> +!endif
> +#########################################################
> #######################
> +#
> +# Following are lists of FD Region layout which correspond to the locations
> of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required)
> followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with
> the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +# Fv Size can be adjusted; FVMAIN_COMPACT can be reduced to 0x120000,
> and FV_RECOVERY can be enlarged to 0x80000
> +#
> +#########################################################
> #######################
> +# Since the Fce tool don't have gcc version, we can't handle default variable
> in Linux,
> +# so we hardcode the default value of variable here.
> +# Please note that we MUST update the binary once the default value is
> changed.
> +
> +#
> + # CPU Microcodes
> + #
> +
> +$(FLASH_REGION_VLVMICROCODE_OFFSET)|$(FLASH_REGION_VLVMICR
> OCODE_SIZE)
> +gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|gPlatform
> ModuleTokenSpaceGuid.PcdFlashMicroCodeSize
> +FV = MICROCODE_FV
> +$(FLASH_REGION_VPD_OFFSET)|$(FLASH_REGION_VPD_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfi
> MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +FILE = Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageVariable.bin
> +
> +$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET
> )|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|g
> EfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +FILE = Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwWorking.bin
> +
> +$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET)|$(
> FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfi
> MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +FILE = Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwSpare.bin
> +
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +
> + $(FLASH_REGION_FSPBIN_OFFSET)|$(FLASH_REGION_FSPBIN_SIZE)
> +
> gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|gFspWrapperTokenSpace
> Guid.PcdFlashFvFspSize
> + FILE = Vlv2SocBinPkg/FspBinary/FvFsp.bin
> +
> +
> +
> $(FLASH_REGION_AZALIABIN_OFFSET)|$(FLASH_REGION_AZALIABIN_SIZE)
> + FILE = Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin
> +
> +!endif
> +
> + #
> + # Main Block
> + #
> +$(FLASH_REGION_FVMAIN_OFFSET)|$(FLASH_REGION_FVMAIN_SIZE)
> +gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|gPlatformModule
> TokenSpaceGuid.PcdFlashFvMainSize
> +FV = FVMAIN_COMPACT
> +
> + #
> + # FV Recovery#2
> + #
> +$(FLASH_REGION_FV_RECOVERY2_OFFSET)|$(FLASH_REGION_FV_RECOV
> ERY2_SIZE)
> +gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|gPlatformM
> oduleTokenSpaceGuid.PcdFlashFvRecovery2Size
> +FV = FVRECOVERY2
> +
> + #
> + # FV Recovery
> + #
> +$(FLASH_REGION_FV_RECOVERY_OFFSET)|$(FLASH_REGION_FV_RECOVE
> RY_SIZE)
> +gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|gPlatformMo
> duleTokenSpaceGuid.PcdFlashFvRecoverySize
> +FV = FVRECOVERY
> +
> +#########################################################
> #######################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed
> within a flash
> +# device file. This section also defines order the components and modules
> are positioned
> +# within the image. The [FV] section consists of define statements, set
> statements and
> +# module statements.
> +#
> +#########################################################
> #######################
> +[FV.MICROCODE_FV]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = FALSE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> +FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
> +
> $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITEC
> TURE)/MicrocodeUpdates.bin
> +}
> +
> +!if $(RECOVERY_ENABLE)
> +[FV.FVRECOVERY_COMPONENTS]
> +FvAlignment = 16 #FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chUsb.inf
> +INF MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf
> +INF MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf
> +INF MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf
> +INF FatPkg/FatPei/FatPei.inf
> +INF MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf
> +INF
> SignedCapsulePkg/Universal/RecoveryModuleLoadPei/RecoveryModuleLoa
> dPei.inf
> +!endif
> +
> +#########################################################
> #######################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed
> within a flash
> +# device file. This section also defines order the components and modules
> are positioned
> +# within the image. The [FV] section consists of define statements, set
> statements and
> +# module statements.
> +#
> +#########################################################
> #######################
> +[FV.FVRECOVERY2]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16 #FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092
> +
> +
> +
> +INF $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf
> +
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chSmbusArpDisabled.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Vl
> vInitPeim.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chInitPeim.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chSpiPeim.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> eiSmmAccess.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> eiSmmControl.inf
> +INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/M
> pS3.inf
> +!endif
> +
> +# INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Pi
> SmmCommunicationPei.inf
> +!if $(TPM_ENABLED) == TRUE
> +INF SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf
> +INF SecurityPkg/Tcg/TcgPei/TcgPei.inf
> +INF SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
> +!endif
> +!if $(FTPM_ENABLE) == TRUE
> +INF SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf #use PCD config
> +!endif
> +INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +
> +!if $(ACPI50_ENABLE) == TRUE
> + INF
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/Firmwa
> rePerformancePei.inf
> +!endif
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +INF
> MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCode
> RouterPei.inf
> +!endif
> +
> +!if $(RECOVERY_ENABLE)
> +FILE FV_IMAGE = 1E9D7604-EF45-46a0-BD8A-71AC78C17AC1 {
> + SECTION PEI_DEPEX_EXP = {gEfiPeiMemoryDiscoveredPpiGuid AND
> gEfiPeiBootInRecoveryModePpiGuid}
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF { # LZMA
> COMPRESS GUID
> + SECTION FV_IMAGE = FVRECOVERY_COMPONENTS
> + }
> +}
> +!endif
> +
> +[FV.FVRECOVERY]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16 #FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270091
> +
> +
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +INF IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf
> +!else
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/S
> ecCore.inf
> +!endif
> +
> +INF MdeModulePkg/Core/Pei/PeiMain.inf
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +INF Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
> +INF IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
> +!endif
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/C
> puPeim.inf
> +INF
> MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> +INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> +
> +INF $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf
> +
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/S
> eCUma.inf
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fT
> PMInitPeim.inf
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> + INF SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf
> +!endif
> +
> +
> +!if $(CAPSULE_ENABLE) == TRUE
> +INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
> +!if $(DXE_ARCHITECTURE) == "X64"
> +INF MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf
> +!endif
> +!endif
> +
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> +!if $(PCIESC_ENABLE) == TRUE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chEarlyInitPeim.inf
> +!endif
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/M
> emoryInit.inf
> +!endif
> +
> +INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> +
> +[FV.FVMAIN]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
> +
> +APRIORI DXE {
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> + INF
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportSt
> atusCodeRouterRuntimeDxe.inf
> + INF
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHan
> dlerRuntimeDxe.inf
> + }
> +
> +FILE FREEFORM = C3E36D09-8294-4b97-A857-D5288FE33E28 {
> + SECTION RAW =
> $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITEC
> TURE)/BiosId.bin
> + }
> +
> + #
> + # EDK II Related Platform codes
> + #
> +
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> + INF IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
> + !endif
> +
> +INF MdeModulePkg/Core/Dxe/DxeMain.inf
> +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +!if $(ACPI50_ENABLE) == TRUE
> +INF
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/Firmw
> arePerformanceDxe.inf
> +INF
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/Firm
> warePerformanceSmm.inf
> +!endif
> +
> +
> +INF IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
> +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
> +INF
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportSt
> atusCodeRouterRuntimeDxe.inf
> +INF
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHan
> dlerRuntimeDxe.inf
> +INF
> MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCod
> eRouterSmm.inf
> +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> +INF UefiCpuPkg/CpuDxe/CpuDxe.inf
> +INF $(PLATFORM_PACKAGE)/Metronome/Metronome.inf
> +INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
> +!if $(ARCH) == IA32
> +INF USE=IA32 MdeModulePkg/Logo/Logo.inf
> +!else
> +INF USE=X64 MdeModulePkg/Logo/Logo.inf
> +!endif
> +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> +INF
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.in
> f
> +INF
> IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.i
> nf
> +
> +INF
> MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.i
> nf
> +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
> +INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
> +INF
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.i
> nf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSpiSmm.inf
> +!if $(SECURE_BOOT_ENABLE)
> +INF
> SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfi
> gDxe.inf
> +!endif
> +
> +INF
> MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +
> +INF
> MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCoun
> terRuntimeDxe.inf
> +INF
> PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime
> Dxe.inf
> +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> +INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf
> +
> +
> +INF $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf
> +
> +!if $(DATAHUB_ENABLE) == TRUE
> +INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf
> +!endif
> +INF
> IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandl
> erDxe/DatahubStatusCodeHandlerDxe.inf
> +INF
> MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryT
> estDxe.inf
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/Dptf.inf
> +
> + #
> + # EDK II Related Silicon codes
> + #
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchS3SupportDxe.inf
> +
> +!if $(USE_HPET_TIMER) == TRUE
> +INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
> +!else
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmartTimer.inf
> +!endif
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmmControl.inf
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSmbusDxe.inf
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/IntelPchLegacyInterrupt.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchReset.inf
> +
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchInitDxe.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchInitSmm.inf
> +!endif
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSmiDispatcher.inf
> +!if $(PCIESC_ENABLE) == TRUE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchPcieSmm.inf
> +!endif
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSpiRuntime.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchPolicyInitDxe.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchBiosWriteProtect.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmmAccess.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PciHostBridge.inf
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/VlvInitDxe.inf
> +!else
> +INF
> IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.i
> nf
> +INF Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf
> +!endif
> +!if $(MINNOW2_FSP_BUILD) == FALSE
> + !if $(SEC_ENABLE) == TRUE
> + INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/HeciDrv.inf
> + INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SeCPolicyInitDxe.inf
> + !endif
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> +INF SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf
> +INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf
> +INF RuleOverride = DRIVER_ACPITABLE
> SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
> +!endif
> +!if $(FTPM_ENABLE) == TRUE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/T
> pm2DeviceSeCPei.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/Tpm2DeviceSeCDxe.inf
> +INF SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf
> +INF SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/FtpmSmm.inf
> +!endif
> +
> +#
> +# EDK II Related Platform codes
> +#
> +INF $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf
> +INF $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf
> +INF $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
> +INF $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf
> +INF $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf
> +INF $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PlatformCpuPolicy.inf
> +INF $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf
> +INF
> $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHand
> lerSmm.inf
> +!if $(GOP_DRIVER_ENABLE) == TRUE
> + INF $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf
> + FILE DRIVER = FF0C8745-3270-4439-B74F-3E45F8C77064 {
> + SECTION DXE_DEPEX_EXP = {gPlatformGOPPolicyGuid}
> + SECTION PE32 =
> Vlv2SocBinPkg/GOP/7.2.1011/RELEASE_VS2008x86/$(DXE_ARCHITECTURE)/I
> ntelGopDriver.efi
> + SECTION UI = "IntelGopDriver"
> +}
> +!endif
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PnpDxe.inf
> + #
> + # SMM
> + #
> +INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
> +INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
> +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
> +
> +INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
> +INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
> +INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
> +INF
> $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmS
> wDispatch2OnSmmSwDispatchThunk.inf
> +
> +#
> +# Remove the following two SMM binary modules that prevent platform
> from booting to UEFI Shell
> +#
> +#INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PowerManagement2.inf
> +#INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/DigitalThermalSensor.inf
> +
> + #
> + # ACPI
> + #
> +INF
> MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutor
> Dxe.inf
> +INF $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf
> +INF
> IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDx
> e.inf
> +INF RuleOverride = ACPITABLE2
> Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTable
> s/PowerManagementAcpiTables.inf
> +
> +INF RuleOverride = ACPITABLE
> $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf
> +
> +INF $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf
> +
> +INF
> MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraph
> icsResourceTableDxe.inf
> +
> + #
> + # PCI
> + #
> +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/ISPDxe.inf
> +
> +
> +#
> +# ISA
> +#
> +INF $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf
> +INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
> +INF IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf
> +!if $(SOURCE_DEBUG_ENABLE) != TRUE
> +INF IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
> +!endif
> +#INF IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
> +#INF
> IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
> +
> +#
> +# SDIO
> +#
> +#INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MmcHost.inf
> +#INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MmcMediaDevice.inf
> +#
> +# IDE/SCSI/AHCI
> +#
> +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> +
> +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> +
> +INF
> MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> +!if $(SATA_ENABLE) == TRUE
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SataController.inf
> +#
> +
> +#
> +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +!if $(SCSI_ENABLE) == TRUE
> +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +!endif
> +#
> +!endif
> +# Console
> +#
> +INF
> MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> +INF
> MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleD
> xe.inf
> +INF
> IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.in
> f
> +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + #
> + # USB
> + #
> +!if $(USB_ENABLE) == TRUE
> +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> +INF
> MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> +INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
> +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> +!endif
> +
> +
> + #
> + # SMBIOS
> + #
> +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
> +INF $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf
> +
> +INF RuleOverride = BINARY
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmbiosMemory.inf
> +
> +
> +#
> +# FAT file system
> +#
> +INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> +#
> +# UEFI Shell
> +#
> +INF ShellPkg/Application/Shell/Shell.inf
> +
> +#
> +# dp command
> +#
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +INF
> ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf
> +!endif
> +
> +!if $(GOP_DRIVER_ENABLE) == TRUE
> +FILE FREEFORM = 878AC2CC-5343-46F2-B563-51F89DAF56BA {
> + SECTION RAW = Vlv2SocBinPkg/GOP/7.2.1011/VBT/MNW2/Vbt.bin
> + SECTION UI = "IntelGopVbt"
> +}
> +!endif
> +
> +#
> +# Network Modules
> +#
> +!if $(NETWORK_ENABLE) == TRUE
> + FILE DRIVER = 22DE1691-D65D-456a-993E-A253DD1F308C {
> + SECTION PE32 =
> Vlv2SocBinPkg/UNDI/RtkUndiDxe/$(DXE_ARCHITECTURE)/RtkUndiDxe.efi
> + SECTION UI = "UNDI"
> + }
> + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + INF NetworkPkg/TcpDxe/TcpDxe.inf
> + !if $(NETWORK_IP6_ENABLE) == TRUE
> + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + !endif
> + !if $(NETWORK_VLAN_ENABLE) == TRUE
> + INF
> MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + !endif
> + !if $(NETWORK_ISCSI_ENABLE) == TRUE
> + INF NetworkPkg/IScsiDxe/IScsiDxe.inf
> + !endif
> +!endif
> +
> +!if $(CAPSULE_ENABLE)
> +INF MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf
> +
> +#
> +# Minnow Max System Firmware FMP
> +#
> +INF FILE_GUID = $(FMP_MINNOW_MAX_SYSTEM)
> FmpDevicePkg/FmpDxe/FmpDxe.inf
> +
> +#
> +# Sample Device FMP
> +#
> +INF FILE_GUID = $(FMP_GREEN_SAMPLE_DEVICE)
> FmpDevicePkg/FmpDxe/FmpDxe.inf
> +INF FILE_GUID = $(FMP_BLUE_SAMPLE_DEVICE)
> FmpDevicePkg/FmpDxe/FmpDxe.inf
> +INF FILE_GUID = $(FMP_RED_SAMPLE_DEVICE)
> FmpDevicePkg/FmpDxe/FmpDxe.inf
> +
> +!endif
> +
> +!if $(MICOCODE_CAPSULE_ENABLE)
> +INF
> IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdateDx
> e.inf
> +!endif
> +
> +!if $(RECOVERY_ENABLE)
> +FILE FREEFORM =
> PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiRsa2048Sha256TestPubli
> cKeyFileGuid) {
> + SECTION RAW =
> BaseTools/Source/Python/Rsa2048Sha256Sign/TestSigningPublicKey.bin
> + SECTION UI = "Rsa2048Sha256TestSigningPublicKey"
> + }
> +!endif
> +
> +[FV.FVMAIN_COMPACT]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> +
> +
> +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> +!if $(LZMA_ENABLE) == TRUE
> +# LZMA Compress
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> +!else
> +!if $(DXE_COMPRESS_ENABLE) == TRUE
> +# Tiano Compress
> + SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779
> PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> +!else
> +# No Compress
> + SECTION COMPRESS PI_NONE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> +!endif
> +!endif
> + }
> +
> +[FV.SETUP_DATA]
> +BlockSize = $(FLASH_BLOCK_SIZE)
> +#NumBlocks = 0x10
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> +#########################################################
> #######################
> +#
> +# Rules are use with the [FV] section's module INF type to define
> +# how an FFS file is created for a given INF file. The following Rule are the
> default
> +# rules for the different module type. User can add the customized rules to
> define the
> +# content of the FFS file.
> +#
> +#########################################################
> #######################
> +[Rule.Common.SEC]
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> + PE32 PE32 Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + RAW BIN Align = 16 |.com
> + }
> +
> +[Rule.Common.SEC.BINARY]
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> + PE32 PE32 Align = 8 |.efi
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> + RAW RAW |.raw
> +!else
> + RAW BIN Align = 16 |.com
> +!endif
> + }
> +
> +[Rule.Common.PEI_CORE]
> + FILE PEI_CORE = $(NAMED_GUID) {
> + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.PEIM]
> + FILE PEIM = $(NAMED_GUID) {
> + PEI_DEPEX PEI_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.PEIM.BINARY]
> + FILE PEIM = $(NAMED_GUID) {
> + PEI_DEPEX PEI_DEPEX Optional |.depex
> + PE32 PE32 Align = Auto |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.PEIM.BIOSID]
> + FILE PEIM = $(NAMED_GUID) {
> + RAW BIN BiosId.bin
> + PEI_DEPEX PEI_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.USER_DEFINED.APINIT]
> + FILE RAW = $(NAMED_GUID) Fixed Align=4K {
> + RAW SEC_BIN |.com
> + }
> +#cjia 2011-07-21
> +[Rule.Common.USER_DEFINED.LEGACY16]
> + FILE FREEFORM = $(NAMED_GUID) {
> + UI STRING="$(MODULE_NAME)" Optional
> + RAW BIN |.bin
> + }
> +#cjia
> +
> +[Rule.Common.USER_DEFINED.ASM16]
> + FILE FREEFORM = $(NAMED_GUID) {
> + UI STRING="$(MODULE_NAME)" Optional
> + RAW BIN |.com
> + }
> +
> +[Rule.Common.DXE_CORE]
> + FILE DXE_CORE = $(NAMED_GUID) {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_DRIVER.BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_DRIVER.NATIVE_BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.de
> pex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_DRIVER.BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_DRIVER.DRIVER_ACPITABLE]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + RAW ACPI Optional |.acpi
> + RAW ASL Optional |.aml
> + }
> +
> +[Rule.Common.DXE_RUNTIME_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_RUNTIME_DRIVER.BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_SMM_DRIVER]
> + FILE SMM = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_SMM_DRIVER.BINARY]
> + FILE SMM = $(NAMED_GUID) {
> + SMM_DEPEX SMM_DEPEX |.depex
> + PE32 PE32 |.efi
> + RAW BIN Optional |.aml
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.DXE_SMM_DRIVER.DRIVER_ACPITABLE]
> + FILE SMM = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + RAW ACPI Optional |.acpi
> + RAW ASL Optional |.aml
> + }
> +
> +[Rule.Common.SMM_CORE]
> + FILE SMM_CORE = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.SMM_CORE.BINARY]
> + FILE SMM_CORE = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_APPLICATION]
> + FILE APPLICATION = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_APPLICATION.UI]
> + FILE APPLICATION = $(NAMED_GUID) {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="Enter Setup"
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.USER_DEFINED]
> + FILE FREEFORM = $(NAMED_GUID) {
> + UI STRING="$(MODULE_NAME)" Optional
> + RAW BIN |.bin
> + }
> +
> +[Rule.Common.USER_DEFINED.BINARY]
> + FILE FREEFORM = $(NAMED_GUID) {
> + UI STRING="$(MODULE_NAME)" Optional
> + RAW BIN |.bin
> + }
> +
> +[Rule.Common.USER_DEFINED.ACPITABLE]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW ACPI Optional |.acpi
> + RAW ASL Optional |.aml
> + }
> +
> +[Rule.Common.USER_DEFINED.ACPITABLE2]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW ASL Optional |.aml
> + }
> +
> +[Rule.Common.ACPITABLE]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW ACPI Optional |.acpi
> + RAW ASL Optional |.aml
> + }
> +
> +[Rule.Common.PEIM.FMP_IMAGE_DESC]
> + FILE PEIM = $(NAMED_GUID) {
> + RAW BIN |.acpi
> + PEI_DEPEX PEI_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> + }
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc
> new file mode 100644
> index 0000000000..b9faf558b7
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc
> @@ -0,0 +1,1711 @@
> +#/** @file
> +# Platform description.
> +#
> +# Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#**/
> +
> +#########################################################
> #######################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +#########################################################
> #######################
> +[Defines]
> + PLATFORM_NAME = Vlv2TbltDevicePkg
> + PLATFORM_GUID = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x00010005
> +
> + #
> + # Set platform specific package/folder name, same as passed from
> PREBUILD script.
> + # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well
> as package build folder
> + # DEFINE only takes effect at R9 DSC and FDF.
> + #
> + DEFINE PLATFORM_PACKAGE = Vlv2TbltDevicePkg
> + DEFINE PLATFORM_RC_PACKAGE = Vlv2DeviceRefCodePkg
> + DEFINE PLATFORM_BINARY_PACKAGE = Vlv2SocBinPkg
> + OUTPUT_DIRECTORY = Build/$(PLATFORM_PACKAGE)
> + SUPPORTED_ARCHITECTURES = IA32|X64
> + BUILD_TARGETS = DEBUG|RELEASE
> + SKUID_IDENTIFIER = DEFAULT
> +
> + DEFINE CPU_ARCH =ValleyView2
> + DEFINE PROJECT_SC_FAMILY =IntelPch
> + DEFINE PROJECT_SC_ROOT
> =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/SouthCluster
> + DEFINE PROJECT_VLV_ROOT
> =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/NorthCluster
> +
> + DEFINE RC_BINARY_RELEASE = TRUE
> + #
> + # Platform On/Off features are defined here
> + #
> + #
> + # Platform Support:: Set only one token except Crestview Hills
> + #
> + # 3.BayleyBay
> + # ENBDT_PF_ENABLE = TRUE
> + #
> + !include $(PLATFORM_PACKAGE)/AutoPlatformCFG.txt
> + !include $(PLATFORM_PACKAGE)/PlatformPkgConfig.dsc
> +
> +!if $(X64_CONFIG) == TRUE
> + DEFINE DXE_ARCHITECTURE = X64
> + DEFINE EDK_DXE_ARCHITECTURE = X64
> + DEFINE UNDI_DXE_ARCHITECTURE = 64
> +!else
> + DEFINE DXE_ARCHITECTURE = IA32
> + DEFINE EDK_DXE_ARCHITECTURE = Ia32
> + DEFINE UNDI_DXE_ARCHITECTURE = 32
> +!endif
> +
> + FLASH_DEFINITION =
> $(PLATFORM_PACKAGE)/PlatformPkgGcc.fdf
> +!if $(LFMA_ENABLE) == TRUE
> + FIX_LOAD_TOP_MEMORY_ADDRESS = 0xFFFFFFFFFFFFFFFF
> + DEFINE TOP_MEMORY_ADDRESS = 0xFFFFFFFFFFFFFFFF
> +!else
> + FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
> + DEFINE TOP_MEMORY_ADDRESS = 0x0
> +!endif
> +
> + DEFINE PLATFORM_PCIEXPRESS_BASE = 0E0000000
> +
> + DEFINE SEC_ENABLE = FALSE
> + DEFINE SEC_DEBUG_INFO_ENABLE = FALSE
> + DEFINE FTPM_ENABLE = FALSE
> +
> +#########################################################
> #######################
> +#
> +# SKU Identification section - list of all SKU IDs supported by this
> +# Platform.
> +#
> +#########################################################
> #######################
> +[SkuIds]
> + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
> +
> +#########################################################
> #######################
> +#
> +# Library Class section - list of all Library Classes needed by this Platform.
> +#
> +#########################################################
> #######################
> +[LibraryClasses.common]
> + #
> + # Entry point
> + #
> +
> PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.in
> f
> + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
> +
> DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint
> .inf
> +
> UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry
> Point.inf
> +
> UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA
> pplicationEntryPoint.inf
> +
> DxeSmmDriverEntryPoint|IntelFrameworkPkg/Library/DxeSmmDriverEntryP
> oint/DxeSmmDriverEntryPoint.inf
> +
> + #
> + # Basic
> + #
> + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> +!if $(SSE2_ENABLE) == TRUE
> +
> BaseMemoryLib|MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2
> .inf
> +!else
> +
> BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibR
> epStr.inf
> +!endif
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
> +
> PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibP
> ci.inf
> + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
> + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> +
> CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCac
> heMaintenanceLib.inf
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> +
> PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/Base
> PeCoffGetEntryPointLib.inf
> +!if $(RC_BINARY_RELEASE) == TRUE
> +
> PchPlatformLib|Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.in
> f
> +!endif
> + #
> + # UEFI & PI
> + #
> +
> UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBo
> otServicesTableLib.inf
> +
> UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib
> /UefiRuntimeServicesTableLib.inf
> + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> +
> UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiService
> sLib.inf
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> +
> UefiDecompressLib|MdeModulePkg/Library/BaseUefiTianoCustomDecompr
> essLib/BaseUefiTianoCustomDecompressLib.inf
> +
> PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/P
> eiServicesTablePointerLibIdt.inf
> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> +
> DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTabl
> eLib.inf
> + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
> + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +
> GenericBdsLib|$(PLATFORM_PACKAGE)/Override/IntelFrameworkModuleP
> kg/Library/GenericBdsLib/GenericBdsLib.inf
> +
> BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupp
> ortLib.inf
> + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
> +
> PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformB
> dsLib.inf
> + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
> +
> FlashDeviceLib|$(PLATFORM_PACKAGE)/Library/FlashDeviceLib/FlashDevice
> Lib.inf
> +
> UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBoo
> tManagerLib.inf
> + #
> + # Framework
> + #
> +!if $(S3_ENABLE) == TRUE
> +
> S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootSc
> riptLib.inf
> +!else
> +
> S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL
> ibNull.inf
> +!endif
> + S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
> + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
> +
> + #
> + # Generic Modules
> + #
> +!if $(USB_ENABLE) == TRUE
> + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +!endif
> +!if $(SCSI_ENABLE) == TRUE
> + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
> +!endif
> +!if $(NETWORK_ENABLE) == TRUE
> + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
> + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
> + TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
> + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
> +!endif
> +!if $(S3_ENABLE) == TRUE
> + S3Lib|IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf
> +!endif
> +
> +
> OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibN
> ull/OemHookStatusCodeLibNull.inf
> +!if $(CAPSULE_ENABLE) == TRUE
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf
> +!else
> +
> CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.i
> nf
> +!endif
> +
> FmpAuthenticationLib|MdeModulePkg/Library/FmpAuthenticationLibNull/F
> mpAuthenticationLibNull.inf
> + IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf
> +
> PlatformFlashAccessLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/Platfor
> mFlashAccessLib/PlatformFlashAccessLib.inf
> +
> MicrocodeFlashAccessLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/Platfo
> rmFlashAccessLib/PlatformFlashAccessLib.inf
> +
> DisplayUpdateProgressLib|MdeModulePkg/Library/DisplayUpdateProgressLi
> bGraphics/DisplayUpdateProgressLibGraphics.inf
> +
> SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniz
> ationLib.inf
> +
> SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementL
> ib/DxeSecurityManagementLib.inf
> + IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
> +
> DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/Bas
> eDebugPrintErrorLevelLib.inf
> +
> + #
> + # CPU
> + #
> + MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
> +
> LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.in
> f
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeC
> puExceptionHandlerLib.inf
> + MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
> +
> + #
> + # ICH
> + #
> + SmbusLib|$(PLATFORM_PACKAGE)/Library/SmbusLib/SmbusLib.inf
> + SmmLib|$(PLATFORM_PACKAGE)/Library/PchSmmLib/PchSmmLib.inf
> +
> + #
> + # Platform
> + #
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +
> ResetSystemLib|$(PLATFORM_PACKAGE)/Library/ResetSystemLib/ResetSys
> temLib.inf
> +
> +
> PlatformCmosLib|$(PLATFORM_PACKAGE)/Library/PlatformCmosLib/Platfor
> mCmosLib.inf
> +
> + #
> + # Misc
> + #
> +
> MonoStatusCodeLib|$(PLATFORM_PACKAGE)/MonoStatusCode/MonoStat
> usCode.inf
> +!if $(TARGET) == RELEASE
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +
> SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.in
> f
> +!else
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> +!endif
> +
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +!if $(TPM_ENABLED) == TRUE
> + TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf
> +
> Tpm12CommandLib|SecurityPkg/Library/Tpm12CommandLib/Tpm12Comma
> ndLib.inf
> +
> Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLib
> DTpm.inf
> +
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibD
> ebug/PeCoffExtraActionLibDebug.inf
> +
> DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicati
> onLibSerialPort/DebugCommunicationLibSerialPort.inf
> +
> PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePla
> tformHookLibNull.inf
> +
> SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort
> Lib16550.inf
> +!else
> +
> PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BaseP
> eCoffExtraActionLibNull.inf
> +
> DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLi
> bNull.inf
> +!endif
> +
> + #
> + # CryptLib
> + #
> +!if $(TPM_ENABLED) == TRUE
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> +!endif
> +
> + BiosIdLib|$(PLATFORM_PACKAGE)/Library/BiosIdLib/BiosIdLib.inf
> + CpuIA32Lib|$(PLATFORM_PACKAGE)/Library/CpuIA32Lib/CpuIA32Lib.inf
> +
> +
> StallSmmLib|$(PLATFORM_PACKAGE)/Library/StallSmmLib/StallSmmLib.inf
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> +
> PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecu
> reLibNull.inf
> +
> TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTp
> mMeasurementLib.inf
> + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
> + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> +!else
> +
> TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/Tp
> mMeasurementLibNull.inf
> +
> AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableL
> ibNull.inf
> +!endif
> + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> +!if $(RC_BINARY_RELEASE) == TRUE
> + I2cLib|Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
> +!endif
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> +!if $(FTPM_ENABLE) == TRUE || $(NETWORK_ISCSI_ENABLE) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> +!endif
> +
> TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTp
> mMeasurementLib.inf
> +
> Tcg2PhysicalPresenceLib|SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/D
> xeTcg2PhysicalPresenceLib.inf
> +
> Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorL
> ibNull.inf
> +
> +
> +
> Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandL
> ib.inf
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> + FspApiLib|IntelFspWrapperPkg/Library/BaseFspApiLib/BaseFspApiLib.inf
> +
> FspPlatformInfoLib|IntelFspWrapperPkg/Library/BaseFspPlatformInfoLibSa
> mple/BaseFspPlatformInfoLibSample.inf
> +
> FspPlatformSecLib|Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSe
> cLibVlv2/FspPlatformSecLibVlv2.inf
> +
> FspHobProcessLib|Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcess
> LibVlv2/FspHobProcessLibVlv2.inf
> +!endif
> +
> + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> +
> +[LibraryClasses.IA32.SEC]
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> +!endif
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +
> +[LibraryClasses.IA32.PEIM, LibraryClasses.IA32.PEI_CORE,
> LibraryClasses.IA32.SEC]
> + #
> + # PEI phase common
> + #
> +
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> +
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory
> AllocationLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiR
> eportStatusCodeLib.inf
> +
> ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiEx
> tractGuidedSectionLib.inf
> +
> MultiPlatformLib|$(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPl
> atformLib.inf
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecP
> eiCpuExceptionHandlerLib.inf
> + MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
> +
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanc
> eLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> +!if $(TARGET) == RELEASE
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +
> SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.in
> f
> +!else
> +
> DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDx
> eDebugLibReportStatusCode.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> +!endif
> +
> +
> LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
> +
> HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoR
> outerPei.inf
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAg
> entLib.inf
> +!endif
> +
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> +
> PlatformFspLib|Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.in
> f
> + !endif
> +!if $(FTPM_ENABLE) == TRUE
> +
> Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2Devi
> ceLibSeC.inf
> +!endif
> +
> +[LibraryClasses.X64]
> + #
> + # DXE phase common
> + #
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemo
> ryAllocationLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/Dx
> eReportStatusCodeLib.inf
> +
> ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeE
> xtractGuidedSectionLib.inf
> +
> +
> TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/Dxe
> TcgPhysicalPresenceLib.inf
> +!if $(TPM_ENABLED) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> +!endif
> +
> +
> LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.in
> f
> +
> EfiRegTableLib|$(PLATFORM_PACKAGE)/Library/EfiRegTableLib/EfiRegTable
> Lib.inf
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> +!endif
> +
> +
> HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoR
> outerDxe.inf
> +
> +[LibraryClasses.X64.DXE_DRIVER]
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> +
> CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Custo
> mizedDisplayLib.inf
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerforma
> nceLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +
> FlashDeviceLib|$(PLATFORM_PACKAGE)/Library/FlashDeviceLib/FlashDevice
> LibDxe.inf
> +
> +[LibraryClasses.X64.DXE_CORE]
> + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> +
> MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLi
> b/DxeCoreMemoryAllocationLib.inf
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCore
> PerformanceLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +[LibraryClasses.X64.DXE_SMM_DRIVER]
> +
> MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTabl
> eLib.inf
> +
> SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesT
> ableLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/S
> mmReportStatusCodeLib.inf
> +
> MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMe
> moryAllocationLib.inf
> +
> LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.i
> nf
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
> +
> SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull
> /SmmCpuPlatformHookLibNull.inf
> +
> SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFea
> turesLib.inf
> +
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
> + !if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAge
> ntLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/Smm
> CpuExceptionHandlerLib.inf
> +
> +[LibraryClasses.X64.SMM_CORE]
> +
> MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocatio
> nLib/PiSmmCoreMemoryAllocationLib.inf
> +
> SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTabl
> eLib/PiSmmCoreSmmServicesTableLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/S
> mmReportStatusCodeLib.inf
> +
> SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHook
> LibNull/SmmCorePlatformHookLibNull.inf
> + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
> +
> +!if $(TPM_ENABLED) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
> +!endif
> +
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> +
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> +
> +[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
> +
> ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCod
> eLib/RuntimeDxeReportStatusCodeLib.inf
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +!if $(CAPSULE_ENABLE) == TRUE
> +
> CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsule
> Lib.inf
> +!endif
> +
> +[LibraryClasses.common.UEFI_DRIVER]
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +[LibraryClasses.X64.UEFI_APPLICATION]
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +#########################################################
> #######################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +#########################################################
> #######################
> +[PcdsFeatureFlag.common]
> +!if $(MINI_BIOS_ENABLE) == FALSE
> + gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|TRUE
> +!else
> +
> gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|FALSE
> +!endif
> +#
> +# If PcdDxeIplSwitchToLongMode is TRUE, DxeIpl will load a 64-bit DxeCore
> and switch to long mode to hand over to DxeCore.
> +#
> + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
> +
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserGrayOutTextStatement|TR
> UE
> +
> +!if $(CAPSULE_RESET_ENABLE) == TRUE
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE
> +!else
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALS
> E
> +!endif
> + gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
> +!if $(DATAHUB_STATUS_CODE_ENABLE) == TRUE
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub
> |TRUE
> +!else
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub
> |FALSE
> +!endif
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSecti
> onFirst|FALSE
> +!if $(TARGET) == RELEASE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> +!else
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> +!endif
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
> +!if $(ISA_SERIAL_STATUS_CODE_ENABLE) == TRUE
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|TRUE
> +!else
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|FALSE
> +!endif
> +!if $(USB_SERIAL_STATUS_CODE_ENABLE) == TRUE
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|TRUE
> +!else
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|FALSE
> +!endif
> +!if $(RAM_SERIAL_STATUS_CODE_ENABLE) == TRUE
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|TRUE
> +!else
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|FALSE
> +!endif
> +
> +
> + ## This PCD specifies whether PS2 keyboard does a extended verification
> during start.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|FALSE
> +
> + ## This PCD specifies whether PS2 mouse does a extended verification
> during start.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|FA
> LSE
> +
> +!if $(VARIABLE_INFO_ENABLE) == TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|TRUE
> +!else
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|FALSE
> +!endif
> +
> + gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE
> +
> +!if $(SOURCE_DEBUG_ENABLE)
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|TRUE
> +!endif
> +
> +[PcdsFixedAtBuild.common]
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +# $(FLASH_REGION_VLVMICROCODE_BASE)
> +
> gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
> +# $(FLASH_REGION_VLVMICROCODE_SIZE)
> +
> gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0004000
> 0
> + gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
> +# $(FLASH_AREA_BASE_ADDRESS)
> + gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
> +# $(FLASH_AREA_SIZE)
> + gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00800000
> +# $(FLASH_REGION_FSPBIN_BASE)
> + gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFCC0000
> +!endif
> +
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> + # in FSP, when this got used, the memory already is up
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
> +!else
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
> +!endif
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
> +
> +!else
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
> + !else
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
> + !endif
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
> + gEfiCpuTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x3C00
> +!endif
> +
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x22000
> +!else
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000
> +!endif
> + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x4
> 00
> + gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemory
> Size|0x10000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
> + gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000
> +!if $(S4_ENABLE) == TRUE
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationC
> hange|TRUE
> +!else
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationC
> hange|FALSE
> +!endif
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +!endif
> +!if $(PERFORMANCE_ENABLE) == TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|60
> +!endif
> +
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySi
> ze|0x10000
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(
> TOP_MEMORY_ADDRESS)
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
> + gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVbeEna
> ble|TRUE
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnab
> le|TRUE
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FAL
> SE
> +
> gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|2
> +!endif
> +
> + #
> + # Set SMM stack size to 16 KB.
> + #
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000
> +
> + #
> + # Clear unused single certificate PCD
> + #
> + gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer|{0}
> +
> + #
> + # Lock all updatable firmware devices at End of DXE
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceLockEventGuid|{GUID(gEfiE
> ndOfDxeEventGroupGuid)}
> +#
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceLockEventGuid|{GUID(gEfiE
> ventReadyToBootGuid)}
> +
> + #
> + # Set PcdFmpDeviceTestKeySha256Digest to {0} to disable test key
> detection
> + #
> +# gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceTestKeySha256Digest|{0}
> +
> +[PcdsFixedAtBuild.IA32]
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +!endif
> +
> +!if $(RECOVERY_ENABLE)
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryFileName|L"VLV2REC.Cap
> "
> +!endif
> +
> +[PcdsPatchableInModule.common]
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
> +
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x$(PLATFORM_PC
> IEXPRESS_BASE)
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacy
> Region|FALSE
> +
> + ## This PCD specifies whether to use the optimized timing for best PS2
> detection performance.
> + # Note this PCD could be set to TRUE for best boot performance and set to
> FALSE for best device compatibility.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE
> +
> +
> ##########################################################
> #############################################
> + #
> + # Begin of MRC parameters
> + #
> +
> + ## Memory Parameter Patchable.
> + # FALSE - MRC Parameters are fixed for MinnowBoard Max<BR>
> + # TRUE - MRC Parameters are patchable by following PCDs<BR>
> + # @Prompt Memory Parameter Patchable.
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|FALSE
> +
> + ## Memory Down or DIMM slot.
> + # 0 - DIMM<BR>
> + # 1 - Memory Down<BR>
> + # @Prompt Enable Memory Down
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|1
> +
> + ## The speed of DRAM.
> + # 0 - 800 MHz<BR>
> + # 1 - 1066 MHz<BR>
> + # 2 - 1333 MHz<BR>
> + # 3 - 1600 MHz<BR>
> + # @Prompt DRAM Speed
> + # @ValidList 0x80000001 | 0, 1, 2, 3
> + gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|1
> +
> + ## DRAM Type.
> + # 0 - DDR3<BR>
> + # 1 - DDR3L<BR>
> + # 2 - DDR3U<BR>
> + # 3 - DDR3All<BR>
> + # 4 - LPDDR2<BR>
> + # 5 - LPDDR3<BR>
> + # 6 - DDR4<BR>
> + # @Prompt DRAM Type
> + # @ValidList 0x80000001 | 0, 1, 2, 3, 4, 5, 6
> + gVlvRefCodePkgTokenSpaceGuid.PcdDramType|1
> +
> + ## Please populate DIMM slot 0 if only one DIMM is supported.
> + # 0 - Disable<BR>
> + # 1 - Enable<BR>
> + # @Prompt DIMM 0 Enable
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|1
> +
> + ## DIMM 1 has to be identical to DIMM 0.
> + # 0 - Disable<BR>
> + # 1 - Enable<BR>
> + # @Prompt DIMM 1 Enable Type
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0
> +
> + ## DRAM device data width.
> + # 0 - x8<BR>
> + # 1 - x16<BR>
> + # 2 - x32<BR>
> + # @Prompt DIMM_DWIDTH
> + # @ValidList 0x80000001 | 0, 1, 2
> + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|1
> +
> + ## DRAM device data density.
> + # 0 - 1 Gbit<BR>
> + # 1 - 2 Gbit<BR>
> + # 2 - 4 Gbit<BR>
> + # 3 - 8 Gbit<BR>
> + # @Prompt DIMM_Density
> + # @ValidList 0x80000001 | 0, 1, 2, 3
> + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|2
> +
> + ## DRAM device data bus width.
> + # 0 - 8 bits<BR>
> + # 1 - 16 bits<BR>
> + # 2 - 32 bits<BR>
> + # 3 - 64 bits<BR>
> + # @Prompt DIMM_BusWidth
> + # @ValidList 0x80000001 | 0, 1, 2, 3
> + gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|3
> +
> + ## Ranks Per DIMM or Sides Per DIMM.
> + # 0 - 1 Rank<BR>
> + # 1 - 2 Ranks<BR>
> + # @Prompt DIMM_Sides
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0
> +
> + ## tCL.<BR><BR>
> + # @Prompt tCL
> + gVlvRefCodePkgTokenSpaceGuid.PcdTcl|11
> +
> + ## tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc.
> + # @Prompt tRP_tRCD
> + gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|11
> +
> + ## tWR in DRAM clk.
> + # @Prompt tWR
> + gVlvRefCodePkgTokenSpaceGuid.PcdTwr|12
> +
> + ## tWTR in DRAM clk.
> + # @Prompt tWTR
> + gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|6
> +
> + ## tRRD in DRAM clk.
> + # @Prompt tRRD
> + gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|6
> +
> + ## tRTP in DRAM clk.
> + # @Prompt tRTP
> + gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|6
> +
> + ## tFAW in DRAM clk.
> + # @Prompt tFAW
> + gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|32
> +
> + #
> + # End of MRC parameters.
> + #
> +
> ##########################################################
> #####################################
> +
> +[PcdsDynamicHii.common.DEFAULT]
> +
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlo
> balVariableGuid|0x0|5 # Variable: L"Timeout"
> +
> gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSup
> port"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
> +
> +[PcdsDynamicDefault.common.DEFAULT]
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x
> 0
> + !if $(TPM_ENABLED) == TRUE
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd,
> 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}
> + !endif
> +
> + ## This PCD defines the video horizontal resolution.
> + # This PCD could be set to 0 then video resolution could be at highest
> resolution.
> + #gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
> + ## This PCD defines the video vertical resolution.
> + # This PCD could be set to 0 then video resolution could be at highest
> resolution.
> + #gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
> +
> + ## This PCD defines the Console output column and the default value is 25
> according to UEFI spec.
> + # This PCD could be set to 0 then console output could be at max column
> and max row.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
> + ## This PCD defines the Console output row and the default value is 80
> according to UEFI spec.
> + # This PCD could be set to 0 then console output could be at max column
> and max row.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
> +
> + ## The PCD is used to specify the video horizontal resolution of text setup.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|80
> 0
> + ## The PCD is used to specify the video vertical resolution of text setup.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
> + ## The PCD is used to specify the console output column of text setup.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100
> + ## The PCD is used to specify the console output column of text setup.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|31
> +
> +!if $(TPM_ENABLED) == TRUE
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1
> +!endif
> +
> +[PcdsDynamicExDefault.common.DEFAULT]
> + gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040
> + gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId|0
> + gEfiVLVTokenSpaceGuid.PcdProductSerialNumber|0
> + gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable|TRUE
> + gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur|FALSE
> + gEfiVLVTokenSpaceGuid.PcdFTPMErrorSkip|FALSE
> + gEfiVLVTokenSpaceGuid.PcdFTPMCommand|0
> + gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0
> + gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE
> + gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataP
> tr|0
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0
> + gEfiCpuTokenSpaceGuid.PcdCpuS3DataAddress|0
> + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugDataAddress|0
> + gEfiCpuTokenSpaceGuid.PcdCpuCallbackSignal|0
> + gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer|0
> + gEfiVLVTokenSpaceGuid.PcdCpuLockBoxDataAddress|0
> + gEfiVLVTokenSpaceGuid.PcdCpuSmramCpuDataAddress|0
> + gEfiVLVTokenSpaceGuid.PcdCpuLockBoxSize|0
> +
> +[PcdsDynamicExDefault.X64.DEFAULT]
> +!if $(RECOVERY_ENABLE)
> +
> gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{G
> UID("AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215")}|VOID*|0x10
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGu
> id|{GUID("4096267b-da0a-42eb-b5eb-fef31d207cb4")}|VOID*|0x10
> +!endif
> +
> +[Components.IA32]
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/S
> ecCore.inf
> +
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> + IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf {
> + !if $(TARGET) == DEBUG
> +
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + }
> + Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
> + IntelFspWrapperPkg/FspInitPei/FspInitPei.inf {
> + !if $(TARGET) == DEBUG
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + }
> + !endif
> +
> + MdeModulePkg/Core/Pei/PeiMain.inf {
> +!if $(TARGET) == DEBUG
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> +!endif
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + }
> +
> + $(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf {
> +!if $(TARGET) == DEBUG
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> +!endif
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/M
> emoryInit.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <BuildOptions>
> + !if $(FTPM_ENABLE)==TRUE
> + *_*_IA32_CC_FLAGS = /D FTPM_ENABLE
> + !endif
> + }
> +
> +!if $(RC_BINARY_RELEASE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/S
> eCUma.inf
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> +$(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/f
> TPMInitPeim.inf
> +!endif
> +
> +!if $(RC_BINARY_RELEASE) == TRUE
> + $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf {
> + <BuildOptions>
> + *_*_IA32_CC_FLAGS = -DRC_BINARY_RELEASE
> + !if $(TARGET) == DEBUG
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> + !endif
> + }
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> + SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf{
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAg
> entLib.inf
> +
> PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePla
> tformHookLibNull.inf
> +
> SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort
> Lib16550.inf
> + }
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/T
> pm2DeviceSeCPei.inf
> +!endif
> +
> +!if $(TPM_ENABLED) == TRUE
> + SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
> + SecurityPkg/Tcg/TcgPei/TcgPei.inf {
> + <LibraryClasses>
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.in
> f
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> +}
> +!endif
> +
> + $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
> + <LibraryClasses>
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> + $(PLATFORM_PACKAGE)/FvInfoPei/FvInfoPei.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Vl
> vInitPeim.inf
> +!if $(PCIESC_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chEarlyInitPeim.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + }
> +!endif
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chInitPeim.inf
> +
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chSmbusArpDisabled.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chSpiPeim.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> eiSmmAccess.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> eiSmmControl.inf
> + MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/C
> puPeim.inf
> + UefiCpuPkg/CpuIoPei/CpuIoPei.inf
> + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/M
> pS3.inf
> +#
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Pi
> SmmCommunicationPei.inf
> +
> +!if $(RECOVERY_ENABLE)
> + #
> + # Recovery
> + #
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chUsb.inf
> + MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf
> + MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf
> + MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf
> + FatPkg/FatPei/FatPei.inf
> + MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf
> +
> SignedCapsulePkg/Universal/RecoveryModuleLoadPei/RecoveryModuleLoa
> dPei.inf {
> + <LibraryClasses>
> +
> FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibRsa2048Sh
> a256/FmpAuthenticationLibRsa2048Sha256.inf
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +!endif
> +
> +!if $(CAPSULE_ENABLE) == TRUE
> + MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
> +!endif
> + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
> + <LibraryClasses>
> +!if $(LZMA_ENABLE) == TRUE
> +
> NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDec
> ompressLib.inf
> +!endif
> + }
> +
> + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> +
> MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> +
> +!if $(FTPM_ENABLE) == TRUE
> + SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +
> NULL|SecurityPkg/Library\HashInstanceLibSha1/HashInstanceLibSha1.inf
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.in
> f
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +!endif
> +!if $(ACPI50_ENABLE) == TRUE
> +
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/Firmwa
> rePerformancePei.inf{
> + <LibraryClasses>
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> + }
> +
> +!endif
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCode
> RouterPei.inf
> +!endif
> +[Components.X64]
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> + IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf {
> + !if $(TARGET) == DEBUG
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + }
> +
> + !endif
> + #
> + # EDK II Related Platform codes
> + #
> + MdeModulePkg/Core/Dxe/DxeMain.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <LibraryClasses>
> +!if $(DXE_CRC32_SECTION_ENABLE) == TRUE
> +
> NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32G
> uidedSectionExtractLib.inf
> +!endif
> +!if $(LZMA_ENABLE) == TRUE
> +
> NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDec
> ompressLib.inf
> +!endif
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + }
> +
> IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.i
> nf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> + <LibraryClasses>
> + !if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + <BuildOptions>
> + ICC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG
> + GCC:RELEASE_*_*_CC_FLAGS = -D MDEPKG_NDEBUG
> + }
> + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + }
> + IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
> + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
> +
> +
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportSt
> atusCodeRouterRuntimeDxe.inf
> +
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHan
> dlerRuntimeDxe.inf {
> + <LibraryClasses>
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + }
> +
> +!if $(CAPSULE_ENABLE) == TRUE
> + MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> +
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory
> AllocationLib.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecP
> eiCpuExceptionHandlerLib.inf
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAg
> entLib.inf
> +!endif
> + }
> +!endif
> +
> +
> MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCod
> eRouterSmm.inf
> + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf{
> + <LibraryClasses>
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> +
> NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib
> .inf
> +!endif
> +!if $(USER_IDENTIFICATION_ENABLE)
> +
> NULL|SecurityPkg/Library/DxeDeferImageLoadLib/DxeDeferImageLoadLib.in
> f
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> +
> NULL|SecurityPkg/Library/DxeTpmMeasureBootLib/DxeTpmMeasureBootLi
> b.inf
> +!endif
> +!if $(FTPM_ENABLE) == TRUE
> +
> NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBoot
> Lib.inf
> +!endif
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MpCpu.inf
> + $(PLATFORM_PACKAGE)/Metronome/Metronome.inf
> +
> + IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf{
> + <LibraryClasses>
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> +
> PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformB
> dsLib.inf
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> + !if $(FTPM_ENABLE) == TRUE
> +
> Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2Devi
> ceLibSeC.inf
> + !else
> +
> Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibTcg2/Tpm2DeviceLibTcg2
> .inf
> + !endif
> + }
> +
> + $(PLATFORM_PACKAGE)/UiApp/UiApp.inf
> +
> + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> +
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.in
> f
> +
> MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.i
> nf
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> + }
> + $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
> +
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.i
> nf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSpiSmm.inf
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> +
> SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfi
> gDxe.inf {
> + <LibraryClasses>
> +
> PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecu
> reLibNull.inf
> + <BuildOptions>
> + #
> + # Specify GUID gEfiIfrBootMaintenanceGuid, to install Secure Boot
> Configuration menu
> + # into Boot Maintenance Manager menu
> + #
> + *_*_*_VFR_FLAGS = -g b2dedc91-d59f-48d2-898a-12490c74a4e0
> + }
> +!endif
> + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf {
> + <LibraryClasses>
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> + }
> +
> +
> MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCoun
> terRuntimeDxe.inf
> +
> PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime
> Dxe.inf
> + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> +
> + $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf
> +
> + $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf
> +
> +!if $(DATAHUB_ENABLE) == TRUE
> + IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
> + }
> +!endif
> +
> IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandl
> erDxe/DatahubStatusCodeHandlerDxe.inf
> +
> MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryT
> estDxe.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchS3SupportDxe.inf
> + !if $(USE_HPET_TIMER) == TRUE
> + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
> + !else
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmartTimer.inf
> + !endif
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmmControl.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSmbusDxe.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/IntelPchLegacyInterrupt.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchReset.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchInitDxe.inf{
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchInitSmm.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSmiDispatcher.inf
> +
> +!if $(PCIESC_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchPcieSmm.inf
> +!endif
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSpiRuntime.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchPolicyInitDxe.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchBiosWriteProtect.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmmAccess.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PciHostBridge.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/VlvInitDxe.inf
> +
> +
> IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.i
> nf
> +
> + #
> + # Performance Application; Set PERFORMANCE_ENABLE=TRUE for normal
> boot performance and smm performance data
> + #
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf
> {
> + <PcdsFixedAtBuild>
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> + }
> +!endif
> +
> + Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf{
> + <LibraryClasses>
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/Dptf.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PnpDxe.inf
> +
> +!if $(SEC_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/HeciDrv.inf {
> +!if $(SEC_DEBUG_INFO_ENABLE) == TRUE
> + <BuildOptions>
> + *_*_X64_CC_FLAGS = /DSEC_DEBUG_INFO=1
> +!else
> + <BuildOptions>
> + *_*_X64_CC_FLAGS = /DSEC_DEBUG_INFO=0
> +!endif
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SeCPolicyInitDxe.inf
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/Tpm2DeviceSeCDxe.inf
> + SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf
> + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf{
> + <LibraryClasses>
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.in
> f
> + PcdLib|MdePkg/Library\DxePcdLib/DxePcdLib.inf
> +
> Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2Devi
> ceLibSeC.inf
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/FtpmSmm.inf
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +
> + SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + <BuildOptions>
> + #
> + # specify GUID gEfiIfrNotInTPVPageGuid, this page will not
> + # be showed in TPV page.
> + #
> + *_*_*_VFR_FLAGS = -g e58809f8-fbc1-48e2-883a-a30fdc4b441e
> + }
> +
> + SecurityPkg/Tcg/TcgDxe/TcgDxe.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> + SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
> +!endif
> + #
> + # EDK II Related Platform codes
> + #
> + $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf{
> + <LibraryClasses>
> + !if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> + $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf
> + $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
> + $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf
> +
> + $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf
> + $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PlatformCpuPolicy.inf
> + $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf
> +
> $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHand
> lerSmm.inf
> +!if $(GOP_DRIVER_ENABLE) == TRUE
> + $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf
> +
> +!endif
> +
> +
> + #
> + # SMM
> + #
> + MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
> + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
> + UefiCpuPkg/CpuDxe/CpuDxe.inf
> + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
> + UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
> + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
> + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
> +
> $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmS
> wDispatch2OnSmmSwDispatchThunk.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PowerManagement2.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/DigitalThermalSensor.inf
> +
> + #
> + # ACPI
> + #
> +
> MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutor
> Dxe.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> +
> + $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf
> +
> IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDx
> e.inf
> +
> Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTable
> s/PowerManagementAcpiTables.inf
> +
> + $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf
> +
> + $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf
> +
> +
> MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraph
> icsResourceTableDxe.inf
> +
> + #
> + # PCI
> + #
> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/ISPDxe.inf
> +
> +
> +#
> +# ISA
> +#
> + $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf
> + IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
> + IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf
> + IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
> + IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
> +
> IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
> +#
> +# SDIO
> +#
> +#
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MmcHost.inf
> +#
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MmcMediaDevice.inf
> +!if $(ACPI50_ENABLE) == TRUE
> +
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/Firmw
> arePerformanceDxe.inf {
> + <LibraryClasses>
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> + }
> +
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/Firm
> warePerformanceSmm.inf {
> + <LibraryClasses>
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> + }
> +!endif
> +
> +#
> +# IDE/SCSI/AHCI
> +#
> + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> + IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf
> + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> +
> MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + FatPkg/EnhancedFatDxe/Fat.inf
> + ShellPkg/Application/Shell/Shell.inf {
> + <LibraryClasses>
> +
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComma
> ndLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1
> CommandsLib.inf
> +
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingL
> ib.inf
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> +
> BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg
> CommandLib.inf
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
> + }
> +!if $(SATA_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SataController.inf
> +!endif
> + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +!if $(SCSI_ENABLE) == TRUE
> + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +!endif
> +#
> +# Console
> +#
> + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> +
> MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleD
> xe.inf
> +
> IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.in
> f
> + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> +
> + #
> + # USB
> + #
> +!if $(USB_ENABLE) == TRUE
> + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
> + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +
> +!endif
> +
> + #
> + # SMBIOS
> + #
> + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
> + $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmbiosMemory.inf
> + #
> + # CPU/FW Microde
> + #
> + Vlv2SocBinPkg/Microcode/MicrocodeUpdates.inf {
> + <BuildOptions>
> + *_*_*_GENFW_FLAGS = -a 0x800 -p 0xFF
> + }
> +
> +
> +
> +!if $(NETWORK_ENABLE) == TRUE
> + !if $(NETWORK_ISCSI_ENABLE) == TRUE
> + NetworkPkg/IScsiDxe/IScsiDxe.inf
> + !endif
> + !if $(NETWORK_VLAN_ENABLE) == TRUE
> + MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + !endif
> + !if $(CSM_ENABLE) == TRUE
> + IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Snp16Dxe.inf
> + !endif
> +!endif
> +
> +!if $(NETWORK_ENABLE) == TRUE
> + #
> + # UEFI network modules
> + #
> + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> +
> + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + NetworkPkg/TcpDxe/TcpDxe.inf
> + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + !if $(NETWORK_IP6_ENABLE) == TRUE
> + NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + !endif
> +!endif
> +
> +!if $(CAPSULE_ENABLE) || $(MICOCODE_CAPSULE_ENABLE)
> + MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf
> + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf
> +!endif
> +
> +!if $(CAPSULE_ENABLE)
> + !include Vlv2TbltDevicePkg/FmpMinnowMaxSystem.dsc
> + !include Vlv2TbltDevicePkg/FmpGreenSampleDevice.dsc
> + !include Vlv2TbltDevicePkg/FmpBlueSampleDevice.dsc
> + !include Vlv2TbltDevicePkg/FmpRedSampleDevice.dsc
> +!endif
> +
> +!if $(MICOCODE_CAPSULE_ENABLE)
> +
> IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdateDx
> e.inf {
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> + }
> +!endif
> +
> +[BuildOptions]
> +#
> +# Define Build Options both for EDK and EDKII drivers.
> +#
> +
> +#
> +# Define token for different Platform
> +#
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> + DEFINE MINNOW2_FSP_OPTION = -DMINNOW2_FSP_BUILD
> +!else
> + DEFINE MINNOW2_FSP_OPTION =
> +!endif
> +
> +!if $(ENBDT_PF_BUILD) == TRUE
> + DEFINE ENBDT_PF_ENABLE = -DENBDT_PF_ENABLE=1
> +!else
> + DEFINE ENBDT_PF_ENABLE = -DENBDT_PF_ENABLE=0
> +!endif
> +
> +
> +!if $(CLKGEN_CONFIG_EXTRA_ENABLE) == TRUE
> + DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION = -
> DCLKGEN_CONFIG_EXTRA=1
> +!else
> + DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION =
> +!endif
> +
> +
> +
> +!if $(PCIESC_ENABLE) == TRUE
> + DEFINE PCIESC_SUPPORT_BUILD_OPTION = -DPCIESC_SUPPORT=1
> +!else
> + DEFINE PCIESC_SUPPORT_BUILD_OPTION =
> +!endif
> +!if $(SATA_ENABLE) == TRUE
> + DEFINE SATA_SUPPORT_BUILD_OPTION = -DSATA_SUPPORT=1
> +!else
> + DEFINE SATA_SUPPORT_BUILD_OPTION =
> +!endif
> +!if $(ENBDT_S3_SUPPORT) == TRUE
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS = -DNOCS_S3_SUPPORT
> +!else
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS =
> +!endif
> +
> +!if $(X64_CONFIG) == TRUE
> + DEFINE X64_BUILD_ENABLE = -DX64_BUILD_ENABLE=1
> +!else
> + DEFINE X64_BUILD_ENABLE =
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> + DEFINE DSC_FTPM_BUILD_OPTIONS = -DFTPM_ENABLE
> +!else
> + DEFINE DSC_FTPM_BUILD_OPTIONS =
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + DEFINE DSC_TPM_BUILD_OPTIONS = -DTPM_ENABLED
> +!else
> + DEFINE DSC_TPM_BUILD_OPTIONS =
> +!endif
> +
> +
> + DEFINE EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS =
> $(MINNOW2_FSP_OPTION) $(MINNOW2_BUILD_OPTION)
> $(ENBDT_PF_ENABLE) $(EXTERNAL_VGA_BUILD_OPTION)
> $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)
> $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS)
> $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS)
> $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS)
> $(SYSCTL_ID_BUILD_OPTION) $(CLKGEN_CONFIG_EXTRA_BUILD_OPTION)
> $(SYSCTL_X0_CONVERT_BOARD_OPTION) $(ENBDT_S3_SUPPORT_OPTIONS)
> $(SATA_SUPPORT_BUILD_OPTION) $(PCIESC_SUPPORT_BUILD_OPTION)
> $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS)
> $(DSC_TPM_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)
> +!if $(PERFORMANCE_ENABLE) == TRUE
> + DEFINE PDB_BUILD_OPTION = /Zi
> +!endif
> +
> + GCC:*_*_*_CC_FLAGS = -Wno-missing-braces
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> + MSFT:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> + GCC:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> + INTEL:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> + DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS =
> +!else
> + DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS =
> +
> +!endif
> +
> +#
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support page
> level
> +# protection of DXE_RUNTIME_DRIVER modules
> +#
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +#
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support page
> level
> +# protection of DXE_SMM_DRIVER/SMM_CORE modules
> +#
> +[BuildOptions.common.EDKII.DXE_SMM_DRIVER,
> BuildOptions.common.EDKII.SMM_CORE]
> + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +[BuildOptions.Common.EDK]
> +
> +#
> +# Define token for different Platform
> +#
> +!if $(ENBDT_PF_BUILD) == TRUE
> + DEFINE ENBDT_PF_ENABLE = -DENBDT_PF_ENABLE=1
> +!else
> + DEFINE ENBDT_PF_ENABLE = -DENBDT_PF_ENABLE=0
> +!endif
> +
> +!if $(PERFORMANCE_ENABLE) == TRUE
> + RELEASE_*_*_DLINK_FLAGS = -DEBUG
> +!endif
> +
> +!if $(S3_ENABLE) == TRUE
> + DEFINE DSC_S3_BUILD_OPTIONS = -DEFI_S3_RESUME
> +!else
> + DEFINE DSC_S3_BUILD_OPTIONS =
> +!endif
> +
> +!if $(ENBDT_S3_SUPPORT) == TRUE
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS = -DNOCS_S3_SUPPORT
> +!else
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS =
> +!endif
> +
> +!if $(X64_CONFIG) == TRUE
> + DEFINE X64_BUILD_ENABLE = -DX64_BUILD_ENABLE=1
> +!else
> + DEFINE X64_BUILD_ENABLE =
> +!endif
> +
> +
> + DEFINE EDK_GLUE_LIB_DEBUG =
> + DEFINE DEBUG_BUILD_OPTIONS = -D EFI_DEBUG -D DEBUG_MODE=1
> /GL- $(EDK_GLUE_LIB_DEBUG) -
> DEDKII_GLUE_DebugPrintErrorLevel=(EFI_D_ERROR)
> + DEFINE EDK_DSC_FEATURE_BUILD_OPTIONS = $(DSC_S3_BUILD_OPTIONS)
> $(DSC_ACPI_BUILD_OPTIONS) $(DSC_SEC_BUILD_OPTIONS)
> $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS)
> $(DSC_TPM_BUILD_OPTIONS) $(SOFTSDV_BUILD_OPTIONS)
> $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS)
> $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS)
> $(QT_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) -
> D$(PROJECT_SC_CHIPSET)
> +
> + DEFINE EDK_DSC_OTHER_BUILD_OPTIONS =
> $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SV_BUILD_OPTIONS)
> $(INTEL_FASTBOOT_BUILD_OPTION)
> + DEFINE EDK_DSC_GLOBAL_BUILD_OPTIONS = $(ENBDT_PF_ENABLE)
> $(EDK_DSC_FEATURE_BUILD_OPTIONS)
> $(EDK_DSC_OTHER_BUILD_OPTIONS) -D
> EFI_SPECIFICATION_VERSION=0x00020000 -D
> PI_SPECIFICATION_VERSION=0x00000009 -D
> TIANO_RELEASE_VERSION=0x00080006 -D
> SUPPORT_DEPRECATED_PCI_CFG_PPI -D CSM_SMMENTRY_PORT8DATA8 -D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) -D
> MAX_VARIABLE_SIZE=0x2000 -D EFI_FIRMWARE_VENDOR="L/"INTEL/"" -D
> EFI_BUILD_VERSION="L/"EDKII/"" -DEFI_PEI_REPORT_STATUS_CODE_ON
> $(ENBDT_S3_SUPPORT_OPTIONS)
> +
> + *_*_IA32_ASM_FLAGS = -DEFI32 -D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h -
> DNOCS_S3_SUPPORT
> + DEBUG_*_IA32_CC_FLAGS = -D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_CC_FLAGS = -D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_IA32_VFRPP_FLAGS = -D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_VFRPP_FLAGS = -D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_IA32_APP_FLAGS = -D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_APP_FLAGS = -D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_IA32_PP_FLAGS = -D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_PP_FLAGS = -D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + *_*_IA32_ASLPP_FLAGS = -D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_IA32_ASLCC_FLAGS = -D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_IA32_ASM16_FLAGS = -D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> +
> + *_*_X64_ASM_FLAGS = -DEFIX64 -D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h -
> DNOCS_S3_SUPPORT
> + DEBUG_*_X64_CC_FLAGS = -D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_CC_FLAGS = -D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_X64_VFRPP_FLAGS = -D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_VFRPP_FLAGS = -D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_X64_APP_FLAGS = -D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_APP_FLAGS = -D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_X64_PP_FLAGS = -D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_PP_FLAGS = -D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + *_*_X64_ASLPP_FLAGS = -D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_X64_ASLCC_FLAGS = -D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_X64_ASM16_FLAGS = -D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> + # *_*_*_BUILD_FLAGS = -s
> + *_*_*_VFR_FLAGS = -c
> + *_*_*_BUILD_FLAGS = -c
> +
> +[BuildOptions.Common.EDKII]
> + *_*_IA32_ASM_FLAGS = $(VP_BUILD_OPTIONS) -D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h -
> DNOCS_S3_SUPPORT
> +
> + *_*_IA32_CC_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_VFRPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_APP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_PP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_ASLPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +
> + *_*_X64_CC_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> $(SOURCE_LEVEL_DEBUG_BUILD_OPTIONS)
> + *_*_X64_VFRPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_X64_APP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_X64_PP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_X64_ASLPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +
> +
> +[Components.X64]
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cBus.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cHost.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cPortA0Pio.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cMmioDeviceDxe.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
> + }
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc
> new file mode 100644
> index 0000000000..2324794841
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc
> @@ -0,0 +1,1699 @@
> +#/** @file
> +# Platform description.
> +#
> +# Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#**/
> +
> +#########################################################
> #######################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +#########################################################
> #######################
> +[Defines]
> + PLATFORM_NAME = Vlv2TbltDevicePkg
> + PLATFORM_GUID = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x00010005
> +
> + #
> + # Set platform specific package/folder name, same as passed from
> PREBUILD script.
> + # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well
> as package build folder
> + # DEFINE only takes effect at R9 DSC and FDF.
> + #
> + DEFINE PLATFORM_PACKAGE = Vlv2TbltDevicePkg
> + DEFINE PLATFORM_RC_PACKAGE = Vlv2DeviceRefCodePkg
> + DEFINE PLATFORM_BINARY_PACKAGE = Vlv2SocBinPkg
> + OUTPUT_DIRECTORY = Build/$(PLATFORM_PACKAGE)
> + SUPPORTED_ARCHITECTURES = IA32
> + BUILD_TARGETS = DEBUG|RELEASE
> + SKUID_IDENTIFIER = DEFAULT
> +
> + DEFINE CPU_ARCH =ValleyView2
> + DEFINE PROJECT_SC_FAMILY =IntelPch
> + DEFINE PROJECT_SC_ROOT
> =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/SouthCluster
> + DEFINE PROJECT_VLV_ROOT
> =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/NorthCluster
> +
> + DEFINE RC_BINARY_RELEASE = TRUE
> + #
> + # Platform On/Off features are defined here
> + #
> + #
> + # Platform Support:: Set only one token except Crestview Hills
> + #
> + # 3.BayleyBay
> + # ENBDT_PF_ENABLE = TRUE
> + #
> + !include $(PLATFORM_PACKAGE)/AutoPlatformCFG.txt
> + !include $(PLATFORM_PACKAGE)/PlatformPkgConfig.dsc
> +
> +!if $(X64_CONFIG) == TRUE
> + DEFINE DXE_ARCHITECTURE = X64
> + DEFINE EDK_DXE_ARCHITECTURE = X64
> + DEFINE UNDI_DXE_ARCHITECTURE = 64
> +!else
> + DEFINE DXE_ARCHITECTURE = IA32
> + DEFINE EDK_DXE_ARCHITECTURE = Ia32
> + DEFINE UNDI_DXE_ARCHITECTURE = 32
> +!endif
> +
> + FLASH_DEFINITION = $(PLATFORM_PACKAGE)/PlatformPkg.fdf
> +!if $(LFMA_ENABLE) == TRUE
> + FIX_LOAD_TOP_MEMORY_ADDRESS = 0xFFFFFFFFFFFFFFFF
> + DEFINE TOP_MEMORY_ADDRESS = 0xFFFFFFFFFFFFFFFF
> +!else
> + FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
> + DEFINE TOP_MEMORY_ADDRESS = 0x0
> +!endif
> +
> + DEFINE PLATFORM_PCIEXPRESS_BASE = 0E0000000
> +
> + DEFINE SEC_ENABLE = FALSE
> + DEFINE SEC_DEBUG_INFO_ENABLE = FALSE
> + DEFINE FTPM_ENABLE = FALSE
> +
> +#########################################################
> #######################
> +#
> +# SKU Identification section - list of all SKU IDs supported by this
> +# Platform.
> +#
> +#########################################################
> #######################
> +[SkuIds]
> + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
> +
> +#########################################################
> #######################
> +#
> +# Library Class section - list of all Library Classes needed by this Platform.
> +#
> +#########################################################
> #######################
> +[LibraryClasses.common]
> + #
> + # Entry point
> + #
> +
> PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.in
> f
> + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
> +
> DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint
> .inf
> +
> UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry
> Point.inf
> +
> UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA
> pplicationEntryPoint.inf
> +
> DxeSmmDriverEntryPoint|IntelFrameworkPkg/Library/DxeSmmDriverEntryP
> oint/DxeSmmDriverEntryPoint.inf
> +
> + #
> + # Basic
> + #
> + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> +!if $(SSE2_ENABLE) == TRUE
> +
> BaseMemoryLib|MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2
> .inf
> +!else
> +
> BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibR
> epStr.inf
> +!endif
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
> +
> PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibP
> ci.inf
> + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
> + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> +
> CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCac
> heMaintenanceLib.inf
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> +
> PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/Base
> PeCoffGetEntryPointLib.inf
> +!if $(RC_BINARY_RELEASE) == TRUE
> +
> PchPlatformLib|Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.in
> f
> +!endif
> + #
> + # UEFI & PI
> + #
> +
> UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBo
> otServicesTableLib.inf
> +
> UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib
> /UefiRuntimeServicesTableLib.inf
> + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> +
> UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiService
> sLib.inf
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> +
> UefiDecompressLib|MdeModulePkg/Library/BaseUefiTianoCustomDecompr
> essLib/BaseUefiTianoCustomDecompressLib.inf
> +
> PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/P
> eiServicesTablePointerLibIdt.inf
> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> +
> DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTabl
> eLib.inf
> + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
> + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +
> GenericBdsLib|$(PLATFORM_PACKAGE)/Override/IntelFrameworkModuleP
> kg/Library/GenericBdsLib/GenericBdsLib.inf
> +
> BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupp
> ortLib.inf
> + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
> +
> PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformB
> dsLib.inf
> + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
> +
> FlashDeviceLib|$(PLATFORM_PACKAGE)/Library/FlashDeviceLib/FlashDevice
> Lib.inf
> +
> UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBoo
> tManagerLib.inf
> + #
> + # Framework
> + #
> +!if $(S3_ENABLE) == TRUE
> +
> S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootSc
> riptLib.inf
> +!else
> +
> S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL
> ibNull.inf
> +!endif
> + S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
> + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
> +
> + #
> + # Generic Modules
> + #
> +!if $(USB_ENABLE) == TRUE
> + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +!endif
> +!if $(SCSI_ENABLE) == TRUE
> + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
> +!endif
> +!if $(NETWORK_ENABLE) == TRUE
> + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
> + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
> + TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
> + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
> +!endif
> +!if $(S3_ENABLE) == TRUE
> + S3Lib|IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf
> +!endif
> +
> +
> OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibN
> ull/OemHookStatusCodeLibNull.inf
> +!if $(CAPSULE_ENABLE) == TRUE
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf
> +!else
> +
> CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.i
> nf
> +!endif
> +
> FmpAuthenticationLib|MdeModulePkg/Library/FmpAuthenticationLibNull/F
> mpAuthenticationLibNull.inf
> + IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf
> +
> PlatformFlashAccessLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/Platfor
> mFlashAccessLib/PlatformFlashAccessLib.inf
> +
> MicrocodeFlashAccessLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/Platfo
> rmFlashAccessLib/PlatformFlashAccessLib.inf
> +
> DisplayUpdateProgressLib|MdeModulePkg/Library/DisplayUpdateProgressLi
> bGraphics/DisplayUpdateProgressLibGraphics.inf
> +
> SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniz
> ationLib.inf
> +
> SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementL
> ib/DxeSecurityManagementLib.inf
> + IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
> +
> DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/Bas
> eDebugPrintErrorLevelLib.inf
> +
> + #
> + # CPU
> + #
> + MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
> +
> LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.in
> f
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeC
> puExceptionHandlerLib.inf
> + MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
> +
> + #
> + # ICH
> + #
> + SmbusLib|$(PLATFORM_PACKAGE)/Library/SmbusLib/SmbusLib.inf
> + SmmLib|$(PLATFORM_PACKAGE)/Library/PchSmmLib/PchSmmLib.inf
> +
> + #
> + # Platform
> + #
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +
> ResetSystemLib|$(PLATFORM_PACKAGE)/Library/ResetSystemLib/ResetSys
> temLib.inf
> +
> +
> PlatformCmosLib|$(PLATFORM_PACKAGE)/Library/PlatformCmosLib/Platfor
> mCmosLib.inf
> +
> + #
> + # Misc
> + #
> +
> MonoStatusCodeLib|$(PLATFORM_PACKAGE)/MonoStatusCode/MonoStat
> usCode.inf
> +!if $(TARGET) == RELEASE
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +
> SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.in
> f
> +!else
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> +!endif
> +
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +!if $(TPM_ENABLED) == TRUE
> + TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf
> +
> Tpm12CommandLib|SecurityPkg/Library/Tpm12CommandLib/Tpm12Comma
> ndLib.inf
> +
> Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLib
> DTpm.inf
> +
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibD
> ebug/PeCoffExtraActionLibDebug.inf
> +
> DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicati
> onLibSerialPort/DebugCommunicationLibSerialPort.inf
> +
> PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePla
> tformHookLibNull.inf
> +
> SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort
> Lib16550.inf
> +!else
> +
> PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BaseP
> eCoffExtraActionLibNull.inf
> +
> DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLi
> bNull.inf
> +!endif
> +
> + #
> + # CryptLib
> + #
> +!if $(TPM_ENABLED) == TRUE
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> +!endif
> +
> + BiosIdLib|$(PLATFORM_PACKAGE)/Library/BiosIdLib/BiosIdLib.inf
> + CpuIA32Lib|$(PLATFORM_PACKAGE)/Library/CpuIA32Lib/CpuIA32Lib.inf
> +
> +
> StallSmmLib|$(PLATFORM_PACKAGE)/Library/StallSmmLib/StallSmmLib.inf
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> +
> PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecu
> reLibNull.inf
> +
> TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTp
> mMeasurementLib.inf
> + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
> + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> +!else
> +
> TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/Tp
> mMeasurementLibNull.inf
> +
> AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableL
> ibNull.inf
> +!endif
> + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> +!if $(RC_BINARY_RELEASE) == TRUE
> + I2cLib|Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
> +!endif
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> +!if $(FTPM_ENABLE) == TRUE || $(NETWORK_ISCSI_ENABLE) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> +!endif
> +
> TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTp
> mMeasurementLib.inf
> +
> Tcg2PhysicalPresenceLib|SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/D
> xeTcg2PhysicalPresenceLib.inf
> +
> Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorL
> ibNull.inf
> +
> +
> +
> Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandL
> ib.inf
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> + FspApiLib|IntelFspWrapperPkg/Library/BaseFspApiLib/BaseFspApiLib.inf
> +
> FspPlatformInfoLib|IntelFspWrapperPkg/Library/BaseFspPlatformInfoLibSa
> mple/BaseFspPlatformInfoLibSample.inf
> +
> FspPlatformSecLib|Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSe
> cLibVlv2/FspPlatformSecLibVlv2.inf
> +
> FspHobProcessLib|Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcess
> LibVlv2/FspHobProcessLibVlv2.inf
> +!endif
> +
> + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> +
> +[LibraryClasses.IA32.SEC]
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> +!endif
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +
> +[LibraryClasses.IA32.PEIM, LibraryClasses.IA32.PEI_CORE,
> LibraryClasses.IA32.SEC]
> + #
> + # PEI phase common
> + #
> +
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> +
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory
> AllocationLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiR
> eportStatusCodeLib.inf
> +
> ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiEx
> tractGuidedSectionLib.inf
> +
> MultiPlatformLib|$(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPl
> atformLib.inf
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecP
> eiCpuExceptionHandlerLib.inf
> + MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
> +
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanc
> eLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> +!if $(TARGET) == RELEASE
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +
> SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.in
> f
> +!else
> +
> DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDx
> eDebugLibReportStatusCode.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> +!endif
> +
> +
> LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
> +
> HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoR
> outerPei.inf
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAg
> entLib.inf
> +!endif
> +
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> +
> PlatformFspLib|Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.in
> f
> + !endif
> +!if $(FTPM_ENABLE) == TRUE
> +
> Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2Devi
> ceLibSeC.inf
> +!endif
> +
> +[LibraryClasses.IA32]
> + #
> + # DXE phase common
> + #
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemo
> ryAllocationLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/Dx
> eReportStatusCodeLib.inf
> +
> ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeE
> xtractGuidedSectionLib.inf
> +
> +
> TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/Dxe
> TcgPhysicalPresenceLib.inf
> +!if $(TPM_ENABLED) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> +!endif
> +
> +
> LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.in
> f
> +
> EfiRegTableLib|$(PLATFORM_PACKAGE)/Library/EfiRegTableLib/EfiRegTable
> Lib.inf
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> +!endif
> +
> +
> HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoR
> outerDxe.inf
> +
> +[LibraryClasses.IA32.DXE_DRIVER]
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> +
> CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Custo
> mizedDisplayLib.inf
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerforma
> nceLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +
> FlashDeviceLib|$(PLATFORM_PACKAGE)/Library/FlashDeviceLib/FlashDevice
> LibDxe.inf
> +
> +[LibraryClasses.IA32.DXE_CORE]
> + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> +
> MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLi
> b/DxeCoreMemoryAllocationLib.inf
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCore
> PerformanceLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +[LibraryClasses.IA32.DXE_SMM_DRIVER]
> +
> MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTabl
> eLib.inf
> +
> SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesT
> ableLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/S
> mmReportStatusCodeLib.inf
> +
> MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMe
> moryAllocationLib.inf
> +
> LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.i
> nf
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
> +
> SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull
> /SmmCpuPlatformHookLibNull.inf
> +
> SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFea
> turesLib.inf
> +
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
> + !if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAge
> ntLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/Smm
> CpuExceptionHandlerLib.inf
> +
> +[LibraryClasses.IA32.SMM_CORE]
> +
> MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocatio
> nLib/PiSmmCoreMemoryAllocationLib.inf
> +
> SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTabl
> eLib/PiSmmCoreSmmServicesTableLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/S
> mmReportStatusCodeLib.inf
> +
> SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHook
> LibNull/SmmCorePlatformHookLibNull.inf
> + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
> +
> +!if $(TPM_ENABLED) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
> +!endif
> +
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> +
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> +
> +[LibraryClasses.IA32.DXE_RUNTIME_DRIVER]
> +
> ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCod
> eLib/RuntimeDxeReportStatusCodeLib.inf
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +!if $(CAPSULE_ENABLE) == TRUE
> +
> CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsule
> Lib.inf
> +!endif
> +
> +[LibraryClasses.common.UEFI_DRIVER]
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +[LibraryClasses.IA32.UEFI_APPLICATION]
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +#########################################################
> #######################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +#########################################################
> #######################
> +[PcdsFeatureFlag.common]
> +!if $(MINI_BIOS_ENABLE) == FALSE
> + gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|TRUE
> +!else
> +
> gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|FALSE
> +!endif
> +#
> +# If PcdDxeIplSwitchToLongMode is TRUE, DxeIpl will load a 64-bit DxeCore
> and switch to long mode to hand over to DxeCore.
> +#
> + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE
> +
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserGrayOutTextStatement|TR
> UE
> +
> +!if $(CAPSULE_RESET_ENABLE) == TRUE
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE
> +!else
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALS
> E
> +!endif
> + gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
> +!if $(DATAHUB_STATUS_CODE_ENABLE) == TRUE
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub
> |TRUE
> +!else
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub
> |FALSE
> +!endif
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSecti
> onFirst|FALSE
> +!if $(TARGET) == RELEASE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> +!else
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> +!endif
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
> +!if $(ISA_SERIAL_STATUS_CODE_ENABLE) == TRUE
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|TRUE
> +!else
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|FALSE
> +!endif
> +!if $(USB_SERIAL_STATUS_CODE_ENABLE) == TRUE
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|TRUE
> +!else
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|FALSE
> +!endif
> +!if $(RAM_SERIAL_STATUS_CODE_ENABLE) == TRUE
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|TRUE
> +!else
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|FALSE
> +!endif
> +
> +
> + ## This PCD specifies whether PS2 keyboard does a extended verification
> during start.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|FALSE
> +
> + ## This PCD specifies whether PS2 mouse does a extended verification
> during start.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|FA
> LSE
> +
> +!if $(VARIABLE_INFO_ENABLE) == TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|TRUE
> +!else
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|FALSE
> +!endif
> +
> + gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE
> +
> +!if $(SOURCE_DEBUG_ENABLE)
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|TRUE
> +!endif
> +
> +[PcdsFixedAtBuild.common]
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +# $(FLASH_REGION_VLVMICROCODE_BASE)
> +
> gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
> +# $(FLASH_REGION_VLVMICROCODE_SIZE)
> +
> gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0004000
> 0
> + gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
> +# $(FLASH_AREA_BASE_ADDRESS)
> + gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
> +# $(FLASH_AREA_SIZE)
> + gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00800000
> +# $(FLASH_REGION_FSPBIN_BASE)
> + gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFCC0000
> +!endif
> +
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> + # in FSP, when this got used, the memory already is up
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
> +!else
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
> +!endif
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
> +
> +!else
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
> + !else
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
> + !endif
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
> + gEfiCpuTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x3C00
> +!endif
> +
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x22000
> +!else
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000
> +!endif
> + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x4
> 00
> + gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemory
> Size|0x10000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
> + gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000
> +!if $(S4_ENABLE) == TRUE
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationC
> hange|TRUE
> +!else
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationC
> hange|FALSE
> +!endif
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +!endif
> +!if $(PERFORMANCE_ENABLE) == TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|60
> +!endif
> +
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySi
> ze|0x10000
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(
> TOP_MEMORY_ADDRESS)
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
> + gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVbeEna
> ble|TRUE
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnab
> le|TRUE
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FAL
> SE
> +
> gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|2
> +!endif
> +
> + #
> + # Set SMM stack size to 16 KB.
> + #
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000
> +
> + #
> + # Clear unused single certificate PCD
> + #
> + gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer|{0}
> +
> + #
> + # Lock all updatable firmware devices at End of DXE
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceLockEventGuid|{GUID(gEfiE
> ndOfDxeEventGroupGuid)}
> +#
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceLockEventGuid|{GUID(gEfiE
> ventReadyToBootGuid)}
> +
> + #
> + # Set PcdFmpDeviceTestKeySha256Digest to {0} to disable test key
> detection
> + #
> +# gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceTestKeySha256Digest|{0}
> +
> +[PcdsFixedAtBuild.IA32]
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +!endif
> +
> +!if $(RECOVERY_ENABLE)
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryFileName|L"VLV2REC.Cap
> "
> +!endif
> +
> +[PcdsPatchableInModule.common]
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
> +
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x$(PLATFORM_PC
> IEXPRESS_BASE)
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacy
> Region|FALSE
> +
> + ## This PCD specifies whether to use the optimized timing for best PS2
> detection performance.
> + # Note this PCD could be set to TRUE for best boot performance and set to
> FALSE for best device compatibility.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE
> +
> +
> ##########################################################
> #############################################
> + #
> + # Begin of MRC parameters
> + #
> +
> + ## Memory Parameter Patchable.
> + # FALSE - MRC Parameters are fixed for MinnowBoard Max<BR>
> + # TRUE - MRC Parameters are patchable by following PCDs<BR>
> + # @Prompt Memory Parameter Patchable.
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|FALSE
> +
> + ## Memory Down or DIMM slot.
> + # 0 - DIMM<BR>
> + # 1 - Memory Down<BR>
> + # @Prompt Enable Memory Down
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|1
> +
> + ## The speed of DRAM.
> + # 0 - 800 MHz<BR>
> + # 1 - 1066 MHz<BR>
> + # 2 - 1333 MHz<BR>
> + # 3 - 1600 MHz<BR>
> + # @Prompt DRAM Speed
> + # @ValidList 0x80000001 | 0, 1, 2, 3
> + gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|1
> +
> + ## DRAM Type.
> + # 0 - DDR3<BR>
> + # 1 - DDR3L<BR>
> + # 2 - DDR3U<BR>
> + # 3 - DDR3All<BR>
> + # 4 - LPDDR2<BR>
> + # 5 - LPDDR3<BR>
> + # 6 - DDR4<BR>
> + # @Prompt DRAM Type
> + # @ValidList 0x80000001 | 0, 1, 2, 3, 4, 5, 6
> + gVlvRefCodePkgTokenSpaceGuid.PcdDramType|1
> +
> + ## Please populate DIMM slot 0 if only one DIMM is supported.
> + # 0 - Disable<BR>
> + # 1 - Enable<BR>
> + # @Prompt DIMM 0 Enable
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|1
> +
> + ## DIMM 1 has to be identical to DIMM 0.
> + # 0 - Disable<BR>
> + # 1 - Enable<BR>
> + # @Prompt DIMM 1 Enable Type
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0
> +
> + ## DRAM device data width.
> + # 0 - x8<BR>
> + # 1 - x16<BR>
> + # 2 - x32<BR>
> + # @Prompt DIMM_DWIDTH
> + # @ValidList 0x80000001 | 0, 1, 2
> + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|1
> +
> + ## DRAM device data density.
> + # 0 - 1 Gbit<BR>
> + # 1 - 2 Gbit<BR>
> + # 2 - 4 Gbit<BR>
> + # 3 - 8 Gbit<BR>
> + # @Prompt DIMM_Density
> + # @ValidList 0x80000001 | 0, 1, 2, 3
> + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|2
> +
> + ## DRAM device data bus width.
> + # 0 - 8 bits<BR>
> + # 1 - 16 bits<BR>
> + # 2 - 32 bits<BR>
> + # 3 - 64 bits<BR>
> + # @Prompt DIMM_BusWidth
> + # @ValidList 0x80000001 | 0, 1, 2, 3
> + gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|3
> +
> + ## Ranks Per DIMM or Sides Per DIMM.
> + # 0 - 1 Rank<BR>
> + # 1 - 2 Ranks<BR>
> + # @Prompt DIMM_Sides
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0
> +
> + ## tCL.<BR><BR>
> + # @Prompt tCL
> + gVlvRefCodePkgTokenSpaceGuid.PcdTcl|11
> +
> + ## tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc.
> + # @Prompt tRP_tRCD
> + gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|11
> +
> + ## tWR in DRAM clk.
> + # @Prompt tWR
> + gVlvRefCodePkgTokenSpaceGuid.PcdTwr|12
> +
> + ## tWTR in DRAM clk.
> + # @Prompt tWTR
> + gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|6
> +
> + ## tRRD in DRAM clk.
> + # @Prompt tRRD
> + gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|6
> +
> + ## tRTP in DRAM clk.
> + # @Prompt tRTP
> + gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|6
> +
> + ## tFAW in DRAM clk.
> + # @Prompt tFAW
> + gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|32
> +
> + #
> + # End of MRC parameters.
> + #
> +
> ##########################################################
> #####################################
> +
> +[PcdsDynamicHii.common.DEFAULT]
> +
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlo
> balVariableGuid|0x0|5 # Variable: L"Timeout"
> +
> gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSup
> port"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
> +
> +[PcdsDynamicDefault.common.DEFAULT]
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x
> 0
> + !if $(TPM_ENABLED) == TRUE
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd,
> 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}
> + !endif
> +
> + ## This PCD defines the video horizontal resolution.
> + # This PCD could be set to 0 then video resolution could be at highest
> resolution.
> + #gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
> + ## This PCD defines the video vertical resolution.
> + # This PCD could be set to 0 then video resolution could be at highest
> resolution.
> + #gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
> +
> + ## This PCD defines the Console output column and the default value is 25
> according to UEFI spec.
> + # This PCD could be set to 0 then console output could be at max column
> and max row.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
> + ## This PCD defines the Console output row and the default value is 80
> according to UEFI spec.
> + # This PCD could be set to 0 then console output could be at max column
> and max row.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
> +
> + ## The PCD is used to specify the video horizontal resolution of text setup.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|80
> 0
> + ## The PCD is used to specify the video vertical resolution of text setup.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
> + ## The PCD is used to specify the console output column of text setup.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100
> + ## The PCD is used to specify the console output column of text setup.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|31
> +
> +!if $(TPM_ENABLED) == TRUE
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1
> +!endif
> +
> +[PcdsDynamicExDefault.common.DEFAULT]
> + gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040
> + gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId|0
> + gEfiVLVTokenSpaceGuid.PcdProductSerialNumber|0
> + gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable|TRUE
> + gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur|FALSE
> + gEfiVLVTokenSpaceGuid.PcdFTPMErrorSkip|FALSE
> + gEfiVLVTokenSpaceGuid.PcdFTPMCommand|0
> + gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0
> + gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE
> + gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataP
> tr|0
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0
> + gEfiCpuTokenSpaceGuid.PcdCpuS3DataAddress|0
> + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugDataAddress|0
> + gEfiCpuTokenSpaceGuid.PcdCpuCallbackSignal|0
> + gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer|0
> + gEfiVLVTokenSpaceGuid.PcdCpuLockBoxDataAddress|0
> + gEfiVLVTokenSpaceGuid.PcdCpuSmramCpuDataAddress|0
> + gEfiVLVTokenSpaceGuid.PcdCpuLockBoxSize|0
> +
> +[PcdsDynamicExDefault.X64.DEFAULT]
> +!if $(RECOVERY_ENABLE)
> +
> gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{G
> UID("AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215")}|VOID*|0x10
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGu
> id|{GUID("4096267b-da0a-42eb-b5eb-fef31d207cb4")}|VOID*|0x10
> +!endif
> +
> +[Components.IA32]
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/S
> ecCore.inf
> +
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> + IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf {
> + !if $(TARGET) == DEBUG
> +
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + }
> + Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
> + IntelFspWrapperPkg/FspInitPei/FspInitPei.inf {
> + !if $(TARGET) == DEBUG
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + }
> + !endif
> +
> + MdeModulePkg/Core/Pei/PeiMain.inf {
> +!if $(TARGET) == DEBUG
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> +!endif
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + }
> +
> + $(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf {
> +!if $(TARGET) == DEBUG
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> +!endif
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/M
> emoryInit.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <BuildOptions>
> + !if $(FTPM_ENABLE)==TRUE
> + *_*_IA32_CC_FLAGS = /D FTPM_ENABLE
> + !endif
> + }
> +
> +!if $(RC_BINARY_RELEASE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/S
> eCUma.inf
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> +$(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/f
> TPMInitPeim.inf
> +!endif
> +
> +!if $(RC_BINARY_RELEASE) == TRUE
> + $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf {
> + <BuildOptions>
> + *_*_IA32_CC_FLAGS = /DRC_BINARY_RELEASE
> + !if $(TARGET) == DEBUG
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> + !endif
> + }
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> + SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf{
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAg
> entLib.inf
> +
> PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePla
> tformHookLibNull.inf
> +
> SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort
> Lib16550.inf
> + }
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/T
> pm2DeviceSeCPei.inf
> +!endif
> +
> +!if $(TPM_ENABLED) == TRUE
> + SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
> + SecurityPkg/Tcg/TcgPei/TcgPei.inf {
> + <LibraryClasses>
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.in
> f
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> +}
> +!endif
> +
> + $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
> + <LibraryClasses>
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> + $(PLATFORM_PACKAGE)/FvInfoPei/FvInfoPei.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Vl
> vInitPeim.inf
> +!if $(PCIESC_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chEarlyInitPeim.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + }
> +!endif
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chInitPeim.inf
> +
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chSmbusArpDisabled.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chSpiPeim.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> eiSmmAccess.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> eiSmmControl.inf
> + MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/C
> puPeim.inf
> + UefiCpuPkg/CpuIoPei/CpuIoPei.inf
> + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/M
> pS3.inf
> +#
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Pi
> SmmCommunicationPei.inf
> +
> +!if $(RECOVERY_ENABLE)
> + #
> + # Recovery
> + #
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chUsb.inf
> + MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf
> + MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf
> + MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf
> + FatPkg/FatPei/FatPei.inf
> + MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf
> +
> SignedCapsulePkg/Universal/RecoveryModuleLoadPei/RecoveryModuleLoa
> dPei.inf {
> + <LibraryClasses>
> +
> FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibRsa2048Sh
> a256/FmpAuthenticationLibRsa2048Sha256.inf
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +!endif
> +
> +!if $(CAPSULE_ENABLE) == TRUE
> + MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
> +!endif
> + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
> + <LibraryClasses>
> +!if $(LZMA_ENABLE) == TRUE
> +
> NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDec
> ompressLib.inf
> +!endif
> + }
> +
> + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> +
> MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> +
> +!if $(FTPM_ENABLE) == TRUE
> + SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +
> NULL|SecurityPkg/Library\HashInstanceLibSha1/HashInstanceLibSha1.inf
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.in
> f
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +!endif
> +!if $(ACPI50_ENABLE) == TRUE
> +
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/Firmwa
> rePerformancePei.inf{
> + <LibraryClasses>
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> + }
> +
> +!endif
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCode
> RouterPei.inf
> +!endif
> +[Components.IA32]
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> + IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf {
> + !if $(TARGET) == DEBUG
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + }
> +
> + !endif
> + #
> + # EDK II Related Platform codes
> + #
> + MdeModulePkg/Core/Dxe/DxeMain.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <LibraryClasses>
> +!if $(DXE_CRC32_SECTION_ENABLE) == TRUE
> +
> NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32G
> uidedSectionExtractLib.inf
> +!endif
> +!if $(LZMA_ENABLE) == TRUE
> +
> NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDec
> ompressLib.inf
> +!endif
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + }
> +
> IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.i
> nf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> + <LibraryClasses>
> + !if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + <BuildOptions>
> + ICC:*_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
> + GCC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG
> + }
> + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + }
> + IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
> + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
> +
> +
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportSt
> atusCodeRouterRuntimeDxe.inf
> +
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHan
> dlerRuntimeDxe.inf {
> + <LibraryClasses>
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + }
> +
> +
> MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCod
> eRouterSmm.inf
> + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf{
> + <LibraryClasses>
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> +
> NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib
> .inf
> +!endif
> +!if $(USER_IDENTIFICATION_ENABLE)
> +
> NULL|SecurityPkg/Library/DxeDeferImageLoadLib/DxeDeferImageLoadLib.in
> f
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> +
> NULL|SecurityPkg/Library/DxeTpmMeasureBootLib/DxeTpmMeasureBootLi
> b.inf
> +!endif
> +!if $(FTPM_ENABLE) == TRUE
> +
> NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBoot
> Lib.inf
> +!endif
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MpCpu.inf
> + $(PLATFORM_PACKAGE)/Metronome/Metronome.inf
> +
> + IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf{
> + <LibraryClasses>
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> +
> PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformB
> dsLib.inf
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> + !if $(FTPM_ENABLE) == TRUE
> +
> Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2Devi
> ceLibSeC.inf
> + !else
> +
> Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibTcg2/Tpm2DeviceLibTcg2
> .inf
> + !endif
> + }
> +
> + $(PLATFORM_PACKAGE)/UiApp/UiApp.inf
> +
> + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> +
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.in
> f
> +
> MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.i
> nf
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> + }
> + $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
> +
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.i
> nf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSpiSmm.inf
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> +
> SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfi
> gDxe.inf {
> + <LibraryClasses>
> +
> PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecu
> reLibNull.inf
> + <BuildOptions>
> + #
> + # Specify GUID gEfiIfrBootMaintenanceGuid, to install Secure Boot
> Configuration menu
> + # into Boot Maintenance Manager menu
> + #
> + *_*_*_VFR_FLAGS = -g b2dedc91-d59f-48d2-898a-12490c74a4e0
> + }
> +!endif
> + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf {
> + <LibraryClasses>
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> + }
> +
> +
> MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCoun
> terRuntimeDxe.inf
> +
> PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime
> Dxe.inf
> + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> +
> + $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf
> +
> + $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf
> +
> +!if $(DATAHUB_ENABLE) == TRUE
> + IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
> + }
> +!endif
> +
> IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandl
> erDxe/DatahubStatusCodeHandlerDxe.inf
> +
> MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryT
> estDxe.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchS3SupportDxe.inf
> + !if $(USE_HPET_TIMER) == TRUE
> + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
> + !else
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmartTimer.inf
> + !endif
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmmControl.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSmbusDxe.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/IntelPchLegacyInterrupt.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchReset.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchInitDxe.inf{
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchInitSmm.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSmiDispatcher.inf
> +
> +!if $(PCIESC_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchPcieSmm.inf
> +!endif
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSpiRuntime.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchPolicyInitDxe.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchBiosWriteProtect.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmmAccess.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PciHostBridge.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/VlvInitDxe.inf
> +
> +
> IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.i
> nf
> +
> + #
> + # Performance Application; Set PERFORMANCE_ENABLE=TRUE for normal
> boot performance and smm performance data
> + #
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf
> {
> + <PcdsFixedAtBuild>
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> + }
> +!endif
> +
> + Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf{
> + <LibraryClasses>
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/Dptf.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PnpDxe.inf
> +
> +!if $(SEC_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/HeciDrv.inf {
> +!if $(SEC_DEBUG_INFO_ENABLE) == TRUE
> + <BuildOptions>
> + *_*_X64_CC_FLAGS = /DSEC_DEBUG_INFO=1
> +!else
> + <BuildOptions>
> + *_*_X64_CC_FLAGS = /DSEC_DEBUG_INFO=0
> +!endif
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SeCPolicyInitDxe.inf
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/Tpm2DeviceSeCDxe.inf
> + SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf
> + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf{
> + <LibraryClasses>
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.in
> f
> + PcdLib|MdePkg/Library\DxePcdLib/DxePcdLib.inf
> +
> Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2Devi
> ceLibSeC.inf
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/FtpmSmm.inf
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +
> + SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + <BuildOptions>
> + #
> + # specify GUID gEfiIfrNotInTPVPageGuid, this page will not
> + # be showed in TPV page.
> + #
> + *_*_*_VFR_FLAGS = -g e58809f8-fbc1-48e2-883a-a30fdc4b441e
> + }
> +
> + SecurityPkg/Tcg/TcgDxe/TcgDxe.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> + SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
> +!endif
> + #
> + # EDK II Related Platform codes
> + #
> + $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf{
> + <LibraryClasses>
> + !if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> + $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf
> + $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
> + $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf
> +
> + $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf
> + $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PlatformCpuPolicy.inf
> + $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf
> +
> $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHand
> lerSmm.inf
> +!if $(GOP_DRIVER_ENABLE) == TRUE
> + $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf
> +
> +!endif
> +
> +
> + #
> + # SMM
> + #
> + MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
> + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
> + UefiCpuPkg/CpuDxe/CpuDxe.inf
> + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
> + UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
> + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
> + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
> +
> $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmS
> wDispatch2OnSmmSwDispatchThunk.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PowerManagement2.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/DigitalThermalSensor.inf
> +
> + #
> + # ACPI
> + #
> +
> MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutor
> Dxe.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> +
> + $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf
> +
> IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDx
> e.inf
> +
> Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTable
> s/PowerManagementAcpiTables.inf
> +
> + $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf
> +
> + $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf
> +
> +
> MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraph
> icsResourceTableDxe.inf
> +
> + #
> + # PCI
> + #
> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/ISPDxe.inf
> +
> +
> +#
> +# ISA
> +#
> + $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf
> + IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
> + IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf
> + IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
> + IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
> +
> IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
> +#
> +# SDIO
> +#
> +#
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MmcHost.inf
> +#
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MmcMediaDevice.inf
> +!if $(ACPI50_ENABLE) == TRUE
> +
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/Firmw
> arePerformanceDxe.inf {
> + <LibraryClasses>
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> + }
> +
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/Firm
> warePerformanceSmm.inf {
> + <LibraryClasses>
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> + }
> +!endif
> +
> +#
> +# IDE/SCSI/AHCI
> +#
> + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> + IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf
> + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> +
> MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + FatPkg/EnhancedFatDxe/Fat.inf
> + ShellPkg/Application/Shell/Shell.inf {
> + <LibraryClasses>
> +
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComma
> ndLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1
> CommandsLib.inf
> +
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingL
> ib.inf
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> +
> BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg
> CommandLib.inf
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
> + }
> +!if $(SATA_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SataController.inf
> +!endif
> + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +!if $(SCSI_ENABLE) == TRUE
> + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +!endif
> +#
> +# Console
> +#
> + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> +
> MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleD
> xe.inf
> +
> IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.in
> f
> + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> +
> + #
> + # USB
> + #
> +!if $(USB_ENABLE) == TRUE
> + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
> + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +
> +!endif
> +
> + #
> + # SMBIOS
> + #
> + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
> + $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmbiosMemory.inf
> + #
> + # CPU/FW Microde
> + #
> + Vlv2SocBinPkg/Microcode/MicrocodeUpdates.inf {
> + <BuildOptions>
> + *_*_*_GENFW_FLAGS = -a 0x800 -p 0xFF
> + }
> +
> +
> +
> +!if $(NETWORK_ENABLE) == TRUE
> + !if $(NETWORK_ISCSI_ENABLE) == TRUE
> + NetworkPkg/IScsiDxe/IScsiDxe.inf
> + !endif
> + !if $(NETWORK_VLAN_ENABLE) == TRUE
> + MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + !endif
> + !if $(CSM_ENABLE) == TRUE
> + IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Snp16Dxe.inf
> + !endif
> +!endif
> +
> +!if $(NETWORK_ENABLE) == TRUE
> + #
> + # UEFI network modules
> + #
> + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> +
> + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + NetworkPkg/TcpDxe/TcpDxe.inf
> + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + !if $(NETWORK_IP6_ENABLE) == TRUE
> + NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + !endif
> +!endif
> +
> +!if $(CAPSULE_ENABLE) || $(MICOCODE_CAPSULE_ENABLE)
> + MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf
> + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf
> +!endif
> +
> +!if $(CAPSULE_ENABLE)
> + !include Vlv2TbltDevicePkg/FmpMinnowMaxSystem.dsc
> + !include Vlv2TbltDevicePkg/FmpGreenSampleDevice.dsc
> + !include Vlv2TbltDevicePkg/FmpBlueSampleDevice.dsc
> + !include Vlv2TbltDevicePkg/FmpRedSampleDevice.dsc
> +!endif
> +
> +!if $(MICOCODE_CAPSULE_ENABLE)
> +
> IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdateDx
> e.inf {
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> + }
> +!endif
> +
> +[BuildOptions]
> +#
> +# Define Build Options both for EDK and EDKII drivers.
> +#
> +
> +#
> +# Define token for different Platform
> +#
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> + DEFINE MINNOW2_FSP_OPTION = /DMINNOW2_FSP_BUILD
> +!else
> + DEFINE MINNOW2_FSP_OPTION =
> +!endif
> +
> +!if $(ENBDT_PF_BUILD) == TRUE
> + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1
> +!else
> + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0
> +!endif
> +
> +
> +!if $(CLKGEN_CONFIG_EXTRA_ENABLE) == TRUE
> + DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION =
> /DCLKGEN_CONFIG_EXTRA=1
> +!else
> + DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION =
> +!endif
> +
> +
> +
> +!if $(PCIESC_ENABLE) == TRUE
> + DEFINE PCIESC_SUPPORT_BUILD_OPTION = /DPCIESC_SUPPORT=1
> +!else
> + DEFINE PCIESC_SUPPORT_BUILD_OPTION =
> +!endif
> +!if $(SATA_ENABLE) == TRUE
> + DEFINE SATA_SUPPORT_BUILD_OPTION = /DSATA_SUPPORT=1
> +!else
> + DEFINE SATA_SUPPORT_BUILD_OPTION =
> +!endif
> +!if $(ENBDT_S3_SUPPORT) == TRUE
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT
> +!else
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS =
> +!endif
> +
> +!if $(X64_CONFIG) == TRUE
> + DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1
> +!else
> + DEFINE X64_BUILD_ENABLE =
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> + DEFINE DSC_FTPM_BUILD_OPTIONS = /DFTPM_ENABLE
> +!else
> + DEFINE DSC_FTPM_BUILD_OPTIONS =
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + DEFINE DSC_TPM_BUILD_OPTIONS = /DTPM_ENABLED
> +!else
> + DEFINE DSC_TPM_BUILD_OPTIONS =
> +!endif
> +
> +
> + DEFINE EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS =
> $(MINNOW2_FSP_OPTION) $(MINNOW2_BUILD_OPTION)
> $(ENBDT_PF_ENABLE) $(EXTERNAL_VGA_BUILD_OPTION)
> $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)
> $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS)
> $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS)
> $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS)
> $(SYSCTL_ID_BUILD_OPTION) $(CLKGEN_CONFIG_EXTRA_BUILD_OPTION)
> $(SYSCTL_X0_CONVERT_BOARD_OPTION) $(ENBDT_S3_SUPPORT_OPTIONS)
> $(SATA_SUPPORT_BUILD_OPTION) $(PCIESC_SUPPORT_BUILD_OPTION)
> $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS)
> $(DSC_TPM_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)
> +!if $(PERFORMANCE_ENABLE) == TRUE
> + DEFINE PDB_BUILD_OPTION = /Zi
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> + MSFT:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> + GCC:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> + INTEL:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> +!if $(TARGET) == DEBUG
> + DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS = /Od /Oy-
> +!endif
> +!else
> + DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS =
> +
> +!endif
> +
> +#
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support page
> level
> +# protection of DXE_RUNTIME_DRIVER modules
> +#
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +#
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support page
> level
> +# protection of DXE_SMM_DRIVER/SMM_CORE modules
> +#
> +[BuildOptions.common.EDKII.DXE_SMM_DRIVER,
> BuildOptions.common.EDKII.SMM_CORE]
> + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +[BuildOptions.Common.EDK]
> +
> +#
> +# Define token for different Platform
> +#
> +!if $(ENBDT_PF_BUILD) == TRUE
> + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1
> +!else
> + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0
> +!endif
> +
> +!if $(PERFORMANCE_ENABLE) == TRUE
> + RELEASE_*_*_DLINK_FLAGS = /DEBUG
> +!endif
> +
> +!if $(S3_ENABLE) == TRUE
> + DEFINE DSC_S3_BUILD_OPTIONS = /DEFI_S3_RESUME
> +!else
> + DEFINE DSC_S3_BUILD_OPTIONS =
> +!endif
> +
> +!if $(ENBDT_S3_SUPPORT) == TRUE
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT
> +!else
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS =
> +!endif
> +
> +!if $(X64_CONFIG) == TRUE
> + DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1
> +!else
> + DEFINE X64_BUILD_ENABLE =
> +!endif
> +
> +
> + DEFINE EDK_GLUE_LIB_DEBUG =
> + DEFINE DEBUG_BUILD_OPTIONS = /D EFI_DEBUG /D DEBUG_MODE=1
> /GL- $(EDK_GLUE_LIB_DEBUG)
> /DEDKII_GLUE_DebugPrintErrorLevel=(EFI_D_ERROR)
> + DEFINE EDK_DSC_FEATURE_BUILD_OPTIONS = $(DSC_S3_BUILD_OPTIONS)
> $(DSC_ACPI_BUILD_OPTIONS) $(DSC_SEC_BUILD_OPTIONS)
> $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS)
> $(DSC_TPM_BUILD_OPTIONS) $(SOFTSDV_BUILD_OPTIONS)
> $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS)
> $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS)
> $(QT_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)
> /D$(PROJECT_SC_CHIPSET)
> +
> + DEFINE EDK_DSC_OTHER_BUILD_OPTIONS =
> $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SV_BUILD_OPTIONS)
> $(INTEL_FASTBOOT_BUILD_OPTION)
> + DEFINE EDK_DSC_GLOBAL_BUILD_OPTIONS = $(ENBDT_PF_ENABLE)
> $(EDK_DSC_FEATURE_BUILD_OPTIONS)
> $(EDK_DSC_OTHER_BUILD_OPTIONS) /D
> EFI_SPECIFICATION_VERSION=0x00020000 /D
> PI_SPECIFICATION_VERSION=0x00000009 /D
> TIANO_RELEASE_VERSION=0x00080006 /D
> SUPPORT_DEPRECATED_PCI_CFG_PPI /D CSM_SMMENTRY_PORT8DATA8 /D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) /D
> MAX_VARIABLE_SIZE=0x2000 /D EFI_FIRMWARE_VENDOR="L/"INTEL/"" /D
> EFI_BUILD_VERSION="L/"EDKII/"" /DEFI_PEI_REPORT_STATUS_CODE_ON
> $(ENBDT_S3_SUPPORT_OPTIONS)
> +
> + *_*_IA32_ASM_FLAGS = /DEFI32 /D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> /DNOCS_S3_SUPPORT
> + DEBUG_*_IA32_CC_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_CC_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_IA32_VFRPP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_VFRPP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_IA32_APP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_APP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_IA32_PP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_PP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + *_*_IA32_ASLPP_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_IA32_ASLCC_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_IA32_ASM16_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> +
> + *_*_X64_ASM_FLAGS = /DEFIX64 /D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> /DNOCS_S3_SUPPORT
> + DEBUG_*_X64_CC_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_CC_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_X64_VFRPP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_VFRPP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_X64_APP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_APP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_X64_PP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_PP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + *_*_X64_ASLPP_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_X64_ASLCC_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_X64_ASM16_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> + # *_*_*_BUILD_FLAGS = -s
> + *_*_*_VFR_FLAGS = -c
> + *_*_*_BUILD_FLAGS = -c
> +
> +[BuildOptions.Common.EDKII]
> + *_*_IA32_ASM_FLAGS = $(VP_BUILD_OPTIONS) /D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> /DNOCS_S3_SUPPORT
> +
> + *_*_IA32_CC_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_VFRPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_APP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_PP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_ASLPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +
> + *_*_X64_CC_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> $(SOURCE_LEVEL_DEBUG_BUILD_OPTIONS)
> + *_*_X64_VFRPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_X64_APP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_X64_PP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_X64_ASLPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +
> +
> +[Components.IA32]
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cBus.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cHost.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cPortA0Pio.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cMmioDeviceDxe.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
> + }
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
> new file mode 100644
> index 0000000000..10d44d5652
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
> @@ -0,0 +1,1714 @@
> +#/** @file
> +# Platform description.
> +#
> +# Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#**/
> +
> +#########################################################
> #######################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +#########################################################
> #######################
> +[Defines]
> + PLATFORM_NAME = Vlv2TbltDevicePkg
> + PLATFORM_GUID = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x00010005
> +
> + #
> + # Set platform specific package/folder name, same as passed from
> PREBUILD script.
> + # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well
> as package build folder
> + # DEFINE only takes effect at R9 DSC and FDF.
> + #
> + DEFINE PLATFORM_PACKAGE = Vlv2TbltDevicePkg
> + DEFINE PLATFORM_RC_PACKAGE = Vlv2DeviceRefCodePkg
> + DEFINE PLATFORM_BINARY_PACKAGE = Vlv2SocBinPkg
> + OUTPUT_DIRECTORY = Build/$(PLATFORM_PACKAGE)
> + SUPPORTED_ARCHITECTURES = IA32|X64
> + BUILD_TARGETS = DEBUG|RELEASE
> + SKUID_IDENTIFIER = DEFAULT
> +
> + DEFINE CPU_ARCH =ValleyView2
> + DEFINE PROJECT_SC_FAMILY =IntelPch
> + DEFINE PROJECT_SC_ROOT
> =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/SouthCluster
> + DEFINE PROJECT_VLV_ROOT
> =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/NorthCluster
> +
> + DEFINE RC_BINARY_RELEASE = TRUE
> + #
> + # Platform On/Off features are defined here
> + #
> + #
> + # Platform Support:: Set only one token except Crestview Hills
> + #
> + # 3.BayleyBay
> + # ENBDT_PF_ENABLE = TRUE
> + #
> + !include $(PLATFORM_PACKAGE)/AutoPlatformCFG.txt
> + !include $(PLATFORM_PACKAGE)/PlatformPkgConfig.dsc
> +
> +!if $(X64_CONFIG) == TRUE
> + DEFINE DXE_ARCHITECTURE = X64
> + DEFINE EDK_DXE_ARCHITECTURE = X64
> + DEFINE UNDI_DXE_ARCHITECTURE = 64
> +!else
> + DEFINE DXE_ARCHITECTURE = IA32
> + DEFINE EDK_DXE_ARCHITECTURE = Ia32
> + DEFINE UNDI_DXE_ARCHITECTURE = 32
> +!endif
> +
> + FLASH_DEFINITION = $(PLATFORM_PACKAGE)/PlatformPkg.fdf
> +!if $(LFMA_ENABLE) == TRUE
> + FIX_LOAD_TOP_MEMORY_ADDRESS = 0xFFFFFFFFFFFFFFFF
> + DEFINE TOP_MEMORY_ADDRESS = 0xFFFFFFFFFFFFFFFF
> +!else
> + FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
> + DEFINE TOP_MEMORY_ADDRESS = 0x0
> +!endif
> +
> + DEFINE PLATFORM_PCIEXPRESS_BASE = 0E0000000
> +
> + DEFINE SEC_ENABLE = FALSE
> + DEFINE SEC_DEBUG_INFO_ENABLE = FALSE
> + DEFINE FTPM_ENABLE = FALSE
> +
> +#########################################################
> #######################
> +#
> +# SKU Identification section - list of all SKU IDs supported by this
> +# Platform.
> +#
> +#########################################################
> #######################
> +[SkuIds]
> + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
> +
> +#########################################################
> #######################
> +#
> +# Library Class section - list of all Library Classes needed by this Platform.
> +#
> +#########################################################
> #######################
> +[LibraryClasses.common]
> + #
> + # Entry point
> + #
> +
> PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.in
> f
> + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
> +
> DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint
> .inf
> +
> UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry
> Point.inf
> +
> UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA
> pplicationEntryPoint.inf
> +
> DxeSmmDriverEntryPoint|IntelFrameworkPkg/Library/DxeSmmDriverEntryP
> oint/DxeSmmDriverEntryPoint.inf
> +
> + #
> + # Basic
> + #
> + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> +!if $(SSE2_ENABLE) == TRUE
> +
> BaseMemoryLib|MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2
> .inf
> +!else
> +
> BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibR
> epStr.inf
> +!endif
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
> +
> PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibP
> ci.inf
> + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
> + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> +
> CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCac
> heMaintenanceLib.inf
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> +
> PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/Base
> PeCoffGetEntryPointLib.inf
> +!if $(RC_BINARY_RELEASE) == TRUE
> +
> PchPlatformLib|Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.in
> f
> +!endif
> + #
> + # UEFI & PI
> + #
> +
> UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBo
> otServicesTableLib.inf
> +
> UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib
> /UefiRuntimeServicesTableLib.inf
> + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> +
> UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiService
> sLib.inf
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> +
> UefiDecompressLib|MdeModulePkg/Library/BaseUefiTianoCustomDecompr
> essLib/BaseUefiTianoCustomDecompressLib.inf
> +
> PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/P
> eiServicesTablePointerLibIdt.inf
> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> +
> DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTabl
> eLib.inf
> + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
> + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +
> GenericBdsLib|$(PLATFORM_PACKAGE)/Override/IntelFrameworkModuleP
> kg/Library/GenericBdsLib/GenericBdsLib.inf
> +
> BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupp
> ortLib.inf
> + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
> +
> PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformB
> dsLib.inf
> + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
> +
> FlashDeviceLib|$(PLATFORM_PACKAGE)/Library/FlashDeviceLib/FlashDevice
> Lib.inf
> +
> UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBoo
> tManagerLib.inf
> + #
> + # Framework
> + #
> +!if $(S3_ENABLE) == TRUE
> +
> S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootSc
> riptLib.inf
> +!else
> +
> S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL
> ibNull.inf
> +!endif
> + S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
> + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
> +
> + #
> + # Generic Modules
> + #
> +!if $(USB_ENABLE) == TRUE
> + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +!endif
> +!if $(SCSI_ENABLE) == TRUE
> + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
> +!endif
> +!if $(NETWORK_ENABLE) == TRUE
> + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
> + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
> + TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
> + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
> +!endif
> +!if $(S3_ENABLE) == TRUE
> + S3Lib|IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf
> +!endif
> +
> +
> OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibN
> ull/OemHookStatusCodeLibNull.inf
> +!if $(CAPSULE_ENABLE) == TRUE
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf
> +!else
> +
> CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.i
> nf
> +!endif
> +
> FmpAuthenticationLib|MdeModulePkg/Library/FmpAuthenticationLibNull/F
> mpAuthenticationLibNull.inf
> + IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf
> +
> PlatformFlashAccessLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/Platfor
> mFlashAccessLib/PlatformFlashAccessLib.inf
> +
> MicrocodeFlashAccessLib|Vlv2TbltDevicePkg/Feature/Capsule/Library/Platfo
> rmFlashAccessLib/PlatformFlashAccessLib.inf
> +
> DisplayUpdateProgressLib|MdeModulePkg/Library/DisplayUpdateProgressLi
> bGraphics/DisplayUpdateProgressLibGraphics.inf
> +
> SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniz
> ationLib.inf
> +
> SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementL
> ib/DxeSecurityManagementLib.inf
> + IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
> +
> DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/Bas
> eDebugPrintErrorLevelLib.inf
> +
> + #
> + # CPU
> + #
> + MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
> +
> LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.in
> f
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeC
> puExceptionHandlerLib.inf
> + MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
> +
> + #
> + # ICH
> + #
> + SmbusLib|$(PLATFORM_PACKAGE)/Library/SmbusLib/SmbusLib.inf
> + SmmLib|$(PLATFORM_PACKAGE)/Library/PchSmmLib/PchSmmLib.inf
> +
> + #
> + # Platform
> + #
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +
> ResetSystemLib|$(PLATFORM_PACKAGE)/Library/ResetSystemLib/ResetSys
> temLib.inf
> +
> +
> PlatformCmosLib|$(PLATFORM_PACKAGE)/Library/PlatformCmosLib/Platfor
> mCmosLib.inf
> +
> + #
> + # Misc
> + #
> +
> MonoStatusCodeLib|$(PLATFORM_PACKAGE)/MonoStatusCode/MonoStat
> usCode.inf
> +!if $(TARGET) == RELEASE
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +
> SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.in
> f
> +!else
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> +!endif
> +
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +!if $(TPM_ENABLED) == TRUE
> + TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf
> +
> Tpm12CommandLib|SecurityPkg/Library/Tpm12CommandLib/Tpm12Comma
> ndLib.inf
> +
> Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLib
> DTpm.inf
> +
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibD
> ebug/PeCoffExtraActionLibDebug.inf
> +
> DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicati
> onLibSerialPort/DebugCommunicationLibSerialPort.inf
> +
> PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePla
> tformHookLibNull.inf
> +
> SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort
> Lib16550.inf
> +!else
> +
> PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BaseP
> eCoffExtraActionLibNull.inf
> +
> DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLi
> bNull.inf
> +!endif
> +
> + #
> + # CryptLib
> + #
> +!if $(TPM_ENABLED) == TRUE
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> +!endif
> +
> + BiosIdLib|$(PLATFORM_PACKAGE)/Library/BiosIdLib/BiosIdLib.inf
> + CpuIA32Lib|$(PLATFORM_PACKAGE)/Library/CpuIA32Lib/CpuIA32Lib.inf
> +
> +
> StallSmmLib|$(PLATFORM_PACKAGE)/Library/StallSmmLib/StallSmmLib.inf
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> +
> PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecu
> reLibNull.inf
> +
> TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTp
> mMeasurementLib.inf
> + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
> + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> +!else
> +
> TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/Tp
> mMeasurementLibNull.inf
> +
> AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableL
> ibNull.inf
> +!endif
> + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> +!if $(RC_BINARY_RELEASE) == TRUE
> + I2cLib|Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
> +!endif
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> +
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComma
> ndLib.inf
> +
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingL
> ib.inf
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> +!if $(FTPM_ENABLE) == TRUE || $(NETWORK_ISCSI_ENABLE) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> +!endif
> +
> TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTp
> mMeasurementLib.inf
> +
> Tcg2PhysicalPresenceLib|SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/D
> xeTcg2PhysicalPresenceLib.inf
> +
> Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorL
> ibNull.inf
> +
> +
> +
> Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandL
> ib.inf
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> + FspApiLib|IntelFspWrapperPkg/Library/BaseFspApiLib/BaseFspApiLib.inf
> +
> FspPlatformInfoLib|IntelFspWrapperPkg/Library/BaseFspPlatformInfoLibSa
> mple/BaseFspPlatformInfoLibSample.inf
> +
> FspPlatformSecLib|Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSe
> cLibVlv2/FspPlatformSecLibVlv2.inf
> +
> FspHobProcessLib|Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcess
> LibVlv2/FspHobProcessLibVlv2.inf
> +!endif
> +
> + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> +
> +[LibraryClasses.IA32.SEC]
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> +!endif
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +
> +[LibraryClasses.IA32.PEIM, LibraryClasses.IA32.PEI_CORE,
> LibraryClasses.IA32.SEC]
> + #
> + # PEI phase common
> + #
> +
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> +
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory
> AllocationLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiR
> eportStatusCodeLib.inf
> +
> ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiEx
> tractGuidedSectionLib.inf
> +
> MultiPlatformLib|$(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPl
> atformLib.inf
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecP
> eiCpuExceptionHandlerLib.inf
> + MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
> +
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanc
> eLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> +!if $(TARGET) == RELEASE
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +
> SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.in
> f
> +!else
> +
> DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDx
> eDebugLibReportStatusCode.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> +!endif
> +
> +
> LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
> +
> HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoR
> outerPei.inf
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAg
> entLib.inf
> +!endif
> +
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> +
> PlatformFspLib|Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.in
> f
> + !endif
> +!if $(FTPM_ENABLE) == TRUE
> +
> Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCPei/Tpm2Devi
> ceLibSeC.inf
> +!endif
> +
> +[LibraryClasses.X64]
> + #
> + # DXE phase common
> + #
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemo
> ryAllocationLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/Dx
> eReportStatusCodeLib.inf
> +
> ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeE
> xtractGuidedSectionLib.inf
> +
> +
> TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/Dxe
> TcgPhysicalPresenceLib.inf
> +!if $(TPM_ENABLED) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> +!endif
> +
> +
> LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.in
> f
> +
> EfiRegTableLib|$(PLATFORM_PACKAGE)/Library/EfiRegTableLib/EfiRegTable
> Lib.inf
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> +!endif
> +
> +
> HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoR
> outerDxe.inf
> +
> +[LibraryClasses.X64.DXE_DRIVER]
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> +
> CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Custo
> mizedDisplayLib.inf
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerforma
> nceLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +
> FlashDeviceLib|$(PLATFORM_PACKAGE)/Library/FlashDeviceLib/FlashDevice
> LibDxe.inf
> +
> +[LibraryClasses.X64.DXE_CORE]
> + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> +
> MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLi
> b/DxeCoreMemoryAllocationLib.inf
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCore
> PerformanceLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +[LibraryClasses.X64.DXE_SMM_DRIVER]
> +
> MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTabl
> eLib.inf
> +
> SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesT
> ableLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/S
> mmReportStatusCodeLib.inf
> +
> MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMe
> moryAllocationLib.inf
> +
> LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.i
> nf
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
> +
> SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull
> /SmmCpuPlatformHookLibNull.inf
> +
> SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFea
> turesLib.inf
> +
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
> + !if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAge
> ntLib.inf
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> +!endif
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/Smm
> CpuExceptionHandlerLib.inf
> +
> +[LibraryClasses.X64.SMM_CORE]
> +
> MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocatio
> nLib/PiSmmCoreMemoryAllocationLib.inf
> +
> SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTabl
> eLib/PiSmmCoreSmmServicesTableLib.inf
> +
> ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/S
> mmReportStatusCodeLib.inf
> +
> SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHook
> LibNull/SmmCorePlatformHookLibNull.inf
> + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
> +
> +!if $(TPM_ENABLED) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
> +!endif
> +
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc
> eLibNull.inf
> +
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> +
> +[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
> +
> ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCod
> eLib/RuntimeDxeReportStatusCodeLib.inf
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +!if $(CAPSULE_ENABLE) == TRUE
> +
> CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsule
> Lib.inf
> +!endif
> +
> +[LibraryClasses.common.UEFI_DRIVER]
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +[LibraryClasses.X64.UEFI_APPLICATION]
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgen
> tLib.inf
> +!endif
> +
> +#########################################################
> #######################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +#########################################################
> #######################
> +[PcdsFeatureFlag.common]
> +!if $(MINI_BIOS_ENABLE) == FALSE
> + gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|TRUE
> +!else
> +
> gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|FALSE
> +!endif
> +#
> +# If PcdDxeIplSwitchToLongMode is TRUE, DxeIpl will load a 64-bit DxeCore
> and switch to long mode to hand over to DxeCore.
> +#
> + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
> +
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserGrayOutTextStatement|TR
> UE
> +
> +!if $(CAPSULE_RESET_ENABLE) == TRUE
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE
> +!else
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALS
> E
> +!endif
> + gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
> +!if $(DATAHUB_STATUS_CODE_ENABLE) == TRUE
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub
> |TRUE
> +!else
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub
> |FALSE
> +!endif
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSecti
> onFirst|FALSE
> +!if $(TARGET) == RELEASE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> +!else
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> +!endif
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
> +!if $(ISA_SERIAL_STATUS_CODE_ENABLE) == TRUE
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|TRUE
> +!else
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|FALSE
> +!endif
> +!if $(USB_SERIAL_STATUS_CODE_ENABLE) == TRUE
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|TRUE
> +!else
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|FALSE
> +!endif
> +!if $(RAM_SERIAL_STATUS_CODE_ENABLE) == TRUE
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|TRUE
> +!else
> + gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|FALSE
> +!endif
> +
> +
> + ## This PCD specifies whether PS2 keyboard does a extended verification
> during start.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|FALSE
> +
> + ## This PCD specifies whether PS2 mouse does a extended verification
> during start.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|FA
> LSE
> +
> +!if $(VARIABLE_INFO_ENABLE) == TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|TRUE
> +!else
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|FALSE
> +!endif
> +
> + gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE
> +
> +!if $(SOURCE_DEBUG_ENABLE)
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|TRUE
> +!endif
> +
> +[PcdsFixedAtBuild.common]
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> +# $(FLASH_REGION_VLVMICROCODE_BASE)
> +
> gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
> +# $(FLASH_REGION_VLVMICROCODE_SIZE)
> +
> gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0004000
> 0
> + gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
> +# $(FLASH_AREA_BASE_ADDRESS)
> + gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
> +# $(FLASH_AREA_SIZE)
> + gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00800000
> +# $(FLASH_REGION_FSPBIN_BASE)
> + gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFCC0000
> +!endif
> +
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> + # in FSP, when this got used, the memory already is up
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
> +!else
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
> +!endif
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
> +
> +!else
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
> + !else
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
> + !endif
> + gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
> + gEfiCpuTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x3C00
> +!endif
> +
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x22000
> +!else
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000
> +!endif
> + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x4
> 00
> + gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemory
> Size|0x10000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
> + gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000
> +!if $(S4_ENABLE) == TRUE
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationC
> hange|TRUE
> +!else
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationC
> hange|FALSE
> +!endif
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +!endif
> +!if $(PERFORMANCE_ENABLE) == TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|60
> +!endif
> +
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySi
> ze|0x10000
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(
> TOP_MEMORY_ADDRESS)
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
> + gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVbeEna
> ble|TRUE
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnab
> le|TRUE
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FAL
> SE
> +
> gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|2
> +!endif
> +
> + #
> + # Set SMM stack size to 16 KB.
> + #
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000
> +
> + #
> + # Clear unused single certificate PCD
> + #
> + gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer|{0}
> +
> + #
> + # Lock all updatable firmware devices at End of DXE
> + #
> +
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceLockEventGuid|{GUID(gEfiE
> ndOfDxeEventGroupGuid)}
> +#
> gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceLockEventGuid|{GUID(gEfiE
> ventReadyToBootGuid)}
> +
> + #
> + # Set PcdFmpDeviceTestKeySha256Digest to {0} to disable test key
> detection
> + #
> +# gFmpDevicePkgTokenSpaceGuid.PcdFmpDeviceTestKeySha256Digest|{0}
> +
> +[PcdsFixedAtBuild.IA32]
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +!endif
> +
> +!if $(RECOVERY_ENABLE)
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryFileName|L"VLV2REC.Cap
> "
> +!endif
> +
> +[PcdsPatchableInModule.common]
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
> +
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x$(PLATFORM_PC
> IEXPRESS_BASE)
> +
> gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacy
> Region|FALSE
> +
> + ## This PCD specifies whether to use the optimized timing for best PS2
> detection performance.
> + # Note this PCD could be set to TRUE for best boot performance and set to
> FALSE for best device compatibility.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE
> +
> +
> ##########################################################
> #############################################
> + #
> + # Begin of MRC parameters
> + #
> +
> + ## Memory Parameter Patchable.
> + # FALSE - MRC Parameters are fixed for MinnowBoard Max<BR>
> + # TRUE - MRC Parameters are patchable by following PCDs<BR>
> + # @Prompt Memory Parameter Patchable.
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|FALSE
> +
> + ## Memory Down or DIMM slot.
> + # 0 - DIMM<BR>
> + # 1 - Memory Down<BR>
> + # @Prompt Enable Memory Down
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|1
> +
> + ## The speed of DRAM.
> + # 0 - 800 MHz<BR>
> + # 1 - 1066 MHz<BR>
> + # 2 - 1333 MHz<BR>
> + # 3 - 1600 MHz<BR>
> + # @Prompt DRAM Speed
> + # @ValidList 0x80000001 | 0, 1, 2, 3
> + gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|1
> +
> + ## DRAM Type.
> + # 0 - DDR3<BR>
> + # 1 - DDR3L<BR>
> + # 2 - DDR3U<BR>
> + # 3 - DDR3All<BR>
> + # 4 - LPDDR2<BR>
> + # 5 - LPDDR3<BR>
> + # 6 - DDR4<BR>
> + # @Prompt DRAM Type
> + # @ValidList 0x80000001 | 0, 1, 2, 3, 4, 5, 6
> + gVlvRefCodePkgTokenSpaceGuid.PcdDramType|1
> +
> + ## Please populate DIMM slot 0 if only one DIMM is supported.
> + # 0 - Disable<BR>
> + # 1 - Enable<BR>
> + # @Prompt DIMM 0 Enable
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|1
> +
> + ## DIMM 1 has to be identical to DIMM 0.
> + # 0 - Disable<BR>
> + # 1 - Enable<BR>
> + # @Prompt DIMM 1 Enable Type
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0
> +
> + ## DRAM device data width.
> + # 0 - x8<BR>
> + # 1 - x16<BR>
> + # 2 - x32<BR>
> + # @Prompt DIMM_DWIDTH
> + # @ValidList 0x80000001 | 0, 1, 2
> + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|1
> +
> + ## DRAM device data density.
> + # 0 - 1 Gbit<BR>
> + # 1 - 2 Gbit<BR>
> + # 2 - 4 Gbit<BR>
> + # 3 - 8 Gbit<BR>
> + # @Prompt DIMM_Density
> + # @ValidList 0x80000001 | 0, 1, 2, 3
> + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|2
> +
> + ## DRAM device data bus width.
> + # 0 - 8 bits<BR>
> + # 1 - 16 bits<BR>
> + # 2 - 32 bits<BR>
> + # 3 - 64 bits<BR>
> + # @Prompt DIMM_BusWidth
> + # @ValidList 0x80000001 | 0, 1, 2, 3
> + gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|3
> +
> + ## Ranks Per DIMM or Sides Per DIMM.
> + # 0 - 1 Rank<BR>
> + # 1 - 2 Ranks<BR>
> + # @Prompt DIMM_Sides
> + # @ValidList 0x80000001 | 0, 1
> + gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0
> +
> + ## tCL.<BR><BR>
> + # @Prompt tCL
> + gVlvRefCodePkgTokenSpaceGuid.PcdTcl|11
> +
> + ## tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc.
> + # @Prompt tRP_tRCD
> + gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|11
> +
> + ## tWR in DRAM clk.
> + # @Prompt tWR
> + gVlvRefCodePkgTokenSpaceGuid.PcdTwr|12
> +
> + ## tWTR in DRAM clk.
> + # @Prompt tWTR
> + gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|6
> +
> + ## tRRD in DRAM clk.
> + # @Prompt tRRD
> + gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|6
> +
> + ## tRTP in DRAM clk.
> + # @Prompt tRTP
> + gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|6
> +
> + ## tFAW in DRAM clk.
> + # @Prompt tFAW
> + gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|32
> +
> + #
> + # End of MRC parameters.
> + #
> +
> ##########################################################
> #####################################
> +
> +[PcdsDynamicHii.common.DEFAULT]
> +
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlo
> balVariableGuid|0x0|5 # Variable: L"Timeout"
> +
> gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSup
> port"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
> +
> +[PcdsDynamicDefault.common.DEFAULT]
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x
> 0
> + !if $(TPM_ENABLED) == TRUE
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd,
> 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}
> + !endif
> +
> + ## This PCD defines the video horizontal resolution.
> + # This PCD could be set to 0 then video resolution could be at highest
> resolution.
> + #gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
> + ## This PCD defines the video vertical resolution.
> + # This PCD could be set to 0 then video resolution could be at highest
> resolution.
> + #gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
> +
> + ## This PCD defines the Console output column and the default value is 25
> according to UEFI spec.
> + # This PCD could be set to 0 then console output could be at max column
> and max row.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
> + ## This PCD defines the Console output row and the default value is 80
> according to UEFI spec.
> + # This PCD could be set to 0 then console output could be at max column
> and max row.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
> +
> + ## The PCD is used to specify the video horizontal resolution of text setup.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|80
> 0
> + ## The PCD is used to specify the video vertical resolution of text setup.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
> + ## The PCD is used to specify the console output column of text setup.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100
> + ## The PCD is used to specify the console output column of text setup.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|31
> +
> +!if $(TPM_ENABLED) == TRUE
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1
> +!endif
> +
> +[PcdsDynamicExDefault.common.DEFAULT]
> + gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040
> + gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId|0
> + gEfiVLVTokenSpaceGuid.PcdProductSerialNumber|0
> + gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable|TRUE
> + gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur|FALSE
> + gEfiVLVTokenSpaceGuid.PcdFTPMErrorSkip|FALSE
> + gEfiVLVTokenSpaceGuid.PcdFTPMCommand|0
> + gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0
> + gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE
> + gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataP
> tr|0
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0
> + gEfiCpuTokenSpaceGuid.PcdCpuS3DataAddress|0
> + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugDataAddress|0
> + gEfiCpuTokenSpaceGuid.PcdCpuCallbackSignal|0
> + gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer|0
> + gEfiVLVTokenSpaceGuid.PcdCpuLockBoxDataAddress|0
> + gEfiVLVTokenSpaceGuid.PcdCpuSmramCpuDataAddress|0
> + gEfiVLVTokenSpaceGuid.PcdCpuLockBoxSize|0
> +
> +[PcdsDynamicExDefault.X64.DEFAULT]
> +!if $(RECOVERY_ENABLE)
> +
> gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{G
> UID("AF9C9EB2-12AD-4D3E-A4D4-96F6C9966215")}|VOID*|0x10
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGu
> id|{GUID("4096267b-da0a-42eb-b5eb-fef31d207cb4")}|VOID*|0x10
> +!endif
> +
> +[Components.IA32]
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/S
> ecCore.inf
> +
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> + IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf {
> + !if $(TARGET) == DEBUG
> +
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + }
> + Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
> + IntelFspWrapperPkg/FspInitPei/FspInitPei.inf {
> + !if $(TARGET) == DEBUG
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + }
> + !endif
> +
> + MdeModulePkg/Core/Pei/PeiMain.inf {
> +!if $(TARGET) == DEBUG
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> +!endif
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + }
> +
> + $(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf {
> +!if $(TARGET) == DEBUG
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> +!endif
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/M
> emoryInit.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <BuildOptions>
> + !if $(FTPM_ENABLE)==TRUE
> + *_*_IA32_CC_FLAGS = /D FTPM_ENABLE
> + !endif
> + }
> +
> +!if $(RC_BINARY_RELEASE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/S
> eCUma.inf
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> +$(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/f
> TPMInitPeim.inf
> +!endif
> +
> +!if $(RC_BINARY_RELEASE) == TRUE
> + $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf {
> + <BuildOptions>
> + *_*_IA32_CC_FLAGS = /DRC_BINARY_RELEASE
> + !if $(TARGET) == DEBUG
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
> + !endif
> + }
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> + SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf{
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAg
> entLib.inf
> +
> PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePla
> tformHookLibNull.inf
> +
> SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort
> Lib16550.inf
> + }
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/T
> pm2DeviceSeCPei.inf
> +!endif
> +
> +!if $(TPM_ENABLED) == TRUE
> + SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
> + SecurityPkg/Tcg/TcgPei/TcgPei.inf {
> + <LibraryClasses>
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.in
> f
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> +}
> +!endif
> +
> + $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
> + <LibraryClasses>
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> + $(PLATFORM_PACKAGE)/FvInfoPei/FvInfoPei.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Vl
> vInitPeim.inf
> +!if $(PCIESC_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chEarlyInitPeim.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + }
> +!endif
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chInitPeim.inf
> +
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chSmbusArpDisabled.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chSpiPeim.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> eiSmmAccess.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> eiSmmControl.inf
> + MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/C
> puPeim.inf
> + UefiCpuPkg/CpuIoPei/CpuIoPei.inf
> + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/M
> pS3.inf
> +#
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Pi
> SmmCommunicationPei.inf
> +
> +!if $(RECOVERY_ENABLE)
> + #
> + # Recovery
> + #
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/P
> chUsb.inf
> + MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf
> + MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf
> + MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf
> + FatPkg/FatPei/FatPei.inf
> + MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf
> +
> SignedCapsulePkg/Universal/RecoveryModuleLoadPei/RecoveryModuleLoa
> dPei.inf {
> + <LibraryClasses>
> +
> FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibRsa2048Sh
> a256/FmpAuthenticationLibRsa2048Sha256.inf
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +!endif
> +
> +!if $(CAPSULE_ENABLE) == TRUE
> + MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
> +!endif
> + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
> + <LibraryClasses>
> +!if $(LZMA_ENABLE) == TRUE
> +
> NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDec
> ompressLib.inf
> +!endif
> + }
> +
> + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> +
> MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> +
> +!if $(FTPM_ENABLE) == TRUE
> + SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +
> NULL|SecurityPkg/Library\HashInstanceLibSha1/HashInstanceLibSha1.inf
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.in
> f
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +!endif
> +!if $(ACPI50_ENABLE) == TRUE
> +
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/Firmwa
> rePerformancePei.inf{
> + <LibraryClasses>
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> + }
> +
> +!endif
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCode
> RouterPei.inf
> +!endif
> +[Components.X64]
> + !if $(MINNOW2_FSP_BUILD) == TRUE
> + IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf {
> + !if $(TARGET) == DEBUG
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + }
> +
> + !endif
> + #
> + # EDK II Related Platform codes
> + #
> + MdeModulePkg/Core/Dxe/DxeMain.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + <LibraryClasses>
> +!if $(DXE_CRC32_SECTION_ENABLE) == TRUE
> +
> NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32G
> uidedSectionExtractLib.inf
> +!endif
> +!if $(LZMA_ENABLE) == TRUE
> +
> NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDec
> ompressLib.inf
> +!endif
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + }
> +
> IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.i
> nf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> + <LibraryClasses>
> + !if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + <BuildOptions>
> + ICC:*_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
> + GCC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG
> + }
> + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + }
> + IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
> + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
> +
> +
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportSt
> atusCodeRouterRuntimeDxe.inf
> +
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHan
> dlerRuntimeDxe.inf {
> + <LibraryClasses>
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + }
> +
> +!if $(CAPSULE_ENABLE) == TRUE
> + MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> +
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory
> AllocationLib.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecP
> eiCpuExceptionHandlerLib.inf
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> +
> DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAg
> entLib.inf
> +!endif
> + }
> +!endif
> +
> +
> MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCod
> eRouterSmm.inf
> + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf{
> + <LibraryClasses>
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> +
> NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib
> .inf
> +!endif
> +!if $(USER_IDENTIFICATION_ENABLE)
> +
> NULL|SecurityPkg/Library/DxeDeferImageLoadLib/DxeDeferImageLoadLib.in
> f
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> +
> NULL|SecurityPkg/Library/DxeTpmMeasureBootLib/DxeTpmMeasureBootLi
> b.inf
> +!endif
> +!if $(FTPM_ENABLE) == TRUE
> +
> NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBoot
> Lib.inf
> +!endif
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MpCpu.inf
> + $(PLATFORM_PACKAGE)/Metronome/Metronome.inf
> +
> + IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf{
> + <LibraryClasses>
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> +
> PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformB
> dsLib.inf
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> + !if $(FTPM_ENABLE) == TRUE
> +
> Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2Devi
> ceLibSeC.inf
> + !else
> +
> Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibTcg2/Tpm2DeviceLibTcg2
> .inf
> + !endif
> + }
> +
> + $(PLATFORM_PACKAGE)/UiApp/UiApp.inf
> +
> + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> +
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.in
> f
> +
> MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.i
> nf
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> + }
> + $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
> +
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.i
> nf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSpiSmm.inf
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> +
> SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfi
> gDxe.inf {
> + <LibraryClasses>
> +
> PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecu
> reLibNull.inf
> + <BuildOptions>
> + #
> + # Specify GUID gEfiIfrBootMaintenanceGuid, to install Secure Boot
> Configuration menu
> + # into Boot Maintenance Manager menu
> + #
> + *_*_*_VFR_FLAGS = -g b2dedc91-d59f-48d2-898a-12490c74a4e0
> + }
> +!endif
> + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf {
> + <LibraryClasses>
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> + }
> +
> +
> MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCoun
> terRuntimeDxe.inf
> +
> PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime
> Dxe.inf
> + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> +
> + $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf
> +
> + $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf
> +
> +!if $(DATAHUB_ENABLE) == TRUE
> + IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
> + }
> +!endif
> +
> IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandl
> erDxe/DatahubStatusCodeHandlerDxe.inf
> +
> MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryT
> estDxe.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchS3SupportDxe.inf
> + !if $(USE_HPET_TIMER) == TRUE
> + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
> + !else
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmartTimer.inf
> + !endif
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmmControl.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSmbusDxe.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/IntelPchLegacyInterrupt.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchReset.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchInitDxe.inf{
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchInitSmm.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSmiDispatcher.inf
> +
> +!if $(PCIESC_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchPcieSmm.inf
> +!endif
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchSpiRuntime.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchPolicyInitDxe.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PchBiosWriteProtect.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmmAccess.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PciHostBridge.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/VlvInitDxe.inf
> +
> +
> IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.i
> nf
> +
> + #
> + # Performance Application; Set PERFORMANCE_ENABLE=TRUE for normal
> boot performance and smm performance data
> + #
> +!if $(PERFORMANCE_ENABLE) == TRUE
> +
> ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf
> {
> + <PcdsFixedAtBuild>
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> + }
> +!endif
> +
> + Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf{
> + <LibraryClasses>
> +!if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> +!endif
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/Dptf.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PnpDxe.inf
> +
> +!if $(SEC_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/HeciDrv.inf {
> +!if $(SEC_DEBUG_INFO_ENABLE) == TRUE
> + <BuildOptions>
> + *_*_X64_CC_FLAGS = /DSEC_DEBUG_INFO=1
> +!else
> + <BuildOptions>
> + *_*_X64_CC_FLAGS = /DSEC_DEBUG_INFO=0
> +!endif
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SeCPolicyInitDxe.inf
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/Tpm2DeviceSeCDxe.inf
> + SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf
> + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf{
> + <LibraryClasses>
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.in
> f
> + PcdLib|MdePkg/Library\DxePcdLib/DxePcdLib.inf
> +
> Tpm2DeviceLib|Vlv2TbltDevicePkg/Library/Tpm2DeviceLibSeCDxe/Tpm2Devi
> ceLibSeC.inf
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/FtpmSmm.inf
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + }
> +
> + SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + <BuildOptions>
> + #
> + # specify GUID gEfiIfrNotInTPVPageGuid, this page will not
> + # be showed in TPV page.
> + #
> + *_*_*_VFR_FLAGS = -g e58809f8-fbc1-48e2-883a-a30fdc4b441e
> + }
> +
> + SecurityPkg/Tcg/TcgDxe/TcgDxe.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> + SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
> +!endif
> + #
> + # EDK II Related Platform codes
> + #
> + $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf{
> + <LibraryClasses>
> + !if $(TARGET) != RELEASE
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + !endif
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> + $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf
> + $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
> + $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf
> +
> + $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf
> + $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PlatformCpuPolicy.inf
> + $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf
> +
> $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHand
> lerSmm.inf
> +!if $(GOP_DRIVER_ENABLE) == TRUE
> + $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf
> +
> +!endif
> +
> +
> + #
> + # SMM
> + #
> + MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
> + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
> + UefiCpuPkg/CpuDxe/CpuDxe.inf
> + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
> + UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
> + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
> + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
> +
> $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmS
> wDispatch2OnSmmSwDispatchThunk.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/PowerManagement2.inf
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/DigitalThermalSensor.inf
> +
> + #
> + # ACPI
> + #
> +
> MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutor
> Dxe.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + }
> +
> + $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf
> +
> IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDx
> e.inf
> +
> Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTable
> s/PowerManagementAcpiTables.inf
> +
> + $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf
> +
> + $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf
> +
> +
> MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraph
> icsResourceTableDxe.inf
> +
> + #
> + # PCI
> + #
> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/ISPDxe.inf
> +
> +
> +#
> +# ISA
> +#
> + $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf
> + IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
> + IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf
> + IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
> + IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
> +
> IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
> +#
> +# SDIO
> +#
> +#
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MmcHost.inf
> +#
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/MmcMediaDevice.inf
> +!if $(ACPI50_ENABLE) == TRUE
> +
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/Firmw
> arePerformanceDxe.inf {
> + <LibraryClasses>
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> + }
> +
> MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/Firm
> warePerformanceSmm.inf {
> + <LibraryClasses>
> +
> TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAc
> piTimerLib.inf
> + }
> +!endif
> +
> +#
> +# IDE/SCSI/AHCI
> +#
> + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> + IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf
> + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> +
> MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + FatPkg/EnhancedFatDxe/Fat.inf
> + ShellPkg/Application/Shell/Shell.inf {
> + <LibraryClasses>
> +
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComma
> ndLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1
> CommandsLib.inf
> +
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingL
> ib.inf
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> +
> BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg
> CommandLib.inf
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
> + }
> +!if $(SATA_ENABLE) == TRUE
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SataController.inf
> +!endif
> + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +!if $(SCSI_ENABLE) == TRUE
> + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +!endif
> +#
> +# Console
> +#
> + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> +
> MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleD
> xe.inf
> +
> IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.in
> f
> + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> +
> + #
> + # USB
> + #
> +!if $(USB_ENABLE) == TRUE
> + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
> + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +
> +!endif
> +
> + #
> + # SMBIOS
> + #
> + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
> + $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/SmbiosMemory.inf
> + #
> + # CPU/FW Microde
> + #
> + Vlv2SocBinPkg/Microcode/MicrocodeUpdates.inf {
> + <BuildOptions>
> + *_*_*_GENFW_FLAGS = -a 0x800 -p 0xFF
> + }
> +
> +
> +
> +!if $(NETWORK_ENABLE) == TRUE
> + !if $(NETWORK_ISCSI_ENABLE) == TRUE
> + NetworkPkg/IScsiDxe/IScsiDxe.inf
> + !endif
> + !if $(NETWORK_VLAN_ENABLE) == TRUE
> + MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + !endif
> + !if $(CSM_ENABLE) == TRUE
> + IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Snp16Dxe.inf
> + !endif
> +!endif
> +
> +!if $(NETWORK_ENABLE) == TRUE
> + #
> + # UEFI network modules
> + #
> + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> +
> + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + NetworkPkg/TcpDxe/TcpDxe.inf
> + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + !if $(NETWORK_IP6_ENABLE) == TRUE
> + NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + !endif
> +!endif
> +
> +!if $(CAPSULE_ENABLE) || $(MICOCODE_CAPSULE_ENABLE)
> + MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf
> + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf
> +!endif
> +
> +!if $(CAPSULE_ENABLE)
> + !include Vlv2TbltDevicePkg/FmpMinnowMaxSystem.dsc
> + !include Vlv2TbltDevicePkg/FmpGreenSampleDevice.dsc
> + !include Vlv2TbltDevicePkg/FmpBlueSampleDevice.dsc
> + !include Vlv2TbltDevicePkg/FmpRedSampleDevice.dsc
> +!endif
> +
> +!if $(MICOCODE_CAPSULE_ENABLE)
> +
> IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdateDx
> e.inf {
> + <LibraryClasses>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
> inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
> + }
> +!endif
> +
> +[BuildOptions]
> +#
> +# Define Build Options both for EDK and EDKII drivers.
> +#
> +
> +#
> +# Define token for different Platform
> +#
> +!if $(MINNOW2_FSP_BUILD) == TRUE
> + DEFINE MINNOW2_FSP_OPTION = /DMINNOW2_FSP_BUILD
> +!else
> + DEFINE MINNOW2_FSP_OPTION =
> +!endif
> +
> +!if $(ENBDT_PF_BUILD) == TRUE
> + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1
> +!else
> + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0
> +!endif
> +
> +
> +!if $(CLKGEN_CONFIG_EXTRA_ENABLE) == TRUE
> + DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION =
> /DCLKGEN_CONFIG_EXTRA=1
> +!else
> + DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION =
> +!endif
> +
> +
> +
> +!if $(PCIESC_ENABLE) == TRUE
> + DEFINE PCIESC_SUPPORT_BUILD_OPTION = /DPCIESC_SUPPORT=1
> +!else
> + DEFINE PCIESC_SUPPORT_BUILD_OPTION =
> +!endif
> +!if $(SATA_ENABLE) == TRUE
> + DEFINE SATA_SUPPORT_BUILD_OPTION = /DSATA_SUPPORT=1
> +!else
> + DEFINE SATA_SUPPORT_BUILD_OPTION =
> +!endif
> +!if $(ENBDT_S3_SUPPORT) == TRUE
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT
> +!else
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS =
> +!endif
> +
> +!if $(X64_CONFIG) == TRUE
> + DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1
> +!else
> + DEFINE X64_BUILD_ENABLE =
> +!endif
> +
> +!if $(FTPM_ENABLE) == TRUE
> + DEFINE DSC_FTPM_BUILD_OPTIONS = /DFTPM_ENABLE
> +!else
> + DEFINE DSC_FTPM_BUILD_OPTIONS =
> +!endif
> +!if $(TPM_ENABLED) == TRUE
> + DEFINE DSC_TPM_BUILD_OPTIONS = /DTPM_ENABLED
> +!else
> + DEFINE DSC_TPM_BUILD_OPTIONS =
> +!endif
> +
> +
> + DEFINE EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS =
> $(MINNOW2_FSP_OPTION) $(MINNOW2_BUILD_OPTION)
> $(ENBDT_PF_ENABLE) $(EXTERNAL_VGA_BUILD_OPTION)
> $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)
> $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS)
> $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS)
> $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS)
> $(SYSCTL_ID_BUILD_OPTION) $(CLKGEN_CONFIG_EXTRA_BUILD_OPTION)
> $(SYSCTL_X0_CONVERT_BOARD_OPTION) $(ENBDT_S3_SUPPORT_OPTIONS)
> $(SATA_SUPPORT_BUILD_OPTION) $(PCIESC_SUPPORT_BUILD_OPTION)
> $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS)
> $(DSC_TPM_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)
> +!if $(PERFORMANCE_ENABLE) == TRUE
> + DEFINE PDB_BUILD_OPTION = /Zi
> +!endif
> +
> +!if $(SOURCE_DEBUG_ENABLE) == TRUE
> + MSFT:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> + GCC:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> + INTEL:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> +!if $(TARGET) == DEBUG
> + DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS = /Od /Oy-
> +!endif
> +!else
> + DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS =
> +
> +!endif
> +
> +#
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support page
> level
> +# protection of DXE_RUNTIME_DRIVER modules
> +#
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +#
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support page
> level
> +# protection of DXE_SMM_DRIVER/SMM_CORE modules
> +#
> +[BuildOptions.common.EDKII.DXE_SMM_DRIVER,
> BuildOptions.common.EDKII.SMM_CORE]
> + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +[BuildOptions.Common.EDK]
> +
> +#
> +# Define token for different Platform
> +#
> +!if $(ENBDT_PF_BUILD) == TRUE
> + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1
> +!else
> + DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0
> +!endif
> +
> +!if $(PERFORMANCE_ENABLE) == TRUE
> + RELEASE_*_*_DLINK_FLAGS = /DEBUG
> +!endif
> +
> +!if $(S3_ENABLE) == TRUE
> + DEFINE DSC_S3_BUILD_OPTIONS = /DEFI_S3_RESUME
> +!else
> + DEFINE DSC_S3_BUILD_OPTIONS =
> +!endif
> +
> +!if $(ENBDT_S3_SUPPORT) == TRUE
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT
> +!else
> + DEFINE ENBDT_S3_SUPPORT_OPTIONS =
> +!endif
> +
> +!if $(X64_CONFIG) == TRUE
> + DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1
> +!else
> + DEFINE X64_BUILD_ENABLE =
> +!endif
> +
> +
> + DEFINE EDK_GLUE_LIB_DEBUG =
> + DEFINE DEBUG_BUILD_OPTIONS = /D EFI_DEBUG /D DEBUG_MODE=1
> /GL- $(EDK_GLUE_LIB_DEBUG)
> /DEDKII_GLUE_DebugPrintErrorLevel=(EFI_D_ERROR)
> + DEFINE EDK_DSC_FEATURE_BUILD_OPTIONS = $(DSC_S3_BUILD_OPTIONS)
> $(DSC_ACPI_BUILD_OPTIONS) $(DSC_SEC_BUILD_OPTIONS)
> $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS)
> $(DSC_TPM_BUILD_OPTIONS) $(SOFTSDV_BUILD_OPTIONS)
> $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS)
> $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS)
> $(QT_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)
> /D$(PROJECT_SC_CHIPSET)
> +
> + DEFINE EDK_DSC_OTHER_BUILD_OPTIONS =
> $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SV_BUILD_OPTIONS)
> $(INTEL_FASTBOOT_BUILD_OPTION)
> + DEFINE EDK_DSC_GLOBAL_BUILD_OPTIONS = $(ENBDT_PF_ENABLE)
> $(EDK_DSC_FEATURE_BUILD_OPTIONS)
> $(EDK_DSC_OTHER_BUILD_OPTIONS) /D
> EFI_SPECIFICATION_VERSION=0x00020000 /D
> PI_SPECIFICATION_VERSION=0x00000009 /D
> TIANO_RELEASE_VERSION=0x00080006 /D
> SUPPORT_DEPRECATED_PCI_CFG_PPI /D CSM_SMMENTRY_PORT8DATA8 /D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) /D
> MAX_VARIABLE_SIZE=0x2000 /D EFI_FIRMWARE_VENDOR="L/"INTEL/"" /D
> EFI_BUILD_VERSION="L/"EDKII/"" /DEFI_PEI_REPORT_STATUS_CODE_ON
> $(ENBDT_S3_SUPPORT_OPTIONS)
> +
> + *_*_IA32_ASM_FLAGS = /DEFI32 /D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> /DNOCS_S3_SUPPORT
> + DEBUG_*_IA32_CC_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_CC_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_IA32_VFRPP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_VFRPP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_IA32_APP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_APP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_IA32_PP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_IA32_PP_FLAGS = /D EFI32
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + *_*_IA32_ASLPP_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_IA32_ASLCC_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_IA32_ASM16_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> +
> + *_*_X64_ASM_FLAGS = /DEFIX64 /D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> /DNOCS_S3_SUPPORT
> + DEBUG_*_X64_CC_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_CC_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_X64_VFRPP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_VFRPP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_X64_APP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_APP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + DEBUG_*_X64_PP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
> + RELEASE_*_X64_PP_FLAGS = /D EFIX64
> $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
> + *_*_X64_ASLPP_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_X64_ASLCC_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
> + *_*_X64_ASM16_FLAGS = /D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> + # *_*_*_BUILD_FLAGS = -s
> + *_*_*_VFR_FLAGS = -c
> + *_*_*_BUILD_FLAGS = -c
> +
> +[BuildOptions.Common.EDKII]
> + *_*_IA32_ASM_FLAGS = $(VP_BUILD_OPTIONS) /D
> EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
> /DNOCS_S3_SUPPORT
> +
> + *_*_IA32_CC_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_VFRPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_APP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_PP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_IA32_ASLPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +
> + *_*_X64_CC_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> $(SOURCE_LEVEL_DEBUG_BUILD_OPTIONS)
> + *_*_X64_VFRPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_X64_APP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_X64_PP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_X64_ASLPP_FLAGS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +
> +
> +[Components.X64]
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cBus.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cHost.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
> + }
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cPortA0Pio.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
> + }
> +
> +
> $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_
> ARCHITECTURE)/I2cMmioDeviceDxe.inf {
> + <PcdsPatchableInModule>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
> + }
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Boot.vfi
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Boot.vfi
> new file mode 100644
> index 0000000000..9c155e5328
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Boot.vfi
> @@ -0,0 +1,72 @@
> +//
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +//
>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +//
>
> +//
> +//
> +// Module Name:
> +//
> +// Boot.vfi
> +//
> +// Abstract:
> +//
> +// Driver Setup formset.
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +form formid = BOOT_CONFIGURATION_FORM_ID,
> +
> + title = STRING_TOKEN(STR_BOOT_CONFIGURATION_TITLE);
> +
> +
> + oneof varid = Setup.FastBoot,
> + prompt = STRING_TOKEN(STR_FAST_BOOT_PROMPT),
> + help = STRING_TOKEN(STR_FAST_BOOT_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags= DEFAULT |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.SecureBoot,
> + prompt = STRING_TOKEN(STR_SECURITY_BOOT_PROMPT),
> + help = STRING_TOKEN(STR_SECURITY_BOOT_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags= DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> RESET_REQUIRED;
> + endoneof;
> +
> +
> + oneof varid = Setup.QuietBoot,
> + prompt = STRING_TOKEN(STR_QUIETBOOT_PROMPT),
> + help = STRING_TOKEN(STR_QUIETBOOT_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> +
> +
> +
> + oneof varid = Setup.LogBootTime,
> + prompt = STRING_TOKEN(STR_LOG_BOOT_TIME_PROMPT),
> + help = STRING_TOKEN(STR_LOG_BOOT_TIME_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = 0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + suppressif ideqval Setup.LogBootTime == 0x00;
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_LOG_BOOT_TIME_RECORD),
> + text = STRING_TOKEN(STR_LOG_BOOT_TIME_VALUE),
> + flags = 0,
> + key = 0;
> + endif;
> +
> +endform;
> +
> +
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Configuration.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Configuration.h
> new file mode 100644
> index 0000000000..7d7920c244
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Configuration.h
> @@ -0,0 +1,56 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + Configuration.h
> +
> +Abstract:
> +
> + Driver configuration include file
> +
> +Revision History:
> + ------------------------------------------------------------------------------
> + Rev Date<MM/DD/YYYY> Name Description
> + ------------------------------------------------------------------------------
> +
> + ------------------------------------------------------------------------------
> +--*/
> +
> +#ifndef _CONFIGURATION_H
> +#define _CONFIGURATION_H
> +
> +//
> +// System Setup Page. Do not have to be sequential but have to be unique
> +//
> +#define ROOT_FORM_ID 1
> +#define ROOT_MAIN_FORM_ID 2
> +#define CPU_CONFIGURATION_FORM_ID 3
> +#define CPU_PWR_CONFIGURATION_FORM_ID 4
> +#define BOOT_CONFIGURATION_FORM_ID 5
> +#define IGD_FORM_ID 6
> +#define SECURITY_CONFIGURATION_FORM_ID 7
> +#define SOUTH_CLUSTER_FORM_ID 8
> +#define DPTF_FORM_ID 9
> +#define PLATFORM_INFORMATION_FORM_ID 10
> +#define DRIVE_CONFIGURATION_ID 11
> +#define SENSOR_CONFIGURATION_ID 12
> +#define LPSS_CONFIGURATION_ID 13
> +#define UNCORE_FORM_ID 14
> +#define TPM_FORM_ID 15
> +#define THERMAL_FORM_ID 16
> +#define PASSWORD_SETTING_ID 17
> +#define LAN_OPTIONS_FORM_ID 18
> +#define AZALIA_OPTIONS_FORM_ID 19
> +#define MISC_OPTIONS_FORM_ID 20
> +#define USB_OPTIONS_FORM_ID 21
> +#define PCIE_DEVICE_OPTIONS_FORM_ID 22
> +#define SYSTEM_COMPONENT_FORM_ID 23
> +#define DEBUG_CONFIGURATION_FORM_ID 24
> +#endif // #ifndef _CONFIGURATION_H
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/DebugConfig.vfi
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/DebugConfig.vfi
> new file mode 100644
> index 0000000000..eea41a5202
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/DebugConfig.vfi
> @@ -0,0 +1,118 @@
> +//
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +//
>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +//
>
> +//
> +//
> +//
> +// Module Name:
> +//
> +// DebugConfiguration.vfi
> +//
> +// Abstract:
> +//
> +// Debug Configuration formset.
> +//
> +
> +
> +// --*/
> +
> +form formid = DEBUG_CONFIGURATION_FORM_ID,
> + title = STRING_TOKEN(STR_DEBUG_CONFIGURATION_TITLE);
> +
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + subtitle text = STRING_TOKEN(STR_ACPIMEMDBG_STRING);
> +
> + //ACPI Memory Debug Switch
> + oneof varid = Setup.ACPIMemDbg,
> + prompt = STRING_TOKEN (STR_ACPIMEMDBG_SWTICH),
> + help = STRING_TOKEN (STR_ACPIMEMDBG_SWTICH_HELP),
> + option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = DEFAULT
> | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + oneof varid = Setup.ExISupport,
> + prompt = STRING_TOKEN(STR_EXISUPPORT_PROMPT),
> + help = STRING_TOKEN(STR_EXISUPPORT_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT |
> RESET_REQUIRED;
> + endoneof;
> + subtitle text = STRING_TOKEN(STR_WITT_CONFIGURATION_TITLE);
> +
> + oneof varid = Setup.WittEnable,
> + prompt = STRING_TOKEN(STR_WITT_PROMPT),
> + help = STRING_TOKEN(STR_WITT_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.UtsEnable,
> + prompt = STRING_TOKEN(STR_UTS_PROMPT),
> + help = STRING_TOKEN(STR_UTS_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + //
> + //Lakemore Settings
> + //
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + subtitle text = STRING_TOKEN(STR_LM_INFORMATION_TITLE);
> +
> + grayoutif ideqval Setup.PunitBIOSConfig == 0x1;
> + oneof varid = Setup.LmMemSize,
> + prompt = STRING_TOKEN (STR_LM_MEMORY_PROMPT),
> + help = STRING_TOKEN (STR_LM_MEMORY_HELP),
> + option text = STRING_TOKEN (STR_LM_MEMORY_16MB), value =
> 16384, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_LM_MEMORY_8MB), value = 8192,
> flags = RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_LM_MEMORY_1MB), value = 1024,
> flags = RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_LM_MEMORY_128KB), value = 128,
> flags = RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_LM_MEMORY_0MB), value = 0,
> flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + oneof varid = Setup.PunitBIOSConfig,
> + prompt = STRING_TOKEN (STR_PUINT_BIOS_CONFIG_DISPLAY),
> + help = STRING_TOKEN (STR_PUINT_BIOS_CONFIG_DISPLAY_HELP),
> + option text = STRING_TOKEN (STR_PUINT_BIOS_PDM), value = 3,
> flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_PUINT_BIOS_PERFORMANCE), value
> = 2, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_PUINT_BIOS_POWERSAVE), value =
> 1, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_PUINT_BIOS_RESERVED), value
> = 0, flags = RESET_REQUIRED;
> + endoneof;
> +
> + suppressif NOT ideqval Setup.PunitBIOSConfig == 0x3;
> + oneof varid = Setup.PDMConfig,
> + prompt = STRING_TOKEN (STR_PDM_OUTPUT_CONFIG_SWTICH),
> + help = STRING_TOKEN
> (STR_PDM_OUTPUT_CONFIG_SWTICH_HELP),
> + option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = DEFAULT
> | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_PDM_OUTPUT_MEM), value = 1,
> flags = RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_PDM_OUTPUT_IO), value = 2, flags
> = RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + oneof varid = Setup.ENDBG2,
> + prompt = STRING_TOKEN (STR_ENABLE_DBG2),
> + help = STRING_TOKEN (STR_ENABLE_DBG2_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> RESET_REQUIRED;
> + endoneof;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + oneof varid = Setup.DisableCodec262,
> + prompt = STRING_TOKEN(STR_CODEC262_DISABLED_PROMPT),
> + help = STRING_TOKEN(STR_CODEC262_DISABLED_HELP),
> + option text = STRING_TOKEN(STR_YES), value = 1, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_NO), value = 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> +endform;
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/FwVersionStrings.un
> i
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/FwVersionStrings.un
> i
> new file mode 100644
> index 0000000000..175ceb1a16
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/FwVersionStrings.un
> i
> @@ -0,0 +1,40 @@
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// InventoryStrings.uni
> +//
> +// Abstract:
> +//
> +// String definitions for Inventory file.
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +#langdef fr-FR "Francais"
> +
> +#string STR_SOC_STRING #language en-US "VLV SOC"
> +#string STR_SOC_VALUE #language en-US "N/A"
> +#string STR_MRC_VERSION_STRING #language en-US "MRC
> Version"
> +#string STR_MRC_VERSION_VALUE #language en-US "N/A"
> +#string STR_PUNIT_FW_STRING #language en-US "PUNIT FW
> Patch"
> +#string STR_PUNIT_FW_VALUE #language en-US "N/A"
> +#string STR_ULPMC_FW_STRING #language en-US "ULPMC
> FW"
> +#string STR_ULPMC_FW_VALUE #language en-US "N/A"
> +#string STR_KSC_FW_STRING #language en-US "KSC FW"
> +#string STR_KSC_FW_VALUE #language en-US "N/A"
> +#string STR_SEC_FW_STRING #language en-US "TXE FW"
> +#string STR_SEC_FW_VALUE #language en-US "N/A"
> +#string STR_GOP_STRING #language en-US "GOP"
> +#string STR_GOP_VALUE #language en-US "N/A"
> +#string STR_PMC_FW_STRING #language en-US "PMC FW
> Patch"
> +#string STR_PMC_FW_VALUE #language en-US "N/A"
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Main.vfi
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Main.vfi
> new file mode 100644
> index 0000000000..6093262e3f
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Main.vfi
> @@ -0,0 +1,331 @@
> +//
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +//
>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +//
>
> +//
> +//
> +//
> +// Module Name:
> +//
> +// Main.vfi
> +//
> +// Abstract:
> +//
> +// Driver Setup formset.
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +form formid = ROOT_MAIN_FORM_ID,
> +
> + title = STRING_TOKEN(STR_MAIN_TITLE);
> +
> + subtitle text = STRING_TOKEN(STR_BIOS_INFORMATION_TITLE);
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_IFWI_VERSION_STRING),
> + text = STRING_TOKEN(STR_IFWI_VERSION_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_BIOS_VERSION_STRING),
> + text = STRING_TOKEN(STR_BIOS_VERSION_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_BIOS_VENDOR_STRING),
> + text = STRING_TOKEN(STR_BIOS_VENDOR_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_CORE_VERSION_STRING),
> + text = STRING_TOKEN(STR_CORE_VERSION_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_BIOS_BUILD_TIME_STRING),
> + text = STRING_TOKEN(STR_BIOS_BUILD_TIME_VALUE),
> + flags = 0,
> + key = 0;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + subtitle text = STRING_TOKEN(STR_PROCESSOR_INFO_STRING);
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_VERSION_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_VERSION_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_SKU_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_SKU_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_SPEED_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_SPEED_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_ID_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_ID_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_MICROCODE_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_MICROCODE_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_CORE_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_CORE_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_EM64T_CAPABILITY_STRING),
> + text = STRING_TOKEN(STR_EM64T_CAPABILITY_VALUE),
> + flags = 0,
> + key = 0;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + goto PLATFORM_INFORMATION_FORM_ID,
> + prompt = STRING_TOKEN(STR_PLATFORM_INFORMATION_TITLE),
> + help = STRING_TOKEN(STR_PLATFORM_INFORMATION_HELP);
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + //
> + // Date and Time section
> + //
> + date year varid = Date.Year, // Note that it is a member of NULL, so the
> RTC will be the system resource to retrieve and save from
> + prompt = STRING_TOKEN(STR_DATE_PROMPT),
> + help = STRING_TOKEN(STR_DATE_YEAR_HELP),
> + minimum = 2003,
> + maximum = 2100,
> + step = 1,
> + default = 2003,
> +
> + month varid = Date.Month, // Note that it is a member of NULL, so the
> RTC will be the system resource to retrieve and save from
> + prompt = STRING_TOKEN(STR_DATE_PROMPT),
> + help = STRING_TOKEN(STR_DATE_MONTH_HELP),
> + minimum = 1,
> + maximum = 12,
> + step = 1,
> + default = 1,
> +
> + day varid = Date.Day, // Note that it is a member of NULL, so the RTC
> will be the system resource to retrieve and save from
> + prompt = STRING_TOKEN(STR_DATE_PROMPT),
> + help = STRING_TOKEN(STR_DATE_DAY_HELP),
> + minimum = 1,
> + maximum = 31,
> + step = 0x1,
> + default = 1,
> +
> + // If the day is 31 AND months is any of the following 2, 4, 6, 9, 11
> + inconsistentif prompt = STRING_TOKEN(STR_ERROR_POPUP),
> + ideqval Date.Day == 31
> + AND
> + ideqvallist Date.Month == 2 4 6 9 11
> + endif
> +
> + // If the day is 30 AND month is 2
> + inconsistentif prompt = STRING_TOKEN(STR_ERROR_POPUP),
> + ideqval Date.Day == 30
> + AND
> + ideqval Date.Month == 2
> + endif
> +
> + // If the day is 29 AND month is 2 AND it year is NOT a leapyear
> + inconsistentif prompt = STRING_TOKEN(STR_ERROR_POPUP),
> + ideqval Date.Day == 0x29
> + AND
> + ideqval Date.Month == 2
> + AND
> + NOT
> + ideqvallist Date.Year == 2004 2008 2012 2016 2020 2024 2028 2032 2036
> 2040 2044 2048 2052 2056 2060 2064 2068 2072 2076 2080 2084 2088 2092 2096
> + endif
> +
> + enddate;
> +
> + time hour varid = Time.Hours, // Note that it is a member of NULL, so
> the RTC will be the system resource to retrieve and save from
> + prompt = STRING_TOKEN(STR_TIME_PROMPT),
> + help = STRING_TOKEN(STR_TIME_HOUR_HELP),
> + minimum = 0,
> + maximum = 23,
> + step = 1,
> + default = 0,
> +
> + minute varid = Time.Minutes, // Note that it is a member of NULL, so
> the RTC will be the system resource to retrieve and save from
> + prompt = STRING_TOKEN(STR_TIME_PROMPT),
> + help = STRING_TOKEN(STR_TIME_MINUTE_HELP),
> + minimum = 0,
> + maximum = 59,
> + step = 1,
> + default = 0,
> +
> + second varid = Time.Seconds, // Note that it is a member of NULL, so
> the RTC will be the system resource to retrieve and save from
> + prompt = STRING_TOKEN(STR_TIME_PROMPT),
> + help = STRING_TOKEN(STR_TIME_SECOND_HELP),
> + minimum = 0,
> + maximum = 59,
> + step = 1,
> + default = 0,
> + endtime;
> +
> +endform;
> +
> +form formid = PLATFORM_INFORMATION_FORM_ID,
> +
> + title = STRING_TOKEN(STR_PLATFORM_INFORMATION_TITLE);
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + subtitle text = STRING_TOKEN(STR_PLATFORM_FIRMWARE_STRING);
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_SOC_STRING),
> + text = STRING_TOKEN(STR_SOC_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_MRC_VERSION_STRING),
> + text = STRING_TOKEN(STR_MRC_VERSION_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_PUNIT_FW_STRING),
> + text = STRING_TOKEN(STR_PUNIT_FW_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_PMC_FW_STRING),
> + text = STRING_TOKEN(STR_PMC_FW_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_KSC_FW_STRING),
> + text = STRING_TOKEN(STR_KSC_FW_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_SEC_VERSION_STRING),
> + text = STRING_TOKEN(STR_SEC_VERSION_VALUE),
> + flags = 0,
> + key = 0;
> +
> + suppressif ideqval Setup.GOPEnable == 0;
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_GOP_STRING),
> + text = STRING_TOKEN(STR_GOP_VALUE),
> + flags = 0,
> + key = 0;
> + endif;
> +
> + suppressif ideqval Setup.GOPEnable == 1;
> + text
> + help = STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_HELP),
> + text = STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_NAME),
> + text = STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_VALUE),
> + flags = 0,
> + key = 0;
> + endif;
> +
> + text
> + help = STRING_TOKEN(STR_CPU_FLAVOR_HELP),
> + text = STRING_TOKEN(STR_CPU_FLAVOR_NAME),
> + text = STRING_TOKEN(STR_CPU_FLAVOR_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_BOARD_ID_HELP),
> + text = STRING_TOKEN(STR_BOARD_ID_NAME),
> + text = STRING_TOKEN(STR_BOARD_ID_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_FAB_ID_HELP),
> + text = STRING_TOKEN(STR_FAB_ID_STRING),
> + text = STRING_TOKEN(STR_FAB_ID_VALUE),
> + flags = 0,
> + key = 0;
> +
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + subtitle text = STRING_TOKEN(STR_MEMORY_INFORMATION_STRING);
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_TOTAL_MEMORY_SIZE_PROMPT),
> + text = STRING_TOKEN(STR_TOTAL_MEMORY_SIZE_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_SYSTEM_MEMORY_SPEED_STRING),
> + text = STRING_TOKEN(STR_SYSTEM_MEMORY_SPEED_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_L1_DATA_CACHE_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_L1_DATA_CACHE_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_L1_INSTR_CACHE_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_L1_INSTR_CACHE_VALUE),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_L2_CACHE_STRING),
> + text = STRING_TOKEN(STR_PROCESSOR_L2_CACHE_VALUE),
> + flags = 0,
> + key = 0;
> +
> +endform;
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.c
> new file mode 100644
> index 0000000000..0bfa3e7cf4
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.c
> @@ -0,0 +1,929 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +**/
> +
> +#include "PlatformSetupDxe.h"
> +#include "Guid/SetupVariable.h"
> +#include <Protocol/FormBrowserEx2.h>
> +
> +
> +#define EFI_CALLBACK_INFO_SIGNATURE SIGNATURE_32 ('C', 'l', 'b', 'k')
> +#define EFI_CALLBACK_INFO_FROM_THIS(a) CR (a, EFI_CALLBACK_INFO,
> ConfigAccess, EFI_CALLBACK_INFO_SIGNATURE)
> +
> +typedef struct {
> + UINTN Signature;
> + EFI_HANDLE DriverHandle;
> + EFI_HII_HANDLE RegisteredHandle;
> + SYSTEM_CONFIGURATION FakeNvData;
> + SYSTEM_CONFIGURATION BackupNvData;
> + EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
> + EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
> +} EFI_CALLBACK_INFO;
> +
> +#pragma pack(1)
> +
> +//
> +// HII specific Vendor Device Path definition.
> +//
> +typedef struct {
> + VENDOR_DEVICE_PATH VendorDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} HII_VENDOR_DEVICE_PATH;
> +
> +#pragma pack()
> +
> +//
> +// uni string and Vfr Binary data.
> +//
> +extern UINT8 VfrBin[];
> +extern UINT8 PlatformSetupDxeStrings[];
> +
> +EFI_HANDLE mImageHandle;
> +
> +//
> +// module global data
> +//
> +#define EFI_NORMAL_SETUP_GUID \
> + { 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd,
> 0xa9 }
> +
> +EFI_GUID mNormalSetupGuid = EFI_NORMAL_SETUP_GUID;
> +
> +EFI_GUID mSystemConfigGuid =
> SYSTEM_CONFIGURATION_GUID;
> +CHAR16 mVariableName[] = L"Setup";
> +CHAR16 mSetupName[] = L"Setup";
> +EFI_CALLBACK_INFO *mCallbackInfo;
> +BOOLEAN GlobalReset=FALSE;
> +
> +HII_VENDOR_DEVICE_PATH mHiiVendorDevicePath = {
> + {
> + {
> + HARDWARE_DEVICE_PATH,
> + HW_VENDOR_DP,
> + {
> + (UINT8) (sizeof (VENDOR_DEVICE_PATH)),
> + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)
> + }
> + },
> + EFI_CALLER_ID_GUID
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + (UINT8) (END_DEVICE_PATH_LENGTH),
> + (UINT8) ((END_DEVICE_PATH_LENGTH) >> 8)
> + }
> + }
> +};
> +
> +/**
> + This function allows a caller to extract the current configuration for one
> + or more named elements from the target driver.
> +
> + @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
> + @param Request A null-terminated Unicode string in <ConfigRequest>
> format.
> + @param Progress On return, points to a character in the Request string.
> + Points to the string's null terminator if request was successful.
> + Points to the most recent '&' before the first failing name/value
> + pair (or the beginning of the string if the failure is in the
> + first name/value pair) if the request was not successful.
> + @param Results A null-terminated Unicode string in <ConfigAltResp>
> format which
> + has all values filled in for the names in the Request string.
> + String to be allocated by the called function.
> +
> + @retval EFI_SUCCESS The Results is filled with the requested values.
> + @retval EFI_OUT_OF_RESOURCES Not enough memory to store the
> results.
> + @retval EFI_INVALID_PARAMETER Request is NULL, illegal syntax, or
> unknown name.
> + @retval EFI_NOT_FOUND Routing data doesn't match any storage in
> this driver.
> +
> +**/
> +
> +VOID
> +CheckSystemConfigLoad(SYSTEM_CONFIGURATION *SystemConfigPtr);
> +
> +VOID
> +CheckSystemConfigSave(SYSTEM_CONFIGURATION *SystemConfigPtr);
> +
> +VOID
> +ConfirmSecureBootTest();
> +
> +VOID
> +LoadLpssDefaultValues (
> + IN EFI_CALLBACK_INFO *Private
> + )
> +{
> + //
> + // Load LPSS and SCC default configurations for Android
> + //
> + Private->FakeNvData.LpsseMMCEnabled = FALSE;
> + Private->FakeNvData.LpssSdioEnabled = TRUE;
> + Private->FakeNvData.LpssSdcardEnabled = TRUE;
> + Private->FakeNvData.LpssSdCardSDR25Enabled = FALSE;
> + Private->FakeNvData.LpssSdCardDDR50Enabled = TRUE;
> + Private->FakeNvData.LpssMipiHsi = FALSE;
> + Private->FakeNvData.LpsseMMC45Enabled = TRUE;
> + Private->FakeNvData.LpsseMMC45DDR50Enabled = TRUE;
> + Private->FakeNvData.LpsseMMC45HS200Enabled = FALSE;
> + Private->FakeNvData.LpsseMMC45RetuneTimerValue = 8;
> + Private->FakeNvData.eMMCBootMode = 1; // Auto Detect
> +
> + Private->FakeNvData.GOPEnable = TRUE;
> + Private->FakeNvData.SecureBoot = TRUE;
> + Private->FakeNvData.UsbAutoMode = TRUE;
> + Private->FakeNvData.UsbXhciSupport = TRUE;
> + Private->FakeNvData.PchUsb30Mode = TRUE;
> + Private->FakeNvData.LegacyUSBBooting = FALSE;
> + Private->FakeNvData.PchUsb20 = FALSE;
> +}
> +
> +
> +EFI_STATUS
> +EFIAPI
> +SystemConfigExtractConfig (
> + IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
> + IN CONST EFI_STRING Request,
> + OUT EFI_STRING *Progress,
> + OUT EFI_STRING *Results
> + )
> +{
> + EFI_STATUS Status;
> + EFI_CALLBACK_INFO *Private;
> + EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
> + EFI_STRING ConfigRequestHdr;
> + EFI_STRING ConfigRequest;
> + BOOLEAN AllocatedRequest;
> + UINTN Size;
> + UINTN BufferSize;
> + VOID *SystemConfigPtr;
> +
> +
> + if (Progress == NULL || Results == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + *Progress = Request;
> + if ((Request != NULL) && !HiiIsConfigHdrMatch (Request,
> &mSystemConfigGuid, mVariableName)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + ConfigRequestHdr = NULL;
> + ConfigRequest = NULL;
> + Size = 0;
> + AllocatedRequest = FALSE;
> +
> + Private = EFI_CALLBACK_INFO_FROM_THIS (This);
> +
> + SetupInfo();
> +
> + HiiConfigRouting = Private->HiiConfigRouting;
> + ConfigRequest = Request;
> + if ((Request == NULL) || (StrStr (Request, L"OFFSET") == NULL)) {
> + //
> + // Request has no request element, construct full request string.
> + // Allocate and fill a buffer large enough to hold the <ConfigHdr>
> template
> + // followed by "&OFFSET=0&WIDTH=WWWWWWWWWWWWWWWW"
> followed by a Null-terminator
> + //
> + ConfigRequestHdr = HiiConstructConfigHdr (&mSystemConfigGuid,
> mVariableName, Private->DriverHandle);
> + Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
> + ConfigRequest = AllocateZeroPool (Size);
> + ASSERT (ConfigRequest != NULL);
> + AllocatedRequest = TRUE;
> + BufferSize = sizeof (SYSTEM_CONFIGURATION);
> + UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX",
> ConfigRequestHdr, (UINT64)BufferSize);
> + FreePool (ConfigRequestHdr);
> + }
> + SystemConfigPtr = GetVariable(mSetupName, &mNormalSetupGuid);
> +
> +
> + if (SystemConfigPtr == NULL) {
> + ZeroMem(&Private->FakeNvData, sizeof(SYSTEM_CONFIGURATION));
> + ZeroMem(&Private->BackupNvData, sizeof(SYSTEM_CONFIGURATION));
> + } else {
> + CheckSystemConfigLoad(SystemConfigPtr);
> + CopyMem(&Private->FakeNvData, SystemConfigPtr,
> sizeof(SYSTEM_CONFIGURATION));
> + CopyMem(&Private->BackupNvData, SystemConfigPtr,
> sizeof(SYSTEM_CONFIGURATION));
> + FreePool(SystemConfigPtr);
> + }
> +
> + //
> + // Convert buffer data to <ConfigResp> by helper function BlockToConfig()
> + //
> + Status = HiiConfigRouting->BlockToConfig (
> + HiiConfigRouting,
> + ConfigRequest,
> + (UINT8 *) &Private->FakeNvData,
> + sizeof (SYSTEM_CONFIGURATION),
> + Results,
> + Progress
> + );
> +
> + //
> + // Free the allocated config request string.
> + //
> + if (AllocatedRequest) {
> + FreePool (ConfigRequest);
> + ConfigRequest = NULL;
> + }
> +
> + //
> + // Set Progress string to the original request string.
> + //
> + if (Request == NULL) {
> + *Progress = NULL;
> + } else if (StrStr (Request, L"OFFSET") == NULL) {
> + *Progress = Request + StrLen (Request);
> + }
> +
> + return Status;
> +}
> +
> +/**
> + This function processes the results of changes in configuration.
> +
> + @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
> + @param Configuration A null-terminated Unicode string in
> <ConfigRequest> format.
> + @param Progress A pointer to a string filled in with the offset of the
> most
> + recent '&' before the first failing name/value pair (or the
> + beginning of the string if the failure is in the first
> + name/value pair) or the terminating NULL if all was successful.
> +
> + @retval EFI_SUCCESS The Results is processed successfully.
> + @retval EFI_INVALID_PARAMETER Configuration is NULL.
> + @retval EFI_NOT_FOUND Routing data doesn't match any storage in
> this driver.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SystemConfigRouteConfig (
> + IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
> + IN CONST EFI_STRING Configuration,
> + OUT EFI_STRING *Progress
> + )
> +{
> + EFI_CALLBACK_INFO *Private;
> + SYSTEM_CONFIGURATION *FakeNvData;
> +
> + if (Configuration == NULL || Progress == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> + *Progress = Configuration;
> +
> + if (!HiiIsConfigHdrMatch (Configuration, &mSystemConfigGuid,
> mVariableName)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + *Progress = Configuration + StrLen (Configuration);
> + Private = EFI_CALLBACK_INFO_FROM_THIS (This);
> + FakeNvData = &Private->FakeNvData;
> + if (!HiiGetBrowserData (&mSystemConfigGuid, mVariableName, sizeof
> (SYSTEM_CONFIGURATION), (UINT8 *) FakeNvData)) {
> + //
> + // FakeNvData can't be got from SetupBrowser, which doesn't need to be
> set.
> + //
> + return EFI_SUCCESS;
> + }
> +
> + if (Private->FakeNvData.ReservedO != Private->BackupNvData.ReservedO)
> {
> + Private->BackupNvData.ReservedO = Private->FakeNvData.ReservedO;
> + LoadLpssDefaultValues (Private);
> +
> + //
> + // Pass changed uncommitted data back to Form Browser
> + //
> + HiiSetBrowserData (&mSystemConfigGuid, mVariableName, sizeof
> (SYSTEM_CONFIGURATION), (UINT8 *) FakeNvData, NULL);
> + }
> +
> + gRT->SetVariable(
> + mSetupName,
> + &mNormalSetupGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + sizeof(SYSTEM_CONFIGURATION),
> + &Private->FakeNvData
> + );
> +
> + CheckSystemConfigSave(&Private->FakeNvData);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This is the function that is called to provide results data to the driver. This
> data
> + consists of a unique key which is used to identify what data is either being
> passed back
> + or being asked for.
> +
> + @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
> + @param Action A null-terminated Unicode string in <ConfigRequest>
> format.
> + @param KeyValue A unique Goto OpCode callback value which record
> user's selection.
> + 0x100 <= KeyValue <0x500 : user select a controller item in the
> first page;
> + KeyValue == 0x1234 : user select 'Refresh' in first page, or
> user select 'Go to Previous Menu' in second page
> + KeyValue == 0x1235 : user select 'Pci device filter' in first
> page
> + KeyValue == 0x1500 : user select 'order ... priority' item in
> second page
> + KeyValue == 0x1800 : user select 'commint changes' in third
> page
> + KeyValue == 0x2000 : user select 'Go to Previous Menu' in
> third page
> + @param Type The type of value for the question.
> + @param Value A pointer to the data being sent to the original
> exporting driver.
> + @param ActionRequest On return, points to the action requested by the
> callback function.
> +
> + @retval EFI_SUCCESS Always returned.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SystemConfigCallback (
> + IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
> + IN EFI_BROWSER_ACTION Action,
> + IN EFI_QUESTION_ID KeyValue,
> + IN UINT8 Type,
> + IN EFI_IFR_TYPE_VALUE *Value,
> + OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
> + )
> +{
> + EFI_CALLBACK_INFO *Private;
> + SYSTEM_CONFIGURATION *FakeNvData;
> + SYSTEM_CONFIGURATION *SetupData;
> + UINTN SizeOfNvStore;
> + EFI_INPUT_KEY Key;
> + CHAR16 *StringBuffer1;
> + CHAR16 *StringBuffer2;
> + CHAR16 *StringBuffer3;
> + EFI_STATUS Status;
> + UINTN DataSize;
> + UINT8 OsSelection;
> + EDKII_FORM_BROWSER_EXTENSION2_PROTOCOL *FormBrowserEx2;
> +
> + StringBuffer1 = AllocateZeroPool (200 * sizeof (CHAR16));
> + ASSERT (StringBuffer1 != NULL);
> + StringBuffer2 = AllocateZeroPool (200 * sizeof (CHAR16));
> + ASSERT (StringBuffer2 != NULL);
> + StringBuffer3 = AllocateZeroPool (200 * sizeof (CHAR16));
> + ASSERT (StringBuffer3 != NULL);
> +
> + switch (Action) {
> + case EFI_BROWSER_ACTION_CHANGING:
> + {
> + if (KeyValue == 0x1235) {
> + StrCpy (StringBuffer1, L"Will you disable PTT ? ");
> + StrCpy (StringBuffer2, L"Enter (YES) / Esc (NO)");
> +
> + //
> + // Popup a menu to notice user
> + //
> + do {
> + CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key,
> StringBuffer1, StringBuffer2, NULL);
> + } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar !=
> CHAR_CARRIAGE_RETURN));
> +
> + //
> + // If the user hits the YES Response key,
> + //
> + if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {
> +
> + }
> + } else if (KeyValue == 0x1236) {
> + StrCpy (StringBuffer1, L"Will you revoke trust ? ");
> + StrCpy (StringBuffer2, L"Enter (YES) / Esc (NO)");
> +
> + //
> + // Popup a menu to notice user
> + //
> + do {
> + CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key,
> StringBuffer1, StringBuffer2, NULL);
> + } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar !=
> CHAR_CARRIAGE_RETURN));
> +
> + //
> + // If the user hits the YES Response key,
> + //
> + if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {
> +
> + }
> + } else if (KeyValue == 0x1239) {
> + if (Value->u8 == 0x00) {
> + StrCpy (StringBuffer1, L"WARNING: SOC may be damaged due to high
> temperature");
> + StrCpy (StringBuffer2, L"when DPTF is disabled and IGD turbo is
> enabled.");
> + StrCpy (StringBuffer3, L"Press Enter/ESC to continue...");
> +
> + //
> + // Popup a menu to notice user
> + //
> + do {
> + CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key,
> StringBuffer1, StringBuffer2, StringBuffer3, NULL);
> + } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar !=
> CHAR_CARRIAGE_RETURN));
> + }
> + } else if (KeyValue == 0x1240) { // secure erase feature of eMMC
> + //
> + // Popup a menu to notice user
> + //
> + StrCpy (StringBuffer1, L"WARNING: All your data on the eMMC will be
> lost");
> + StrCpy (StringBuffer2, L"Do you really want to enable secure erase on
> eMMC?");
> + StrCpy (StringBuffer3, L" Enter (YES) / Esc (NO) ");
> +
> + do {
> + CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key,
> StringBuffer1, StringBuffer2, StringBuffer3,NULL);
> + } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar !=
> CHAR_CARRIAGE_RETURN));
> +
> + //
> + // If the user hits the ESC Response key,
> + //
> + if (Key.ScanCode == SCAN_ESC) {
> + Private = EFI_CALLBACK_INFO_FROM_THIS (This);
> + FakeNvData = &Private->FakeNvData;
> +
> + Status = HiiGetBrowserData (
> + &mSystemConfigGuid,
> + mVariableName,
> + sizeof (SYSTEM_CONFIGURATION),
> + (UINT8 *) FakeNvData
> + );
> + if (!EFI_ERROR (Status)) {
> + FakeNvData->SecureErase = 0;
> + HiiSetBrowserData (
> + &mSystemConfigGuid,
> + mVariableName,
> + sizeof (SYSTEM_CONFIGURATION),
> + (UINT8 *) FakeNvData,
> + NULL
> + );
> + }
> + break;
> + }
> +
> + //
> + // If the user hits the YES Response key
> + //
> + if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {
> + //
> + // Save change
> + //
> + Private = EFI_CALLBACK_INFO_FROM_THIS (This);
> + FakeNvData = &Private->FakeNvData;
> +
> + Status = HiiGetBrowserData (
> + &mSystemConfigGuid,
> + mVariableName,
> + sizeof (SYSTEM_CONFIGURATION),
> + (UINT8 *) FakeNvData
> + );
> + if (!EFI_ERROR (Status)) {
> + Status = gRT->SetVariable (
> + L"Setup",
> + &mNormalSetupGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + sizeof(SYSTEM_CONFIGURATION),
> + &Private->FakeNvData
> + );
> + }
> +
> + //
> + // Reset system
> + //
> + gRT->ResetSystem(
> + EfiResetCold,
> + EFI_SUCCESS,
> + 0,
> + NULL
> + );
> +
> + }
> +
> +
> + }
> + else if (KeyValue == 0xF001) {
> + //
> + // Popup a menu to notice user
> + //
> + StrCpy (StringBuffer1, L"Do you want to Commit Changes and Exit?");
> + StrCpy (StringBuffer2, L" Enter (YES) / Esc (NO) ");
> +
> + do {
> + CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key,
> StringBuffer1, StringBuffer2, NULL);
> + } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar !=
> CHAR_CARRIAGE_RETURN));
> +
> + //
> + // If the user hits the YES Response key
> + //
> + if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {
> + //
> + // Save change
> + //
> + Private = EFI_CALLBACK_INFO_FROM_THIS (This);
> + FakeNvData = &Private->FakeNvData;
> +
> + Status = HiiGetBrowserData (
> + &mSystemConfigGuid,
> + mVariableName,
> + sizeof (SYSTEM_CONFIGURATION),
> + (UINT8 *) FakeNvData
> + );
> + if (!EFI_ERROR (Status)) {
> + Status = gRT->SetVariable (
> + L"Setup",
> + &mNormalSetupGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + sizeof(SYSTEM_CONFIGURATION),
> + &Private->FakeNvData
> + );
> + }
> +
> + //
> + // Update Secure Boot configuration changes
> + //
> + CheckSystemConfigSave(FakeNvData);
> +
> + //
> + // Reset system
> + //
> + if (GlobalReset == TRUE) {
> + //
> + // Issue full reset
> + //
> + IoWrite8 (
> + (UINTN) 0XCF9,
> + (UINT8) 0x02
> + );
> +
> + IoWrite8 (
> + (UINTN) 0xCF9,
> + (UINT8) 0x0E
> + );
> + } else {
> + gRT->ResetSystem(
> + EfiResetCold,
> + EFI_SUCCESS,
> + 0,
> + NULL
> + );
> + }
> + }
> + } else if (KeyValue == 0xF002) {
> + //
> + // Popup a menu to notice user
> + //
> + StrCpy (StringBuffer1, L"Do you want to Discard Changes and Exit?");
> + StrCpy (StringBuffer2, L" Enter (YES) / Esc (NO) ");
> +
> + do {
> + CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key,
> StringBuffer1, StringBuffer2, NULL);
> + } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar !=
> CHAR_CARRIAGE_RETURN));
> +
> + //
> + // If the user hits the YES Response key
> + //
> + if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {
> + //
> + // Reset system
> + //
> + gRT->ResetSystem(EfiResetCold, EFI_SUCCESS, 0, NULL);
> + }
> + } else if (KeyValue == 0xF003) {
> + //
> + // Popup a menu to notice user
> + //
> + StrCpy (StringBuffer1, L"Do you want to load setup defaults and Exit?");
> + StrCpy (StringBuffer2, L" Enter (YES) / Esc (NO) ");
> +
> + do {
> + CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key,
> StringBuffer1, StringBuffer2, NULL);
> + } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar !=
> CHAR_CARRIAGE_RETURN));
> +
> + //
> + // If the user hits the YES Response key
> + //
> + if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {
> +
> + Status = gBS->LocateProtocol (&gEdkiiFormBrowserEx2ProtocolGuid,
> NULL, (VOID **) &FormBrowserEx2);
> + FormBrowserEx2->ExecuteAction(BROWSER_ACTION_DEFAULT,
> EFI_HII_DEFAULT_CLASS_STANDARD);
> +
> + FakeNvData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
> +
> + if (FakeNvData == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + Status = HiiGetBrowserData (
> + &mSystemConfigGuid,
> + mVariableName,
> + sizeof (SYSTEM_CONFIGURATION),
> + (UINT8 *) FakeNvData
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + Status = gRT->SetVariable (
> + L"Setup",
> + &mNormalSetupGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + sizeof(SYSTEM_CONFIGURATION),
> + FakeNvData
> + );
> + }
> +
> + FreePool (FakeNvData);
> +
> + DataSize = sizeof(OsSelection);
> + Status = gRT->GetVariable(
> + L"OsSelection",
> + &gOsSelectionVariableGuid,
> + NULL,
> + &DataSize,
> + &OsSelection
> + );
> +
> + if (EFI_ERROR(Status) || (OsSelection != FakeNvData->ReservedO)) {
> + OsSelection = FakeNvData->ReservedO;
> + Status = gRT->SetVariable (
> + L"OsSelection",
> + &gOsSelectionVariableGuid,
> + EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + sizeof(OsSelection),
> + &OsSelection
> + );
> + }
> +
> + //
> + // Reset system
> + //
> + gRT->ResetSystem(
> + EfiResetCold,
> + EFI_SUCCESS,
> + 0,
> + NULL
> + );
> + }
> + } else if ((KeyValue == 0x123A) || (KeyValue == 0x123B) || (KeyValue ==
> 0x123C)) {
> + StrCpy (StringBuffer1, L"WARNING: Enable or disable USB Controllers
> will ");
> + StrCpy (StringBuffer2, L"make global reset to restart system.");
> + StrCpy (StringBuffer3, L"Press Enter/ESC to continue...");
> + //
> + // Popup a menu to notice user
> + //
> + do {
> + CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key,
> StringBuffer1, StringBuffer2, StringBuffer3, NULL);
> + } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar !=
> CHAR_CARRIAGE_RETURN));
> +
> + FakeNvData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
> + Status = HiiGetBrowserData (
> + &mSystemConfigGuid,
> + mVariableName,
> + sizeof (SYSTEM_CONFIGURATION),
> + (UINT8 *) FakeNvData
> + );
> + //
> + // Get variable data
> + //
> + SizeOfNvStore = sizeof(SYSTEM_CONFIGURATION);
> + SetupData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
> + Status = gRT->GetVariable(
> + L"Setup",
> + &mNormalSetupGuid,
> + NULL,
> + &SizeOfNvStore,
> + SetupData
> + );
> + if ((SetupData->UsbAutoMode != FakeNvData->UsbAutoMode) ||
> + (SetupData->UsbXhciSupport != FakeNvData->UsbXhciSupport) ||
> + (SetupData->PchUsb20 != FakeNvData->PchUsb20)) {
> + GlobalReset = TRUE;
> + } else {
> + GlobalReset = FALSE;
> + }
> +
> + }
> + }
> + break;
> +
> + default:
> + break;
> + }
> +
> + FreePool (StringBuffer1);
> + FreePool (StringBuffer2);
> + FreePool (StringBuffer3);
> +
> + //
> + // Workaround for Load Default for "DPTF Enable"
> + //
> + if (Action == EFI_BROWSER_ACTION_DEFAULT_STANDARD) {
> + if (KeyValue == 0x1239) {
> + return EFI_NOT_FOUND;
> + }
> + }
> +
> + if (Action == EFI_BROWSER_ACTION_FORM_CLOSE) {
> + //
> + // Do nothing for UEFI OPEN/CLOSE Action
> + //
> + return EFI_SUCCESS;
> + }
> +
> + Private = EFI_CALLBACK_INFO_FROM_THIS (This);
> + FakeNvData = &Private->FakeNvData;
> + if (!HiiGetBrowserData (&mSystemConfigGuid, mVariableName, sizeof
> (SYSTEM_CONFIGURATION), (UINT8 *) FakeNvData)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + if ((Action == EFI_BROWSER_ACTION_FORM_OPEN) && (Private-
> >FakeNvData.ReservedO != Private->BackupNvData.ReservedO)) {
> + Private->BackupNvData.ReservedO = Private->FakeNvData.ReservedO;
> + LoadLpssDefaultValues (Private);
> + }
> +
> + //
> + // When user selected the secure erase, set it to disable
> + //
> + if((KeyValue == 0x1240) && (Action == EFI_BROWSER_ACTION_CHANGED))
> {
> + FakeNvData->SecureErase = 0;
> + }
> +
> + if ((Action == EFI_BROWSER_ACTION_FORM_OPEN) || (Action ==
> EFI_BROWSER_ACTION_CHANGED)) {
> + //
> + // If function 0 is disabled, function 1 ~ 7 also required to be disabled.
> + //
> + if (Private->FakeNvData.LpssDma0Enabled == 0) {
> + Private->FakeNvData.LpssHsuart0Enabled = 0;
> + Private->FakeNvData.LpssHsuart1Enabled = 0;
> + Private->FakeNvData.LpssPwm0Enabled = 0;
> + Private->FakeNvData.LpssPwm1Enabled = 0;
> + Private->FakeNvData.LpssSpiEnabled = 0;
> + }
> +
> +
> + //
> + // If function 0 is disabled, function 1 ~ 7 also required to be disabled.
> + //
> + if (Private->FakeNvData.LpssDma1Enabled == 0) {
> + Private->FakeNvData.LpssI2C0Enabled = 0;
> + Private->FakeNvData.LpssI2C1Enabled = 0;
> + Private->FakeNvData.LpssI2C2Enabled = 0;
> + Private->FakeNvData.LpssI2C3Enabled = 0;
> + Private->FakeNvData.LpssI2C4Enabled = 0;
> + Private->FakeNvData.LpssI2C5Enabled = 0;
> + Private->FakeNvData.LpssI2C6Enabled = 0;
> + }
> + }
> +
> +
> + //
> + // Pass changed uncommitted data back to Form Browser
> + //
> + HiiSetBrowserData (&mSystemConfigGuid, mVariableName, sizeof
> (SYSTEM_CONFIGURATION), (UINT8 *) FakeNvData, NULL);
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + The driver Entry Point. The function will export a disk device class formset
> and
> + its callback function to hii database.
> +
> + @param ImageHandle The firmware allocated handle for the EFI image.
> + @param SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The entry point is executed successfully.
> + @retval other Some error occurs when executing this entry point.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PlatformSetupDxeInit (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_FORM_BROWSER2_PROTOCOL *FormBrowser2;
> +
> + mImageHandle = ImageHandle;
> +
> + //
> + // There should only be one Form Configuration protocol
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiFormBrowser2ProtocolGuid,
> + NULL,
> + (VOID **) &FormBrowser2
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + mCallbackInfo = AllocateZeroPool (sizeof (EFI_CALLBACK_INFO));
> + if (mCallbackInfo == NULL) {
> + return EFI_BAD_BUFFER_SIZE;
> + }
> +
> + mCallbackInfo->Signature = EFI_CALLBACK_INFO_SIGNATURE;
> + mCallbackInfo->ConfigAccess.ExtractConfig = SystemConfigExtractConfig;
> + mCallbackInfo->ConfigAccess.RouteConfig = SystemConfigRouteConfig;
> + mCallbackInfo->ConfigAccess.Callback = SystemConfigCallback;
> +
> + //
> + // Install Device Path Protocol and Config Access protocol to driver handle
> + // Install Platform Driver Override Protocol to driver handle
> + //
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &mCallbackInfo->DriverHandle,
> + &gEfiDevicePathProtocolGuid,
> + &mHiiVendorDevicePath,
> + &gEfiHiiConfigAccessProtocolGuid,
> + &mCallbackInfo->ConfigAccess,
> + NULL
> + );
> + if (EFI_ERROR (Status)) {
> + goto Finish;
> + }
> +
> + //
> + // Publish our HII data
> + //
> + mCallbackInfo->RegisteredHandle = HiiAddPackages (
> + &mSystemConfigGuid,
> + mCallbackInfo->DriverHandle,
> + VfrBin,
> + PlatformSetupDxeStrings,
> + NULL
> + );
> + if (mCallbackInfo->RegisteredHandle == NULL) {
> + Status = EFI_OUT_OF_RESOURCES;
> + goto Finish;
> + }
> +
> + mHiiHandle = mCallbackInfo->RegisteredHandle;
> +
> + //
> + // Locate ConfigRouting protocol
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiHiiConfigRoutingProtocolGuid,
> + NULL,
> + (VOID **) &mCallbackInfo->HiiConfigRouting
> + );
> + if (EFI_ERROR (Status)) {
> + goto Finish;
> + }
> +
> + //
> + // Clear all the globle variable
> + //
> + return EFI_SUCCESS;
> +
> +Finish:
> + if (mCallbackInfo->DriverHandle != NULL) {
> + gBS->UninstallMultipleProtocolInterfaces (
> + mCallbackInfo->DriverHandle,
> + &gEfiDevicePathProtocolGuid,
> + &mHiiVendorDevicePath,
> + &gEfiHiiConfigAccessProtocolGuid,
> + &mCallbackInfo->ConfigAccess,
> + NULL
> + );
> + }
> +
> + if (mCallbackInfo->RegisteredHandle != NULL) {
> + HiiRemovePackages (mCallbackInfo->RegisteredHandle);
> + }
> +
> + if (mCallbackInfo != NULL) {
> + FreePool (mCallbackInfo);
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Unload its installed protocol.
> +
> + @param[in] ImageHandle Handle that identifies the image to be
> unloaded.
> +
> + @retval EFI_SUCCESS The image has been unloaded.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PlatformSetupDxeUnload (
> + IN EFI_HANDLE ImageHandle
> + )
> +{
> + if (mCallbackInfo != NULL) {
> + if (mCallbackInfo->DriverHandle != NULL) {
> + gBS->UninstallMultipleProtocolInterfaces (
> + mCallbackInfo->DriverHandle,
> + &gEfiDevicePathProtocolGuid,
> + &mHiiVendorDevicePath,
> + &gEfiHiiConfigAccessProtocolGuid,
> + &mCallbackInfo->ConfigAccess,
> + NULL
> + );
> + }
> +
> + if (mCallbackInfo->RegisteredHandle != NULL) {
> + HiiRemovePackages (mCallbackInfo->RegisteredHandle);
> + }
> +
> + FreePool (mCallbackInfo);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.h
> new file mode 100644
> index 0000000000..53372bb922
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.h
> @@ -0,0 +1,97 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +**/
> +
> +#ifndef _PLAT_OVER_MNGR_H_
> +#define _PLAT_OVER_MNGR_H_
> +
> +#include <FrameworkDxe.h>
> +
> +#include <Protocol/HiiConfigAccess.h>
> +#include <Protocol/HiiConfigRouting.h>
> +#include <Protocol/HiiDatabase.h>
> +#include <Protocol/FormBrowser2.h>
> +#include <Protocol/LoadedImage.h>
> +#include <Protocol/FirmwareVolume2.h>
> +#include <Protocol/PciIo.h>
> +#include <Protocol/BusSpecificDriverOverride.h>
> +#include <Protocol/ComponentName2.h>
> +#include <Protocol/ComponentName.h>
> +#include <Protocol/DriverBinding.h>
> +#include <Protocol/DevicePathToText.h>
> +#include <Protocol/DevicePath.h>
> +#include <Protocol/PlatformDriverOverride.h>
> +#include <Protocol/DataHub.h>
> +#include <Guid/MdeModuleHii.h>
> +#include <Guid/VariableFormat.h>
> +#include <Guid/DataHubRecords.h>
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/DxeServicesTableLib.h>
> +#include <Library/HiiLib.h>
> +#include <Library/BiosIdLib.h>
> +#include <Library/CpuIA32.h>
> +#include <Library/HobLib.h>
> +#include <Guid/PlatformInfo.h>
> +#include <IndustryStandard/Pci22.h>
> +
> +#include "Guid/SetupVariable.h"
> +#include "Guid/OsSelection.h"
> +
> +#include <CpuType.h>
> +#include <Guid/PlatformCpuInfo.h>
> +#include <Protocol/SimpleTextIn.h>
> +#include <Protocol/FrameworkFormBrowser.h>
> +extern EFI_HII_HANDLE mHiiHandle;
> +
> +UINT32
> +ConvertBase10ToRaw (
> + IN EFI_EXP_BASE10_DATA *Data);
> +
> +UINT32
> +ConvertBase2ToRaw (
> + IN EFI_EXP_BASE2_DATA *Data);
> +
> +EFI_STATUS
> +GetStringFromToken (
> + IN EFI_GUID *ProducerGuid,
> + IN STRING_REF Token,
> + OUT CHAR16 **String
> + );
> +
> +VOID
> +SwapEntries (
> + IN CHAR8 *Data
> + );
> +
> +VOID
> +AsciiToUnicode (
> + IN CHAR8 *AsciiString,
> + IN CHAR16 *UnicodeString
> + );
> +
> +VOID
> +EFIAPI
> +SetupInfo (
> + );
> +
> +
> +extern EFI_HANDLE mImageHandle;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.i
> nf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.i
> nf
> new file mode 100644
> index 0000000000..6d7e7c3f6c
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.i
> nf
> @@ -0,0 +1,141 @@
> +#
> +#
> +# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +# This driver produces UEFI PLATFORM_DRIVER_OVERRIDE_PROTOCOL if
> this protocol doesn't exist.
> +# It doesn't install again if this protocol exists.
> +# It only implements one interface GetDriver of
> PLATFORM_DRIVER_OVERRIDE_PROTOCOL protocol
> +# and doesn't support other two interfaces GetDriverPath, DriverLoaded.
> +#
> +# This driver also offers an UI interface in device manager to let user
> configure
> +# platform override protocol to override the default algorithm for matching
> +# drivers to controllers.
> +#
> +# The main flow:
> +# 1. It dynamicly locate all controller device path.
> +# 2. It dynamicly locate all drivers which support binding protocol.
> +# 3. It export and dynamicly update two menu to let user select the
> +# mapping between drivers to controllers.
> +# 4. It save all the mapping info in NV variables for the following boot,
> +# which will be consumed by GetDriver API of the produced the platform
> override protocol.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformSetupDxe
> + FILE_GUID = C1A69A12-8653-4fde-A215-48FCD95288C3
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PlatformSetupDxeInit
> + UNLOAD_IMAGE = PlatformSetupDxeUnload
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + VfrStrings.uni
> + FwVersionStrings.uni
> + Vfr.vfr
> + Main.vfi
> + Boot.vfi
> + PlatformSetupDxe.c
> + SetupInfoRecords.c
> + PlatformSetupDxe.h
> + Security.vfi
> + SouthClusterConfig.vfi
> + Thermal.vfi
> + SetupFunctions.c
> + UnCore.vfi
> + SystemComponent.vfi
> + DebugConfig.vfi
> + UqiList.uni
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec #for PchAccess.h
> + SecurityPkg/SecurityPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + UefiLib
> + UefiDriverEntryPoint
> + UefiBootServicesTableLib
> + HiiLib
> + BaseMemoryLib
> + MemoryAllocationLib
> + DevicePathLib
> + DxeServicesTableLib
> + UefiRuntimeServicesTableLib
> + PrintLib
> + BiosIdLib
> + CpuIA32Lib
> + IoLib
> +
> +[Guids]
> + ## This GUID C Name is not required for build since it is from UefiLib and
> not directly used by this module source.
> + ## gEfiGlobalVariableGuid ## SOMETIMES_CONSUMED ##
> Variable:L"PlatformLang" this variable specifies the platform supported
> language string (RFC 4646 format)
> + ## gEfiGlobalVariableGuid ## SOMETIMES_CONSUMED ##
> Variable:L"Lang" this variable specifies the platform supported language
> string (ISO 639-2 format)
> + ##
> + # There could be more than one variables, from PlatDriOver, PlatDriOver1,
> PlatDriOver2,...
> + #
> + # gEfiCallerIdGuid ## Private ## Variable:L"PlatDriOver"
> + gEfiIfrTianoGuid ## CONSUMES ## Guid
> + gEfiProcessorSubClassGuid
> + gEfiMiscSubClassGuid
> + gEfiCacheSubClassGuid
> + gEfiMemorySubClassGuid
> + gEfiPlatformInfoGuid
> + gEfiNormalSetupGuid
> + gEfiSecureBootEnableDisableGuid
> + gOsSelectionVariableGuid
> + gEfiGlobalVariableGuid
> +
> +[Protocols]
> + gEfiComponentName2ProtocolGuid ## SOMETIMES_CONSUMED
> (Get Driver Name if ComponentName2Protocol exists)
> + gEfiComponentNameProtocolGuid ## SOMETIMES_CONSUMED
> (Get Driver Name if ComponentNameProtocol exists and
> ComponentName2Protocol doesn't exist)
> + gEfiFirmwareVolume2ProtocolGuid ## SOMETIMES_CONSUMED
> (Get Driver Name from EFI UI section if ComponentName2Protocol and
> ComponentNameProtocol don't exist)
> + gEfiPciIoProtocolGuid ## SOMETIMES_CONSUMED (Find the
> PCI device if PciIo protocol is installed)
> + gEfiPciRootBridgeIoProtocolGuid
> + gEfiBusSpecificDriverOverrideProtocolGuid ## SOMETIMES_CONSUMED
> (Check whether the PCI device contains one or more efi drivers in its option
> rom by this protocol)
> +
> + gEfiDriverBindingProtocolGuid ## SOMETIMES_CONSUMED
> + gEfiLoadedImageProtocolGuid ## SOMETIMES_CONSUMED
> + gEfiLoadedImageDevicePathProtocolGuid ##
> SOMETIMES_CONSUMED (Show the drivers in the second page that support
> DriverBindingProtocol, LoadedImageProtocol and
> LoadedImageDevicePathProtocol)
> + gEfiDevicePathProtocolGuid ## SOMETIMES_CONSUMED (Show
> the controller device in the first page that support DevicePathProtocol)
> +
> + gEfiFormBrowser2ProtocolGuid ## CONSUMED
> + gEfiHiiConfigRoutingProtocolGuid ## CONSUMED
> + gEfiHiiConfigAccessProtocolGuid ## PRODUCED
> + gEfiDevicePathToTextProtocolGuid ## CONSUMED
> + gEdkiiFormBrowserEx2ProtocolGuid
> +
> + gEfiDataHubProtocolGuid
> + gEfiLegacyBiosProtocolGuid
> + gEfiSimpleNetworkProtocolGuid
> +
> + gEfiDiskInfoProtocolGuid ## CONSUMED
> + gEfiMpServiceProtocolGuid
> + gDxePchPlatformPolicyProtocolGuid
> + gEfiCpuIo2ProtocolGuid
> + gEfiTdtOperationProtocolGuid
> + gEfiSmbiosProtocolGuid ## PROTOCOL CONSUMES
> +
> +[Pcd.common]
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> +
> +[Depex]
> + gEfiFormBrowser2ProtocolGuid AND gEfiHiiConfigRoutingProtocolGuid
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Security.vfi
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Security.vfi
> new file mode 100644
> index 0000000000..49669e684d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Security.vfi
> @@ -0,0 +1,104 @@
> +//
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +//
>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +//
>
> +//
> +//
> +//
> +// Module Name:
> +//
> +// Security.vfi
> +//
> +// Abstract:
> +//
> +// Driver Setup formset.
> +//
> +// --*/
> +
> +//
> +// Security Configuration Form
> +//
> +
> +
> +form formid = SECURITY_CONFIGURATION_FORM_ID,
> + title = STRING_TOKEN(STR_SECURITY_CONFIGURATION_TITLE);
> +
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + //
> + //TPM related
> + //
> + subtitle text = STRING_TOKEN(STR_TPM_CONFIGURATION_PROMPT);
> +grayoutif ideqval Setup.ETpm== 0x1;
> + oneof varid = Setup.fTPM,
> + prompt = STRING_TOKEN(STR_PTT_PROMPT),
> + help = STRING_TOKEN(STR_PTT_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value= 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +endif;
> +
> +grayoutif ideqval Setup.fTPM == 0x1;
> + oneof varid = Setup.ETpm,
> + prompt = STRING_TOKEN(STR_TPM_PROMPT),
> + help = STRING_TOKEN(STR_TPM_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value= 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +endif;
> +
> +suppressif ideqval Setup.fTPM == 0;
> + oneof varid = Setup.MeasuredBootEnable,
> + prompt = STRING_TOKEN(STR_MEASURED_BOOT_ENABLE_PROMPT),
> + help = STRING_TOKEN(STR_MEASURED_BOOT_ENABLE_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +endif;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + subtitle text =
> STRING_TOKEN(STR_PASSWORD_CONFIGURATION_SUBTITLE);
> +
> + password varid = Setup.AdminPassword,
> + prompt = STRING_TOKEN(STR_ADMIN_PASSWORD),
> + help = STRING_TOKEN(STR_ADMIN_PASSWORD_HELP),
> + flags = 0,
> + minsize = 0,
> + maxsize = PASSWORD_MAX_SIZE,
> + encoding = 1,
> + endpassword;
> +
> + password varid = Setup.UserPassword,
> + prompt = STRING_TOKEN(STR_USER_PASSWORD),
> + help = STRING_TOKEN(STR_USER_PASSWORD_HELP),
> + flags = 0,
> + minsize = 0,
> + maxsize = PASSWORD_MAX_SIZE,
> + encoding = 1,
> + endpassword;
> +suppressif TRUE;
> + password varid = Setup.AdminPassword,
> + prompt = STRING_TOKEN(STR_CHANGE_ADMIN_PASSWORD),
> + help = STRING_TOKEN(STR_CHANGE_ADMIN_PASSWORD_HELP),
> + flags = 0,
> + minsize = 0,
> + maxsize = PASSWORD_MAX_SIZE,
> + encoding = 1,
> + endpassword;
> +
> + password varid = Setup.UserPassword,
> + prompt = STRING_TOKEN(STR_CHANGE_USER_PASSWORD),
> + help = STRING_TOKEN(STR_CHANGE_USER_PASSWORD_HELP),
> + flags = 0,
> + minsize = 0,
> + maxsize = PASSWORD_MAX_SIZE,
> + encoding = 1,
> + endpassword;
> +endif;
> +
> +endform;
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupFunctions.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupFunctions.c
> new file mode 100644
> index 0000000000..a84b425826
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupFunctions.c
> @@ -0,0 +1,85 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + SetupFunctions.c
> +
> +Abstract:
> +
> +Revision History
> +
> +--*/
> +
> +#include "PlatformSetupDxe.h"
> +
> +VOID
> +AsciiToUnicode (
> + IN CHAR8 *AsciiString,
> + IN CHAR16 *UnicodeString
> + )
> +{
> + UINT8 Index;
> +
> + Index = 0;
> + while (AsciiString[Index] != 0) {
> + UnicodeString[Index] = (CHAR16)AsciiString[Index];
> + Index++;
> + }
> +}
> +
> +VOID
> +SwapEntries (
> + IN CHAR8 *Data
> + )
> +{
> + UINT16 Index;
> + CHAR8 Temp8;
> +
> + Index = 0;
> + while (Data[Index] != 0 && Data[Index+1] != 0) {
> + Temp8 = Data[Index];
> + Data[Index] = Data[Index+1];
> + Data[Index+1] = Temp8;
> + Index +=2;
> + }
> +
> + return;
> +}
> +
> +UINT32
> +ConvertBase10ToRaw (
> + IN EFI_EXP_BASE10_DATA *Data)
> +{
> + UINTN Index;
> + UINT32 RawData;
> +
> + RawData = Data->Value;
> + for (Index = 0; Index < (UINTN) Data->Exponent; Index++) {
> + RawData *= 10;
> + }
> +
> + return RawData;
> +}
> +
> +UINT32
> +ConvertBase2ToRaw (
> + IN EFI_EXP_BASE2_DATA *Data)
> +{
> + UINTN Index;
> + UINT32 RawData;
> +
> + RawData = Data->Value;
> + for (Index = 0; Index < (UINTN) Data->Exponent; Index++) {
> + RawData <<= 1;
> + }
> +
> + return RawData;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupInfoRecords.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupInfoRecords.c
> new file mode 100644
> index 0000000000..c404ada588
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupInfoRecords.c
> @@ -0,0 +1,1855 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + SetupInfoRecords.c
> +
> +Abstract:
> +
> + This is the filter driver to retrieve data hub entries.
> +
> +Revision History:
> +--*/
> +
> +#include "PlatformSetupDxe.h"
> +#include <Protocol/LegacyBios.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include <Protocol/SimpleNetwork.h>
> +#include <Protocol/DevicePath.h>
> +#include <Protocol/DiskInfo.h>
> +#include <Protocol/IdeControllerInit.h>
> +#include <Protocol/MpService.h>
> +#include <Protocol/PchPlatformPolicy.h>
> +#include <Protocol/CpuIo2.h>
> +#include <Protocol/Smbios.h>
> +#include <IndustryStandard/SmBios.h>
> +#include <Library/IoLib.h>
> +#include <Library/I2CLib.h>
> +#include <Guid/GlobalVariable.h>
> +
> +#include "Valleyview.h"
> +#include "VlvAccess.h"
> +#include "PchAccess.h"
> +#include "SetupMode.h"
> +#include "PchCommonDefinitions.h"
> +#include <PlatformBaseAddresses.h>
> +
> +
> +typedef struct {
> + UINT8 ID;
> + CHAR8 String[16];
> +} VLV_REV;
> +
> +typedef struct {
> + UINT8 RevId;
> + CHAR8 String[16];
> +} SB_REV;
> +
> +//
> +// Silicon Steppings
> +//
> +SB_REV SBRevisionTable[] = {
> + {V_PCH_LPC_RID_0, "(A0 Stepping)"},
> + {V_PCH_LPC_RID_1, "(A0 Stepping)"},
> + {V_PCH_LPC_RID_2, "(A1 Stepping)"},
> + {V_PCH_LPC_RID_3, "(A1 Stepping)"},
> + {V_PCH_LPC_RID_4, "(B0 Stepping)"},
> + {V_PCH_LPC_RID_5, "(B0 Stepping)"},
> + {V_PCH_LPC_RID_6, "(B1 Stepping)"},
> + {V_PCH_LPC_RID_7, "(B1 Stepping)"},
> + {V_PCH_LPC_RID_8, "(B2 Stepping)"},
> + {V_PCH_LPC_RID_9, "(B2 Stepping)"},
> + {V_PCH_LPC_RID_A, "(B3 Stepping)"},
> + {V_PCH_LPC_RID_B, "(B3 Stepping)"},
> + {V_PCH_LPC_RID_C, "(C0 Stepping)"},
> + {V_PCH_LPC_RID_D, "(C0 Stepping)"}
> +};
> +
> +#define LEFT_JUSTIFY 0x01
> +#define PREFIX_SIGN 0x02
> +#define PREFIX_BLANK 0x04
> +#define COMMA_TYPE 0x08
> +#define LONG_TYPE 0x10
> +#define PREFIX_ZERO 0x20
> +
> +#define ICH_REG_REV 0x08
> +#define MSR_IA32_PLATFORM_ID 0x17
> +
> +
> +BOOLEAN mSetupInfoDone = FALSE;
> +UINT8 mUseProductKey = 0;
> +EFI_EXP_BASE10_DATA mProcessorFrequency;
> +EFI_EXP_BASE10_DATA mProcessorFsbFrequency;
> +
> +EFI_GUID mProcessorProducerGuid;
> +EFI_HII_HANDLE mHiiHandle;
> +EFI_PLATFORM_CPU_INFO mPlatformCpuInfo;
> +SYSTEM_CONFIGURATION mSystemConfiguration;
> +EFI_PLATFORM_INFO_HOB *mPlatformInfo;
> +
> +
> +#define memset SetMem
> +
> +UINT16 mMemorySpeed = 0xffff;
> +EFI_PHYSICAL_ADDRESS mMemorySizeChannelASlot0 = 0;
> +UINT16 mMemorySpeedChannelASlot0 = 0xffff;
> +EFI_PHYSICAL_ADDRESS mMemorySizeChannelASlot1 = 0;
> +UINT16 mMemorySpeedChannelASlot1 = 0xffff;
> +EFI_PHYSICAL_ADDRESS mMemorySizeChannelBSlot0 = 0;
> +UINT16 mMemorySpeedChannelBSlot0 = 0xffff;
> +EFI_PHYSICAL_ADDRESS mMemorySizeChannelBSlot1 = 0;
> +UINT16 mMemorySpeedChannelBSlot1 = 0xffff;
> +EFI_PHYSICAL_ADDRESS mMemorySizeChannelCSlot0 = 0;
> +UINT16 mMemorySpeedChannelCSlot0 = 0xffff;
> +EFI_PHYSICAL_ADDRESS mMemorySizeChannelCSlot1 = 0;
> +UINT16 mMemorySpeedChannelCSlot1 = 0xffff;
> +UINTN mMemoryMode = 0xff;
> +
> +#define CHARACTER_NUMBER_FOR_VALUE 30
> + typedef struct {
> + EFI_STRING_TOKEN MemoryDeviceLocator;
> + EFI_STRING_TOKEN MemoryBankLocator;
> + EFI_STRING_TOKEN MemoryManufacturer;
> + EFI_STRING_TOKEN MemorySerialNumber;
> + EFI_STRING_TOKEN MemoryAssetTag;
> + EFI_STRING_TOKEN MemoryPartNumber;
> + EFI_INTER_LINK_DATA MemoryArrayLink;
> + EFI_INTER_LINK_DATA MemorySubArrayLink;
> + UINT16 MemoryTotalWidth;
> + UINT16 MemoryDataWidth;
> + UINT64 MemoryDeviceSize;
> + EFI_MEMORY_FORM_FACTOR MemoryFormFactor;
> + UINT8 MemoryDeviceSet;
> + EFI_MEMORY_ARRAY_TYPE MemoryType;
> + EFI_MEMORY_TYPE_DETAIL MemoryTypeDetail;
> + UINT16 MemorySpeed;
> + EFI_MEMORY_STATE MemoryState;
> +} EFI_MEMORY_ARRAY_LINK;
> +
> +
> +typedef struct {
> + EFI_PHYSICAL_ADDRESS MemoryArrayStartAddress;
> + EFI_PHYSICAL_ADDRESS MemoryArrayEndAddress;
> + EFI_INTER_LINK_DATA PhysicalMemoryArrayLink;
> + UINT16 MemoryArrayPartitionWidth;
> +} EFI_MEMORY_ARRAY_START_ADDRESS;
> +
> +
> +typedef enum {
> + PCH_SATA_MODE_IDE = 0,
> + PCH_SATA_MODE_AHCI,
> + PCH_SATA_MODE_RAID,
> + PCH_SATA_MODE_MAX
> +} PCH_SATA_MODE;
> +
> +/**
> + Acquire the string associated with the Index from smbios structure and
> return it.
> + The caller is responsible for free the string buffer.
> +
> + @param OptionalStrStart The start position to search the string
> + @param Index The index of the string to extract
> + @param String The string that is extracted
> +
> + @retval EFI_SUCCESS The function returns EFI_SUCCESS always.
> +
> +**/
> +EFI_STATUS
> +GetOptionalStringByIndex (
> + IN CHAR8 *OptionalStrStart,
> + IN UINT8 Index,
> + OUT CHAR16 **String
> + )
> +{
> + UINTN StrSize;
> +
> + if (Index == 0) {
> + *String = AllocateZeroPool (sizeof (CHAR16));
> + return EFI_SUCCESS;
> + }
> +
> + StrSize = 0;
> + do {
> + Index--;
> + OptionalStrStart += StrSize;
> + StrSize = AsciiStrSize (OptionalStrStart);
> + } while (OptionalStrStart[StrSize] != 0 && Index != 0);
> +
> + if ((Index != 0) || (StrSize == 1)) {
> + //
> + // Meet the end of strings set but Index is non-zero, or
> + // Find an empty string
> + //
> + return EFI_NOT_FOUND;
> + } else {
> + *String = AllocatePool (StrSize * sizeof (CHAR16));
> + AsciiStrToUnicodeStr (OptionalStrStart, *String);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + VSPrint worker function that prints a Value as a decimal number in Buffer
> +
> + @param Buffer Location to place ascii decimal number string of Value.
> + @param Value Decimal value to convert to a string in Buffer.
> + @param Flags Flags to use in printing decimal string, see file header for
> details.
> + @param Width Width of hex value.
> +
> + Number of characters printed.
> +
> +**/
> +UINTN
> +EfiValueToString (
> + IN OUT CHAR16 *Buffer,
> + IN INT64 Value,
> + IN UINTN Flags,
> + IN UINTN Width
> + )
> +{
> + CHAR16 TempBuffer[CHARACTER_NUMBER_FOR_VALUE];
> + CHAR16 *TempStr;
> + CHAR16 *BufferPtr;
> + UINTN Count;
> + UINTN ValueCharNum;
> + UINTN Remainder;
> + CHAR16 Prefix;
> + UINTN Index;
> + BOOLEAN ValueIsNegative;
> + UINT64 TempValue;
> +
> + TempStr = TempBuffer;
> + BufferPtr = Buffer;
> + Count = 0;
> + ValueCharNum = 0;
> + ValueIsNegative = FALSE;
> +
> + if (Width > CHARACTER_NUMBER_FOR_VALUE - 1) {
> + Width = CHARACTER_NUMBER_FOR_VALUE - 1;
> + }
> +
> + if (Value < 0) {
> + Value = -Value;
> + ValueIsNegative = TRUE;
> + }
> +
> + do {
> + TempValue = Value;
> + Value = (INT64)DivU64x32 ((UINT64)Value, 10);
> + Remainder = (UINTN)((UINT64)TempValue - 10 * Value);
> + *(TempStr++) = (CHAR16)(Remainder + '0');
> + ValueCharNum++;
> + Count++;
> + if ((Flags & COMMA_TYPE) == COMMA_TYPE) {
> + if (ValueCharNum % 3 == 0 && Value != 0) {
> + *(TempStr++) = ',';
> + Count++;
> + }
> + }
> + } while (Value != 0);
> +
> + if (ValueIsNegative) {
> + *(TempStr++) = '-';
> + Count++;
> + }
> +
> + if ((Flags & PREFIX_ZERO) && !ValueIsNegative) {
> + Prefix = '0';
> + } else {
> + Prefix = ' ';
> + }
> +
> + Index = Count;
> + if (!(Flags & LEFT_JUSTIFY)) {
> + for (; Index < Width; Index++) {
> + *(TempStr++) = Prefix;
> + }
> + }
> +
> + //
> + // Reverse temp string into Buffer.
> + //
> + if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {
> + TempStr = TempBuffer + Width;
> + }
> + Index = 0;
> + while (TempStr != TempBuffer) {
> + *(BufferPtr++) = *(--TempStr);
> + Index++;
> + }
> +
> + *BufferPtr = 0;
> + return Index;
> +}
> +
> +static CHAR16 mHexStr[] = { L'0', L'1', L'2', L'3', L'4', L'5', L'6', L'7',
> + L'8', L'9', L'A', L'B', L'C', L'D', L'E', L'F' };
> +
> +/**
> + VSPrint worker function that prints a Value as a hex number in Buffer
> +
> + @param Buffer Location to place ascii hex string of Value.
> + @param Value Hex value to convert to a string in Buffer.
> + @param Flags Flags to use in printing Hex string, see file header for
> details.
> + @param Width Width of hex value.
> +
> + @retval Number of characters printed.
> +
> +**/
> +UINTN
> +EfiValueToHexStr (
> + IN OUT CHAR16 *Buffer,
> + IN UINT64 Value,
> + IN UINTN Flags,
> + IN UINTN Width
> + )
> +{
> + CHAR16 TempBuffer[CHARACTER_NUMBER_FOR_VALUE];
> + CHAR16 *TempStr;
> + CHAR16 Prefix;
> + CHAR16 *BufferPtr;
> + UINTN Count;
> + UINTN Index;
> +
> + TempStr = TempBuffer;
> + BufferPtr = Buffer;
> +
> + //
> + // Count starts at one since we will null terminate. Each iteration of the
> + // loop picks off one nibble. Oh yea TempStr ends up backwards
> + //
> + Count = 0;
> +
> + if (Width > CHARACTER_NUMBER_FOR_VALUE - 1) {
> + Width = CHARACTER_NUMBER_FOR_VALUE - 1;
> + }
> +
> + do {
> + Index = ((UINTN)Value & 0xf);
> + *(TempStr++) = mHexStr[Index];
> + Value = RShiftU64 (Value, 4);
> + Count++;
> + } while (Value != 0);
> +
> + if (Flags & PREFIX_ZERO) {
> + Prefix = '0';
> + } else {
> + Prefix = ' ';
> + }
> +
> + Index = Count;
> + if (!(Flags & LEFT_JUSTIFY)) {
> + for (; Index < Width; Index++) {
> + *(TempStr++) = Prefix;
> + }
> + }
> +
> + //
> + // Reverse temp string into Buffer.
> + //
> + if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {
> + TempStr = TempBuffer + Width;
> + }
> + Index = 0;
> + while (TempStr != TempBuffer) {
> + *(BufferPtr++) = *(--TempStr);
> + Index++;
> + }
> +
> + *BufferPtr = 0;
> + return Index;
> +}
> +
> +/*++
> + Converts MAC address to Unicode string.
> + The value is 64-bit and the resulting string will be 12
> + digit hex number in pairs of digits separated by dashes.
> +
> + @param String string that will contain the value
> + @param MacAddr add argument and description to function comment
> + @param AddrSize add argument and description to function comment
> +
> +**/
> +CHAR16 *
> +StrMacToString (
> + OUT CHAR16 *String,
> + IN EFI_MAC_ADDRESS *MacAddr,
> + IN UINT32 AddrSize
> + )
> +{
> + UINT32 i;
> +
> + for (i = 0; i < AddrSize; i++) {
> +
> + EfiValueToHexStr (
> + &String[2 * i],
> + MacAddr->Addr[i] & 0xFF,
> + PREFIX_ZERO,
> + 2
> + );
> + }
> +
> + //
> + // Terminate the string.
> + //
> + String[2 * AddrSize] = L'\0';
> +
> + return String;
> +}
> +
> +VOID UpdateLatestBootTime() {
> + UINTN VarSize;
> + EFI_STATUS Status;
> + UINT64 TimeValue;
> + CHAR16 Buffer[40];
> + if (mSystemConfiguration.LogBootTime != 1) {
> + return;
> + }
> + VarSize = sizeof(TimeValue);
> + Status = gRT->GetVariable(
> + BOOT_TIME_NAME,
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &TimeValue
> + );
> + if (EFI_ERROR(Status)) {
> + return;
> + }
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%d ms", (UINT32)TimeValue);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_LOG_BOOT_TIME_VALUE),
> Buffer, NULL);
> +}
> +
> +/**
> + Get Cache Type for the specified Cache. This function is invoked when
> there is data records
> + available in the Data Hub.
> +
> + Get Cache Type function arguments:
> +
> + @param Instance The instance number of the subclass with the same
> ProducerName..
> + @param SubInstance The instance number of the RecordType for the
> same Instance.
> + @param CacheType Cache type, see definition of
> EFI_CACHE_TYPE_DATA.
> +
> + @retval EFI_STATUS
> +
> +**/
> +EFI_STATUS
> +GetCacheType(
> + IN UINT16 Instance,
> + IN UINT16 SubInstance,
> + IN EFI_CACHE_TYPE_DATA* CacheType)
> +{
> + EFI_STATUS Status;
> + EFI_DATA_HUB_PROTOCOL *DataHub;
> + EFI_DATA_RECORD_HEADER *Record;
> + UINT64 MonotonicCount;
> + EFI_CACHE_VARIABLE_RECORD* CacheVariableRecord;
> + EFI_SUBCLASS_TYPE1_HEADER *DataHeader;
> +
> + Status = gBS->LocateProtocol (
> + &gEfiDataHubProtocolGuid,
> + NULL,
> + (void **)&DataHub
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // Get all available data records from data hub
> + //
> + MonotonicCount = 0;
> + Record = NULL;
> +
> + do {
> + Status = DataHub->GetNextRecord (
> + DataHub,
> + &MonotonicCount,
> + NULL,
> + &Record
> + );
> + if (!EFI_ERROR(Status)) {
> + if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {
> + DataHeader = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);
> +
> + if(CompareGuid(&Record->DataRecordGuid, &gEfiCacheSubClassGuid)
> &&
> + (DataHeader->RecordType == CacheTypeRecordType) &&
> + (DataHeader->Instance == Instance) &&
> + (DataHeader->SubInstance == SubInstance)) {
> + CacheVariableRecord = (EFI_CACHE_VARIABLE_RECORD
> *)(DataHeader + 1);
> + if(CacheType){
> + *CacheType = CacheVariableRecord->CacheType;
> + return EFI_SUCCESS;
> + }
> + }
> + }
> + }
> + } while(!EFI_ERROR(Status) && (MonotonicCount != 0));
> +
> + return EFI_NOT_FOUND;
> +}
> +
> +/**
> + Setup data filter function. This function is invoked when there is data
> records
> + available in the Data Hub.
> +
> +
> + Standard event notification function arguments:
> + @param Event The event that is signaled.
> + @param Context Not used here.
> +
> + @retval EFI_STATUS
> +
> +**/
> +VOID
> +PrepareSetupInformation (
> + )
> +{
> +
> + EFI_STATUS Status;
> + EFI_DATA_HUB_PROTOCOL *DataHub;
> + EFI_DATA_RECORD_HEADER *Record;
> + UINT8 *SrcData;
> + EFI_SUBCLASS_TYPE1_HEADER *DataHeader;
> + CHAR16 *NewString;
> + CHAR16 *NewString2;
> + CHAR16 *NewStringToken;
> + STRING_REF TokenToUpdate;
> + EFI_PROCESSOR_VERSION_DATA *ProcessorVersion;
> + UINTN Index;
> + UINTN DataOutput;
> +
> + EFI_PROCESSOR_MICROCODE_REVISION_DATA *CpuUcodeRevisionData;
> + EFI_MEMORY_ARRAY_START_ADDRESS *MemoryArray;
> + EFI_MEMORY_ARRAY_LINK *MemoryArrayLink;
> + UINT64 MonotonicCount;
> +
> + CHAR16 Version[100]; //Assuming that strings are < 100
> UCHAR
> + CHAR16 ReleaseDate[100]; //Assuming that strings are < 100
> UCHAR
> + CHAR16 ReleaseTime[100]; //Assuming that strings are < 100
> UCHAR
> +
> + NewString = AllocateZeroPool (0x100);
> + NewString2 = AllocateZeroPool (0x100);
> + SetMem(Version, sizeof(Version), 0);
> + SetMem(ReleaseDate, sizeof(ReleaseDate), 0);
> + SetMem(ReleaseTime, sizeof(ReleaseTime), 0);
> +
> + //
> + // Get the Data Hub Protocol. Assume only one instance
> + //
> + Status = gBS->LocateProtocol (&gEfiDataHubProtocolGuid, NULL, (void
> **)&DataHub);
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // Get all available data records from data hub
> + //
> + MonotonicCount = 0;
> + Record = NULL;
> +
> + do {
> + Status = DataHub->GetNextRecord (DataHub, &MonotonicCount, NULL,
> &Record);
> + if (!EFI_ERROR(Status)) {
> + if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {
> + DataHeader = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);
> + SrcData = (UINT8 *)(DataHeader + 1);
> +
> + //
> + // Processor
> + //
> + if (CompareGuid(&Record->DataRecordGuid,
> &gEfiProcessorSubClassGuid)) {
> + CopyMem (&mProcessorProducerGuid, &Record->ProducerName,
> sizeof(EFI_GUID));
> + switch (DataHeader->RecordType) {
> + case ProcessorCoreFrequencyRecordType:
> + CopyMem(&mProcessorFrequency, SrcData,
> sizeof(EFI_EXP_BASE10_DATA));
> + Index = EfiValueToString (
> + NewString,
> + ConvertBase10ToRaw
> ((EFI_EXP_BASE10_DATA *)SrcData)/1000000000,
> + PREFIX_ZERO,
> + 0
> + );
> + StrCat (NewString, L".");
> + EfiValueToString (
> + NewString + Index + 1,
> + ((ConvertBase10ToRaw
> ((EFI_EXP_BASE10_DATA *)SrcData)%1000000000)/10000000),
> + PREFIX_ZERO,
> + 0
> + );
> + StrCat (NewString, L" GHz");
> + TokenToUpdate = (STRING_REF)STR_PROCESSOR_SPEED_VALUE;
> + HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);
> + break;
> +
> + case ProcessorVersionRecordType:
> + ProcessorVersion = (EFI_PROCESSOR_VERSION_DATA *)SrcData;
> + NewStringToken = HiiGetPackageString(&mProcessorProducerGuid,
> *ProcessorVersion, NULL);
> + TokenToUpdate = (STRING_REF)STR_PROCESSOR_VERSION_VALUE;
> + HiiSetString(mHiiHandle, TokenToUpdate, NewStringToken, NULL);
> + break;
> + case CpuUcodeRevisionDataRecordType:
> + CpuUcodeRevisionData =
> (EFI_PROCESSOR_MICROCODE_REVISION_DATA *) SrcData;
> + if (CpuUcodeRevisionData->ProcessorMicrocodeRevisionNumber !=
> 0) {
> + EfiValueToHexStr (
> + NewString,
> + CpuUcodeRevisionData->ProcessorMicrocodeRevisionNumber,
> + PREFIX_ZERO,
> + 8
> + );
> + TokenToUpdate =
> (STRING_REF)STR_PROCESSOR_MICROCODE_VALUE;
> + HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);
> + }
> + break;
> + default:
> + break;
> + }
> +
> + //
> + // Cache
> + //
> + } else if (CompareGuid(&Record->DataRecordGuid,
> &gEfiCacheSubClassGuid) &&
> + (DataHeader->RecordType == CacheSizeRecordType)) {
> + if (DataHeader->SubInstance == EFI_CACHE_L1) {
> + EFI_CACHE_TYPE_DATA CacheType;
> + if (EFI_SUCCESS == GetCacheType(DataHeader->Instance,
> DataHeader->SubInstance,&CacheType)){
> + if (CacheType == EfiCacheTypeData) {
> + TokenToUpdate =
> (STRING_REF)STR_PROCESSOR_L1_DATA_CACHE_VALUE;
> + } else if (CacheType == EfiCacheTypeInstruction) {
> + TokenToUpdate =
> (STRING_REF)STR_PROCESSOR_L1_INSTR_CACHE_VALUE;
> + } else {
> + continue;
> + }
> + } else {
> + continue;
> + }
> + }
> + else if (DataHeader->SubInstance == EFI_CACHE_L2) {
> + TokenToUpdate = (STRING_REF)STR_PROCESSOR_L2_CACHE_VALUE;
> + } else {
> + continue;
> + }
> + if (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA *)SrcData)) {
> + DataOutput = ConvertBase2ToRaw((EFI_EXP_BASE2_DATA
> *)SrcData) >> 10;
> + EfiValueToString (NewString, DataOutput, PREFIX_ZERO, 0);
> +
> + StrCat (NewString, L" KB");
> + if (DataHeader->SubInstance == EFI_CACHE_L3) {
> + HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);
> + } else if(DataHeader->SubInstance == EFI_CACHE_L2 &&
> mPlatformCpuInfo.CpuPackage.CoresPerPhysicalPackage > 1){
> + //
> + // Show XxL2 string
> + //
> + EfiValueToString (
> + NewString2,
> + mPlatformCpuInfo.CpuPackage.CoresPerPhysicalPackage,
> + PREFIX_ZERO,
> + 0
> + );
> + StrCat(NewString2, L"x ");
> + StrCat(NewString2, NewString);
> + HiiSetString(mHiiHandle, TokenToUpdate, NewString2, NULL);
> + } else {
> + HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);
> + }
> + }
> +
> + //
> + // Memory
> + //
> + } else if (CompareGuid(&Record->DataRecordGuid,
> &gEfiMemorySubClassGuid)) {
> + switch (DataHeader->RecordType) {
> + case EFI_MEMORY_ARRAY_LINK_RECORD_NUMBER:
> + MemoryArrayLink = (EFI_MEMORY_ARRAY_LINK *)SrcData;
> +
> + if (MemoryArrayLink->MemorySpeed > 0) {
> + //
> + // Save the lowest speed memory module
> + //
> + if (MemoryArrayLink->MemorySpeed < mMemorySpeed) {
> + mMemorySpeed = MemoryArrayLink->MemorySpeed;
> + }
> + switch (DataHeader->SubInstance) {
> + case 1:
> + mMemorySpeedChannelASlot0 = MemoryArrayLink-
> >MemorySpeed;
> + mMemorySizeChannelASlot0 = MemoryArrayLink-
> >MemoryDeviceSize;
> + break;
> + case 2:
> + mMemorySpeedChannelASlot1 = MemoryArrayLink-
> >MemorySpeed;
> + mMemorySizeChannelASlot1 = MemoryArrayLink-
> >MemoryDeviceSize;
> + break;
> + case 3:
> + mMemorySpeedChannelBSlot0 = MemoryArrayLink-
> >MemorySpeed;
> + mMemorySizeChannelBSlot0 = MemoryArrayLink-
> >MemoryDeviceSize;
> + break;
> + case 4:
> + mMemorySpeedChannelBSlot1 = MemoryArrayLink-
> >MemorySpeed;
> + mMemorySizeChannelBSlot1 = MemoryArrayLink-
> >MemoryDeviceSize;
> + break;
> + case 5:
> + mMemorySpeedChannelCSlot0 = MemoryArrayLink-
> >MemorySpeed;
> + mMemorySizeChannelCSlot0 = MemoryArrayLink-
> >MemoryDeviceSize;
> + break;
> + case 6:
> + mMemorySpeedChannelCSlot1 = MemoryArrayLink-
> >MemorySpeed;
> + mMemorySizeChannelCSlot1 = MemoryArrayLink-
> >MemoryDeviceSize;
> + break;
> + default:
> + break;
> + }
> + }
> + break;
> +
> + case EFI_MEMORY_ARRAY_START_ADDRESS_RECORD_NUMBER:
> + MemoryArray = (EFI_MEMORY_ARRAY_START_ADDRESS *)SrcData;
> + if (MemoryArray->MemoryArrayEndAddress - MemoryArray-
> >MemoryArrayStartAddress) {
> + DataOutput = (UINTN)RShiftU64((MemoryArray-
> >MemoryArrayEndAddress - MemoryArray->MemoryArrayStartAddress + 1),
> 20);
> + EfiValueToString (NewString, DataOutput / 1024,
> PREFIX_ZERO, 0);
> + if(DataOutput % 1024) {
> + StrCat (NewString, L".");
> + DataOutput = ((DataOutput % 1024) * 1000) / 1024;
> + while(!(DataOutput % 10))
> + DataOutput = DataOutput / 10;
> + EfiValueToString (NewString2, DataOutput, PREFIX_ZERO, 0);
> + StrCat (NewString, NewString2);
> + }
> + StrCat (NewString, L" GB");
> + TokenToUpdate =
> (STRING_REF)STR_TOTAL_MEMORY_SIZE_VALUE;
> + HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);
> + }
> + break;
> +
> + default:
> + break;
> + }
> + }
> + }
> + }
> + } while (!EFI_ERROR(Status) && (MonotonicCount != 0));
> +
> + Status = GetBiosVersionDateTime (
> + Version,
> + ReleaseDate,
> + ReleaseTime
> + );
> +
> + DEBUG ((EFI_D_ERROR, "GetBiosVersionDateTime :%s %s %s \n", Version,
> ReleaseDate, ReleaseTime));
> + if (!EFI_ERROR (Status)) {
> + UINTN Length = 0;
> + CHAR16 *BuildDateTime;
> +
> + Length = StrLen(ReleaseDate) + StrLen(ReleaseTime);
> +
> + BuildDateTime = AllocateZeroPool ((Length+2) * sizeof(CHAR16));
> + StrCpy (BuildDateTime, ReleaseDate);
> + StrCat (BuildDateTime, L" ");
> + StrCat (BuildDateTime, ReleaseTime);
> +
> + TokenToUpdate = (STRING_REF)STR_BIOS_VERSION_VALUE;
> + DEBUG ((EFI_D_ERROR, "update STR_BIOS_VERSION_VALUE\n"));
> + HiiSetString(mHiiHandle, TokenToUpdate, Version, NULL);
> +
> + TokenToUpdate = (STRING_REF)STR_BIOS_BUILD_TIME_VALUE;
> + DEBUG ((EFI_D_ERROR, "update STR_BIOS_BUILD_TIME_VALUE\n"));
> + HiiSetString(mHiiHandle, TokenToUpdate, BuildDateTime, NULL);
> + }
> +
> + //
> + // Calculate and update memory speed display in Main Page
> + //
> + //
> + // Update the overall memory speed
> + //
> + if (mMemorySpeed != 0xffff) {
> + EfiValueToString (NewString, mMemorySpeed, PREFIX_ZERO, 0);
> + StrCat (NewString, L" MHz");
> +
> + TokenToUpdate = (STRING_REF)STR_SYSTEM_MEMORY_SPEED_VALUE;
> + HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);
> + }
> +
> + gBS->FreePool(NewString);
> + gBS->FreePool(NewString2);
> +
> + return;
> +}
> +
> +/**
> +
> + Routine Description: update the SETUP info for "Additional Information"
> which is SMBIOS info.
> +
> + @retval EFI_STATUS
> +
> +**/
> +EFI_STATUS
> +UpdateAdditionalInformation (
> + )
> +{
> + EFI_STATUS Status;
> + UINT64 MonotonicCount;
> + EFI_DATA_HUB_PROTOCOL *DataHub;
> + EFI_DATA_RECORD_HEADER *Record;
> + EFI_SUBCLASS_TYPE1_HEADER *DataHeader;
> + EFI_SMBIOS_PROTOCOL *Smbios;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + EFI_SMBIOS_TABLE_HEADER *SmbiosRecord;
> + SMBIOS_TABLE_TYPE0 *Type0Record;
> + UINT8 StrIndex;
> + CHAR16 *BiosVersion = NULL;
> + CHAR16 *IfwiVersion = NULL;
> + UINT16 SearchIndex;
> + EFI_STRING_ID TokenToUpdate;
> +#if defined( RVP_SUPPORT ) && RVP_SUPPORT
> + EFI_MISC_SYSTEM_MANUFACTURER *SystemManufacturer;
> +#endif
> +
> + Status = gBS->LocateProtocol (
> + &gEfiDataHubProtocolGuid,
> + NULL,
> + (void **)&DataHub
> + );
> +
> + ASSERT_EFI_ERROR(Status);
> +
> + MonotonicCount = 0;
> + Record = NULL;
> + do {
> + Status = DataHub->GetNextRecord (
> + DataHub,
> + &MonotonicCount,
> + NULL,
> + &Record
> + );
> + if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {
> + DataHeader = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);
> +
> + if (CompareGuid(&Record->DataRecordGuid, &gEfiMiscSubClassGuid)
> &&
> + (DataHeader->RecordType ==
> EFI_MISC_SYSTEM_MANUFACTURER_RECORD_NUMBER)) {
> +#if defined( RVP_SUPPORT ) && RVP_SUPPORT
> + //
> + // System Information
> + //
> + SystemManufacturer = (EFI_MISC_SYSTEM_MANUFACTURER
> *)(DataHeader + 1);
> +
> + //
> + // UUID (System Information)
> + //
> + SMBIOSString = EfiLibAllocateZeroPool (0x100);
> + GuidToString ( &SystemManufacturer->SystemUuid, SMBIOSString,
> 0x00 );
> +
> + TokenToUpdate = (STRING_REF)STR_SYSTEM_UUID_VALUE;
> + HiiSetString(mHiiHandle, TokenToUpdate, SMBIOSString, NULL);
> +
> + gBS->FreePool(SMBIOSString);
> +#endif
> + }
> + }
> + } while (!EFI_ERROR(Status) && (MonotonicCount != 0));
> +
> + Status = gBS->LocateProtocol (
> + &gEfiSmbiosProtocolGuid,
> + NULL,
> + (VOID **) &Smbios
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + do {
> + Status = Smbios->GetNext (
> + Smbios,
> + &SmbiosHandle,
> + NULL,
> + &SmbiosRecord,
> + NULL
> + );
> + if (SmbiosRecord->Type == EFI_SMBIOS_TYPE_BIOS_INFORMATION) {
> + Type0Record = (SMBIOS_TABLE_TYPE0 *) SmbiosRecord;
> + StrIndex = Type0Record->BiosVersion;
> + GetOptionalStringByIndex ((CHAR8*)((UINT8*)Type0Record +
> Type0Record->Hdr.Length), StrIndex, &BiosVersion);
> + TokenToUpdate = STRING_TOKEN (STR_BIOS_VERSION_VALUE);
> + for (SearchIndex = 0x0; SearchIndex < SMBIOS_STRING_MAX_LENGTH;
> SearchIndex++) {
> + if (BiosVersion[SearchIndex] == 0x0020) {
> + BiosVersion[SearchIndex] = 0x0000;
> + IfwiVersion = (CHAR16 *)(&BiosVersion[SearchIndex+1]);
> + break;
> + } else if (BiosVersion[SearchIndex] == 0x0000) {
> + break;
> + }
> + }
> + HiiSetString (mHiiHandle, TokenToUpdate, BiosVersion, NULL);
> +
> + //
> + // Check IfwiVersion, to avoid no IFWI version in SMBIOS Type 0
> strucntion
> + //
> + if(IfwiVersion) {
> + TokenToUpdate = STRING_TOKEN (STR_IFWI_VERSION_VALUE);
> + HiiSetString (mHiiHandle, TokenToUpdate, IfwiVersion, NULL);
> + }
> + }
> + } while (!EFI_ERROR(Status));
> +
> + UpdateLatestBootTime();
> +
> + return EFI_SUCCESS;
> +}
> +
> +VOID
> +UpdateCPUInformation ()
> +{
> + CHAR16
> Buffer[40];
> + UINT16 FamilyId;
> + UINT8 Model;
> + UINT8 SteppingId;
> + UINT8 ProcessorType;
> + EFI_STATUS Status;
> + EFI_MP_SERVICES_PROTOCOL *MpService;
> + UINTN MaximumNumberOfCPUs;
> + UINTN NumberOfEnabledCPUs;
> + UINT32
> Buffer32 = 0xFFFFFFFF; // Keep buffer with unknown device
> +
> + EfiCpuVersion (&FamilyId, &Model, &SteppingId, &ProcessorType);
> +
> + //
> + //we need raw Model data
> + //
> + Model = Model & 0xf;
> +
> + //
> + //Family/Model/Step
> + //
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%d/%d/%d", FamilyId, Model,
> SteppingId);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_PROCESSOR_ID_VALUE),
> Buffer, NULL);
> +
> + Status = gBS->LocateProtocol (
> + &gEfiMpServiceProtocolGuid,
> + NULL,
> + (void **)&MpService
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Determine the number of processors
> + //
> + MpService->GetNumberOfProcessors (
> + MpService,
> + &MaximumNumberOfCPUs,
> + &NumberOfEnabledCPUs
> + );
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%d", MaximumNumberOfCPUs);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_PROCESSOR_CORE_VALUE),
> Buffer, NULL);
> + }
> + //
> + // Update Mobile / Desktop / Tablet SKU
> + //
> + Buffer32 =(UINT32) RShiftU64 (EfiReadMsr (MSR_IA32_PLATFORM_ID), 50)
> & 0x07;
> +
> + switch(Buffer32){
> + case 0x0:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"(%d) - ISG SKU SOC", Buffer32);
> + break;
> + case 0x01:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"(%d) - Mobile SKU SOC",
> Buffer32);
> + break;
> + case 0x02:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"(%d) - Desktop SKU SOC",
> Buffer32);
> + break;
> + case 0x03:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"(%d) - Mobile SKU SOC",
> Buffer32);
> + break;
> + default:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"(%d) - Unknown SKU SOC",
> Buffer32);
> + break;
> + }
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_PROCESSOR_SKU_VALUE),
> Buffer, NULL);
> +
> +}
> +
> +
> +EFI_STATUS
> +SearchChildHandle(
> + EFI_HANDLE Father,
> + EFI_HANDLE *Child
> + )
> +{
> + EFI_STATUS Status;
> + UINTN HandleIndex;
> + EFI_GUID **ProtocolGuidArray = NULL;
> + UINTN ArrayCount;
> + UINTN ProtocolIndex;
> + UINTN OpenInfoCount;
> + UINTN OpenInfoIndex;
> + EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfo = NULL;
> + UINTN mHandleCount;
> + EFI_HANDLE *mHandleBuffer= NULL;
> +
> + //
> + // Retrieve the list of all handles from the handle database
> + //
> + Status = gBS->LocateHandleBuffer (
> + AllHandles,
> + NULL,
> + NULL,
> + &mHandleCount,
> + &mHandleBuffer
> + );
> +
> + for (HandleIndex = 0; HandleIndex < mHandleCount; HandleIndex++)
> + {
> + //
> + // Retrieve the list of all the protocols on each handle
> + //
> + Status = gBS->ProtocolsPerHandle (
> + mHandleBuffer[HandleIndex],
> + &ProtocolGuidArray,
> + &ArrayCount
> + );
> + if (!EFI_ERROR (Status))
> + {
> + for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++)
> + {
> + Status = gBS->OpenProtocolInformation (
> + mHandleBuffer[HandleIndex],
> + ProtocolGuidArray[ProtocolIndex],
> + &OpenInfo,
> + &OpenInfoCount
> + );
> + if (!EFI_ERROR (Status))
> + {
> + for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount;
> OpenInfoIndex++)
> + {
> + if(OpenInfo[OpenInfoIndex].AgentHandle == Father)
> + {
> + if ((OpenInfo[OpenInfoIndex].Attributes &
> EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) ==
> EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER)
> + {
> + *Child = mHandleBuffer[HandleIndex];
> + Status = EFI_SUCCESS;
> + goto TryReturn;
> + }
> + }
> + }
> + Status = EFI_NOT_FOUND;
> + }
> + }
> + if(OpenInfo != NULL)
> + {
> + FreePool(OpenInfo);
> + OpenInfo = NULL;
> + }
> + }
> + FreePool (ProtocolGuidArray);
> + ProtocolGuidArray = NULL;
> + }
> +TryReturn:
> + if(OpenInfo != NULL)
> + {
> + FreePool (OpenInfo);
> + OpenInfo = NULL;
> + }
> + if(ProtocolGuidArray != NULL)
> + {
> + FreePool(ProtocolGuidArray);
> + ProtocolGuidArray = NULL;
> + }
> + if(mHandleBuffer != NULL)
> + {
> + FreePool (mHandleBuffer);
> + mHandleBuffer = NULL;
> + }
> + return Status;
> +}
> +
> +EFI_STATUS
> +JudgeHandleIsPCIDevice(
> + EFI_HANDLE Handle,
> + UINT8 Device,
> + UINT8 Funs
> + )
> +{
> + EFI_STATUS Status;
> + EFI_DEVICE_PATH *DPath;
> +
> + Status = gBS->HandleProtocol (
> + Handle,
> + &gEfiDevicePathProtocolGuid,
> + (VOID **) &DPath
> + );
> + if(!EFI_ERROR(Status))
> + {
> + while(!IsDevicePathEnd(DPath))
> + {
> + if((DPath->Type == HARDWARE_DEVICE_PATH) && (DPath->SubType ==
> HW_PCI_DP))
> + {
> + PCI_DEVICE_PATH *PCIPath;
> +
> + PCIPath = (PCI_DEVICE_PATH*) DPath;
> + DPath = NextDevicePathNode(DPath);
> + if(IsDevicePathEnd(DPath) && (PCIPath->Device == Device) &&
> (PCIPath->Function == Funs))
> + {
> + return EFI_SUCCESS;
> + }
> + }
> + else
> + {
> + DPath = NextDevicePathNode(DPath);
> + }
> + }
> + }
> + return EFI_UNSUPPORTED;
> +}
> +
> +EFI_STATUS
> +GetDriverName(
> + EFI_HANDLE Handle,
> + CHAR16 *Name
> + )
> +{
> + EFI_DRIVER_BINDING_PROTOCOL *BindHandle = NULL;
> + EFI_STATUS Status;
> + UINT32 Version;
> + UINT16 *Ptr;
> + Status = gBS->OpenProtocol(
> + Handle,
> + &gEfiDriverBindingProtocolGuid,
> + (VOID**)&BindHandle,
> + NULL,
> + NULL,
> + EFI_OPEN_PROTOCOL_GET_PROTOCOL
> + );
> +
> + if (EFI_ERROR(Status))
> + {
> + return EFI_NOT_FOUND;
> + }
> +
> + Version = BindHandle->Version;
> + Ptr = (UINT16*)&Version;
> + UnicodeSPrint(Name, 40, L"%d.%d.%d", Version >> 24 , (Version >>16)&
> 0x0f ,*(Ptr));
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +GetGOPDriverName(
> + CHAR16 *Name
> + )
> +{
> + UINTN HandleCount;
> + EFI_HANDLE *Handles= NULL;
> + UINTN Index;
> + EFI_STATUS Status;
> + EFI_HANDLE Child = 0;
> +
> + Status = gBS->LocateHandleBuffer(
> + ByProtocol,
> + &gEfiDriverBindingProtocolGuid,
> + NULL,
> + &HandleCount,
> + &Handles
> + );
> + for (Index = 0; Index < HandleCount ; Index++)
> + {
> + Status = SearchChildHandle(Handles[Index], &Child);
> + if(!EFI_ERROR(Status))
> + {
> + Status = JudgeHandleIsPCIDevice(
> + Child,
> + 0x02,
> + 0x00
> + );
> + if(!EFI_ERROR(Status))
> + {
> + return GetDriverName(Handles[Index], Name);
> + }
> + }
> + }
> + return EFI_UNSUPPORTED;
> +}
> +
> +EFI_STATUS
> +UpdatePlatformInformation (
> + )
> +{
> + UINT32 MicroCodeVersion;
> + CHAR16 Buffer[40];
> + UINT8 IgdVBIOSRevH;
> + UINT8 IgdVBIOSRevL;
> + UINT16 EDX;
> + EFI_IA32_REGISTER_SET RegSet;
> + EFI_LEGACY_BIOS_PROTOCOL *LegacyBios = NULL;
> + EFI_STATUS Status;
> + UINT8 CpuFlavor=0;
> + EFI_PEI_HOB_POINTERS GuidHob;
> + UINTN NumHandles;
> + EFI_HANDLE *HandleBuffer;
> + UINTN Index;
> + DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy;
> + UINTN PciD31F0RegBase;
> + UINT8 count;
> + UINT8 Data8;
> + UINT8 PIDData8;
> +
> + CHAR16 Name[40];
> + UINT32 MrcVersion;
> +
> + //
> + // Get the HOB list. If it is not present, then ASSERT.
> + //
> + GuidHob.Raw = GetHobList ();
> + if (GuidHob.Raw != NULL) {
> + if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid,
> GuidHob.Raw)) != NULL) {
> + mPlatformInfo = GET_GUID_HOB_DATA (GuidHob.Guid);
> + }
> + }
> +
> + //
> + //VBIOS version
> + //
> + Status = gBS->LocateProtocol(
> + &gEfiLegacyBiosProtocolGuid,
> + NULL,
> + (void **)&LegacyBios
> + );
> + if (!EFI_ERROR (Status)) {
> + RegSet.X.AX = 0x5f01;
> + Status = LegacyBios->Int86 (LegacyBios, 0x10, &RegSet);
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // simulate AMI int15 (ax=5f01) handler
> + // check NbInt15.asm in AMI code for asm edition
> + //
> + EDX = (UINT16)((RegSet.E.EBX >> 16) & 0xffff);
> + IgdVBIOSRevH = (UINT8)(((EDX & 0x0F00) >> 4) | (EDX & 0x000F));
> + IgdVBIOSRevL = (UINT8)(((RegSet.X.BX & 0x0F00) >> 4) | (RegSet.X.BX &
> 0x000F));
> +
> + if (IgdVBIOSRevH==0 && IgdVBIOSRevL==0){
> + HiiSetString(mHiiHandle,
> STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_VALUE), L"N/A", NULL);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%02X%02X",
> IgdVBIOSRevH,IgdVBIOSRevL);
> + HiiSetString(mHiiHandle,
> STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_VALUE), Buffer, NULL);
> + }
> + }
> +
> + Status = GetGOPDriverName(Name);
> +
> + if (!EFI_ERROR(Status))
> + {
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_GOP_VALUE), Name,
> NULL);
> + }
> +
> +
> + //
> + // CpuFlavor
> + // ISG-DC Tablet 000
> + // VLV-QC Tablet 001
> + // VLV-QC Desktop 010
> + // VLV-QC Notebook 011
> + //
> + CpuFlavor = RShiftU64 (EfiReadMsr (MSR_IA32_PLATFORM_ID), 50) & 0x07;
> +
> + switch(CpuFlavor){
> + case 0x0:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-DC Tablet",
> CpuFlavor);
> + break;
> + case 0x01:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC
> Notebook", CpuFlavor);
> + break;
> + case 0x02:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC Desktop",
> CpuFlavor);
> + break;
> + case 0x03:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC
> Notebook", CpuFlavor);
> + break;
> + default:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"Unknown CPU",
> CpuFlavor);
> + break;
> + }
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_CPU_FLAVOR_VALUE),
> Buffer, NULL);
> +
> + if ( NULL != mPlatformInfo) {
> + //
> + //BoardId
> + //
> + switch(mPlatformInfo->BoardId){
> + case 0x2:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"BAY LAKE RVP(%02x)",
> mPlatformInfo->BoardId);
> + break;
> +
> + case 0x4:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"BAY LAKE FFRD(%02x)",
> mPlatformInfo->BoardId);
> + break;
> +
> + case 0x5:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"BAY ROCK RVP DDR3L (%02x)",
> mPlatformInfo->BoardId);
> + break;
> +
> + case 0x20:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"BAYLEY BAY (%02x)",
> mPlatformInfo->BoardId);
> + break;
> +
> + case 0x30:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"BAKER SPORT (%02x)",
> mPlatformInfo->BoardId);
> + break;
> +
> + case 0x0:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"ALPINE VALLEY (%x)",
> mPlatformInfo->BoardId);
> + break;
> +
> + case 0x3:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"BAY LAKE FFD8 (%x)",
> mPlatformInfo->BoardId);
> + break;
> +
> + default:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"Unknown BOARD (%02x)",
> mPlatformInfo->BoardId);
> + break;
> + }
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_BOARD_ID_VALUE), Buffer,
> NULL);
> +
> +
> + //
> + // Get Board FAB ID Info from protocol, update into the NVS area.
> + // bit0~bit3 are for Fab ID, 0x0F means unknow FAB.
> + //
> + if(mPlatformInfo->BoardRev == 0x0F) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", L"Unknown FAB");
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_FAB_ID_VALUE), Buffer,
> NULL);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%2x", mPlatformInfo-
> >BoardRev);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_FAB_ID_VALUE), Buffer,
> NULL);
> + }
> + }
> +
> + //
> + //Update MRC Version
> + //
> + MrcVersion = 0x00000000;
> + MrcVersion &= 0xffff;
> + Index = EfiValueToString (Buffer, MrcVersion/100, PREFIX_ZERO, 0);
> + StrCat (Buffer, L".");
> + EfiValueToString (Buffer + Index + 1, (MrcVersion%100)/10, PREFIX_ZERO,
> 0);
> + EfiValueToString (Buffer + Index + 2, (MrcVersion%100)%10, PREFIX_ZERO,
> 0);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MRC_VERSION_VALUE),
> Buffer, NULL);
> +
> + //
> + //Update Soc Version
> + //
> +
> + //
> + // Retrieve all instances of PCH Platform Policy protocol
> + //
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gDxePchPlatformPolicyProtocolGuid,
> + NULL,
> + &NumHandles,
> + &HandleBuffer
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Find the matching PCH Policy protocol
> + //
> + for (Index = 0; Index < NumHandles; Index++) {
> + Status = gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gDxePchPlatformPolicyProtocolGuid,
> + (void **)&PchPlatformPolicy
> + );
> + if (!EFI_ERROR (Status)) {
> + PciD31F0RegBase = MmPciAddress (
> + 0,
> + PchPlatformPolicy->BusNumber,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + 0
> + );
> +
> + Data8 = MmioRead8 (PciD31F0RegBase + R_PCH_LPC_RID_CC);
> + count = ARRAY_SIZE (SBRevisionTable);
> + for (Index = 0; Index < count; Index++) {
> + if(Data8 == SBRevisionTable[Index].RevId) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%02x %a", Data8,
> SBRevisionTable[Index].String);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_SOC_VALUE), Buffer,
> NULL);
> + break;
> + }
> + }
> + break;
> + }
> + }
> + }
> +
> + //
> + // Microcode Revision
> + //
> + EfiWriteMsr (EFI_MSR_IA32_BIOS_SIGN_ID, 0);
> + EfiCpuid (EFI_CPUID_VERSION_INFO, NULL);
> + MicroCodeVersion = (UINT32) RShiftU64 (EfiReadMsr
> (EFI_MSR_IA32_BIOS_SIGN_ID), 32);
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", MicroCodeVersion);
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_PROCESSOR_MICROCODE_VAL
> UE), Buffer, NULL);
> +
> + //
> + // Punit Version
> + //
> + Data8 = 0;
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"0x%x", Data8);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_PUNIT_FW_VALUE), Buffer,
> NULL);
> +
> + //
> + // PMC Version
> + //
> + Data8 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS +
> R_PCH_PMC_PRSTS)>>16)&0x00FF);
> + PIDData8 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS +
> R_PCH_PMC_PRSTS)>>24)&0x00FF);
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"0x%X_%X",PIDData8, Data8);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_PMC_FW_VALUE), Buffer,
> NULL);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +
> + Update SATA Drivesize Strings for Setup and Boot order
> +
> + @param NewString - pointer to string.
> + @param DeviceSpeed - speed of drive.
> +
> +**/
> +VOID
> +GetDeviceSpeedString (
> + CHAR16 *NewString,
> + IN UINTN DeviceSpeed
> + )
> +{
> + if (DeviceSpeed == 0x01) {
> + StrCat (NewString, L"1.5Gb/s");
> + } else if (DeviceSpeed == 0x02) {
> + StrCat (NewString, L"3.0Gb/s");
> + } else if (DeviceSpeed == 0x03) {
> + StrCat (NewString, L"6.0Gb/s");
> + } else if (DeviceSpeed == 0x0) {
> +
> + }
> +}
> +
> +UINT8
> +GetChipsetSataPortSpeed (
> + UINTN PortNum
> + )
> +{
> + UINT32 DeviceSpeed;
> + UINT8 DeviceConfigStatus;
> + UINT32 IdeAhciBar;
> + EFI_PHYSICAL_ADDRESS MemBaseAddress = 0;
> + UINT8 FunNum;
> +
> + DeviceSpeed = 0x01; // generation 1
> +
> +
> + //
> + // Allocate the AHCI BAR
> + //
> + FunNum = PCI_FUNCTION_NUMBER_PCH_SATA;
> + MemBaseAddress = 0x0ffffffff;
> + gDS->AllocateMemorySpace (
> + EfiGcdAllocateMaxAddressSearchBottomUp,
> + EfiGcdMemoryTypeMemoryMappedIo,
> + N_PCH_SATA_ABAR_ALIGNMENT, // 2^11: 2K Alignment
> + V_PCH_SATA_ABAR_LENGTH, // 2K Length
> + &MemBaseAddress,
> + mImageHandle,
> + NULL
> + );
> + IdeAhciBar = MmioRead32 (
> + MmPciAddress (
> + 0,
> + 0,
> + PCI_DEVICE_NUMBER_PCH_SATA,
> + FunNum,
> + R_PCH_SATA_ABAR
> + )
> + );
> + IdeAhciBar &= 0xFFFFF800;
> + DeviceConfigStatus = 0;
> + if (IdeAhciBar == 0) {
> + DeviceConfigStatus = 1;
> + IdeAhciBar = (UINT32)MemBaseAddress;
> + MmioWrite32 (
> + MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_SATA, FunNum,
> R_PCH_SATA_ABAR),
> + IdeAhciBar
> + );
> + MmioOr16 (
> + MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_SATA, FunNum,
> R_PCH_SATA_COMMAND),
> + B_PCH_SATA_COMMAND_MSE
> + );
> + }
> +
> + if (mSystemConfiguration.SataType == PCH_SATA_MODE_IDE){
> + //
> + // Program the "Ports Implemented Register"
> + //
> + MmioAndThenOr32 (IdeAhciBar + R_PCH_SATA_AHCI_PI,
> (UINT32)~(B_PCH_SATA_PORT0_IMPLEMENTED +
> B_PCH_SATA_PORT1_IMPLEMENTED),
> (UINT32)(B_PCH_SATA_PORT0_IMPLEMENTED +
> B_PCH_SATA_PORT1_IMPLEMENTED));
> + }
> +
> + switch (PortNum)
> + {
> + case 0:
> + DeviceSpeed = *(volatile UINT32 *)(UINTN)(IdeAhciBar +
> R_PCH_SATA_AHCI_P0SSTS);
> + break;
> + case 1:
> + DeviceSpeed = *(volatile UINT32 *)(UINTN)(IdeAhciBar +
> R_PCH_SATA_AHCI_P1SSTS);
> + break;
> + }
> +
> + if (MemBaseAddress) {
> + gDS->FreeMemorySpace (
> + MemBaseAddress,
> + V_PCH_SATA_ABAR_LENGTH
> + );
> + }
> +
> + if (DeviceConfigStatus) {
> + IdeAhciBar = 0;
> + MmioWrite32 (
> + MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_SATA, FunNum,
> R_PCH_SATA_ABAR),
> + IdeAhciBar
> + );
> + }
> +
> + DeviceSpeed = (UINT8)((DeviceSpeed >> 4) & 0x0F);
> +
> + return (UINT8)DeviceSpeed;
> +}
> +
> +/**
> +
> + IDE data filter function.
> +
> +**/
> +void
> +IdeDataFilter (void)
> +{
> + EFI_STATUS Status;
> + UINTN HandleCount;
> + EFI_HANDLE *HandleBuffer;
> + EFI_DISK_INFO_PROTOCOL *DiskInfo;
> + EFI_DEVICE_PATH_PROTOCOL *DevicePath, *DevicePathNode;
> + PCI_DEVICE_PATH *PciDevicePath;
> + UINTN Index;
> + UINT8 Index1;
> + UINT32 BufferSize;
> + UINT32 DriveSize;
> + UINT32 IdeChannel;
> + UINT32 IdeDevice;
> + EFI_ATA_IDENTIFY_DATA *IdentifyDriveInfo;
> + CHAR16 *NewString;
> + CHAR16 SizeString[20];
> + STRING_REF NameToUpdate;
> + CHAR8 StringBuffer[0x100];
> + UINT32 DeviceSpeed;
> + UINTN PortNumber;
> +
> + //
> + // Assume no line strings is longer than 256 bytes.
> + //
> + NewString = AllocateZeroPool (0x100);
> + PciDevicePath = NULL;
> +
> + //
> + // Fill IDE Infomation
> + //
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiDiskInfoProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> +
> + if (EFI_ERROR (Status)) {
> + return;
> + }
> +
> + for (Index = 0; Index < HandleCount; Index++) {
> +
> + Status = gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gEfiDevicePathProtocolGuid,
> + (VOID*)&DevicePath
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + DevicePathNode = DevicePath;
> + while (!IsDevicePathEnd (DevicePathNode) ) {
> + if ((DevicePathType (DevicePathNode) == HARDWARE_DEVICE_PATH)
> &&
> + ( DevicePathSubType (DevicePathNode) == HW_PCI_DP)) {
> + PciDevicePath = (PCI_DEVICE_PATH *) DevicePathNode;
> + break;
> + }
> + DevicePathNode = NextDevicePathNode (DevicePathNode);
> + }
> +
> + if (PciDevicePath == NULL) {
> + continue;
> + }
> +
> + //
> + // Check for onboard IDE
> + //
> + if (PciDevicePath->Device== PCI_DEVICE_NUMBER_PCH_SATA) {
> + Status = gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gEfiDiskInfoProtocolGuid,
> + (void **)&DiskInfo
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = DiskInfo->WhichIde (
> + DiskInfo,
> + &IdeChannel,
> + &IdeDevice
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + IdentifyDriveInfo = AllocatePool (sizeof(EFI_ATA_IDENTIFY_DATA));
> +
> + BufferSize = sizeof(EFI_ATA_IDENTIFY_DATA);
> + Status = DiskInfo->Identify (
> + DiskInfo,
> + IdentifyDriveInfo,
> + &BufferSize
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // Onboard SATA Devices
> + //
> + if (PciDevicePath->Function == PCI_FUNCTION_NUMBER_PCH_SATA) {
> + if (IdeChannel == 0 && IdeDevice == 0) {
> + NameToUpdate = (STRING_REF)STR_SATA0_NAME;
> + } else if (IdeChannel == 1 && IdeDevice == 0) {
> + NameToUpdate = (STRING_REF)STR_SATA1_NAME;
> + } else {
> + continue;
> + }
> + } else {
> + continue;
> + }
> +
> + ZeroMem(StringBuffer, sizeof(StringBuffer));
> + CopyMem(
> + StringBuffer,
> + (CHAR8 *)&IdentifyDriveInfo->ModelName,
> + sizeof(IdentifyDriveInfo->ModelName)
> + );
> + SwapEntries(StringBuffer);
> + AsciiToUnicode(StringBuffer, NewString);
> +
> + //
> + // Chap it off after 16 characters
> + //
> + NewString[16] = 0;
> +
> + //
> + // For HardDisk append the size. Otherwise display atapi
> + //
> + if ((IdentifyDriveInfo->config & 0x8000) == 00) {
> + //
> + // 48 bit address feature set is supported, get maximum capacity
> + //
> + if ((IdentifyDriveInfo->command_set_supported_83 & 0x0400) == 0) {
> + DriveSize = (((((IdentifyDriveInfo->user_addressable_sectors_hi << 16)
> +
> + IdentifyDriveInfo->user_addressable_sectors_lo) / 1000) * 512)
> / 1000);
> + } else {
> + DriveSize = IdentifyDriveInfo-
> >maximum_lba_for_48bit_addressing[0];
> + for (Index1 = 1; Index1 < 4; Index1++) {
> + //
> + // Lower byte goes first: word[100] is the lowest word, word[103] is
> highest
> + //
> + DriveSize |= LShiftU64(IdentifyDriveInfo-
> >maximum_lba_for_48bit_addressing[Index1], 16 * Index1);
> + }
> + DriveSize = (UINT32) DivU64x32(MultU64x32(DivU64x32(DriveSize,
> 1000), 512), 1000);
> + }
> +
> + StrCat (NewString, L"(");
> + EfiValueToString (SizeString, DriveSize/1000, PREFIX_BLANK, 0);
> + StrCat (NewString, SizeString);
> + StrCat (NewString, L".");
> + EfiValueToString (SizeString, (DriveSize%1000)/100, PREFIX_BLANK, 0);
> + StrCat (NewString, SizeString);
> + StrCat (NewString, L"GB");
> + } else {
> + StrCat (NewString, L"(ATAPI");
> + }
> +
> + //
> + // Update SPEED.
> + //
> + PortNumber = (IdeDevice << 1) + IdeChannel;
> + DeviceSpeed = GetChipsetSataPortSpeed(PortNumber);
> +
> + if (DeviceSpeed) {
> + StrCat (NewString, L"-");
> + GetDeviceSpeedString( NewString, DeviceSpeed);
> + }
> +
> + StrCat (NewString, L")");
> +
> + HiiSetString(mHiiHandle, NameToUpdate, NewString, NULL);
> +
> + }
> + }
> +
> + if (HandleBuffer != NULL) {
> + gBS->FreePool (HandleBuffer);
> + }
> +
> + gBS->FreePool(NewString);
> +
> + return;
> +}
> +
> +
> +VOID
> +EFIAPI
> +SetupInfo (void)
> +{
> + EFI_STATUS Status;
> + UINTN VarSize;
> + EFI_PEI_HOB_POINTERS GuidHob;
> +
> + if (mSetupInfoDone) {
> + return;
> + }
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + NORMAL_SETUP_NAME,
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> +
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = gRT->GetVariable(
> + L"SetupRecovery",
> + &gEfiNormalSetupGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + //
> + // Update HOB variable for PCI resource information
> + // Get the HOB list. If it is not present, then ASSERT.
> + //
> + GuidHob.Raw = GetHobList ();
> + if (GuidHob.Raw != NULL) {
> + if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid,
> GuidHob.Raw)) != NULL) {
> + mPlatformInfo = GET_GUID_HOB_DATA (GuidHob.Guid);
> + }
> + }
> +
> +
> + PrepareSetupInformation();
> + UpdateAdditionalInformation ();
> + UpdatePlatformInformation();
> + UpdateCPUInformation();
> + IdeDataFilter();
> + mSetupInfoDone = TRUE;
> +
> + return;
> +}
> +
> +
> +#define EFI_SECURE_BOOT_MODE_NAME L"SecureBoot"
> +
> +VOID
> +CheckSystemConfigLoad(SYSTEM_CONFIGURATION *SystemConfigPtr)
> +{
> + EFI_STATUS Status;
> + UINT8 SecureBoot;
> + UINTN DataSize;
> +
> +
> + DataSize = sizeof(SecureBoot);
> + Status = gRT->GetVariable (
> + EFI_SECURE_BOOT_MODE_NAME,
> + &gEfiGlobalVariableGuid,
> + NULL,
> + &DataSize,
> + &SecureBoot
> + );
> +
> + if (EFI_ERROR(Status)) {
> + SystemConfigPtr->SecureBoot = 0;
> + } else {
> + SystemConfigPtr->SecureBoot = SecureBoot;
> + }
> +}
> +
> +
> +//
> +// "SecureBootEnable" variable for the Secure boot feature enable/disable.
> +//
> +#define EFI_SECURE_BOOT_ENABLE_NAME L"SecureBootEnable"
> +extern EFI_GUID gEfiSecureBootEnableDisableGuid;
> +
> +
> +VOID
> +CheckSystemConfigSave(SYSTEM_CONFIGURATION *SystemConfigPtr)
> +{
> + EFI_STATUS Status;
> + UINT8 SecureBootCfg;
> + BOOLEAN SecureBootNotFound;
> + UINTN DataSize;
> +
> +
> + //
> + // Secure Boot configuration changes
> + //
> + DataSize = sizeof(SecureBootCfg);
> + SecureBootNotFound = FALSE;
> + Status = gRT->GetVariable (
> + EFI_SECURE_BOOT_ENABLE_NAME,
> + &gEfiSecureBootEnableDisableGuid,
> + NULL,
> + &DataSize,
> + &SecureBootCfg
> + );
> +
> + if (EFI_ERROR(Status)) {
> + SecureBootNotFound = TRUE;
> + }
> + if (SecureBootNotFound) {
> + Status = gRT->GetVariable (
> + EFI_SECURE_BOOT_ENABLE_NAME,
> + &gEfiSecureBootEnableDisableGuid,
> + NULL,
> + &DataSize,
> + &SecureBootCfg
> + );
> + ASSERT_EFI_ERROR(Status);
> + }
> + if ((SecureBootCfg) != SystemConfigPtr->SecureBoot) {
> + SecureBootCfg = !SecureBootCfg;
> + Status = gRT->SetVariable (
> + EFI_SECURE_BOOT_ENABLE_NAME,
> + &gEfiSecureBootEnableDisableGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + sizeof (UINT8),
> + &SecureBootCfg
> + );
> + }
> +
> +}
> +
> +VOID
> +ConfirmSecureBootTest()
> +{
> +
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SouthClusterConfig.
> vfi
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SouthClusterConfig.
> vfi
> new file mode 100644
> index 0000000000..f7ed978c8b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SouthClusterConfig.
> vfi
> @@ -0,0 +1,933 @@
> +// /** @file
> +//
> +// Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +//
> +
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +//
> +
> +//
> +//
> +//
> +// Module Name:
> +//
> +// SourthClusterConfig.vfi
> +//
> +// Abstract:
> +//
> +// Driver Setup formset.
> +//
> +//Revision History:
> +// ------------------------------------------------------------------------------
> +// Rev Date<MM/DD/YYYY> Name Description
> +// ------------------------------------------------------------------------------
> +
> +// **/
> +
> +//
> +// South Cluster Configuration Form
> +//
> +
> +form formid = SOUTH_CLUSTER_FORM_ID,
> + title = STRING_TOKEN(STR_SOUTH_CLUSTER_TITLE);
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + //
> + // Jump to PCIe Configuration Form
> + //
> + goto PCIE_DEVICE_OPTIONS_FORM_ID,
> + prompt = STRING_TOKEN(STR_PCIE_OPTIONS_FORM_TITLE),
> + help = STRING_TOKEN(STR_PCIE_OPTIONS_FORM_HELP);
> +
> + //
> + // Jump to USB Configuration Form
> + //
> + goto USB_OPTIONS_FORM_ID,
> + prompt = STRING_TOKEN(STR_USB_OPTIONS_FORM_TITLE),
> + help = STRING_TOKEN(STR_USB_OPTIONS_FORM_HELP);
> + //
> + // Jump to Azalia Configuration Form
> + //
> + goto AZALIA_OPTIONS_FORM_ID,
> + prompt = STRING_TOKEN(STR_AZALIA_OPTIONS_FORM_TITLE),
> + help = STRING_TOKEN(STR_AZALIA_OPTIONS_FORM_HELP);
> +
> + //
> + // Jump to Drive Configuration Form
> + //
> + goto DRIVE_CONFIGURATION_ID,
> + prompt = STRING_TOKEN(STR_IDE_FORM_TITLE),
> + help = STRING_TOKEN(STR_IDE_FORM_HELP);
> + //
> + // Jump to LAN Configuration Form
> + //
> +
> + //
> + // Jump to LPSS Configuration Form
> + //
> + goto LPSS_CONFIGURATION_ID,
> + prompt = STRING_TOKEN(STR_LPSS_SCC_FORM_TITLE),
> + help = STRING_TOKEN(STR_LPSS_SCC_FORM_HELP);
> +
> + //
> + // Jump to Misc Configuration Form
> + //
> + goto MISC_OPTIONS_FORM_ID,
> + prompt = STRING_TOKEN(STR_MISC_OPTION_FORM_TITLE),
> + help = STRING_TOKEN(STR_MISC_OPTION_FORM_HELP);
> +endform;
> +
> +form formid = PCIE_DEVICE_OPTIONS_FORM_ID,
> +
> + title = STRING_TOKEN(STR_PCIE_OPTIONS_FORM_TITLE);
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + oneof varid = Setup.PcieRootPortSpeed[0],
> + prompt = STRING_TOKEN (STR_PCIE_SPEED_PROMPT0),
> + help = STRING_TOKEN (STR_PCIE_SPEED_HELP),
> + option text = STRING_TOKEN (STR_AUTO), value = 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_GEN1), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_GEN2), value = 2, flags =
> RESET_REQUIRED;
> + endoneof;
> + oneof varid = Setup.PcieRootPortSpeed[1],
> + prompt = STRING_TOKEN (STR_PCIE_SPEED_PROMPT1),
> + help = STRING_TOKEN (STR_PCIE_SPEED_HELP),
> + option text = STRING_TOKEN (STR_AUTO), value = 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_GEN1), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_GEN2), value = 2, flags =
> RESET_REQUIRED;
> + endoneof;
> + oneof varid = Setup.PcieRootPortSpeed[2],
> + prompt = STRING_TOKEN (STR_PCIE_SPEED_PROMPT2),
> + help = STRING_TOKEN (STR_PCIE_SPEED_HELP),
> + option text = STRING_TOKEN (STR_AUTO), value = 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_GEN1), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_GEN2), value = 2, flags =
> RESET_REQUIRED;
> + endoneof;
> + oneof varid = Setup.PcieRootPortSpeed[3],
> + prompt = STRING_TOKEN (STR_PCIE_SPEED_PROMPT3),
> + help = STRING_TOKEN (STR_PCIE_SPEED_HELP),
> + option text = STRING_TOKEN (STR_AUTO), value = 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_GEN1), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_GEN2), value = 2, flags =
> RESET_REQUIRED;
> + endoneof;
> + //
> + //PCIe Port
> + //
> + oneof varid = Setup.IchPciExp[0],
> + prompt = STRING_TOKEN(STR_ICH_PCIERP1_PROMPT),
> + help = STRING_TOKEN(STR_ICH_PCIERP_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> +
> + suppressif ideqval Setup.IchPciExp[0] == 0x0;
> + oneof varid = Setup.IchPciExp[1],
> + prompt = STRING_TOKEN(STR_ICH_PCIERP2_PROMPT),
> + help = STRING_TOKEN(STR_ICH_PCIERP_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags= DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + suppressif NOT ideqval Setup.IchPciExp[0] == 0x0;
> + text
> + help = STRING_TOKEN(STR_ICH_PCIERP_HELP),
> + text = STRING_TOKEN(STR_ICH_PCIERP2_PROMPT),
> + text = STRING_TOKEN(STR_ICH_PCIERP_DISABLE_HELP),
> + flags = 0,
> + key = 0;
> + endif;
> +
> + suppressif ideqval Setup.IchPciExp[0] == 0x0;
> + oneof varid = Setup.IchPciExp[2],
> + prompt = STRING_TOKEN(STR_ICH_PCIERP3_PROMPT),
> + help = STRING_TOKEN(STR_ICH_PCIERP_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + suppressif NOT ideqval Setup.IchPciExp[0] == 0x0;
> + text
> + help = STRING_TOKEN(STR_ICH_PCIERP_HELP),
> + text = STRING_TOKEN(STR_ICH_PCIERP3_PROMPT),
> + text = STRING_TOKEN(STR_ICH_PCIERP_DISABLE_HELP),
> + flags = 0,
> + key = 0;
> + endif;
> +
> + suppressif ideqval Setup.IchPciExp[0] == 0x0;
> + oneof varid = Setup.IchPciExp[3],
> + prompt = STRING_TOKEN(STR_ICH_PCIERP4_PROMPT),
> + help = STRING_TOKEN(STR_ICH_PCIERP_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags= DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags= 0 |
> RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + suppressif NOT ideqval Setup.IchPciExp[0] == 0x0;
> + text
> + help = STRING_TOKEN(STR_ICH_PCIERP_HELP),
> + text = STRING_TOKEN(STR_ICH_PCIERP4_PROMPT),
> + text = STRING_TOKEN(STR_ICH_PCIERP_DISABLE_HELP),
> + flags = 0,
> + key = 0;
> + endif;
> +
> +
> +endform;
> +
> +form formid = USB_OPTIONS_FORM_ID,
> +
> + title = STRING_TOKEN(STR_USB_OPTIONS_FORM_TITLE);
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + oneof varid = Setup.UsbAutoMode,
> + questionid = 0x123A,
> + prompt = STRING_TOKEN(STR_USB_AUTO_MODE_PROMPT),
> + help = STRING_TOKEN(STR_USB_AUTO_MODE_HELP),
> + flags = INTERACTIVE,
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + //
> + //XHCI support
> + //
> + grayoutif ideqval Setup.UsbAutoMode == 0x1;
> + grayoutif ideqval Setup.PchUsb20 == 0x1;
> + oneof varid = Setup.UsbXhciSupport,
> + questionid = 0x123B,
> + prompt = STRING_TOKEN(STR_USB_XHCI_SUPPORT_PROMPT),
> + help = STRING_TOKEN(STR_USB_XHCI_SUPPORT_HELP),
> + flags = INTERACTIVE,
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT
> | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + suppressif ideqval Setup.UsbXhciSupport == 0x0;
> + oneof varid = Setup.Hsic0,
> + prompt = STRING_TOKEN(STR_USB_HSIC_0_PROMPT),
> + help = STRING_TOKEN(STR_USB_HSIC_0_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + oneof varid = Setup.PchUsb30Mode,
> + prompt = STRING_TOKEN(STR_PCH_USB30_MODE_PROMPT),
> + help = STRING_TOKEN(STR_PCH_USB30_MODE_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT
> | MANUFACTURING |RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.UsbXhciLpmSupport,
> + prompt = STRING_TOKEN(STR_USB_XHCI_LPM_SUPPORT_PROMPT),
> + help = STRING_TOKEN(STR_USB_XHCI_LPM_SUPPORT_HELP),
> +
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT
> | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> +
> + endoneof;
> + endif;
> + endif;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + oneof varid = Setup.PchUsbOtg,
> + prompt = STRING_TOKEN(STR_PCH_USB_OTG_PROMPT),
> + help = STRING_TOKEN(STR_PCH_USB_OTG_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT |
> MANUFACTURING |RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_PCI_MODE_STRING), value = 1, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.PchUsbVbusOn,
> + prompt = STRING_TOKEN(STR_PCH_USB_VBUS_PROMPT),
> + help = STRING_TOKEN(STR_PCH_USB_VBUS_HELP),
> + option text = STRING_TOKEN(STR_OFF), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ON), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_AUTO), value = 2, flags =
> RESET_REQUIRED;
> + endoneof;
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + //
> + //EHCI support
> + //
> + grayoutif ideqval Setup.UsbAutoMode == 0x1;
> + grayoutif ideqval Setup.UsbXhciSupport == 0x1;
> + oneof varid = Setup.PchUsb20,
> + questionid = 0x123C,
> + prompt = STRING_TOKEN(STR_PCH_USB21_PROMPT),
> + help = STRING_TOKEN(STR_PCH_USB2_HELP),
> + flags = INTERACTIVE,
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value= 0, flags= DEFAULT |
> MANUFACTURING |RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.PchUsbRmh,
> + prompt = STRING_TOKEN(STR_PCH_USBRMH_PROMPT),
> + help = STRING_TOKEN(STR_PCH_USBRMH_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT
> | MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.PchEhciDebug,
> + prompt = STRING_TOKEN(STR_PCH_USB_EHCIDEBUG_PROMPT),
> + help = STRING_TOKEN(STR_PCH_USB_EHCIDEBUG_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT
> | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + suppressif TRUE;
> + oneof varid = Setup.EhciPllCfgEnable,
> + prompt = STRING_TOKEN(STR_EHCI_PLL_CFG_PROMPT),
> + help = STRING_TOKEN(STR_EHCI_PLL_CFG_RTD3_DIS_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT
> | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + endoneof;
> + endif;
> + endif;
> +
> + //
> + // Usb ports per-port disable control enable
> + //
> + oneof varid = Setup.PchUsbPerPortCtl,
> + prompt = STRING_TOKEN(STR_PCH_USB_PER_PORT_PROMPT),
> + help = STRING_TOKEN(STR_PCH_USB_PER_PORT_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + suppressif ideqval Setup.PchUsbPerPortCtl == 0x0;
> + oneof varid = Setup.PchUsbPort[0],
> + prompt = STRING_TOKEN(STR_PCH_USB_PORT0_PROMPT),
> + help = STRING_TOKEN(STR_PCH_USB_PORT_DIS_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.PchUsbPort[1],
> + prompt = STRING_TOKEN(STR_PCH_USB_PORT1_PROMPT),
> + help = STRING_TOKEN(STR_PCH_USB_PORT_DIS_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.PchUsbPort[2],
> + prompt = STRING_TOKEN(STR_PCH_USB_PORT2_PROMPT),
> + help = STRING_TOKEN(STR_PCH_USB_PORT_DIS_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.PchUsbPort[3],
> + prompt = STRING_TOKEN(STR_PCH_USB_PORT3_PROMPT),
> + help = STRING_TOKEN(STR_PCH_USB_PORT_DIS_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> +
> + endif;
> +
> +endform;
> +
> +//
> +// SATA Controller
> +//
> +form formid = DRIVE_CONFIGURATION_ID,
> +
> + title = STRING_TOKEN(STR_IDE_FORM_TITLE);
> +
> + //
> + // Title on Drive Configuration Page
> + //
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_IDE_FORM_TITLE),
> + text = STRING_TOKEN(STR_NULL_STRING),
> + flags = 0,
> + key = 0;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + subtitle text = STRING_TOKEN(STR_CHIPSET_SATA_STRING);
> +
> + oneof varid = Setup.Sata,
> + prompt = STRING_TOKEN(STR_SATA_PROMPT),
> + help = STRING_TOKEN(STR_SATA_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.SataTestMode,
> + prompt = STRING_TOKEN(STR_SATA_TEST_MODE_PROMPT),
> + help = STRING_TOKEN(STR_SATA_TEST_MODE_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + suppressif ideqval Setup.Sata == 0x00;
> + oneof varid = Setup.SataType,
> + prompt = STRING_TOKEN(STR_SATA_TYPE_PROMPT),
> + help = STRING_TOKEN(STR_SATA_TYPE_HELP1),
> + option text = STRING_TOKEN(STR_SATA_IDE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_SATA_AHCI), value = 1, flags =
> DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_SATA0_STRING),
> + text = STRING_TOKEN(STR_SATA0_NAME),
> + flags = 0,
> + key = 0;
> +
> + text
> + help = STRING_TOKEN(STR_NULL_STRING),
> + text = STRING_TOKEN(STR_SATA1_STRING),
> + text = STRING_TOKEN(STR_SATA1_NAME),
> + flags = 0,
> + key = 0;
> +
> + suppressif ideqval Setup.SataType == 0x0;
> + oneof varid = Setup.Sata0HotPlugCap,
> + prompt = STRING_TOKEN(STR_SATA0_HOTPLUG_CAP_PROMPT),
> + help = STRING_TOKEN(STR_SATA_HOTPLUG_CAP_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value= 1, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.Sata1HotPlugCap,
> + prompt = STRING_TOKEN(STR_SATA1_HOTPLUG_CAP_PROMPT),
> + help = STRING_TOKEN(STR_SATA_HOTPLUG_CAP_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value= 1, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + endif; //SATA enable
> +
> +endform;
> +
> +form formid = LPSS_CONFIGURATION_ID,
> +
> + title = STRING_TOKEN(STR_LPSS_SCC_FORM_TITLE);
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + oneof varid = Setup.LpssPciModeEnabled,
> + prompt = STRING_TOKEN(STR_LPSS_PCI_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_PCI_HELP),
> + option text = STRING_TOKEN(STR_ACPI_MODE), value=0, flags=DEFAULT
> | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_PCI_MODE), value=1, flags=0|
> RESET_REQUIRED;
> + endoneof;
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + subtitle text = STRING_TOKEN(STR_SCC_SETTING_SUBTITLE);
> + oneof varid = Setup.eMMCBootMode,
> + prompt = STRING_TOKEN(STR_EMMC_BOOT_PROMPT),
> + help = STRING_TOKEN(STR_EMMC_BOOT_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_AUTO_DETECT), value=1,
> flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC_BOOT_41), value=2, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC_BOOT_45), value=3, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> +
> +
> +
> + oneof varid = Setup.SecureErase,
> + questionid = 0x1240,
> + prompt = STRING_TOKEN(STR_SECURE_ERASE_PROMPT),
> + help = STRING_TOKEN(STR_SECURE_ERASE_HELP),
> + flags = INTERACTIVE,
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags= DEFAULT
> |MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> RESET_REQUIRED;
> + endoneof;
> +
> +
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +grayoutif NOT ideqval Setup.eMMCBootMode == 0x3;
> + oneof varid = Setup.LpsseMMC45Enabled,
> + prompt = STRING_TOKEN(STR_SCC_EMMC45_PROMPT),
> + help = STRING_TOKEN(STR_SCC_EMMC45_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT |
> RESET_REQUIRED;
> + endoneof;
> + oneof varid = Setup.LpsseMMC45DDR50Enabled,
> + prompt = STRING_TOKEN(STR_SCC_EMMC45_DDR50_PROMPT),
> + help = STRING_TOKEN(STR_SCC_EMMC45_DDR50_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT |
> RESET_REQUIRED;
> + endoneof;
> + oneof varid = Setup.LpsseMMC45HS200Enabled,
> + prompt = STRING_TOKEN(STR_SCC_EMMC45_HS200_PROMPT),
> + help = STRING_TOKEN(STR_SCC_EMMC45_HS200_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT|
> RESET_REQUIRED;
> + endoneof;
> +
> + grayoutif ideqval Setup.LpsseMMC45DDR50Enabled == 0x1;
> + oneof varid = Setup.LpsseMMC45RetuneTimerValue,
> + prompt = STRING_TOKEN(STR_SCC_EMMC45_RE_TUNE_TIMER_VALUE),
> + help =
> STRING_TOKEN(STR_SCC_EMMC45_RE_TUNE_TIMER_VALUE_HELP),
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_0), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_1), value =1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_2), value =2, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_3), value =3, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_4), value =4, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_5), value =5, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_6), value =6, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_7), value =7, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_8), value =8, flags =
> MANUFACTURING| DEFAULT|RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_9), value =9, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_10), value =10, flags
> = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_11), value =11, flags
> = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_12), value =12, flags
> = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_13), value =13, flags
> = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_14), value =14, flags
> = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EMMC45_TIMER_15), value =15, flags
> = RESET_REQUIRED;
> + endoneof;
> + endif; // grayoutif ideqval Setup.LpsseMMC45DDR50Enabled == 0x1;
> + endif; // grayoutif NOT ideqval Setup.eMMCBootMode == 0x1;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + oneof varid = Setup.LpssSdioEnabled,
> + prompt = STRING_TOKEN(STR_SCC_SDIO_PROMPT),
> + help = STRING_TOKEN(STR_SCC_SDIO_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.LpssSdcardEnabled,
> + prompt = STRING_TOKEN(STR_SCC_SDCARD_PROMPT),
> + help = STRING_TOKEN(STR_SCC_SDCARD_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> DEFAULT|MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> +
> +grayoutif NOT ideqval Setup.LpssSdcardEnabled == 0x1;
> + grayoutif ideqval Setup.LpssSdCardDDR50Enabled == 0x1;
> + oneof varid = Setup.LpssSdCardSDR25Enabled,
> + prompt = STRING_TOKEN(STR_SCC_SD_SDR25_PROMPT),
> + help = STRING_TOKEN(STR_SCC_SD_SDR25_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> + endif; // grayoutif ideqval Setup.LpsseMMC45DDR50Enabled == 0x1;
> +
> + grayoutif ideqval Setup.LpssSdCardSDR25Enabled == 0x1;
> + oneof varid = Setup.LpssSdCardDDR50Enabled,
> + prompt = STRING_TOKEN(STR_SCC_SD_DDR50_PROMPT),
> + help = STRING_TOKEN(STR_SCC_SD_DDR50_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> + endif; // grayoutif ideqval Setup.LpssSdCardSDR25Enabled == 0x1;
> +
> + oneof varid = Setup.SdCardRemovable,
> + prompt = STRING_TOKEN(STR_SCC_SDCARD_REMOVABILITY),
> + help = STRING_TOKEN(STR_SCC_SDCARD_REMOVABILITY_HELP),
> + option text = STRING_TOKEN(STR_SCC_SDCARD_NON_REMOVABLE),
> value=0, flags=0 | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_SCC_SDCARD_REMOVABLE), value=1,
> flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> +endif; // grayoutif NOT ideqval Setup.LpssSdcardEnabled == 0x1;
> +
> +
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + subtitle text = STRING_TOKEN(STR_LPSS1_SETTING_SUBTITLE);
> +
> + oneof varid = Setup.LpssDma0Enabled,
> + prompt = STRING_TOKEN(STR_LPSS_DMA1_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_DMA1_HELP),
> + flags = INTERACTIVE,
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags= DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + grayoutif ideqval Setup.LpssDma0Enabled == 0x00;
> + oneof varid = Setup.LpssHsuart0Enabled,
> + prompt = STRING_TOKEN(STR_LPSS_HSUART1_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_HSUART1_HELP_ENBDT_DEV_LIST),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags= 0 | DEFAULT
> | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + //Add control flow
> + grayoutif ideqval Setup.LpssHsuart0Enabled == 0x00;
> + oneof varid = Setup.LpssHsuart0FlowControlEnabled,
> + prompt =
> STRING_TOKEN(STR_LPSS_HSUART1_FLOWCONTROL_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_HSUART1_HELP_ENBDT_DEV_LIST),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + grayoutif ideqval Setup.LpssDma0Enabled == 0x00;
> + oneof varid = Setup.LpssHsuart1Enabled,
> + prompt = STRING_TOKEN(STR_LPSS_HSUART2_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_HSUART2_HELP_ENBDT_DEV_LIST),
> + option text = STRING_TOKEN(STR_DISABLE), value=0,
> flags=MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags= 0 | DEFAULT
> | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + //Add control flow
> + grayoutif ideqval Setup.LpssHsuart1Enabled == 0x00;
> + oneof varid = Setup.LpssHsuart1FlowControlEnabled,
> + prompt =
> STRING_TOKEN(STR_LPSS_HSUART2_FLOWCONTROL_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_HSUART1_HELP_ENBDT_DEV_LIST),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> +
> + grayoutif ideqval Setup.LpssDma0Enabled == 0x00;
> + oneof varid = Setup.LpssPwm0Enabled,
> + prompt = STRING_TOKEN(STR_PWM1_PROMPT),
> + help = STRING_TOKEN(STR_PWM1_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0,
> flags=MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags= 0 | DEFAULT
> | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + grayoutif ideqval Setup.LpssDma0Enabled == 0x00;
> + oneof varid = Setup.LpssPwm1Enabled,
> + prompt = STRING_TOKEN(STR_PWM2_PROMPT),
> + help = STRING_TOKEN(STR_PWM2_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0,
> flags=MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags= 0 | DEFAULT
> | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + grayoutif ideqval Setup.LpssDma0Enabled == 0x00;
> + oneof varid = Setup.LpssSpiEnabled,
> + prompt = STRING_TOKEN(STR_LPSS_SPI_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_SPI_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0,
> flags=MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags= 0 |DEFAULT |
> RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + subtitle text = STRING_TOKEN(STR_LPSS2_SETTING_SUBTITLE);
> +
> + oneof varid = Setup.LpssDma1Enabled,
> + prompt = STRING_TOKEN(STR_LPSS_DMA2_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_DMA2_HELP),
> + flags = INTERACTIVE,
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0
> |RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags= DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> +/*
> + grayoutif ideqval Setup.LpssDma1Enabled == 0x00;
> + oneof varid = Setup.LpssI2C0Enabled,
> + prompt = STRING_TOKEN(STR_LPSS_I2C1_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_I2C1_HELP_ENBDT_DEV_LIST),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT
> |RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> +
> + grayoutif ideqval Setup.LpssDma1Enabled == 0x00;
> + oneof varid = Setup.LpssI2C1Enabled,
> + prompt = STRING_TOKEN(STR_LPSS_I2C2_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_I2C2_HELP_ENBDT_DEV_LIST),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + grayoutif ideqval Setup.LpssDma1Enabled == 0x00;
> + oneof varid = Setup.LpssI2C2Enabled,
> + prompt = STRING_TOKEN(STR_LPSS_I2C3_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_I2C3_HELP_ENBDT_DEV_LIST),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + grayoutif ideqval Setup.LpssDma1Enabled == 0x00;
> + oneof varid = Setup.LpssI2C3Enabled,
> + prompt = STRING_TOKEN(STR_LPSS_I2C4_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_I2C4_HELP_ENBDT_DEV_LIST),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + grayoutif ideqval Setup.LpssDma1Enabled == 0x00;
> + oneof varid = Setup.LpssI2C4Enabled,
> + prompt = STRING_TOKEN(STR_LPSS_I2C5_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_I2C5_HELP_ENBDT_DEV_LIST),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +*/
> + grayoutif ideqval Setup.LpssDma1Enabled == 0x00;
> + oneof varid = Setup.LpssI2C5Enabled,
> + prompt = STRING_TOKEN(STR_LPSS_I2C6_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_I2C6_HELP_ENBDT_DEV_LIST),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0
> |RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags= DEFAULT
> |MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + grayoutif ideqval Setup.LpssDma1Enabled == 0x00;
> + oneof varid = Setup.LpssI2C6Enabled,
> + prompt = STRING_TOKEN(STR_LPSS_I2C7_PROMPT),
> + help = STRING_TOKEN(STR_LPSS_I2C7_HELP_ENBDT_DEV_LIST),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0
> |RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags= DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + subtitle text = STRING_TOKEN(STR_I2C_DEVICE_SETTING_SUBTITLE);
> +
> + oneof varid = Setup.I2CTouchAd,
> + prompt = STRING_TOKEN(STR_I2C_TOUCH_PROMPT),
> + help = STRING_TOKEN(STR_I2C_TOUCH_HELP),
> + option text = STRING_TOKEN(STR_AUTO), value=0, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_I2C_FVP), value=0x4B, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_I2C_FFRD), value=0x4A, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + oneof varid = Setup.SAR1,
> + prompt = STRING_TOKEN(STR_SAR_SENSOR_PROMPT),
> + help = STRING_TOKEN(STR_SAR_SENSOR_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING |RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + endoneof;
> +endform;
> +
> +
> +//
> +//LAN Controller
> +//
> +form formid = LAN_OPTIONS_FORM_ID,
> +
> + title = STRING_TOKEN(STR_LAN_OPTIONS_FORM_TITLE);
> +
> + subtitle text = STRING_TOKEN(STR_LAN_OPTIONS_FORM_TITLE);
> +
> + oneof varid = Setup.Lan,
> + prompt = STRING_TOKEN(STR_PCH_LAN_CONTROLLER),
> + help = STRING_TOKEN(STR_PCH_LAN_CONTROLLER_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + suppressif ideqval Setup.Lan == 0;
> + oneof varid = Setup.WakeOnLanS5,
> + prompt = STRING_TOKEN(STR_PCH_LAN_WOL_PROMPT),
> + help = STRING_TOKEN(STR_PCH_LAN_WOL_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.SlpLanLowDc,
> + prompt = STRING_TOKEN(STR_PCH_SLP_LAN_LOW_DC_PROMPT),
> + help = STRING_TOKEN(STR_PCH_SLP_LAN_LOW_DC_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.BootNetwork,
> + prompt = STRING_TOKEN(STR_PCH_PXEROM_CONTROL),
> + help = STRING_TOKEN(STR_PCH_PXEROM_CONTROL_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT |
> MANUFACTURING |RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> +endform;
> +
> +//
> +// Azalia Configuration
> +//
> +form formid = AZALIA_OPTIONS_FORM_ID,
> +
> + title = STRING_TOKEN(STR_AZALIA_OPTIONS_FORM_TITLE);
> +
> + subtitle text = STRING_TOKEN(STR_AZALIA_OPTIONS_FORM_TITLE);
> + oneof varid = Setup.Lpe,
> + prompt = STRING_TOKEN(STR_LPE_PROMPT),
> + help = STRING_TOKEN(STR_LPE_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_LPE_PCI_MODE), value=1, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_LPE_ACPI_MODE), value=2, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> +
> + grayoutif NOT ideqval Setup.Lpe == 0x2;
> + oneof varid = Setup.LpeAudioReportedByDSDT,
> + prompt = STRING_TOKEN(STR_LPE_REPORTED_BY_DSDT_PROMPT),
> + help = STRING_TOKEN(STR_LPE_REPORTED_BY_DSDT_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1,
> flags=RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + suppressif ideqval Setup.AzaliaDs == 0x1;
> + oneof varid = Setup.PchAzalia,
> + prompt = STRING_TOKEN(STR_PCH_AZALIA_PROMPT),
> + help = STRING_TOKEN(STR_PCH_AZALIA_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = 0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + suppressif ideqval Setup.AzaliaDs == 0x0;
> + text
> + help = STRING_TOKEN(STR_PCH_AZALIA_DS_SUPPORT),
> + text = STRING_TOKEN(STR_PCH_AZALIA_PROMPT),
> + text = STRING_TOKEN(STR_ENABLE),
> + flags = 0,
> + key = 0;
> + endif;
> +
> + suppressif ideqval Setup.PchAzalia == 0x0;
> + oneof varid = Setup.AzaliaVCiEnable,
> + prompt = STRING_TOKEN(STR_AZALIA_VC_PROMPT),
> + help = STRING_TOKEN(STR_AZALIA_VC_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + suppressif ideqval Setup.PchAzalia == 0x0;
> + oneof varid = Setup.AzaliaDs,
> + prompt = STRING_TOKEN(STR_AZALIA_DS_PROMPT),
> + help = STRING_TOKEN(STR_AZALIA_DS_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + suppressif ideqval Setup.PchAzalia == 0x0;
> + oneof varid = Setup.AzaliaPme,
> + prompt = STRING_TOKEN(STR_AZALIA_PME_PROMPT),
> + help = STRING_TOKEN(STR_AZALIA_PME_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.HdmiCodec,
> + prompt = STRING_TOKEN(STR_HDMI_CODEC_PROMPT),
> + help = STRING_TOKEN(STR_HDMI_CODEC_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> +endform;
> +
> +//
> +// Misc Configuration
> +//
> +form formid = MISC_OPTIONS_FORM_ID,
> +
> + title = STRING_TOKEN(STR_MISC_OPTION_FORM_TITLE);
> +
> + subtitle text = STRING_TOKEN(STR_MISC_OPTION_FORM_TITLE);
> + //
> + // HPET Disable/Enable
> + //
> + oneof varid = Setup.Hpet,
> + prompt = STRING_TOKEN(STR_HPET_PROMPT),
> + help = STRING_TOKEN(STR_HPET_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0x00,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=0x01, flags=DEFAULT |
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.StateAfterG3,
> + prompt = STRING_TOKEN(STR_STATE_AFTER_G3),
> + help = STRING_TOKEN(STR_STATE_AFTER_G3_HELP),
> + option text = STRING_TOKEN(STR_S0_AFTER_G3_STRING), value = 0,
> flags = DEFAULT | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_S5_AFTER_G3_STRING), value = 1,
> flags = MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.EnableClockSpreadSpec,
> + prompt = STRING_TOKEN(STR_CLOCK_SPREAD_SPEC_ENABLE),
> + help = STRING_TOKEN(STR_CLOCK_SPREAD_SPEC_ENABLE_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> +
> + oneof varid = Setup.UartInterface,
> + prompt = STRING_TOKEN(STR_PCH_UART_SELECT),
> + help = STRING_TOKEN(STR_PCH_UART_SELECT_HELP),
> + option text = STRING_TOKEN(STR_UART_SELECT_PCU), value = 0, flags =
> DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_UART_SELECT_SIO), value = 1, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + suppressif ideqval Setup.LpssHsuart0Enabled == 1 OR ideqval
> Setup.UartInterface == 1;
> + oneof varid = Setup.PcuUart1,
> + prompt = STRING_TOKEN(STR_PCU_UART_A),
> + help = STRING_TOKEN(STR_PCU_UART_A_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + oneof varid = Setup.SpiRwProtect,
> + prompt = STRING_TOKEN(STR_PCH_SPI_WP_PROMPT),
> + help = STRING_TOKEN(STR_PCH_SPI_WP_HELP),
> + option text = STRING_TOKEN(STR_PCH_SPI_WP_DISABLE), value = 0,
> flags = DEFAULT | MANUFACTURING |RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_PCH_SPI_WP_ENABLE), value = 1,
> flags = RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.MmioSize,
> + prompt = STRING_TOKEN(STR_MMIO_PROMPT),
> + help = STRING_TOKEN(STR_MMIO_HELP),
> + option text = STRING_TOKEN(STR_MMIO_0_75G_STRING), value = 0,
> flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_MMIO_1G_STRING), value = 1, flags
> = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_MMIO_1_25G_STRING), value = 2,
> flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_MMIO_1_5G_STRING), value = 3,
> flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_MMIO_2G_STRING), value = 4, flags
> = DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.PcieDynamicGating,
> + prompt = STRING_TOKEN(STR_PCIEDYNCLK_PROMPT),
> + help = STRING_TOKEN(STR_PCIEDYNCLK_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT
> | MANUFACTURING |RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.GpioWakeCapability,
> + prompt = STRING_TOKEN(STR_GPIO_WAKE_CAPABILITY_ENABLE),
> + help =
> STRING_TOKEN(STR_GPIO_WAKE_CAPABILITY_ENABLE_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT
> | MANUFACTURING |RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.RtcBattery,
> + prompt = STRING_TOKEN(STR_RTC_BATTERY),
> + help = STRING_TOKEN(STR_RTC_BATTERY_HELP),
> + option text = STRING_TOKEN(STR_RTC_BATTERY_NOT_PRESENT), value
> = 0, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_RTC_BATTERY_PRESENT), value = 1,
> flags = DEFAULT | MANUFACTURING |RESET_REQUIRED;
> + endoneof;
> +
> +endform;
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SystemComponent.
> vfi
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SystemComponent.
> vfi
> new file mode 100644
> index 0000000000..96cf470eaf
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/SystemComponent.
> vfi
> @@ -0,0 +1,81 @@
> +//
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +//
>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +//
>
> +//
> +//
> +//
> +// Module Name:
> +//
> +// SystemComponent.vfr
> +//
> +// Abstract:
> +//
> +// Driver Setup formset.
> +//
> +// Revision History:
> +// ------------------------------------------------------------------------------
> +// Rev Date<MM/DD/YYYY> Name Description
> +// ------------------------------------------------------------------------------
> +
> +// --*/
> +
> +form formid = SYSTEM_COMPONENT_FORM_ID,
> +
> + title = STRING_TOKEN(STR_SYSTEM_COMPONENT_TITLE);
> +/*
> + oneof varid = Setup.CRIDSettings,
> + prompt = STRING_TOKEN(STR_CRID_PROMPT),
> + help = STRING_TOKEN(STR_CRID_SETTING_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> MANUFACTURING | DEFAULT | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_CRID_0_STRING), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_CRID_1_STRING), value = 2, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_CRID_2_STRING), value = 3, flags =
> RESET_REQUIRED;
> + endoneof;
> +*/
> +
> + subtitle text = STRING_TOKEN(STR_PNP_CONFIGURATION_TITLE);
> + oneof varid = Setup.PnpSettings,
> + prompt = STRING_TOKEN(STR_PNP_SETTING_PROMPT),
> + help = STRING_TOKEN(STR_PNP_SETTING_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> +#if (PNP_DEBUG == 1)
> + option text = STRING_TOKEN(STR_PNP_POWER_STRING), value = 1,
> flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_PNP_PERFORMANCE_STRING), value
> = 2, flags = RESET_REQUIRED;
> +#endif
> + option text =
> STRING_TOKEN(STR_PNP_POWER_PERFORMANCE_STRING), value = 3, flags
> = DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + option text =
> STRING_TOKEN(STR_PNP_POWER_PERFORMANCE_STRING_A0), value = 4,
> flags = 0 | RESET_REQUIRED;
> + option text =
> STRING_TOKEN(STR_PNP_POWER_PERFORMANCE_STRING_B0), value = 5,
> flags = 0 | RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.CfioPnpSettings,
> + prompt = STRING_TOKEN(STR_CFIO_PNP_SETTING_PROMPT),
> + help = STRING_TOKEN(STR_CFIO_PNP_SETTING_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> MANUFACTURING | DEFAULT | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = 0 |
> RESET_REQUIRED;
> + endoneof;
> + oneof varid = Setup.TristateLpc,
> + prompt = STRING_TOKEN(STR_TRISTATE_LPC_PROMPT),
> + help = STRING_TOKEN(STR_TRISTATE_LPC_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> MANUFACTURING | DEFAULT | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = 0 |
> RESET_REQUIRED;
> + endoneof;
> +
> +
> +
> +
> +
> +
> + oneof varid = Setup.PchFSAOn,
> + prompt = STRING_TOKEN(STR_PCH_FSA_PROMPT),
> + help = STRING_TOKEN(STR_PCH_FSA_HELP),
> + option text = STRING_TOKEN(STR_OFF), value = 0, flags = DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ON), value = 1, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> +
> +
> +endform;
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Thermal.vfi
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Thermal.vfi
> new file mode 100644
> index 0000000000..63063a73b2
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Thermal.vfi
> @@ -0,0 +1,106 @@
> +//
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +//
>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +//
>
> +//
> +//
> +//
> +// Module Name:
> +//
> +// DPTF.vfr
> +//
> +// Abstract:
> +//
> +// Driver Setup formset.
> +//
> +// Revision History:
> +// ------------------------------------------------------------------------------
> +// Rev Date<MM/DD/YYYY> Name Description
> +// ------------------------------------------------------------------------------
> +
> +// --*/
> +
> +form formid = THERMAL_FORM_ID,
> +
> + title = STRING_TOKEN(STR_THERMAL_TITLE);
> +
> + subtitle text = STRING_TOKEN(STR_THERMAL_CONFIGURATION);
> + oneof varid = Setup.CriticalThermalTripPoint,
> + prompt =
> STRING_TOKEN(STR_ACPI_CRITICAL_THERMAL_TRIP_POINT),
> + help =
> STRING_TOKEN(STR_ACPI_CRITICAL_THERMAL_TRIP_POINT_HELP),
> + option text = STRING_TOKEN (STR_85_C), value = 85, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_87_C), value = 87, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_90_C), value = 90, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_105_C), value = 105, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_110_C), value = 110, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_200_C), value = 200, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + oneof varid = Setup.PassiveThermalTripPoint,
> + prompt = STRING_TOKEN
> (STR_ACPI_PASSIVE_THERMAL_TRIP_POINT),
> + help = STRING_TOKEN
> (STR_ACPI_PASSIVE_THERMAL_TRIP_POINT_HELP),
> + option text = STRING_TOKEN (STR_85_C), value = 85, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_87_C), value = 87, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_90_C), value = 90, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_100_C), value = 100, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_105_C), value = 105, flags=0 |
> RESET_REQUIRED;
> + option text = STRING_TOKEN (STR_180_C), value = 180, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + suppressif TRUE;
> + numeric varid = Setup.PassiveTc1Value,
> + prompt = STRING_TOKEN (STR_ACPI_PASSIVE_TC1_VALUE),
> + help = STRING_TOKEN (STR_ACPI_PASSIVE_TC1_VALUE_HELP),
> + flags = 0 | RESET_REQUIRED,
> + minimum = 1,
> + maximum = 16,
> + step = 1,
> + default = 1,
> + endnumeric;
> +
> + numeric varid = Setup.PassiveTc2Value,
> + prompt = STRING_TOKEN (STR_ACPI_PASSIVE_TC2_VALUE),
> + help = STRING_TOKEN (STR_ACPI_PASSIVE_TC2_VALUE_HELP),
> + flags = 0 | RESET_REQUIRED,
> + minimum = 1,
> + maximum = 16,
> + step = 1,
> + default = 5,
> + endnumeric;
> +
> + numeric varid = Setup.PassiveTspValue,
> + prompt = STRING_TOKEN (STR_ACPI_PASSIVE_TSP_VALUE),
> + help = STRING_TOKEN (STR_ACPI_PASSIVE_TSP_VALUE_HELP),
> + flags = 0 | RESET_REQUIRED,
> + minimum = 2,
> + maximum = 50,
> + step = 2,
> + default = 50,
> + endnumeric;
> + endif;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + oneof varid = Setup.DisableActiveTripPoints,
> + prompt = STRING_TOKEN(STR_DATP_PROMPT),
> + help = STRING_TOKEN(STR_DATP_HELP),
> + option text = STRING_TOKEN(STR_DISABLED), value = 0, flags =
> DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLED), value = 1, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + suppressif TRUE;
> + oneof varid = Setup.EnableDigitalThermalSensor,
> + prompt = STRING_TOKEN(STR_DTS_PROMPT),
> + help = STRING_TOKEN(STR_DTS_PROMPT_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =
> MANUFACTURING |RESET_REQUIRED |DEFAULT;
> + endoneof;
> + endif;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> +
> +
> +endform;
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/UnCore.vfi
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/UnCore.vfi
> new file mode 100644
> index 0000000000..ed6bb3a00b
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/UnCore.vfi
> @@ -0,0 +1,235 @@
> +//
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +//
>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +//
>
> +//
> +//
> +//
> +// Module Name:
> +//
> +// UncoreConfiguration.vfi
> +//
> +// Abstract:
> +//
> +// Driver Setup formset.
> +//
> +
> +
> +// --*/
> +
> +form formid = UNCORE_FORM_ID,
> + title = STRING_TOKEN(STR_UNCORE_CONFIGURATION_TITLE);
> +
> + subtitle text = STRING_TOKEN(STR_GOP_TITLE);
> +
> + oneof varid = Setup.GOPEnable,
> + prompt = STRING_TOKEN(STR_GOP_VBIOS_SWITCH),
> + help = STRING_TOKEN(STR_GOP_VBIOS_SWITCH_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value =1, flags =
> MANUFACTURING | DEFAULT | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.GOPBrightnessLevel,
> + prompt = STRING_TOKEN(STR_GOP_BRIGHTNESS_LEVEL),
> + help = STRING_TOKEN(STR_GOP_BRIGHTNESS_LEVEL_HELP),
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_20), value =2, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_40), value =3, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_60), value =4, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_80), value =5, flags =
> MANUFACTURING| DEFAULT| RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_100), value =6, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_120), value =7, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_140), value =8, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_160), value =9, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_180), value =10, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_200), value =11, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_220), value =12, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_240), value =13, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_GOP_BRIGHT_255), value =14, flags =
> RESET_REQUIRED;
> + endoneof;
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + subtitle text = STRING_TOKEN(STR_IGD_TITLE);
> +
> + suppressif ideqval Setup.PrimaryVideoAdaptor == 0x2;
> + oneof varid = Setup.Igd,
> + prompt = STRING_TOKEN (STR_IGD_PROMPT),
> + help = STRING_TOKEN (STR_IGD_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> + oneof varid = Setup.PrimaryVideoAdaptor,
> + prompt = STRING_TOKEN(STR_PRIMARY_DISPLAY),
> + help = STRING_TOKEN(STR_PRIMARY_DISPLAY_HELP),
> + option text = STRING_TOKEN(STR_AUTOMATIC), value = 3, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_IGD_STRING), value = 0, flags =
> DEFAULT |MANUFACTURING |RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_PCI_STRING), value = 2, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> +
> + oneof varid = Setup.PavpMode,
> + prompt = STRING_TOKEN(STR_PAVC_PROMPT),
> + help = STRING_TOKEN(STR_PAVC_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_PAVP_LITE_MODE), value = 1, flags =
> MANUFACTURING | DEFAULT | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_PAVP_SERPENT_MODE), value = 2,
> flags = RESET_REQUIRED;
> + endoneof;
> +
> +
> + oneof varid = Setup.GTTSize,
> + prompt = STRING_TOKEN(STR_GTT_SIZE),
> + help = STRING_TOKEN(STR_GTT_SIZE_HELP),
> + option text = STRING_TOKEN(GTT_SIZE_1MB), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(GTT_SIZE_2MB), value = 2, flags = DEFAULT
> | MANUFACTURING | RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.IgdApertureSize,
> + prompt = STRING_TOKEN(STR_APERTURE_SIZE),
> + help = STRING_TOKEN(STR_APERTURE_SIZE_HELP),
> + option text = STRING_TOKEN(APERTURE_SIZE_128MB), value = 1, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(APERTURE_SIZE_256MB), value = 2, flags =
> DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(APERTURE_SIZE_512MB), value = 3, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.IgdDvmt50PreAlloc,
> + prompt = STRING_TOKEN(STR_DVMT50_PRE_ALLOC),
> + help = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_HELP),
> +// option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_32M), value =
> 1, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_64M), value = 2,
> flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_96M), value = 3,
> flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_128M), value =
> 4, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_160M), value =
> 5, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_192M), value =
> 6, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_224M), value =
> 7, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_256M), value =
> 8, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_288M), value =
> 9, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_320M), value =
> 10, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_352M), value =
> 11, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_384M), value =
> 12, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_416M), value =
> 13, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_448M), value =
> 14, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_480M), value =
> 15, flags = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_512M), value =
> 16, flags = RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.IgdDvmt50TotalAlloc,
> + prompt = STRING_TOKEN(STR_DVMT50_DVMT ),
> + help = STRING_TOKEN(STR_DVMT50_DVMT_HELP),
> + option text = STRING_TOKEN(STR_DVMT50_ALLOC_128), value = 1, flags
> = RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_ALLOC_256), value = 2, flags
> = DEFAULT | MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DVMT50_ALLOC_MAX), value = 3,
> flags = RESET_REQUIRED;
> + endoneof;
> +
> + //
> + //Igd Thermal
> + //
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> +
> + subtitle text = STRING_TOKEN(STR_IGD_LCD_CONTROL);
> +
> + oneof varid = Setup.LidStatus,
> + prompt = STRING_TOKEN(STR_FORCE_LID_STATUS_PROMPT),
> + help = STRING_TOKEN(STR_FORCE_LID_STATUS_ENBDT_HELP),
> + option text = STRING_TOKEN(STR_LID_STATUS__OFF_PROMPT), value =
> 0, flags = 0 | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_LID_STATUS__ON_PROMPT), value =
> 1, flags = 0 | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_LID_STATUS__AUTO_PROMPT), value
> = 2, flags = MANUFACTURING| DEFAULT| RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.IgdLcdIBia,
> + prompt = STRING_TOKEN(STR_VIDEO_LCD_IBIA),
> + help = STRING_TOKEN(STR_VIDEO_LCD_IBIAHLP),
> + option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAA), value = 0, flags
> =MANUFACTURING| DEFAULT| RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAD), value = 1, flags =
> 0| RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAL1), value = 2, flags =
> 0| RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAL2), value = 3, flags =
> 0| RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAL3), value = 4, flags =
> 0| RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAL4), value = 5, flags =
> 0| RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAL5), value = 6, flags =
> 0| RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.AlsEnable,
> + prompt = STRING_TOKEN (STR_ACPI_ALS_ENABLE),
> + help = STRING_TOKEN (STR_ACPI_ALS_ENABLE_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT |
> MANUFACTURING | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ENABLE), value=1, flags=0 |
> RESET_REQUIRED;
> + endoneof;
> +
> +
> + oneof varid = Setup.IgdFlatPanel,
> + prompt = STRING_TOKEN(STR_IGD_FLAT_PANEL_PROMPT),
> + help = STRING_TOKEN(STR_IGD_FLAT_PANEL_HELP),
> + option text = STRING_TOKEN(STR_AUTOMATIC), value=0x00,
> flags=DEFAULT | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_640X480), value=0x01,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_800X600), value=0x02,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_1024X768), value=0x03,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_1280X1024), value=0x04,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_1366X768), value=0x05,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_1680X1050), value=0x06,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_1920X1200), value=0x07,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_1280X800), value=0x08,
> flags=RESET_REQUIRED;
> + endoneof;
> +
> + oneof varid = Setup.BootDisplayDevice,
> + prompt = STRING_TOKEN(STR_BOOT_DISPLAY_DEVICE_PROMPT),
> + help = STRING_TOKEN(STR_BOOT_DISPLAY_DEVICE_HELP),
> + option text = STRING_TOKEN(STR_AUTOMATIC), value=0x00,
> flags=DEFAULT | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_VGAPORT), value=0x01,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_HDMIPORTB), value=0x02,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DPPORTB), value=0x03,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DPPORTC), value=0x04,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_EDPPORTC), value=0x05,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DSIPORTA), value=0x06,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DSIPORTC), value=0x07,
> flags=RESET_REQUIRED;
> +
> + endoneof;
> + //
> + //Pannel Scaling
> + //
> + oneof varid = Setup.PanelScaling,
> + prompt = STRING_TOKEN(STR_PANNEL_SCALING_PROMPT),
> + help = STRING_TOKEN(STR_PANNEL_SCALING_HELP),
> + option text = STRING_TOKEN(STR_AUTOMATIC), value=0x00,
> flags=DEFAULT | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_PANNEL_SCALING_STRETCH),
> value=0x01, flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_PANNEL_SCALING_CENTER),
> value=0x02, flags=RESET_REQUIRED;
> + endoneof;
> +
> + //
> + //GMCH BLC Control
> + //
> + oneof varid = Setup.IgdLcdIGmchBlc,
> + prompt = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC_PROMPT),
> + help = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC_HELP),
> + option text = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC1), value=0x00,
> flags=DEFAULT | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC2), value=0x01,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC3), value=0x02,
> flags=RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC4), value=0x03,
> flags=RESET_REQUIRED;
> + endoneof;
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + //
> + //ISP Configuration
> + //
> + subtitle text = STRING_TOKEN(STR_ISP_CONFIGURATION_TITLE);
> +
> + oneof varid = Setup.ISPEn,
> + prompt = STRING_TOKEN(STR_ISP_ENABLED),
> + help = STRING_TOKEN(STR_ISP_ENABLED_HELP),
> + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT |
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + endoneof;
> +
> + grayoutif ideqval Setup.ISPEn == 0;
> + oneof varid = Setup.ISPDevSel,
> + prompt = STRING_TOKEN (STR_ISP_PCICONFIGURATION_TITLE),
> + help = STRING_TOKEN (STR_ISP_PCICONFIGURATION_HELP),
> + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =
> RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ISP_PCICONFIG_B0D2F0_TITLE),
> value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
> + option text = STRING_TOKEN(STR_ISP_PCICONFIG_B0D3F0_TITLE),
> value = 2, flags = RESET_REQUIRED;
> + endoneof;
> + endif;
> +
> +endform;
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/UqiList.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/UqiList.uni
> new file mode 100644
> index 0000000000..504539a02f
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/UqiList.uni
> @@ -0,0 +1,452 @@
> +// /** @file
> +//
> +// Copyright (c) 2013 - 2016 Intel Corporation. All rights reserved
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// UqiList.uni
> +//
> +// Abstract:
> +//
> +// UQI (Universal Question Identifier) allocation for setup options.
> +//
> +// This file should define UQIs in the following range only: [0x0000...0x7FFF]
> +//
> +// **/
> +
> +/=#
> +
> +//----------------------------------------------------------------------------
> +//
> +// Purpose: The translations in this file are intended to be globally
> +// consistent. All products should use the same translation for the
> +// same functional question.
> +//
> +// Usage:
> +//
> +// 1. DO NOT OVERRIDE THIS FILE!
> +// The translations in this file should be globally consistent across
> +// all of our products.
> +//
> +// 2. Never delete tokens from this file
> +//
> +// 3. When adding a new question:
> +//
> +// * Always do a thorough check of the tokens below to determine if
> +// a question is already represented. This is important, because
> +// we want to generate scripts based on these tokens which will
> +// work on our entire product line.
> +//
> +// * Always choose the first available new token number for your
> +// new token. Do not worry about "grouping" your questions
> +// together. That goal will only make it more difficult to manage
> +// the token numbering. Always add your new token to the correct
> +// place to preserve numerical ordering. This makes it easy to
> +// determine which token should be used next.
> +//
> +//----------------------------------------------------------------------------
> +
> +#langdef uqi "uqi"
> +
> +//
> +// Keep in numerical order to prevent token reuse
> +//
> +#string STR_FAST_BOOT_PROMPT #language uqi "\x0001"
> +#string STR_MEMORY_CHECK_SETUP #language uqi "\x0002"
> +#string STR_NUM_AUTO_BOOT #language uqi "\x0003"
> +#string STR_LOAD_OPTION_FORCE_RECON #language uqi
> "\x0004"
> +#string STR_ONE_OF_PROMPT #language uqi "\x0005"
> +#string STR_CHECK_BOX_PROMPT #language uqi "\x0006"
> +#string STR_TEST_OPCODE #language uqi "\x0007"
> +#string STR_TEST_OPCODE2 #language uqi "\x0008"
> +#string STR_ERROR_POPUP #language uqi "\x0009"
> +#string STR_NUMERIC_READONLY_PROMPT #language uqi
> "\x000A"
> +#string STR_NUMERIC_MANUAL_PROMPT #language uqi
> "\x000B"
> +#string STR_TALL_HEX_PROMPT #language uqi "\x000C"
> +#string STR_NAME_VALUE_VAR_NAME0 #language uqi
> "\x000D"
> +#string STR_NAME_VALUE_VAR_NAME1 #language uqi
> "\x000E"
> +#string STR_NUMERIC_STEP_PROMPT #language uqi "\x000F"
> +#string STR_DEFAULT_VALUE_FROM_ACCESS_PROMPT #language uqi
> "\x0010"
> +#string STR_DEFAULT_VALUE_FROM_CALLBACK_PROMPT #language
> uqi "\x0011"
> +#string STR_SERIAL_PORT #language uqi "\x0012"
> +#string STR_SERIAL_PORT_STATUS #language uqi "\x0013"
> +#string STR_SERIAL_PORT_IO_ADDRESS #language uqi "\x0014"
> +#string STR_SERIAL_PORT_IRQ #language uqi "\x0015"
> +#string STR_TEXT_REFRESH_GUID_COUNT #language uqi
> "\x0016"
> +#string STR_IP4_CONFIGURE #language uqi "\x0017"
> +#string STR_IP4_ENABLE_DHCP #language uqi "\x0018"
> +#string STR_ISCSI_DEVICE_ENABLE #language uqi "\x0019"
> +#string STR_ISCSI_ENABLE_DHCP #language uqi "\x001A"
> +#string STR_ISCSI_ENABLE_DHCP_ON_TARGET #language uqi
> "\x001B"
> +#string STR_ISCSI_TARGET_PORT #language uqi "\x001C"
> +#string STR_CHAP_TYPE_PROMPT #language uqi "\x001D"
> +#string STR_VLAN_VID_PROMPT #language uqi "\x001E"
> +#string STR_VLAN_PRIORITY_PROMPT #language uqi "\x001F"
> +#string STR_PCI_DEVICE_FILTER_PROMPT #language uqi "\x0020"
> +#string STR_IP6_DAD_TRANSMIT_COUNT #language uqi
> "\x0021"
> +#string STR_POLICY_TYPE_PROMPT #language uqi "\x0022"
> +#string STR_ISCSI_MODE_PROMPT #language uqi "\x0023"
> +#string STR_IP_MODE_PROMPT #language uqi "\x0024"
> +#string STR_ISCSI_CONFIG_RETRY #language uqi "\x0025"
> +#string STR_ISCSI_CONFIG_TIMEOUT #language uqi "\x0026"
> +#string STR_AUTHEN_TYPE_PROMPT #language uqi "\x0027"
> +#string STR_NULL #language uqi "\x0028"
> +#string STR_HIDE_TPM_PROMPT #language uqi "\x0029"
> +#string STR_TPM_OPERATION #language uqi "\x002A"
> +#string STR_MOR_PROMPT #language uqi "\x002B"
> +#string STR_SECURE_BOOT_PROMPT #language uqi "\x002C"
> +#string STR_USB_SUPPORT #language uqi "\x002D"
> +#string STR_USB_LEGACY_SUPPORT #language uqi "\x002E"
> +#string STR_USB_XHCI_SUPPORT #language uqi "\x002F"
> +#string STR_USB_BIOS_XHCI_HANDOFF #language uqi "\x0030"
> +#string STR_USB_BIOS_EHCI_HANDOFF #language uqi "\x0031"
> +#string STR_USB_6064 #language uqi "\x0032"
> +#string STR_USB_HOTPLUG_FDD #language uqi "\x0033"
> +#string STR_USB_HOTPLUG_HDD #language uqi "\x0034"
> +#string STR_USB_HOTPLUG_CDROM #language uqi "\x0035"
> +#string STR_USB_CONTROL_TIME_OUT #language uqi "\x0036"
> +#string STR_USB_MASS_RESET_DELAY #language uqi "\x0037"
> +#string STR_USB_POWERGOOD_DELAY #language uqi "\x0038"
> +#string STR_USB_DELAY_NUM_VALUE #language uqi "\x0039"
> +#string STR_USB_MASS_DEVICE1 #language uqi "\x003A"
> +#string STR_USB_MASS_DEVICE2 #language uqi "\x003B"
> +#string STR_USB_MASS_DEVICE3 #language uqi "\x003C"
> +#string STR_USB_MASS_DEVICE4 #language uqi "\x003D"
> +#string STR_USB_MASS_DEVICE5 #language uqi "\x003E"
> +#string STR_USB_MASS_DEVICE6 #language uqi "\x003F"
> +#string STR_USB_MASS_DEVICE7 #language uqi "\x0040"
> +#string STR_USB_MASS_DEVICE8 #language uqi "\x0041"
> +#string STR_USB_MASS_DEVICE9 #language uqi "\x0042"
> +#string STR_USB_MASS_DEVICE10 #language uqi "\x0043"
> +#string STR_USB_MASS_DEVICE11 #language uqi "\x0044"
> +#string STR_USB_MASS_DEVICE12 #language uqi "\x0045"
> +#string STR_USB_MASS_DEVICE13 #language uqi "\x0046"
> +#string STR_USB_MASS_DEVICE14 #language uqi "\x0047"
> +#string STR_USB_MASS_DEVICE15 #language uqi "\x0048"
> +#string STR_USB_MASS_DEVICE16 #language uqi "\x0049"
> +#string STR_SECURITY_BOOT_PROMPT #language uqi "\x004A"
> +#string STR_QUIETBOOT_PROMPT #language uqi "\x004B"
> +#string STR_LOG_BOOT_TIME_PROMPT #language uqi "\x004C"
> +#string STR_EXECUTE_DISABLE_BIT_PROMPT #language uqi
> "\x004D"
> +#string STR_LIMIT_CPUID_MAX_PROMPT #language uqi
> "\x004E"
> +#string STR_PROC_HOT_ENABLE #language uqi "\x004F"
> +#string STR_VTX2_PROMPT #language uqi "\x0050"
> +#string STR_CORE_FRE_MULTIP_SELECT_PROMPT #language uqi
> "\x0051"
> +#string STR_TM1_PROMPT #language uqi "\x0052"
> +#string STR_TM2_PROMPT #language uqi "\x0053"
> +#string STR_DTS_PROMPT #language uqi "\x0054"
> +#string STR_ACTIVE_PROCESSOR_CORES_PROMPT #language uqi
> "\x0055"
> +#string STR_CPU_IST_PROMPT #language uqi "\x0056"
> +#string STR_BOOT_P_STATE #language uqi "\x0057"
> +#string STR_PROCESSOR_TURBO_MODE #language uqi "\x0058"
> +#string STR_CSTATE_PROMPT #language uqi "\x0059"
> +#string STR_CXE_PROMPT #language uqi "\x005A"
> +#string STR_HARDC4E_PROMPT #language uqi "\x005B"
> +#string STR_MAX_C_STATE_SUPPORT_PROMPT #language uqi
> "\x005C"
> +#string STR_PPM_C4_EXIT_PROMPT #language uqi "\x005D"
> +#string STR_CX_POPDOWN_PROMPT #language uqi "\x005E"
> +#string STR_CX_POPUP_PROMPT #language uqi "\x005F"
> +#string STR_SEC_SETTING_PROMPT #language uqi "\x0060"
> +#string STR_SEC_FLASH_UPDATE_PROMPT #language uqi
> "\x0061"
> +#string STR_SEC_FIRMWARE_UPDATE_PROMPT #language uqi
> "\x0062"
> +#string STR_FIRMWARE_TPM_PROMPT #language uqi "\x0063"
> +#string STR_TPM_PROMPT #language uqi "\x0064"
> +#string STR_TDT_CONFIG_PROMPT #language uqi "\x0065"
> +#string STR_TDT_RECOVERY_PROMPT #language uqi "\x0066"
> +#string STR_TDT_SUSPEND_PROMPT #language uqi "\x0067"
> +#string STR_ICH_PCIERP1_PROMPT #language uqi "\x0068"
> +#string STR_ICH_PCIERP2_PROMPT #language uqi "\x0069"
> +#string STR_ICH_PCIERP3_PROMPT #language uqi "\x006A"
> +#string STR_ICH_PCIERP4_PROMPT #language uqi "\x006B"
> +#string STR_USB_DEBUG_PROMPT #language uqi "\x006C"
> +#string STR_USB_XHCI_SUPPORT_PROMPT #language uqi
> "\x006D"
> +#string STR_PCH_USB21_PROMPT #language uqi "\x006E"
> +#string STR_PCH_USB30_MODE_PROMPT #language uqi
> "\x006F"
> +#string STR_PCH_USB30_STREAMS #language uqi "\x0070"
> +#string STR_PCH_USB_PER_PORT_PROMPT #language uqi
> "\x0071"
> +#string STR_PCH_USB_PORT0_PROMPT #language uqi "\x0072"
> +#string STR_PCH_USB_PORT1_PROMPT #language uqi "\x0073"
> +#string STR_PCH_USB_PORT2_PROMPT #language uqi "\x0074"
> +#string STR_PCH_USB_PORT3_PROMPT #language uqi "\x0075"
> +#string STR_PCH_USBRMH_PROMPT #language uqi "\x0076"
> +#string STR_SATA_PROMPT #language uqi "\x0077"
> +#string STR_SATA_TYPE_PROMPT #language uqi "\x0078"
> +#string STR_SATA0_HOTPLUG_CAP_PROMPT #language uqi
> "\x0079"
> +#string STR_SATA1_HOTPLUG_CAP_PROMPT #language uqi
> "\x007A"
> +#string STR_LPSS_EMMC_PROMPT #language uqi "\x007B"
> +#string STR_LPSS_SDIO_PROMPT #language uqi "\x007C"
> +#string STR_LPSS_SDCARD_PROMPT #language uqi "\x007D"
> +#string STR_LPSS_DMA_PROMPT #language uqi "\x007E"
> +#string STR_LPSS_I2C1_PROMPT #language uqi "\x007F"
> +#string STR_LPSS_I2C2_PROMPT #language uqi "\x0080"
> +#string STR_LPSS_PCM_PROMPT #language uqi "\x0081"
> +#string STR_LPSS_I2S_PROMPT #language uqi "\x0082"
> +#string STR_LPSS_HSUART1_PROMPT #language uqi "\x0083"
> +#string STR_LPSS_HSUART2_PROMPT #language uqi "\x0084"
> +#string STR_LPSS_SPI_PROMPT #language uqi "\x0085"
> +#string STR_PCH_LAN_CONTROLLER #language uqi "\x0086"
> +#string STR_PCH_LAN_WOL_PROMPT #language uqi "\x0087"
> +#string STR_PCH_SLP_LAN_LOW_DC_PROMPT #language uqi
> "\x0088"
> +#string STR_PCH_PXEROM_CONTROL #language uqi "\x0089"
> +#string STR_LPE_PROMPT #language uqi "\x008A"
> +#string STR_PCH_AZALIA_PROMPT #language uqi "\x008B"
> +#string STR_AZALIA_VC_PROMPT #language uqi "\x008C"
> +#string STR_AZALIA_DS_PROMPT #language uqi "\x008D"
> +#string STR_AZALIA_PME_PROMPT #language uqi "\x008E"
> +#string STR_HDMI_CODEC_PROMPT #language uqi "\x008F"
> +#string STR_HPET_PROMPT #language uqi "\x0090"
> +#string STR_HPET_BOOTTIME_PROMPT #language uqi "\x0091"
> +#string STR_STATE_AFTER_G3 #language uqi "\x0092"
> +#string STR_PCH_UART_SELECT #language uqi "\x0093"
> +#string STR_PCU_UART_A #language uqi "\x0094"
> +#string STR_PCU_UART_B #language uqi "\x0095"
> +#string STR_ACPI_CRITICAL_THERMAL_TRIP_POINT #language uqi
> "\x0096"
> +#string STR_ACPI_PASSIVE_THERMAL_TRIP_POINT #language uqi
> "\x0097"
> +#string STR_ACPI_PASSIVE_TC1_VALUE #language uqi "\x0098"
> +#string STR_ACPI_PASSIVE_TC2_VALUE #language uqi "\x0099"
> +#string STR_ACPI_PASSIVE_TSP_VALUE #language uqi "\x009A"
> +#string STR_DPTF_PROMPT #language uqi "\x009B"
> +#string STR_LPM_PROMPT #language uqi "\x009C"
> +#string STR_CTDP_PROMPT #language uqi "\x009D"
> +#string STR_MEMORY_PROMPT #language uqi "\x009E"
> +#string STR_DPTF_ACTIVE_TRIP_POINT_PROMPT #language uqi
> "\x009F"
> +#string STR_DPTF_PASSIVE_TRIP_POINT_PROMPT #language uqi
> "\x00A0"
> +#string STR_SKIN_SENSOR_PROMPT #language uqi "\x00A1"
> +#string STR_PCH_PROMPT #language uqi "\x00A2"
> +#string STR_PRIMARY_DISPLAY #language uqi "\x00A3"
> +#string STR_VIDEO_RS2_PROMPT #language uqi "\x00A4"
> +#string STR_DVMT40_PRE_ALLOC #language uqi "\x00A5"
> +#string STR_GFX_BOOST_PROMPT #language uqi "\x00A6"
> +#string STR_IGD_THERMAL_PROMPT #language uqi "\x00A7"
> +#string STR_SPREAD_SPECTRUM_CLOCK_PROMPT #language uqi
> "\x00A8"
> +#string STR_VIDEO_LCD_IBIA #language uqi "\x00A9"
> +#string STR_ACPI_ALS_ENABLE #language uqi "\x00AA"
> +#string STR_IGD_FLAT_PANEL_PROMPT #language uqi "\x00AB"
> +#string STR_BOOT_DISPLAY_DEVICE_PROMPT #language uqi
> "\x00AC"
> +#string STR_PANNEL_SCALING_PROMPT #language uqi
> "\x00AD"
> +#string STR_VIDEO_LCD_IGMCHBLC_PROMPT #language uqi
> "\x00AE"
> +#string STR_MEMORY_SCRAMBLER_PROMPT #language uqi
> "\x00AF"
> +#string STR_CSTATE_C4 #language uqi "\x00B0"
> +#string STR_CSTATE_C6 #language uqi "\x00B1"
> +#string STR_SEC_EOP_PROMPT #language uqi "\x00B2"
> +#string STR_PCH_USB_PORT4_PROMPT #language uqi "\x00B3"
> +#string STR_PCH_USB_PORT5_PROMPT #language uqi "\x00B4"
> +#string STR_PCH_USB_PORT6_PROMPT #language uqi "\x00B5"
> +#string STR_PCH_USB_PORT7_PROMPT #language uqi "\x00B6"
> +#string STR_HDMI_CODEC_PORTB_PROMPT #language uqi
> "\x00B7"
> +#string STR_HDMI_CODEC_PORTC_PROMPT #language uqi
> "\x00B8"
> +#string STR_HDMI_CODEC_PORTD_PROMPT #language uqi
> "\x00B9"
> +#string STR_CONVERT_BOARD_SELECT #language uqi "\x00BA"
> +#string STR_DPTF_CLPM_PROMPT #language uqi "\x00BB"
> +#string STR_PROCESSOR_DPTF_PROMPT #language uqi
> "\x00BC"
> +#string STR_DPTF_SYSTHERM0_PROMPT #language uqi
> "\x00BD"
> +#string STR_DPTF_SYSTHERM1_PROMPT #language uqi "\x00BE"
> +#string STR_DPTF_SYSTHERM2_PROMPT #language uqi "\x00BF"
> +#string STR_DPTF_SYSTHERM3_PROMPT #language uqi "\x00C0"
> +#string STR_DPTF_CHARGER_PROMPT #language uqi "\x00C1"
> +#string STR_DPTF_DISPLAY_PROMPT #language uqi "\x00C2"
> +#string STR_DPTF_SOC_PROMPT #language uqi "\x00C3"
> +#string STR_GOP_VBIOS_SWITCH #language uqi "\x00C4"
> +#string STR_PAVC_PROMPT #language uqi "\x00C5"
> +#string STR_GTT_SIZE #language uqi "\x00C6"
> +#string STR_APERTURE_SIZE #language uqi "\x00C7"
> +#string STR_DVMT50_PRE_ALLOC #language uqi "\x00C8"
> +#string STR_FORCE_LID_STATUS_PROMPT #language uqi
> "\x00C9"
> +#string STR_TREE_DEVICE_PROMPT #language uqi "\x00CA"
> +#string STR_TPM2_REVOKE_TRUST_PROMPT #language uqi
> "\x00CB"
> +#string STR_PCH_USB_OTG_PROMPT #language uqi "\x00CC"
> +#string STR_LPSS_PCI_PROMPT #language uqi "\x00CD"
> +#string STR_SCC_EMMC_PROMPT #language uqi "\x00CE"
> +#string STR_SCC_SDIO_PROMPT #language uqi "\x00CF"
> +#string STR_SCC_SDCARD_PROMPT #language uqi "\x00D0"
> +#string STR_MIPI_HSI_PROMPT #language uqi "\x00D1"
> +#string STR_LPSS_DMA1_PROMPT #language uqi "\x00D2"
> +#string STR_LPSS_DMA2_PROMPT #language uqi "\x00D3"
> +#string STR_LPSS_I2C3_PROMPT #language uqi "\x00D4"
> +#string STR_LPSS_I2C4_PROMPT #language uqi "\x00D5"
> +#string STR_LPSS_I2C5_PROMPT #language uqi "\x00D6"
> +#string STR_LPSS_I2C6_PROMPT #language uqi "\x00D7"
> +#string STR_LPSS_I2C7_PROMPT #language uqi "\x00D8"
> +#string STR_PWM1_PROMPT #language uqi "\x00D9"
> +#string STR_PWM2_PROMPT #language uqi "\x00DA"
> +#string STR_LPSS_LPE_PROMPT #language uqi "\x00DB"
> +#string STR_PMIC_ACPI_OBJECT_PROMPT #language uqi
> "\x00DC"
> +#string STR_S0IX_PROMPT #language uqi "\x00DD"
> +#string STR_DPTF_CRITICAL_TEMP #language uqi "\x00DE"
> +#string STR_DPTF_PASSIVE_TEMP #language uqi "\x00DF"
> +#string STR_DPTF_SDBG #language uqi "\x00E0"
> +#string STR_DPTF_CLPO #language uqi "\x00E1"
> +#string STR_DPTF_CLPO_START_PINDEX #language uqi "\x00E2"
> +#string STR_DPTF_CLPO_STEP_SIZE #language uqi "\x00E3"
> +#string STR_DPTF_CLPO_PWR_CTRL #language uqi "\x00E4"
> +#string STR_DPTF_CLPO_PERF_CTRL #language uqi "\x00E5"
> +#string STR_DPTF_DPPM #language uqi "\x00E6"
> +#string STR_ISP_ENABLED #language uqi "\x00E7"
> +#string STR_ISP_PCICONFIGURATION_TITLE #language uqi
> "\x00E8"
> +#string STR_IGD_PROMPT #language uqi "\x00E9"
> +#string STR_PNP_SETTING_PROMPT #language uqi "\x00EA"
> +#string STR_DPTF_SYSTHERM4_PROMPT #language uqi "\x00EB"
> +#string STR_ACPIMEMDBG_SWTICH #language uqi "\x00EC"
> +#string STR_SECURE_BOOT #language uqi "\x00ED"
> +#string STR_SECURE_BOOT_MODE #language uqi "\x00EE"
> +#string STR_PCIE_SPEED_PROMPT0 #language uqi "\x00EF"
> +#string STR_PCIE_SPEED_PROMPT1 #language uqi "\x00F0"
> +#string STR_PCIE_SPEED_PROMPT2 #language uqi "\x00F1"
> +#string STR_PCIE_SPEED_PROMPT3 #language uqi "\x00F2"
> +#string STR_SATA_TEST_MODE_PROMPT #language uqi
> "\x00F3"
> +#string STR_CLOCK_SPREAD_SPEC_ENABLE #language uqi
> "\x00F4"
> +#string STR_BATTERY_ACPI_OBJECT_PROMPT #language uqi
> "\x00F5"
> +#string STR_MFGMODE #language uqi "\x00F6"
> +#string STR_PCH_USB_VBUS_PROMPT #language uqi "\x00F7"
> +#string STR_PCH_USB_EHCIDEBUG_PROMPT #language uqi
> "\x00F8"
> +#string STR_CRID_PROMPT #language uqi "\x00F9"
> +#string STR_GOP_BRIGHTNESS_LEVEL #language uqi "\x00FA"
> +#string STR_ULPMC_FW_LOCK_PROMPT #language uqi
> "\x00FC"
> +#string STR_SECURE_BOOT_MODE_PROMPT #language uqi
> "\x00FD"
> +#string STR_DELETE_PK #language uqi "\x00FE"
> +#string STR_I2C_TOUCH_PROMPT #language uqi "\x00FF"
> +#string STR_PCH_SPI_WP_PROMPT #language uqi "\x0100"
> +#string STR_PMWEIGHTS_PROMPT #language uqi "\x0101"
> +#string STR_FORM_BOOT_CHG_TITLE #language uqi "\x0102"
> +#string STR_FORM_DRV_CHG_TITLE #language uqi "\x0103"
> +#string STR_TALL_MANUAL_PROMPT #language uqi "\x0104"
> +#string STR_NUMERIC_PROMPT #language uqi "\x0105"
> +#string STR_NUMERIC_PROMPT1 #language uqi "\x0106"
> +#string STR_ACTIVE_CORE_COUNT_PROMPT #language uqi
> "\x0107"
> +#string STR_PBA_CONFIG_PROMPT #language uqi "\x0108"
> +#string STR_IGD_TURBO_PROMPT #language uqi "\x0109"
> +#string STR_IGD_TURBO_HELP #language uqi "\x010A"
> +#string STR_EHCI_PLL_CFG_PROMPT #language uqi "\x010B"
> +#string STR_EHCI_PLL_CFG_RTD3_DIS_HELP #language uqi
> "\x010C"
> +#string STR_LM_MEMORY_PROMPT #language uqi "\x010D"
> +#string STR_PDM_OUTPUT_CONFIG_SWTICH #language uqi
> "\x010E"
> +#string STR_PUINT_BIOS_CONFIG_DISPLAY #language uqi
> "\x010F"
> +#string STR_SCC_SDIO_MODE_PROMPT #language uqi "\x0110"
> +#string STR_ISCT_CONFIGURATION #language uqi "\x0111"
> +#string STR_ISCT_NOTIFICATION_CONTROL_PROMPT #language uqi
> "\x0112"
> +#string STR_ISCT_WLAN_CONTROL_PROMPT #language uqi
> "\x0113"
> +#string STR_ISCT_WWAN_CONTROL_PROMPT #language uqi
> "\x0114"
> +#string STR_EXISUPPORT_PROMPT #language uqi "\x0115"
> +#string STR_PCH_FSA_PROMPT #language uqi "\x0116"
> +#string STR_PCH_FSA_HELP #language uqi "\x0117"
> +#string STR_USB_AUTO_MODE_PROMPT #language uqi
> "\x0118"
> +#string STR_SCC_EMMC45_PROMPT #language uqi "\x0119"
> +#string STR_SCC_EMMC45_HELP #language uqi "\x011A"
> +#string STR_SCC_EMMC45_DDR50_PROMPT #language uqi
> "\x011B"
> +#string STR_SCC_EMMC45_DDR50_HELP #language uqi "\x011C"
> +#string STR_SCC_EMMC45_HS200_PROMPT #language uqi
> "\x011D"
> +#string STR_SCC_EMMC45_HS200_HELP #language uqi "\x011E"
> +#string STR_SCC_EMMC45_RE_TUNE_TIMER_VALUE #language uqi
> "\x011F"
> +#string STR_SCC_EMMC45_RE_TUNE_TIMER_VALUE_HELP #language
> uqi "\x0120"
> +#string STR_CFIO_PNP_SETTING_PROMPT #language uqi
> "\x0121"
> +#string STR_CFIO_PNP_SETTING_HELP #language uqi "\x0122"
> +#string STR_EMMC_BOOT_PROMPT #language uqi "\x0123"
> +#string STR_EMMC_BOOT_HELP #language uqi "\x0124"
> +#string STR_WITT_PROMPT #language uqi "\x0125"
> +#string STR_SECURE_BOOT_TEST_PROMPT #language uqi
> "\x0126"
> +#string STR_TRISTATE_LPC_PROMPT #language uqi "\x0127"
> +#string STR_DOP_CG_PROMPT #language uqi "\x0128"
> +#string STR_PSS_ENABLE_PROMPT #language uqi "\x0129"
> +#string STR_PSS_ENABLE_HELP #language uqi "\x012A"
> +#string STR_ISCT_SLEEP_DURATION_FORMAT #language uqi
> "\x012B"
> +#string STR_ISCT_RF_KILL_SUPPORT #language uqi "\x012C"
> +#string STR_SECURE_BOOT_UPP_PROMPT #language uqi
> "\x012D"
> +#string STR_MEASURED_BOOT_ENABLE_PROMPT #language uqi
> "\x012E"
> +#string STR_MEASURED_BOOT_ENABLE_HELP #language uqi
> "\x012F"
> +#string STR_PTT_PROMPT #language uqi "\x0130"
> +#string STR_CHECK_SHA256_HASH_MASTER_BOOT_CODES #language
> uqi "\x0131"
> +#string STR_USB_XHCI_LPM_SUPPORT_PROMPT #language uqi "\x0132"
> +
> +#string STR_VIRTUAL_KB_PROMPT #language uqi "\x0135"
> +#string STR_VIRTUAL_KB_HELP #language uqi "\x0136"
> +#string STR_TREE_OPERATION #language uqi "\x0137"
> +#string STR_SLP_S0IX_N_PROMPT #language uqi "\x0138"
> +#string STR_SLP_S0IX_N_HELP #language uqi "\x0139"
> +#string STR_DPTF_AMBIENTTRIPPOINTCHANGE_PROMPT #language
> uqi "\x013A"
> +#string STR_DPTF_THERM0_PCAT_PROMPT #language uqi
> "\x013B"
> +#string STR_DPTF_THERM1_PCAT_PROMPT #language uqi
> "\x013C"
> +#string STR_DPTF_THERM2_PCAT_PROMPT #language uqi
> "\x013D"
> +#string STR_MMIO_PROMPT #language uqi "\x013E"
> +#string STR_UTS_PROMPT #language uqi "\x013F"
> +#string STR_UTS_HELP #language uqi "\x0140"
> +#string STR_WLAN_NGFF_CARD #language uqi "\x0141"
> +#string STR_WLAN_UHPAM_CARD #language uqi "\x0142"
> +#string STR_ENABLE_DBG2 #language uqi "\x0143"
> +#string STR_DPTF_ALLOWHIGHERPERFORMANCE_PROMPT #language
> uqi "\x0144"
> +#string STR_DATP_PROMPT #language uqi "\x0145"
> +#string STR_DPTF_OFFLINING #language uqi "\x0146"
> +#string STR_SAR_SENSOR_PROMPT #language uqi "\x0147"
> +#string STR_DPTF_BRAND_STRING #language uqi "\x0148"
> +#string STR_CODEC262_DISABLED_PROMPT #language uqi
> "\x0149"
> +#string STR_CODEC262_DISABLED_HELP #language uqi "\x014A"
> +
> +//SD CARD SDR25 and DDR50
> +#string STR_SCC_SD_SDR25_PROMPT #language uqi "\x014B"
> +#string STR_SCC_SD_SDR25_HELP #language uqi "\x014C"
> +#string STR_SCC_SD_DDR50_PROMPT #language uqi "\x014D"
> +#string STR_SCC_SD_DDR50_HELP #language uqi "\x014E"
> +#string STR_SB_PROFILE_PROMPT #language uqi "\x014F"
> +#string STR_SECURE_BOOT_PRO_KEY_PROMPT #language uqi
> "\x0150"
> +
> +#string STR_OS_SELETION_PROMPT #language uqi "\x0151"
> +#string STR_OS_SELETION_HELP #language uqi "\x0152"
> +#string STR_WINDOWS #language uqi "\x0153"
> +#string STR_ANDROID #language uqi "\x0154"
> +#string STR_AESNI_PROMPT #language uqi "\x0155"
> +
> +#string STR_LPSS_I2C1_HELP_ENBDT_DEV_LIST #language uqi
> "\x0156"
> +#string STR_LPSS_I2C2_HELP_ENBDT_DEV_LIST #language uqi
> "\x0157"
> +#string STR_LPSS_I2C3_HELP_ENBDT_DEV_LIST #language uqi
> "\x0158"
> +#string STR_LPSS_I2C4_HELP_ENBDT_DEV_LIST #language uqi
> "\x0159"
> +#string STR_LPSS_I2C5_HELP_ENBDT_DEV_LIST #language uqi
> "\x015A"
> +#string STR_LPSS_I2C6_HELP_ENBDT_DEV_LIST #language uqi
> "\x015B"
> +#string STR_LPSS_I2C7_HELP_ENBDT_DEV_LIST #language uqi
> "\x015C"
> +#string STR_LPSS_HSUART1_HELP_ENBDT_DEV_LIST #language uqi
> "\x015D"
> +#string STR_LPSS_HSUART2_HELP_ENBDT_DEV_LIST #language uqi
> "\x015E"
> +
> +#string STR_SECURE_ERASE_PROMPT #language uqi "\x015F"
> +#string STR_SEC_FIRMWARE_WRITE_PROMPT #language uqi
> "\x0160"
> +
> +#string STR_BOOT_DISPLAY_MIPIDSI_PROMPT #language uqi
> "\x0161"
> +#string STR_SEC_FIRMWARE_TOGGLE_PROMPT #language uqi
> "\x0162"
> +#string STR_PCIEDYNCLK_PROMPT #language uqi "\x0163"
> +#string STR_PAVP_LITE_MODE #language uqi "\x0164"
> +#string STR_PAVP_SERPENT_MODE #language uqi "\x0165"
> +#string STR_SCC_SDCARD_FORWIN_PROMPT #language uqi
> "\x0166"
> +#string STR_DROIDBOOT_PROMPT #language uqi "\x0167"
> +#string STR_ANDROIDBOOT_PROMPT #language uqi "\x0168"
> +
> +#string STR_CRITICAL_BATTERY_LIMIT_PROMPT #language uqi "\x0169"
> +#string STR_CRITICAL_BATTERY_LIMIT_HELP #language uqi "\x016A"
> +#string STR_CRITICAL_BATTERY_LIMIT_FEATURE_PROMPT #language uqi
> "\x016B"
> +#string STR_CRITICAL_BATTERY_LIMIT_FEATURE_HELP #language uqi
> "\x016C"
> +#string STR_WINDOWS7 #language uqi "\x016D"
> +#string STR_LPSSDEVHIDE_PROMPT #language uqi "\x016E"
> +#string STR_EM1_IAAPPSRUN_PROMPT #language uqi "\x016F"
> +#string STR_EM1_IAAPPSCAP_PROMPT #language uqi "\x0170"
> +#string STR_EM1_CAP_OR_VOLTAGE_PROMPT #language uqi
> "\x0171"
> +#string STR_EM1_BOOT_ON_INVALID_BAT_PROMPT #language uqi
> "\x0172"
> +
> +#string STR_USB_HSIC_0_PROMPT #language uqi "\x0173"
> +#string STR_USB_HSIC_0_HELP #language uqi "\x0174"
> +#string STR_LEGACYUSBBOOTING_PROMPT #language uqi
> "\x0175"
> +#string STR_STR_LEGACYUSBBOOTING_HELP #language uqi
> "\x0176"
> +#string STR_LWINDOWS7 #language uqi "\x0177"
> +#string STR_WEC7 #language uqi "\x0178"
> +#string STR_LINUX #language uqi "\x0179"
> +#string STR_WARNING_POPUP #language uqi "\x017A"
> +#string STR_LPSS_HSUART1_FLOWCONTROL_PROMPT #language uqi
> "\x017B"
> +#string STR_LPSS_HSUART2_FLOWCONTROL_PROMPT #language uqi
> "\x017C"
> +#string STR_SCC_SDCARD_REMOVABILITY #language uqi
> "\x017D"
> +#string STR_SCC_SDCARD_REMOVABLE #language uqi "\x017E"
> +#string STR_SCC_SDCARD_NON_REMOVABLE #language uqi
> "\x017F"
> +#string STR_SCC_SDCARD_REMOVABILITY_HELP #language uqi
> "\x0180"
> +#string STR_RTC_BATTERY #language uqi "\x0181"
> +#string STR_RTC_BATTERY_NOT_PRESENT #language uqi
> "\x0182"
> +#string STR_RTC_BATTERY_PRESENT #language uqi "\x0183"
> +#string STR_RTC_BATTERY_HELP #language uqi "\x0184"
> +#string STR_LPE_REPORTED_BY_DSDT_PROMPT #language uqi
> "\x0185"
> +#string STR_LPE_REPORTED_BY_DSDT_HELP #language uqi
> "\x0186"
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Vfr.vfr
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Vfr.vfr
> new file mode 100644
> index 0000000000..77976322de
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/Vfr.vfr
> @@ -0,0 +1,123 @@
> +//
> +//
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +//
>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +//
>
> +//
> +//
> +#include "Configuration.h"
> +#include "PlatformSetupDxeStrDefs.h"
> +#include "Guid/SetupVariable.h"
> +
> +formset
> + guid = SYSTEM_CONFIGURATION_GUID,
> + title = STRING_TOKEN(STR_SYSTEM_SETUP_TITLE),
> + help = STRING_TOKEN(STR_SYSTEM_SETUP_HELP),
> + class = 1,
> + subclass = 0,
> +
> +
> + varstore SYSTEM_CONFIGURATION, name = Setup, guid =
> SYSTEM_CONFIGURATION_GUID;
> + form formid = ROOT_FORM_ID,
> + title = STRING_TOKEN(STR_SYSTEM_SETUP_TITLE);
> +
> + //
> + // Jump to 2)Main Form
> + //
> + goto ROOT_MAIN_FORM_ID,
> + prompt = STRING_TOKEN(STR_MAIN_TITLE),
> + help = STRING_TOKEN(STR_MAIN_HELP);
> +
> + //
> + // Jump to 3)Uncore Configuration Form
> + //
> + goto UNCORE_FORM_ID,
> + prompt = STRING_TOKEN(STR_UNCORE_CONFIGURATION_TITLE),
> + help = STRING_TOKEN(STR_UNCORE_CONFIGURATION_HELP);
> +
> + //
> + // Jump to 4)South Cluster Configuration Form
> + //
> + goto SOUTH_CLUSTER_FORM_ID,
> + prompt = STRING_TOKEN(STR_SOUTH_CLUSTER_TITLE),
> + help = STRING_TOKEN(STR_SOUTH_CLUSTER_HELP);
> +
> + // Jump to 5)Boot Form
> + //
> + goto BOOT_CONFIGURATION_FORM_ID,
> + prompt = STRING_TOKEN(STR_BOOT_CONFIGURATION_TITLE),
> + help = STRING_TOKEN(STR_BOOT_CONFIGURATION_HELP);
> +
> + //
> + // Jump to 6)Security Configuration Form
> + //
> + goto SECURITY_CONFIGURATION_FORM_ID,
> + prompt = STRING_TOKEN(STR_SECURITY_CONFIGURATION_TITLE),
> + help = STRING_TOKEN(STR_SECURITY_CONFIGURATION_HELP);
> +
> + //
> + // Jump to 7)Thermal Form
> + //
> + goto THERMAL_FORM_ID,
> + prompt = STRING_TOKEN(STR_THERMAL_TITLE),
> + help = STRING_TOKEN(STR_THERMAL_HELP);
> +
> + //
> + // Jump to 8) System Component Form
> + goto SYSTEM_COMPONENT_FORM_ID,
> + prompt = STRING_TOKEN(STR_SYSTEM_COMPONENT_TITLE),
> + help = STRING_TOKEN(STR_SYSTEM_COMPONENT_HELP);
> +
> + //
> + // Jump to 10)Debug Configuration Form
> + //
> +#if (BYTI_PF_ENABLE == 0)
> + goto DEBUG_CONFIGURATION_FORM_ID,
> + prompt = STRING_TOKEN(STR_DEBUG_CONFIGURATION_TITLE),
> + help = STRING_TOKEN(STR_DEBUG_CONFIGURATION_HELP);
> +#endif
> +
> + subtitle text = STRING_TOKEN(STR_NULL_STRING);
> + //
> + // Commit change and exit
> + //
> + text
> + help = STRING_TOKEN(STR_COMMIT_CHANGE_AND_EXIT_HELP),
> + text = STRING_TOKEN(STR_COMMIT_CHANGE_AND_EXIT_PROMPT),
> + text = STRING_TOKEN(STR_COMMIT_CHANGE_AND_EXIT_PROMPT),
> + flags = INTERACTIVE,
> + key = 0xF001;
> +
> + //
> + // Discard change and exit
> + //
> + text
> + help = STRING_TOKEN(STR_DISCARD_CHANGE_AND_EXIT_HELP),
> + text = STRING_TOKEN(STR_DISCARD_CHANGE_AND_EXIT_PROMPT),
> + text = STRING_TOKEN(STR_DISCARD_CHANGE_AND_EXIT_PROMPT),
> + flags = INTERACTIVE,
> + key = 0xF002;
> +
> + //
> + // Load default and exit
> + //
> + text
> + help = STRING_TOKEN(STR_LOAD_DEFAULT_AND_EXIT_HELP),
> + text = STRING_TOKEN(STR_LOAD_DEFAULT_AND_EXIT_PROMPT),
> + text = STRING_TOKEN(STR_LOAD_DEFAULT_AND_EXIT_PROMPT),
> + flags = INTERACTIVE,
> + key = 0xF003;
> + endform;
> +
> + #include "Main.vfi"
> + #include "UnCore.vfi"
> + #include "SouthClusterConfig.vfi"
> + #include "Boot.vfi"
> + #include "Security.vfi"
> + #include "Thermal.vfi"
> + #include "SystemComponent.vfi"
> + #include "DebugConfig.vfi"
> +endformset;
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni
> new file mode 100644
> index 0000000000..42c767e30d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni
> @@ -0,0 +1,1417 @@
> +// /** @file
> +// Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// Strings.vfr
> +//
> +// Abstract:
> +//
> +// String definitions for Platform Setup formset.
> +//
> +// Revision History:
> +//
> +// **/
> +
> +//
> +// NOTE: for SETUP engine spacing, the following character spaces denote
> how much room in each section you have.
> +// In the Help Text section " " -this is 23 spaces wide.
> +// In the Far left panel " " -this is 37 spaces wide.
> +// In the middle section " " -this is 37 spaces wide.
> +//
> +/=#
> +
> +#langdef en-US "English"
> +#langdef fr-FR "Français"
> +
> +// STR_LANG_NAME is dummy for font extrace tool. Without this,
> +// some characters for language selection menu will not be displayed
> +// correctly.
> +#string STR_LANG_NAME #language fr-FR "Français"
> +#string STR_LANG_NAME #language en-US "English"
> +
> +//Root form
> +#string STR_SYSTEM_SETUP_TITLE #language en-US "System
> Setup"
> +#string STR_SYSTEM_SETUP_HELP #language en-US "Press
> <Enter> to select the System Configuration Setup options."
> +
> +#string STR_MAIN_TITLE #language en-US "Main"
> +#string STR_MAIN_HELP #language en-US ""
> +
> +#string STR_CPU_CONFIGURATION_TITLE #language en-US "CPU
> Configuration"
> +#string STR_CPU_CONFIGURATION_HELP #language en-US ""
> +
> +#string STR_CPU_POWERMNG_TITLE #language en-US "CPU
> Power Management"
> +#string STR_CPU_POWERMNG_HELP #language en-US ""
> +
> +#string STR_BOOT_CONFIGURATION_TITLE #language en-US
> "Boot"
> +#string STR_BOOT_CONFIGURATION_HELP #language en-US ""
> +
> +#string STR_IGD_TITLE #language en-US "IGD
> Configuration"
> +#string STR_IGD_HELP #language en-US ""
> +
> +#string STR_MEMORY_CONFIGURATION_TITLE #language en-US
> "Memory Configuration"
> +#string STR_MEMORY_CONFIGURATION_HELP #language en-US ""
> +
> +#string STR_ISP_ENABLED #language en-US "ISP
> Enable/Disable"
> +#string STR_ISP_ENABLED_HELP #language en-US
> "Enable/Disable ISP PCI Device Selection."
> +
> +#string STR_ISP_CONFIGURATION_TITLE #language en-US "ISP
> PCI Device Configuration"
> +#string STR_ISP_PCICONFIGURATION_TITLE #language en-US "ISP
> PCI Device Selection"
> +#string STR_ISP_PCICONFIGURATION_HELP #language en-US
> "Default ISP is PCI B0D2F0 for Window Boot. Linux Boot to select B0D3F0"
> +#string STR_ISP_PCICONFIG_B0D2F0_TITLE #language en-US "ISP
> PCI Device as B0D2F0"
> +#string STR_ISP_PCICONFIG_B0D3F0_TITLE #language en-US "ISP
> PCI Device as B0D3F0"
> +
> +#string STR_SECURITY_CONFIGURATION_TITLE #language en-US
> "Security Configuration"
> +#string STR_SECURITY_CONFIGURATION_HELP #language en-US ""
> +
> +#string STR_SOUTH_CLUSTER_TITLE #language en-US "South
> Cluster Configuration"
> +#string STR_SOUTH_CLUSTER_HELP #language en-US ""
> +
> +#string STR_UNCORE_CONFIGURATION_TITLE #language en-US
> "Uncore Configuration"
> +#string STR_UNCORE_CONFIGURATION_HELP #language en-US ""
> +
> +#string STR_DPTF_CONFIGURATION_TITLE #language en-US
> "DPTF"
> +#string STR_DPTF_CONFIGURATION_HELP #language en-US ""
> +
> +#string STR_THERMAL_TITLE #language en-US "Thermal"
> +#string STR_THERMAL_HELP #language en-US ""
> +
> +#string STR_SYSTEM_COMPONENT_TITLE #language en-US
> "System Component"
> +#string STR_SYSTEM_COMPONENT_HELP #language en-US ""
> +
> +#string STR_DEBUG_CONFIGURATION_TITLE #language en-US
> "Debug Configuration"
> +#string STR_DEBUG_CONFIGURATION_HELP #language en-US ""
> +
> +//
> +// Main form definition
> +//
> +#string STR_DATE_PROMPT #language en-US "System
> Date"
> +
> +
> +#string STR_DATE_YEAR_HELP #language en-US "Displays
> and changes the System Date from the Real-Time Clock. Format is
> Month/Day/Year. "
> +#string STR_DATE_MONTH_HELP #language en-US "Displays
> and changes the System Date from the Real-Time Clock. Format is
> Month/Day/Year. "
> +#string STR_DATE_DAY_HELP #language en-US "Displays and
> changes the System Date from the Real-Time Clock. Format is
> Month/Day/Year. "
> +#string STR_ERROR_POPUP #language en-US "Try Again"
> +#string STR_BIOS_INFORMATION_TITLE #language en-US "Bios
> Information"
> +
> +#string STR_NULL_STRING #language en-US ""
> +#string STR_NULL_STRING #language fr-FR ""
> +
> +#string STR_BIOS_VENDOR_STRING #language en-US "BIOS
> Vendor"
> +#string STR_BIOS_VENDOR_STRING #language fr-FR "Verdor
> du BIOS"
> +
> +#string STR_BIOS_VENDOR_VALUE #language en-US "Intel
> Corporation"
> +#string STR_BIOS_VENDOR_VALUE #language fr-FR ""
> +
> +#string STR_BIOS_VERSION_STRING #language en-US "BIOS
> Version"
> +#string STR_BIOS_VERSION_STRING #language fr-FR "Version
> du BIOS"
> +
> +#string STR_BIOS_VERSION_VALUE #language en-US ""
> +#string STR_BIOS_VERSION_VALUE #language fr-FR ""
> +
> +#string STR_IFWI_VERSION_STRING #language en-US "IFWI
> Version"
> +#string STR_IFWI_VERSION_STRING #language fr-FR "Version
> du IFWI"
> +
> +#string STR_IFWI_VERSION_VALUE #language en-US ""
> +#string STR_IFWI_VERSION_VALUE #language fr-FR ""
> +
> +#string STR_BIOS_BUILD_TIME_STRING #language en-US "Build
> Time"
> +#string STR_BIOS_BUILD_TIME_VALUE #language en-US "NA"
> +
> +#string STR_CORE_VERSION_STRING #language en-US "Core
> Version"
> +#string STR_CORE_VERSION_VALUE #language en-US "UEFI
> 2.40"
> +
> +#string STR_SEC_VERSION_STRING #language en-US "TXE FW
> Version"
> +#string STR_SEC_VERSION_VALUE #language en-US ""
> +
> +#string STR_SEC_CAPABILITY_STRING #language en-US "TXE FW
> Capabilities"
> +#string STR_SEC_CAPABILITY_VALUE #language en-US ""
> +
> +#string STR_SEC_FEATURE_STRING #language en-US "TXE FW
> Features"
> +#string STR_SEC_FEATURE_VALUE #language en-US ""
> +
> +#string STR_SEC_OEMTAG_STRING #language en-US "TXE FW
> OEM Tag"
> +#string STR_SEC_OEMTAG_VALUE #language en-US ""
> +
> +#string STR_SEC_FILE_SYSTEM_INTEGRITY_VALUE_STRING #language
> en-US "TXE File System Integrity Value"
> +#string STR_SEC_FILE_SYSTEM_INTEGRITY_VALUE #language en-US
> ""
> +
> +#string STR_SEC_TEMP_DISABLE_HELP #language en-US "TXE
> Temporary Disable"
> +#string STR_SEC_TEMP_DISABLE_STRING #language en-US "TXE
> Firmware Mode"
> +#string STR_SEC_TEMP_DISABLE_PROMPT #language en-US "TXE
> Temporary Disable"
> +
> +#string STR_SEC_LOCAL_FW_UPDATE_HELP #language en-US
> "TXE Disable/Enable TXE Local Fw Update"
> +#string STR_SEC_LOCAL_FW_UPDATE_STRING #language en-US
> "TXE Local Fw Update"
> +#string STR_SEC_LOCAL_FW_UPDATE_PROMPT #language en-US
> "TXE Temporary Disable"
> +
> +#string STR_SEC_FIRMWARE_WRITE_PROMPT #language en-US
> "TXE Firmware R/W Mode"
> +#string STR_SEC_FIRMWARE_WRITE_VALUE #language en-US ""
> +
> +#string STR_SEC_FIRMWARE_TOGGLE_PROMPT #language en-US
> "TXE Firmware R/W Toggle"
> +#string STR_SEC_FIRMWARE_TOGGLE_HELP #language en-US
> "Use to Toggle between R/W and R/O"
> +#string STR_SEC_FIRMWARE_TOGGLE_NO #language en-US
> "No"
> +#string STR_SEC_FIRMWARE_TOGGLE_YES #language en-US
> "Yes"
> +
> +#string STR_SEC_HMRFPO_HELP #language en-US "TXE
> HMRFPO Disable"
> +#string STR_SEC_HMRFPO_STRING #language en-US "TXE
> HMRFPO "
> +#string STR_SEC_HMRFPO_PROMPT #language en-US "TXE
> HMRFPO Disable"
> +
> +#string STR_SEC_EOP_HELP #language en-US "Send EOP
> Message Befor Enter OS"
> +#string STR_SEC_EOP_PROMPT #language en-US "TXE EOP
> Message"
> +
> +#string STR_PLATFORM_INFORMATION_TITLE #language en-US
> "Platform Information"
> +#string STR_PLATFORM_INFORMATION_HELP #language en-US
> "Display platform information"
> +
> +#string STR_PROCESSOR_INFO_STRING #language en-US
> "Processor Information"
> +#string STR_PROCESSOR_VERSION_STRING #language en-US
> "Processor Type"
> +#string STR_PROCESSOR_VERSION_VALUE #language en-US
> "N/A"
> +#string STR__STRING #language en-US " "
> +#string STR__VALUE #language en-US ""
> +#string STR_PROCESSOR_SPEED_STRING #language en-US
> "Processor Speed"
> +#string STR_PROCESSOR_SPEED_VALUE #language en-US ""
> +#string STR_PROCESSOR_MICROCODE_STRING #language en-US
> "Microcode Revision"
> +#string STR_PROCESSOR_MICROCODE_VALUE #language en-US
> "Not loaded"
> +#string STR_PROCESSOR_CORE_STRING #language en-US
> "Number of Cores"
> +#string STR_PROCESSOR_CORE_VALUE #language en-US "1"
> +#string STR_EM64T_CAPABILITY_STRING #language en-US "Intel(r)
> 64 Architecture Capable"
> +#string STR_EM64T_CAPABILITY_VALUE #language en-US
> "Support"
> +
> +#string STR_PLATFORM_FIRMWARE_STRING #language en-US
> "Platform firmware Information"
> +
> +#string STR_MFGMODE #language en-US "Manufacture
> Mode"
> +#string STR_MFGMODE_HELP #language en-US
> "Manufacture Mode Status"
> +
> +
> +
> +#string STR_MEMORY_INFORMATION_STRING #language en-US
> "Memory Information"
> +#string STR_TOTAL_MEMORY_SIZE_PROMPT #language en-US
> "Total Memory"
> +#string STR_TOTAL_MEMORY_SIZE_VALUE #language en-US ""
> +#string STR_MEMORY_SPEED_PROMPT #language en-US
> "DIMM Frequency"
> +#string STR_MEMORY_SPEED_PROMPT_VALUE #language en-US
> ""
> +#string STR_PROCESSOR_L1_DATA_CACHE_STRING #language en-US
> "L1 Data Cache"
> +#string STR_PROCESSOR_L1_DATA_CACHE_VALUE #language en-US
> "N/A"
> +#string STR_PROCESSOR_L1_INSTR_CACHE_STRING #language en-US
> "L1 Instruction Cache"
> +#string STR_PROCESSOR_L1_INSTR_CACHE_VALUE #language en-US
> "N/A"
> +#string STR_PROCESSOR_L2_CACHE_STRING #language en-US "L2
> Cache RAM"
> +#string STR_PROCESSOR_L2_CACHE_VALUE #language en-US
> "NO"
> +#string STR_SYSTEM_MEMORY_SPEED_STRING #language en-US
> "Memory Speed"
> +#string STR_SYSTEM_MEMORY_SPEED_VALUE #language en-US
> ""
> +
> +#string STR_CHIP_IGD_VBIOS_REV_HELP #language en-US "IGD
> VBIOS Version"
> +#string STR_CHIP_IGD_VBIOS_REV_NAME #language en-US "IGD
> VBIOS Version"
> +#string STR_CHIP_IGD_VBIOS_REV_VALUE #language en-US
> "N/A"
> +
> +#string STR_CPU_FLAVOR_HELP #language en-US "CPU
> Flavor"
> +#string STR_CPU_FLAVOR_NAME #language en-US "CPU
> Flavor"
> +#string STR_CPU_FLAVOR_VALUE #language en-US "N/A"
> +
> +#string STR_BOARD_INFORMATION_STRING #language en-US
> "Board Information"
> +#string STR_BOARD_ID_HELP #language en-US "Displays the
> Board ID."
> +#string STR_BOARD_ID_NAME #language en-US "Board ID"
> +#string STR_BOARD_ID_VALUE #language en-US "N/A"
> +
> +//
> +// CPU INFORMATION
> +//
> +#string STR_CPU_FORM_SUBTITLE #language en-US
> "Processor Information"
> +
> +#string STR_PROCESSOR_VERSION_HELP #language en-US
> "Displays the Processor Type."
> +#string STR_PROCESSOR_VERSION_STRING #language en-US
> "Type"
> +#string STR_PROCESSOR_VERSION_VALUE #language en-US
> "N/A"
> +
> +#string STR_PROCESSOR_SKU_HELP #language en-US "Displays the
> Processor SKU Type."
> +#string STR_PROCESSOR_SKU_STRING #language en-US "SKU Type"
> +#string STR_PROCESSOR_SKU_VALUE #language en-US "N/A"
> +
> +#string STR_PROCESSOR_SPEED_STRING #language en-US
> "Speed"
> +#string STR_PROCESSOR_SPEED_VALUE #language en-US "N/A"
> +#string STR_PROCESSOR_SPEED_HELP #language en-US
> "Displays the Processor Speed."
> +
> +#string STR_PROCESSOR_ID_STRING #language en-US
> "Family/Model/Step"
> +#string STR_PROCESSOR_ID_VALUE #language en-US "N/A"
> +#string STR_PROCESSOR_ID_HELP #language en-US
> "Family/Model/Step of Processor"
> +
> +#string STR_PROCESSOR_STEPPING_STRING #language en-US
> "Stepping"
> +#string STR_PROCESSOR_STEPPING_VALUE #language en-US
> "Unknown"
> +#string STR_PROCESSOR_STEPPING_HELP #language en-US
> "Displays the Processor Stepping."
> +
> +
> +#string STR_FAB_ID_HELP #language en-US "Displays the
> Fab ID"
> +#string STR_FAB_ID_STRING #language en-US "Fab ID"
> +#string STR_FAB_ID_VALUE #language en-US "N/A"
> +
> +#string STR_TIME_PROMPT #language en-US "System
> Time"
> +#string STR_TIME_HOUR_HELP #language en-US "Displays
> and changes the System Time from the Real-Time Clock. Clock is displayed in
> 24-hour format. "
> +#string STR_TIME_MINUTE_HELP #language en-US "Displays
> and changes the System Time from the Real-Time Clock. Clock is displayed in
> 24-hour format. 9"
> +#string STR_TIME_SECOND_HELP #language en-US "Displays
> and changes the System Time from the Real-Time Clock. Clock is displayed in
> 24-hour format. "
> +
> +//
> +// Boot form definition
> +//
> +#string STR_FAST_BOOT_PROMPT #language en-US "Fast
> Boot"
> +#string STR_FAST_BOOT_HELP #language en-US "Enable or
> Disable FastBoot features. \n Most probes are skipped to reduce time cost
> during boot."
> +#string STR_SECURITY_BOOT_PROMPT #language en-US "UEFI
> Security Boot"
> +#string STR_SECURITY_BOOT_HELP #language en-US
> "Disable/Enable UEFI Security boot feature"
> +#string STR_LOG_BOOT_TIME_PROMPT #language en-US
> "BootTime Log"
> +#string STR_LOG_BOOT_TIME_HELP #language en-US
> "BootTime for OS Booting"
> +#string STR_LOG_BOOT_TIME_RECORD #language en-US "
> Latest BootTime"
> +#string STR_LOG_BOOT_TIME_VALUE #language en-US "No
> Record"
> +#string STR_QUIETBOOT_PROMPT #language en-US "Silent
> Boot"
> +#string STR_QUIETBOOT_HELP #language en-US "Disable
> console output and show logo if it is enabled."
> +#string STR_LEGACYUSBBOOTING_PROMPT #language en-US
> "Legacy USB Booting"
> +#string STR_STR_LEGACYUSBBOOTING_HELP #language en-US
> "Enable or Disable Legacy USB Booting features."
> +#string STR_DROIDBOOT_PROMPT #language en-US "Droid
> Boot"
> +#string STR_DROIDBOOT_HELP #language en-US "Go to
> Droidboot to flash Android Image"
> +#string STR_ANDROIDBOOT_PROMPT #language en-US
> "Android Boot"
> +#string STR_ANDROIDBOOT_HELP #language en-US "Boot
> android OS"
> +
> +// Enable or Disable or Automatic
> +#string STR_ENABLE #language en-US "Enable"
> +#string STR_ENABLE #language fr-FR "Activé"
> +
> +#string STR_DISABLE #language en-US "Disable"
> +#string STR_DISABLE #language fr-FR "Désactivé"
> +
> +#string STR_PCI_MODE #language en-US "PCI Mode"
> +#string STR_ACPI_MODE #language en-US "ACPI Mode"
> +
> +#string STR_ENABLED #language en-US "Enabled"
> +#string STR_ENABLED #language fr-FR "Activé"
> +
> +#string STR_DISABLED #language en-US "Disabled"
> +#string STR_DISABLED #language fr-FR "Désactivé"
> +#string STR_AUTOMATIC #language en-US "Auto"
> +#string STR_AUTOMATIC #language fr-FR "Auto"
> +
> +#string STR_ON #language en-US "ON"
> +#string STR_OFF #language en-US "OFF"
> +
> +#string STR_YES #language en-US "YES"
> +#string STR_NO #language en-US "NO"
> +
> +//
> +//CPU Features Configuration
> +//
> +#string STR_ACTIVE_CORE_COUNT_PROMPT #language en-US
> "Active Processor Cores"
> +#string STR_ACTIVE_CORE_COUNT_PROMPT_HELP #language en-US
> "Number of cores to enable in each processor package."
> +
> +#string STR_AESNI_PROMPT #language en-US "AESNI
> Feature"
> +#string STR_AESNI_PROMPT_HELP #language en-US
> "Enable/Disable AESNI ."
> +
> +#string STR_EXECUTE_DISABLE_BIT_PROMPT #language en-US
> "Execute Disable Bit"
> +#string STR_EXECUTE_DISABLE_BIT_HELP #language en-US
> "Execute Disable Bit prevent certain classes of malicious buffer overflow
> attacks when combined with a supporting OS"
> +
> +#string STR_LIMIT_CPUID_MAX_PROMPT #language en-US
> "Limit CPUID Maximum"
> +#string STR_LIMIT_CPUID_MAX_HELP #language en-US
> "Disabled for Windows XP"
> +
> +#string STR_CORE_FRE_MULTIP_SELECT_PROMPT #language en-US
> "Core Frequency Multiplier select"
> +#string STR_CORE_FRE_MULTIP_SELECT_HELP #language en-US
> "for Debug only"
> +
> +#string STR_VTX2_PROMPT #language en-US "VTX-2"
> +#string STR_VTX2_HELP #language en-US "To enable or
> disable the VTX-2 Mode support"
> +
> +#string STR_PROC_HOT_ENABLE #language en-US "Bi-
> directional PROCHOT#"
> +#string STR_PROC_HOT_ENABLE_HELP #language en-US "When
> a processor thermal sensor trips (either core), the PROCHOT# will be
> driven.\nIf bi-direction is enabled, external agents can drive PROCHOT# to
> throttle the processor."
> +#string STR_TM1_PROMPT #language en-US "TM1 "
> +#string STR_TM1_PROMPT_HELP #language en-US
> "Enable/Disable TM1"
> +#string STR_TM2_PROMPT #language en-US "TM2 "
> +#string STR_TM2_PROMPT_HELP #language en-US
> "Enable/Disable TM2"
> +#string STR_DTS_PROMPT #language en-US "DTS "
> +#string STR_DTS_PROMPT_HELP #language en-US
> "Enabled/Disable Digital Thermal Sensor"
> +#string STR_ACTIVE_PROCESSOR_CORES_PROMPT #language en-US
> "Active Processor Cores"
> +#string STR_ACTIVE_PROCESSOR_CORES_HELP #language en-US
> "Number of cores to enable in each processor package"
> +#string STR_PROCESSOR_HT_MODE #language en-US "Intel(r)
> Hyper-Threading Technology"
> +#string STR_PROCESSOR_HT_MODE_HELP #language en-US
> "When disabled, only one thread per active core will be available."
> +#string STR_CAPABILITY_NOT_SUPPORT #language en-US "Not
> Supported"
> +
> +#string STR_ALL #language en-US "ALL"
> +#string STR_1 #language en-US "1"
> +
> +//
> +//CPU Power Option
> +//
> +#string STR_SYSTEM_POWER_OPTIONS #language en-US
> "System Power Options"
> +#string STR_BOOT_P_STATE #language en-US "Boot
> performance mode"
> +#string STR_BOOT_P_STATE_HELP #language en-US "Select
> the performance state that the BIOS will set before OS handoff."
> +#string STR_BOOT_P_STATE_MAX #language en-US "Max
> Performance"
> +#string STR_BOOT_P_STATE_MIN #language en-US "Max
> Battery"
> +#string STR_BOOT_P_STATE_FLEX #language en-US "Flexible
> Ratio(Override)"
> +#string STR_CPU_IST_PROMPT #language en-US "Intel(R)
> SpeedStep(tm)"
> +#string STR_CPU_IST_HELP #language en-US "Allows more
> than two frequency ranges to be supported."
> +#string STR_CSTATE_PROMPT #language en-US "C-States"
> +#string STR_CSTATE_PROMPT_HELP #language en-US
> "Enable/Disable C States"
> +#string STR_CXE_PROMPT #language en-US " Enhanced C-
> states"
> +#string STR_CXE_PROMPT_HELP #language en-US
> "Enable/Disable C1E, C2E and C4E. When enabled, CPU will switch to
> minimum speed when all cores enter C-State."
> +#string STR_HARDC4E_PROMPT #language en-US "Hard C4E"
> +#string STR_HARDC4E_PROMPT_HELP #language en-US
> "Enable/Disable Hard C4E"
> +#string STR_PROCESSOR_TURBO_MODE #language en-US
> "Intel(r) Turbo Boost Technology"
> +#string STR_PROCESSOR_TURBO_MODE_HELP #language en-US
> "Enable to automatically allow processor cores to run faster than the base
> operating frequency if it's operating below power, current, and temperature
> specification limits. Turbo will be disabled under auto mode if SoC is B0
> Stepping"
> +#string STR_MAX_C_STATE_SUPPORT_PROMPT #language en-US
> " Max C State"
> +#string STR_MAX_C_STATE_SUPPORT_HELP #language en-US
> "This option controls the Max C State that the processor will support."
> +#string STR_CSTATE_C7 #language en-US "C7"
> +#string STR_CSTATE_C6 #language en-US "C6"
> +#string STR_CSTATE_C4 #language en-US "C4"
> +#string STR_CSTATE_C1 #language en-US "C1"
> +#string STR_CX_POPDOWN_PROMPT #language en-US "C-
> state POPDOWN"
> +#string STR_CX_POPDOWN_PROMPT_HELP #language en-US
> "Disabling the option, prevents automatic return to a previous C3 or C4
> states"
> +#string STR_CX_POPUP_PROMPT #language en-US "C-state
> POPUP"
> +#string STR_CX_POPUP_PROMPT_HELP #language en-US "On
> enabled, SB observes bus master request, will take system from a C3/C4
> state to a C2 state and auto enables bus masters."
> +#string STR_PPM_C4_EXIT_PROMPT #language en-US "C4 Exit
> Timing"
> +#string STR_PPM_C4_EXIT_HELP #language en-US "This
> option controls a programmable time for the CPU voltage to stabilize when
> exiting from a C4 state."
> +#string STR_PPM_DEFAULT_C4_EXIT #language en-US
> "Default"
> +#string STR_PPM_FAST_C4_EXIT #language en-US "Fast"
> +#string STR_PPM_SLOW_C4_EXIT #language en-US "Slow"
> +#string STR_PPM_FORCE_SLOW_C4_EXIT #language en-US
> "Force Slow"
> +
> +
> +//
> +// IGD Configuration form
> +//
> +#string STR_IGD_LCD_CONTROL #language en-US "IGD - LCD
> Control"
> +#string STR_BOOT_DISPLAY_DEVICE_PROMPT #language en-US
> "IGD Boot Type"
> +#string STR_BOOT_DISPLAY_DEVICE_HELP #language en-US
> "Select preference for Integrated Graphics Device (IGD) display interface
> used when system boots."
> +#string STR_EDP #language en-US "eDP"
> +#string STR_HDMI #language en-US "HDMI"
> +#string STR_MIPI2DSI #language en-US "MIPI-DSI"
> +#string STR_VGAPORT #language en-US "VGA Port"
> +#string STR_HDMIPORTB #language en-US "HDMI"
> +#string STR_DPPORTB #language en-US "DP Port B"
> +#string STR_DPPORTC #language en-US "DP Port C"
> +#string STR_EDPPORTC #language en-US "eDP"
> +#string STR_DSIPORTA #language en-US "DSI PORT A"
> +#string STR_DSIPORTC #language en-US "DSI PORT C"
> +
> +#string STR_IGD_FLAT_PANEL_PROMPT #language en-US "LCD
> Panel Type"
> +#string STR_IGD_FLAT_PANEL_HELP #language en-US "Select
> the LCD panel used by Internal Graphics Device by selecting the appropriate
> setup item."
> +#string STR_640X480 #language en-US "640 x 480"
> +#string STR_800X600 #language en-US "800 x 600"
> +#string STR_1024X768 #language en-US "1024 x 768"
> +#string STR_1280X1024 #language en-US "1280 x 1024"
> +#string STR_1366X768 #language en-US "1366 x 768"
> +#string STR_1680X1050 #language en-US "1680 x 1050"
> +#string STR_1920X1200 #language en-US "1920 x 1200"
> +#string STR_1280X800 #language en-US "1280 x 800"
> +
> +#string STR_IGD_LCD_CONTROL #language en-US "IGD - LCD
> Control"
> +#string STR_IGD_FIXED_GRAPHICS_MEMORY_SIZE #language en-US
> "IGD Fixed Graphics Memory"
> +#string STR_128MB #language en-US "128 MB"
> +#string STR_256MB #language en-US "256 MB"
> +
> +#string STR_IGD_THERMAL_PROMPT #language en-US "IGD
> Thermal"
> +#string STR_IGD_THERMAL_HELP #language en-US "Check to
> enable thermal monitoring on IGD."
> +
> +#string STR_GFX_BOOST_PROMPT #language en-US "GFX
> Boost"
> +#string STR_GFX_BOOST_HELP #language en-US
> "Enable/Disable GFX boost"
> +
> +#string STR_SPREAD_SPECTRUM_CLOCK_PROMPT #language en-US
> "Spread Spectrum clock"
> +#string STR_SPREAD_SPECTRUM_CLOCK_HELP #language en-US
> "Enable/Disable Spread Spectrum clock"
> +
> +#string STR_FORCE_LID_STATUS_PROMPT #language en-US
> "Force Lid Status"
> +#string STR_LID_STATUS__AUTO_PROMPT #language en-US
> "Auto"
> +#string STR_LID_STATUS__ON_PROMPT #language en-US "ON"
> +#string STR_LID_STATUS__OFF_PROMPT #language en-US "OFF"
> +#string STR_FORCE_LID_STATUS_TABLET_HELP #language en-US
> "For test: force to set lid status as on or off"
> +#string STR_FORCE_LID_STATUS_ENBDT_HELP #language en-US
> "For AUTO: BIOS updates LID Status as per Virtual LID Switch. For ON/OFF:
> BIOS force to set lid status as ON or OFF"
> +
> +#string STR_PANNEL_SCALING_PROMPT #language en-US "Panel
> Scaling"
> +#string STR_PANNEL_SCALING_HELP #language en-US "Select
> the LCD panel scaling option used by Internal Graphics Device."
> +#string STR_PANNEL_SCALING_STRETCH #language en-US
> "Centering"
> +#string STR_PANNEL_SCALING_CENTER #language en-US
> "Stretching"
> +
> +#string STR_VIDEO_LCD_IGMCHBLC_PROMPT #language en-US
> "GMCH BLC Control"
> +#string STR_VIDEO_LCD_IGMCHBLC_HELP #language en-US "Back
> Light Control Setting"
> +#string STR_VIDEO_LCD_IGMCHBLC1 #language en-US "PWM-
> Inverted"
> +#string STR_VIDEO_LCD_IGMCHBLC2 #language en-US
> "GMBus-Inverted"
> +#string STR_VIDEO_LCD_IGMCHBLC3 #language en-US "PWM-
> Normal"
> +#string STR_VIDEO_LCD_IGMCHBLC4 #language en-US
> "GMBus-Normal"
> +
> +
> +#string STR_VIDEO_LCD_IBIA #language en-US "BIA"
> +#string STR_VIDEO_LCD_IBIAA #language en-US "Auto"
> +#string STR_VIDEO_LCD_IBIAD #language en-US "Disabled"
> +#string STR_VIDEO_LCD_IBIAL1 #language en-US "Level 1"
> +#string STR_VIDEO_LCD_IBIAL2 #language en-US "Level 2"
> +#string STR_VIDEO_LCD_IBIAL3 #language en-US "Level 3"
> +#string STR_VIDEO_LCD_IBIAL4 #language en-US "Level 4"
> +#string STR_VIDEO_LCD_IBIAL5 #language en-US "Level 5"
> +#string STR_VIDEO_LCD_IBIAHLP #language en-US ">>Auto:
> GMCH Use VBIOS Default; >>Level n: Enabled with Selected
> Aggressiveness Level."
> +
> +#string STR_PRIMARY_DISPLAY #language en-US "Primary
> Display"
> +#string STR_PRIMARY_DISPLAY_HELP #language en-US "Select
> which of IGD/PCI Graphics device should be Primary Display"
> +#string STR_IGD_STRING #language en-US "IGD"
> +#string STR_PCI_STRING #language en-US "PCIe"
> +
> +#string STR_VIDEO_RS2_PROMPT #language en-US
> "RC6(Render Standby)"
> +#string STR_VIDEO_RS2_HELP #language en-US "Check to
> enable render standby support, RC6 should be enabled if S0ix is
> enabled.\n\nThis item will be read only if S0ix is enabled"
> +
> +#string STR_PAVC_PROMPT #language en-US "PAVC"
> +#string STR_PAVC_HELP #language en-US "Enable/Disable
> Protected Audio Video Control"
> +#string STR_PAVP_LITE_MODE #language en-US "LITE Mode"
> +#string STR_PAVP_SERPENT_MODE #language en-US
> "SERPENT Mode"
> +#string STR_DVMT40_TITLE #language en-US "DVMT4.0
> Graphic memory setting"
> +#string STR_DVMT40_PRE_ALLOC #language en-US "DVMT
> Pre-Allocated"
> +#string STR_DVMT40_PRE_ALLOC_1M #language en-US "1M"
> +#string STR_DVMT40_PRE_ALLOC_8M #language en-US "8M"
> +#string STR_DVMT40_PRE_ALLOC_HELP #language en-US "Select
> DVMT 4.0 Pre-Allocated (UMA) Graphics Memory size used by the Internal
> Graphics Device."
> +#string STR_LOCK_ECO_PROMPT #language en-US "ECO
> Lock"
> +#string STR_LOCK_ECO_HELP #language en-US
> "Enable/Disable ECO Lock"
> +#string STR_DOP_CG_PROMPT #language en-US "DOP CG"
> +#string STR_DOP_CG__HELP #language en-US
> "Enable/Disable DOP Clock Gating"
> +
> +//
> +// DVMT5.0 Graphics Memory
> +//
> +#string STR_DVMT50_TITLE #language en-US "DVMT5.0 Graphic
> memory setting"
> +#string STR_DVMT50_PRE_ALLOC #language en-US "DVMT Pre-
> Allocated"
> +#string STR_DVMT50_PRE_ALLOC_0M #language en-US "0M"
> +#string STR_DVMT50_PRE_ALLOC_32M #language en-US "32M"
> +#string STR_DVMT50_PRE_ALLOC_64M #language en-US "64M"
> +#string STR_DVMT50_PRE_ALLOC_96M #language en-US "96M"
> +#string STR_DVMT50_PRE_ALLOC_128M #language en-US "128M"
> +#string STR_DVMT50_PRE_ALLOC_160M #language en-US "160M"
> +#string STR_DVMT50_PRE_ALLOC_192M #language en-US "192M"
> +#string STR_DVMT50_PRE_ALLOC_224M #language en-US "224M"
> +#string STR_DVMT50_PRE_ALLOC_256M #language en-US "256M"
> +#string STR_DVMT50_PRE_ALLOC_288M #language en-US "288M"
> +#string STR_DVMT50_PRE_ALLOC_320M #language en-US "320M"
> +#string STR_DVMT50_PRE_ALLOC_352M #language en-US "352M"
> +#string STR_DVMT50_PRE_ALLOC_384M #language en-US "384M"
> +#string STR_DVMT50_PRE_ALLOC_416M #language en-US "416M"
> +#string STR_DVMT50_PRE_ALLOC_448M #language en-US "448M"
> +#string STR_DVMT50_PRE_ALLOC_480M #language en-US "480M"
> +#string STR_DVMT50_PRE_ALLOC_512M #language en-US "512M"
> +
> +#string STR_DVMT50_PRE_ALLOC_HELP #language en-US "Select
> DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal
> Graphics Device"
> +#string STR_DVMT50_DVMT #language en-US "DVMT Total Gfx
> Mem"
> +#string STR_DVMT50_DVMT_HELP #language en-US "Select
> DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device"
> +#string STR_DVMT50_ALLOC_128 #language en-US "128M"
> +#string STR_DVMT50_ALLOC_256 #language en-US "256M"
> +#string STR_DVMT50_ALLOC_MAX #language en-US "MAX"
> +#string STR_GTT_SIZE #language en-US "GTT Size"
> +#string STR_GTT_SIZE_HELP #language en-US "Select the GTT
> Size "
> +#string GTT_SIZE_1MB #language en-US "1MB"
> +#string GTT_SIZE_2MB #language en-US "2MB"
> +#string STR_APERTURE_SIZE #language en-US "Aperture Size"
> +#string STR_APERTURE_SIZE_HELP #language en-US "Select the
> Aperture Size"
> +#string APERTURE_SIZE_128MB #language en-US "128MB"
> +#string APERTURE_SIZE_256MB #language en-US "256MB"
> +#string APERTURE_SIZE_512MB #language en-US "512MB"
> +
> +#string STR_IGD_PROMPT #language en-US "Integrated
> Graphics Device"
> +#string STR_IGD_HELP #language en-US "Enable : Enable
> Integrated Graphics Device (IGD) when selected as the Primary Video
> Adaptor. Disable: Alwarys disable IGD"
> +
> +#string STR_ACPI_ALS_ENABLE #language en-US "ALS
> Support"
> +#string STR_ACPI_ALS_ENABLE_HELP #language en-US "Valid
> only for ACPI."
> +
> +#string STR_SEC_CONFIGURATION_SUBTITLE #language en-US "TXE
> Configuration"
> +
> +#string STR_SEC_SETTING_PROMPT #language en-US "TXE"
> +#string STR_SEC_SETTING_HELP #language en-US ""
> +
> +#string STR_TPM_CONFIGURATION_PROMPT #language en-US
> "TPM Configuration"
> +
> +#string STR_FIRMWARE_TPM_PROMPT #language en-US
> "fTPM"
> +#string STR_FIRMWARE_TPM_HELP #language en-US
> "Enable/Disable fTPM"
> +
> +#string STR_PTT_PROMPT #language en-US "PTT"
> +#string STR_PTT_HELP #language en-US "Enable/Disable
> PTT"
> +
> +#string STR_TPM_PROMPT #language en-US "Discrete
> TPM"
> +#string STR_TPM_HELP #language en-US "Enable/Disable
> TPM"
> +
> +#string STR_MEASURED_BOOT_ENABLE_PROMPT #language en-US
> "Measured Boot"
> +#string STR_MEASURED_BOOT_ENABLE_HELP #language en-US
> "Enable/Disable Measured Boot"
> +
> +#string STR_SEC_FLASH_UPDATE_PROMPT #language en-US "TXE
> HMRFPO "
> +#string STR_SEC_FLASH_UPDATE_HELP #language en-US ""
> +
> +#string STR_SEC_FIRMWARE_UPDATE_PROMPT #language en-US
> "TXE Firmware Update"
> +#string STR_SEC_FIRMWARE_UPDATE_HELP #language en-US ""
> +#string STR_SEC_UNCONFIGURATION_PROMPT #language en-US
> "TXE Unconfiguration Perform"
> +#string STR_SEC_UNCONFIGURATION_HELP #language en-US
> "Revert TXE settings to factory defaults"
> +#string STR_PTT_SUBTITLE #language en-US "Platform Trust
> Technology"
> +#string STR_PTT_DISABLE_PROMPT #language en-US "PTT
> Disable"
> +#string STR_PTT_DISABLE_HELP #language en-US "Disable PTT
> "
> +
> +#string STR_REVOKE_TRUST_PROMPT #language en-US
> "Revoke Trust"
> +#string STR_REVOKE_TRUST_HELP #language en-US
> "Enable/Disable Revoke Trust"
> +
> +#string STR_PASSWORD_CONFIGURATION_SUBTITLE #language en-
> US "Password Setting"
> +#string STR_PASSWORD_CONFIGURATION_HELP #language en-US
> "Password Setting"
> +
> +#string STR_TDT_TITLE #language en-US "Intel(R) Anti-
> Theft Technology Configuration"
> +
> +#string STR_TDT_CONFIG_PROMPT #language en-US "Intel(R)
> ATAM"
> +#string STR_TDT_CONFIG_HELP #language en-US
> "Enable/Disable BIOS AT Code from Running."
> +
> +#string STR_PBA_CONFIG_PROMPT #language en-US "Intel(R)
> AT Platform PBA"
> +#string STR_PBA_CONFIG_HELP #language en-US
> "Enable/Disable BIOS AT Code from Running."
> +
> +#string STR_TDT_RECOVERY_PROMPT #language en-US "AT
> Recovery"
> +#string STR_TDT_RECOVERY_HELP #language en-US "Set the
> number of times AT Recovery attempts will be allowed"
> +
> +#string STR_TDT_SUSPEND_PROMPT #language en-US "Intel(R)
> AT Suspend Mode"
> +#string STR_TDT_SUSPEND_HELP #language en-US "Request
> that platform enter AT Suspend Mode - Only Available when AT Enrolled"
> +
> +#string STR_ADMIN_PASSWORD #language en-US "Setup
> Administrator Password"
> +#string STR_ADMIN_PASSWORD_HELP #language en-US "Set
> Setup Administrator Password"
> +#string STR_USER_PASSWORD #language en-US "User
> Password"
> +#string STR_USER_PASSWORD_HELP #language en-US "Set
> User Password"
> +#string STR_CHANGE_ADMIN_PASSWORD #language en-US
> "Change Supervisor Password"
> +#string STR_CHANGE_ADMIN_PASSWORD_HELP #language en-US
> "Change Setup Administrator Password"
> +#string STR_CHANGE_USER_PASSWORD #language en-US
> "Change User Password"
> +#string STR_CHANGE_USER_PASSWORD_HELP #language en-US
> "Change User Password"
> +#string STR_SB_TITLE #language en-US "Secure Boot
> Configuration"
> +#string STR_CHECK_SHA256_HASH_MASTER_BOOT_CODES #language
> en-US "Check SHA256 Hash of Master Boot Codes"
> +#string STR_CHECK_SHA256_HASH_MASTER_BOOT_CODES_HELP
> #language en-US "Enable/Disable the checking of SHA256 hash of Master
> Boot Codes"
> +//
> +//South Cluster Configuration
> +//
> +#string STR_HPET_PROMPT #language en-US "High Precision
> Timer"
> +#string STR_HPET_HELP #language en-US "Enable or
> Disable the High Precision Event Timer."
> +#string STR_HPET_BOOTTIME_PROMPT #language en-US "Boot
> Time with HPET Timer"
> +#string STR_HPET_BOOTTIME_HELP #language en-US "Boot
> time calculation with High Precision Event Timer enabled."
> +
> +#string STR_HPET_SUBTITLE #language en-US "High Precision
> Event Timer Configuration"
> +
> +#string STR_USB_CONFIG_SUBTITLE #language en-US "USB
> Configuration"
> +#string STR_USB_DEBUG_PROMPT #language en-US "USB
> Debug"
> +#string STR_USB_DEBUG_HELP #language en-US "Enable or
> Disable USB debug feature"
> +#string STR_USB_XHCI_SUPPORT_PROMPT #language en-US
> "XHCI Controller"
> +#string STR_USB_XHCI_SUPPORT_HELP #language en-US
> "Enable/Disable XHCI Controller "
> +
> +#string STR_USB_HSIC_0_PROMPT #language en-US " HSIC #0"
> +#string STR_USB_HSIC_0_HELP #language en-US
> "Enable/Disable HSIC #0. Enabling HSIC #0 will also enable USB4640 USB HUB
> with an useless card reader and impact responsiveness."
> +
> +#string STR_USB_XHCI_LPM_SUPPORT_PROMPT #language en-US
> "USB2 Link Power Management"
> +#string STR_USB_XHCI_LPM_SUPPORT_HELP #language en-US
> "Enable/Disable USB2 Link Power Management "
> +
> +#string STR_USB_AUTO_MODE_PROMPT #language en-US "USB
> Controller Auto Mode"
> +#string STR_USB_AUTO_MODE_HELP #language en-US "If
> enabled, EHCI is enabled as default for A0. For A1 and later, XHCI is enabled
> as default."
> +
> +#string STR_PCH_USB30_MODE_PROMPT #language en-US
> "XHCI Mode"
> +#string STR_PCH_USB30_MODE_HELP #language en-US "Mode
> of operation of xHCI controller."
> +#string STR_PCH_USB30_STREAMS #language en-US "XHCI
> Streams"
> +#string STR_PCH_USB30_STREAMS_HELP #language en-US
> "Enable/Disable XHCI Streams"
> +//
> +// USB Devices
> +//
> +#string STR_USB_OPTIONS_FORM_TITLE #language en-US "USB
> Configuration"
> +#string STR_USB_OPTIONS_FORM_HELP #language en-US "USB
> Configuration Settings"
> +
> +#string STR_PCH_USB21_PROMPT #language en-US "EHCI
> Controller"
> +#string STR_PCH_USB2_HELP #language en-US "Control the
> USB EHCI (USB 2.0) functions."
> +#string STR_PCH_USB_PER_PORT_PROMPT #language en-US
> "USB Per-Port Control"
> +#string STR_PCH_USB_PER_PORT_HELP #language en-US
> "Control each of the USB ports (0~3) enable/disable"
> +#string STR_PCH_USB_PORT0_PROMPT #language en-US "USB
> Port #0"
> +#string STR_PCH_USB_PORT1_PROMPT #language en-US "USB
> Port #1"
> +#string STR_PCH_USB_PORT2_PROMPT #language en-US "USB
> Port #2"
> +#string STR_PCH_USB_PORT3_PROMPT #language en-US "USB
> Port #3"
> +#string STR_PCH_USB_PORT4_PROMPT #language en-US "USB
> Port #4"
> +#string STR_PCH_USB_PORT5_PROMPT #language en-US "USB
> Port #5"
> +#string STR_PCH_USB_PORT6_PROMPT #language en-US "USB
> Port #6"
> +#string STR_PCH_USB_PORT7_PROMPT #language en-US "USB
> Port #7"
> +#string STR_PCH_USB_PORT_DIS_HELP #language en-US
> "Enable/Disable USB port"
> +#string STR_PCH_USBRMH_PROMPT #language en-US "USB
> RMH Mode"
> +#string STR_PCH_USBRMH_HELP #language en-US
> "Enable/Disable PCH USB Rate Matching Hubs mode"
> +#string STR_PCH_USB_EHCIDEBUG_PROMPT #language en-US
> "USB EHCI debug"
> +#string STR_PCH_USB_EHCIDEBUG_HELP #language en-US
> "Enable/Disable PCH EHCI debug capability"
> +
> +#string STR_PCH_USB_OTG_PROMPT #language en-US "USB
> OTG Support"
> +#string STR_PCH_USB_OTG_HELP #language en-US
> "Enable/Disable USB OTG Support"
> +#string STR_PCH_USB_VBUS_PROMPT #language en-US "USB
> VBUS"
> +#string STR_PCH_USB_VBUS_HELP #language en-US "VBUS
> should be ON in HOST mode. It should be OFF in OTG device mode. VBUS is
> forced to Auto mode for FFRD-PR1 since FSA mux will control it."
> +#string STR_PCH_FSA_PROMPT #language en-US "FSA ON"
> +#string STR_PCH_FSA_HELP #language en-US "FSA should be
> ON for PR1"
> +
> +#string STR_PCI_MODE_STRING #language en-US "PCI Mode"
> +#string STR_ACPI_MODE_STRING #language en-US "ACPI
> Mode"
> +
> +#string STR_SMARTAUTO_STRING #language en-US "Smart
> Auto"
> +
> +#string STR_DEVICE_SUBTITLE #language en-US "Onboard
> Devices"
> +
> +#string STR_LAN_PROMPT #language en-US "LAN"
> +#string STR_LAN_HELP #language en-US "Enables or
> Disables the Onboard LAN Controller."
> +
> +//
> +// GbE
> +//
> +#string STR_LAN_OPTIONS_FORM_TITLE #language en-US "LAN
> Configuration"
> +#string STR_LAN_OPTIONS_FORM_HELP #language en-US "LAN
> Configuration Settings"
> +
> +#string STR_PCH_LAN_CONTROLLER #language en-US "LAN
> Controller"
> +#string STR_PCH_LAN_CONTROLLER_HELP #language en-US
> "Enable/Disable onboard NIC"
> +#string STR_PCH_LAN_WOL_PROMPT #language en-US "
> Wake on LAN Enable"
> +#string STR_PCH_LAN_WOL_HELP #language en-US
> "Enable/Disable integrated LAN to wake the system"
> +#string STR_PCH_SLP_LAN_LOW_DC_PROMPT #language en-US "
> SLP_LAN# Low on DC Power"
> +#string STR_PCH_SLP_LAN_LOW_DC_HELP #language en-US
> "Enable/Disable SLP_LAN# Low on DC Power"
> +
> +#string STR_PCH_PXEROM_CONTROL #language en-US "PXE
> ROM"
> +#string STR_PCH_PXEROM_CONTROL_HELP #language en-US
> "Enable/Disable PXE Option ROM execution for onboard LAN"
> +
> +//
> +// Azalia
> +//
> +#string STR_AZALIA_OPTIONS_FORM_TITLE #language en-US
> "Audio Configuration"
> +#string STR_AZALIA_OPTIONS_FORM_HELP #language en-US
> "Audio Configuration Settings"
> +
> +#string STR_PCH_AZALIA_PROMPT #language en-US "Audio
> Controller"
> +#string STR_PCH_AZALIA_HELP #language en-US "Control
> Detection of the Azalia device.\n\nDisabled = Azalia will be unconditionally
> disabled\n\nEnabled = Azalia will be unconditionally Enabled\n\nAuto =
> Azalia will be enabled if present, disabled otherwise"
> +#string STR_PCH_AZALIA_DS_SUPPORT #language en-US
> "Always enable Azalia while Azalia Docking Support is enabled"
> +
> +#string STR_AZALIA_VC_PROMPT #language en-US " Azalia
> VCi Enable"
> +#string STR_AZALIA_VC_HELP #language en-US
> "Enable/Disable Virtual Channel 1 of Audio Controller"
> +#string STR_AZALIA_DS_PROMPT #language en-US " Azalia
> Docking Support Enable"
> +#string STR_AZALIA_DS_HELP #language en-US
> "Enable/Disable Azalia Docking Support of Audio Controller"
> +#string STR_AZALIA_PME_PROMPT #language en-US " Azalia
> PME Enable"
> +#string STR_AZALIA_PME_HELP #language en-US
> "Enable/Disable Power Management capability of Audio Controller"
> +#string STR_HDMI_CODEC_PROMPT #language en-US " Azalia
> HDMI Codec"
> +#string STR_HDMI_CODEC_HELP #language en-US
> "Enable/Disable internal HDMI codec for Azalia"
> +
> +#string STR_HDMI_CODEC_PORTB_PROMPT #language en-US "
> Azalia HDMI codec Port B"
> +#string STR_HDMI_CODEC_PORTC_PROMPT #language en-US "
> Azalia HDMI codec Port C"
> +#string STR_HDMI_CODEC_PORTD_PROMPT #language en-US "
> Azalia HDMI codec Port D"
> +#string STR_HDMI_CODEC_PORT_HELP #language en-US
> "Enable/Disable internal HDMI codec Port for Azalia"
> +//
> +// Misc.
> +//
> +#string STR_MISC_OPTION_FORM_TITLE #language en-US
> "Miscellaneous Configuration"
> +#string STR_MISC_OPTION_FORM_HELP #language en-US
> "Enable/Disable Misc. Features"
> +
> +#string STR_HPET_PROMPT #language en-US "High Precision
> Timer"
> +#string STR_HPET_HELP #language en-US "Enable or
> Disable the High Precision Event Timer"
> +#string STR_HPET_BOOTTIME_PROMPT #language en-US "Boot
> Time with HPET Timer"
> +#string STR_HPET_BOOTTIME_HELP #language en-US "Boot
> time calculation with High Precision Event Timer enabled"
> +
> +
> +#string STR_CLOCK_SPREAD_SPEC_ENABLE #language en-US
> "Clock Spread Spectrum"
> +#string STR_CLOCK_SPREAD_SPEC_ENABLE_HELP #language en-US
> "Enable Clock Chip's Spread Spectrum feature"
> +
> +
> +#string STR_STATE_AFTER_G3 #language en-US "State After
> G3"
> +#string STR_STATE_AFTER_G3_HELP #language en-US "Specify
> what state to go to when power is re-applied after a power failure (G3
> state)"
> +#string STR_S0_AFTER_G3_STRING #language en-US "S0 State"
> +#string STR_S5_AFTER_G3_STRING #language en-US "S5 State"
> +
> +#string STR_PCH_UART_SELECT #language en-US "UART
> Interface Selection"
> +#string STR_PCH_UART_SELECT_HELP #language en-US "Select
> which UART interface to use"
> +#string STR_UART_SELECT_PCU #language en-US "Internal
> UART"
> +#string STR_UART_SELECT_SIO #language en-US "SuperIO
> UART"
> +
> +#string STR_PCU_UART_A #language en-US "PCU UART
> COM 1"
> +#string STR_PCU_UART_A_HELP #language en-US
> "Enable/Disable Onboard PCU UART COM 1"
> +#string STR_PCU_UART_B #language en-US "PCU UART
> COM 2"
> +#string STR_PCU_UART_B_HELP #language en-US
> "Enable/Disable Onboard PCU UART COM 2"
> +
> +#string STR_AUDIO_PROMPT #language en-US "Audio"
> +#string STR_AUDIO_HELP #language en-US "Enables or
> Disables Onboard Audio."
> +
> +#string STR_LPE_PROMPT #language en-US "LPE"
> +#string STR_LPE_HELP #language en-US "Enables or
> Disables Onboard LPE Sub-System."
> +
> +#string STR_GPIO_WAKE_CAPABILITY_ENABLE #language en-US
> "GPIO Wake Capability"
> +#string STR_GPIO_WAKE_CAPABILITY_ENABLE_HELP #language en-US
> "Enable or Disable GPIO Wake Capability"
> +
> +#string STR_RTC_BATTERY #language en-US "RTC Battery
> Presence"
> +#string STR_RTC_BATTERY_PRESENT #language en-US "Present"
> +#string STR_RTC_BATTERY_NOT_PRESENT #language en-US "Not
> Present"
> +#string STR_RTC_BATTERY_HELP #language en-US "RTC Battery
> is Present or Not Present"
> +
> +#string STR_LPE_REPORTED_BY_DSDT_PROMPT #language en-US
> "LPE Audio Reported By DSDT"
> +#string STR_LPE_REPORTED_BY_DSDT_HELP #language en-US
> "Recommended solution is to keep option disabled and expose LPE Audio
> device with an EFI application that updates the SSDT"
> +
> +//
> +// PCI Express
> +//
> +#string STR_PCIE_OPTIONS_FORM_TITLE #language en-US "PCI
> Express Configuration"
> +#string STR_PCIE_OPTIONS_FORM_HELP #language en-US "PCI
> Express Configuration Settings"
> +#string STR_ICH_PCIERP1_PROMPT #language en-US "PCI
> Express Root Port 1"
> +#string STR_ICH_PCIERP2_PROMPT #language en-US "PCI
> Express Root Port 2"
> +#string STR_ICH_PCIERP3_PROMPT #language en-US "PCI
> Express Root Port 3"
> +#string STR_ICH_PCIERP4_PROMPT #language en-US "PCI
> Express Root Port 4"
> +#string STR_ICH_PCIERP_HELP #language en-US "Control the
> PCI Express Root Port."
> +#string STR_ICH_PCIERP_DISABLE_HELP #language en-US "This
> Root Port is disabled because Root Port 1 is disabled."
> +#string STR_PCIEDYNCLK_PROMPT #language en-US "PCI
> Express Dynamic Clock Gating"
> +#string STR_PCIEDYNCLK_HELP #language en-US
> "Enable/Disable PCIE Dynamic Clock Gating"
> +
> +#string STR_IDE_FORM_TITLE #language en-US "SATA Drives"
> +#string STR_IDE_FORM_HELP #language en-US "Press <Enter>
> to select the SATA Device Configuration Setup options."
> +
> +#string STR_DISCRETE_SATA_STRING #language en-US
> "Discrete-SATA Controller Configuration"
> +#string STR_CHIPSET_SATA_STRING #language en-US "Chipset-
> SATA Controller Configuration"
> +
> +#string STR_SATA_PROMPT #language en-US " Chipset
> SATA"
> +#string STR_SATA_HELP #language en-US "Enables or
> Disables the Chipset SATA Controller. The Chipset SATA controller supports
> the 2 black internal SATA ports (up to 3Gb/s supported per port)."
> +
> +#string STR_SATA_TYPE_PROMPT #language en-US " Chipset
> SATA Mode"
> +#string STR_SATA_TYPE_PROMPT #language fr-FR "
> Configurer SATA comme"
> +
> +#string STR_SATA_TYPE_HELP #language en-US "This will
> configure SATA into the corresponding types."
> +#string STR_SATA_TYPE_HELP #language fr-FR "Configure
> SATA selon les types correspondants."
> +#string STR_SATA_TYPE_HELP1 #language en-US "IDE:
> Compatibility mode disables AHCI support. AHCI: Supports advanced SATA
> features such as Native Command Queuing. \nWarning: OS may not boot if
> this setting is changed after OS install."
> +
> +#string STR_SATA_IDE #language en-US "IDE"
> +#string STR_SATA_AHCI #language en-US "AHCI"
> +
> +#string STR_SATA0_STRING #language en-US " SATA Port 0"
> +#string STR_SATA0_STRING #language fr-FR " Port SATA 0"
> +
> +#string STR_SATA0_NAME #language en-US "[Not
> Installed]"
> +#string STR_SATA0_NAME #language fr-FR "[Absent]"
> +
> +#string STR_MSATA_STRING #language en-US " mSATA
> Port"
> +
> +#string STR_SATA1_STRING #language en-US " SATA Port 1"
> +#string STR_SATA1_STRING #language fr-FR " Port SATA 1"
> +
> +#string STR_SATA1_NAME #language en-US "[Not
> Installed]"
> +#string STR_SATA1_NAME #language fr-FR "[Absent]"
> +
> +#string STR_SATA0_HOTPLUG_CAP_PROMPT #language en-US "
> SATA Port 0 Hot Plug Capability"
> +#string STR_SATA1_HOTPLUG_CAP_PROMPT #language en-US "
> SATA Port 1 Hot Plug Capability"
> +#string STR_SATA_HOTPLUG_CAP_HELP #language en-US "If
> enabled, SATA port will be reported as Hot Plug capable."
> +
> +#string STR_SENSOR_FORM_TITLE #language en-US "Sensor
> setting"
> +#string STR_SENSOR_FORM_HELP #language en-US "Press
> <Enter> to select the Sensor Configuration Setup options."
> +
> +//
> +//Sensor Settings
> +//
> +#string STR_SENSOR_SUBTITLE #language en-US "Sensor
> Modules Setting"
> +#string STR_ACCELEROMETER_PROMPT #language en-US
> "Accelerometer"
> +#string STR_ACCELEROMETER_HELP #language en-US "This will
> configure disable/enable Accelerometer."
> +#string STR_GYROMETER_PROMPT #language en-US
> "Gyrometer"
> +#string STR_GYROMETER_HELP #language en-US "This will
> configure disable/enable Gyrometer."
> +#string STR_BAROMETER_PROMPT #language en-US
> "Barometer"
> +#string STR_BAROMETER_HELP #language en-US "This will
> configure disable/enable Barometer."
> +#string STR_PROXIMITY_SENSOR_PROMPT #language en-US
> "Proximity Sensor"
> +#string STR_PROXIMITY_SENSOR_HELP #language en-US "This
> will configure disable/enable Proximity Sensor."
> +#string STR_COMPASS_PROMPT #language en-US
> "Compass"
> +#string STR_COMPASS_HELP #language en-US "This will
> configure disable/enable Compass."
> +#string STR_NFS_PROMPT #language en-US "NFS"
> +#string STR_NFS_HELP #language en-US "This will
> configure disable/enable NFS."
> +
> +#string STR_LPSS_SCC_FORM_TITLE #language en-US "LPSS &
> SCC Configuration"
> +#string STR_LPSS_SCC_FORM_HELP #language en-US ""
> +
> +#string STR_LPSS_PCI_PROMPT #language en-US "LPSS & SCC
> Devices Mode"
> +#string STR_LPSS_PCI_HELP #language en-US
> "Enable/Disable LPSS & SCC Devices Mode"
> +
> +#string STR_SCC_SETTING_SUBTITLE #language en-US "SCC
> Configuration"
> +#string STR_SCC_EMMC_PROMPT #language en-US "SCC
> eMMC Support"
> +#string STR_SCC_EMMC_HELP #language en-US
> "Enable/Disable SCC eMMC Support"
> +#string STR_SCC_SDIO_PROMPT #language en-US "SCC SDIO
> Support "
> +#string STR_SCC_SDIO_HELP #language en-US
> "Enable/Disable SCC SDIO Support"
> +#string STR_SCC_SDCARD_PROMPT #language en-US "SCC SD
> Card Support"
> +#string STR_SCC_SDCARD_HELP #language en-US
> "Enable/Disable SCC SD Card Support"
> +#string STR_SCC_SDCARD_FORWIN_PROMPT #language en-US
> "SCC SD Card for Windows"
> +#string STR_SCC_SDCARD_FORWIN_HELP #language en-US
> "Enable/Disable SCC SD Card for Windows"
> +#string STR_SCC_SDIO_MODE_PROMPT #language en-US "SCC
> SDIO Mode for WIFI"
> +#string STR_SCC_SDIO_MODE_HELP #language en-US "Select
> SDIO mode for WIFI, only for A0/A1 stepping."
> +#string STR_SCC_SDCARD_REMOVABILITY #language en-US "ACPI
> Reporting MMC/SD Media As"
> +#string STR_SCC_SDCARD_REMOVABLE #language en-US
> "Removable"
> +#string STR_SCC_SDCARD_NON_REMOVABLE #language en-US
> "Non-Removable"
> +#string STR_SCC_SDCARD_REMOVABILITY_HELP #language en-US
> "ACPI Reporting MMC/SD Media to Win 8 as non-Removable."
> +
> +#string STR_SDIO_DEFAULT_MODE #language en-US "Default"
> +#string STR_SDIO_DDR50_MODE #language en-US "DDR50"
> +
> +#string STR_LPSS1_SETTING_SUBTITLE #language en-US "LPSS 1
> Configuration"
> +#string STR_LPSS2_SETTING_SUBTITLE #language en-US "LPSS 2
> Configuration"
> +#string STR_LPSS_DMA1_PROMPT #language en-US "LPSS
> DMA #1 Support"
> +#string STR_LPSS_DMA1_HELP #language en-US
> "Enable/Disable LPSS DMA #1 Support"
> +#string STR_LPSS_DMA2_PROMPT #language en-US "LPSS
> DMA #2 Support"
> +#string STR_LPSS_DMA2_HELP #language en-US
> "Enable/Disable LPSS DMA #2 Support"
> +#string STR_LPSS_I2C1_PROMPT #language en-US "LPSS I2C
> #1 Support"
> +#string STR_LPSS_I2C1_HELP #language en-US
> "Enable/Disable LPSS I2C #1 Support"
> +#string STR_LPSS_I2C2_PROMPT #language en-US "LPSS I2C
> #2 Support"
> +#string STR_LPSS_I2C2_HELP #language en-US
> "Enable/Disable LPSS I2C #2 Support"
> +#string STR_LPSS_I2C3_PROMPT #language en-US "LPSS I2C
> #3 Support"
> +#string STR_LPSS_I2C3_HELP #language en-US
> "Enable/Disable LPSS I2C #3 Support"
> +#string STR_LPSS_I2C4_PROMPT #language en-US "LPSS I2C
> #4 Support"
> +#string STR_LPSS_I2C4_HELP #language en-US
> "Enable/Disable LPSS I2C #4 Support"
> +#string STR_LPSS_I2C5_PROMPT #language en-US "LPSS I2C
> #5 Support"
> +#string STR_LPSS_I2C5_HELP #language en-US
> "Enable/Disable LPSS I2C #5 Support"
> +#string STR_LPSS_I2C6_PROMPT #language en-US "Low
> Speed Expansion I2C (#5)"
> +#string STR_LPSS_I2C6_HELP #language en-US
> "Enable/Disable Low Speed Expansion I2C (#5);I2C Controller PCI device
> Dev24: Func6; Schematic names it I2C5, ACPI table names it I2C6"
> +#string STR_LPSS_I2C7_PROMPT #language en-US "High
> Speed Expansion I2C (#6)"
> +#string STR_LPSS_I2C7_HELP #language en-US
> "Enable/Disable High Speed Expansion I2C (#6);I2C Controller PCI device
> Dev24: Func7; Schematic names it I2C6, ACPI table names it I2C7"
> +#string STR_LPSS_I2S_PROMPT #language en-US "LPSS I2S
> Support"
> +#string STR_LPSS_I2S_HELP #language en-US
> "Enable/Disable LPSS I2S Support"
> +#string STR_LPSS_HSUART1_PROMPT #language en-US "LPSS
> HSUART #1 Support"
> +#string STR_LPSS_HSUART1_FLOWCONTROL_PROMPT #language en-
> US "LPSS HSUART #1 FlowCtrl"
> +#string STR_LPSS_HSUART2_FLOWCONTROL_PROMPT #language en-
> US "LPSS HSUART #2 FlowCtrl"
> +#string STR_LPSS_HSUART1_HELP #language en-US
> "Enable/Disable LPSS HSUART #1 Support"
> +#string STR_LPSS_HSUART2_PROMPT #language en-US "LPSS
> HSUART #2 Support"
> +#string STR_LPSS_HSUART2_HELP #language en-US
> "Enable/Disable LPSS HSUART #2 Support"
> +#string STR_LPSS_SPI_PROMPT #language en-US "LPSS SPI
> Support"
> +#string STR_LPSS_SPI_HELP #language en-US
> "Enable/Disable LPSS SPI Support"
> +
> +#string STR_LPSS_I2C1_HELP_ENBDT_DEV_LIST #language en-US
> "Disable/Enable LPSS I2C #1 Support\n\n "
> +#string STR_LPSS_I2C2_HELP_ENBDT_DEV_LIST #language en-US
> "Disable/Enable LPSS I2C #2 Support\n\n "
> +#string STR_LPSS_I2C3_HELP_ENBDT_DEV_LIST #language en-US
> "Disable/Enable LPSS I2C #3 Support\n\n "
> +#string STR_LPSS_I2C4_HELP_ENBDT_DEV_LIST #language en-US
> "Disable/Enable LPSS I2C #4 Support\n\n "
> +#string STR_LPSS_I2C5_HELP_ENBDT_DEV_LIST #language en-US
> "Disable/Enable LPSS I2C #5 Support\n\n "
> +#string STR_LPSS_I2C6_HELP_ENBDT_DEV_LIST #language en-US
> "Enable/Disable Low Speed Expansion I2C (#5);I2C Controller PCI device
> Dev24: Func6; Schematic names it I2C5, ACPI table names it I2C6\n\n "
> +#string STR_LPSS_I2C7_HELP_ENBDT_DEV_LIST #language en-US
> "Enable/Disable High Speed Expansion I2C (#6);I2C Controller PCI device
> Dev24: Func7; Schematic names it I2C6, ACPI table names it I2C7\n\n "
> +#string STR_LPSS_HSUART1_HELP_ENBDT_DEV_LIST #language en-US
> "Disable/Enable LPSS High Speed UART
> #1\n\nEnabled(RX/TX/RTS/CTS)\nW\O
> FlowCtrl(RX/TX+GPIOx2)\nDisabled(GPIOx4)"
> +#string STR_LPSS_HSUART2_HELP_ENBDT_DEV_LIST #language en-US
> "Disable/Enable LPSS High Speed UART
> #2\n\nEnabled(RX/TX/RTS/CTS)\nW\O
> FlowCtrl(RX/TX+GPIOx2)\nDisabled(GPIOx4)"
> +
> +#string STR_I2C_DEVICE_SETTING_SUBTITLE #language en-US "I2C
> Devics Configuration"
> +#string STR_I2C_TOUCH_PROMPT #language en-US "I2C
> Touch Devic Address"
> +#string STR_I2C_TOUCH_HELP #language en-US "I2C Touch
> Address Select:\n RVP/iCDK(0x4B)\n FFRD(0x4A)"
> +#string STR_I2C_FFRD #language en-US "0x4A"
> +#string STR_I2C_FVP #language en-US "0x4B"
> +
> +
> +#string STR_PWM1_PROMPT #language en-US "LPSS PWM
> #1 Support"
> +#string STR_PWM1_HELP #language en-US
> "Enable/DisableLPSS PWM #1 Support"
> +#string STR_PWM2_PROMPT #language en-US "LPSS PWM
> #2 Support"
> +#string STR_PWM2_HELP #language en-US
> Enable/Disable"LPSS PWM #2 Support"
> +#string STR_MIPI_HSI_PROMPT #language en-US "MIPI HSI
> Support"
> +#string STR_MIPI_HSI_HELP #language en-US
> "Enable/Disable MIPI HSI Support \n Note: Official BIOS cannot support MIPI
> display directly even you select enable here. MIPI VBT is specific to different
> panel, user need replace VBT manually."
> +#string STR_LPE_PROMPT #language en-US "LPE Audio
> Support"
> +#string STR_LPE_HELP #language en-US "Enable/Disable
> LPE Audio Support"
> +#string STR_LPE_PCI_MODE #language en-US "LPE Audio
> PCI mode"
> +#string STR_LPE_ACPI_MODE #language en-US "LPE Audio
> ACPI mode"
> +
> +//
> +// ISCT Configuration
> +//
> +#string STR_ISCT_FORM_TITLE #language en-US "ISCT
> Configuration"
> +#string STR_ISCT_FORM_HELP #language en-US "ISCT / AOAC
> Configuration Settings"
> +
> +#string STR_ISCT_CONFIGURATION #language en-US "ISCT
> Configuration"
> +#string STR_ISCT_CONFIGURATION_HELP #language en-US
> "Enable/Disable ISCT Feature"
> +
> +#string STR_ISCT_NOTIFICATION_CONTROL_PROMPT #language en-
> US "ISCT Notification Control"
> +#string STR_ISCT_NOTIFICATION_CONTROL_HELP #language en-US
> "Enable/Disable ISCT Notification Control"
> +#string STR_ISCT_WLAN_CONTROL_PROMPT #language en-US
> "ISCT WLAN Power Control"
> +#string STR_ISCT_WLAN_CONTROL_HELP #language en-US
> "Enable/Disable ISCT WLAN Power Control"
> +#string STR_ISCT_WWAN_CONTROL_PROMPT #language en-US
> "ISCT WWAN Power Control"
> +#string STR_ISCT_WWAN_CONTROL_HELP #language en-US
> "Enable/Disable ISCT WWAN Power Control"
> +
> +#string STR_ISCT_SLEEP_DURATION_FORMAT #language en-US
> "ISCT Sleep Duration Value Format"
> +#string STR_ISCT_SLEEP_DURATION_FORMAT_HELP #language en-US
> "ISCT Sleep Duration is only in Seconds Format, Actual time format is not
> supported"
> +
> +#string STR_ISCT_RF_KILL_SUPPORT #language en-US "ISCT RF
> Kill Support"
> +#string STR_ISCT_RF_KILL_SUPPORT_HELP #language en-US "ISCT
> RF Kill (Radio On/Off) is based on Soft switch, No physical switch available"
> +
> +#string STR_SECONDS #language en-US "Seconds"
> +#string STR_ACTUAL_TIME #language en-US "Actual Time"
> +
> +#string STR_RF_KILL_SOFT #language en-US "Soft Switch"
> +#string STR_RF_KILL_PHYSICAL #language en-US "Physical
> Switch"
> +
> +#string STR_WLAN_PRESENCE_FORM_TITLE #language en-US
> "WLAN Card Presence"
> +#string STR_WLAN_NGFF_CARD #language en-US "NGFF Card
> Inserted"
> +#string STR_WLAN_NGFF_HELP #language en-US "Set 'YES' If
> NGFF Card is Inserted"
> +#string STR_WLAN_UHPAM_CARD #language en-US "UHPAM
> Card Inserted"
> +#string STR_WLAN_UHPAM_HELP #language en-US "Set 'YES'
> If UHPAM Card is Inserted"
> +
> +//
> +// THERMAL INFORMATION
> +//
> +
> +//
> +// S0iX supported or not
> +//
> +#string STR_S0IX_PROMPT #language en-US "S0ix"
> +#string STR_S0IX_HELP #language en-US "Set platform to
> configure S0ix supported or not"
> +
> +#string STR_THERMAL_CONFIGURATION #language en-US
> "Processor Participant"
> +#string STR_THERMAL_CONFIGURATION_HELP #language en-US
> "Thermal Configuration Parameters"
> +
> +
> +#string STR_ACPI_PASSIVE_THERMAL_TRIP_POINT #language en-US
> "Passive Trip Point"
> +#string STR_ACPI_PASSIVE_THERMAL_TRIP_POINT_HELP #language en-
> US "This value controls the temperature of the ACPI Passive Trip Point - the
> point in which the OS will begin throttling the processor."
> +#string STR_ACPI_CRITICAL_THERMAL_TRIP_POINT #language en-US
> "Critical Trip Point"
> +#string STR_ACPI_CRITICAL_THERMAL_TRIP_POINT_HELP #language en-
> US "This value controls the temperature of the ACPI Critical Trip Point - the
> point in which the OS will shut the system off."
> +#string STR_15_C #language en-US "15 C"
> +#string STR_23_C #language en-US "23 C"
> +#string STR_31_C #language en-US "31 C"
> +#string STR_39_C #language en-US "39 C"
> +#string STR_47_C #language en-US "47 C"
> +#string STR_55_C #language en-US "55 C"
> +#string STR_63_C #language en-US "63 C"
> +#string STR_71_C #language en-US "71 C"
> +#string STR_79_C #language en-US "79 C"
> +#string STR_85_C #language en-US "85 C"
> +#string STR_87_C #language en-US "87 C"
> +#string STR_90_C #language en-US "90 C"
> +#string STR_95_C #language en-US "95 C"
> +#string STR_100_C #language en-US "100 C"
> +#string STR_103_C #language en-US "103 C"
> +#string STR_105_C #language en-US "105 C"
> +#string STR_110_C #language en-US "110 C"
> +#string STR_111_C #language en-US "111 C"
> +#string STR_119_C #language en-US "119 C"
> +#string STR_180_C #language en-US "180 C"
> +#string STR_200_C #language en-US "200 C"
> +#string STR_POR #language en-US "POR"
> +#string STR_0LEN #language en-US ""
> +
> +#string STR_ACPI_PASSIVE_TC1_VALUE #language en-US "
> Passive TC1 Value"
> +#string STR_ACPI_PASSIVE_TC1_VALUE_HELP #language en-US
> "This value sets the TC1 value for the ACPI Passive Cooling Formula. Range 1 -
> 16"
> +#string STR_ACPI_PASSIVE_TC2_VALUE #language en-US "
> Passive TC2 Value"
> +#string STR_ACPI_PASSIVE_TC2_VALUE_HELP #language en-US
> "This value value sets the TC2 value for the ACPI Passive Cooling Formula.
> Range 1 - 16"
> +#string STR_ACPI_PASSIVE_TSP_VALUE #language en-US "
> Passive TSP Value"
> +#string STR_ACPI_PASSIVE_TSP_VALUE_HELP #language en-US
> "This item sets the TSP value for the ACPI Passive Cooling Formula. It
> represents in tenths of a second how often the OS will read the temperature
> when passive cooling is enabled. Range 2 - 32"
> +
> +#string STR_DPTF_CONFIGURATION #language en-US "DPTF
> Configuration"
> +
> +#string STR_DATP_PROMPT #language en-US "Active Trip
> Points"
> +#string STR_DATP_HELP #language en-US "Disable Active
> Trip Points"
> +
> +
> +//
> +// DPTF Form
> +//
> +#string STR_DPTF_PROMPT #language en-US "DPTF"
> +#string STR_DPTF_HELP #language en-US "Enable/Disable
> DPTF"
> +#string STR_ACTIVE_PROMPT #language en-US "Active"
> +#string STR_ACTIVE_HELP #language en-US ""
> +#string STR_CTDP_PROMPT #language en-US "CTDP"
> +#string STR_CTDP_HELP #language en-US ""
> +#string STR_COOLING_MODE_PROMPT #language en-US
> "Cooling Mode"
> +#string STR_COOLING_MODE_HELP #language en-US ""
> +#string STR_CRITICAL_PROMPT #language en-US "Critical"
> +#string STR_CRITICAL_HELP #language en-US ""
> +
> +#string STR_DPTF_CLPM_PROMPT #language en-US "CLPM"
> +
> +#string STR_DPTF_CLPM_HELP #language en-US "Current
> Low Power Mode"
> +
> +#string STR_DPTF_LPM_APP #language en-US "Application
> specific"
> +
> +#string STR_DPTF_LPM_OS #language en-US "OS level"
> +
> +#string STR_DPTF_SYSTHERM0_PROMPT #language en-US "T1
> Sensor" // Skin Temperature Sensor 0
> +#string STR_DPTF_SYSTHERM0_HELP #language en-US
> "Enable/Disable T1 skin sensor"
> +#string STR_DPTF_THERM0_PCAT_PROMPT #language en-US
> "CPU Sensors"
> +#string STR_DPTF_THERM0_PCAT_HELP #language en-US
> "Enable/Disable CPU Temperature Sensors"
> +
> +#string STR_DPTF_SYSTHERM1_PROMPT #language en-US
> "Display Board Sensor" //System Thermal Sensor 1
> +#string STR_DPTF_SYSTHERM1_HELP #language en-US
> "Enable/Disable Display Board skin Sensor"
> +#string STR_DPTF_THERM1_PCAT_PROMPT #language en-US
> "Ambient Sensors"
> +#string STR_DPTF_THERM1_PCAT_HELP #language en-US
> "Enable/Disable Ambient Temperature Sensors"
> +
> +#string STR_DPTF_SYSTHERM2_PROMPT #language en-US "SOC
> Board Sensor" //System Thermal Sensor 2
> +#string STR_DPTF_SYSTHERM2_HELP #language en-US
> "Enable/Disable SOC Board skin Sensor"
> +#string STR_DPTF_THERM2_PCAT_PROMPT #language en-US
> "DDR Sensors"
> +#string STR_DPTF_THERM2_PCAT_HELP #language en-US
> "Enable/Disable DDR Temperature Sensors"
> +
> +#string STR_DPTF_SYSTHERM3_PROMPT #language en-US
> "Charger Board Sensor" //System Thermal Sensor 3
> +#string STR_DPTF_SYSTHERM3_HELP #language en-US
> "Enable/Disable ULPMC Skin Temperature Sensor"
> +#string STR_DPTF_SYSTHERM4_PROMPT #language en-US
> "Ambient Temperature"
> +#string STR_DPTF_SYSTHERM4_HELP #language en-US
> "Enable/Disable Ambient Temperature"
> +#string STR_DPTF_AMBIENTTRIPPOINTCHANGE_PROMPT #language
> en-US "Ambient based Trip Point Change"
> +#string STR_DPTF_AMBIENTTRIPPOINTCHANGE_HELP #language en-
> US "This controls the Action part of the Ambient participant. When disabled,
> trip points would not be changed when Ambient participant notifies the FW
> of a new ambient temperature via _ATI."
> +#string STR_DPTF_ALLOWHIGHERPERFORMANCE_PROMPT #language
> en-US "Allow higher performance on AC/USB"
> +#string STR_DPTF_ALLOWHIGHERPERFORMANCE_HELP #language en-
> US "On AC/USB power source allow for higher performance and relax tablet
> skin temperature to higher limits. Warning: Note users may feel warm tablet
> skin."
> +#string STR_DPTF_CHARGER_PROMPT #language en-US
> "Charger Participant"
> +#string STR_DPTF_CHARGER_HELP #language en-US
> "Enable/Disable Charger Participant Device"
> +#string STR_DPTF_DISPLAY_PROMPT #language en-US "Display
> Participant"
> +#string STR_DPTF_DISPLAY_HELP #language en-US
> "Enable/Disable Display Participant Device"
> +#string STR_DPTF_SOC_PROMPT #language en-US "Power
> Participant"
> +#string STR_DPTF_SOC_HELP #language en-US
> "Enable/Disable Power Participant Device"
> +#string STR_PROCESSOR_DPTF_PROMPT #language en-US "DPTF
> Processor"
> +#string STR_PROCESSOR_DPTF_HELP #language en-US
> "Enable/Disable Processor Participant Device"
> +
> +#string STR_PASSIVE_PROMPT #language en-US "Passive"
> +#string STR_PASSIVE_HELP #language en-US ""
> +
> +#string STR_DPTF_GENERIC_PARTICIPANT #language en-US "DPTF
> Generic Sensor Participant"
> +#string STR_DPTF_CRITICAL_TEMP #language en-US "Critical"
> +#string STR_DPTF_PASSIVE_TEMP #language en-US "Passive"
> +#string STR_DPTF_CRITICAL_TEMP_HELP #language en-US
> "Critical Temperature"
> +#string STR_DPTF_PASSIVE_TEMP_HELP #language en-US
> "Passive Temperature"
> +#string STR_DPTF_25_C #language en-US "25 C"
> +#string STR_DPTF_30_C #language en-US "30 C"
> +#string STR_DPTF_35_C #language en-US "35 C"
> +#string STR_DPTF_40_C #language en-US "40 C"
> +#string STR_DPTF_45_C #language en-US "45 C"
> +#string STR_DPTF_50_C #language en-US "50 C"
> +#string STR_DPTF_55_C #language en-US "55 C"
> +#string STR_DPTF_60_C #language en-US "60 C"
> +#string STR_DPTF_65_C #language en-US "65 C"
> +#string STR_DPTF_70_C #language en-US "70 C"
> +#string STR_DPTF_75_C #language en-US "75 C"
> +#string STR_DPTF_80_C #language en-US "80 C"
> +#string STR_DPTF_85_C #language en-US "85 C"
> +#string STR_DPTF_90_C #language en-US "90 C"
> +#string STR_DPTF_95_C #language en-US "95 C"
> +#string STR_DPTF_100_C #language en-US "100 C"
> +#string STR_DPTF_105_C #language en-US "105 C"
> +#string STR_DPTF_110_C #language en-US "110 C"
> +#string STR_DPTF_115_C #language en-US "115 C"
> +#string STR_DPTF_120_C #language en-US "120 C"
> +#string STR_DPTF_125_C #language en-US "125 C"
> +#string STR_DPTF_52_C #language en-US "52 C"
> +#string STR_DPTF_61_C #language en-US "61 C"
> +#string STR_DPTF_64_C #language en-US "64 C"
> +#string STR_DPTF_43_C #language en-US "43 C"
> +#string STR_DPTF_57_C #language en-US "57 C"
> +#string STR_DPTF_62_C #language en-US "62 C"
> +#string STR_DPTF_78_C #language en-US "78 C"
> +#string STR_DPTF_81_C #language en-US "81 C"
> +
> +#string STR_DPTF_GENERIC0_PART_PCAT #language en-US "CPU
> Sensor Participants"
> +#string STR_DPTF_GENERIC1_PART_PCAT #language en-US
> "Ambient Sensor Participants"
> +#string STR_DPTF_GENERIC2_PART_PCAT #language en-US "DDR
> Sensor Participants"
> +#string STR_DPTF_GENERIC0_PARTICIPANT #language en-US
> "DPTF T1 Sensor Participant"
> +#string STR_DPTF_GENERIC1_PARTICIPANT #language en-US
> "DPTF Display Board Sensor Participant"
> +#string STR_DPTF_GENERIC2_PARTICIPANT #language en-US
> "DPTF SOC Board Sensor Participant"
> +#string STR_DPTF_SDP #language en-US "Scenario Design
> Power"
> +
> +#string STR_DPTF_BRAND_STRING #language en-US "Brand
> String"
> +#string STR_DPTF_BRAND_STRING_HELP #language en-US
> "Brand string for the processor, example Nxxx or Jxxx"
> +
> +#string STR_DPTF_N3510 #language en-US "N3510/20"
> +#string STR_DPTF_N2910 #language en-US "N2910/20"
> +#string STR_DPTF_N2810 #language en-US "N2810/15/20"
> +#string STR_DPTF_N2805 #language en-US "N2805/06"
> +#string STR_DPTF_J2850 #language en-US "J2850/2900"
> +#string STR_DPTF_J1850 #language en-US "J1850/1900"
> +#string STR_DPTF_J1750 #language en-US "J1750/1800"
> +
> +#string STR_DPTF_GENERIC3_PARTICIPANT #language en-US
> "DPTF Charger Board Sensor Participant"
> +#string STR_DPTF_GENERIC4_PARTICIPANT #language en-US
> "DPTF Generic Sensor4 Participant"
> +#string STR_DPTF_CRITICAL_TEMP #language en-US "Critical"
> +#string STR_DPTF_PASSIVE_TEMP #language en-US "Passive"
> +#string STR_DPTF_CRITICAL_TEMP_HELP #language en-US
> "Critical Temperature"
> +#string STR_DPTF_PASSIVE_TEMP_HELP #language en-US
> "Passive Temperature"
> +#string STR_DPTF_CLPM #language en-US "CLPM"
> +#string STR_DPTF_CLPM_HELP #language en-US "Current
> Low Power Mode"
> +#string STR_DPTF_LPM_APP #language en-US "Application
> specific"
> +#string STR_DPTF_LPM_OS #language en-US "OS level"
> +#string STR_DPTF_SDBG #language en-US "Super Debug"
> +#string STR_DPTF_SDBG_HELP #language en-US "Super
> debug is for validation purpose"
> +#string STR_DPTF_OFFLINING #language en-US "Processor
> Offlining"
> +#string STR_DPTF_OFFLINING_HELP #language en-US "Enable
> or disable processor offlining, passive policy only"
> +#string STR_DPTF_CLPO #language en-US "Current Logical
> Processor Offlining"
> +#string STR_DPTF_CLPO_HELP #language en-US "Controls
> LPO Control preferences. Used only by Passive policy"
> +#string STR_DPTF_CLPO_START_PINDEX #language en-US "Start
> P-State"
> +#string STR_DPTF_CLPO_START_PINDEX_HELP #language en-US
> "Instructs the policy when to initiate Active Core control if enabled"
> +#string STR_DPTF_CLPO_PSTATE_INDEX0 #language en-US "P0"
> +#string STR_DPTF_CLPO_PSTATE_INDEX1 #language en-US "P1"
> +#string STR_DPTF_CLPO_PSTATE_INDEX2 #language en-US "P2"
> +#string STR_DPTF_CLPO_PSTATE_INDEX3 #language en-US "P3"
> +#string STR_DPTF_CLPO_PSTATE_INDEX4 #language en-US "P4"
> +#string STR_DPTF_CLPO_PSTATE_INDEX5 #language en-US "P5"
> +#string STR_DPTF_CLPO_PSTATE_INDEX6 #language en-US "P6"
> +#string STR_DPTF_CLPO_PSTATE_INDEX7 #language en-US "P7"
> +#string STR_DPTF_CLPO_PSTATE_INDEX8 #language en-US "P8"
> +#string STR_DPTF_CLPO_PSTATE_INDEX9 #language en-US "P9"
> +#string STR_DPTF_CLPO_PSTATE_INDEX10 #language en-US "P10"
> +#string STR_DPTF_CLPO_PSTATE_INDEX11 #language en-US "P11"
> +#string STR_DPTF_CLPO_PSTATE_INDEX12 #language en-US "P12"
> +#string STR_DPTF_CLPO_STEP_SIZE #language en-US "Step
> size"
> +#string STR_DPTF_CLPO_STEP_SIZE_HELP #language en-US
> "Instructs the policy to take away logical processors in the specified
> percentage steps."
> +#string STR_DPTF_CLPO_STEP_SIZE_VALUE_25 #language en-US
> "25%"
> +#string STR_DPTF_CLPO_STEP_SIZE_VALUE_50 #language en-US
> "50%"
> +#string STR_DPTF_CLPO_STEP_SIZE_VALUE_75 #language en-US
> "75%"
> +#string STR_DPTF_CLPO_PWR_CTRL #language en-US "Power
> Control Setting"
> +#string STR_DPTF_CLPO_PWR_CTRL_HELP #language en-US
> "Instructs the policy whether to use Core offliing if Active core control is
> enabled to be used in P0 or when power control is applied"
> +#string STR_DPTF_CLPO_PERF_CTRL #language en-US
> "Performance Control Setting"
> +#string STR_DPTF_CLPO_PERF_CTRL_HELP #language en-US
> "Instructs the policy whether to use Core offliing if Active core control is
> enabled to be used in P1 or when performance control is applied"
> +#string STR_DPTF_SMT_OFFFLINING #language en-US "SMT
> Offlining"
> +#string STR_DPTF_CORE_OFFFLINING #language en-US "Core
> Offlining"
> +#string STR_DPTF_DPPM #language en-US "DPPM"
> +#string STR_DPTF_DPPM_HELP #language en-US "Controls
> DPPM policies"
> +
> +#string STR_DYNAMIC_PLATFORM_THER_FRAME_PROMPT #language
> en-US "Dynamic Platform&Thermal Framework"
> +#string STR_DYNAMIC_PLATFORM_THER_FRAME_HELP #language en-
> US ""
> +#string STR_DYNAMIC_PLATFORM_THER_FRAME_PROMPT #language
> en-US "Dynamic Platform&Thermal Framework"
> +#string STR_DYNAMIC_PLATFORM_THER_FRAME_HELP #language en-
> US ""
> +
> +#string STR_DPTF_PASSIVE_TRIP_POINT_PROMPT #language en-US "
> Passive Trip Point"
> +#string STR_DPTF_PASSIVE_TRIP_POINT_HELP #language en-US ""
> +#string STR_DPTF_ACTIVE_TRIP_POINT_PROMPT #language en-US "
> Active Trip Point"
> +#string STR_DPTF_ACTIVE_TRIP_POINT_HELP #language en-US ""
> +#string STR_DPTF_CRITICAL_TRIP_POINT_PROMPT #language en-US "
> Critical Trip Point"
> +#string STR_DPTF_CRITICAL_TRIP_POINT_HELP #language en-US ""
> +#string STR_DPTF_HOT_TRIP_POINT_PROMPT #language en-US "
> Hot Trip Point"
> +#string STR_DPTF_HOT_TRIP_POINT_HELP #language en-US ""
> +#string STR_NEW #language en-US "New"
> +#string STR_LEGACY #language en-US "Legacy"
> +#string STR_CPU #language en-US "CPU"
> +#string STR_SA #language en-US "SA"
> +
> +//
> +//Memory
> +//
> +#string STR_MEMORY_SCRAMBLER_PROMPT #language en-US
> "Memory Scrambler"
> +#string STR_MEMORY_SCRAMBLER_HELP #language en-US
> "Enable/Disable Memory Scrambler support."
> +
> +#string STR_GOP_TITLE #language en-US "GOP
> Configuration"
> +#string STR_GOP_VBIOS_SWITCH #language en-US "GOP
> Driver"
> +#string STR_GOP_BRIGHTNESS_LEVEL #language en-US "GOP
> Brightness Level"
> +#string STR_GOP_BRIGHTNESS_LEVEL_HELP #language en-US "Set
> GOP Brightness Level; Value ranges from 0-255"
> +#string STR_GOP_VBIOS_SWITCH_HELP #language en-US
> "Enable GOP Driver will unload VBIOS; Disable it will load VBIOS"
> +#string STR_GOP_BRIGHT_0 #language en-US "0"
> +#string STR_GOP_BRIGHT_20 #language en-US "20"
> +#string STR_GOP_BRIGHT_40 #language en-US "40"
> +#string STR_GOP_BRIGHT_60 #language en-US "60"
> +#string STR_GOP_BRIGHT_80 #language en-US "80"
> +#string STR_GOP_BRIGHT_100 #language en-US "100"
> +#string STR_GOP_BRIGHT_120 #language en-US "120"
> +#string STR_GOP_BRIGHT_140 #language en-US "140"
> +#string STR_GOP_BRIGHT_160 #language en-US "160"
> +#string STR_GOP_BRIGHT_180 #language en-US "180"
> +#string STR_GOP_BRIGHT_200 #language en-US "200"
> +#string STR_GOP_BRIGHT_220 #language en-US "220"
> +#string STR_GOP_BRIGHT_240 #language en-US "240"
> +#string STR_GOP_BRIGHT_255 #language en-US "255"
> +
> +
> +//
> +//System Components
> +//
> +#string STR_PMIC_CONFIGURATION_TITLE #language en-US
> "PMIC Configuration"
> +#string STR_PMIC_ACPI_OBJECT_PROMPT #language en-US
> "PMIC ACPI OBJECT"
> +#string STR_PMIC_ACPI_OBJECT_HELP #language en-US
> "Enable/Disable PMIC ACPI Device."
> +
> +#string STR_PNP_CONFIGURATION_TITLE #language en-US
> "System Power and Performance(PnP) Configuration"
> +#string STR_PNP_SETTING_PROMPT #language en-US "SoC PnP
> Setting"
> +#string STR_PNP_SETTING_HELP #language en-US "Select SoC
> PnP setting mode. Auto detect mode will load the SoC PnP table against
> stepping."
> +#string STR_PNP_POWER_STRING #language en-US
> "Performance"
> +#string STR_PNP_PERFORMANCE_STRING #language en-US
> "Power"
> +#string STR_PNP_POWER_PERFORMANCE_STRING #language en-US
> "Auto Detect"
> +#string STR_PNP_POWER_PERFORMANCE_STRING_A0 #language en-
> US "Ax Stepping"
> +#string STR_PNP_POWER_PERFORMANCE_STRING_B0 #language en-
> US "Bx Stepping"
> +
> +#string STR_CFIO_PNP_SETTING_PROMPT #language en-US
> "CFIO/GPIO PnP Setting"
> +#string STR_CFIO_PNP_SETTING_HELP #language en-US
> "Enable/Disable CFIO/GPIO PnP setting mode. When enabled, CFIO/GPIO
> unused pins will be in tri-state for power saving."
> +
> +#string STR_TRISTATE_LPC_PROMPT #language en-US "LPC PnP
> Setting"
> +#string STR_TRISTATE_LPC_HELP #language en-US
> "Enable/Disable LPC PnP Setting. When enabled, the Lpc will diable clock and
> be placed in tri-state for power saveing when Bios hands over control to OS.
> If there is device connected to LPC bus, this setting should not be enabled."
> +
> +#string STR_SLP_S0IX_N_PROMPT #language en-US "Asset
> SLP_S0IX_N in S0ix"
> +#string STR_SLP_S0IX_N_HELP #language en-US
> "Auto/Enable/Disable Asset SLP_S0IX_N in S0ix. In Auto mode, PMC will
> assert SLP_S0IX_N ONLY for PR1.4 and beyond, RVP plus Rohm B3 or Dialog
> C0 or Maxim. In Enable mode, PMC will assert the SLP_S0IX_N to save power
> regardless the board type."
> +
> +#string STR_CRID_SETTING_HELP #language en-US "Select the
> Revision ID reflected in PCI config space"
> +#string STR_CRID_PROMPT #language en-US "CRID Setting"
> +#string STR_CRID_0_STRING #language en-US "CRID_0"
> +#string STR_CRID_1_STRING #language en-US "CRID_1"
> +#string STR_CRID_2_STRING #language en-US "CRID_2"
> +
> +#string STR_PCIE_SPEED_PROMPT0 #language en-US "PCIe 0
> Speed"
> +#string STR_PCIE_SPEED_PROMPT1 #language en-US "PCIe 1
> Speed"
> +#string STR_PCIE_SPEED_PROMPT2 #language en-US "PCIe 2
> Speed"
> +#string STR_PCIE_SPEED_PROMPT3 #language en-US "PCIe 3
> Speed"
> +#string STR_SATA_TEST_MODE_PROMPT #language en-US
> "SATA Test Mode"
> +#string STR_PCIE_SPEED_HELP #language en-US "Configure
> PCIe Speed"
> +#string STR_AUTO #language en-US "Auto"
> +#string STR_GEN1 #language en-US "Gen1"
> +#string STR_GEN2 #language en-US "Gen2"
> +#string STR_SATA_TEST_MODE_HELP #language en-US "Test
> Mode Enable/Disable"
> +
> +#string STR_SECURE_BOOT_MODE_HELP #language en-US
> "Secure Boot Mode - Custom & Standard"
> +#string STR_SECURE_BOOT #language en-US "SecureBoot"
> +#string STR_CLEAR_ALL_KEYS #language en-US "Clear all
> Keys"
> +#string STR_CLEAR_ALL_KEYS_HELP #language en-US "Clears PK,
> KEK, DB and DBx. Clearing Keys should be done in Custom Mode"
> +#string STR_LOAD_DEFAULTS_KEYS #language en-US "Load
> UEFI Secure Boot Defaults and Exit"
> +#string STR_LOAD_DEFAULTS_KEYS_HELP #language en-US "Loads
> PK,KEK, DBx and DB. Should be done in Custom Mode"
> +#string STR_SECURE_BOOT_UPP_PROMPT #language en-US
> "User Physical Present"
> +#string STR_SECURE_BOOT_UPP_HELP #language en-US "User is
> Physical Present User"
> +#string STR_SECURE_BOOT_MODE_PROMPT #language en-US
> "UEFI Secure Boot Mode"
> +#string STR_SECURE_BOOT_MODE_HELP #language en-US "Set
> UEFI Secure Boot Mode to STANDARD mode or CUSTOM mode, this change
> is effect after save. And after reset, the mode will return to STANDARD
> mode"
> +#string STR_SB_STANDARD_MODE #language en-US
> "STANDARD"
> +#string STR_SB_CUSTOM_MODE #language en-US "CUSTOM"
> +#string STR_SECURE_BOOT_PRO_KEY_PROMPT #language en-US
> "UEFI Secure Boot Key"
> +#string STR_SECURE_BOOT_PRO_KEY_HELP #language en-US "Set
> the UEFI Secure Boot Key to Development Key or Production Key, Change
> Key should be done in Custom Mode"
> +#string STR_DEV_KEY #language en-US "Development
> Key"
> +#string STR_PRO_KEY #language en-US "Production Key"
> +
> +// ACPI Memory Debug
> +//
> +#string STR_ACPIMEMDBG_STRING #language en-US "ACPI
> Memory Debug Switch"
> +#string STR_ACPIMEMDBG_SWTICH #language en-US "ACPI
> Memory Debug"
> +#string STR_ACPIMEMDBG_SWTICH_HELP #language en-US
> "Enable or Disable ACPI Memory Debug"
> +
> +#string STR_EXISUPPORT_PROMPT #language en-US "ExI"
> +#string STR_EXISUPPORT_HELP #language en-US
> "Enabled/Disabled ExI"
> +
> +#string STR_PMWEIGHTS_PROMPT #language en-US "PM
> Weights"
> +#string STR_PMWEIGHTS_HELP #language en-US
> "Enabled/Disabled PM Weights"
> +
> +#string STR_LPSSDEVHIDE_PROMPT #language en-US
> "Unsupported LPSS Device"
> +#string STR_LPSSDEVHIDE_HELP #language en-US "Hide
> unsupported LPSS devices when in ACPI Mode"
> +#string STR_HIDE #language en-US "Hide"
> +#string STR_UNHIDE #language en-US "UnHide"
> +
> +#string STR_BATTERY_CONFIGURATION_TITLE #language en-US
> "Battery Charging Configuration"
> +#string STR_BATTERY_ACPI_OBJECT_PROMPT #language en-US
> "Battery solution"
> +#string STR_BATTERY_ACPI_OBJECT_HELP #language en-US "If it
> does not match, battery will not work properly."
> +#string STR_NON_ULPMC #language en-US "Non ULPMC
> solution"
> +#string STR_ULPMC #language en-US "ULPMC solution"
> +
> +#string STR_CRITICAL_BATTERY_LIMIT_PROMPT #language en-US
> "Critical Battery Limit"
> +#string STR_CRITICAL_BATTERY_LIMIT_HELP #language en-US "Limit
> in percentage below which the system is not allowed to boot.
> +
> +#string STR_CRITICAL_BATTERY_LIMIT_FEATURE_PROMPT #language en-
> US "Critical Battery Limit Feature"
> +#string STR_CRITICAL_BATTERY_LIMIT_FEATURE_HELP #language en-US
> "Enable or Disable Critical Battery Limit Feature."
> +
> +#string STR_ULPMC_FW_LOCK_PROMPT #language en-US
> "ULPMC Firmware Lock"
> +#string STR_ULPMC_FW_LOCK_HELP #language en-US "Enable
> or Disable Lock ULPMC Firmware Update."
> +#string STR_WITT_CONFIGURATION_TITLE #language en-US "WITT
> Configuration"
> +#string STR_WITT_PROMPT #language en-US "Enable WITT"
> +#string STR_WITT_HELP #language en-US "Enable or
> Disable WITT"
> +#string STR_UTS_PROMPT #language en-US "Enable
> UTS(Uart Test Suite)"
> +#string STR_UTS_HELP #language en-US "Enable or Disable
> Uart Test suite"
> +#string STR_PCH_SPI_WP_PROMPT #language en-US "BIOS
> Read/Write Protection"
> +#string STR_PCH_SPI_WP_HELP #language en-US "Enable or
> Disable BIOS SPI region read/write protect."
> +#string STR_PCH_SPI_WP_DISABLE #language en-US "Disable"
> +#string STR_PCH_SPI_WP_ENABLE #language en-US "Enable"
> +#string STR_IGD_TURBO_PROMPT #language en-US "IGD
> Turbo"
> +#string STR_IGD_TURBO_HELP #language en-US "Select the
> IGD Turbo feature, if Auto selected, IGD Turbo will only be enabled when
> SOC stepping is B0 or above."
> +#string STR_EHCI_PLL_CFG_PROMPT #language en-US "EHCI PLL
> Configure"
> +#string STR_EHCI_PLL_CFG_RTD3_DIS_HELP #language en-US
> "Enable/Disable EHCI PLL Configure For RTD3"
> +
> +// Codec ALC-262 disabled
> +#string STR_CODEC262_DISABLED_PROMPT #language en-US
> "Disable Codec ALC-262"
> +#string STR_CODEC262_DISABLED_HELP #language en-US
> "Enable/Disable Codec ALC-262."
> +
> +// SAR Sensor
> +#string STR_SAR_SENSOR_PROMPT #language en-US "SAR
> Sensor"
> +#string STR_SAR_SENSOR_HELP #language en-US "Enable or
> Disable SAR sensor"
> +
> +//Lakemore
> +//
> +#string STR_LM_INFORMATION_TITLE #language en-US
> "Lakemore Configuration:"
> +#string STR_LM_MEMORY_HELP #language en-US "Specify
> the amount of main memory to be reserved for Lakemore. The memory will
> be allocated right after MRC initialization and its location will be stored into
> the Lakemore STOREMEMBAR registers."
> +#string STR_LM_MEMORY_PROMPT #language en-US
> "Memory Allocation Size"
> +#string STR_LM_MEMORY_16MB #language en-US "16000
> KiB"
> +#string STR_LM_MEMORY_8MB #language en-US "8000 KiB"
> +#string STR_LM_MEMORY_1MB #language en-US "1000 KiB"
> +#string STR_LM_MEMORY_128KB #language en-US "128 KiB"
> +#string STR_LM_MEMORY_0MB #language en-US "0 KiB"
> +
> +#string STR_PUINT_BIOS_CONFIG_DISPLAY #language en-US
> "PDM/Dfx Setting"
> +#string STR_PUINT_BIOS_CONFIG_DISPLAY_HELP #language en-US
> "PDM On: Enable PDM and keep Dfx powered.\n\nPerf Mode: Disable PDM
> and keep Dfx powered. Allows more VISA signals to be used for HW
> debug.\n\nPower Save: Disable PDM, turn off Dfx power and Visa
> clocks.\n\nNOTE: If previous setting was POWERSAVE, then cold boot will be
> needed for Dfx to come back up."
> +#string STR_PUINT_BIOS_PDM #language en-US "PDM On"
> +#string STR_PUINT_BIOS_PERFORMANCE #language en-US "Perf
> Mode"
> +#string STR_PUINT_BIOS_POWERSAVE #language en-US "Power
> Save"
> +#string STR_PUINT_BIOS_RESERVED #language en-US "Debug
> Reserved"
> +
> +#string STR_PDM_OUTPUT_CONFIG_SWTICH #language en-US
> "PDM Msg Output"
> +#string STR_PDM_OUTPUT_CONFIG_SWTICH_HELP #language en-US
> "Configure VISA and Lakemore for PDM with the given output.\n\nIf
> MainMem is selected then be sure to allocate memory for the output msgs
> in the above setting."
> +#string STR_PDM_OUTPUT_MEM #language en-US "Main
> Memory"
> +#string STR_PDM_OUTPUT_IO #language en-US "IO - TBD"
> +
> +#string STR_ENABLE_DBG2 #language en-US "Enable DBG2
> Table"
> +#string STR_ENABLE_DBG2_HELP #language en-US
> "Enable/Disable DBG2 ACPI Table for Windbg"
> +
> +//eMMC
> +//
> +#string STR_SCC_EMMC_PROMPT #language en-US "SCC
> eMMC 4.41 Support"
> +#string STR_SCC_EMMC_HELP #language en-US
> "Enable/Disable SCC eMMC 4.41 Support"
> +
> +#string STR_SCC_EMMC45_PROMPT #language en-US "SCC
> eMMC45 Support"
> +#string STR_SCC_EMMC45_HELP #language en-US
> "Enable/Disable SCC eMMC 4.5 Support"
> +#string STR_SCC_EMMC45_DDR50_PROMPT #language en-US
> "DDR50 Capability Support"
> +#string STR_SCC_EMMC45_DDR50_HELP #language en-US
> "Enable/Disable SCC eMMC 4.5 DDR 50 support"
> +#string STR_SCC_EMMC45_HS200_PROMPT #language en-US
> "HS200 Capability Support"
> +#string STR_SCC_EMMC45_HS200_HELP #language en-US
> "Enable/Disable SCC eMMC 4.5 HS 200 support"
> +#string STR_SCC_EMMC45_RE_TUNE_TIMER_VALUE #language en-US
> "Re Tune Timer Value"
> +#string STR_SCC_EMMC45_RE_TUNE_TIMER_VALUE_HELP #language
> en-US "Set the re tune timer value"
> +
> +#string STR_SCC_EMMC45_SETTING_SUBTITLE #language en-US
> "SCC eMMC 4.5 Configuration"
> +#string STR_EMMC45_TIMER_0 #language en-US "0"
> +#string STR_EMMC45_TIMER_1 #language en-US "1"
> +#string STR_EMMC45_TIMER_2 #language en-US "2"
> +#string STR_EMMC45_TIMER_3 #language en-US "3"
> +#string STR_EMMC45_TIMER_4 #language en-US "4"
> +#string STR_EMMC45_TIMER_5 #language en-US "5"
> +#string STR_EMMC45_TIMER_6 #language en-US "6"
> +#string STR_EMMC45_TIMER_7 #language en-US "7"
> +#string STR_EMMC45_TIMER_8 #language en-US "8"
> +#string STR_EMMC45_TIMER_9 #language en-US "9"
> +#string STR_EMMC45_TIMER_10 #language en-US "10"
> +#string STR_EMMC45_TIMER_11 #language en-US "11"
> +#string STR_EMMC45_TIMER_12 #language en-US "12"
> +#string STR_EMMC45_TIMER_13 #language en-US "13"
> +#string STR_EMMC45_TIMER_14 #language en-US "14"
> +#string STR_EMMC45_TIMER_15 #language en-US "15"
> +
> +#string STR_EMMC_BOOT_PROMPT #language en-US "SCC
> eMMC Boot Controller"
> +#string STR_EMMC_BOOT_HELP #language en-US
> "Disable/Select eMMC Boot mode; Auto Detect mode can switch the eMMC
> controller against the stepping"
> +#string STR_AUTO_DETECT #language en-US "Auto Detect"
> +#string STR_EMMC_BOOT_41 #language en-US "eMMC 4.41"
> +#string STR_EMMC_BOOT_45 #language en-US "eMMC 4.5"
> +
> +// SD card DDR50 and SD25
> +#string STR_SCC_SD_SDR25_PROMPT #language en-US "SDR25
> Capability Support for SDCard"
> +#string STR_SCC_SD_SDR25_HELP #language en-US
> "Disable/Enable SDR25 Capability in SD Card controller;
> +#string STR_SCC_SD_DDR50_PROMPT #language en-US "DDR50
> Capability Support for SDCard"
> +#string STR_SCC_SD_DDR50_HELP #language en-US
> "Disable/Enable DDR50 Capability in SD Card controller;
> +
> +#string STR_SECURE_ERASE_PROMPT #language en-US "eMMC
> Secure Erase"
> +#string STR_SECURE_ERASE_HELP #language en-US
> "Disable/Enable eMMC Secure Erase. When enabled, all the data on eMMC
> will be erased."
> +
> +
> +//
> +//Exit Option
> +//
> +#string STR_COMMIT_CHANGE_AND_EXIT_PROMPT #language en-
> US "Commit Changes and Exit"
> +#string STR_COMMIT_CHANGE_AND_EXIT_HELP #language en-US
> "Save the setup changes and exit"
> +
> +#string STR_DISCARD_CHANGE_AND_EXIT_PROMPT #language en-US
> "Discard Changes and Exit"
> +#string STR_DISCARD_CHANGE_AND_EXIT_HELP #language en-US
> "Discard the setup changes and exit"
> +
> +#string STR_LOAD_DEFAULT_AND_EXIT_PROMPT #language en-US
> "Load Defaults and Exit"
> +#string STR_LOAD_DEFAULT_AND_EXIT_HELP #language en-US
> "Load the setup defaults and Exit"
> +
> +#string STR_PSS_ENABLE_PROMPT #language en-US "PSS
> Storage"
> +#string STR_PSS_ENABLE_HELP #language en-US
> "Disable/Enable PSS-based secure boot"
> +#string STR_PSS_CONFIGURATION_TITLE #language en-US "PSS
> Settings"
> +
> +//
> +//Virtual Keyboard Option
> +//
> +#string STR_VIRTUAL_KB_TITLE #language en-US "Virtual
> Keyboard Configuration"
> +#string STR_VIRTUAL_KB_PROMPT #language en-US "Virtual
> Keyboard Support"
> +#string STR_VIRTUAL_KB_HELP #language en-US
> "Enable/Disable Virtual Keyboard"
> +
> +//
> +// MMIO Option
> +//
> +#string STR_MMIO_PROMPT #language en-US "PCI MMIO
> Size"
> +#string STR_MMIO_0_75G_STRING #language en-US "0.75GB"
> +#string STR_MMIO_1G_STRING #language en-US "1GB"
> +#string STR_MMIO_1_25G_STRING #language en-US "1.25GB"
> +#string STR_MMIO_1_5G_STRING #language en-US "1.5GB"
> +#string STR_MMIO_2G_STRING #language en-US "2GB"
> +#string STR_MMIO_HELP #language en-US "Setup PCI
> MMIO Size 0.75G, 1G, 1.25G, 1.5G, 2GB Size"
> +
> +//
> +// OS Selection Option
> +//
> +#string STR_OS_SELETION_PROMPT #language en-US "OS
> Selection"
> +#string STR_OS_SELETION_HELP #language en-US "OS
> Selection"
> +#string STR_WINDOWS #language en-US "Windows 8.X"
> +#string STR_ANDROID #language en-US "Android"
> +#string STR_WINDOWS7 #language en-US "Windows 7 UEFI
> 64bit"
> +#string STR_LWINDOWS7 #language en-US "Win7 32/64
> Legacy"
> +#string STR_WEC7 #language en-US "WEC7"
> +#string STR_LINUX #language en-US "Linux"
> +#string STR_BOOT_DISPLAY_MIPIDSI_PROMPT #language en-US
> "MIPI DSI"
> +#string STR_BOOT_DISPLAY_MIPIDSI_HELP #language en-US
> "Disable/enable MIPI DSI."
> +
> +
> +//
> +// EM-1 Selection Option
> +//
> +#string STR_EM1_IAAPPSRUN_PROMPT #language en-US
> "IA_APPS_RUN"
> +#string STR_EM1_IAAPPSRUN_HELP #language en-US "Voltage
> in mV"
> +#string STR_EM1_IAAPPSCAP_PROMPT #language en-US
> "IA_APPS_CAP"
> +#string STR_EM1_IAAPPSCAP_HELP #language en-US
> "Percentage"
> +#string STR_EM1_CAP_OR_VOLTAGE_PROMPT #language en-US
> "USE IA_APPS_RUN or CAP"
> +#string STR_EM1_CAP_OR_VOLTAGE_HELP #language en-US "Use
> Voltage or Capacity to decide boot flow"
> +#string STR_EM1_BOOT_ON_INVALID_BAT_PROMPT #language en-
> US "Boot on invalid battery"
> +#string STR_EM1_BOOT_ON_INVALID_BAT_HELP #language en-US
> "Allow to boot from invalid battery"
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/Platform.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/Platform.c
> new file mode 100644
> index 0000000000..8b46fbdfd1
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/Platform.c
> @@ -0,0 +1,997 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + Platform.c
> +
> +Abstract:
> +
> + This is a generic template for a child of the IchSmm driver.
> +
> +
> +--*/
> +
> +#include "SmmPlatform.h"
> +#include <Protocol/CpuIo2.h>
> +
> +
> +//
> +// Local variables
> +//
> +typedef struct {
> + UINT8 Device;
> + UINT8 Function;
> +} EFI_PCI_BUS_MASTER;
> +
> +EFI_PCI_BUS_MASTER mPciBm[] = {
> + { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
> PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 },
> + { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
> PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 },
> + { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
> PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 },
> + { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
> PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 },
> + { PCI_DEVICE_NUMBER_PCH_USB, PCI_FUNCTION_NUMBER_PCH_EHCI }
> +};
> +
> +
> +UINT16 mAcpiBaseAddr;
> +SYSTEM_CONFIGURATION mSystemConfiguration;
> +EFI_SMM_VARIABLE_PROTOCOL *mSmmVariable;
> +EFI_GLOBAL_NVS_AREA_PROTOCOL *mGlobalNvsAreaPtr;
> +
> +UINT16
> mPM1_SaveState16;
> +UINT32
> mGPE_SaveState32;
> +
> +BOOLEAN mSetSmmVariableProtocolSmiAllowed = TRUE;
> +
> +
> +//
> +// Variables. Need to initialize this from Setup
> +//
> +BOOLEAN mWakeOnLanS5Variable;
> +BOOLEAN mWakeOnRtcVariable;
> +UINT8 mWakeupDay;
> +UINT8 mWakeupHour;
> +UINT8 mWakeupMinute;
> +UINT8 mWakeupSecond;
> +
> +//
> +// Use an enum. 0 is Stay Off, 1 is Last State, 2 is Stay On
> +//
> +UINT8 mAcLossVariable;
> +
> +
> +static
> +UINT8 mTco1Sources[] = {
> + IchnNmi
> +};
> +
> +UINTN
> +DevicePathSize (
> + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
> + );
> +
> +VOID
> +S4S5ProgClock();
> +
> +EFI_STATUS
> +InitRuntimeScriptTable (
> + IN EFI_SYSTEM_TABLE *SystemTable
> + );
> +
> +VOID
> +S5SleepWakeOnRtcCallBack (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +
> +VOID
> +EnableS5WakeOnRtc();
> +
> +UINT8
> +HexToBcd(
> + UINT8 HexValue
> + );
> +
> +UINT8
> +BcdToHex(
> + IN UINT8 BcdValue
> + );
> +
> +
> +VOID
> +CpuSmmSxWorkAround(
> + );
> +
> +/**
> + Initializes the SMM Handler Driver
> +
> + @param ImageHandle
> + @param SystemTable
> +
> + @retval None
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializePlatformSmm (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 Index;
> + EFI_HANDLE Handle;
> + EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT PowerButtonContext;
> + EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL
> *PowerButtonDispatch;
> + EFI_SMM_ICHN_DISPATCH_CONTEXT IchnContext;
> + EFI_SMM_ICHN_DISPATCH_PROTOCOL *IchnDispatch;
> + EFI_SMM_SX_DISPATCH_PROTOCOL *SxDispatch;
> + EFI_SMM_SX_DISPATCH_CONTEXT EntryDispatchContext;
> + EFI_SMM_SW_DISPATCH_PROTOCOL *SwDispatch;
> + EFI_SMM_SW_DISPATCH_CONTEXT SwContext;
> + UINTN VarSize;
> + EFI_BOOT_MODE BootMode;
> +
> + Handle = NULL;
> +
> + //
> + // Locate the Global NVS Protocol.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiGlobalNvsAreaProtocolGuid,
> + NULL,
> + (void **)&mGlobalNvsAreaPtr
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> +
> + //
> + // Get the ACPI Base Address
> + //
> +
> + mAcpiBaseAddr = PchLpcPciCfg16( R_PCH_LPC_ACPI_BASE ) &
> B_PCH_LPC_ACPI_BASE_BAR;
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = SystemTable->RuntimeServices->GetVariable(
> + L"Setup",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = SystemTable->RuntimeServices->GetVariable(
> + L"SetupRecovery",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> + if (!EFI_ERROR(Status)) {
> + mAcLossVariable = mSystemConfiguration.StateAfterG3;
> +
> + //
> + // If LAN is disabled, WOL function should be disabled too.
> + //
> + if (mSystemConfiguration.Lan == 0x01){
> + mWakeOnLanS5Variable = mSystemConfiguration.WakeOnLanS5;
> + } else {
> + mWakeOnLanS5Variable = FALSE;
> + }
> +
> + mWakeOnRtcVariable = mSystemConfiguration.WakeOnRtcS5;
> + }
> +
> + BootMode = GetBootModeHob ();
> +
> + //
> + // Get the Power Button protocol
> + //
> + Status = gBS->LocateProtocol(
> + &gEfiSmmPowerButtonDispatchProtocolGuid,
> + NULL,
> + (void **)&PowerButtonDispatch
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + if (BootMode != BOOT_ON_FLASH_UPDATE) {
> + //
> + // Register for the power button event
> + //
> + PowerButtonContext.Phase = PowerButtonEntry;
> + Status = PowerButtonDispatch->Register(
> + PowerButtonDispatch,
> + PowerButtonCallback,
> + &PowerButtonContext,
> + &Handle
> + );
> + ASSERT_EFI_ERROR(Status);
> + }
> + //
> + // Get the Sx dispatch protocol
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiSmmSxDispatchProtocolGuid,
> + NULL,
> + (void **)&SxDispatch
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // Register entry phase call back function
> + //
> + EntryDispatchContext.Type = SxS3;
> + EntryDispatchContext.Phase = SxEntry;
> +
> + Status = SxDispatch->Register (
> + SxDispatch,
> + (EFI_SMM_SX_DISPATCH)SxSleepEntryCallBack,
> + &EntryDispatchContext,
> + &Handle
> + );
> +
> +
> + EntryDispatchContext.Type = SxS4;
> +
> + Status = SxDispatch->Register (
> + SxDispatch,
> + S4S5CallBack,
> + &EntryDispatchContext,
> + &Handle
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> +
> + EntryDispatchContext.Type = SxS5;
> +
> + Status = SxDispatch->Register (
> + SxDispatch,
> + S4S5CallBack,
> + &EntryDispatchContext,
> + &Handle
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + Status = SxDispatch->Register (
> + SxDispatch,
> + S5SleepAcLossCallBack,
> + &EntryDispatchContext,
> + &Handle
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // Get the Sw dispatch protocol
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiSmmSwDispatchProtocolGuid,
> + NULL,
> + (void **)&SwDispatch
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // Register ACPI enable handler
> + //
> + SwContext.SwSmiInputValue = ACPI_ENABLE;
> + Status = SwDispatch->Register (
> + SwDispatch,
> + EnableAcpiCallback,
> + &SwContext,
> + &Handle
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // Register ACPI disable handler
> + //
> + SwContext.SwSmiInputValue = ACPI_DISABLE;
> + Status = SwDispatch->Register (
> + SwDispatch,
> + DisableAcpiCallback,
> + &SwContext,
> + &Handle
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> +
> + //
> + // Register for SmmReadyToBootCallback
> + //
> + SwContext.SwSmiInputValue = SMI_SET_SMMVARIABLE_PROTOCOL;
> + Status = SwDispatch->Register(
> + SwDispatch,
> + SmmReadyToBootCallback,
> + &SwContext,
> + &Handle
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // Get the ICHn protocol
> + //
> + Status = gBS->LocateProtocol(
> + &gEfiSmmIchnDispatchProtocolGuid,
> + NULL,
> + (void **)&IchnDispatch
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // Register for the events that may happen that we do not care.
> + // This is true for SMI related to TCO since TCO is enabled by BIOS WP
> + //
> + for (Index = 0; Index < sizeof(mTco1Sources)/sizeof(UINT8); Index++) {
> + IchnContext.Type = mTco1Sources[Index];
> + Status = IchnDispatch->Register(
> + IchnDispatch,
> + (EFI_SMM_ICHN_DISPATCH)DummyTco1Callback,
> + &IchnContext,
> + &Handle
> + );
> + ASSERT_EFI_ERROR( Status );
> + }
> +
> + //
> + // Lock TCO_EN bit.
> + //
> + IoWrite16( mAcpiBaseAddr + R_PCH_TCO_CNT, IoRead16( mAcpiBaseAddr
> + R_PCH_TCO_CNT ) | B_PCH_TCO_CNT_LOCK );
> +
> + //
> + // Set to power on from G3 dependent on WOL instead of AC Loss variable
> in order to support WOL from G3 feature.
> + //
> + //
> + // Set wake from G3 dependent on AC Loss variable and Wake On LAN
> variable.
> + // This is because no matter how, if WOL enabled or AC Loss variable not
> disabled, the board needs to wake from G3 to program the LAN WOL settings.
> + // This needs to be done after LAN enable/disable so that the PWR_FLR
> state clear not impacted the WOL from G3 feature.
> + //
> + if (mAcLossVariable != 0x00) {
> + SetAfterG3On (TRUE);
> + } else {
> + SetAfterG3On (FALSE);
> + }
> +
> +
> +
> +
> + return EFI_SUCCESS;
> +}
> +
> +VOID
> +EFIAPI
> +SmmReadyToBootCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
> + )
> +{
> + EFI_STATUS Status;
> +
> + if (mSetSmmVariableProtocolSmiAllowed)
> + {
> + //
> + // It is okay to use gBS->LocateProtocol here because
> + // we are still in trusted execution.
> + //
> + Status = gBS->LocateProtocol(
> + &gEfiSmmVariableProtocolGuid,
> + NULL,
> + (void **)&mSmmVariable
> + );
> +
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // mSetSmmVariableProtocolSmiAllowed will prevent this function from
> + // being executed more than 1 time.
> + //
> + mSetSmmVariableProtocolSmiAllowed = FALSE;
> + }
> +
> +}
> +
> +/**
> +
> + @param DispatchHandle The handle of this callback, obtained when
> registering
> + @param DispatchContext The predefined context which contained sleep
> type and phase
> +
> +
> + @retval EFI_SUCCESS Operation successfully performed
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SxSleepEntryCallBack (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = SaveRuntimeScriptTable ();
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + //
> + // Workaround for S3 wake hang if C State is enabled
> + //
> + CpuSmmSxWorkAround();
> +
> + return EFI_SUCCESS;
> +}
> +
> +VOID
> +CpuSmmSxWorkAround(
> + )
> +{
> + UINT64 MsrValue;
> +
> + MsrValue = AsmReadMsr64 (0xE2);
> +
> + if (MsrValue & BIT15) {
> + return;
> + }
> +
> + if (MsrValue & BIT10) {
> + MsrValue &= ~BIT10;
> + AsmWriteMsr64 (0xE2, MsrValue);
> + }
> +}
> +
> +VOID
> +ClearP2PBusMaster(
> + )
> +{
> + UINT8 Command;
> + UINT8 Index;
> +
> + for (Index = 0; Index < sizeof(mPciBm)/sizeof(EFI_PCI_BUS_MASTER);
> Index++) {
> + Command = MmioRead8 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + mPciBm[Index].Device,
> + mPciBm[Index].Function,
> + PCI_COMMAND_OFFSET
> + )
> + );
> + Command &= ~EFI_PCI_COMMAND_BUS_MASTER;
> + MmioWrite8 (
> + MmPciAddress (0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + mPciBm[Index].Device,
> + mPciBm[Index].Function,
> + PCI_COMMAND_OFFSET
> + ),
> + Command
> + );
> + }
> +}
> +
> +/**
> +
> + Set the AC Loss to turn on or off.
> +
> +**/
> +VOID
> +SetAfterG3On (
> + BOOLEAN Enable
> + )
> +{
> + UINT8 PmCon1;
> +
> + //
> + // ICH handling portion
> + //
> + PmCon1 = MmioRead8 ( PMC_BASE_ADDRESS +
> R_PCH_PMC_GEN_PMCON_1 );
> + PmCon1 &= ~B_PCH_PMC_GEN_PMCON_AFTERG3_EN;
> + if (Enable) {
> + PmCon1 |= B_PCH_PMC_GEN_PMCON_AFTERG3_EN;
> + }
> + MmioWrite8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1,
> PmCon1);
> +
> +}
> +
> +/**
> + When a power button event happens, it shuts off the machine
> +
> +**/
> +VOID
> +EFIAPI
> +PowerButtonCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *DispatchContext
> + )
> +{
> + //
> + // Check what the state to return to after AC Loss. If Last State, then
> + // set it to Off.
> + //
> + UINT16 data16;
> +
> + if (mWakeOnRtcVariable) {
> + EnableS5WakeOnRtc();
> + }
> +
> + if (mAcLossVariable == 1) {
> + SetAfterG3On (TRUE);
> + }
> +
> + ClearP2PBusMaster();
> +
> + //
> + // Program clock chip
> + //
> + S4S5ProgClock();
> +
> +
> + data16 = (UINT16)(IoRead16(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN));
> + data16 &= B_PCH_ACPI_GPE0a_EN_PCI_EXP;
> +
> +
> + //
> + // Clear Sleep SMI Status
> + //
> + IoWrite16 (mAcpiBaseAddr + R_PCH_SMI_STS,
> + (UINT16)(IoRead16 (mAcpiBaseAddr + R_PCH_SMI_STS) |
> B_PCH_SMI_STS_ON_SLP_EN));
> + //
> + // Clear Sleep Type Enable
> + //
> + IoWrite16 (mAcpiBaseAddr + R_PCH_SMI_EN,
> + (UINT16)(IoRead16 (mAcpiBaseAddr + R_PCH_SMI_EN) &
> (~B_PCH_SMI_EN_ON_SLP_EN)));
> +
> + //
> + // Clear Power Button Status
> + //
> + IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS,
> B_PCH_ACPI_PM1_STS_PWRBTN);
> +
> + //
> + // Shut it off now!
> + //
> + IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT,
> V_PCH_ACPI_PM1_CNT_S5);
> + IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT,
> B_PCH_ACPI_PM1_CNT_SLP_EN | V_PCH_ACPI_PM1_CNT_S5);
> +
> + //
> + // Should not return
> + //
> + CpuDeadLoop();
> +}
> +
> +
> +/**
> + @param DispatchHandle - The handle of this callback, obtained when
> registering
> +
> + @param DispatchContext - The predefined context which contained sleep
> type and phase
> +
> +**/
> +VOID
> +EFIAPI
> +S5SleepAcLossCallBack (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext
> + )
> +{
> + //
> + // Check what the state to return to after AC Loss. If Last State, then
> + // set it to Off.
> + //
> + if (mAcLossVariable == 1) {
> + SetAfterG3On (TRUE);
> + }
> +}
> +
> +/**
> +
> + @param DispatchHandle The handle of this callback, obtained when
> registering
> + @param DispatchContext The predefined context which contained sleep
> type and phase
> +
> + @retval Clears the Save State bit in the clock.
> +
> +**/
> +VOID
> +EFIAPI
> +S4S5CallBack (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext
> + )
> +{
> +
> + UINT32 Data32;
> +
> + //
> + // Enable/Disable USB Charging
> + //
> + if (mSystemConfiguration.UsbCharging == 0x01) {
> + Data32 = IoRead32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL);
> + Data32 |= BIT8;
> + IoWrite32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL, Data32);
> + }
> +
> +}
> +
> +
> +VOID
> +S4S5ProgClock()
> +{
> +}
> +
> +/**
> + SMI handler to enable ACPI mode
> +
> + Dispatched on reads from APM port with value 0xA0
> +
> + Disables the SW SMI Timer.
> + ACPI events are disabled and ACPI event status is cleared.
> + SCI mode is then enabled.
> +
> + Disable SW SMI Timer
> +
> + Clear all ACPI event status and disable all ACPI events
> + Disable PM sources except power button
> + Clear status bits
> +
> + Disable GPE0 sources
> + Clear status bits
> +
> + Disable GPE1 sources
> + Clear status bits
> +
> + Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real
> Time Clock Alarm")
> +
> + Enable SCI
> +
> + @param DispatchHandle - EFI Handle
> + @param DispatchContext - Pointer to the
> EFI_SMM_SW_DISPATCH_CONTEXT
> +
> + @retval Nothing
> +
> +**/
> +VOID
> +EFIAPI
> +EnableAcpiCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
> + )
> +{
> + UINT32 SmiEn;
> + UINT16 Pm1Cnt;
> + UINT16 wordValue;
> + UINT32 RegData32;
> +
> + //
> + // Disable SW SMI Timer
> + //
> + SmiEn = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);
> + SmiEn &= ~B_PCH_SMI_STS_SWSMI_TMR;
> + IoWrite32(mAcpiBaseAddr + R_PCH_SMI_EN, SmiEn);
> +
> + wordValue = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS);
> + if(wordValue & B_PCH_ACPI_PM1_STS_WAK) {
> + IoWrite32((mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN), 0x0000);
> + IoWrite32((mAcpiBaseAddr + R_PCH_ACPI_GPE0a_STS), 0xffffffff);
> + }
> + else {
> + mPM1_SaveState16 = IoRead16(mAcpiBaseAddr +
> R_PCH_ACPI_PM1_EN);
> +
> + //
> + // Disable PM sources except power button
> + //
> + // power button is enabled only for PCAT. Disabled it on Tablet platform
> + //
> + IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN,
> B_PCH_ACPI_PM1_EN_PWRBTN);
> + IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xffff);
> +
> + mGPE_SaveState32 = IoRead16(mAcpiBaseAddr +
> R_PCH_ACPI_GPE0a_EN);
> + IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN,
> 0x0000);
> + IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_STS,
> 0xffffffff);
> +
> + }
> +
> + //
> + // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real
> Time Clock Alarm")
> + // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS
> RAM is no longer Valid
> + //
> + IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
> + IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);
> +
> +
> + RegData32 = IoRead32(ACPI_BASE_ADDRESS +
> R_PCH_ALT_GP_SMI_EN);
> + RegData32 &= ~(BIT7);
> + IoWrite32((ACPI_BASE_ADDRESS + R_PCH_ALT_GP_SMI_EN),
> RegData32);
> +
> +
> + //
> + // Enable SCI
> + //
> + Pm1Cnt = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
> + Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
> + IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
> +
> +
> +}
> +
> +/**
> + SMI handler to disable ACPI mode
> +
> + Dispatched on reads from APM port with value 0xA1
> +
> + ACPI events are disabled and ACPI event status is cleared.
> + SCI mode is then disabled.
> + Clear all ACPI event status and disable all ACPI events
> + Disable PM sources except power button
> + Clear status bits
> + Disable GPE0 sources
> + Clear status bits
> + Disable GPE1 sources
> + Clear status bits
> + Disable SCI
> +
> + @param DispatchHandle - EFI Handle
> + @param DispatchContext - Pointer to the
> EFI_SMM_SW_DISPATCH_CONTEXT
> +
> + @retval Nothing
> +
> +**/
> +VOID
> +EFIAPI
> +DisableAcpiCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
> + )
> +{
> + UINT16 Pm1Cnt;
> +
> + IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xffff);
> + IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN, mPM1_SaveState16);
> +
> + IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_STS, 0xffffffff);
> + IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN,
> mGPE_SaveState32);
> +
> + //
> + // Disable SCI
> + //
> + Pm1Cnt = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
> + Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN;
> + IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
> +
> +}
> +
> +/**
> + When an unknown event happen.
> +
> + @retval None
> +
> +**/
> +VOID
> +DummyTco1Callback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_ICHN_DISPATCH_CONTEXT *DispatchContext
> + )
> +{
> +}
> +
> +UINTN
> +DevicePathSize (
> + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
> + )
> +{
> + EFI_DEVICE_PATH_PROTOCOL *Start;
> +
> + if (DevicePath == NULL) {
> + return 0;
> + }
> +
> + //
> + // Search for the end of the device path structure
> + //
> + Start = DevicePath;
> + while (!IsDevicePathEnd (DevicePath)) {
> + DevicePath = NextDevicePathNode (DevicePath);
> + }
> +
> + //
> + // Compute the size and add back in the size of the end device path
> structure
> + //
> + return ((UINTN)DevicePath - (UINTN)Start) +
> sizeof(EFI_DEVICE_PATH_PROTOCOL);
> +}
> +
> +/**
> +
> + @param DispatchHandle The handle of this callback, obtained when
> registering
> + @param DispatchContext The predefined context which contained sleep
> type and phase
> +
> +**/
> +VOID
> +S5SleepWakeOnRtcCallBack (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext
> + )
> +{
> + EnableS5WakeOnRtc();
> +}
> +
> +/**
> +
> + @retval 1. Check Alarm interrupt is not set.
> + 2. Clear Alarm interrupt.
> + 2. Set RTC wake up date and time.
> + 2. Enable RTC wake up alarm.
> + 3. Enable ICH PM1 EN Bit 10(RTC_EN)
> +
> +**/
> +VOID
> +EnableS5WakeOnRtc()
> +{
> + UINT8 CmosData;
> + UINTN i;
> + EFI_STATUS Status;
> + UINTN VarSize;
> +
> + //
> + // make sure EFI_SMM_VARIABLE_PROTOCOL is available
> + //
> + if (!mSmmVariable) {
> + return;
> + }
> +
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> +
> + //
> + // read the variable into the buffer
> + //
> + Status = mSmmVariable->SmmGetVariable(
> + L"Setup",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + if (EFI_ERROR(Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
> + //The setup variable is corrupted
> + VarSize = sizeof(SYSTEM_CONFIGURATION);
> + Status = mSmmVariable->SmmGetVariable(
> + L"SetupRecovery",
> + &gEfiSetupVariableGuid,
> + NULL,
> + &VarSize,
> + &mSystemConfiguration
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + if (!mSystemConfiguration.WakeOnRtcS5) {
> + return;
> + }
> + mWakeupDay =
> HexToBcd((UINT8)mSystemConfiguration.RTCWakeupDate);
> + mWakeupHour =
> HexToBcd((UINT8)mSystemConfiguration.RTCWakeupTimeHour);
> + mWakeupMinute =
> HexToBcd((UINT8)mSystemConfiguration.RTCWakeupTimeMinute);
> + mWakeupSecond =
> HexToBcd((UINT8)mSystemConfiguration.RTCWakeupTimeSecond);
> +
> + //
> + // Check RTC alarm interrupt is enabled. If enabled, someone already
> + // grabbed RTC alarm. Just return.
> + //
> + IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_B);
> + if(IoRead8(PCAT_RTC_DATA_REGISTER) & B_RTC_ALARM_INT_ENABLE){
> + return;
> + }
> +
> + //
> + // Set Date
> + //
> + IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
> + CmosData = IoRead8(PCAT_RTC_DATA_REGISTER);
> + CmosData &= ~(B_RTC_DATE_ALARM_MASK);
> + CmosData |= mWakeupDay ;
> + for(i = 0 ; i < 0xffff ; i++){
> + IoWrite8(PCAT_RTC_DATA_REGISTER, CmosData);
> + SmmStall(1);
> + if(((CmosData = IoRead8(PCAT_RTC_DATA_REGISTER)) &
> B_RTC_DATE_ALARM_MASK)
> + == mWakeupDay){
> + break;
> + }
> + }
> +
> + //
> + // Set Second
> + //
> + IoWrite8(PCAT_RTC_ADDRESS_REGISTER,
> RTC_ADDRESS_SECOND_ALARM);
> + for(i = 0 ; i < 0xffff ; i++){
> + IoWrite8(PCAT_RTC_DATA_REGISTER, mWakeupSecond);
> + SmmStall(1);
> + if(IoRead8(PCAT_RTC_DATA_REGISTER) == mWakeupSecond){
> + break;
> + }
> + }
> +
> + //
> + // Set Minute
> + //
> + IoWrite8(PCAT_RTC_ADDRESS_REGISTER,
> RTC_ADDRESS_MINUTE_ALARM);
> + for(i = 0 ; i < 0xffff ; i++){
> + IoWrite8(PCAT_RTC_DATA_REGISTER, mWakeupMinute);
> + SmmStall(1);
> + if(IoRead8(PCAT_RTC_DATA_REGISTER) == mWakeupMinute){
> + break;
> + }
> + }
> +
> + //
> + // Set Hour
> + //
> + IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_HOUR_ALARM);
> + for(i = 0 ; i < 0xffff ; i++){
> + IoWrite8(PCAT_RTC_DATA_REGISTER, mWakeupHour);
> + SmmStall(1);
> + if(IoRead8(PCAT_RTC_DATA_REGISTER) == mWakeupHour){
> + break;
> + }
> + }
> +
> + //
> + // Wait for UIP to arm RTC alarm
> + //
> + IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_A);
> + while (IoRead8(PCAT_RTC_DATA_REGISTER) & 0x80);
> +
> + //
> + // Read RTC register 0C to clear pending RTC interrupts
> + //
> + IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_C);
> + IoRead8(PCAT_RTC_DATA_REGISTER);
> +
> + //
> + // Enable RTC Alarm Interrupt
> + //
> + IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_B);
> + IoWrite8(PCAT_RTC_DATA_REGISTER,
> IoRead8(PCAT_RTC_DATA_REGISTER) | B_RTC_ALARM_INT_ENABLE);
> +
> + //
> + // Clear ICH RTC Status
> + //
> + IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS,
> B_PCH_ACPI_PM1_STS_RTC);
> +
> + //
> + // Enable ICH RTC event
> + //
> + IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN,
> + (UINT16)(IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN) |
> B_PCH_ACPI_PM1_EN_RTC));
> +}
> +
> +UINT8
> +HexToBcd(
> + IN UINT8 HexValue
> + )
> +{
> + UINTN HighByte;
> + UINTN LowByte;
> +
> + HighByte = (UINTN)HexValue / 10;
> + LowByte = (UINTN)HexValue % 10;
> +
> + return ((UINT8)(LowByte + (HighByte << 4)));
> +}
> +
> +UINT8
> +BcdToHex(
> + IN UINT8 BcdValue
> + )
> +{
> + UINTN HighByte;
> + UINTN LowByte;
> +
> + HighByte = (UINTN)((BcdValue >> 4) * 10);
> + LowByte = (UINTN)(BcdValue & 0x0F);
> +
> + return ((UINT8)(LowByte + HighByte));
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/PlatformSmm.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/PlatformSmm.inf
> new file mode 100644
> index 0000000000..1b7b05d9b3
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/PlatformSmm.inf
> @@ -0,0 +1,93 @@
> +#
> +#
> +# Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +# Module Name:
> +#
> +# Platform.inf
> +#
> +# Abstract:
> +#
> +# Component description file for SMM Platform handler module
> +#
> +#--*/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformSmm
> + FILE_GUID = 99C20A37-042A-46e2-80F4-E4027FDBC86F
> + MODULE_TYPE = DXE_SMM_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = InitializePlatformSmm
> + PI_SPECIFICATION_VERSION = 0x0001000A
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +[Sources]
> + S3Save.c
> + Platform.c
> +
> +[LibraryClasses]
> + UefiDriverEntryPoint
> + UefiBootServicesTableLib
> + DebugLib
> + IoLib
> + BaseLib
> + BaseMemoryLib
> + DevicePathLib
> + HobLib
> + S3BootScriptLib
> + StallSmmLib
> + PchPlatformLib
> +
> +[Guids]
> + gEfiSetupVariableGuid
> + gDmiDataGuid
> + gEfiAcpiVariableCompatiblityGuid
> + gEfiPciLanInfoGuid
> + gEfiPciLanInfoGuid
> +
> +[FeaturePcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
> +
> +[Protocols]
> + gEfiSmmBase2ProtocolGuid
> + gEfiSmmIchnDispatchProtocolGuid
> + gEfiGlobalNvsAreaProtocolGuid
> + gEfiSmmSwDispatchProtocolGuid
> + gEfiSmmPowerButtonDispatchProtocolGuid
> + gEfiSmmSxDispatchProtocolGuid
> + gEfiSmmVariableProtocolGuid
> + gEfiCpuIo2ProtocolGuid
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
> +
> +[Pcd.common]
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> +
> +[Depex]
> + gEfiSmmBase2ProtocolGuid AND
> + gEfiSmmAccess2ProtocolGuid AND
> + gEfiSmmPowerButtonDispatchProtocolGuid AND
> + gEfiSmmSxDispatchProtocolGuid AND
> + gEfiSmmIchnDispatchProtocolGuid AND
> + gEfiSmmSwDispatchProtocolGuid AND
> + gEfiVariableArchProtocolGuid AND
> + gEfiVariableWriteArchProtocolGuid AND
> + gEfiGlobalNvsAreaProtocolGuid
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/S3Save.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/S3Save.c
> new file mode 100644
> index 0000000000..19089233b2
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/S3Save.c
> @@ -0,0 +1,377 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + IchS3Save.c
> +
> +Abstract:
> +
> + SMM S3 handler Driver implementation file
> +
> +Revision History
> +
> +**/
> +#include "SmmPlatform.h"
> +
> +extern UINT16 mAcpiBaseAddr;
> +EFI_PHYSICAL_ADDRESS mRuntimeScriptTableBase;
> +
> +EFI_STATUS
> +InitRuntimeScriptTable (
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 VarAttrib;
> + UINTN VarSize;
> + ACPI_VARIABLE_SET_COMPATIBILITY *AcpiVariableBase;
> +
> + //
> + // Allocate runtime ACPI script table space. We need it to save some
> + // settings done by CSM, which runs after normal script table closed
> + //
> + Status = gBS->AllocatePages (
> + AllocateAnyPages,
> + EfiACPIReclaimMemory,
> + 1,
> + &mRuntimeScriptTableBase
> + );
> + if (EFI_ERROR(Status)) {
> + return EFI_OUT_OF_RESOURCES ;
> + }
> +
> + //
> + // Save runtime script table base into global ACPI variable
> + //
> + VarAttrib = EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS
> + | EFI_VARIABLE_NON_VOLATILE;
> + VarSize = sizeof (UINTN);
> + Status = SystemTable->RuntimeServices->GetVariable (
> + ACPI_GLOBAL_VARIABLE,
> + &gEfiAcpiVariableCompatiblityGuid,
> + &VarAttrib,
> + &VarSize,
> + &AcpiVariableBase
> + );
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + AcpiVariableBase->RuntimeScriptTableBase = mRuntimeScriptTableBase;
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +SaveRuntimeScriptTable (
> + VOID
> + )
> +{
> + SMM_PCI_IO_ADDRESS PciAddress;
> + UINT32 Data32;
> + UINT16 Data16;
> + UINT8 Data8;
> + UINT8 Mask;
> + UINTN Index;
> + UINTN Offset;
> + UINT8 RegTable[] = {
> +
> + //
> + //Bus , Dev, Func, DMI
> + //
> + 0x00 , 0x00, 0x00,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x00 , 0x08, 0x00, 0x00, 0x30, 0x00, 0x00, 0xa0,
> +
> + //
> + //Bus , Dev, Func, LPC device
> + //
> + 0x00 , 0x1F, 0x00,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x00 , 0x08, 0x00, 0x07, 0x00, 0x00, 0x90, 0x00,
> +
> + //
> + //Bus , Dev, Func, PCIE device
> + //
> + 0x00 , 0x1C, 0x00,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0xC0 , 0x83, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
> +
> + //
> + //Bus , Dev, Func, PCIE device
> + //
> + 0x00 , 0x1C, 0x00,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x03 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +
> + //
> + //Bus , Dev, Func, SATA device
> + //
> + 0x00 , 0x13, 0x00,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0xf4 , 0xab, 0x27, 0x10, 0xf1, 0x1d, 0x00, 0x40,
> +
> + //
> + //Bus , Dev, Func, EHCI device
> + //
> + 0x00 , 0x1D, 0x00,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x10 , 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
> +
> + //
> + //Bus , Dev, Func, SMBUS device
> + //
> + 0x00 , 0x1f, 0x03,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x10 , 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +
> + //
> + //Bus , Dev, Func, SMBUS device
> + //
> + 0x00 , 0x1f, 0x03,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +
> + //
> + //Bus , Dev, Func, VGA bus1
> + //
> + 0x01 , 0x00, 0x00,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x58 , 0x81, 0x18, 0x01, 0xb0, 0x00, 0x00, 0x00,
> +
> + //
> + //Bus , Dev, Func, VGA bus1
> + //
> + 0x01 , 0x00, 0x00,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +
> + //
> + //Bus , Dev, Func, VGA bus1 function 1
> + //
> + 0x01 , 0x00, 0x01,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x51 , 0x80, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00,
> +
> + //
> + //Bus , Dev, Func, VGA bus1 function 1
> + //
> + 0x01 , 0x00, 0x01,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +
> + //
> + //Bus , Dev, Func, IGD bus0 function 0
> + //
> + 0x00 , 0x02, 0x00,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x42 , 0x81, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
> +
> + //
> + //Bus , Dev, Func, USB bus0 function 0
> + //
> + 0x00 , 0x16, 0x00,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x32 , 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +
> + //
> + //Bus , Dev, Func, HD Audio bus0 function 0
> + //
> + 0x00 , 0x1B, 0x00,
> +
> + //
> + //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
> + //
> + 0x00 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
> +
> + //
> + //0xFF indicates the end of the table
> + //
> + 0xFF
> + };
> +
> + //
> + // These registers have to set in byte order
> + //
> + UINT8 ExtReg[] = { 0x9E, 0x9D }; // SMRAM settings
> +
> +
> +
> + //
> + // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by
> CSM
> + // and vital to S3 resume. That's why we put save code here
> + //
> + PciAddress.Bus = 0;
> + PciAddress.Device = 0;
> + PciAddress.Function = 0;
> + PciAddress.ExtendedRegister = 0;
> +
> + for (Index = 0; Index < 2; Index++) {
> + //
> + // Read SRAM setting from Pci(0, 0, 0)
> + //
> + PciAddress.Register = ExtReg[Index];
> + Data8 = MmioRead8 (
> + MmPciAddress (0,
> + PciAddress.Bus,
> + PciAddress.Device,
> + PciAddress.Function,
> + PciAddress.Register
> + )
> + );
> +
> + //
> + // Save latest settings to runtime script table
> + //
> + S3BootScriptSavePciCfgWrite(
> + S3BootScriptWidthUint8,
> + *(UINT64*)&PciAddress,
> + 1,
> + &Data8
> + );
> + }
> +
> +
> + //
> + // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by
> CSM
> + // and vital to S3 resume. That's why we put save code here
> + //
> + Index = 0;
> + while (RegTable[Index] != 0xFF) {
> +
> + PciAddress.Bus = RegTable[Index++];
> + PciAddress.Device = RegTable[Index++];
> + PciAddress.Function = RegTable[Index++];
> + PciAddress.Register = 0;
> + PciAddress.ExtendedRegister = 0;
> +
> + Data16 = MmioRead16 (
> + MmPciAddress (0,
> + PciAddress.Bus,
> + PciAddress.Device,
> + PciAddress.Function,
> + PciAddress.Register
> + )
> + );
> +
> + if (Data16 == 0xFFFF) {
> + Index+=8;
> + continue;
> + }
> +
> + for (Offset = 0, Mask = 0x01; Offset < 256; Offset+=4, Mask<<=1) {
> +
> + if (Mask == 0x00) {
> + Mask = 0x01;
> + }
> +
> + if (RegTable[Index + Offset/32] & Mask ) {
> +
> + PciAddress.Register = (UINT8)Offset;
> + Data32 = MmioRead32 (MmPciAddress (0, PciAddress.Bus,
> PciAddress.Device, PciAddress.Function, PciAddress.Register));
> +
> + //
> + // Save latest settings to runtime script table
> + //
> + S3BootScriptSavePciCfgWrite (
> + S3BootScriptWidthUint32,
> + *(UINT64*)&PciAddress,
> + 1,
> + &Data32
> + );
> + }
> + }
> +
> + Index += 8;
> +
> + }
> +
> +
> + //
> + // Save I/O ports to S3 script table
> + //
> +
> + //
> + // Selftest KBC
> + //
> + Data8 = 0xAA;
> + S3BootScriptSaveIoWrite (
> + S3BootScriptWidthUint8,
> + 0x64,
> + (UINTN)1,
> + &Data8
> + );
> +
> + Data32 = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);
> +
> + S3BootScriptSaveIoWrite (
> + S3BootScriptWidthUint32,
> + (mAcpiBaseAddr + R_PCH_SMI_EN),
> + 1,
> + &Data32
> + );
> +
> + //
> + // Save B_ICH_TCO_CNT_LOCK so it will be done on S3 resume path.
> + //
> + Data16 = IoRead16(mAcpiBaseAddr + R_PCH_TCO_CNT);
> +
> + S3BootScriptSaveIoWrite (
> + S3BootScriptWidthUint16,
> + mAcpiBaseAddr + R_PCH_TCO_CNT,
> + 1,
> + &Data16
> + );
> +
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmPlatform.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmPlatform.h
> new file mode 100644
> index 0000000000..8bf2ebafc1
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmPlatform.h
> @@ -0,0 +1,240 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + SmmPlatform.h
> +
> +Abstract:
> +
> + Header file for
> +
> +++*/
> +
> +#ifndef _PLATFORM_H
> +#define _PLATFORM_H
> +
> +#include <PiSmm.h>
> +
> +
> +
> +#include <Protocol/SmmBase.h>
> +#include <Protocol/FirmwareVolume.h>
> +#include <Protocol/SmmPowerButtonDispatch.h>
> +#include <Protocol/SmmSxDispatch.h>
> +#include <Protocol/SmmSwDispatch.h>
> +#include <Protocol/SmmSwDispatch2.h>
> +#include <Protocol/SmmIchnDispatch.h>
> +#include <Protocol/SmmAccess.h>
> +#include <Protocol/SmmVariable.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include <Protocol/LoadedImage.h>
> +#include "Protocol/GlobalNvsArea.h"
> +#include <Guid/AcpiVariableCompatibility.h>
> +#include <Guid/SetupVariable.h>
> +#include <Guid/EfiVpdData.h>
> +#include <Guid/PciLanInfo.h>
> +#include <IndustryStandard/Pci22.h>
> +
> +#include "PchAccess.h"
> +#include "PlatformBaseAddresses.h"
> +
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/S3BootScriptLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PchPlatformLib.h>
> +#include <Library/StallSmmLib.h>
> +
> +
> +
> +typedef struct {
> + UINT8 Register;
> + UINT8 Function;
> + UINT8 Device;
> + UINT8 Bus;
> + UINT32 ExtendedRegister;
> +} SMM_PCI_IO_ADDRESS;
> +
> +typedef struct {
> + CHAR8 BoardAaNumber[7];
> + UINTN BoardFabNumber;
> +} BOARD_AA_NUMBER_DECODE;
> +
> +//
> +// BugBug -- Need to get these two values from acpi.h, but right now, they
> are
> +// declared in platform-specific variants of this file, so no easy
> +// way to pick-up the include file and work across platforms.
> +// Need these definitions to go into a file like common\acpi.h.
> +//
> +#define ACPI_ENABLE 0xA0
> +#define ACPI_DISABLE 0xA1
> +
> +#define APM_12_FUNCS 0x50
> +#define SMI_SET_SMMVARIABLE_PROTOCOL 0x51 // this is used in
> Cpu\Pentium\Smm\Base\SmmBase.c
> +
> +#define SMI_CMD_GET_MSEG_STATUS 0x70
> +#define SMI_CMD_UPDATE_MSEG_SIZE 0x71
> +#define SMI_CMD_LOAD_STM 0x72
> +#define SMI_CMD_UNLOAD_STM 0x73
> +#define SMI_CMD_GET_SMRAM_RANGES 0x74
> +
> +
> +#define PCAT_RTC_ADDRESS_REGISTER 0x74
> +#define PCAT_RTC_DATA_REGISTER 0x75
> +
> +#define RTC_ADDRESS_SECOND 0x00
> +#define RTC_ADDRESS_SECOND_ALARM 0x01
> +#define RTC_ADDRESS_MINUTE 0x02
> +#define RTC_ADDRESS_MINUTE_ALARM 0x03
> +#define RTC_ADDRESS_HOUR 0x04
> +#define RTC_ADDRESS_HOUR_ALARM 0x05
> +
> +#define RTC_ADDRESS_REGISTER_A 0x0A
> +#define RTC_ADDRESS_REGISTER_B 0x0B
> +#define RTC_ADDRESS_REGISTER_C 0x0C
> +#define RTC_ADDRESS_REGISTER_D 0x0D
> +
> +#define B_RTC_ALARM_INT_ENABLE 0x20
> +#define B_RTC_ALARM_INT_STATUS 0x20
> +
> +#define B_RTC_DATE_ALARM_MASK 0x3F
> +
> +#define PCAT_CMOS_2_ADDRESS_REGISTER 0x72
> +#define PCAT_CMOS_2_DATA_REGISTER 0x73
> +
> +#define EC_C_PORT 0x66
> +#define SMC_SMI_DISABLE 0xBC
> +#define SMC_ENABLE_ACPI_MODE 0xAA // Enable ACPI mode
> +
> +#define IO_MISC 156
> +
> +
> +#define MAXIMUM_NUMBER_OF_PSTATES 12
> +#define ICH_SMM_DATA_PORT 0xB3
> +
> +#define EFI_IA32_PMG_CST_CONFIG 0x000000E2
> +#define B_EFI_CST_CONTROL_LOCK BIT15
> +#define B_EFI_IO_MWAIT_REDIRECTION_ENABLE BIT10
> +#define EFI_IA32_PMG_IO_CAPTURE_ADDR 0x000000E4
> +
> +extern EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
> +
> +//
> +// Callback function prototypes
> +//
> +VOID
> +EFIAPI
> +PowerButtonCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +VOID
> +S5SleepWakeOnLanCallBack (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +VOID
> +EFIAPI
> +S5SleepAcLossCallBack (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +
> +VOID
> +EFIAPI
> +S4S5CallBack (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +VOID
> +EFIAPI
> +EnableAcpiCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +VOID
> +EFIAPI
> +DisableAcpiCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +VOID
> +EFIAPI
> +SmmReadyToBootCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +VOID
> +DummyTco1Callback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_ICHN_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +
> +VOID
> +PerrSerrCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_ICHN_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +VOID
> +RiCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_ICHN_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +
> +VOID
> +SetAfterG3On (
> + BOOLEAN Enable
> + );
> +
> +VOID
> +TurnOffVregUsb (
> + );
> +
> +VOID
> +PStateSupportCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +VOID
> +PStateTransitionCallback (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +SxSleepEntryCallBack (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext
> + );
> +
> +EFI_STATUS
> +SaveRuntimeScriptTable (
> + VOID
> + );
> +
> +
> +#endif
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.c
> new file mode 100644
> index 0000000000..26599620ba
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.c
> @@ -0,0 +1,252 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> +
> + SmmScriptSave.c
> +
> +Abstract:
> +
> + ScriptTableSave module at run time
> +
> +--*/
> +
> +#include "SmmScriptSave.h"
> +
> +//
> +// internal functions
> +//
> +
> +EFI_STATUS
> +BootScriptIoWrite (
> + IN EFI_SMM_SCRIPT_TABLE *ScriptTable,
> + IN VA_LIST Marker
> + );
> +
> +EFI_STATUS
> +BootScriptPciCfgWrite (
> + IN EFI_SMM_SCRIPT_TABLE *ScriptTable,
> + IN VA_LIST Marker
> + );
> +
> +VOID
> +SmmCopyMem (
> + IN UINT8 *Destination,
> + IN UINT8 *Source,
> + IN UINTN ByteCount
> + );
> +
> +//
> +// Function implementations
> +//
> +EFI_STATUS
> +SmmBootScriptWrite (
> + IN OUT EFI_SMM_SCRIPT_TABLE *ScriptTable,
> + IN UINTN Type,
> + IN UINT16 OpCode,
> + ...
> + )
> +{
> + EFI_STATUS Status;
> + VA_LIST Marker;
> +
> + if (ScriptTable == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Build script according to opcode
> + //
> + switch ( OpCode ) {
> +
> + case EFI_BOOT_SCRIPT_IO_WRITE_OPCODE:
> + VA_START(Marker, OpCode);
> + Status = BootScriptIoWrite (ScriptTable, Marker);
> + VA_END(Marker);
> + break;
> +
> + case EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE:
> + VA_START(Marker, OpCode);
> + Status = BootScriptPciCfgWrite(ScriptTable, Marker);
> + VA_END(Marker);
> + break;
> +
> + default:
> + Status = EFI_SUCCESS;
> + break;
> + }
> +
> + return Status;
> +}
> +
> +
> +EFI_STATUS
> +SmmBootScriptCreateTable (
> + IN OUT EFI_SMM_SCRIPT_TABLE *ScriptTable,
> + IN UINTN Type
> + )
> +{
> + BOOT_SCRIPT_POINTERS Script;
> + UINT8 *Buffer;
> +
> + if (ScriptTable == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Buffer = (UINT8*) ((UINTN)(*ScriptTable));
> +
> + //
> + // Fill Table Header
> + //
> + Script.Raw = Buffer;
> + Script.TableInfo->OpCode = EFI_BOOT_SCRIPT_TABLE_OPCODE;
> + Script.TableInfo->Length = sizeof(EFI_BOOT_SCRIPT_TABLE_HEADER);
> + Script.TableInfo->TableLength =
> sizeof(EFI_BOOT_SCRIPT_TABLE_HEADER);
> +
> + //
> + // Update current table pointer
> + //
> + *ScriptTable = *ScriptTable + sizeof(EFI_BOOT_SCRIPT_TABLE_HEADER);
> + return EFI_SUCCESS;
> +}
> +
> +
> +EFI_STATUS
> +SmmBootScriptCloseTable (
> + IN EFI_SMM_SCRIPT_TABLE ScriptTableBase,
> + IN EFI_SMM_SCRIPT_TABLE ScriptTablePtr,
> + IN UINTN Type
> + )
> +{
> + BOOT_SCRIPT_POINTERS Script;
> +
> + //
> + // Add final "termination" node to script table
> + //
> + Script.Raw = (UINT8*) ((UINTN)ScriptTablePtr);
> + Script.Terminate->OpCode = EFI_BOOT_SCRIPT_TERMINATE_OPCODE;
> + Script.Terminate->Length = sizeof (EFI_BOOT_SCRIPT_TERMINATE);
> + ScriptTablePtr += sizeof (EFI_BOOT_SCRIPT_TERMINATE);
> +
> +
> + //
> + // Update Table Header
> + //
> + Script.Raw = (UINT8*) ((UINTN)ScriptTableBase);
> + Script.TableInfo->OpCode = EFI_BOOT_SCRIPT_TABLE_OPCODE;
> + Script.TableInfo->Length = sizeof (EFI_BOOT_SCRIPT_TABLE_HEADER);
> + Script.TableInfo->TableLength = (UINT32)(ScriptTablePtr - ScriptTableBase);
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +EFI_STATUS
> +BootScriptIoWrite (
> + IN EFI_SMM_SCRIPT_TABLE *ScriptTable,
> + IN VA_LIST Marker
> + )
> +{
> + BOOT_SCRIPT_POINTERS Script;
> + EFI_BOOT_SCRIPT_WIDTH Width;
> + UINTN Address;
> + UINTN Count;
> + UINT8 *Buffer;
> + UINTN NodeLength;
> + UINT8 WidthInByte;
> +
> + Width = VA_ARG(Marker, EFI_BOOT_SCRIPT_WIDTH);
> + Address = VA_ARG(Marker, UINTN);
> + Count = VA_ARG(Marker, UINTN);
> + Buffer = VA_ARG(Marker, UINT8*);
> +
> + WidthInByte = (UINT8)(0x01 << (Width & 0x03));
> + Script.Raw = (UINT8*) ((UINTN)(*ScriptTable));
> + NodeLength = sizeof (EFI_BOOT_SCRIPT_IO_WRITE) + (WidthInByte *
> Count);
> +
> + //
> + // Build script data
> + //
> + Script.IoWrite->OpCode = EFI_BOOT_SCRIPT_IO_WRITE_OPCODE;
> + Script.IoWrite->Length = (UINT8)(NodeLength);
> + Script.IoWrite->Width = Width;
> + Script.IoWrite->Address = Address;
> + Script.IoWrite->Count = (UINT32)Count;
> + SmmCopyMem (
> + (UINT8*)(Script.Raw + sizeof (EFI_BOOT_SCRIPT_IO_WRITE)),
> + Buffer,
> + WidthInByte * Count
> + );
> +
> + //
> + // Update Script table pointer
> + //
> + *ScriptTable = *ScriptTable + NodeLength;
> + return EFI_SUCCESS;
> +}
> +
> +
> +EFI_STATUS
> +BootScriptPciCfgWrite (
> + IN EFI_SMM_SCRIPT_TABLE *ScriptTable,
> + IN VA_LIST Marker
> + )
> +{
> + BOOT_SCRIPT_POINTERS Script;
> + EFI_BOOT_SCRIPT_WIDTH Width;
> + UINT64 Address;
> + UINTN Count;
> + UINT8 *Buffer;
> + UINTN NodeLength;
> + UINT8 WidthInByte;
> +
> + Width = VA_ARG(Marker, EFI_BOOT_SCRIPT_WIDTH);
> + Address = VA_ARG(Marker, UINT64);
> + Count = VA_ARG(Marker, UINTN);
> + Buffer = VA_ARG(Marker, UINT8*);
> +
> + WidthInByte = (UINT8)(0x01 << (Width & 0x03));
> + Script.Raw = (UINT8*) ((UINTN)(*ScriptTable));
> + NodeLength = sizeof (EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE) +
> (WidthInByte * Count);
> +
> + //
> + // Build script data
> + //
> + Script.PciWrite->OpCode =
> EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE;
> + Script.PciWrite->Length = (UINT8)(NodeLength);
> + Script.PciWrite->Width = Width;
> + Script.PciWrite->Address = Address;
> + Script.PciWrite->Count = (UINT32)Count;
> + SmmCopyMem (
> + (UINT8*)(Script.Raw + sizeof (EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE)),
> + Buffer,
> + WidthInByte * Count
> + );
> +
> + //
> + // Update Script table pointer
> + //
> + *ScriptTable = *ScriptTable + NodeLength;
> + return EFI_SUCCESS;
> +}
> +
> +VOID
> +SmmCopyMem (
> + IN UINT8 *Destination,
> + IN UINT8 *Source,
> + IN UINTN ByteCount
> + )
> +{
> + UINTN Index;
> +
> + for (Index = 0; Index < ByteCount; Index++, Destination++, Source++) {
> + *Destination = *Source;
> + }
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.h
> new file mode 100644
> index 0000000000..d3eca8cdc0
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.h
> @@ -0,0 +1,50 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + SmmScriptSave.h
> +
> +Abstract:
> +
> + This is an implementation of the BootScript at run time.
> +
> +--*/
> +
> +#ifndef _RUNTIME_SCRIPT_SAVE_H
> +#define _RUNTIME_SCRIPT_SAVE_H
> +
> +#include "Efi.h"
> +#include "EfiBootScript.h"
> +
> +
> +typedef EFI_PHYSICAL_ADDRESS EFI_SMM_SCRIPT_TABLE;
> +
> +EFI_STATUS
> +SmmBootScriptCreateTable (
> + IN OUT EFI_SMM_SCRIPT_TABLE *ScriptTable,
> + IN UINTN Type
> + );
> +
> +EFI_STATUS
> +SmmBootScriptWrite (
> + IN OUT EFI_SMM_SCRIPT_TABLE *ScriptTable,
> + IN UINTN Type,
> + IN UINT16 OpCode,
> + ...
> + );
> +
> +EFI_STATUS
> +SmmBootScriptCloseTable (
> + IN EFI_SMM_SCRIPT_TABLE ScriptTableBase,
> + IN EFI_SMM_SCRIPT_TABLE ScriptTablePtr,
> + IN UINTN Type
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.c
> b/Platform/Intel/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.c
> new file mode 100644
> index 0000000000..3583e324e6
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.c
> @@ -0,0 +1,148 @@
> +/**
> + Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +Module Name:
> +
> +
> + PpmPolicy.c
> +
> +Abstract:
> +
> + This file is a wrapper for Intel PPM Platform Policy driver.
> + Get Setup Value to initilize Intel PPM DXE Platform Policy.
> +
> +--*/
> +#include "PpmPolicy.h"
> +#include <Protocol/MpService.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/CpuIA32.h>
> +
> +#include <PchRegs.h>
> +#include <Library/PchPlatformLib.h>
> +
> +#define EFI_CPUID_FAMILY 0x0F00
> +#define EFI_CPUID_MODEL 0x00F0
> +#define EFI_CPUID_STEPPING 0x000F
> +
> +EFI_STATUS
> +EFIAPI
> +PpmPolicyEntry(
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> +)
> +{
> + EFI_BOOT_SERVICES *pBS;
> + EFI_MP_SERVICES_PROTOCOL *MpService;
> + EFI_CPUID_REGISTER Cpuid01 = { 0, 0, 0, 0};
> + EFI_HANDLE Handle;
> + EFI_STATUS Status;
> + UINTN CpuCount;
> + UINTN CpuEnabledCount;
> + UINT8 CPUMobileFeature;
> +
> + PCH_STEPPING Stepping;
> +
> + pBS = SystemTable->BootServices;
> +
> + //
> + // Set PPM policy structure to known value
> + //
> + pBS->SetMem (&mDxePlatformPpmPolicy,
> sizeof(PPM_PLATFORM_POLICY_PROTOCOL), 0);
> +
> + //
> + // Find the MpService Protocol
> + //
> + Status = pBS->LocateProtocol (&gEfiMpServiceProtocolGuid,
> + NULL,
> + (void **)&MpService
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Get processor count from MP service.
> + //
> + Status = MpService->GetNumberOfProcessors (MpService, &CpuCount,
> &CpuEnabledCount);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Store the CPUID for use by SETUP items.
> + //
> + AsmCpuid (EFI_CPUID_VERSION_INFO, &Cpuid01.RegEax,
> &Cpuid01.RegEbx, &Cpuid01.RegEcx, &Cpuid01.RegEdx);
> +
> + mDxePlatformPpmPolicy.Revision =
> PPM_PLATFORM_POLICY_PROTOCOL_REVISION_4;
> +
> + //Read CPU Mobile feature from PLATFORM_ID_MSR MSR(0x17)
> NOTFB_I_AM_NOT_MOBILE_FUSE_CLIAMC00H Bit 28
> + //Bit Description: { Disables Mobile features 0 = I am NOT a mobile part 1 =
> I am a mobile part (default)"}
> + CPUMobileFeature = ((RShiftU64
> (AsmReadMsr64(EFI_MSR_IA32_PLATFORM_ID), 28)) & 0x1);
> +
> + if (!EFI_ERROR(Status)) {
> + if (CPUMobileFeature == 1){//CPU mobile feature
> + mDxePlatformPpmPolicy.FunctionEnables.EnableGv =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableCx =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableCxe =
> ICH_DEVICE_DISABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableTm =
> ICH_DEVICE_ENABLE;
> + //MaxC7
> + mDxePlatformPpmPolicy.FunctionEnables.EnableC7 =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableC6 =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableC4 =
> ICH_DEVICE_ENABLE;
> +
> +
> + }else{//CPU desktop feature
> + mDxePlatformPpmPolicy.FunctionEnables.EnableGv =
> ICH_DEVICE_DISABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableCx =
> ICH_DEVICE_DISABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableCxe =
> ICH_DEVICE_DISABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableTm =
> ICH_DEVICE_DISABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableC4 =
> ICH_DEVICE_DISABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableC6 =
> ICH_DEVICE_DISABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableC7 =
> ICH_DEVICE_DISABLE;
> + }
> +
> +
> + mDxePlatformPpmPolicy.FunctionEnables.EnableProcHot =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.TStatesEnable =
> ICH_DEVICE_ENABLE;
> +
> +
> + Stepping = PchStepping();
> + if (Stepping < PchB3) {
> + // If SoC is B0~B2 Stepping, disable the Turbo
> + mDxePlatformPpmPolicy.FunctionEnables.EnableTurboMode=
> ICH_DEVICE_DISABLE;
> + } else {
> + mDxePlatformPpmPolicy.FunctionEnables.EnableTurboMode=
> ICH_DEVICE_ENABLE;
> + }
> +
> + mDxePlatformPpmPolicy.FunctionEnables.EnableTm =
> ICH_DEVICE_ENABLE;
> +
> + mDxePlatformPpmPolicy.FunctionEnables.EnableCMP =
> ICH_DEVICE_ENABLE;
> +
> + } else {
> + mDxePlatformPpmPolicy.FunctionEnables.EnableGv =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableCx =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableCxe =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableTm =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableProcHot =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableCMP =
> ICH_DEVICE_DISABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.TStatesEnable =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableTurboMode=
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableC4 =
> ICH_DEVICE_ENABLE;
> + mDxePlatformPpmPolicy.FunctionEnables.EnableC6 =
> ICH_DEVICE_ENABLE;
> + }
> +
> +
> +
> + mDxePlatformPpmPolicy.S3RestoreMsrSwSmiNumber =
> S3_RESTORE_MSR_SW_SMI;
> +
> + Handle = NULL;
> + Status = pBS->InstallMultipleProtocolInterfaces (
> + &Handle,
> + &gPpmPlatformPolicyProtocolGuid,
> + &mDxePlatformPpmPolicy,
> + NULL
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.h
> b/Platform/Intel/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.h
> new file mode 100644
> index 0000000000..346bb18724
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.h
> @@ -0,0 +1,36 @@
> +/**
> + Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +Module Name:
> +
> + PpmPolicy.h
> +
> +Abstract:
> +
> + Header file for the PpmPolicyInitDxe Driver.
> +
> +--*/
> +#include <PiDxe.h>
> +//
> +// Driver Produced Protocol Prototypes
> +//
> +#include <Protocol/PpmPlatformPolicy.h>
> +
> +PPM_PLATFORM_POLICY_PROTOCOL mDxePlatformPpmPolicy;
> +
> +// Function Definition
> +#define ICH_DEVICE_ENABLE 1
> +#define ICH_DEVICE_DISABLE 0
> +
> +#define POWER_STATE_SWITCH_SMI 43
> +#define ENABLE_C_STATE_IO_REDIRECTION_SMI 70
> +#define DISABLE_C_STATE_IO_REDIRECTION_SMI 71
> +#define ENABLE_SMI_C_STATE_COORDINATION_SMI 72
> +#define DISABLE_SMI_C_STATE_COORDINATION_SMI 73
> +#define ENABLE_P_STATE_HARDWARE_COORDINATION_SMI 74
> +#define DISABLE_P_STATE_HARDWARE_COORDINATION_SMI 75
> +#define S3_RESTORE_MSR_SW_SMI 48
> +#define ENABLE_C6_RESIDENCY_SMI 76
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.inf
> new file mode 100644
> index 0000000000..331076a2d4
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.inf
> @@ -0,0 +1,49 @@
> +#/*++
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +# Module Name:
> +#
> +# PpmPolicy.inf
> +#
> +# Abstract:
> +#
> +# Implement platform power management policy
> +#
> +#--*/
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PpmPolicy
> + FILE_GUID = 2EE72E7C-FB9E-4318-B888-33A315C7A91D
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PpmPolicyEntry
> +
> +[Sources]
> + PpmPolicy.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2SocBinPkg/Vlv2SocBinPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + BaseLib
> + PchPlatformLib
> + UefiDriverEntryPoint
> +
> +[Protocols]
> + gEfiMpServiceProtocolGuid
> + gPpmPlatformPolicyProtocolGuid
> +
> +[Guids]
> + gEfiSetupVariableGuid
> +
> +[Depex]
> + gEfiMpServiceProtocolGuid
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Readme.md
> b/Platform/Intel/Vlv2TbltDevicePkg/Readme.md
> new file mode 100644
> index 0000000000..cbbb465b69
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Readme.md
> @@ -0,0 +1,233 @@
> +# **EDK II firmware for Minnowboard Max/Turbot which is based on Intel
> Valleyview2 SoC (Byatrail platform)**
> +
> +----------
> +# Windows Pre-requisites
> +
> +* GIT client: Available from https://git-scm.com/downloads
> +
> +* Microsoft Visual Studio.
> + - Visual Studio 2015 recommended and is used in the examples below.
> Visual Studio 2013 is also supported.
> +
> +* WINDDK
> + - Download Microsoft Windows Driver Development Kit 3790.1830 and
> install it to C:\WINDDK\3790.1830.
> +
> +* Python 3
> + - https://www.python.org/downloads/
> +
> +* Install iASL
> + - Install the iasl compiler by downloading iasl-win-20160527.zip from the
> following
> + location: "https://acpica.org/downloads/" and place the unzipped
> + content ("iasl.exe") into the directory "C:\ASL" on your local hard drive
> + (create the folder "C:\ASL" if it does not exist).
> +
> +* Install the NASM* assembly language compiler
> + - Download NASM* 2.12.02 binaries from
> + http://www.nasm.us/pub/nasm/releasebuilds/2.12.02/win64/nasm-
> 2.12.02-win64.zip and place the
> + unzipped content ("nasm.exe") into the directory "C:\NASM" on your
> local hard drive
> + (create the folder "C:\NASM" if it does not exist). Add the path
> "C:\NASM\" to system environment variable **NASM_PREFIX**.
> +
> +* Install Openssl
> + - Download a pre-compiled Openssl Windows binary from
> + https://wiki.openssl.org/index.php/Binaries. Search for a Windows binary
> in the list
> + of "Third Party OpenSSL Related Binary Distributions". Go to the third
> party site to
> + download the latest version. Download and extract to C:\Openssl, add the
> path of openssl.exe
> + ("C:\openssl") to system environment variable **OPENSSL_PATH**.
> +
> +# Download and Build MinnowMax using Windows/Visual Studio
> +
> +Run the script below from an empty directory. The script clones the EDK II
> +repository from GitHub and downloads and unzips the binary support files
> for the
> +MinnowBoard MAX. It then sets up the environment for EDK II builds and
> builds
> +the MinnowBoard MAX firmware and generates UEFI Capsules that can be
> used to
> +update the MinnowBoard MAX firmware and three sample devices.
> +
> +```
> +git clone --recurse-submodules https://github.com/tianocore/edk2.git
> +
> +powershell "& {[Net.ServicePointManager]::SecurityProtocol =
> [Net.SecurityProtocolType]::Tls12; Invoke-WebRequest -Uri
> "https://indy.fulgan.com/SSL/openssl-1.0.2r-x64_86-win64.zip -OutFile
> openssl-1.0.2r-x64_86-win64.zip"}"
> +powershell Expand-Archive openssl-1.0.2r-x64_86-win64.zip
> +
> +powershell "& {[Net.ServicePointManager]::SecurityProtocol =
> [Net.SecurityProtocolType]::Tls12; Invoke-WebRequest -Uri
> "https://firmware.intel.com/sites/default/files/MinnowBoardMax-
> Development190216.zip -OutFile MinnowBoardMax-
> Development190216.zip"}"
> +powershell Expand-Archive MinnowBoardMax-Development190216.zip
> +sleep 1
> +rename MinnowBoardMax-Development190216 Vlv2Binaries
> +cd Vlv2Binaries
> +powershell Expand-Archive Vlv2SocBinPkg.zip .
> +sleep 1
> +cd ..
> +
> +powershell "& {[Net.ServicePointManager]::SecurityProtocol =
> [Net.SecurityProtocolType]::Tls12; Invoke-WebRequest -Uri
> "https://www.nasm.us/pub/nasm/releasebuilds/2.13.03/win64/nasm-
> 2.13.03-win64.zip -OutFile nasm-2.13.03-win64.zip"}"
> +powershell Expand-Archive nasm-2.13.03-win64.zip .
> +
> +mkdir Conf
> +
> +set WORKSPACE=%CD%
> +set EDK_TOOLS_PATH=%WORKSPACE%\edk2\BaseTools
> +set EDK_TOOLS_BIN=%EDK_TOOLS_PATH%\BinWrappers\WindowsLike
> +set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\Vlv2Binaries
> +path=%path%;%EDK_TOOLS_PATH%\Bin\Win32;%WORKSPACE%\openssl-
> 1.0.2r-x64_86-win64
> +set NASM_PREFIX=%WORKSPACE%\nasm-2.13.03\
> +
> +cd %WORKSPACE%\edk2
> +
> +call edkSetup.bat Rebuild
> +
> +cd Vlv2TbltDevicePkg
> +
> +Build_IFWI.bat /m /y MNW2 Debug
> +```
> +
> +Once all the code and tools are downloaded and installed, only the
> following
> +commands are required to setup the environment. Run these from the
> same
> +directory used to install the source and binaries.
> +
> +```
> +set WORKSPACE=%CD%
> +set EDK_TOOLS_PATH=%WORKSPACE%\edk2\BaseTools
> +set EDK_TOOLS_BIN=%EDK_TOOLS_PATH%\BinWrappers\WindowsLike
> +set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\Vlv2Binaries
> +path=%path%;%EDK_TOOLS_PATH%\Bin\Win32;%WORKSPACE%\openssl-
> 1.0.2r-x64_86-win64
> +set NASM_PREFIX=%WORKSPACE%\nasm-2.13.03\
> +
> +cd %WORKSPACE%\edk2
> +
> +call edkSetup.bat Rebuild
> +```
> +
> +Once the environment is setup, the MinnowBoard MAX firmware and
> capsules can be
> +rebuilt using the following commands.
> +
> +* Build Debug Image
> +
> +```
> +cd Vlv2TbltDevicePkg
> +Build_IFWI.bat /m /y MNW2 Debug
> +```
> +
> +* Build Release Image
> +
> +```
> +cd Vlv2TbltDevicePkg
> +Build_IFWI.bat /m /y MNW2 Release
> +```
> +
> +The generated firmware image is the newest `.bin` file in
> `edk2/Vlv2TbltDevicePkg/Stitch`.
> +The file is in the form `MNW2MAX1.X64.0084.D01.<DATE>.bin`.
> +
> +The CapsuleApp and generated UEFI Capsules are in
> `Build/Vlv2TbltDevicePkg/Capsules`
> +
> +# Linux Pre-requisites
> +
> +* The tool GenBiosId has a dependency on libc.so.6. Make sure it is
> installed.
> + Here are a few example installation commands:
> +
> + sudo dnf install libc.so.6
> +
> + apt-get install libc:i386
> +
> +# Download and Build MinnowMax using Linux/GCC
> +
> +Run the script below from an empty directory. The script clones the EDK II
> +repository from GitHub and downloads and unzips the binary support files
> for the
> +MinnowBoard MAX. It then sets up the environment for EDK II builds and
> builds
> +the MinnowBoard MAX firmware and generates UEFI Capsules that can be
> used to
> +update the MinnowBoard MAX firmware and three sample devices.
> +
> +```
> +git clone --recurse-submodules https://github.com/tianocore/edk2.git
> +
> +mkdir Vlv2Binaries
> +cd Vlv2Binaries
> +wget https://firmware.intel.com/sites/default/files/MinnowBoardMax-
> Development190216.zip
> +unzip MinnowBoardMax-Development190216.zip
> +unzip Vlv2SocBinPkg.zip
> +
> +cd ..
> +mkdir Conf
> +
> +export WORKSPACE=$PWD/edk2
> +export PACKAGES_PATH=$PWD/Vlv2Binaries
> +export EDK_TOOLS_PATH=$WORKSPACE/BaseTools
> +
> +cd edk2
> +cd Vlv2TbltDevicePkg
> +. Build_IFWI.sh MNW2 Debug
> +```
> +
> +Once all the code is downloaded and installed, only the following
> commands are
> +required to setup the environment. Run these from the same directory
> used to
> +install the source and binaries.
> +
> +```
> +export WORKSPACE=$PWD/edk2
> +export PACKAGES_PATH=$PWD/Vlv2Binaries
> +export EDK_TOOLS_PATH=$WORKSPACE/BaseTools
> +
> +cd edk2
> +cd Vlv2TbltDevicePkg
> +```
> +
> +Once the environment is setup, the MinnowBoard MAX firmware and
> capsules can be
> +rebuilt using the following commands.
> +
> +
> +* Build Debug Image
> +
> +```
> +cd Vlv2TbltDevicePkg
> +./Build_IFWI.sh MNW2 Debug
> +```
> +
> +* Build Release Image
> +
> +```
> +cd Vlv2TbltDevicePkg
> +./Build_IFWI.sh MNW2 Release
> +```
> +
> +The generated firmware image is the
> `MNW2MAX_X64_D_0084_01_GCC.bin` file in
> +`edk2\Vlv2TbltDevicePkg\Stitch`
> +
> +The CapsuleApp and generated UEFI Capsules are in
> `Build\Vlv2TbltDevicePkg\Capsules`
> +
> +# Use DediProg to update FLASH image on a MinnowBoard MAX Target
> +
> +# Update MinnowBoard MAX Firmware from UEFI Capsules
> +
> +* Copy the `Build/Vlv2TbltDevicePkg/Capsules` directory to a USB FLASH
> drive
> +* Connect USB FLASH Drive to MinnowBoard MAX
> +* Boot MinnowBoard MAX to the Boot Manager
> +* Boot the `EFI Internal Shell` boot option
> +* Mount the USB FLASH Drive (usually `FS1`)
> +* Use `cd` command to go to `Capsules/TestCert` directory
> +* Run the following command to apply all four capsules
> +
> +```
> +CapsuleApp.efi Red.cap Green.cap Blue.cap MinnowMax.cap
> +```
> +
> +* The MinnowBoard MAX should reboot and the four capsules are applied
> in the
> + order listed. The progress bar matches the color name of the capsule.
> + MinnowMax.cap uses the color purple. Once all capsules are processed,
> the
> + MinnowBoard MAX should reboot again using the new firmware images.
> +
> +# Generate and Test a UX BitMap Capsule
> +
> +* Use bitmap editor to generate a BMP file. Recommend resolution of 600
> wide
> + by 100 tell and either 24 or 32 bits per pixel.
> +* Save BMP file to USB FLASH drive
> +* Use CapsuleApp.efi to convert BMP file to a UX Capsule
> +
> +```
> +CapsuleApp.efi -G MyImage.bmp -O MyImage.cap
> +```
> +
> +* When updating firmware using capsules, add UX capsule to the list of
> capsules
> + passed into CapsuleApp.efi.
> +
> +```
> +CapsuleApp.efi MyImage.cap Red.cap Green.cap Blue.cap MinnowMax.cap
> +```
> +
> +* When the capsules are processed the UX bitmap image should be
> displayed at the
> + bottom of the screen.
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfi
> g.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfi
> g.c
> new file mode 100644
> index 0000000000..69c16c5a3f
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfi
> g.c
> @@ -0,0 +1,181 @@
> +/**
> + Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +Module Name:
> +
> + SaveMemoryConfig.c
> +
> +Abstract:
> + This is the driver that locates the MemoryConfigurationData HOB, if it
> + exists, and saves the data to nvRAM.
> +
> +
> +
> +--*/
> +
> +#include "SaveMemoryConfig.h"
> +
> +CHAR16 EfiMemoryConfigVariable[] = L"MemoryConfig";
> +
> +
> +EFI_STATUS
> +EFIAPI
> +SaveMemoryConfigEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +/*++
> +
> + Routine Description:
> + This is the standard EFI driver point that detects whether there is a
> + MemoryConfigurationData HOB and, if so, saves its data to nvRAM.
> +
> + Arguments:
> + ImageHandle - Handle for the image of this driver
> + SystemTable - Pointer to the EFI System Table
> +
> + Returns:
> + EFI_SUCCESS - if the data is successfully saved or there was no data
> + EFI_NOT_FOUND - if the HOB list could not be located.
> + EFI_UNLOAD_IMAGE - It is not success
> +
> +--*/
> +{
> + EFI_STATUS Status=EFI_SUCCESS;
> + VOID *MemHobData;
> + VOID *VariableData;
> + UINTN BufferSize;
> + BOOLEAN MfgMode;
> + EFI_PLATFORM_SETUP_ID *BootModeBuffer;
> + EFI_PLATFORM_INFO_HOB *PlatformInfoHobPtr;
> + MEM_INFO_PROTOCOL *MemInfoProtocol;
> + EFI_HANDLE Handle;
> + UINT8
> Channel, Slot;
> + VOID *GuidHob;
> +
> + VariableData = NULL;
> + MfgMode = FALSE;
> + Handle = NULL;
> + BootModeBuffer = NULL;
> + MemHobData = NULL;
> + PlatformInfoHobPtr = NULL;
> + BufferSize = 0;
> +
> + //
> + // Get Platform Info HOB
> + //
> + GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
> + if (GuidHob == NULL) {
> + Status = EFI_NOT_FOUND;
> + }
> + ASSERT_EFI_ERROR (Status);
> +
> + PlatformInfoHobPtr = GET_GUID_HOB_DATA (GuidHob);
> +
> + //
> + // Get the BootMode guid hob
> + //
> + GuidHob = GetFirstGuidHob (&gEfiPlatformBootModeGuid);
> + if (GuidHob == NULL) {
> + Status = EFI_NOT_FOUND;
> + }
> + ASSERT_EFI_ERROR (Status);
> +
> + BootModeBuffer = GET_GUID_HOB_DATA (GuidHob);
> +
> +
> + //
> + // Check whether in Manufacturing Mode
> + //
> + if (BootModeBuffer) {
> + if ( !CompareMem ( //EfiCompareMem
> + &BootModeBuffer->SetupName,
> + MANUFACTURE_SETUP_NAME,
> + StrSize (MANUFACTURE_SETUP_NAME) //EfiStrSize
> + ) ) {
> + MfgMode = TRUE;
> + }
> + }
> +
> + if (MfgMode) {
> + //
> + // Don't save Memory Configuration in Manufacturing Mode. Clear
> memory configuration.
> + //
> + Status = gRT->SetVariable (
> + EfiMemoryConfigVariable,
> + &gEfiVlv2VariableGuid,
> + EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,
> + 0,
> + NULL
> + );
> + } else {
> +
> + MemInfoProtocol =
> (MEM_INFO_PROTOCOL*)AllocateZeroPool(sizeof(MEM_INFO_PROTOCOL)
> );
> + if (PlatformInfoHobPtr != NULL) {
> + MemInfoProtocol->MemInfoData.memSize = 0;
> + for (Channel = 0; Channel < CH_NUM; Channel ++){
> + for (Slot = 0; Slot < DIMM_NUM; Slot ++){
> + MemInfoProtocol->MemInfoData.dimmSize[Slot + (Channel *
> DIMM_NUM)] = PlatformInfoHobPtr->MemData.DimmSize[Slot + (Channel
> * DIMM_NUM)];
> + }
> + }
> + MemInfoProtocol->MemInfoData.memSize =
> PlatformInfoHobPtr->MemData.MemSize;
> + MemInfoProtocol->MemInfoData.EccSupport =
> PlatformInfoHobPtr->MemData.EccSupport;
> + MemInfoProtocol->MemInfoData.ddrFreq = PlatformInfoHobPtr-
> >MemData.DdrFreq;
> + MemInfoProtocol->MemInfoData.ddrType = PlatformInfoHobPtr-
> >MemData.DdrType;
> + if (MemInfoProtocol->MemInfoData.memSize == 0){
> + //
> + // We hardcode if MRC didn't fill these info in
> + //
> + MemInfoProtocol->MemInfoData.memSize = 0x800; //per 1MB
> + MemInfoProtocol->MemInfoData.dimmSize[0] = 0x800;
> + MemInfoProtocol->MemInfoData.dimmSize[1] = 0;
> + MemInfoProtocol->MemInfoData.EccSupport = FALSE;
> + MemInfoProtocol->MemInfoData.ddrType = 5; //DDRType_LPDDR3
> + }
> +
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Handle,
> + &gMemInfoProtocolGuid,
> + MemInfoProtocol,
> + NULL
> + );
> + }
> +
> + Status = EFI_SUCCESS;
> + if (BOOT_WITH_MINIMAL_CONFIGURATION != GetBootModeHob()){
> + //
> + // Get the Memory Config guid hob
> + //
> + GuidHob = GetFirstGuidHob (&gEfiMemoryConfigDataGuid);
> + if (GuidHob == NULL) {
> + Status = EFI_NOT_FOUND;
> + }
> + ASSERT_EFI_ERROR (Status);
> +
> + MemHobData = GET_GUID_HOB_DATA (GuidHob);
> + BufferSize = GET_GUID_HOB_DATA_SIZE (GuidHob);
> +
> + Status = gRT->GetVariable (
> + EfiMemoryConfigVariable,
> + &gEfiVlv2VariableGuid,
> + NULL,
> + &BufferSize,
> + VariableData
> + );
> + if (EFI_ERROR(Status) && (MemHobData != NULL)) {
> + Status = gRT->SetVariable (
> + EfiMemoryConfigVariable,
> + &gEfiVlv2VariableGuid,
> + (EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS),
> + BufferSize,
> + MemHobData
> + );
> + }
> + }
> +
> + } // if-else MfgMode
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfi
> g.h
> b/Platform/Intel/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfi
> g.h
> new file mode 100644
> index 0000000000..59ad09747a
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfi
> g.h
> @@ -0,0 +1,66 @@
> +/**
> + Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +Module Name:
> +
> + SaveMemoryConfig.h
> +
> +Abstract:
> +
> + Header file for Save Previous Memory Configuration Driver.
> +
> +
> +
> +--*/
> +
> +
> +#ifndef _SAVE_MEMORY_CONFIG_DRIVER_H
> +#define _SAVE_MEMORY_CONFIG_DRIVER_H
> +
> +#include "Protocol/SetupMode.h"
> +#include "Guid/PlatformInfo.h"
> +#include "Library/HobLib.h"
> +#include "Library/DebugLib.h"
> +#include "Library/UefiBootServicesTableLib.h"
> +#include "Library/BaseMemoryLib.h"
> +#include "PlatformBootMode.h"
> +#include "Library/BaseLib.h"
> +#include "Library/UefiRuntimeServicesTableLib.h"
> +#include "Guid/GlobalVariable.h"
> +#include "Library/UefiLib.h"
> +#include "Guid/HobList.h"
> +#include "Guid/MemoryConfigData.h"
> +#include "Protocol/MemInfo.h"
> +#include "Library/MemoryAllocationLib.h"
> +#include <Guid/Vlv2Variable.h>
> +
> +//
> +// Prototypes
> +//
> +EFI_STATUS
> +EFIAPI
> +SaveMemoryConfigEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +/*++
> +
> + Routine Description:
> + This is the standard EFI driver point that detects whether there is a
> + MemoryConfigurationData HOB and, if so, saves its data to nvRAM.
> +
> + Arguments:
> + ImageHandle - Handle for the image of this driver
> + SystemTable - Pointer to the EFI System Table
> +
> + Returns:
> + EFI_SUCCESS - if the data is successfully saved or there was no data
> + EFI_NOT_FOUND - if the HOB list could not be located.
> + EFI_UNLOAD_IMAGE - It is not success
> +
> +--*/
> +;
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfi
> g.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfi
> g.inf
> new file mode 100644
> index 0000000000..c2d693859d
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfi
> g.inf
> @@ -0,0 +1,60 @@
> +#/*++
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#
> +#
> +# Module Name:
> +#
> +# SaveMemoryConfig.inf
> +#
> +# Abstract:
> +#
> +#
> +--*/
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SaveMemoryConfig
> + FILE_GUID = E0ECBEC9-B193-4351-A488-36A655F22F9F
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = SaveMemoryConfigEntryPoint
> +
> +[sources.common]
> + SaveMemoryConfig.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + UefiDriverEntryPoint
> + UefiBootServicesTableLib
> + HobLib
> + DebugLib
> + UefiRuntimeServicesTableLib
> + UefiLib
> + BaseLib
> +
> +[Protocols]
> + gMemInfoProtocolGuid
> +
> +[Guids]
> + gEfiMemoryConfigDataGuid
> + gEfiPlatformInfoGuid
> + gEfiPlatformBootModeGuid
> + gEfiVlv2VariableGuid
> + #gEfiHobListGuid
> + #gEfiPlatformInfoGuid
> + #gEfiPlatformBootModeGuid
> + #gEfiGlobalVariableGuid
> + #gEfiMemoryConfigDataGuid
> +
> +[Depex]
> + gEfiVariableArchProtocolGuid AND
> + gEfiVariableWriteArchProtocolGuid
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/CommonHeader.h
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/CommonHeader.h
> new file mode 100644
> index 0000000000..e339b31065
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/CommonHeader.h
> @@ -0,0 +1,39 @@
> +/**@file
> + Common header file shared by all source files.
> +
> + This file includes package header files, library classes and protocol, PPI &
> GUID definitions.
> +
> + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +**/
> +
> +#ifndef __COMMON_HEADER_H_
> +#define __COMMON_HEADER_H_
> +
> +
> +
> +#include <FrameworkDxe.h>
> +#include <IndustryStandard/SmBios.h>
> +#include <Protocol/Smbios.h>
> +
> +#include <Guid/DataHubRecords.h>
> +#include <Guid/MdeModuleHii.h>
> +
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/HiiLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiLib.h>
> +#include <PchRegs.h>
> +#include <Library/PchPlatformLib.h>
> +#include <Library/PrintLib.h>
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufa
> cturer.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufa
> cturer.uni
> new file mode 100644
> index 0000000000..32309bd97a
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufa
> cturer.uni
> @@ -0,0 +1,33 @@
> +// *++
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscBaseBoardManufacturer.uni
> +//
> +// Abstract:
> +//
> +// Base board information
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +
> +#string STR_MISC_BASE_BOARD_MANUFACTURER #language en-US
> "Circuitco"
> +#string STR_MISC_BASE_BOARD_PRODUCT_NAME #language en-US
> "TABLET"
> +#string STR_MISC_BASE_BOARD_PRODUCT_NAME_FFD8 #language en-
> US "BYT-T FFD8"
> +#string STR_MISC_BASE_BOARD_PRODUCT_NAME1 #language en-US
> "MinnowBoard MAX"
> +#string STR_MISC_BASE_BOARD_VERSION #language en-US "REV A"
> +#string STR_MISC_BASE_BOARD_VERSION_FFD8 #language en-US "PR0"
> +#string STR_MISC_BASE_BOARD_SERIAL_NUMBER #language en-US "To
> be filled by O.E.M"
> +#string STR_MISC_BASE_BOARD_ASSET_TAG #language en-US "To be
> filled by O.E.M"
> +#string STR_MISC_BASE_BOARD_CHASSIS_LOCATION #language en-US
> "To be filled by O.E.M"
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufa
> cturerData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufa
> cturerData.c
> new file mode 100644
> index 0000000000..068a32f390
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufa
> cturerData.c
> @@ -0,0 +1,58 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscBaseBoardManufacturerData.c
> +
> +Abstract:
> +
> + Static data of Base board manufacturer information.
> + Base board manufacturer information is Misc. subclass type 4 and SMBIOS
> type 2.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) Bios Vendor data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_BASE_BOARD_MANUFACTURER_D
> ATA, MiscBaseBoardManufacturer)
> += {
> + STRING_TOKEN(STR_MISC_BASE_BOARD_MANUFACTURER),
> + STRING_TOKEN(STR_MISC_BASE_BOARD_PRODUCT_NAME),
> + STRING_TOKEN(STR_MISC_BASE_BOARD_VERSION),
> + STRING_TOKEN(STR_MISC_BASE_BOARD_SERIAL_NUMBER),
> + STRING_TOKEN(STR_MISC_BASE_BOARD_ASSET_TAG),
> + STRING_TOKEN(STR_MISC_BASE_BOARD_CHASSIS_LOCATION),
> + { // BaseBoardFeatureFlags
> + 1, // Motherboard
> + 0, // RequiresDaughterCard
> + 0, // Removable
> + 1, // Replaceable,
> + 0, // HotSwappable
> + 0, // Reserved
> + },
> + EfiBaseBoardTypeUnknown, // BaseBoardType
> + { // BaseBoardChassisLink
> + EFI_MISC_SUBCLASS_GUID, // ProducerName
> + 1, // Instance
> + 1, // SubInstance
> + },
> + 0, // BaseBoardNumberLinks
> + { // LinkN
> + EFI_MISC_SUBCLASS_GUID, // ProducerName
> + 1, // Instance
> + 1, // SubInstance
> + },
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufa
> cturerFunction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufa
> cturerFunction.c
> new file mode 100644
> index 0000000000..aa8c213d83
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufa
> cturerFunction.c
> @@ -0,0 +1,238 @@
> +/*++
> +
> +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +Module Name:
> +
> + MiscBaseBoardManufacturerFunction.c
> +
> +Abstract:
> +
> + BaseBoard manufacturer information boot time changes.
> + SMBIOS type 2.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +#include "MiscSubclassDriver.h"
> +#include <Library/NetLib.h>
> +#include "Library/DebugLib.h"
> +#include <Uefi/UefiBaseType.h>
> +#include <Guid/PlatformInfo.h>
> +
> +
> +extern EFI_PLATFORM_INFO_HOB *mPlatformInfo;
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscBaseBoardManufacturer (Type 2).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION(MiscBaseBoardManufacturer)
> +{
> + CHAR8 *OptionalStrStart;
> + UINTN ManuStrLen;
> + UINTN ProductStrLen;
> + UINTN VerStrLen;
> + UINTN AssertTagStrLen;
> + UINTN SerialNumStrLen;
> + UINTN ChassisStrLen;
> + EFI_STATUS Status;
> + EFI_STRING Manufacturer;
> + EFI_STRING Product;
> + EFI_STRING Version;
> + EFI_STRING SerialNumber;
> + EFI_STRING AssertTag;
> + EFI_STRING Chassis;
> + STRING_REF TokenToGet;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE2 *SmbiosRecord;
> + EFI_MISC_BASE_BOARD_MANUFACTURER *ForType2InputData;
> +
> + CHAR16 *MacStr;
> + EFI_HANDLE *Handles;
> + UINTN BufferSize;
> + CHAR16 Buffer[40];
> +
> + ForType2InputData = (EFI_MISC_BASE_BOARD_MANUFACTURER
> *)RecordData;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL || mPlatformInfo == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if (BOARD_ID_MINNOW2_TURBOT == mPlatformInfo->BoardId) {
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"ADI");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_BASE_BOARD_MANUFA
> CTURER), Buffer, NULL);
> + }
> + TokenToGet = STRING_TOKEN
> (STR_MISC_BASE_BOARD_MANUFACTURER);
> + Manufacturer = SmbiosMiscGetString (TokenToGet);
> + ManuStrLen = StrLen(Manufacturer);
> + if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + if (BOARD_ID_MINNOW2_TURBOT == mPlatformInfo->BoardId) {
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"MinnowBoard Turbot");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_BASE_BOARD_PRODUC
> T_NAME1), Buffer, NULL);
> + }
> + TokenToGet = STRING_TOKEN
> (STR_MISC_BASE_BOARD_PRODUCT_NAME1);
> + Product = SmbiosMiscGetString (TokenToGet);
> + ProductStrLen = StrLen(Product);
> + if (ProductStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION);
> + Version = SmbiosMiscGetString (TokenToGet);
> + VerStrLen = StrLen(Version);
> + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + //Get handle infomation
> + //
> + BufferSize = 0;
> + Handles = NULL;
> + Status = gBS->LocateHandle (
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + Handles
> + );
> +
> + if (Status == EFI_BUFFER_TOO_SMALL) {
> + Handles = AllocateZeroPool(BufferSize);
> + if (Handles == NULL) {
> + return (EFI_OUT_OF_RESOURCES);
> + }
> + Status = gBS->LocateHandle(
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + Handles
> + );
> + }
> +
> + //
> + //Get the MAC string
> + //
> + Status = NetLibGetMacString (
> + *Handles,
> + NULL,
> + &MacStr
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + SerialNumber = MacStr;
> + SerialNumStrLen = StrLen(SerialNumber);
> + if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> + DEBUG ((EFI_D_ERROR, "MAC Address: %S\n", MacStr));
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG);
> + AssertTag = SmbiosMiscGetString (TokenToGet);
> + AssertTagStrLen = StrLen(AssertTag);
> + if (AssertTagStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = STRING_TOKEN
> (STR_MISC_BASE_BOARD_CHASSIS_LOCATION);
> + Chassis = SmbiosMiscGetString (TokenToGet);
> + ChassisStrLen = StrLen(Chassis);
> + if (ChassisStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE2) +
> ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 +
> AssertTagStrLen + 1 + ChassisStrLen +1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE2) + ManuStrLen +
> 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 +
> AssertTagStrLen + 1 + ChassisStrLen +1 + 1);
> +
> + SmbiosRecord->Hdr.Type =
> EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE2);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + //
> + // Manu will be the 1st optional string following the formatted structure.
> + //
> + SmbiosRecord->Manufacturer = 1;
> +
> + //
> + // ProductName will be the 2st optional string following the formatted
> structure.
> + //
> + SmbiosRecord->ProductName = 2;
> +
> + //
> + // Version will be the 3rd optional string following the formatted structure.
> + //
> + SmbiosRecord->Version = 3;
> +
> + //
> + // SerialNumber will be the 4th optional string following the formatted
> structure.
> + //
> + SmbiosRecord->SerialNumber = 4;
> +
> + //
> + // AssertTag will be the 5th optional string following the formatted
> structure.
> + //
> + SmbiosRecord->AssetTag = 5;
> +
> + //
> + // LocationInChassis will be the 6th optional string following the formatted
> structure.
> + //
> + SmbiosRecord->LocationInChassis = 6;
> + SmbiosRecord->FeatureFlag =
> (*(BASE_BOARD_FEATURE_FLAGS*)&(ForType2InputData-
> >BaseBoardFeatureFlags));
> + SmbiosRecord->ChassisHandle = 0;
> + SmbiosRecord->BoardType = (UINT8)ForType2InputData-
> >BaseBoardType;
> + SmbiosRecord->NumberOfContainedObjectHandles = 0;
> +
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> +
> + //
> + // Since we fill NumberOfContainedObjectHandles = 0 for simple, just after
> this filed to fill string
> + //
> + UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart);
> + UnicodeStrToAsciiStr(Product, OptionalStrStart + ManuStrLen + 1);
> + UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1 +
> ProductStrLen + 1);
> + UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 +
> ProductStrLen + 1 + VerStrLen + 1);
> + UnicodeStrToAsciiStr(AssertTag, OptionalStrStart + ManuStrLen + 1 +
> ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1);
> + UnicodeStrToAsciiStr(Chassis, OptionalStrStart + ManuStrLen + 1 +
> ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen +
> 1);
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> +
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendor.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendor.uni
> new file mode 100644
> index 0000000000..80b099d210
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendor.uni
> @@ -0,0 +1,26 @@
> +// *++
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscBiosVendor.uni
> +//
> +// Abstract:
> +//
> +// BIOS vendor information.
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +
> +#string STR_MISC_BIOS_VENDOR #language en-US "Intel Corp."
> +#string STR_MISC_BIOS_VERSION #language en-US "Valleyview A0
> BIOS"
> +#string STR_MISC_BIOS_RELEASE_DATE #language en-US "08/06/2012"
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorData.c
> new file mode 100644
> index 0000000000..91e8efc228
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorData.c
> @@ -0,0 +1,101 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscBiosVendorData.c
> +
> +Abstract:
> +
> + Static data of BIOS vendor information.
> + BIOS vendor information is Misc. subclass type 2 and SMBIOS type 0.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) Bios Vendor data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_BIOS_VENDOR_DATA,
> MiscBiosVendor)
> += {
> + STRING_TOKEN(STR_MISC_BIOS_VENDOR), // BiosVendor
> + STRING_TOKEN(STR_MISC_BIOS_VERSION), // BiosVersion
> + STRING_TOKEN(STR_MISC_BIOS_RELEASE_DATE), // BiosReleaseDate
> + 0xF000, // BiosStartingAddress
> + { // BiosPhysicalDeviceSize
> + 1, // Value
> + 21 , // Exponent
> + },
> + { // BiosCharacteristics1
> + 0, // Reserved1 :2
> + 0, // Unknown :1
> + 0, // BiosCharacteristicsNotSupported :1
> + 0, // IsaIsSupported :1
> + 0, // McaIsSupported :1
> + 0, // EisaIsSupported :1
> + 1, // PciIsSupported :1
> + 0, // PcmciaIsSupported :1
> + 0, // PlugAndPlayIsSupported :1
> + 0, // ApmIsSupported :1
> + 1, // BiosIsUpgradable :1
> + 1, // BiosShadowingAllowed :1
> + 0, // VlVesaIsSupported :1
> + 0, // EscdSupportIsAvailable :1
> + 1, // BootFromCdIsSupported :1
> + 1, // SelectableBootIsSupported :1
> + 0, // RomBiosIsSocketed :1
> + 0, // BootFromPcmciaIsSupported :1
> + 1, // EDDSpecificationIsSupported :1
> + 0, // JapaneseNecFloppyIsSupported :1
> + 0, // JapaneseToshibaFloppyIsSupported :1
> + 0, // Floppy525_360IsSupported :1
> + 0, // Floppy525_12IsSupported :1
> + 0, // Floppy35_720IsSupported :1
> + 0, // Floppy35_288IsSupported :1
> + 0, // PrintScreenIsSupported :1
> + 1, // Keyboard8042IsSupported :1
> + 1, // SerialIsSupported :1
> + 1, // PrinterIsSupported :1
> + 1, // CgaMonoIsSupported :1
> + 0, // NecPc98 :1
> +
> +//
> +//BIOS Characteristics Extension Byte 1
> +//
> + 1, // AcpiIsSupported :1
> + 1, // UsbLegacyIsSupported :1
> + 0, // AgpIsSupported :1
> + 0, // I20BootIsSupported :1
> + 0, // Ls120BootIsSupported :1
> + 1, // AtapiZipDriveBootIsSupported :1
> + 0, // Boot1394IsSupported :1
> + 0, // SmartBatteryIsSupported :1
> +
> +//
> +//BIOS Characteristics Extension Byte 2
> +//
> + 1, // BiosBootSpecIsSupported :1
> + 1, // FunctionKeyNetworkBootIsSupported :1
> + 0x1 // Reserved :19 Bit 2 is SMBiosIsTargContDistEnabled
> + },
> + { // BiosCharacteristics2
> + 0x0001,// BiosReserved :16 Bit 0 is BIOS Splash Screen
> + 0, // SystemReserved :16
> + 0 // Reserved :32
> + },
> + 0xFF, // BiosMajorRelease;
> + 0xFF, // BiosMinorRelease;
> + 0xFF, // BiosEmbeddedFirmwareMajorRelease;
> + 0xFF, // BiosEmbeddedFirmwareMinorRelease;
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorFunctio
> n.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorFuncti
> on.c
> new file mode 100644
> index 0000000000..1817f456cb
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorFuncti
> on.c
> @@ -0,0 +1,336 @@
> +/*++
> +
> +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscBiosVendorFunction.c
> +
> +Abstract:
> +
> + BIOS vendor information boot time changes.
> + Misc. subclass type 2.
> + SMBIOS type 0.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +#include <Library/BiosIdLib.h>
> +#include <Library/SpiFlash.H>
> +
> +EFI_SPI_PROTOCOL *mSpiProtocol = NULL;
> +
> +
> +/**
> + This function read the data from Spi Rom.
> +
> + @param BaseAddress The starting address of the read.
> + @param Byte The pointer to the destination buffer.
> + @param Length The number of bytes.
> + @param SpiRegionType Spi Region Type.
> +
> + @retval Status
> +
> +**/
> +EFI_STATUS
> +FlashRead (
> + IN UINTN BaseAddress,
> + IN UINT8 *Byte,
> + IN UINTN Length,
> + IN SPI_REGION_TYPE SpiRegionType
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + UINT32 SectorSize;
> + UINT32 SpiAddress;
> + UINT8 Buffer[SECTOR_SIZE_4KB];
> +
> + SpiAddress = (UINT32)(UINTN)(BaseAddress);
> + SectorSize = SECTOR_SIZE_4KB;
> +
> + Status = mSpiProtocol->Execute (
> + mSpiProtocol,
> + SPI_READ,
> + SPI_WREN,
> + TRUE,
> + TRUE,
> + FALSE,
> + (UINT32) SpiAddress,
> + SectorSize,
> + Buffer,
> + SpiRegionType
> + );
> +
> + if (EFI_ERROR (Status)) {
> +#ifdef _SHOW_LOG_
> + Print(L"Read SPI ROM Failed [%08x]\n", SpiAddress);
> +#endif
> + return Status;
> + }
> +
> + CopyMem (Byte, (void *)Buffer, Length);
> +
> + return Status;
> +}
> +
> +/**
> + This function returns the value & exponent to Base2 for a given
> + Hex value. This is used to calculate the BiosPhysicalDeviceSize.
> +
> + @param Value The hex value which is to be converted into
> value-exponent form
> + @param Exponent The exponent out of the conversion
> +
> + @retval EFI_SUCCESS All parameters were valid and *Value &
> *Exponent have been set.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +EFI_STATUS
> +GetValueExponentBase2(
> + IN OUT UINTN *Value,
> + OUT UINTN *Exponent
> + )
> +{
> + if ((Value == NULL) || (Exponent == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + while ((*Value % 2) == 0) {
> + *Value=*Value/2;
> + (*Exponent)++;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Field Filling Function. Transform an EFI_EXP_BASE2_DATA to a byte, with
> '64k'
> + as the unit.
> +
> + @param Base2Data Pointer to Base2_Data
> +
> + @retval EFI_SUCCESS Transform successfully.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +UINT16
> +Base2ToByteWith64KUnit (
> + IN EFI_EXP_BASE2_DATA *Base2Data
> + )
> +{
> + UINT16 Value;
> + UINT16 Exponent;
> +
> + Value = Base2Data->Value;
> + Exponent = Base2Data->Exponent;
> + Exponent -= 16;
> + Value <<= Exponent;
> +
> + return Value;
> +}
> +
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscBiosVendor (Type 0).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION(MiscBiosVendor)
> +{
> + CHAR8 *OptionalStrStart;
> + UINTN VendorStrLen;
> + UINTN VerStrLen;
> + UINTN DateStrLen;
> + CHAR16 *Version;
> + CHAR16 *ReleaseDate;
> + CHAR16 BiosVersion[100]; //Assuming that strings are < 100
> UCHAR
> + CHAR16 BiosReleaseDate[100]; //Assuming that strings are < 100
> UCHAR
> + CHAR16 BiosReleaseTime[100]; //Assuming that strings are < 100
> UCHAR
> + EFI_STATUS Status;
> + EFI_STRING Char16String;
> + STRING_REF TokenToGet;
> + STRING_REF TokenToUpdate;
> + SMBIOS_TABLE_TYPE0 *SmbiosRecord;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + EFI_MISC_BIOS_VENDOR *ForType0InputData;
> + BIOS_ID_IMAGE BiosIdImage;
> + UINT16 UVerStr[32];
> + UINTN LoopIndex;
> + UINTN CopyIndex;
> + MANIFEST_OEM_DATA *IFWIVerStruct;
> + UINT8 *Data8 = NULL;
> + UINT16 SpaceVer[2]={0x0020,0x0000};
> + UINT16 BIOSVersionTemp[100];
> +
> + ForType0InputData = (EFI_MISC_BIOS_VENDOR *)RecordData;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> + GetBiosId (&BiosIdImage);
> +
> + //
> + // Add VLV2 BIOS Version and Release data
> + //
> + SetMem(BiosVersion, sizeof(BiosVersion), 0);
> + SetMem(BiosReleaseDate, sizeof(BiosReleaseDate), 0);
> + SetMem(BiosReleaseTime, sizeof(BiosReleaseTime), 0);
> + Status = GetBiosVersionDateTime (BiosVersion, BiosReleaseDate,
> BiosReleaseTime);
> + DEBUG ((EFI_D_ERROR, "GetBiosVersionDateTime :%s %s %s \n",
> BiosVersion, BiosReleaseDate, BiosReleaseTime));
> + if (StrLen (BiosVersion) > 0) {
> + TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);
> + HiiSetString (mHiiHandle, TokenToUpdate, BiosVersion, NULL);
> + }
> +
> + if (StrLen(BiosReleaseDate) > 0) {
> + TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);
> + HiiSetString (mHiiHandle, TokenToUpdate, BiosReleaseDate, NULL);
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR);
> + Char16String = SmbiosMiscGetString (TokenToGet);
> + VendorStrLen = StrLen(Char16String);
> + if (VendorStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION);
> + Version = SmbiosMiscGetString (TokenToGet);
> +
> + ZeroMem (UVerStr, 2*32);
> + ZeroMem (BIOSVersionTemp, 2*100);
> + StrCat (BIOSVersionTemp,Version);
> + Data8 = AllocatePool (SECTOR_SIZE_4KB);
> + ZeroMem (Data8, SECTOR_SIZE_4KB);
> +
> + Status = gBS->LocateProtocol (
> + &gEfiSpiProtocolGuid,
> + NULL,
> + (VOID **)&mSpiProtocol
> + );
> + if (!EFI_ERROR(Status)) {
> + //
> + // Get data form SPI ROM.
> + //
> + Status = FlashRead (
> + MEM_IFWIVER_START,
> + Data8,
> + SECTOR_SIZE_4KB,
> + EnumSpiRegionAll
> + );
> + if (!EFI_ERROR(Status)) {
> + for(LoopIndex = 0; LoopIndex <= SECTOR_SIZE_4KB; LoopIndex++) {
> + IFWIVerStruct = (MANIFEST_OEM_DATA *)(Data8 + LoopIndex);
> + if(IFWIVerStruct->Signature == SIGNATURE_32('$','F','U','D')) {
> + DEBUG ((EFI_D_ERROR, "the IFWI Length is:%d\n", IFWIVerStruct-
> >IFWIVersionLen));
> + if(IFWIVerStruct->IFWIVersionLen < 32) {
> + for(CopyIndex = 0; CopyIndex < IFWIVerStruct->IFWIVersionLen;
> CopyIndex++) {
> + UVerStr[CopyIndex] = (UINT16)IFWIVerStruct-
> >IFWIVersion[CopyIndex];
> + }
> + UVerStr[CopyIndex] = 0x0000;
> + DEBUG ((EFI_D_ERROR, "The IFWI Version is :%s,the IFWI Length
> is:%d\n", UVerStr,IFWIVerStruct->IFWIVersionLen));
> + StrCat(BIOSVersionTemp,SpaceVer);
> + StrCat(BIOSVersionTemp,UVerStr);
> + DEBUG ((EFI_D_ERROR, "The BIOS and IFWI Version is :%s\n",
> BIOSVersionTemp));
> + }
> + break;
> + }
> + }
> + }
> + }
> + FreePool(Data8);
> +
> + VerStrLen = StrLen(BIOSVersionTemp);
> + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);
> + ReleaseDate = SmbiosMiscGetString (TokenToGet);
> + DateStrLen = StrLen(ReleaseDate);
> + if (DateStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE0) +
> VendorStrLen + 1 + VerStrLen + 1 + DateStrLen + 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen
> + 1 + VerStrLen + 1 + DateStrLen + 1 + 1);
> +
> + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BIOS_INFORMATION;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + //
> + // Vendor will be the 1st optional string following the formatted structure.
> + //
> + SmbiosRecord->Vendor = 1;
> +
> + //
> + // Version will be the 2nd optional string following the formatted structure.
> + //
> + SmbiosRecord->BiosVersion = 2;
> + SmbiosRecord->BiosSegment = (UINT16)ForType0InputData-
> >BiosStartingAddress;
> +
> + //
> + // ReleaseDate will be the 3rd optional string following the formatted
> structure.
> + //
> + SmbiosRecord->BiosReleaseDate = 3;
> +
> + //
> + // Tiger has no PCD value to indicate BIOS Size, just fill 0 for simply.
> + //
> + SmbiosRecord->BiosSize = 0;
> + SmbiosRecord->BiosCharacteristics =
> *(MISC_BIOS_CHARACTERISTICS*)(&ForType0InputData-
> >BiosCharacteristics1);
> +
> + //
> + // CharacterExtensionBytes also store in ForType0InputData-
> >BiosCharacteristics1 later two bytes to save size.
> + //
> + SmbiosRecord->BIOSCharacteristicsExtensionBytes[0] = *((UINT8 *)
> &ForType0InputData->BiosCharacteristics1 + 4);
> + SmbiosRecord->BIOSCharacteristicsExtensionBytes[1] = *((UINT8 *)
> &ForType0InputData->BiosCharacteristics1 + 5);
> +
> + SmbiosRecord->SystemBiosMajorRelease = ForType0InputData-
> >BiosMajorRelease;
> + SmbiosRecord->SystemBiosMinorRelease = ForType0InputData-
> >BiosMinorRelease;
> + SmbiosRecord->EmbeddedControllerFirmwareMajorRelease =
> ForType0InputData->BiosEmbeddedFirmwareMajorRelease;
> + SmbiosRecord->EmbeddedControllerFirmwareMinorRelease =
> ForType0InputData->BiosEmbeddedFirmwareMinorRelease;
> +
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(Char16String, OptionalStrStart);
> + UnicodeStrToAsciiStr(BIOSVersionTemp, OptionalStrStart + VendorStrLen
> + 1);
> + UnicodeStrToAsciiStr(ReleaseDate, OptionalStrStart + VendorStrLen + 1 +
> VerStrLen + 1);
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> +
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationD
> ata.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationD
> ata.c
> new file mode 100644
> index 0000000000..6b0f562261
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationD
> ata.c
> @@ -0,0 +1,34 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscBootInformationData.c
> +
> +Abstract:
> +
> + Static data of Boot information.
> + Boot information is Misc. subclass type 26 and SMBIOS type 32.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) Bios Vendor data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_BOOT_INFORMATION_STATUS_D
> ATA, BootInformationStatus)
> += {
> + EfiBootInformationStatusNoError, // BootInformationStatus
> + 0 // BootInformationData
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationF
> unction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationF
> unction.c
> new file mode 100644
> index 0000000000..0d4d50c663
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationF
> unction.c
> @@ -0,0 +1,82 @@
> +/*++
> +
> +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscBootInformationFunction.c
> +
> +Abstract:
> +
> + boot information boot time changes.
> + SMBIOS type 32.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscBootInformation (Type 32).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +
> +MISC_SMBIOS_TABLE_FUNCTION(BootInformationStatus)
> +{
> + EFI_STATUS Status;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE32 *SmbiosRecord;
> + EFI_MISC_BOOT_INFORMATION_STATUS* ForType32InputData;
> +
> + ForType32InputData = (EFI_MISC_BOOT_INFORMATION_STATUS
> *)RecordData;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1);
> +
> + SmbiosRecord->Hdr.Type =
> EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE32);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> + SmbiosRecord->BootStatus = (UINT8)ForType32InputData-
> >BootInformationStatus;
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufactur
> er.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufactu
> rer.uni
> new file mode 100644
> index 0000000000..1c8dd35b37
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufactu
> rer.uni
> @@ -0,0 +1,28 @@
> +// *++
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscChassisManufacturer.uni
> +//
> +// Abstract:
> +//
> +// Chassis information
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +
> +#string STR_MISC_CHASSIS_MANUFACTURER #language en-US "Circuitco"
> +#string STR_MISC_CHASSIS_VERSION #language en-US " "
> +#string STR_MISC_CHASSIS_SERIAL_NUMBER #language en-US " "
> +#string STR_MISC_CHASSIS_ASSET_TAG #language en-US " "
> +#string STR_MISC_CHASSIS_SKU_NUMBER #language en-US " "
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufactur
> erData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufactu
> rerData.c
> new file mode 100644
> index 0000000000..ee11c9eac4
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufactu
> rerData.c
> @@ -0,0 +1,57 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscChassisManufacturerData.c
> +
> +Abstract:
> +
> + Static data is Chassis Manufacturer information.
> + Chassis Manufacturer information is Misc. subclass type 5 and SMBIOS
> type 3.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) Chassis Manufacturer data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_CHASSIS_MANUFACTURER_DATA,
> MiscChassisManufacturer)
> += {
> + STRING_TOKEN(STR_MISC_CHASSIS_MANUFACTURER), //
> ChassisManufactrurer
> + STRING_TOKEN(STR_MISC_CHASSIS_VERSION), // ChassisVersion
> + STRING_TOKEN(STR_MISC_CHASSIS_SERIAL_NUMBER), //
> ChassisSerialNumber
> + STRING_TOKEN(STR_MISC_CHASSIS_ASSET_TAG), // ChassisAssetTag
> + { // ChassisTypeStatus
> + EfiMiscChassisTypeUnknown, // ChassisType
> + 0, // ChassisLockPresent
> + 0 // Reserved
> + },
> + EfiChassisStateSafe, // ChassisBootupState
> + EfiChassisStateSafe, // ChassisPowerSupplyState
> + EfiChassisStateOther, // ChassisThermalState
> + EfiChassisSecurityStatusOther, // ChassisSecurityState
> + 0, // ChassisOemDefined
> + 0, // ChassisHeight
> + 0, // ChassisNumberPowerCords
> + 0, // ChassisElementCount
> + 0, // ChassisElementRecordLength
> + { // ChassisElements
> + {0, 0, 0}, // ChassisElementType
> + 0, // ChassisElementStructure
> + EfiBaseBoardTypeUnknown, // ChassisBaseBoard
> + 0, // ChassisElementMinimum
> + 0 // ChassisElementMaximum
> + },
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufactur
> erFunction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufactu
> rerFunction.c
> new file mode 100644
> index 0000000000..c42ba3d0d1
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufactu
> rerFunction.c
> @@ -0,0 +1,158 @@
> +/*++
> +
> +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscChassisManufacturerFunction.c
> +
> +Abstract:
> +
> + Chassis manufacturer information boot time changes.
> + SMBIOS type 3.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +#include "MiscSubclassDriver.h"
> +#include <Guid/PlatformInfo.h>
> +
> +
> +extern EFI_PLATFORM_INFO_HOB *mPlatformInfo;
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscChassisManufacturer (Type 3).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION(MiscChassisManufacturer)
> +{
> + CHAR8 *OptionalStrStart;
> + UINTN ManuStrLen;
> + UINTN VerStrLen;
> + UINTN AssertTagStrLen;
> + UINTN SerialNumStrLen;
> + EFI_STATUS Status;
> + EFI_STRING Manufacturer;
> + EFI_STRING Version;
> + EFI_STRING SerialNumber;
> + EFI_STRING AssertTag;
> + STRING_REF TokenToGet;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE3 *SmbiosRecord;
> + EFI_MISC_CHASSIS_MANUFACTURER *ForType3InputData;
> + CHAR16 Buffer[40];
> +
> + ForType3InputData = (EFI_MISC_CHASSIS_MANUFACTURER *)RecordData;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL || mPlatformInfo == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if (BOARD_ID_MINNOW2_TURBOT == mPlatformInfo->BoardId) {
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"ADI");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_CHASSIS_MANUFACTUR
> ER), Buffer, NULL);
> + }
> + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER);
> + Manufacturer = SmbiosMiscGetString (TokenToGet);
> + ManuStrLen = StrLen(Manufacturer);
> + if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_VERSION);
> + Version = SmbiosMiscGetString (TokenToGet);
> + VerStrLen = StrLen(Version);
> + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER);
> + SerialNumber = SmbiosMiscGetString (TokenToGet);
> + SerialNumStrLen = StrLen(SerialNumber);
> + if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG);
> + AssertTag = SmbiosMiscGetString (TokenToGet);
> + AssertTagStrLen = StrLen(AssertTag);
> + if (AssertTagStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE3) +
> ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1
> + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen +
> 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + 1);
> +
> + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE3);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + //
> + // Manu will be the 1st optional string following the formatted structure.
> + //
> + SmbiosRecord->Manufacturer = 1;
> + SmbiosRecord->Type = (UINT8)ForType3InputData-
> >ChassisType.ChassisType;
> +
> + //
> + // Version will be the 2nd optional string following the formatted structure.
> + //
> + SmbiosRecord->Version = 2;
> +
> + //
> + // SerialNumber will be the 3rd optional string following the formatted
> structure.
> + //
> + SmbiosRecord->SerialNumber = 3;
> +
> + //
> + // AssertTag will be the 4th optional string following the formatted
> structure.
> + //
> + SmbiosRecord->AssetTag = 4;
> + SmbiosRecord->BootupState = (UINT8)ForType3InputData-
> >ChassisBootupState;
> + SmbiosRecord->PowerSupplyState = (UINT8)ForType3InputData-
> >ChassisPowerSupplyState;
> + SmbiosRecord->ThermalState = (UINT8)ForType3InputData-
> >ChassisThermalState;
> + SmbiosRecord->SecurityStatus = (UINT8)ForType3InputData-
> >ChassisSecurityState;
> + CopyMem (SmbiosRecord->OemDefined,(UINT8*)&ForType3InputData-
> >ChassisOemDefined, 4);
> +
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart);
> + UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1);
> + UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 +
> VerStrLen + 1);
> + UnicodeStrToAsciiStr(AssertTag, OptionalStrStart + ManuStrLen + 1 +
> VerStrLen + 1 + SerialNumStrLen + 1);
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> +
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDevice.un
> i
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDevice.un
> i
> new file mode 100644
> index 0000000000..9dd0b76ea2
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDevice.un
> i
> @@ -0,0 +1,35 @@
> +// *++
> +//
> +// Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscMemoryDevice.uni
> +//
> +// Abstract:
> +//
> +// Memory Device
> +// Misc. subclass type 17.
> +// SMBIOS type 17.
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +
> +#string STR_MISC_MEM_DEV_LOCATOR_0 #language en-US
> "MODULE 0"
> +#string STR_MISC_MEM_DEV_LOCATOR_1 #language en-US
> "MODULE 1"
> +#string STR_MISC_MEM_DEV_LOCATOR0 #language en-US "DIMM 0"
> +#string STR_MISC_MEM_DEV_LOCATOR1 #language en-US "DIMM 1"
> +#string STR_MISC_MEM_BANK_LOCATOR0 #language en-US "BANK 0"
> +#string STR_MISC_MEM_BANK_LOCATOR1 #language en-US "BANK 1"
> +#string STR_MISC_MEM_MANUFACTURER #language en-US "Micron"
> +#string STR_MISC_MEM_SERIAL_NO #language en-US " "
> +#string STR_MISC_MEM_ASSET_TAG #language en-US " "
> +#string STR_MISC_MEM_PART_NUMBER #language en-US " "
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceDat
> a.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceDat
> a.c
> new file mode 100644
> index 0000000000..4a416dfdeb
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceDat
> a.c
> @@ -0,0 +1,45 @@
> +/*++
> +
> +Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscMemoryDeviceData.c
> +
> +Abstract:
> +
> + Memory Device
> + Misc. subclass type 17.
> + SMBIOS type 17.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +#include "MiscSubclassDriver.h"
> +
> +MISC_SMBIOS_TABLE_DATA(EFI_MEMORY_ARRAY_LINK_DATA,
> MiscMemoryDevice) = {
> + STRING_TOKEN (STR_MISC_MEM_DEV_LOCATOR0), // Memory
> Device locator
> + STRING_TOKEN (STR_MISC_MEM_BANK_LOCATOR0), // Memory
> Bank Locator
> + STRING_TOKEN (STR_MISC_MEM_MANUFACTURER), // Memory
> manufacturer
> + STRING_TOKEN (STR_MISC_MEM_SERIAL_NO), // Memory
> serial Number
> + STRING_TOKEN (STR_MISC_MEM_ASSET_TAG), // Memory
> Asset Tag
> + STRING_TOKEN (STR_MISC_MEM_PART_NUMBER), // Memory
> Part Number
> + 0,
> // Memory Array Link
> + 0, // Memory SubArray
> link
> + 0, // UINT16
> MemoryTotalWidth
> + 0, // UINT16
> MemoryDatawidth
> + 0,
> // Memory Device Size
> + EfiMemoryFormFactorDip, // Memory Form Factor
> + 2, // UINT8 Memory Device type
> + EfiMemoryTypeDram, // Memory Type
> + 0, // Memory Type Detail
> + 0,
> // Memory Speed
> + 0 // Memory State
> +
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceFu
> nction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceFu
> nction.c
> new file mode 100644
> index 0000000000..3872312c30
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceFu
> nction.c
> @@ -0,0 +1,319 @@
> +/*++
> +
> +Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscMemoryDeviceFunction.c
> +
> +Abstract:
> +
> + Memory Device
> + Misc. subclass type 17.
> + SMBIOS type 17.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +#include "MiscSubclassDriver.h"
> +#include <Protocol/DataHub.h>
> +#include <Guid/DataHubRecords.h>
> +#include <Protocol/MemInfo.h>
> +
> +
> +#define FREQ_800 0x00
> +#define FREQ_1066 0x01
> +#define FREQ_1333 0x02
> +#define FREQ_1600 0x03
> +
> +#define MAX_SOCKETS 2
> +#define EfiMemoryTypeDdr3 0x18
> +
> +enum {
> + DDRType_DDR3 = 0,
> + DDRType_DDR3L = 1,
> + DDRType_DDR3U = 2,
> + DDRType_DDR3All = 3,
> + DDRType_LPDDR2 = 4,
> + DDRType_LPDDR3 = 5,
> + DDRType_DDR4 = 6
> +};
> +
> +
> +typedef struct {
> + EFI_PHYSICAL_ADDRESS MemoryArrayStartAddress;
> + EFI_PHYSICAL_ADDRESS MemoryArrayEndAddress;
> + EFI_INTER_LINK_DATA PhysicalMemoryArrayLink;
> + UINT16 MemoryArrayPartitionWidth;
> +} EFI_MEMORY_ARRAY_START_ADDRESS;
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscBiosVendor (Type 0).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +VOID
> +GetType16Hndl (
> + IN EFI_SMBIOS_PROTOCOL *Smbios,
> + OUT EFI_SMBIOS_HANDLE *Handle
> + )
> +{
> + EFI_STATUS Status;
> + EFI_SMBIOS_TYPE RecordType;
> + EFI_SMBIOS_TABLE_HEADER *Buffer;
> +
> + *Handle = 0;
> + RecordType = EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY;
> +
> + Status = Smbios->GetNext (
> + Smbios,
> + Handle,
> + &RecordType,
> + &Buffer,
> + NULL
> + );
> + if (!EFI_ERROR(Status)) {
> + return;
> + }
> + *Handle = 0xFFFF;
> +}
> +
> +MISC_SMBIOS_TABLE_FUNCTION( MiscMemoryDevice )
> +{
> + CHAR8 *OptionalStrStart;
> + UINTN MemDeviceStrLen;
> + UINTN MemBankLocatorStrLen;
> + UINTN MemManufacturerStrLen;
> + UINTN MemSerialNumberStrLen;
> + UINTN MemAssetTagStrLen;
> + UINTN MemPartNumberStrLen;
> + CHAR16 *MemDevice;
> + CHAR16 *MemBankLocator;
> + CHAR16 *MemManufacturer;
> + CHAR16 *MemSerialNumber;
> + CHAR16 *MemAssetTag;
> + CHAR16 *MemPartNumber;
> + EFI_STATUS Status;
> + STRING_REF TokenToGet;
> + SMBIOS_TABLE_TYPE17 *SmbiosRecord;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + EFI_MEMORY_ARRAY_LINK_DATA *ForType17InputData;
> + UINT16 DdrFreq=0;
> + UINT16 Type16Handle=0;
> + MEM_INFO_PROTOCOL *MemInfoHob;
> + UINT8 MemoryType;
> +
> + UINT8 Dimm;
> + UINT8 NumSlots;
> + STRING_REF DevLocator[] = {
> + STRING_TOKEN(STR_MISC_MEM_DEV_LOCATOR0),
> STRING_TOKEN(STR_MISC_MEM_DEV_LOCATOR1)
> + };
> + STRING_REF BankLocator[] = {
> + STRING_TOKEN(STR_MISC_MEM_BANK_LOCATOR0),
> STRING_TOKEN(STR_MISC_MEM_BANK_LOCATOR1)
> + };
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> + ForType17InputData = (EFI_MEMORY_ARRAY_LINK_DATA
> *)RecordData;
> +
> + //
> + // Get Memory size parameters for each rank from the chipset registers
> + //
> + Status = gBS->LocateProtocol (
> + &gMemInfoProtocolGuid,
> + NULL,
> + (void **)&MemInfoHob
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + NumSlots = (UINT8)(MAX_SOCKETS);
> +
> + //
> + // Memory Freq
> + //
> + switch (MemInfoHob->MemInfoData.ddrFreq){
> + case FREQ_800:
> + DdrFreq = 800;
> + break;
> + case FREQ_1066:
> + DdrFreq = 1066;
> + break;
> + case FREQ_1333:
> + DdrFreq = 1333;
> + break;
> + case FREQ_1600:
> + DdrFreq = 1600;
> + break;
> + default:
> + DdrFreq = 0;
> + break;
> + }
> +
> + //
> + // Memory Type
> + //
> + switch (MemInfoHob->MemInfoData.ddrType) {
> + case DDRType_LPDDR2:
> + MemoryType = EfiMemoryTypeDdr2;
> + break;
> + case DDRType_DDR3:
> + case DDRType_DDR3L:
> + case DDRType_DDR3U:
> + case DDRType_LPDDR3:
> + MemoryType = EfiMemoryTypeDdr3;
> + break;
> + default:
> + MemoryType = EfiMemoryTypeUnknown;
> + break;
> + }
> +
> + for (Dimm = 0; Dimm < NumSlots; Dimm++) {
> + //
> + // Memory Device Locator
> + //
> + TokenToGet = DevLocator[Dimm];
> + MemDevice = SmbiosMiscGetString (TokenToGet);
> + MemDeviceStrLen = StrLen(MemDevice);
> + if (MemDeviceStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = DevLocator[Dimm];
> + MemDevice = SmbiosMiscGetString (TokenToGet);
> + MemDeviceStrLen = StrLen(MemDevice);
> + if (MemDeviceStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Memory Bank Locator
> + //
> + TokenToGet = BankLocator[Dimm];
> + MemBankLocator = SmbiosMiscGetString (TokenToGet);
> + MemBankLocatorStrLen = StrLen(MemBankLocator);
> + if (MemBankLocatorStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Memory Manufacturer
> + //
> + TokenToGet = STRING_TOKEN (STR_MISC_MEM_MANUFACTURER);
> + MemManufacturer = SmbiosMiscGetString (TokenToGet);
> + MemManufacturerStrLen = StrLen(MemManufacturer);
> + if (MemManufacturerStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Memory Serial Number
> + //
> + TokenToGet = STRING_TOKEN (STR_MISC_MEM_SERIAL_NO);
> + MemSerialNumber = SmbiosMiscGetString (TokenToGet);
> + MemSerialNumberStrLen = StrLen(MemSerialNumber);
> + if (MemSerialNumberStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Memory Asset Tag Number
> + //
> + TokenToGet = STRING_TOKEN (STR_MISC_MEM_ASSET_TAG);
> + MemAssetTag = SmbiosMiscGetString (TokenToGet);
> + MemAssetTagStrLen = StrLen(MemAssetTag);
> + if (MemAssetTagStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Memory Part Number
> + //
> + TokenToGet = STRING_TOKEN (STR_MISC_MEM_PART_NUMBER);
> + MemPartNumber = SmbiosMiscGetString (TokenToGet);
> + MemPartNumberStrLen = StrLen(MemPartNumber);
> + if (MemPartNumberStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE17) +
> MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 +
> MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1 +
> MemAssetTagStrLen+1 + MemPartNumberStrLen + 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE17) +
> MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 +
> MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1 +
> MemAssetTagStrLen+1 + MemPartNumberStrLen + 1 + 1);
> +
> + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_DEVICE;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE17);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + //
> + // Memory Array Handle will be the 3rd optional string following the
> formatted structure.
> + //
> + GetType16Hndl( Smbios, &Type16Handle);
> + SmbiosRecord->MemoryArrayHandle = Type16Handle;
> +
> + //
> + // Memory Size
> + //
> + if ((MemInfoHob->MemInfoData.dimmSize[Dimm])!=0){
> + SmbiosRecord->TotalWidth = 32;
> + SmbiosRecord->DataWidth = 32;
> + SmbiosRecord->Size = MemInfoHob->MemInfoData.dimmSize[Dimm];
> + SmbiosRecord->Speed = DdrFreq;
> + SmbiosRecord->ConfiguredMemoryClockSpeed = DdrFreq;
> + SmbiosRecord->FormFactor = EfiMemoryFormFactorDimm;
> + }
> +
> + SmbiosRecord->DeviceSet =(UINT8) ForType17InputData-
> >MemoryDeviceSet;
> + SmbiosRecord->DeviceLocator= 1;
> + SmbiosRecord->BankLocator = 2;
> +
> +
> + SmbiosRecord->Manufacturer = 3;
> + SmbiosRecord->SerialNumber= 4;
> + SmbiosRecord->AssetTag= 5;
> + SmbiosRecord->PartNumber= 6;
> + SmbiosRecord->Attributes = (UINT8) ForType17InputData->MemoryState;
> + SmbiosRecord->MemoryType = MemoryType;
> +
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(MemDevice, OptionalStrStart);
> + UnicodeStrToAsciiStr(MemBankLocator, OptionalStrStart +
> MemDeviceStrLen + 1);
> + UnicodeStrToAsciiStr(MemManufacturer, OptionalStrStart +
> MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1);
> + UnicodeStrToAsciiStr(MemSerialNumber, OptionalStrStart +
> MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 +
> MemManufacturerStrLen + 1);
> + UnicodeStrToAsciiStr(MemAssetTag, OptionalStrStart +
> MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 +
> MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1);
> + UnicodeStrToAsciiStr(MemPartNumber, OptionalStrStart +
> MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 +
> MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1+
> MemAssetTagStrLen+1 );
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + FreePool(SmbiosRecord);
> + }
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstalla
> bleLanguagesData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstalla
> bleLanguagesData.c
> new file mode 100644
> index 0000000000..1b41d8fac7
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstalla
> bleLanguagesData.c
> @@ -0,0 +1,38 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscNumberOfInstallableLanguagesData.c
> +
> +Abstract:
> +
> + Static data of the Number of installable languages information.
> + Number of installable languages information is Misc. subclass type 11 and
> SMBIOS type 13.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) Bios Vendor data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_NUMBER_OF_INSTALLABLE_LANG
> UAGES_DATA, NumberOfInstallableLanguages)
> += {
> + 1, // NumberOfInstallableLanguages
> + { // LanguageFlags
> + 1, // AbbreviatedLanguageFormat
> + 0 // Reserved
> + },
> + STRING_TOKEN(STR_MISC_SYSTEM_LANGUAGE_EN_US) //
> CurrentLanguageNumber
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstalla
> bleLanguagesFunction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstalla
> bleLanguagesFunction.c
> new file mode 100644
> index 0000000000..4a96a2c465
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstalla
> bleLanguagesFunction.c
> @@ -0,0 +1,251 @@
> +/*++
> +
> +Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>
> +
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +
> +
> +Module Name:
> +
> + MiscNumberOfInstallableLanguagesFunction.c
> +
> +Abstract:
> +
> + This driver parses the mSmbiosMiscDataTable structure and reports
> + any generated data.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +/**
> + Check whether the language is supported for given HII handle
> +
> + @param HiiHandle The HII package list handle.
> + @param Offset The offest of current lanague in the supported
> languages.
> + @param CurrentLang The language code.
> +
> + @retval TRUE Supported.
> + @retval FALSE Not Supported.
> +
> +**/
> +VOID
> +EFIAPI
> +CurrentLanguageMatch (
> + IN EFI_HII_HANDLE HiiHandle,
> + OUT UINT16 *Offset,
> + OUT CHAR8 *CurrentLang
> + )
> +{
> + CHAR8 *DefaultLang;
> + CHAR8 *BestLanguage;
> + CHAR8 *Languages;
> + CHAR8 *MatchLang;
> + CHAR8 *EndMatchLang;
> + UINTN CompareLength;
> +
> + Languages = HiiGetSupportedLanguages (HiiHandle);
> + if (Languages == NULL) {
> + return;
> + }
> +
> + CurrentLang = GetEfiGlobalVariable (L"PlatformLang");
> + DefaultLang = (CHAR8 *) PcdGetPtr (PcdUefiVariableDefaultPlatformLang);
> + BestLanguage = GetBestLanguage (
> + Languages,
> + FALSE,
> + (CurrentLang != NULL) ? CurrentLang : "",
> + DefaultLang,
> + NULL
> + );
> + if (BestLanguage != NULL) {
> + //
> + // Find the best matching RFC 4646 language, compute the offset.
> + //
> + CompareLength = AsciiStrLen (BestLanguage);
> + for (MatchLang = Languages, (*Offset) = 0; *MatchLang != '\0';
> (*Offset)++) {
> + //
> + // Seek to the end of current match language.
> + //
> + for (EndMatchLang = MatchLang; *EndMatchLang != '\0' &&
> *EndMatchLang != ';'; EndMatchLang++);
> +
> + if ((EndMatchLang == MatchLang + CompareLength) &&
> AsciiStrnCmp(MatchLang, BestLanguage, CompareLength) == 0) {
> + //
> + // Find the current best Language in the supported languages
> + //
> + break;
> + }
> + //
> + // best language match be in the supported language.
> + //
> + ASSERT (*EndMatchLang == ';');
> + MatchLang = EndMatchLang + 1;
> + }
> + FreePool (BestLanguage);
> + }
> +
> + FreePool (Languages);
> + if (CurrentLang != NULL) {
> + FreePool (CurrentLang);
> + }
> + return ;
> +}
> +
> +
> +/**
> + Get next language from language code list (with separator ';').
> +
> + @param LangCode Input: point to first language in the list. On
> + Otput: point to next language in the list, or
> + NULL if no more language in the list.
> + @param Lang The first language in the list.
> +
> +**/
> +VOID
> +EFIAPI
> +GetNextLanguage (
> + IN OUT CHAR8 **LangCode,
> + OUT CHAR8 *Lang
> + )
> +{
> + UINTN Index;
> + CHAR8 *StringPtr;
> +
> + ASSERT (LangCode != NULL);
> + ASSERT (*LangCode != NULL);
> + ASSERT (Lang != NULL);
> +
> + Index = 0;
> + StringPtr = *LangCode;
> + while (StringPtr[Index] != 0 && StringPtr[Index] != ';') {
> + Index++;
> + }
> +
> + CopyMem (Lang, StringPtr, Index);
> + Lang[Index] = 0;
> +
> + if (StringPtr[Index] == ';') {
> + Index++;
> + }
> + *LangCode = StringPtr + Index;
> +}
> +
> +/**
> + This function returns the number of supported languages on HiiHandle.
> +
> + @param HiiHandle The HII package list handle.
> +
> + @retval The number of supported languages.
> +
> +**/
> +UINT16
> +EFIAPI
> +GetSupportedLanguageNumber (
> + IN EFI_HII_HANDLE HiiHandle
> + )
> +{
> + CHAR8 *Lang;
> + CHAR8 *Languages;
> + CHAR8 *LanguageString;
> + UINT16 LangNumber;
> +
> + Languages = HiiGetSupportedLanguages (HiiHandle);
> + if (Languages == NULL) {
> + return 0;
> + }
> +
> + LangNumber = 0;
> + Lang = AllocatePool (AsciiStrSize (Languages));
> + if (Lang != NULL) {
> + LanguageString = Languages;
> + while (*LanguageString != 0) {
> + GetNextLanguage (&LanguageString, Lang);
> + LangNumber++;
> + }
> + FreePool (Lang);
> + }
> + FreePool (Languages);
> + return LangNumber;
> +}
> +
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscNumberOfInstallableLanguages (Type 13).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION(NumberOfInstallableLanguages)
> +{
> + UINTN LangStrLen;
> + CHAR8 CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1];
> + CHAR8 *OptionalStrStart;
> + UINT16 Offset;
> + EFI_STATUS Status;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE13 *SmbiosRecord;
> + EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES
> *ForType13InputData;
> +
> + ForType13InputData =
> (EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES *)RecordData;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + ForType13InputData->NumberOfInstallableLanguages =
> GetSupportedLanguageNumber (mHiiHandle);
> +
> + //
> + // Try to check if current langcode matches with the langcodes in installed
> languages
> + //
> + ZeroMem(CurrentLang, SMBIOS_STRING_MAX_LENGTH + 1);
> + CurrentLanguageMatch (mHiiHandle, &Offset, CurrentLang);
> + LangStrLen = AsciiStrLen(CurrentLang);
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE13) +
> LangStrLen + 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE13) + LangStrLen + 1
> + 1);
> +
> + SmbiosRecord->Hdr.Type =
> EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE13);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + SmbiosRecord->InstallableLanguages = (UINT8)ForType13InputData-
> >NumberOfInstallableLanguages;
> + SmbiosRecord->Flags = (UINT8)ForType13InputData-
> >LanguageFlags.AbbreviatedLanguageFormat;
> + SmbiosRecord->CurrentLanguages = 1;
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + AsciiStrCpy(OptionalStrStart, CurrentLang);
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemString.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemString.uni
> new file mode 100644
> index 0000000000..c6eb8bf498
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemString.uni
> @@ -0,0 +1,25 @@
> +// *++
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscOemSring.uni
> +//
> +// Abstract:
> +//
> +// Language Information
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +#string STR_INTEL_ETK_VER #language en-US "ETK_VER_02.01"
> +#string STR_INTEL_ETK_VER_FOR_ROEM #language en-US
> "ETK_VER_02.00"
> +#string STR_MISC_OEM_EN_US #language en-US "English (US)"
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringData.c
> new file mode 100644
> index 0000000000..ceecaad549
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringData.c
> @@ -0,0 +1,34 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscOemStringData.c
> +
> +Abstract:
> +
> + Static data of OEM String information.
> + OEM String information is Misc. subclass type 9 and SMBIOS type 11.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) Bios Vendor data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_STRING, MiscOemString) = {
> + STRING_TOKEN(STR_INTEL_ETK_VER)
> +};
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_STRING_DATA, OemString)
> += { STRING_TOKEN(STR_MISC_OEM_EN_US) };
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringFunctio
> n.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringFunctio
> n.c
> new file mode 100644
> index 0000000000..8624481149
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringFunctio
> n.c
> @@ -0,0 +1,89 @@
> +/*++
> +
> +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + MiscOemStringFunction.c
> +
> +Abstract:
> +
> + boot information boot time changes.
> + SMBIOS type 11.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscOemString (Type 11).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION(OemString)
> +{
> + UINTN OemStrLen;
> + CHAR8 *OptionalStrStart;
> + EFI_STATUS Status;
> + EFI_STRING OemStr;
> + STRING_REF TokenToGet;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE11 *SmbiosRecord;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_OEM_EN_US);
> + OemStr = SmbiosMiscGetString (TokenToGet);
> + OemStrLen = StrLen(OemStr);
> + if (OemStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE11) +
> OemStrLen + 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE11) + OemStrLen +
> 1 + 1);
> +
> + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_OEM_STRINGS;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE11);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> + SmbiosRecord->StringCount = 1;
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(OemStr, OptionalStrStart);
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90.uni
> new file mode 100644
> index 0000000000..917a7b9d6e
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90.uni
> @@ -0,0 +1,31 @@
> +// *++
> +//
> +// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscOemType0x90.uni
> +//
> +// Abstract:
> +//
> +// Firmware Version Information
> +// SMBIOS type 0x90.
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +#langdef en-US "English"
> +
> +#string STR_MISC_SEC_VERSION #language en-US "NA"
> +#string STR_MISC_UCODE_VERSION #language en-US "NA"
> +#string STR_MISC_GOP_VERSION #language en-US "NA"
> +#string STR_MISC_PROCESSOR_STEPPING #language en-US "NA"
> +
> +
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Data
> .c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Dat
> a.c
> new file mode 100644
> index 0000000000..9b348813a7
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Dat
> a.c
> @@ -0,0 +1,36 @@
> +/*++
> +
> +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +Module Name:
> +
> + MiscOemType0x90Data.c
> +
> +Abstract:
> +
> + This file contains the Misc Oem Data (SMBIOS data type 0x90)
> +
> +--*/
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +
> +//
> +// Static (possibly build generated) Oem data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_TYPE_0x90,
> MiscOemType0x90) = {
> +
> +STRING_TOKEN (STR_MISC_SEC_VERSION),
> +STRING_TOKEN (STR_MISC_UCODE_VERSION),
> +STRING_TOKEN (STR_MISC_GOP_VERSION),
> +STRING_TOKEN (STR_MISC_PROCESSOR_STEPPING),
> +
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Fun
> ction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Fun
> ction.c
> new file mode 100644
> index 0000000000..684cda83ec
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Fun
> ction.c
> @@ -0,0 +1,442 @@
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +Module Name:
> +
> + MiscOemType0x88Function.c
> +
> +Abstract:
> +
> + The function that processes the Smbios data type 0x88 before they
> + are submitted to Data Hub
> +
> +--*/
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +#include <Library/PrintLib.h>
> +#include <Library/CpuIA32.h>
> +#include <Protocol/DxeSmmReadyToLock.h>
> +
> +
> +VOID
> +GetCPUStepping ( )
> +{
> + CHAR16 Buffer[40];
> +
> + UINT16 FamilyId;
> + UINT8 Model;
> + UINT8 SteppingId;
> + UINT8 ProcessorType;
> +
> +
> + EfiCpuVersion (&FamilyId, &Model, &SteppingId, &ProcessorType);
> +
> + //
> + //we need raw Model data
> + //
> + Model = Model & 0xf;
> +
> + //
> + //Family/Model/Step
> + //
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%d/%d/%d", FamilyId, Model,
> SteppingId);
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_PROCESSOR_STEPPING),
> Buffer, NULL);
> +
> +}
> +
> +EFI_STATUS
> +SearchChildHandle(
> + EFI_HANDLE Father,
> + EFI_HANDLE *Child
> + )
> +{
> + EFI_STATUS Status;
> + UINTN HandleIndex;
> + EFI_GUID **ProtocolGuidArray = NULL;
> + UINTN ArrayCount;
> + UINTN ProtocolIndex;
> + UINTN OpenInfoCount;
> + UINTN OpenInfoIndex;
> + EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfo = NULL;
> + UINTN mHandleCount;
> + EFI_HANDLE *mHandleBuffer= NULL;
> +
> + //
> + // Retrieve the list of all handles from the handle database
> + //
> + Status = gBS->LocateHandleBuffer (
> + AllHandles,
> + NULL,
> + NULL,
> + &mHandleCount,
> + &mHandleBuffer
> + );
> +
> + for (HandleIndex = 0; HandleIndex < mHandleCount; HandleIndex++) {
> + //
> + // Retrieve the list of all the protocols on each handle
> + //
> + Status = gBS->ProtocolsPerHandle (
> + mHandleBuffer[HandleIndex],
> + &ProtocolGuidArray,
> + &ArrayCount
> + );
> + if (!EFI_ERROR (Status)) {
> + for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++) {
> + Status = gBS->OpenProtocolInformation (
> + mHandleBuffer[HandleIndex],
> + ProtocolGuidArray[ProtocolIndex],
> + &OpenInfo,
> + &OpenInfoCount
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount;
> OpenInfoIndex++) {
> + if(OpenInfo[OpenInfoIndex].AgentHandle == Father) {
> + if ((OpenInfo[OpenInfoIndex].Attributes &
> EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) ==
> EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {
> + *Child = mHandleBuffer[HandleIndex];
> + Status = EFI_SUCCESS;
> + goto TryReturn;
> + }
> + }
> + }
> + Status = EFI_NOT_FOUND;
> + }
> + }
> + if(OpenInfo != NULL) {
> + FreePool(OpenInfo);
> + OpenInfo = NULL;
> + }
> + }
> + if(ProtocolGuidArray != NULL) {
> + FreePool (ProtocolGuidArray);
> + ProtocolGuidArray = NULL;
> + }
> + }
> +TryReturn:
> + if(OpenInfo != NULL) {
> + FreePool (OpenInfo);
> + OpenInfo = NULL;
> + }
> + if(ProtocolGuidArray != NULL) {
> + FreePool(ProtocolGuidArray);
> + ProtocolGuidArray = NULL;
> + }
> + if(mHandleBuffer != NULL) {
> + FreePool (mHandleBuffer);
> + mHandleBuffer = NULL;
> + }
> + return Status;
> +}
> +
> +EFI_STATUS
> +JudgeHandleIsPCIDevice(
> + EFI_HANDLE Handle,
> + UINT8 Device,
> + UINT8 Funs
> + )
> +{
> + EFI_STATUS Status;
> + EFI_DEVICE_PATH *DPath;
> +
> + Status = gBS->HandleProtocol (
> + Handle,
> + &gEfiDevicePathProtocolGuid,
> + (VOID **) &DPath
> + );
> + if(!EFI_ERROR(Status)) {
> + while(!IsDevicePathEnd(DPath)) {
> + if((DPath->Type == HARDWARE_DEVICE_PATH) && (DPath->SubType ==
> HW_PCI_DP)) {
> + PCI_DEVICE_PATH *PCIPath;
> + PCIPath = (PCI_DEVICE_PATH*) DPath;
> + DPath = NextDevicePathNode(DPath);
> +
> + if(IsDevicePathEnd(DPath) && (PCIPath->Device == Device) &&
> (PCIPath->Function == Funs)) {
> + return EFI_SUCCESS;
> + }
> + } else {
> + DPath = NextDevicePathNode(DPath);
> + }
> + }
> + }
> + return EFI_UNSUPPORTED;
> +}
> +
> +EFI_STATUS
> +GetDriverName(
> + EFI_HANDLE Handle
> +)
> +{
> + EFI_DRIVER_BINDING_PROTOCOL *BindHandle = NULL;
> + EFI_STATUS Status;
> + UINT32 Version;
> + UINT16 *Ptr;
> + CHAR16 Buffer[40];
> + STRING_REF TokenToUpdate;
> + Status = gBS->OpenProtocol(
> + Handle,
> + &gEfiDriverBindingProtocolGuid,
> + (VOID**)&BindHandle,
> + NULL,
> + NULL,
> + EFI_OPEN_PROTOCOL_GET_PROTOCOL
> + );
> +
> + if (EFI_ERROR(Status)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + Version = BindHandle->Version;
> + Ptr = (UINT16*)&Version;
> + UnicodeSPrint(Buffer, sizeof (Buffer), L"%d.%d.%d", Version >> 24 ,
> (Version >>16)& 0x0f ,*(Ptr));
> +
> + TokenToUpdate = (STRING_REF)STR_MISC_GOP_VERSION;
> + HiiSetString(mHiiHandle, TokenToUpdate, Buffer, NULL);
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +GetGOPDriverName()
> +{
> + UINTN HandleCount;
> + EFI_HANDLE *Handles= NULL;
> + UINTN Index;
> + EFI_STATUS Status;
> + EFI_HANDLE Child = 0;
> +
> + Status = gBS->LocateHandleBuffer(
> + ByProtocol,
> + &gEfiDriverBindingProtocolGuid,
> + NULL,
> + &HandleCount,
> + &Handles
> + );
> +
> + for (Index = 0; Index < HandleCount ; Index++) {
> + Status = SearchChildHandle(Handles[Index], &Child);
> + if(!EFI_ERROR(Status)) {
> + Status = JudgeHandleIsPCIDevice(Child, 0x02, 0x00);
> + if(!EFI_ERROR(Status)) {
> + return GetDriverName(Handles[Index]);
> + }
> + }
> + }
> + return EFI_UNSUPPORTED;
> +}
> +
> +VOID
> +GetUcodeVersion()
> +{
> + UINT32 MicroCodeVersion;
> + CHAR16 Buffer[40];
> +
> + //
> + // Microcode Revision
> + //
> + EfiWriteMsr (EFI_MSR_IA32_BIOS_SIGN_ID, 0);
> + EfiCpuid (EFI_CPUID_VERSION_INFO, NULL);
> + MicroCodeVersion = (UINT32) RShiftU64 (EfiReadMsr
> (EFI_MSR_IA32_BIOS_SIGN_ID), 32);
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", MicroCodeVersion);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_UCODE_VERSION),
> Buffer, NULL);
> +}
> +
> +/**
> + Publish the smbios OEM type 0x90.
> +
> + @param Event - Event whose notification function is being invoked
> (gEfiDxeSmmReadyToLockProtocolGuid).
> + @param Context - Pointer to the notification functions context, which is
> implementation dependent.
> +
> + @retval None
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +AddSmbiosT0x90Callback (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> + UINTN SECVerStrLen = 0;
> + UINTN uCodeVerStrLen = 0;
> + UINTN GOPStrLen = 0;
> + UINTN SteppingStrLen = 0;
> + SMBIOS_TABLE_TYPE90 *SmbiosRecord;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + CHAR16 *SECVer;
> + CHAR16 *uCodeVer;
> + CHAR16 *GOPVer;
> + CHAR16 *Stepping;
> + STRING_REF TokenToGet;
> + CHAR8 *OptionalStrStart;
> + EFI_SMBIOS_PROTOCOL *SmbiosProtocol;
> +
> + DEBUG ((EFI_D_INFO, "Executing SMBIOS T0x90 callback.\n"));
> +
> + gBS->CloseEvent (Event); // Unload this event.
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (Context == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Status = gBS->LocateProtocol (
> + &gEfiSmbiosProtocolGuid,
> + NULL,
> + (VOID *) &SmbiosProtocol
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + GetUcodeVersion();
> + GetGOPDriverName();
> + GetCPUStepping();
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_SEC_VERSION);
> + SECVer = SmbiosMiscGetString (TokenToGet);
> + SECVerStrLen = StrLen(SECVer);
> + if (SECVerStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_UCODE_VERSION);
> + uCodeVer = SmbiosMiscGetString (TokenToGet);
> + uCodeVerStrLen = StrLen(uCodeVer);
> + if (uCodeVerStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_GOP_VERSION);
> + GOPVer = SmbiosMiscGetString (TokenToGet);
> + GOPStrLen = StrLen(GOPVer);
> + if (GOPStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_PROCESSOR_STEPPING);
> + Stepping = SmbiosMiscGetString (TokenToGet);
> + SteppingStrLen = StrLen(Stepping);
> +
> +
> + if (SteppingStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE90) +
> SECVerStrLen + 1 + uCodeVerStrLen + 1 + GOPStrLen + 1 + SteppingStrLen + 1
> + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE90) + SECVerStrLen
> + 1 + uCodeVerStrLen + 1 + GOPStrLen + 1 + SteppingStrLen + 1 + 1);
> +
> + SmbiosRecord->Hdr.Type =
> EFI_SMBIOS_TYPE_FIRMWARE_VERSION_INFO;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE90);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + //
> + // SEC VERSION will be the 1st optional string following the formatted
> structure.
> + //
> + SmbiosRecord->SECVersion = 0;
> +
> + //
> + // Microcode VERSION will be the 2nd optional string following the
> formatted structure.
> + //
> + SmbiosRecord->uCodeVersion = 2;
> +
> + //
> + // GOP VERSION will be the 3rd optional string following the formatted
> structure.
> + //
> + SmbiosRecord->GOPVersion = 3;
> +
> + //
> + // CPU Stepping will be the 4th optional string following the formatted
> structure.
> + //
> + SmbiosRecord->CpuStepping = 4;
> +
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(SECVer, OptionalStrStart);
> + UnicodeStrToAsciiStr(uCodeVer, OptionalStrStart + SECVerStrLen + 1);
> + UnicodeStrToAsciiStr(GOPVer, OptionalStrStart + SECVerStrLen + 1 +
> uCodeVerStrLen + 1);
> + UnicodeStrToAsciiStr(Stepping, OptionalStrStart + SECVerStrLen + 1 +
> uCodeVerStrLen + 1 + GOPStrLen + 1);
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = SmbiosProtocol-> Add(
> + SmbiosProtocol,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> +
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> +
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscOemType0x90 (Type 0x90).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION(MiscOemType0x90)
> +{
> + EFI_STATUS Status;
> + static BOOLEAN CallbackIsInstalledT0x90 = FALSE;
> + VOID *AddSmbiosT0x90CallbackNotifyReg;
> + EFI_EVENT AddSmbiosT0x90CallbackEvent;
> +
> + //
> + // This callback will create a OEM Type 0x90 record.
> + //
> + if (CallbackIsInstalledT0x90 == FALSE) {
> + CallbackIsInstalledT0x90 = TRUE; // Prevent more than 1
> callback.
> + DEBUG ((EFI_D_INFO, "Create Smbios T0x90 callback.\n"));
> +
> + //
> + // gEfiDxeSmmReadyToLockProtocolGuid is ready
> + //
> + Status = gBS->CreateEvent (
> + EVT_NOTIFY_SIGNAL,
> + TPL_CALLBACK,
> + (EFI_EVENT_NOTIFY)AddSmbiosT0x90Callback,
> + RecordData,
> + &AddSmbiosT0x90CallbackEvent
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + return Status;
> +
> + }
> +
> + Status = gBS->RegisterProtocolNotify (
> + &gEfiDxeSmmReadyToLockProtocolGuid,
> + AddSmbiosT0x90CallbackEvent,
> + &AddSmbiosT0x90CallbackNotifyReg
> + );
> +
> + return Status;
> + }
> +
> + return EFI_SUCCESS;
> +
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94.uni
> new file mode 100644
> index 0000000000..2c8bf4ce49
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94.uni
> @@ -0,0 +1,42 @@
> +// *++
> +//
> +// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscOemType0x94.uni
> +//
> +// Abstract:
> +//
> +// Firmware Version Information
> +// SMBIOS type 0x94.
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +#langdef en-US "English"
> +
> +#string STR_MISC_PMIC_VERSION #language en-US "NA"
> +#string STR_MISC_TOUCH_VERSION #language en-US "NA"
> +#string STR_MISC_PROCESSOR_MICROCODE_VALUE #language en-US
> "NA"
> +#string STR_MISC_ULPMC_FW_VALUE #language en-US "NA"
> +#string STR_MISC_PUNIT_FW_VALUE #language en-US "NA"
> +#string STR_MISC_PMC_FW_VALUE #language en-US "NA"
> +#string STR_MISC_SOC_VALUE #language en-US "NA"
> +#string STR_MISC_MRC_VERSION_VALUE #language en-US "NA"
> +#string STR_MISC_BOARD_ID_VALUE #language en-US "NA"
> +#string STR_MISC_FAB_ID_VALUE #language en-US "NA"
> +#string STR_MISC_CPU_FLAVOR_VALUE #language en-US "NA"
> +#string STR_MISC_SECURE_BOOT #language en-US "NA"
> +#string STR_MISC_BOOT_MODE #language en-US "NA"
> +#string STR_MISC_SPEED_STEP #language en-US "NA"
> +#string STR_MISC_CPU_TURBO #language en-US "NA"
> +#string STR_MISC_CSTATE #language en-US "NA"
> +#string STR_MISC_GFX_TURBO #language en-US "NA"
> +#string STR_MISC_S0IX_VALUE #language en-US "NA"
> +#string STR_MISC_RC6_VALUE #language en-US "NA"
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Data
> .c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Dat
> a.c
> new file mode 100644
> index 0000000000..8709d61847
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Dat
> a.c
> @@ -0,0 +1,54 @@
> +/*++
> +
> +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +Module Name:
> +
> + MiscOemType0x94Data.c
> +
> +Abstract:
> +
> + This file contains the Misc version Data (SMBIOS data type 0x94)
> +
> +--*/
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +
> +//
> +// Static (possibly build generated) Oem data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_TYPE_0x94,
> MiscOemType0x94) = {
> +
> +STRING_TOKEN (STR_MISC_GOP_VERSION),
> +STRING_TOKEN (STR_MISC_SEC_VERSION),
> +STRING_TOKEN (STR_MISC_MRC_VERSION_VALUE),
> +STRING_TOKEN (STR_MISC_UCODE_VERSION),
> +STRING_TOKEN (STR_MISC_PUNIT_FW_VALUE),
> +STRING_TOKEN (STR_MISC_PMC_FW_VALUE),
> +STRING_TOKEN (STR_MISC_ULPMC_FW_VALUE),
> +STRING_TOKEN (STR_MISC_SOC_VALUE),
> +STRING_TOKEN (STR_MISC_BOARD_ID_VALUE),
> +STRING_TOKEN (STR_MISC_FAB_ID_VALUE),
> +STRING_TOKEN (STR_MISC_CPU_FLAVOR_VALUE),
> +STRING_TOKEN (STR_MISC_BIOS_VERSION),
> +STRING_TOKEN (STR_MISC_PMIC_VERSION),
> +STRING_TOKEN (STR_MISC_TOUCH_VERSION),
> +STRING_TOKEN (STR_MISC_SECURE_BOOT),
> +STRING_TOKEN (STR_MISC_BOOT_MODE),
> +STRING_TOKEN (STR_MISC_SPEED_STEP),
> +STRING_TOKEN (STR_MISC_CPU_TURBO),
> +STRING_TOKEN (STR_MISC_CSTATE),
> +STRING_TOKEN (STR_MISC_GFX_TURBO),
> +STRING_TOKEN (STR_MISC_S0IX_VALUE),
> +STRING_TOKEN (STR_MISC_RC6_VALUE),
> +
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Fun
> ction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Fun
> ction.c
> new file mode 100644
> index 0000000000..15c180129c
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Fun
> ction.c
> @@ -0,0 +1,1218 @@
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +Module Name:
> +
> + MiscOemType0x94Function.c
> +
> +Abstract:
> +
> + The function that processes the Smbios data type 0x94.
> +
> +--*/
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +#include <Protocol/DataHub.h>
> +#include <Library/HiiLib.h>
> +#include <Protocol/CpuIo2.h>
> +#include <Library/PrintLib.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include <Protocol/SimpleNetwork.h>
> +#include <Protocol/DevicePath.h>
> +#include <Protocol/DiskInfo.h>
> +#include <Protocol/IdeControllerInit.h>
> +#include <Protocol/MpService.h>
> +#include <Protocol/PchPlatformPolicy.h>
> +#include <Protocol/CpuIo2.h>
> +#include <Protocol/I2cBus.h>
> +
> +#include <Library/IoLib.h>
> +#include <Library/I2CLib.h>
> +#include <Library/CpuIA32.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Guid/PlatformInfo.h>
> +#include <Guid/SetupVariable.h>
> +#include <Guid/Vlv2Variable.h>
> +
> +#include "Valleyview.h"
> +#include "VlvAccess.h"
> +#include "PchAccess.h"
> +#include "SetupMode.h"
> +#include "PchCommonDefinitions.h"
> +#include <PlatformBaseAddresses.h>
> +
> +typedef struct {
> + UINT8 RevId;
> + CHAR8 String[16];
> +} SB_REV;
> +
> +//
> +// Silicon Steppings
> +//
> +SB_REV SBRevisionTable[] = {
> + {V_PCH_LPC_RID_0, "(A0 Stepping)"},
> + {V_PCH_LPC_RID_1, "(A0 Stepping)"},
> + {V_PCH_LPC_RID_2, "(A1 Stepping)"},
> + {V_PCH_LPC_RID_3, "(A1 Stepping)"},
> + {V_PCH_LPC_RID_4, "(B0 Stepping)"},
> + {V_PCH_LPC_RID_5, "(B0 Stepping)"},
> + {V_PCH_LPC_RID_6, "(B1 Stepping)"},
> + {V_PCH_LPC_RID_7, "(B1 Stepping)"},
> + {V_PCH_LPC_RID_8, "(B2 Stepping)"},
> + {V_PCH_LPC_RID_9, "(B2 Stepping)"},
> + {V_PCH_LPC_RID_A, "(B3 Stepping)"},
> + {V_PCH_LPC_RID_B, "(B3 Stepping)"}
> +};
> +
> +#define LEFT_JUSTIFY 0x01
> +#define PREFIX_SIGN 0x02
> +#define PREFIX_BLANK 0x04
> +#define COMMA_TYPE 0x08
> +#define LONG_TYPE 0x10
> +#define PREFIX_ZERO 0x20
> +
> +#define ICH_REG_REV 0x08
> +#define MSR_IA32_PLATFORM_ID 0x17
> +#define CHARACTER_NUMBER_FOR_VALUE 30
> +
> +
> +UINT8 ReadBuffer[20]; //Version report length
> +UINT8 WriteBuffer[22] =
> {0x40,0x01,0x14,0x00,0x06,0x51,0x02,0x07,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
> //Version request
> +
> +/**
> +
> + VSPrint worker function that prints a Value as a decimal number in Buffer
> +
> + @param Buffer Location to place ascii decimal number string of Value.
> + @param Value Decimal value to convert to a string in Buffer.
> + @param Flags Flags to use in printing decimal string, see file header for
> details.
> + @param Width Width of hex value.
> +
> + @retval Number of characters printed.
> +
> +**/
> +UINTN
> +EfiValueToString (
> + IN OUT CHAR16 *Buffer,
> + IN INT64 Value,
> + IN UINTN Flags,
> + IN UINTN Width
> + )
> +{
> + CHAR16 TempBuffer[CHARACTER_NUMBER_FOR_VALUE];
> + CHAR16 *TempStr;
> + CHAR16 *BufferPtr;
> + UINTN Count;
> + UINTN ValueCharNum;
> + UINTN Remainder;
> + CHAR16 Prefix;
> + UINTN Index;
> + BOOLEAN ValueIsNegative;
> + UINT64 TempValue;
> +
> + TempStr = TempBuffer;
> + BufferPtr = Buffer;
> + Count = 0;
> + ValueCharNum = 0;
> + ValueIsNegative = FALSE;
> +
> + if (Width > CHARACTER_NUMBER_FOR_VALUE - 1) {
> + Width = CHARACTER_NUMBER_FOR_VALUE - 1;
> + }
> +
> + if (Value < 0) {
> + Value = -Value;
> + ValueIsNegative = TRUE;
> + }
> +
> + do {
> + TempValue = Value;
> + Value = (INT64)DivU64x32 ((UINT64)Value, 10);
> + Remainder = (UINTN)((UINT64)TempValue - 10 * Value);
> + *(TempStr++) = (CHAR16)(Remainder + '0');
> + ValueCharNum++;
> + Count++;
> + if ((Flags & COMMA_TYPE) == COMMA_TYPE) {
> + if (ValueCharNum % 3 == 0 && Value != 0) {
> + *(TempStr++) = ',';
> + Count++;
> + }
> + }
> + } while (Value != 0);
> +
> + if (ValueIsNegative) {
> + *(TempStr++) = '-';
> + Count++;
> + }
> +
> + if ((Flags & PREFIX_ZERO) && !ValueIsNegative) {
> + Prefix = '0';
> + } else {
> + Prefix = ' ';
> + }
> +
> + Index = Count;
> + if (!(Flags & LEFT_JUSTIFY)) {
> + for (; Index < Width; Index++) {
> + *(TempStr++) = Prefix;
> + }
> + }
> +
> + //
> + // Reverse temp string into Buffer.
> + //
> + if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {
> + TempStr = TempBuffer + Width;
> + }
> + Index = 0;
> + while (TempStr != TempBuffer) {
> + *(BufferPtr++) = *(--TempStr);
> + Index++;
> + }
> +
> + *BufferPtr = 0;
> + return Index;
> +}
> +
> +static CHAR16 mHexStr[] = { L'0', L'1', L'2', L'3', L'4', L'5', L'6', L'7',
> + L'8', L'9', L'A', L'B', L'C', L'D', L'E', L'F' };
> +/**
> + VSPrint worker function that prints a Value as a hex number in Buffer
> +
> + @param Buffer Location to place ascii hex string of Value.
> + @param Value Hex value to convert to a string in Buffer.
> + @param Flags Flags to use in printing Hex string, see file header for
> details.
> + @param Width Width of hex value.
> +
> + @retval Number of characters printed.
> +
> +**/
> +UINTN
> +EfiValueToHexStr (
> + IN OUT CHAR16 *Buffer,
> + IN UINT64 Value,
> + IN UINTN Flags,
> + IN UINTN Width
> + )
> +{
> + CHAR16 TempBuffer[CHARACTER_NUMBER_FOR_VALUE];
> + CHAR16 *TempStr;
> + CHAR16 Prefix;
> + CHAR16 *BufferPtr;
> + UINTN Count;
> + UINTN Index;
> +
> + TempStr = TempBuffer;
> + BufferPtr = Buffer;
> +
> + //
> + // Count starts at one since we will null terminate. Each iteration of the
> + // loop picks off one nibble. Oh yea TempStr ends up backwards
> + //
> + Count = 0;
> +
> + if (Width > CHARACTER_NUMBER_FOR_VALUE - 1) {
> + Width = CHARACTER_NUMBER_FOR_VALUE - 1;
> + }
> +
> + do {
> + Index = ((UINTN)Value & 0xf);
> + *(TempStr++) = mHexStr[Index];
> + Value = RShiftU64 (Value, 4);
> + Count++;
> + } while (Value != 0);
> +
> + if (Flags & PREFIX_ZERO) {
> + Prefix = '0';
> + } else {
> + Prefix = ' ';
> + }
> +
> + Index = Count;
> + if (!(Flags & LEFT_JUSTIFY)) {
> + for (; Index < Width; Index++) {
> + *(TempStr++) = Prefix;
> + }
> + }
> +
> + //
> + // Reverse temp string into Buffer.
> + //
> + if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {
> + TempStr = TempBuffer + Width;
> + }
> + Index = 0;
> + while (TempStr != TempBuffer) {
> + *(BufferPtr++) = *(--TempStr);
> + Index++;
> + }
> +
> + *BufferPtr = 0;
> + return Index;
> +}
> +
> +/**
> + Converts MAC address to Unicode string.
> + The value is 64-bit and the resulting string will be 12
> + digit hex number in pairs of digits separated by dashes.
> +
> + @param String - string that will contain the value
> + @param Val - value to convert
> +
> +**/
> +CHAR16 *
> +StrMacToString (
> + OUT CHAR16 *String,
> + IN EFI_MAC_ADDRESS *MacAddr,
> + IN UINT32 AddrSize
> + )
> +{
> + UINT32 i;
> +
> + for (i = 0; i < AddrSize; i++) {
> +
> + EfiValueToHexStr (
> + &String[2 * i],
> + MacAddr->Addr[i] & 0xFF,
> + PREFIX_ZERO,
> + 2
> + );
> + }
> +
> + //
> + // Terminate the string.
> + //
> + String[2 * AddrSize] = L'\0';
> +
> + return String;
> +}
> +
> +
> +
> +EFI_STATUS
> +TJudgeHandleIsPCIDevice(
> + EFI_HANDLE Handle,
> + UINT8 Device,
> + UINT8 Funs
> +)
> +{
> + EFI_STATUS Status;
> + EFI_DEVICE_PATH *DPath;
> + EFI_DEVICE_PATH *DevicePath;
> +
> + Status = gBS->HandleProtocol (
> + Handle,
> + &gEfiDevicePathProtocolGuid,
> + (VOID **) &DPath
> + );
> + if(!EFI_ERROR(Status))
> + {
> + DevicePath = DPath;
> + while(!IsDevicePathEnd(DPath))
> + {
> + if((DPath->Type == HARDWARE_DEVICE_PATH) && (DPath->SubType ==
> HW_PCI_DP))
> + {
> + PCI_DEVICE_PATH *PCIPath;
> +
> + PCIPath = (PCI_DEVICE_PATH*) DPath;
> + DPath = NextDevicePathNode(DPath);
> + if(IsDevicePathEnd(DPath) && (PCIPath->Device == Device) &&
> (PCIPath->Function == Funs))
> + {
> + return EFI_SUCCESS;
> + }
> + }
> + else
> + {
> + DPath = NextDevicePathNode(DPath);
> + }
> + }
> + }
> + return EFI_UNSUPPORTED;
> +}
> +
> +EFI_STATUS
> +TSearchChildHandle(
> + EFI_HANDLE Father,
> + EFI_HANDLE *Child
> + )
> +{
> + EFI_STATUS Status;
> + UINTN HandleIndex;
> + EFI_GUID **ProtocolGuidArray = NULL;
> + UINTN ArrayCount;
> + UINTN ProtocolIndex;
> + UINTN OpenInfoCount;
> + UINTN OpenInfoIndex;
> + EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfo = NULL;
> + UINTN mHandleCount;
> + EFI_HANDLE *mHandleBuffer= NULL;
> +
> + //
> + // Retrieve the list of all handles from the handle database
> + //
> + Status = gBS->LocateHandleBuffer (
> + AllHandles,
> + NULL,
> + NULL,
> + &mHandleCount,
> + &mHandleBuffer
> + );
> +
> + for (HandleIndex = 0; HandleIndex < mHandleCount; HandleIndex++)
> + {
> + //
> + // Retrieve the list of all the protocols on each handle
> + //
> + Status = gBS->ProtocolsPerHandle (
> + mHandleBuffer[HandleIndex],
> + &ProtocolGuidArray,
> + &ArrayCount
> + );
> + if (!EFI_ERROR (Status))
> + {
> + for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++)
> + {
> + Status = gBS->OpenProtocolInformation (
> + mHandleBuffer[HandleIndex],
> + ProtocolGuidArray[ProtocolIndex],
> + &OpenInfo,
> + &OpenInfoCount
> + );
> + if (!EFI_ERROR (Status))
> + {
> + for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount;
> OpenInfoIndex++)
> + {
> + if(OpenInfo[OpenInfoIndex].AgentHandle == Father)
> + {
> + if ((OpenInfo[OpenInfoIndex].Attributes &
> EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) ==
> EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER)
> + {
> + *Child = mHandleBuffer[HandleIndex];
> + Status = EFI_SUCCESS;
> + goto TryReturn;
> + }
> + }
> + }
> + Status = EFI_NOT_FOUND;
> + }
> + }
> + if(OpenInfo != NULL)
> + {
> + FreePool(OpenInfo);
> + OpenInfo = NULL;
> + }
> + }
> + FreePool (ProtocolGuidArray);
> + ProtocolGuidArray = NULL;
> + }
> +TryReturn:
> + if(OpenInfo != NULL)
> + {
> + FreePool (OpenInfo);
> + OpenInfo = NULL;
> + }
> + if(ProtocolGuidArray != NULL)
> + {
> + FreePool(ProtocolGuidArray);
> + ProtocolGuidArray = NULL;
> + }
> + if(mHandleBuffer != NULL)
> + {
> + FreePool (mHandleBuffer);
> + mHandleBuffer = NULL;
> + }
> + return Status;
> +}
> +
> +EFI_STATUS
> +TGetDriverName(
> + EFI_HANDLE Handle,
> + CHAR16 *Name
> +)
> +{
> + EFI_DRIVER_BINDING_PROTOCOL *BindHandle = NULL;
> + EFI_STATUS Status;
> + UINT32 Version;
> + UINT16 *Ptr;
> + Status = gBS->OpenProtocol(
> + Handle,
> + &gEfiDriverBindingProtocolGuid,
> + (VOID**)&BindHandle,
> + NULL,
> + NULL,
> + EFI_OPEN_PROTOCOL_GET_PROTOCOL
> + );
> +
> + if (EFI_ERROR(Status))
> + {
> + return EFI_NOT_FOUND;
> + }
> +
> + Version = BindHandle->Version;
> + Ptr = (UINT16*)&Version;
> + UnicodeSPrint(Name, 40, L"%d.%d.%d", Version >> 24 , (Version >>16)&
> 0x0f ,*(Ptr));
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +TGetGOPDriverName(
> + CHAR16 *Name
> +)
> +{
> + UINTN HandleCount;
> + EFI_HANDLE *Handles= NULL;
> + UINTN Index;
> + EFI_STATUS Status;
> + EFI_HANDLE Child = 0;
> +
> + Status = gBS->LocateHandleBuffer(
> + ByProtocol,
> + &gEfiDriverBindingProtocolGuid,
> + NULL,
> + &HandleCount,
> + &Handles
> + );
> + for (Index = 0; Index < HandleCount ; Index++)
> + {
> + Status = TSearchChildHandle(Handles[Index], &Child);
> + if(!EFI_ERROR(Status))
> + {
> + Status = TJudgeHandleIsPCIDevice(Child, 0x02, 0x00);
> + if(!EFI_ERROR(Status))
> + {
> + return TGetDriverName(Handles[Index], Name);
> + }
> + }
> + }
> + return EFI_UNSUPPORTED;
> +}
> +
> +EFI_STATUS
> +TGetTouchFirmwareVersion(
> + )
> +{
> + EFI_STATUS rc=EFI_SUCCESS;
> + UINTN TouchVer = 0;
> + UINTN Size = sizeof(UINTN);
> +
> +
> + CHAR16 Buffer[40];
> +
> + rc = gRT->GetVariable(
> + L"TouchVer",
> + &gEfiVlv2VariableGuid,
> + NULL,
> + &Size,
> + &TouchVer
> + );
> + if(!EFI_ERROR(rc)){
> + UnicodeSPrint(Buffer, sizeof(Buffer), L"%02x.%02x",
> (TouchVer&0xFFFF)>>8,TouchVer&0xFF);
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_TOUCH_VERSION),
> Buffer, NULL);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +UpdatePlatformInformation (
> + )
> +{
> + UINT32 MicroCodeVersion;
> + CHAR16 Buffer[40];
> + UINT8 IgdVBIOSRevH;
> + UINT8 IgdVBIOSRevL;
> + UINT16 EDX;
> + EFI_IA32_REGISTER_SET RegSet;
> + EFI_LEGACY_BIOS_PROTOCOL *LegacyBios = NULL;
> + EFI_STATUS Status;
> + UINT8 CpuFlavor=0;
> + EFI_PEI_HOB_POINTERS GuidHob;
> + EFI_PLATFORM_INFO_HOB *mPlatformInfo=NULL;
> + UINTN NumHandles;
> + EFI_HANDLE *HandleBuffer;
> + UINTN Index;
> + DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy;
> + UINTN PciD31F0RegBase;
> + UINT8 count;
> + UINT8 Data8;
> + UINT8 Data8_1;
> +
> + CHAR16 Name[40];
> + UINT32 MrcVersion;
> +
> + UINT8 KscFwRevH =0;
> + UINT8 KscFwRevL =0;
> +
> + //
> + // Get the HOB list. If it is not present, then ASSERT.
> + //
> + GuidHob.Raw = GetHobList ();
> + if (GuidHob.Raw != NULL) {
> + if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid,
> GuidHob.Raw)) != NULL) {
> + mPlatformInfo = GET_GUID_HOB_DATA (GuidHob.Guid);
> + }
> + }
> +
> + //
> + //VBIOS version
> + //
> + Status = gBS->LocateProtocol(
> + &gEfiLegacyBiosProtocolGuid,
> + NULL,
> + (VOID **)&LegacyBios
> + );
> +
> + RegSet.X.AX = 0x5f01;
> + Status = LegacyBios->Int86 (LegacyBios, 0x10, &RegSet);
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // simulate AMI int15 (ax=5f01) handler
> + // check NbInt15.asm in AMI code for asm edition
> + //
> + EDX = (UINT16)((RegSet.E.EBX >> 16) & 0xffff);
> + IgdVBIOSRevH = (UINT8)(((EDX & 0x0F00) >> 4) | (EDX & 0x000F));
> + IgdVBIOSRevL = (UINT8)(((RegSet.X.BX & 0x0F00) >> 4) | (RegSet.X.BX &
> 0x000F));
> +
> + if (IgdVBIOSRevH==0 && IgdVBIOSRevL==0) {
> + HiiSetString(mHiiHandle,
> STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_VALUE), L"N/A", NULL);
> + } else {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%02X%02X",
> IgdVBIOSRevH,IgdVBIOSRevL);
> + HiiSetString(mHiiHandle,
> STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_VALUE), Buffer, NULL);
> + }
> +
> + Status = TGetGOPDriverName(Name);
> +
> + if(!EFI_ERROR(Status))
> + {
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_GOP_VERSION),
> Name, NULL);
> + }
> +
> + //
> + //CpuFlavor
> + //
> + //VLV
> + //VLV-DC Tablet 000
> + //VLV-QC Notebook 001
> + //VLV-QC Desktop 010
> + //
> + //CPU flavor
> + //
> + CpuFlavor = RShiftU64 (EfiReadMsr (MSR_IA32_PLATFORM_ID), 50) & 0x07;
> +
> + switch(CpuFlavor){
> + case 0x0:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-DC Tablet",
> CpuFlavor);
> + break;
> + case 0x01:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC
> Notebook", CpuFlavor);
> + break;
> + case 0x02:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC
> Desktop", CpuFlavor);
> + break;
> + case 0x03:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC
> Notebook", CpuFlavor);
> + break;
> + default:
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"Unknown CPU",
> CpuFlavor);
> + break;
> + }
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_CPU_FLAVOR_VALUE),
> Buffer, NULL);
> +
> + if ( NULL != mPlatformInfo) {
> + //
> + // Board Id
> + //
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", mPlatformInfo->BoardId);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_BOARD_ID_VALUE),
> Buffer, NULL);
> +
> + //
> + // FAB ID
> + //
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", mPlatformInfo->BoardRev);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_FAB_ID_VALUE),
> Buffer, NULL);
> + }
> +
> + //
> + //Update MRC Version
> + //
> + MrcVersion = MmioRead32 (MmPciAddress (0, 0, 0, 0, 0xF0));
> + MrcVersion &= 0xffff;
> + Index = EfiValueToString (Buffer, MrcVersion/100, PREFIX_ZERO, 0);
> + StrCat (Buffer, L".");
> + EfiValueToString (Buffer + Index + 1, (MrcVersion%100)/10, PREFIX_ZERO,
> 0);
> + EfiValueToString (Buffer + Index + 2, (MrcVersion%100)%10, PREFIX_ZERO,
> 0);
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_MRC_VERSION_VALUE),
> Buffer, NULL);
> +
> + //
> + //Update Soc Version
> + //
> +
> + //
> + // Retrieve all instances of PCH Platform Policy protocol
> + //
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gDxePchPlatformPolicyProtocolGuid,
> + NULL,
> + &NumHandles,
> + &HandleBuffer
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Find the matching PCH Policy protocol
> + //
> + for (Index = 0; Index < NumHandles; Index++) {
> + Status = gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gDxePchPlatformPolicyProtocolGuid,
> + (VOID **) &PchPlatformPolicy
> + );
> + if (!EFI_ERROR (Status)) {
> + PciD31F0RegBase = MmPciAddress (
> + 0,
> + PchPlatformPolicy->BusNumber,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + 0
> + );
> +
> + Data8 = MmioRead8 (PciD31F0RegBase + R_PCH_LPC_RID_CC);
> + count = ARRAY_SIZE (SBRevisionTable);
> + for (Index = 0; Index < count; Index++) {
> + if(Data8 == SBRevisionTable[Index].RevId) {
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%02x %a", Data8,
> SBRevisionTable[Index].String);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SOC_VALUE),
> Buffer, NULL);
> + break;
> + }
> + }
> + break;
> + }
> + }
> + }
> +
> + //
> + // Microcode Revision
> + //
> + EfiWriteMsr (EFI_MSR_IA32_BIOS_SIGN_ID, 0);
> + EfiCpuid (EFI_CPUID_VERSION_INFO, NULL);
> + MicroCodeVersion = (UINT32) RShiftU64 (EfiReadMsr
> (EFI_MSR_IA32_BIOS_SIGN_ID), 32);
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", MicroCodeVersion);
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_PROCESSOR_MICROCO
> DE_VALUE), Buffer, NULL);
> +
> +
> + //
> + //Secure boot
> + //
> + Data8 = SystemConfiguration.SecureBoot;
> + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_SECURE_BOOT),
> Buffer, NULL);
> +
> + //
> + //Bootmode
> + //
> + BootMode = GetBootModeHob();
> + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", BootMode);
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_BOOT_MODE), Buffer,
> NULL);
> +
> + //
> + //SpeedStep
> + //
> + Data8 = 1;
> + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_SPEED_STEP), Buffer,
> NULL);
> +
> + //
> + //CPU Turbo
> + //
> + Data8 = 2;
> + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_CPU_TURBO), Buffer,
> NULL);
> +
> + //
> + //CState
> + //
> + Data8 = 3;
> + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_CSTATE), Buffer,
> NULL);
> +
> + //
> + //GFX Turbo
> + //
> + Data8 = SystemConfiguration.IgdTurboEnabled;
> + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_GFX_TURBO), Buffer,
> NULL);
> +
> + Data8 = 0;
> + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_S0IX_VALUE), Buffer,
> NULL);
> +
> + //
> + //RC6
> + //
> + Data8 = 0;
> + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_RC6_VALUE), Buffer,
> NULL);
> +
> + //
> + // Punit Version
> + //
> + Data8 = 0;
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"0x%x", Data8);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_PUNIT_FW_VALUE),
> Buffer, NULL);
> +
> + //
> + // PMC Version
> + //
> + Data8 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS +
> R_PCH_PMC_PRSTS)>>16)&0x00FF);
> + Data8_1 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS +
> R_PCH_PMC_PRSTS)>>24)&0x00FF);
> + UnicodeSPrint (Buffer, sizeof (Buffer), L"0x%X_%X", Data8_1, Data8);
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_PMC_FW_VALUE),
> Buffer, NULL);
> +
> + //
> + //PMIC Version
> + //
> + Status = ByteReadI2C(PMICI2cBus, PMICI2cAdd, PMICVendorOffset, 1,
> &Data8);
> + if(!EFI_ERROR(Status)){
> + Status = ByteReadI2C(PMICI2cBus, PMICI2cAdd, PMICRevOffset, 1,
> &Data8_1);
> + if(!EFI_ERROR(Status)){
> + UnicodeSPrint(Buffer, sizeof(Buffer), L"%02x.%02x", Data8, Data8_1);
> + HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_PMIC_VERSION),
> Buffer, NULL);
> + }
> + }
> +
> + TGetTouchFirmwareVersion();
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Smbios OEM type 0x94 callback.
> +
> + @param Event Event whose notification function is being invoked.
> + @param Context Pointer to the notification functions context, which is
> implementation dependent.
> +
> + @retval None
> +
> +**/
> +VOID
> +AddSmbiosT0x94Callback (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> + UINTN SECVerStrLen = 0;
> + UINTN uCodeVerStrLen = 0;
> + UINTN GOPStrLen = 0;
> + UINTN MRCVersionStrLen = 0;
> + UINTN PMCVersionStrLen = 0;
> + UINTN ULPMCVersionStrLen = 0;
> + UINTN PUNITVersionStrLen = 0;
> + UINTN SOCVersionStrLen = 0;
> + UINTN BOARDVersionStrLen = 0;
> + UINTN FABVersionStrLen = 0;
> + UINTN CPUFLAVORStrLen = 0;
> + UINTN BIOSVersionStrLen = 0;
> + UINTN PMICVersionStrLen = 0;
> + UINTN TOUCHVersionStrLen = 0;
> + UINTN SecureBootModeLen = 0;
> + UINTN BootModeLen = 0;
> + UINTN SpeedStepModeLen = 0;
> + UINTN MaxCStateLen = 0;
> + UINTN CpuTurboLen = 0;
> + UINTN GfxTurboLen = 0;
> + UINTN IdleReserveLen = 0;
> + UINTN RC6Len = 0;
> +
> + SMBIOS_TABLE_TYPE94 *SmbiosRecord;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + EFI_MISC_OEM_TYPE_0x94 *ForType94InputData;
> + CHAR16 *SECVer;
> + CHAR16 *uCodeVer;
> + CHAR16 *GOPVer;
> + CHAR16 *MrcVer;
> + CHAR16 *PmcVer;
> + CHAR16 *UlpmcVer;
> + CHAR16 *PunitVer;
> + CHAR16 *SocVer;
> + CHAR16 *BoardVer;
> + CHAR16 *FabVer;
> + CHAR16 *CpuFlavor;
> + CHAR16 *BiosVer;
> + CHAR16 *PmicVer;
> + CHAR16 *TouchVer = L"15.16";
> + CHAR16 *SecureBootMode;
> + CHAR16 *BootMode;
> + CHAR16 *SpeedStepMode;
> + CHAR16 *MaxCState;
> + CHAR16 *CpuTurbo;
> + CHAR16 *GfxTurbo;
> + CHAR16 *IdleReserve;
> + CHAR16 *RC6;
> +
> + UINTN RecordLen = 0;
> + UINTN StrIdx = 0;
> +
> +
> + STRING_REF TokenToGet;
> + CHAR8 *OptionalStrStart;
> + EFI_SMBIOS_PROTOCOL *SmbiosProtocol;
> +
> + ForType94InputData = (EFI_MISC_OEM_TYPE_0x94 *)Context;
> +
> + DEBUG ((EFI_D_INFO, "Executing SMBIOS T0x94 callback.\n"));
> +
> + gBS->CloseEvent (Event); // Unload this event.
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (Context == NULL) {
> + return;
> + }
> +
> + UpdatePlatformInformation();
> +
> + Status = gBS->LocateProtocol (
> + &gEfiSmbiosProtocolGuid,
> + NULL,
> + (VOID **) &SmbiosProtocol
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_SEC_VERSION);
> + SECVer = SmbiosMiscGetString (TokenToGet);
> + SECVerStrLen = StrLen(SECVer);
> + if (SECVerStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_UCODE_VERSION);
> + uCodeVer = SmbiosMiscGetString (TokenToGet);
> + uCodeVerStrLen = StrLen(uCodeVer);
> + if (uCodeVerStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_GOP_VERSION);
> + GOPVer = SmbiosMiscGetString (TokenToGet);
> + GOPStrLen = StrLen(GOPVer);
> + if (GOPStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_MRC_VERSION_VALUE);
> + MrcVer = SmbiosMiscGetString (TokenToGet);
> + MRCVersionStrLen = StrLen(MrcVer);
> + if (MRCVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_PMC_FW_VALUE);
> + PmcVer = SmbiosMiscGetString (TokenToGet);
> + PMCVersionStrLen = StrLen(PmcVer);
> + if (PMCVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_ULPMC_FW_VALUE);
> + UlpmcVer = SmbiosMiscGetString (TokenToGet);
> + ULPMCVersionStrLen = StrLen(UlpmcVer);
> + if (ULPMCVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_PUNIT_FW_VALUE);
> + PunitVer = SmbiosMiscGetString (TokenToGet);
> + PUNITVersionStrLen = StrLen(PunitVer);
> + if (PUNITVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_SOC_VALUE);
> + SocVer = SmbiosMiscGetString (TokenToGet);
> + SOCVersionStrLen = StrLen(SocVer);
> + if (SOCVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_BOARD_ID_VALUE);
> + BoardVer = SmbiosMiscGetString (TokenToGet);
> + BOARDVersionStrLen = StrLen(BoardVer);
> + if (BOARDVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_FAB_ID_VALUE);
> + FabVer = SmbiosMiscGetString (TokenToGet);
> + FABVersionStrLen = StrLen(FabVer);
> + if (FABVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_CPU_FLAVOR_VALUE);
> + CpuFlavor = SmbiosMiscGetString (TokenToGet);
> + CPUFLAVORStrLen = StrLen(CpuFlavor);
> + if (CPUFLAVORStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION);
> + BiosVer = SmbiosMiscGetString (TokenToGet);
> + BIOSVersionStrLen = StrLen(BiosVer);
> + if (BIOSVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_PMIC_VERSION);
> + PmicVer = SmbiosMiscGetString (TokenToGet);
> + PMICVersionStrLen = StrLen(PmicVer);
> + if (PMICVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_TOUCH_VERSION);
> + TouchVer = SmbiosMiscGetString (TokenToGet);
> + TOUCHVersionStrLen = StrLen(TouchVer);
> + if (TOUCHVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_SECURE_BOOT);
> + SecureBootMode = SmbiosMiscGetString(TokenToGet);
> + SecureBootModeLen = StrLen(SecureBootMode);
> + if (SecureBootModeLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_BOOT_MODE);
> + BootMode = SmbiosMiscGetString(TokenToGet);
> + BootModeLen = StrLen(BootMode);
> + if (BootModeLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_SPEED_STEP);
> + SpeedStepMode = SmbiosMiscGetString(TokenToGet);
> + SpeedStepModeLen = StrLen(SpeedStepMode);
> + if (SpeedStepModeLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_CPU_TURBO);
> + CpuTurbo = SmbiosMiscGetString(TokenToGet);
> + CpuTurboLen = StrLen(CpuTurbo);
> + if (CpuTurboLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_CSTATE);
> + MaxCState = SmbiosMiscGetString(TokenToGet);
> + MaxCStateLen = StrLen(MaxCState);
> + if (MaxCStateLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_GFX_TURBO);
> + GfxTurbo = SmbiosMiscGetString(TokenToGet);
> + GfxTurboLen = StrLen(GfxTurbo);
> + if (GfxTurboLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_S0IX_VALUE);
> + IdleReserve = SmbiosMiscGetString(TokenToGet);
> + IdleReserveLen = StrLen(IdleReserve);
> + if (S0ixLen > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_RC6_VALUE);
> + RC6 = SmbiosMiscGetString(TokenToGet);
> + RC6Len = StrLen(RC6);
> + if (RC6Len > SMBIOS_STRING_MAX_LENGTH) {
> + return;
> + }
> +
> + RecordLen = sizeof (SMBIOS_TABLE_TYPE94) + SECVerStrLen + 1 +
> uCodeVerStrLen + 1 + GOPStrLen + 1 + PMCVersionStrLen + 1 + \
> + TOUCHVersionStrLen + 1 + PMICVersionStrLen + 1 +
> BIOSVersionStrLen + 1 + CPUFLAVORStrLen + 1 + \
> + BOARDVersionStrLen + 1 + FABVersionStrLen + 1 +
> PUNITVersionStrLen+ 1 + ULPMCVersionStrLen + 1 + \
> + MRCVersionStrLen + 1 + SOCVersionStrLen + 1 +
> SecureBootModeLen + 1 + BootModeLen + 1 + \
> + SpeedStepModeLen + 1 + CpuTurboLen + 1 + MaxCStateLen + 1
> + GfxTurboLen + 1 + + RC6Len + 1 + 1;
> +
> + SmbiosRecord = AllocatePool(RecordLen);
> +
> + ZeroMem(SmbiosRecord, RecordLen);
> +
> + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_MISC_VERSION_INFO;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE94);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + SmbiosRecord->GopVersion = 1;
> +
> + SmbiosRecord->SECVersion = 2;
> +
> + SmbiosRecord->MRCVersion = 3;
> +
> + SmbiosRecord->uCodeVersion = 4;
> +
> + SmbiosRecord->PUnitVersion = 5;
> +
> + SmbiosRecord->PMCVersion = 6;
> +
> + SmbiosRecord->ULPMCVersion = 7;
> +
> + SmbiosRecord->SoCVersion = 8;
> +
> + SmbiosRecord->BoardVersion = 9;
> +
> + SmbiosRecord->FabVersion = 10;
> +
> + SmbiosRecord->CPUFlavor = 11;
> +
> + SmbiosRecord->BiosVersion = 12;
> +
> + SmbiosRecord->PmicVersion = 13;
> +
> + SmbiosRecord->TouchVersion = 14;
> +
> + SmbiosRecord->SecureBoot = 15;
> +
> + SmbiosRecord->BootMode = 16;
> +
> + SmbiosRecord->SpeedStepMode= 17;
> +
> + SmbiosRecord->CPUTurboMode = 18;
> +
> + SmbiosRecord->MaxCState = 19;
> +
> + SmbiosRecord->GfxTurbo = 20;
> + SmbiosRecord->IdleReserve = 21;
> +
> + SmbiosRecord->RC6 = 22;
> +
> +
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(GOPVer, OptionalStrStart);
> + StrIdx += GOPStrLen + 1;
> +
> + UnicodeStrToAsciiStr(SECVer, OptionalStrStart + StrIdx);
> + StrIdx += SECVerStrLen + 1;
> +
> + UnicodeStrToAsciiStr(MrcVer, OptionalStrStart + StrIdx);
> + StrIdx += MRCVersionStrLen + 1;
> +
> + UnicodeStrToAsciiStr(uCodeVer, OptionalStrStart + StrIdx);
> + StrIdx += uCodeVerStrLen + 1;
> +
> + UnicodeStrToAsciiStr(PunitVer, OptionalStrStart + StrIdx);
> + StrIdx += PUNITVersionStrLen + 1;
> +
> + UnicodeStrToAsciiStr(PmcVer, OptionalStrStart + StrIdx);
> + StrIdx += PMCVersionStrLen + 1;
> +
> + UnicodeStrToAsciiStr(UlpmcVer, OptionalStrStart + StrIdx);
> + StrIdx += ULPMCVersionStrLen + 1;
> +
> +
> + UnicodeStrToAsciiStr(SocVer, OptionalStrStart + StrIdx);
> + StrIdx += SOCVersionStrLen +1;
> +
> + UnicodeStrToAsciiStr(BoardVer, OptionalStrStart + StrIdx);
> + StrIdx += BOARDVersionStrLen + 1;
> +
> + UnicodeStrToAsciiStr(FabVer, OptionalStrStart + StrIdx);
> + StrIdx += FABVersionStrLen + 1;
> +
> + UnicodeStrToAsciiStr(CpuFlavor, OptionalStrStart + StrIdx);
> + StrIdx += CPUFLAVORStrLen + 1;
> +
> + UnicodeStrToAsciiStr(BiosVer, OptionalStrStart + StrIdx);
> + StrIdx += BIOSVersionStrLen + 1;
> +
> + UnicodeStrToAsciiStr(PmicVer, OptionalStrStart + StrIdx);
> + StrIdx += PMICVersionStrLen + 1;
> +
> + UnicodeStrToAsciiStr(TouchVer, OptionalStrStart + StrIdx);
> + StrIdx += TOUCHVersionStrLen + 1;
> +
> + UnicodeStrToAsciiStr(SecureBootMode, OptionalStrStart + StrIdx);
> + StrIdx += SecureBootModeLen + 1;
> +
> + UnicodeStrToAsciiStr(BootMode, OptionalStrStart + StrIdx);
> + StrIdx += BootModeLen + 1;
> +
> + UnicodeStrToAsciiStr(SpeedStepMode, OptionalStrStart + StrIdx);
> + StrIdx += SpeedStepModeLen + 1;
> +
> + UnicodeStrToAsciiStr(CpuTurbo, OptionalStrStart + StrIdx);
> + StrIdx += CpuTurboLen + 1;
> +
> + UnicodeStrToAsciiStr(MaxCState, OptionalStrStart + StrIdx);
> + StrIdx += MaxCStateLen + 1;
> +
> + UnicodeStrToAsciiStr(GfxTurbo, OptionalStrStart + StrIdx);
> + StrIdx += GfxTurboLen + 1;
> +
> + UnicodeStrToAsciiStr(IdleReserve, OptionalStrStart + StrIdx);
> + StrIdx += S0ixLen + 1;
> +
> + UnicodeStrToAsciiStr(RC6, OptionalStrStart + StrIdx);
> + StrIdx += RC6Len + 1;
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = SmbiosProtocol-> Add (
> + SmbiosProtocol,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> +
> + FreePool(SmbiosRecord);
> + return;
> +}
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscOemType0x94 (Type 0x94).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION(MiscOemType0x94)
> +{
> + EFI_STATUS Status;
> + EFI_EVENT AddSmbiosT0x94CallbackEvent;
> +
> + Status = EfiCreateEventReadyToBootEx (
> + TPL_CALLBACK,
> + AddSmbiosT0x94Callback,
> + RecordData,
> + &AddSmbiosT0x94CallbackEvent
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> + return Status;
> +
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDevice.un
> i
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDevice.un
> i
> new file mode 100644
> index 0000000000..85c60a06fe
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDevice.un
> i
> @@ -0,0 +1,26 @@
> +// *++
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscOnboardDevice.uni
> +//
> +// Abstract:
> +//
> +// Onboard device information
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +
> +#string STR_MISC_ONBOARD_DEVICE_VIDEO #language en-US "Intel(R)
> ValleyView2 HD Graphics"
> +#string STR_MISC_ONBOARD_DEVICE_AUDIO #language en-US "Intel(R)
> HD Audio Device"
> +#string STR_MISC_ONBOARD_DEVICE_NETWORK #language en-US ""
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceDat
> a.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceDa
> ta.c
> new file mode 100644
> index 0000000000..f82cfa8985
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceDa
> ta.c
> @@ -0,0 +1,48 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscOnboardDeviceData.c
> +
> +Abstract:
> +
> + Static data of Onboard device information .
> + The onboard device information is Misc. subclass type 8 and SMBIOS type
> 10.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) Bios Vendor data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_ONBOARD_DEVICE_DATA,
> MiscOnboardDeviceVideo) = {
> + STRING_TOKEN(STR_MISC_ONBOARD_DEVICE_VIDEO), //
> OnBoardDeviceDescription
> + { // OnBoardDeviceStatus
> + EfiOnBoardDeviceTypeVideo, // DeviceType
> + 1, // DeviceEnabled
> + 0 // Reserved
> + },
> + 0 // OnBoardDevicePath
> +};
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_ONBOARD_DEVICE_DATA,
> MiscOnboardDeviceAudio) = {
> + STRING_TOKEN(STR_MISC_ONBOARD_DEVICE_AUDIO), //
> OnBoardDeviceDescription
> + { // OnBoardDeviceStatus
> + EfiOnBoardDeviceTypeSound, // DeviceType
> + 1, // DeviceEnabled
> + 0 // Reserved
> + },
> + 0 // OnBoardDevicePath
> +};
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceFu
> nction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceFu
> nction.c
> new file mode 100644
> index 0000000000..aef25065b8
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceFu
> nction.c
> @@ -0,0 +1,135 @@
> +/** @file
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscOnboardDeviceFunction.c
> +
> +Abstract:
> +
> + Create the device path for the Onboard device.
> + The Onboard device information is Misc. subclass type 8 and SMBIOS type
> 10.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +
> +
> +/**
> + This is a macro defined function, in fact, the function is
> + MiscOnboardDeviceFunction (RecordType, RecordLen, RecordData,
> LogRecordData)
> + This function makes boot time changes to the contents of the
> + MiscOnboardDevice structure.
> +
> + @param MiscOnboardDevice The string which is used to create the
> function
> + The Arguments in fact:
> + @param RecordType Type of record to be processed from the Data
> + Table. mMiscSubclassDataTable[].RecordType
> + @param RecordLen Size of static RecordData from the Data Table.
> + mMiscSubclassDataTable[].RecordLen
> + @param RecordData Pointer to RecordData, which will be written to
> + the Data Hub
> + @param LogRecordData TRUE to log RecordData to Data Hub. FALSE
> when
> + there is no more data to log.
> +
> + @retval EFI_SUCCESS *RecordData and *LogRecordData have been
> set.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER One of the following parameter
> conditions was
> + true: RecordLen was zero. RecordData was NULL.
> + LogRecordData was NULL.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION (
> + MiscOnboardDevice
> + )
> +{
> + CHAR8 *OptionalStrStart;
> + UINT8 StatusAndType;
> + UINTN DescriptionStrLen;
> + EFI_STRING DeviceDescription;
> + STRING_REF TokenToGet;
> + EFI_STATUS Status;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE10 *SmbiosRecord;
> + EFI_MISC_ONBOARD_DEVICE *ForType10InputData;
> +
> + ForType10InputData = (EFI_MISC_ONBOARD_DEVICE *)RecordData;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + TokenToGet = 0;
> + switch (ForType10InputData->OnBoardDeviceDescription) {
> + case STR_MISC_ONBOARD_DEVICE_VIDEO:
> + TokenToGet = STRING_TOKEN (STR_MISC_ONBOARD_DEVICE_VIDEO);
> + break;
> + case STR_MISC_ONBOARD_DEVICE_AUDIO:
> + TokenToGet = STRING_TOKEN (STR_MISC_ONBOARD_DEVICE_AUDIO);
> + break;
> + default:
> + break;
> + }
> +
> + DeviceDescription = SmbiosMiscGetString (TokenToGet);
> + DescriptionStrLen = StrLen(DeviceDescription);
> + if (DescriptionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE10) +
> DescriptionStrLen + 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE10) +
> DescriptionStrLen + 1 + 1);
> +
> + SmbiosRecord->Hdr.Type =
> EFI_SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE10);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + //
> + // Status & Type: Bit 7 Devicen Status, Bits 6:0 Type of Device
> + //
> + StatusAndType = (UINT8) ForType10InputData-
> >OnBoardDeviceStatus.DeviceType;
> + if (ForType10InputData->OnBoardDeviceStatus.DeviceEnabled != 0) {
> + StatusAndType |= 0x80;
> + } else {
> + StatusAndType &= 0x7F;
> + }
> +
> + SmbiosRecord->Device[0].DeviceType = StatusAndType;
> + SmbiosRecord->Device[0].DescriptionString = 1;
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(DeviceDescription, OptionalStrStart);
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArray.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArray.uni
> new file mode 100644
> index 0000000000..bed00e0de5
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArray.uni
> @@ -0,0 +1,25 @@
> +// *++
> +//
> +// Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscPhysicalArray.uni
> +//
> +// Abstract:
> +//
> +// BIOS Physical Memory
> +// SMBIOS type 16.
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +#langdef en-US "English"
> +
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayData.
> c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayData.
> c
> new file mode 100644
> index 0000000000..66370f7eea
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayData.
> c
> @@ -0,0 +1,38 @@
> +/*++
> +
> +Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscPhysicalArrayData.c
> +
> +Abstract:
> +
> + BIOS Physical Array static data.
> + SMBIOS type 16.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +
> +
> +//
> +// Static (possibly build generated) Physical Memory Array Dat.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MEMORY_ARRAY_LOCATION_DATA,
> MiscPhysicalMemoryArray) =
> +{
> + EfiMemoryArrayLocationSystemBoard,
> // Memory location
> + EfiMemoryArrayUseSystemMemory,
> // Memory array use
> + EfiMemoryErrorCorrectionNone,
> // Memory error correction
> + 0, // Maximum Memory Capacity
> + 0x01 //
> Number of Devices
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayFunct
> ion.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayFunct
> ion.c
> new file mode 100644
> index 0000000000..67fc04152c
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayFunct
> ion.c
> @@ -0,0 +1,101 @@
> +/*++
> +
> +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscPhysicalArrayFunction.c
> +
> +Abstract:
> +
> + BIOS system Physical Array boot time changes.
> + SMBIOS type 16.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +#include "MiscSubclassDriver.h"
> +
> +
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscPhysicalArrayFunction (Type 16).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +
> +MISC_SMBIOS_TABLE_FUNCTION(MiscPhysicalMemoryArray)
> +{
> + EFI_STATUS Status;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE16 *SmbiosRecord;
> + EFI_MEMORY_ARRAY_LOCATION_DATA *ForType16InputData;
> + UINT32 TopOfMemory = 8 * 1024 * 1024;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + ForType16InputData = (EFI_MEMORY_ARRAY_LOCATION_DATA
> *)RecordData;
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE16) + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE16) + 1);
> +
> + SmbiosRecord->Hdr.Type =
> EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE16);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + //
> + // ReleaseDate will be the 3rd optional string following the formatted
> structure.
> + //
> + SmbiosRecord->Location = *(UINT8 *) &ForType16InputData -
> >MemoryArrayLocation;
> + SmbiosRecord->Use = *(UINT8 *) &ForType16InputData -
> >MemoryArrayUse;
> + SmbiosRecord->MemoryErrorCorrection = *(UINT8 *)
> &ForType16InputData->MemoryErrorCorrection;
> +
> + //
> + // System does not provide the error information structure
> + //
> + SmbiosRecord->MemoryErrorInformationHandle = 0xFFFE;
> +
> + //
> + // Maximum memory capacity
> + //
> + SmbiosRecord-> MaximumCapacity = TopOfMemory;
> + SmbiosRecord-> NumberOfMemoryDevices= 0x02;
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + FreePool(SmbiosRecord);
> + return Status;
> +
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConne
> ctorDesignator.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConne
> ctorDesignator.uni
> new file mode 100644
> index 0000000000..80fa99ecbe
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConne
> ctorDesignator.uni
> @@ -0,0 +1,31 @@
> +// *++
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscPortInternalConnectorDesignator.uni
> +//
> +// Abstract:
> +//
> +// Port internal connector information
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +
> +#string STR_MISC_PORT_INTERNAL_IDE1 #language en-US "J4J1"
> +#string STR_MISC_PORT_EXTERNAL_IDE1 #language en-US
> "SATA_CON1"
> +#string STR_MISC_PORT_INTERNAL_IDE2 #language en-US "J4E3"
> +#string STR_MISC_PORT_EXTERNAL_IDE2 #language en-US
> "SATA_CON2"
> +#string STR_MISC_PORT_INTERNAL_ATX_POWER #language en-US "J3J1"
> +#string STR_MISC_PORT_EXTERNAL_ATX_POWER #language en-US
> "ATX_PWR"
> +#string STR_MISC_PORT_INTERNAL_BTX_POWER #language en-US
> "BTX_PWR"
> +#string STR_MISC_PORT_EXTERNAL_BTX_POWER #language en-US ""
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConne
> ctorDesignatorData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConne
> ctorDesignatorData.c
> new file mode 100644
> index 0000000000..b98bab40ab
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConne
> ctorDesignatorData.c
> @@ -0,0 +1,56 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscPortInternalConnectorDesignatorData.c
> +
> +Abstract:
> +
> + Static data of Port internal connector designator information.
> + Port internal connector designator information is Misc. subclass type 6 and
> + SMBIOS type 8.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) Port connector designations
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DE
> SIGNATOR_DATA, MiscPortIde1) = {
> + STRING_TOKEN(STR_MISC_PORT_INTERNAL_IDE1),
> + STRING_TOKEN(STR_MISC_PORT_EXTERNAL_IDE1),
> + EfiPortConnectorTypeOnboardIde,
> + EfiPortConnectorTypeNone,
> + EfiPortTypeOther,
> + 0
> +};
> +
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DE
> SIGNATOR_DATA, MiscPortIde2) = {
> + STRING_TOKEN(STR_MISC_PORT_INTERNAL_IDE2),
> + STRING_TOKEN(STR_MISC_PORT_EXTERNAL_IDE2),
> + EfiPortConnectorTypeOnboardIde,
> + EfiPortConnectorTypeNone,
> + EfiPortTypeOther,
> + 0
> +};
> +
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DE
> SIGNATOR_DATA, MiscPortAtxPower) = {
> + STRING_TOKEN(STR_MISC_PORT_INTERNAL_ATX_POWER),
> + STRING_TOKEN(STR_MISC_PORT_EXTERNAL_ATX_POWER),
> + EfiPortConnectorTypeOther,
> + EfiPortConnectorTypeNone,
> + EfiPortTypeOther,
> + 0
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConne
> ctorDesignatorFunction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConne
> ctorDesignatorFunction.c
> new file mode 100644
> index 0000000000..6bc088cd13
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConne
> ctorDesignatorFunction.c
> @@ -0,0 +1,152 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscPortInternalConnectorDesignatorFunction.c
> +
> +Abstract:
> +
> + Create the device path for the Port internal connector designator.
> + Port internal connector designator information is Misc. subclass type 6
> + and SMBIOS type 8.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +
> +/**
> + This is a macro defined function, in fact, the function is
> + MiscPortInternalConnectorDesignatorFunction (RecordType, RecordLen,
> RecordData, LogRecordData)
> + This function makes boot time changes to the contents of the
> + MiscPortConnectorInformation.
> +
> + @param MiscPortInternalConnectorDesignator The string which is used to
> create
> + the function
> + The Arguments in fact:
> + @param RecordType Type of record to be processed from
> + the Data Table.
> + mMiscSubclassDataTable[].RecordType
> + @param RecordLen Size of static RecordData from the
> + Data Table.
> + mMiscSubclassDataTable[].RecordLen
> + @param RecordData Pointer to RecordData, which will be
> + written to the Data Hub
> + @param LogRecordData TRUE to log RecordData to Data Hub.
> + FALSE when there is no more data to
> + log.
> +
> + @retval EFI_SUCCESS *RecordData and *LogRecordData have
> + been set.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER One of the following parameter
> + conditions was true: RecordLen was
> + zero. RecordData was NULL.
> + LogRecordData was NULL.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION (
> + MiscPortInternalConnectorDesignator
> + )
> +{
> + CHAR8 *OptionalStrStart;
> + UINTN InternalRefStrLen;
> + UINTN ExternalRefStrLen;
> + EFI_STRING InternalRef;
> + EFI_STRING ExternalRef;
> + STRING_REF TokenForInternal;
> + STRING_REF TokenForExternal;
> + EFI_STATUS Status;
> + SMBIOS_TABLE_TYPE8 *SmbiosRecord;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR
> *ForType8InputData;
> +
> + ForType8InputData =
> (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR *)RecordData;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + TokenForInternal = 0;
> + TokenForExternal = 0;
> +
> + switch (ForType8InputData->PortInternalConnectorDesignator) {
> +
> + case STR_MISC_PORT_INTERNAL_IDE1:
> + TokenForInternal = STRING_TOKEN (STR_MISC_PORT_INTERNAL_IDE1);
> + TokenForExternal = STRING_TOKEN(STR_MISC_PORT_EXTERNAL_IDE1);
> + break;
> + case STR_MISC_PORT_INTERNAL_IDE2:
> + TokenForInternal = STRING_TOKEN (STR_MISC_PORT_INTERNAL_IDE2);
> + TokenForExternal = STRING_TOKEN(STR_MISC_PORT_EXTERNAL_IDE2);
> + break;
> + case STR_MISC_PORT_INTERNAL_ATX_POWER:
> + TokenForInternal = STRING_TOKEN
> (STR_MISC_PORT_INTERNAL_ATX_POWER);
> + TokenForExternal =
> STRING_TOKEN(STR_MISC_PORT_EXTERNAL_ATX_POWER);
> + break;
> + default:
> + break;
> + }
> +
> + InternalRef = SmbiosMiscGetString (TokenForInternal);
> + InternalRefStrLen = StrLen(InternalRef);
> + if (InternalRefStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + ExternalRef = SmbiosMiscGetString (TokenForExternal);
> + ExternalRefStrLen = StrLen(ExternalRef);
> + if (ExternalRefStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE8) +
> InternalRefStrLen + 1 + ExternalRefStrLen + 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE8) +
> InternalRefStrLen + 1 + ExternalRefStrLen + 1 + 1);
> +
> + SmbiosRecord->Hdr.Type =
> EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE8);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> + SmbiosRecord->InternalReferenceDesignator = 1;
> + SmbiosRecord->InternalConnectorType = (UINT8)ForType8InputData-
> >PortInternalConnectorType;
> + SmbiosRecord->ExternalReferenceDesignator = 2;
> + SmbiosRecord->ExternalConnectorType = (UINT8)ForType8InputData-
> >PortExternalConnectorType;
> + SmbiosRecord->PortType = (UINT8)ForType8InputData->PortType;
> +
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(InternalRef, OptionalStrStart);
> + UnicodeStrToAsciiStr(ExternalRef, OptionalStrStart + InternalRefStrLen + 1);
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCache.u
> ni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCache.u
> ni
> new file mode 100644
> index 0000000000..fee69bb139
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCache.u
> ni
> @@ -0,0 +1,22 @@
> +// *++
> +//
> +// Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscProcessorCache.uni
> +//
> +// Abstract:
> +//
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +#langdef en-US "English"
> +
> +#string STR_SOCKET_DESIGNATION #language en-US "0x01"
> \ No newline at end of file
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheDa
> ta.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheDa
> ta.c
> new file mode 100644
> index 0000000000..6af7f56107
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheDa
> ta.c
> @@ -0,0 +1,33 @@
> +/*++
> +
> +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscBiosProcessorCache.c
> +
> +Abstract:
> +
> + Processor cache static data.
> + Misc. subclass type 7.
> + SMBIOS type 7.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +
> +//
> +// Static (possibly build generated) Processor cache data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_CACHE_VARIABLE_RECORD,
> MiscProcessorCache) = {
> +0
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheFu
> nction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheFu
> nction.c
> new file mode 100644
> index 0000000000..ca121525a0
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheFu
> nction.c
> @@ -0,0 +1,189 @@
> +/*++
> +
> +Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscProcessorCacheFunction.c
> +
> +Abstract:
> +
> + BIOS processor cache details.
> + Misc. subclass type 7.
> + SMBIOS type 7.
> +
> +--*/
> +#include "CommonHeader.h"
> +#include "MiscSubclassDriver.h"
> +#include <Protocol/DataHub.h>
> +#include <Guid/DataHubRecords.h>
> +
> +UINT32
> +ConvertBase2ToRaw (
> + IN EFI_EXP_BASE2_DATA *Data)
> +{
> + UINTN Index;
> + UINT32 RawData;
> +
> + RawData = Data->Value;
> + for (Index = 0; Index < (UINTN) Data->Exponent; Index++) {
> + RawData <<= 1;
> + }
> +
> + return RawData;
> +}
> +
> +
> +MISC_SMBIOS_TABLE_FUNCTION(MiscProcessorCache)
> +{
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE7 *SmbiosRecordL1;
> + SMBIOS_TABLE_TYPE7 *SmbiosRecordL2;
> +
> + EFI_CACHE_SRAM_TYPE_DATA CacheSramType;
> + CHAR16 *SocketDesignation;
> + CHAR8 *OptionalStrStart;
> + UINTN SocketStrLen;
> + STRING_REF TokenToGet;
> + EFI_DATA_HUB_PROTOCOL *DataHub;
> + UINT64 MonotonicCount;
> + EFI_DATA_RECORD_HEADER *Record;
> + EFI_SUBCLASS_TYPE1_HEADER *DataHeader;
> + UINT8 *SrcData;
> + EFI_STATUS Status;
> +
> + //
> + // Memory Device LOcator
> + //
> + DEBUG ((EFI_D_ERROR, "type 7\n"));
> +
> + TokenToGet = STRING_TOKEN (STR_SOCKET_DESIGNATION);
> + SocketDesignation = SmbiosMiscGetString (TokenToGet);
> + SocketStrLen = StrLen(SocketDesignation);
> + if (SocketStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + SmbiosRecordL1 = AllocatePool(sizeof (SMBIOS_TABLE_TYPE7) + 7 +
> 1 + 1);
> + ASSERT (SmbiosRecordL1 != NULL);
> + ZeroMem(SmbiosRecordL1, sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 +
> 1);
> +
> + SmbiosRecordL2 = AllocatePool(sizeof (SMBIOS_TABLE_TYPE7) + 7 +
> 1 + 1);
> + ASSERT (SmbiosRecordL2 != NULL);
> + ZeroMem(SmbiosRecordL2, sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 +
> 1);
> +
> + //
> + // Get the Data Hub Protocol. Assume only one instance
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiDataHubProtocolGuid,
> + NULL,
> + (VOID **)&DataHub
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + MonotonicCount = 0;
> + Record = NULL;
> +
> + do {
> + Status = DataHub->GetNextRecord (
> + DataHub,
> + &MonotonicCount,
> + NULL,
> + &Record
> + );
> + if (!EFI_ERROR(Status)) {
> + if (Record->DataRecordClass ==
> EFI_DATA_RECORD_CLASS_DATA) {
> + DataHeader =
> (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);
> + SrcData = (UINT8 *)(DataHeader + 1);
> + if (CompareGuid(&Record->DataRecordGuid,
> &gEfiCacheSubClassGuid) && (DataHeader->RecordType ==
> CacheSizeRecordType)) {
> + if (DataHeader->SubInstance == EFI_CACHE_L1) {
> + SmbiosRecordL1-
> >InstalledSize += (UINT16) (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA
> *)SrcData) >> 10);
> + SmbiosRecordL1-
> >MaximumCacheSize = SmbiosRecordL1->InstalledSize;
> + }
> + else if (DataHeader->SubInstance == EFI_CACHE_L2)
> {
> + SmbiosRecordL2-
> >InstalledSize += (UINT16) (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA
> *)SrcData) >> 10);
> + SmbiosRecordL2-
> >MaximumCacheSize = SmbiosRecordL2->InstalledSize;
> + } else {
> + continue;
> + }
> + }
> + }
> + }
> + } while (!EFI_ERROR(Status) && (MonotonicCount != 0));
> +
> + //
> + //Filling SMBIOS type 7 information for different cache levels.
> + //
> +
> + SmbiosRecordL1->Hdr.Type =
> EFI_SMBIOS_TYPE_CACHE_INFORMATION;
> + SmbiosRecordL1->Hdr.Length = (UINT8) sizeof
> (SMBIOS_TABLE_TYPE7);
> + SmbiosRecordL1->Hdr.Handle = 0;
> +
> + SmbiosRecordL1->Associativity = CacheAssociativity8Way;
> + SmbiosRecordL1->SystemCacheType = CacheTypeUnknown;
> + SmbiosRecordL1->SocketDesignation = 0x01;
> + SmbiosRecordL1->CacheSpeed = 0;
> + SmbiosRecordL1->CacheConfiguration = 0x0180;
> + ZeroMem (&CacheSramType, sizeof
> (EFI_CACHE_SRAM_TYPE_DATA));
> + CacheSramType.Synchronous = 1;
> + CopyMem(&SmbiosRecordL1->SupportedSRAMType,
> &CacheSramType, 2);
> + CopyMem(&SmbiosRecordL1->CurrentSRAMType, &CacheSramType,
> 2);
> + SmbiosRecordL1->ErrorCorrectionType = EfiCacheErrorSingleBit;
> +
> +
> + SmbiosRecordL2->Hdr.Type =
> EFI_SMBIOS_TYPE_CACHE_INFORMATION;
> + SmbiosRecordL2->Hdr.Length = (UINT8) sizeof
> (SMBIOS_TABLE_TYPE7);
> + SmbiosRecordL2->Hdr.Handle = 0;
> +
> + SmbiosRecordL2->Associativity = CacheAssociativity16Way;
> + SmbiosRecordL2->SystemCacheType = CacheTypeInstruction;
> + SmbiosRecordL2->SocketDesignation = 0x01;
> + SmbiosRecordL2->CacheSpeed = 0;
> + SmbiosRecordL2->CacheConfiguration = 0x0281;
> + ZeroMem (&CacheSramType, sizeof
> (EFI_CACHE_SRAM_TYPE_DATA));
> + CacheSramType.Synchronous = 1;
> + CopyMem(&SmbiosRecordL2->SupportedSRAMType,
> &CacheSramType, 2);
> + CopyMem(&SmbiosRecordL2->CurrentSRAMType, &CacheSramType,
> 2);
> + SmbiosRecordL2->ErrorCorrectionType = EfiCacheErrorSingleBit;
> +
> +
> +
> + //
> + //Adding SMBIOS type 7 records to SMBIOS table.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + OptionalStrStart = (CHAR8 *)(SmbiosRecordL1 + 1);
> + UnicodeStrToAsciiStr(SocketDesignation, OptionalStrStart);
> +
> + Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecordL1
> + );
> +
> + //
> + //VLV2 incorporates two SLM modules (quad cores) in the SoC. 2
> cores share BIU/L2 cache
> + //
> + SmbiosRecordL2->InstalledSize = (SmbiosRecordL2->InstalledSize)/2;
> + SmbiosRecordL2->MaximumCacheSize = SmbiosRecordL2-
> >InstalledSize;
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> +
> + OptionalStrStart = (CHAR8 *)(SmbiosRecordL2 + 1);
> + UnicodeStrToAsciiStr(SocketDesignation, OptionalStrStart);
> +
> + Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecordL2
> + );
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformat
> ion.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformat
> ion.uni
> new file mode 100644
> index 0000000000..2e6c79009b
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformat
> ion.uni
> @@ -0,0 +1,27 @@
> +// *++
> +//
> +// Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscProcessorInformation.uni
> +//
> +// Abstract:
> +//
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +#langdef en-US "English"
> +
> +#string STR_MISC_SOCKET_NAME #language en-US "VLV"
> +#string STR_MISC_PROCESSOR_MAUFACTURER #language en-US "Intel"
> +#string STR_MISC_PROCESSOR_VERSION #language en-US "Baytrail
> A0"
> +#string STR_MISC_PROCESSOR_SERIAL_NUMBER #language en-US " "
> +#string STR_MISC_ASSERT_TAG_DATA #language en-US " "
> +#string STR_MISC_PART_NUMBER #language en-US " "
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformat
> ionData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformat
> ionData.c
> new file mode 100644
> index 0000000000..846e9ec838
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformat
> ionData.c
> @@ -0,0 +1,71 @@
> +/*++
> +
> +Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscOnboardDeviceData.c
> +
> +Abstract:
> +
> + This driver parses the mMiscSubclassDataTable structure and reports
> + any generated data to smbios.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +
> +/*
> + EFI_PROCESSOR_CORE_FREQUENCY_LIST_DATA
> ProcessorCoreFrequencyList;
> + EFI_PROCESSOR_FSB_FREQUENCY_LIST_DATA
> ProcessorFsbFrequencyList;
> + EFI_PROCESSOR_SERIAL_NUMBER_DATA ProcessorSerialNumber;
> + EFI_PROCESSOR_CORE_FREQUENCY_DATA ProcessorCoreFrequency;
> + EFI_PROCESSOR_FSB_FREQUENCY_DATA ProcessorFsbFrequency;
> + EFI_PROCESSOR_MAX_CORE_FREQUENCY_DATA
> ProcessorMaxCoreFrequency;
> + EFI_PROCESSOR_MAX_FSB_FREQUENCY_DATA
> ProcessorMaxFsbFrequency;
> + EFI_PROCESSOR_VERSION_DATA ProcessorVersion;
> + EFI_PROCESSOR_MANUFACTURER_DATA ProcessorManufacturer;
> + EFI_PROCESSOR_ID_DATA ProcessorId;
> + EFI_PROCESSOR_TYPE_DATA ProcessorType;
> + EFI_PROCESSOR_FAMILY_DATA ProcessorFamily;
> + EFI_PROCESSOR_VOLTAGE_DATA ProcessorVoltage;
> + EFI_PROCESSOR_APIC_BASE_ADDRESS_DATA ProcessorApicBase;
> + EFI_PROCESSOR_APIC_ID_DATA ProcessorApicId;
> + EFI_PROCESSOR_APIC_VERSION_NUMBER_DATA
> ProcessorApicVersionNumber;
> + EFI_PROCESSOR_MICROCODE_REVISION_DATA CpuUcodeRevisionData;
> + EFI_PROCESSOR_STATUS_DATA ProcessorStatus;
> + EFI_PROCESSOR_SOCKET_TYPE_DATA ProcessorSocketType;
> + EFI_PROCESSOR_SOCKET_NAME_DATA ProcessorSocketName;
> + EFI_PROCESSOR_ASSET_TAG_DATA ProcessorAssetTag;
> + EFI_PROCESSOR_HEALTH_STATUS ProcessorHealthStatus;
> + EFI_PROCESSOR_PACKAGE_NUMBER_DATA ProcessorPackageNumber;
> +} EFI_CPU_VARIABLE_RECORD;
> +*/
> +
> +
> +// Static (possibly build generated) Bios Vendor data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_CPU_DATA_RECORD,
> MiscProcessorInformation) = {
> +
> +0,
> + /*
> + STRING_TOKEN (STR_MISC_SOCKET_NAME), //
> Processor Socket Name
> + STRING_TOKEN (STR_MISC_PROCESSOR_MAUFACTURER), //
> Processor Manufacturer
> + STRING_TOKEN (STR_MISC_PROCESSOR_VERSION), //
> Processor Version Information
> + STRING_TOKEN (STR_MISC_PROCESSOR_SERIAL_NUMBER), //
> Serial Number
> + STRING_TOKEN (STR_MISC_ASSERT_TAG_DATA), //
> Processor Assert TAg Data
> + STRING_TOKEN (STR_MISC_PART_NUMBER) //
> Processor Part Numbe
> +*/
> +};
> +
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformat
> ionFunction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformat
> ionFunction.c
> new file mode 100644
> index 0000000000..e01693ede7
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformat
> ionFunction.c
> @@ -0,0 +1,448 @@
> +/*++
> +
> +Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscProcessorInformationFunction.c
> +
> +Abstract:
> +
> + Onboard processor information boot time changes.
> + SMBIOS type 4.
> +
> +--*/
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +#include <Protocol/MpService.h>
> +#include <Protocol/DataHub.h>
> +#include <Guid/DataHubRecords.h>
> +#include <Library/CpuIA32.h>
> +
> +#define EfiProcessorFamilyIntelAtomProcessor 0x2B
> +
> +EFI_GUID mProcessorProducerGuid;
> +
> +
> +/**
> + Get cache SMBIOS record handle.
> +
> + @param Smbios Pointer to SMBIOS protocol instance.
> + @param CacheLevel Level of cache, starting from one.
> + @param Handle Returned record handle.
> +
> +**/
> +
> +VOID
> +GetCacheHandle (
> + IN EFI_SMBIOS_PROTOCOL *Smbios,
> + IN UINT8 CacheLevel,
> + OUT EFI_SMBIOS_HANDLE *Handle
> + )
> +{
> + UINT16 CacheConfig;
> + EFI_STATUS Status;
> + EFI_SMBIOS_TYPE RecordType;
> + EFI_SMBIOS_TABLE_HEADER *Buffer;
> +
> + *Handle = 0;
> + RecordType = EFI_SMBIOS_TYPE_CACHE_INFORMATION;
> +
> + do {
> + Status = Smbios->GetNext (
> + Smbios,
> + Handle,
> + &RecordType,
> + &Buffer,
> + NULL
> + );
> + if (!EFI_ERROR(Status)) {
> + CacheConfig = *(UINT16*)((UINT8*)Buffer + 5);
> + if ((CacheConfig & 0x7) == (CacheLevel -1) ) {
> + return;
> + }
> + }
> + } while (!EFI_ERROR(Status));
> +
> + *Handle = 0xFFFF;
> +}
> +
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscProcessorInformation (Type 4).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +UINT32
> +ConvertBase10ToRaw (
> + IN EFI_EXP_BASE10_DATA *Data)
> +{
> + UINTN Index;
> + UINT32 RawData;
> +
> + RawData = Data->Value;
> + for (Index = 0; Index < (UINTN) Data->Exponent; Index++) {
> + RawData *= 10;
> + }
> +
> + return RawData;
> +}
> +
> +#define BSEL_CR_OVERCLOCK_CONTROL 0xCD
> +#define FUSE_BSEL_MASK 0x03
> +
> +
> +
> +UINT16 miFSBFrequencyTable[4] = {
> + 83, // 83.3MHz
> + 100, // 100MHz
> + 133, // 133MHz
> + 117 // 116.7MHz
> +};
> +
> +/**
> + Determine the processor core frequency
> +
> + @param None
> +
> + @retval Processor core frequency multiplied by 3
> +
> +
> +**/
> +UINT16
> +DetermineiFsbFromMsr (
> + VOID
> + )
> +{
> + //
> + // Determine the processor core frequency
> + //
> + UINT64 Temp;
> + Temp = (EfiReadMsr (BSEL_CR_OVERCLOCK_CONTROL)) &
> FUSE_BSEL_MASK;
> + return miFSBFrequencyTable[(UINT32)(Temp)];
> +
> +}
> +
> +MISC_SMBIOS_TABLE_FUNCTION (MiscProcessorInformation)
> +{
> + CHAR8 *OptionalStrStart;
> + EFI_STRING SerialNumber;
> + CHAR16 *Version=NULL;
> + CHAR16 *Manufacturer=NULL;
> + CHAR16 *Socket=NULL;
> + CHAR16 *AssetTag=NULL;
> + CHAR16 *PartNumber=NULL;
> + UINTN SerialNumberStrLen=0;
> + UINTN VersionStrLen=0;
> + UINTN ManufacturerStrLen=0;
> + UINTN SocketStrLen=0;
> + UINTN AssetTagStrLen=0;
> + UINTN PartNumberStrLen=0;
> + UINTN ProcessorVoltage=0xAE;
> + UINT32 Eax01;
> + UINT32 Ebx01;
> + UINT32 Ecx01;
> + UINT32 Edx01;
> + STRING_REF TokenToGet;
> + EFI_STATUS Status;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE4 *SmbiosRecord;
> + EFI_CPU_DATA_RECORD *ForType4InputData;
> + UINT16 L1CacheHandle=0;
> + UINT16 L2CacheHandle=0;
> + UINT16 L3CacheHandle=0;
> + UINTN NumberOfEnabledProcessors=0 ;
> + UINTN NumberOfProcessors=0;
> + UINT64 Frequency = 0;
> + EFI_MP_SERVICES_PROTOCOL *MpService;
> + EFI_DATA_HUB_PROTOCOL *DataHub;
> + UINT64 MonotonicCount;
> + EFI_DATA_RECORD_HEADER *Record;
> + EFI_SUBCLASS_TYPE1_HEADER *DataHeader;
> + UINT8 *SrcData;
> + EFI_PROCESSOR_VERSION_DATA *ProcessorVersion;
> + CHAR16 *NewStringToken;
> + STRING_REF TokenToUpdate;
> + PROCESSOR_ID_DATA *ProcessorId = NULL;
> +
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + ForType4InputData = (EFI_CPU_DATA_RECORD *)RecordData;
> +
> + ProcessorId = AllocateZeroPool(sizeof(PROCESSOR_ID_DATA));
> + if (ProcessorId == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Get the Data Hub Protocol. Assume only one instance
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiDataHubProtocolGuid,
> + NULL,
> + (VOID **)&DataHub
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + MonotonicCount = 0;
> + Record = NULL;
> +
> + do {
> + Status = DataHub->GetNextRecord (
> + DataHub,
> + &MonotonicCount,
> + NULL,
> + &Record
> + );
> + if (!EFI_ERROR(Status)) {
> + if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {
> +
> + DataHeader = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);
> + SrcData = (UINT8 *)(DataHeader + 1);
> +
> + //
> + // Processor
> + //
> + if (CompareGuid(&Record->DataRecordGuid,
> &gEfiProcessorSubClassGuid)) {
> + CopyMem (&mProcessorProducerGuid, &Record->ProducerName,
> sizeof(EFI_GUID));
> + switch (DataHeader->RecordType) {
> + case ProcessorVoltageRecordType:
> + ProcessorVoltage = (((EFI_EXP_BASE10_DATA *)SrcData)-
> >Value)/100 + 0x80;
> + break;
> + case ProcessorCoreFrequencyRecordType:
> + DEBUG ((EFI_D_ERROR, "ProcessorCoreFrequencyRecordType
> SrcData1 =%d\n", ConvertBase10ToRaw((EFI_EXP_BASE10_DATA
> *)SrcData)/1000000));
> + Frequency = (ConvertBase10ToRaw((EFI_EXP_BASE10_DATA
> *)SrcData)/1000000);
> + break;
> + case ProcessorVersionRecordType:
> + ProcessorVersion = (EFI_PROCESSOR_VERSION_DATA *)SrcData;
> + NewStringToken =
> HiiGetPackageString(&mProcessorProducerGuid, *ProcessorVersion, NULL);
> + TokenToUpdate = (STRING_REF)STR_MISC_PROCESSOR_VERSION;
> + HiiSetString(mHiiHandle, TokenToUpdate, NewStringToken, NULL);
> + break;
> + default:
> + break;
> + }
> + }
> + }
> + }
> + } while (!EFI_ERROR(Status) && (MonotonicCount != 0));
> +
> + //
> + // Token to get for Socket Name
> + //
> + TokenToGet = STRING_TOKEN (STR_MISC_SOCKET_NAME);
> + Socket = SmbiosMiscGetString (TokenToGet);
> + SocketStrLen = StrLen(Socket);
> + if (SocketStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Token to get for Processor Manufacturer
> + //
> + TokenToGet = STRING_TOKEN (STR_MISC_PROCESSOR_MAUFACTURER);
> + Manufacturer = SmbiosMiscGetString (TokenToGet);
> + ManufacturerStrLen = StrLen(Manufacturer);
> + if (ManufacturerStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Token to get for Processor Version
> + //
> + TokenToGet = STRING_TOKEN (STR_MISC_PROCESSOR_VERSION);
> + Version = SmbiosMiscGetString (TokenToGet);
> + VersionStrLen = StrLen(Version);
> + if (VersionStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Token to get for Serial Number
> + //
> + TokenToGet = STRING_TOKEN
> (STR_MISC_PROCESSOR_SERIAL_NUMBER);
> + SerialNumber = SmbiosMiscGetString (TokenToGet);
> + SerialNumberStrLen = StrLen(SerialNumber);
> + if (SerialNumberStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Token to get for Assert Tag Information
> + //
> + TokenToGet = STRING_TOKEN (STR_MISC_ASSERT_TAG_DATA);
> + AssetTag = SmbiosMiscGetString (TokenToGet);
> + AssetTagStrLen = StrLen(AssetTag);
> + if (AssetTagStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Token to get for part number Information
> + //
> + TokenToGet = STRING_TOKEN (STR_MISC_PART_NUMBER);
> + PartNumber = SmbiosMiscGetString (TokenToGet);
> + PartNumberStrLen = StrLen(PartNumber);
> + if (PartNumberStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE4) +
> AssetTagStrLen + 1 + SocketStrLen + 1+ ManufacturerStrLen +1 +
> VersionStrLen+ 1+ SerialNumberStrLen + 1 + PartNumberStrLen+ 1 + 1);
> +
> + SmbiosRecord->Hdr.Type =
> EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE4);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + SmbiosRecord-> Socket= 1;
> + SmbiosRecord -> ProcessorManufacture = 2;
> + SmbiosRecord -> ProcessorVersion = 3;
> + SmbiosRecord ->SerialNumber =4;
> +
> + SmbiosRecord-> AssetTag= 5;
> + SmbiosRecord-> PartNumber= 6;
> +
> + //
> + // Processor Type
> + //
> + ForType4InputData-> VariableRecord.ProcessorType=
> EfiCentralProcessor;
> + SmbiosRecord -> ProcessorType = ForType4InputData->
> VariableRecord.ProcessorType;
> +
> + //
> + // Processor Family
> + //
> + ForType4InputData-> VariableRecord.ProcessorFamily=
> EfiProcessorFamilyIntelAtomProcessor; //0x2B;;
> + SmbiosRecord -> ProcessorFamily = ForType4InputData->
> VariableRecord.ProcessorFamily;
> + SmbiosRecord -> ExternalClock = DetermineiFsbFromMsr();
> +
> + //
> + // Processor ID
> + //
> + AsmCpuid(0x001, &Eax01, &Ebx01, &Ecx01, &Edx01);
> + ProcessorId->Signature = *(PROCESSOR_SIGNATURE *)&Eax01;
> + ProcessorId->FeatureFlags = *(PROCESSOR_FEATURE_FLAGS *)&Edx01;
> + SmbiosRecord -> ProcessorId = *(PROCESSOR_ID_DATA *)ProcessorId;
> +
> + //
> + // Processor Voltage
> + //
> + ForType4InputData-> VariableRecord.ProcessorVoltage=
> *(EFI_PROCESSOR_VOLTAGE_DATA *)&ProcessorVoltage;
> + SmbiosRecord -> Voltage = *(PROCESSOR_VOLTAGE *)
> &(ForType4InputData-> VariableRecord.ProcessorVoltage);
> +
> + //
> + // Status
> + //
> + ForType4InputData-> VariableRecord.ProcessorHealthStatus=
> 0x41;//0x41;
> + SmbiosRecord -> Status = ForType4InputData->
> VariableRecord.ProcessorHealthStatus;
> +
> + //
> + // Processor Upgrade
> + //
> + SmbiosRecord -> ProcessorUpgrade = 0x008;
> +
> + //
> + // Processor Family 2
> + //
> + SmbiosRecord -> ProcessorFamily2 = ForType4InputData->
> VariableRecord.ProcessorFamily;
> +
> + //
> + // Processor speed
> + //
> + SmbiosRecord-> CurrentSpeed = *(UINT16*) & Frequency;
> + SmbiosRecord-> MaxSpeed = *(UINT16*) & Frequency;
> +
> + //
> + // Processor Characteristics
> + //
> + AsmCpuid(0x8000000, NULL, NULL, NULL, &Edx01);
> + Edx01= Edx01 >> 28;
> + Edx01 &= 0x01;
> + SmbiosRecord-> ProcessorCharacteristics= (UINT16)Edx01;
> +
> + //
> + // Processor Core Count and Enabled core count
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiMpServiceProtocolGuid,
> + NULL,
> + (void **)&MpService
> + );
> + if (!EFI_ERROR (Status)) {
> + //
> + // Determine the number of processors
> + //
> + MpService->GetNumberOfProcessors (
> + MpService,
> + &NumberOfProcessors,
> + &NumberOfEnabledProcessors
> + );
> + }
> + SmbiosRecord-> CoreCount= (UINT8)NumberOfProcessors;
> + SmbiosRecord-> EnabledCoreCount=
> (UINT8)NumberOfEnabledProcessors;
> + SmbiosRecord-> ThreadCount= (UINT8)NumberOfEnabledProcessors;
> + SmbiosRecord-> ProcessorCharacteristics = 0x2; // Unknown
> +
> + //
> + // Processor Cache Handle
> + //
> + GetCacheHandle( Smbios,1, &L1CacheHandle);
> + GetCacheHandle( Smbios,2, &L2CacheHandle);
> + GetCacheHandle( Smbios,3, &L3CacheHandle);
> +
> + //
> + // Updating Cache Handle Information
> + //
> + SmbiosRecord->L1CacheHandle = L1CacheHandle;
> + SmbiosRecord->L2CacheHandle = L2CacheHandle;
> + SmbiosRecord->L3CacheHandle = L3CacheHandle;
> +
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(Socket, OptionalStrStart);
> + UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart + SocketStrLen + 1);
> + UnicodeStrToAsciiStr(Version, OptionalStrStart + SocketStrLen + 1 +
> ManufacturerStrLen+ 1);
> + UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + SocketStrLen + 1 +
> VersionStrLen + 1 + ManufacturerStrLen + 1);
> + UnicodeStrToAsciiStr(AssetTag, OptionalStrStart + SerialNumberStrLen + 1
> + VersionStrLen + 1 + ManufacturerStrLen + 1 + SocketStrLen + 1);
> + UnicodeStrToAsciiStr(PartNumber, OptionalStrStart + SerialNumberStrLen
> + 1 + VersionStrLen + 1 + ManufacturerStrLen + 1 + SocketStrLen + 1 +
> AssetTagStrLen + 1 );
> +
> + //
> + // Now we have got the full Smbios record, call Smbios protocol to add
> this record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + if (EFI_ERROR (Status)) return Status;
> + FreePool(SmbiosRecord);
> + return Status;
> +
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesD
> ata.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesD
> ata.c
> new file mode 100644
> index 0000000000..e3b847f7ce
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesD
> ata.c
> @@ -0,0 +1,43 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscResetCapabilitiesData.c
> +
> +Abstract:
> +
> + Static data of Reset Capabilities information.
> + Reset Capabilities information is Misc. subclass type 17 and SMBIOS type 23.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) Bios Vendor data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_RESET_CAPABILITIES,
> MiscResetCapabilities)
> += {
> + { // ResetCapabilities
> + 0, // Status
> + 0, // BootOption
> + 0, // BootOptionOnLimit
> + 0, // WatchdogTimerPresent
> + 0 // Reserved
> + },
> + 0xFFFF, // ResetCount
> + 0xFFFF, // ResetLimit
> + 0xFFFF, // ResetTimerInterval
> + 0xFFFF // ResetTimeout
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesF
> unction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesF
> unction.c
> new file mode 100644
> index 0000000000..67a549a6ba
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesF
> unction.c
> @@ -0,0 +1,85 @@
> +/*++
> +
> +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + MiscResetCapabilitiesFunction.c
> +
> +Abstract:
> +
> + ResetCapabilities.
> + SMBIOS type 23.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscOemString (Type 11).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION(MiscResetCapabilities)
> +{
> + EFI_STATUS Status;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE23 *SmbiosRecord;
> + EFI_MISC_RESET_CAPABILITIES *ForType23InputData;
> +
> + ForType23InputData = (EFI_MISC_RESET_CAPABILITIES *)RecordData;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE23) + 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE23) + 1 + 1);
> +
> + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_RESET;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE23);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> + SmbiosRecord->Capabilities = *(UINT8*)&(ForType23InputData-
> >ResetCapabilities);
> + SmbiosRecord->ResetCount = (UINT16)ForType23InputData-
> >ResetCount;
> + SmbiosRecord->ResetLimit = (UINT16)ForType23InputData->ResetLimit;
> + SmbiosRecord->TimerInterval = (UINT16)ForType23InputData-
> >ResetTimerInterval;
> + SmbiosRecord->Timeout = (UINT16)ForType23InputData-
> >ResetTimeout;
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.h
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.h
> new file mode 100644
> index 0000000000..67ea100fad
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.h
> @@ -0,0 +1,188 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscSubclassDriver.h
> +
> +Abstract:
> +
> + Header file for MiscSubclass Driver.
> +
> +
> +**/
> +
> +#ifndef _MISC_SUBCLASS_DRIVER_H
> +#define _MISC_SUBCLASS_DRIVER_H
> +
> +
> +#include "CommonHeader.h"
> +
> +extern UINT8 MiscSubclassStrings[];
> +
> +
> +#define T14_FVI_STRING "Driver/firmware version"
> +#define EFI_SMBIOS_TYPE_FIRMWARE_VERSION_INFO 0x90
> +#define EFI_SMBIOS_TYPE_MISC_VERSION_INFO 0x94
> +#define TOUCH_ACPI_ID "I2C05\\SFFFF\\400K"
> +#define TOUCH_RESET_GPIO_MMIO 0xFED0C508
> +#define EFI_SMBIOS_TYPE_SEC_INFO 0x83
> +#define IntelIdentifer 0x6F725076
> +
> +//
> +// Data table entry update function.
> +//
> +typedef EFI_STATUS (EFIAPI EFI_MISC_SMBIOS_DATA_FUNCTION) (
> + IN VOID *RecordData,
> + IN EFI_SMBIOS_PROTOCOL *Smbios
> + );
> +
> +//
> +// Data table entry definition.
> +//
> +typedef struct {
> + //
> + // intermediat input data for SMBIOS record
> + //
> + VOID *RecordData;
> + EFI_MISC_SMBIOS_DATA_FUNCTION *Function;
> +} EFI_MISC_SMBIOS_DATA_TABLE;
> +
> +//
> +// Data Table extern definitions.
> +//
> +#define MISC_SMBIOS_TABLE_EXTERNS(NAME1, NAME2, NAME3) \
> +extern NAME1 NAME2 ## Data; \
> +extern EFI_MISC_SMBIOS_DATA_FUNCTION NAME3 ## Function
> +
> +
> +//
> +// Data Table entries
> +//
> +#define MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(NAME1,
> NAME2) \
> +{ \
> + & NAME1 ## Data, \
> + & NAME2 ## Function \
> +}
> +
> +//
> +// Global definition macros.
> +//
> +#define MISC_SMBIOS_TABLE_DATA(NAME1, NAME2) \
> + NAME1 NAME2 ## Data
> +
> +#define MISC_SMBIOS_TABLE_FUNCTION(NAME2) \
> + EFI_STATUS EFIAPI NAME2 ## Function( \
> + IN VOID *RecordData, \
> + IN EFI_SMBIOS_PROTOCOL *Smbios \
> + )
> +
> +#pragma pack(1)
> +
> +//
> +// This is definition for SMBIOS Oem data type 0x90
> +//
> +typedef struct {
> + STRING_REF SECVersion;
> + STRING_REF uCodeVersion;
> + STRING_REF GOPVersion;
> + STRING_REF CpuStepping;
> +} EFI_MISC_OEM_TYPE_0x90;
> +
> +//
> +// This is definition for SMBIOS Oem data type 0x90
> +//
> +typedef struct {
> + SMBIOS_STRUCTURE Hdr;
> + SMBIOS_TABLE_STRING SECVersion;
> + SMBIOS_TABLE_STRING uCodeVersion;
> + SMBIOS_TABLE_STRING GOPVersion;
> + SMBIOS_TABLE_STRING CpuStepping;
> +} SMBIOS_TABLE_TYPE90;
> +
> +typedef struct {
> + STRING_REF GopVersion;
> + STRING_REF UCodeVersion;
> + STRING_REF MRCVersion;
> + STRING_REF SECVersion;
> + STRING_REF ULPMCVersion;
> + STRING_REF PMCVersion;
> + STRING_REF PUnitVersion;
> + STRING_REF SoCVersion;
> + STRING_REF BoardVersion;
> + STRING_REF FabVersion;
> + STRING_REF CPUFlavor;
> + STRING_REF BiosVersion;
> + STRING_REF PmicVersion;
> + STRING_REF TouchVersion;
> + STRING_REF SecureBoot;
> + STRING_REF BootMode;
> + STRING_REF SpeedStepMode;
> + STRING_REF CPUTurboMode;
> + STRING_REF MaxCState;
> + STRING_REF GfxTurbo;
> + STRING_REF IdleReserve;
> + STRING_REF RC6;
> +}EFI_MISC_OEM_TYPE_0x94;
> +
> +typedef struct {
> + SMBIOS_STRUCTURE Hdr;
> + SMBIOS_TABLE_STRING GopVersion;
> + SMBIOS_TABLE_STRING uCodeVersion;
> + SMBIOS_TABLE_STRING MRCVersion;
> + SMBIOS_TABLE_STRING SECVersion;
> + SMBIOS_TABLE_STRING ULPMCVersion;
> + SMBIOS_TABLE_STRING PMCVersion;
> + SMBIOS_TABLE_STRING PUnitVersion;
> + SMBIOS_TABLE_STRING SoCVersion;
> + SMBIOS_TABLE_STRING BoardVersion;
> + SMBIOS_TABLE_STRING FabVersion;
> + SMBIOS_TABLE_STRING CPUFlavor;
> + SMBIOS_TABLE_STRING BiosVersion;
> + SMBIOS_TABLE_STRING PmicVersion;
> + SMBIOS_TABLE_STRING TouchVersion;
> + SMBIOS_TABLE_STRING SecureBoot;
> + SMBIOS_TABLE_STRING BootMode;
> + SMBIOS_TABLE_STRING SpeedStepMode;
> + SMBIOS_TABLE_STRING CPUTurboMode;
> + SMBIOS_TABLE_STRING MaxCState;
> + SMBIOS_TABLE_STRING GfxTurbo;
> + SMBIOS_TABLE_STRING IdleReserve;
> + SMBIOS_TABLE_STRING RC6;
> +}SMBIOS_TABLE_TYPE94;
> +
> +#pragma pack()
> +//
> +// Data Table Array
> +//
> +extern EFI_MISC_SMBIOS_DATA_TABLE mMiscSubclassDataTable[];
> +
> +//
> +// Data Table Array Entries
> +//
> +extern UINTN mMiscSubclassDataTableEntries;
> +extern EFI_HII_HANDLE mHiiHandle;
> +
> +//
> +// Prototypes
> +//
> +EFI_STATUS
> +EFIAPI
> +MiscSubclassDriverEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + );
> +
> +EFI_STRING
> +EFIAPI
> +SmbiosMiscGetString (
> + IN EFI_STRING_ID StringId
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.uni
> new file mode 100644
> index 0000000000..3a6ccf1d75
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.uni
> @@ -0,0 +1,35 @@
> +// *++
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscSubclassDriver.uni
> +//
> +// Abstract:
> +//
> +// Misc Subclass information.
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +/=#
> +
> +#langdef en-US "English"
> +
> +#string STR_MISC_SUBCLASS_DRIVER_TITLE #language en-US "Not used"
> +
> +#include "MiscBaseBoardManufacturer.uni"
> +#include "MiscBiosVendor.uni"
> +#include "MiscChassisManufacturer.uni"
> +#include "MiscOemString.uni"
> +#include "MiscOnboardDevice.uni"
> +#include "MiscPortInternalConnectorDesignator.uni"
> +#include "MiscSystemLanguageString.uni"
> +#include "MiscSystemManufacturer.uni"
> +#include "MiscSystemOptionString.uni"
> +#include "MiscSystemSlotDesignation.uni"
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverData
> Table.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverDat
> aTable.c
> new file mode 100644
> index 0000000000..93347a1a04
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverDat
> aTable.c
> @@ -0,0 +1,98 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscSubclassDriverDataTable.c
> +
> +Abstract:
> +
> + Create the mMiscSubclassDataTable structure, and it is used to report
> + any generate data to the DataHub.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// External definitions referenced by Data Table entries.
> +//
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BIOS_VENDOR_DATA,
> MiscBiosVendor, MiscBiosVendor);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_MANUFACTURER_DAT
> A, MiscSystemManufacturer, MiscSystemManufacturer);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BASE_BOARD_MANUFACTURE
> R_DATA, MiscBaseBoardManufacturer, MiscBaseBoardManufacturer);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_CHASSIS_MANUFACTURER_DA
> TA, MiscChassisManufacturer, MiscChassisManufacturer);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_CACHE_VARIABLE_RECORD,
> MiscProcessorCache, MiscProcessorCache); //type 7
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_CPU_DATA_RECORD,
> MiscProcessorInformation, MiscProcessorInformation); //type 4
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MEMORY_ARRAY_LOCATION_DATA,
> MiscPhysicalMemoryArray,MiscPhysicalMemoryArray);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MEMORY_ARRAY_LINK_DATA,
> MiscMemoryDevice, MiscMemoryDevice);
> +
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR
> _DESIGNATOR_DATA, MiscPortIde1, MiscPortInternalConnectorDesignator);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR
> _DESIGNATOR_DATA, MiscPortIde2, MiscPortInternalConnectorDesignator);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR
> _DESIGNATOR_DATA, MiscPortAtxPower,
> MiscPortInternalConnectorDesignator);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_
> DATA, MiscSystemSlotPCIEx16Slot1, MiscSystemSlotDesignation);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_
> DATA, MiscSystemSlotPCIEx16Slot2, MiscSystemSlotDesignation);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_
> DATA, MiscSystemSlotPCIEx4, MiscSystemSlotDesignation);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_
> DATA, MiscSystemSlotPCIEx1Slot1, MiscSystemSlotDesignation);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_
> DATA, MiscSystemSlotPCIEx1Slot2, MiscSystemSlotDesignation);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_
> DATA, MiscSystemSlotPCIEx1Slot3, MiscSystemSlotDesignation);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_
> DATA, MiscSystemSlotPCI1, MiscSystemSlotDesignation);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_
> DATA, MiscSystemSlotPCI2, MiscSystemSlotDesignation);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_
> DATA, MiscSystemSlotPCI3, MiscSystemSlotDesignation);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_ONBOARD_DEVICE_DATA,
> MiscOnboardDeviceVideo, MiscOnboardDevice);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_ONBOARD_DEVICE_DATA,
> MiscOnboardDeviceNetwork, MiscOnboardDevice);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_ONBOARD_DEVICE_DATA,
> MiscOnboardDeviceAudio, MiscOnboardDevice);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_NUMBER_OF_INSTALLABLE_LA
> NGUAGES_DATA, NumberOfInstallableLanguages,
> NumberOfInstallableLanguages);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_LANGUAGE_STRING_
> DATA, SystemLanguageString, SystemLanguageString);
> +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BOOT_INFORMATION_STATUS
> _DATA, BootInformationStatus, BootInformationStatus);
> +
> +//
> +// Data Table.
> +//
> +EFI_MISC_SMBIOS_DATA_TABLE mMiscSubclassDataTable[] = {
> + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBiosVendor,
> MiscBiosVendor),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemManufact
> urer, MiscSystemManufacturer),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBaseBoardManu
> facturer, MiscBaseBoardManufacturer),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscChassisManufact
> urer, MiscChassisManufacturer),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscProcessorCache,
> MiscProcessorCache), //type 7
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscProcessorInform
> ation, MiscProcessorInformation), //type 4
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPhysicalMemory
> Array, MiscPhysicalMemoryArray), //Type 16
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscMemoryDevice,
> MiscMemoryDevice), //Type 17
> + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortIde1,
> MiscPortInternalConnectorDesignator),
> + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortIde2,
> MiscPortInternalConnectorDesignator),
> + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortAtxPower,
> MiscPortInternalConnectorDesignator),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx
> 16Slot1, MiscSystemSlotDesignation),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx
> 16Slot2, MiscSystemSlotDesignation),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx
> 4, MiscSystemSlotDesignation),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx
> 1Slot1, MiscSystemSlotDesignation),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx
> 1Slot2, MiscSystemSlotDesignation),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx
> 1Slot3, MiscSystemSlotDesignation),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCI1,
> MiscSystemSlotDesignation),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCI2,
> MiscSystemSlotDesignation),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCI3,
> MiscSystemSlotDesignation),
> +#if defined( ALWAYS_DISABLE_ONBOARD_VIDEO ) && \
> + ( ALWAYS_DISABLE_ONBOARD_VIDEO != 0 )
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnboardDevice
> Network, MiscOnboardDevice),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnboardDeviceA
> udio, MiscOnboardDevice),
> +#else
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnboardDeviceV
> ideo, MiscOnboardDevice),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnboardDeviceA
> udio, MiscOnboardDevice),
> +#endif
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(SystemLanguageStrin
> g, SystemLanguageString),
> +
> MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(BootInformationStat
> us, BootInformationStatus),
> +};
> +
> +//
> +// Number of Data Table entries.
> +//
> +UINTN mMiscSubclassDataTableEntries =
> + (sizeof mMiscSubclassDataTable) /
> sizeof(EFI_MISC_SMBIOS_DATA_TABLE);
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverEntr
> yPoint.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverEntr
> yPoint.c
> new file mode 100644
> index 0000000000..e70732f5c2
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverEntr
> yPoint.c
> @@ -0,0 +1,182 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscSubclassDriverEntryPoint.c
> +
> +Abstract:
> +
> + This driver parses the mMiscSubclassDataTable structure and reports
> + any generated data to the DataHub.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +#include "MiscSubclassDriver.h"
> +#include <Protocol/HiiString.h>
> +#include <Guid/PlatformInfo.h>
> +
> +
> +EFI_HII_HANDLE mHiiHandle;
> +EFI_HII_STRING_PROTOCOL *mHiiString;
> +EFI_PLATFORM_INFO_HOB *mPlatformInfo=NULL;
> +
> +EFI_STRING
> +EFIAPI
> +SmbiosMiscGetString (
> + IN EFI_STRING_ID StringId
> + ){
> +
> + EFI_STATUS Status;
> + UINTN StringSize;
> + CHAR16 TempString;
> + EFI_STRING String;
> + String = NULL;
> +
> + //
> + // Retrieve the size of the string in the string package for the BestLanguage
> + //
> + StringSize = 0;
> + Status = mHiiString->GetString (
> + mHiiString,
> + "en-US",
> + mHiiHandle,
> + StringId,
> + &TempString,
> + &StringSize,
> + NULL
> + );
> + //
> + // If GetString() returns EFI_SUCCESS for a zero size,
> + // then there are no supported languages registered for HiiHandle. If
> GetString()
> + // returns an error other than EFI_BUFFER_TOO_SMALL, then HiiHandle is
> not present
> + // in the HII Database
> + //
> + if (Status != EFI_BUFFER_TOO_SMALL) {
> + goto Error;
> + }
> +
> + //
> + // Allocate a buffer for the return string
> + //
> + String = AllocateZeroPool (StringSize);
> + if (String == NULL) {
> + goto Error;
> + }
> +
> + //
> + // Retrieve the string from the string package
> + //
> + Status = mHiiString->GetString (
> + mHiiString,
> + "en-US",
> + mHiiHandle,
> + StringId,
> + String,
> + &StringSize,
> + NULL
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + // Free the buffer and return NULL if the supported languages can not be
> retrieved.
> + //
> + FreePool (String);
> + String = NULL;
> + }
> +Error:
> +
> + return String;
> +}
> +
> +/**
> + Standard EFI driver point. This driver parses the mMiscSubclassDataTable
> + structure and reports any generated data to the DataHub.
> +
> + @param ImageHandle - Handle for the image of this driver
> + @param SystemTable - Pointer to the EFI System Table
> +
> + @retval EFI_SUCCESS - The data was successfully reported to the Data
> Hub.
> + @retval EFI_DEVICE_ERROR - Can not locate any protocols
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +MiscSubclassDriverEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + UINTN Index;
> + EFI_STATUS EfiStatus;
> + EFI_SMBIOS_PROTOCOL *Smbios;
> + EFI_PEI_HOB_POINTERS GuidHob;
> +
> +
> +
> + GuidHob.Raw = GetHobList ();
> + if (GuidHob.Raw != NULL) {
> + if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid,
> GuidHob.Raw)) != NULL) {
> + mPlatformInfo = GET_GUID_HOB_DATA (GuidHob.Guid);
> + }
> + }
> +
> + DEBUG ((EFI_D_ERROR, "PlatformInfoHob->BoardId [0x%x]\n",
> mPlatformInfo->BoardId));
> +
> + //
> + // Retrieve the pointer to the UEFI HII String Protocol
> + //
> + EfiStatus = gBS->LocateProtocol (
> + &gEfiHiiStringProtocolGuid,
> + NULL,
> + (VOID **) &mHiiString
> + );
> + ASSERT_EFI_ERROR (EfiStatus);
> +
> + EfiStatus = gBS->LocateProtocol(
> + &gEfiSmbiosProtocolGuid,
> + NULL,
> + (VOID**)&Smbios
> + );
> +
> + if (EFI_ERROR(EfiStatus)) {
> + DEBUG((EFI_D_ERROR, "Could not locate SMBIOS protocol. %r\n",
> EfiStatus));
> + return EfiStatus;
> + }
> +
> + mHiiHandle = HiiAddPackages (
> + &gEfiCallerIdGuid,
> + NULL,
> + MiscSubclassStrings,
> + NULL
> + );
> + ASSERT (mHiiHandle != NULL);
> +
> + for (Index = 0; Index < mMiscSubclassDataTableEntries; ++Index) {
> + //
> + // If the entry have a function pointer, just log the data.
> + //
> + if (mMiscSubclassDataTable[Index].Function != NULL) {
> + EfiStatus = (*mMiscSubclassDataTable[Index].Function)(
> + mMiscSubclassDataTable[Index].RecordData,
> + Smbios
> + );
> +
> + if (EFI_ERROR(EfiStatus)) {
> + DEBUG((EFI_D_ERROR, "Misc smbios store error. Index=%d,
> ReturnStatus=%r\n", Index, EfiStatus));
> + return EfiStatus;
> + }
> + }
> + }
> +
> + return EfiStatus;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageSt
> ring.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageSt
> ring.uni
> new file mode 100644
> index 0000000000..9f3fdf8a3f
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageSt
> ring.uni
> @@ -0,0 +1,24 @@
> +// *++
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscSystemLanguageString.uni
> +//
> +// Abstract:
> +//
> +// System language information
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +
> +#string STR_MISC_SYSTEM_LANGUAGE_EN_US #language en-US "enUS"
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageSt
> ringData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageSt
> ringData.c
> new file mode 100644
> index 0000000000..a9def23560
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageSt
> ringData.c
> @@ -0,0 +1,34 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscSystemLanguageStringData.c
> +
> +Abstract:
> +
> + Static data of System language string information.
> + System language string information is Misc. subclass type 12 and SMBIOS
> type 13.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) Bios Vendor data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_LANGUAGE_STRING_DAT
> A, SystemLanguageString)
> += {
> + 0,
> + STRING_TOKEN(STR_MISC_SYSTEM_LANGUAGE_EN_US)
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageSt
> ringFunction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageSt
> ringFunction.c
> new file mode 100644
> index 0000000000..8abfa4074a
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageSt
> ringFunction.c
> @@ -0,0 +1,93 @@
> +/*++
> +
> +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + MiscResetCapabilitiesFunction.c
> +
> +Abstract:
> +
> + ResetCapabilities.
> + SMBIOS type 23.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +/**
> + This function makes boot time changes to the contents of the
> + MiscOemString (Type 11).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +
> +MISC_SMBIOS_TABLE_FUNCTION(SystemLanguageString)
> +{
> + EFI_STATUS Status;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE13 *SmbiosRecord;
> + UINTN StrLeng;
> + CHAR8 *OptionalStrStart;
> + EFI_STRING Str;
> + STRING_REF TokenToGet;
> +
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_LANGUAGE_EN_US);
> + Str = SmbiosMiscGetString (TokenToGet);
> + StrLeng = StrLen(Str);
> + if (StrLeng > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE13) + StrLeng +
> 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE13) + StrLeng + 1 +
> 1);
> +
> + SmbiosRecord->Hdr.Type =
> EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE13);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> + SmbiosRecord->InstallableLanguages = 1;
> + SmbiosRecord->Flags = 1;
> + SmbiosRecord->CurrentLanguages = 1;
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(Str, OptionalStrStart);
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufactu
> rer.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufactu
> rer.uni
> new file mode 100644
> index 0000000000..d587e0d7df
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufactu
> rer.uni
> @@ -0,0 +1,30 @@
> +// *++
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscSystemManufacturer.uni
> +//
> +// Abstract:
> +//
> +// System manufacturer information
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +
> +#string STR_MISC_SYSTEM_MANUFACTURER #language en-US "Circuitco"
> +#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US
> "VALLEYVIEW A0 PLATFORM"
> +#string STR_MISC_SYSTEM_VERSION #language en-US "A0"
> +#string STR_MISC_SYSTEM_SERIAL_NUMBER #language en-US "To be
> filled by O.E.M"
> +#string STR_MISC_SYSTEM_SKU_NUMBER #language en-US "To be filled
> by O.E.M"
> +#string STR_MISC_SYSTEM_FAMILY_NAME #language en-US "IA Tablet"
> +#string STR_MISC_SYSTEM_FAMILY_NAME1 #language en-US "IA
> Notebook"
> \ No newline at end of file
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufactu
> rerData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufactu
> rerData.c
> new file mode 100644
> index 0000000000..dc12fa8e16
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufactu
> rerData.c
> @@ -0,0 +1,48 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscSystemManufacturerData.c
> +
> +Abstract:
> +
> + Static data of System manufacturer information.
> + System manufacturer information is Misc. subclass type 3 and SMBIOS
> type 1.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) System Manufacturer data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_MANUFACTURER_DATA,
> MiscSystemManufacturer)
> += {
> + STRING_TOKEN(STR_MISC_SYSTEM_MANUFACTURER), //
> SystemManufactrurer
> + STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), //
> SystemProductName
> + STRING_TOKEN(STR_MISC_SYSTEM_VERSION), // SystemVersion
> + STRING_TOKEN(STR_MISC_SYSTEM_SERIAL_NUMBER), //
> SystemSerialNumber
> + { // SystemUuid
> + //
> + // Undefined GUID but can be programmed later.
> + //0xFFFFFFFF, 0xFFFF, 0xFFFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> 0xFF
> +
> + // Undefined GUID that cannot be programmed later.
> + //0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00
> + // TODO Hard code here for WHCT test.
> + 0xa5000288, 0x6462, 0x4524, 0x98, 0x6a, 0x9b, 0x77, 0x37, 0xe3, 0x15,
> 0xcf
> + //
> + },
> + EfiSystemWakeupTypePowerSwitch // SystemWakeupType
> +};
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufactu
> rerFunction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufactu
> rerFunction.c
> new file mode 100644
> index 0000000000..63c4f50ed5
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufactu
> rerFunction.c
> @@ -0,0 +1,364 @@
> +/*++
> +
> +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
> +
> +Module Name:
> +
> + MiscSystemManufacturerFunction.c
> +
> +Abstract:
> +
> + This driver parses the mMiscSubclassDataTable structure and reports
> + any generated data.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +#include "MiscSubclassDriver.h"
> +#include <Protocol/DxeSmmReadyToLock.h>
> +#include <Library/NetLib.h>
> +#include "Library/DebugLib.h"
> +#include <Uefi/UefiBaseType.h>
> +#include <Guid/PlatformInfo.h>
> +
> +
> +extern EFI_PLATFORM_INFO_HOB *mPlatformInfo;
> +
> +
> +/**
> +
> + Publish the smbios type 1.
> +
> + @param Event Event whose notification function is being invoked
> (gEfiDxeSmmReadyToLockProtocolGuid).
> + @param Context Pointer to the notification functions context, which is
> implementation dependent.
> +
> + @retval None
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +AddSmbiosManuCallback (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> +
> + CHAR8 *OptionalStrStart;
> + UINTN ManuStrLen;
> + UINTN VerStrLen;
> + UINTN PdNameStrLen;
> + UINTN SerialNumStrLen;
> + UINTN SkuNumberStrLen;
> + UINTN FamilyNameStrLen;
> + EFI_STATUS Status;
> + EFI_STRING Manufacturer;
> + EFI_STRING ProductName;
> + EFI_STRING Version;
> + EFI_STRING SerialNumber;
> + EFI_STRING SkuNumber;
> + EFI_STRING FamilyName;
> + STRING_REF TokenToGet;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE1 *SmbiosRecord;
> + EFI_MISC_SYSTEM_MANUFACTURER *ForType1InputData;
> + EFI_SMBIOS_PROTOCOL *Smbios;
> + CHAR16 Buffer[40];
> +
> + CHAR16 *MacStr;
> + EFI_HANDLE *Handles;
> + UINTN BufferSize;
> + CHAR16 PlatformNameBuffer[40];
> +
> + ForType1InputData = (EFI_MISC_SYSTEM_MANUFACTURER *)Context;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (Context == NULL || mPlatformInfo == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID *)
> &Smbios);
> + ASSERT_EFI_ERROR (Status);
> +
> +
> + if (BOARD_ID_MINNOW2_TURBOT == mPlatformInfo->BoardId) {
> + // Detect the board is Turbot board platform
> + UnicodeSPrint (PlatformNameBuffer, sizeof
> (PlatformNameBuffer),L"%s",L"Minnowboard Turbot ");
> + } else {
> + UnicodeSPrint (PlatformNameBuffer, sizeof
> (PlatformNameBuffer),L"%s",L"Minnowboard Max ");
> + }
> +
> + //
> + // Silicon Steppings
> + //
> + switch (PchStepping()) {
> + case PchA0:
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s%s", PlatformNameBuffer,
> L"A0 PLATFORM");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NA
> ME), Buffer, NULL);
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"A0");
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION),
> Buffer, NULL);
> + DEBUG ((EFI_D_ERROR, "A0 Stepping Detected\n"));
> + break;
> + case PchA1:
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s%s", PlatformNameBuffer,
> L"A1 PLATFORM");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NA
> ME), Buffer, NULL);
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"A1");
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION),
> Buffer, NULL);
> + DEBUG ((EFI_D_ERROR, "A1 Stepping Detected\n"));
> + break;
> + case PchB0:
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s%s", PlatformNameBuffer,
> L"B0 PLATFORM");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NA
> ME), Buffer, NULL);
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"B0");
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION),
> Buffer, NULL);
> + DEBUG ((EFI_D_ERROR, "B0 Stepping Detected\n"));
> + break;
> + case PchB1:
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s%s", PlatformNameBuffer,
> L"B1 PLATFORM");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NA
> ME), Buffer, NULL);
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"B1");
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION),
> Buffer, NULL);
> + DEBUG ((EFI_D_ERROR, "B1 Stepping Detected\n"));
> + break;
> + case PchB2:
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s%s", PlatformNameBuffer,
> L"B2 PLATFORM");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NA
> ME), Buffer, NULL);
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"B2");
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION),
> Buffer, NULL);
> + DEBUG ((EFI_D_ERROR, "B2 Stepping Detected\n"));
> + break;
> + case PchB3:
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s%s", PlatformNameBuffer,
> L"B3 PLATFORM");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NA
> ME), Buffer, NULL);
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"B3");
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION),
> Buffer, NULL);
> + DEBUG ((EFI_D_ERROR, "B3 Stepping Detected\n"));
> + break;
> + case PchC0:
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s%s", PlatformNameBuffer,
> L"C0 PLATFORM");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NA
> ME), Buffer, NULL);
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"C0");
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION),
> Buffer, NULL);
> + DEBUG ((EFI_D_ERROR, "C0 Stepping Detected\n"));
> + break;
> + case PchD0:
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s%s", PlatformNameBuffer,
> L"D0 PLATFORM");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NA
> ME), Buffer, NULL);
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"D0");
> + HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION),
> Buffer, NULL);
> + DEBUG ((EFI_D_ERROR, "D0 Stepping Detected\n"));
> + break;
> + default:
> + DEBUG ((EFI_D_ERROR, "Unknow Stepping Detected\n"));
> + break;
> + }
> +
> + if (BOARD_ID_MINNOW2_TURBOT == mPlatformInfo->BoardId) {
> + UnicodeSPrint (Buffer, sizeof (Buffer),L"ADI");
> +
> HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_MANUFACTUR
> ER), Buffer, NULL);
> + }
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER);
> + Manufacturer = SmbiosMiscGetString (TokenToGet);
> + ManuStrLen = StrLen(Manufacturer);
> + if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);
> + ProductName = SmbiosMiscGetString (TokenToGet);
> + PdNameStrLen = StrLen(ProductName);
> + if (PdNameStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);
> + Version = SmbiosMiscGetString (TokenToGet);
> + VerStrLen = StrLen(Version);
> + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + //Get handle infomation
> + //
> + BufferSize = 0;
> + Handles = NULL;
> + Status = gBS->LocateHandle (
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + Handles
> + );
> +
> + if (Status == EFI_BUFFER_TOO_SMALL) {
> + Handles = AllocateZeroPool(BufferSize);
> + if (Handles == NULL) {
> + return (EFI_OUT_OF_RESOURCES);
> + }
> + Status = gBS->LocateHandle(
> + ByProtocol,
> + &gEfiSimpleNetworkProtocolGuid,
> + NULL,
> + &BufferSize,
> + Handles
> + );
> + }
> +
> + //
> + //Get the MAC string
> + //
> + Status = NetLibGetMacString (
> + *Handles,
> + NULL,
> + &MacStr
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + SerialNumber = MacStr;
> + SerialNumStrLen = StrLen(SerialNumber);
> + if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER);
> + SkuNumber = SmbiosMiscGetString (TokenToGet);
> + SkuNumberStrLen = StrLen(SkuNumber);
> + if (SkuNumberStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY_NAME1);
> + FamilyName = SmbiosMiscGetString (TokenToGet);
> + FamilyNameStrLen = StrLen(FamilyName);
> + if (FamilyNameStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE1) +
> ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 +
> SkuNumberStrLen + 1 + FamilyNameStrLen + 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE1) + ManuStrLen +
> 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 +
> SkuNumberStrLen + 1 + FamilyNameStrLen + 1 + 1);
> +
> + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_INFORMATION;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE1);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + //
> + // Manu will be the 1st optional string following the formatted structure.
> + //
> + SmbiosRecord->Manufacturer = 1;
> +
> + //
> + // ProductName will be the 2nd optional string following the formatted
> structure.
> + //
> + SmbiosRecord->ProductName = 2;
> +
> + //
> + // Version will be the 3rd optional string following the formatted structure.
> + //
> + SmbiosRecord->Version = 3;
> +
> + //
> + // Version will be the 4th optional string following the formatted structure.
> + //
> + SmbiosRecord->SerialNumber = 4;
> +
> + SmbiosRecord->SKUNumber= 5;
> + SmbiosRecord->Family= 6;
> +
> + //
> + // Unique UUID
> + //
> + ForType1InputData->SystemUuid.Data1 = PcdGet32
> (PcdProductSerialNumber);
> + ForType1InputData->SystemUuid.Data4[0] = PcdGet8
> (PcdEmmcManufacturerId);
> +
> + CopyMem ((UINT8 *) (&SmbiosRecord->Uuid),&ForType1InputData-
> >SystemUuid,16);
> +
> + SmbiosRecord->WakeUpType = (UINT8)ForType1InputData-
> >SystemWakeupType;
> +
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart);
> + UnicodeStrToAsciiStr(ProductName, OptionalStrStart + ManuStrLen + 1);
> + UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1 +
> PdNameStrLen + 1);
> + UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 +
> PdNameStrLen + 1 + VerStrLen + 1);
> +
> + UnicodeStrToAsciiStr(SkuNumber, OptionalStrStart + ManuStrLen + 1 +
> PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1);
> + UnicodeStrToAsciiStr(FamilyName, OptionalStrStart + ManuStrLen + 1 +
> PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 +
> SkuNumberStrLen +1);
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscSystemManufacturer (Type 1).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer)
> +{
> + EFI_STATUS Status;
> + static BOOLEAN CallbackIsInstalledManu = FALSE;
> + VOID *AddSmbiosManuCallbackNotifyReg;
> + EFI_EVENT AddSmbiosManuCallbackEvent;
> +
> +
> + if (CallbackIsInstalledManu == FALSE) {
> + CallbackIsInstalledManu = TRUE; // Prevent more than 1
> callback.
> + DEBUG ((EFI_D_INFO, "Create Smbios Manu callback.\n"));
> +
> + //
> + // gEfiDxeSmmReadyToLockProtocolGuid is ready
> + //
> + Status = gBS->CreateEvent (
> + EVT_NOTIFY_SIGNAL,
> + TPL_CALLBACK,
> + (EFI_EVENT_NOTIFY)AddSmbiosManuCallback,
> + RecordData,
> + &AddSmbiosManuCallbackEvent
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + return Status;
> +
> + }
> +
> + Status = gBS->RegisterProtocolNotify (
> + &gEfiDxeSmmReadyToLockProtocolGuid,
> + AddSmbiosManuCallbackEvent,
> + &AddSmbiosManuCallbackNotifyReg
> + );
> +
> + return Status;
> + }
> +
> + return EFI_SUCCESS;
> +
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStrin
> g.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStrin
> g.uni
> new file mode 100644
> index 0000000000..a90fa93cd6
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStrin
> g.uni
> @@ -0,0 +1,24 @@
> +// *++
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscSystemOptionString.uni
> +//
> +// Abstract:
> +//
> +// System option language
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +
> +#string STR_MISC_SYSTEM_OPTION_EN_US #language en-US "English
> (US)"
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStrin
> gData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStrin
> gData.c
> new file mode 100644
> index 0000000000..e8d5fb3ee9
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStrin
> gData.c
> @@ -0,0 +1,31 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscSystemOptionStringData.c
> +
> +Abstract:
> +
> + Static data of System option string.
> + System option string is Miscellaneous subclass type: 10 and SMBIOS type:
> 13.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +//
> +// Static (possibly build generated) Bios Vendor data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_OPTION_STRING_DATA,
> SystemOptionString)
> += { STRING_TOKEN(STR_MISC_SYSTEM_OPTION_EN_US) };
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStrin
> gFunction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStrin
> gFunction.c
> new file mode 100644
> index 0000000000..ee27a75e3a
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStrin
> gFunction.c
> @@ -0,0 +1,93 @@
> +/*++
> +
> +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscSystemOptionStringFunction.c
> +
> +Abstract:
> +
> + BIOS system option string boot time changes.
> + SMBIOS type 12.
> +
> +--*/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscSystemOptionString (Type 12).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION(SystemOptionString)
> +{
> + CHAR8 *OptionalStrStart;
> + UINTN OptStrLen;
> + EFI_STRING OptionString;
> + EFI_STATUS Status;
> + STRING_REF TokenToGet;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + SMBIOS_TABLE_TYPE12 *SmbiosRecord;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_OPTION_EN_US);
> + OptionString = SmbiosMiscGetString (TokenToGet);
> + OptStrLen = StrLen(OptionString);
> + if (OptStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE12) + OptStrLen
> + 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE12) + OptStrLen + 1
> + 1);
> +
> + SmbiosRecord->Hdr.Type =
> EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE12);
> +
> + //
> + // Make handle chosen by smbios protocol.add automatically.
> + //
> + SmbiosRecord->Hdr.Handle = 0;
> +
> + SmbiosRecord->StringCount = 1;
> + OptionalStrStart = (CHAR8*) (SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(OptionString, OptionalStrStart);
> +
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> +
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesigna
> tion.uni
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesign
> ation.uni
> new file mode 100644
> index 0000000000..f1d3e866e7
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesign
> ation.uni
> @@ -0,0 +1,34 @@
> +// *++
> +//
> +// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +// Module Name:
> +//
> +// MiscSystemSlotDesignation.uni
> +//
> +// Abstract:
> +//
> +// System slot information
> +//
> +// Revision History:
> +//
> +// --*/
> +
> +
> +/=#
> +
> +#langdef en-US "English"
> +#string STR_MISC_SYSTEM_SLOT_PCIEX16 #language en-US "PCIE X16
> SLOT"
> +#string STR_MISC_SYSTEM_SLOT_PCIEX16_1 #language en-US "PCIE X16
> SLOT 1"
> +#string STR_MISC_SYSTEM_SLOT_PCIEX16_2 #language en-US "PCIE X16
> SLOT 2"
> +#string STR_MISC_SYSTEM_SLOT_PCIEX4 #language en-US "PCIE X4
> SLOT"
> +#string STR_MISC_SYSTEM_SLOT_PCIEX1_1 #language en-US "PCIE X1
> SLOT 1"
> +#string STR_MISC_SYSTEM_SLOT_PCIEX1_2 #language en-US "PCIE X1
> SLOT 2"
> +#string STR_MISC_SYSTEM_SLOT_PCIEX1_3 #language en-US "PCIE X1
> SLOT 3"
> +#string STR_MISC_SYSTEM_SLOT_PCI1 #language en-US "PCI SLOT 1"
> +#string STR_MISC_SYSTEM_SLOT_PCI2 #language en-US "PCI SLOT 2"
> +#string STR_MISC_SYSTEM_SLOT_PCI3 #language en-US "PCI SLOT 3"
> +
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesigna
> tionData.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesign
> ationData.c
> new file mode 100644
> index 0000000000..48beeb52d3
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesign
> ationData.c
> @@ -0,0 +1,246 @@
> +/** @file
> +
> +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscSystemSlotDesignationData.c
> +
> +Abstract:
> +
> + Static data of System Slot Designation.
> + System Slot Designation is Misc. subclass type 7 and SMBIOS type 9.
> +
> +
> +**/
> +
> +
> +#include "CommonHeader.h"
> +
> +#include "MiscSubclassDriver.h"
> +
> +
> +//
> +// Static (possibly build generated) Bios Vendor data.
> +//
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DAT
> A, MiscSystemSlotPCIEx16Slot1) = {
> + STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX16_1), //
> SlotDesignation
> + EfiSlotTypePciExpress, // SlotType
> + EfiSlotDataBusWidth16xOrx16, // SlotDataBusWidth
> + EfiSlotUsageAvailable, // SlotUsage
> + EfiSlotLengthShort, // SlotLength
> + 0x06, // SlotId
> + { // SlotCharacteristics
> + 0, // CharacteristicsUnknown :1;
> + 0, // Provides50Volts :1;
> + 1, // Provides33Volts :1;
> + 0, // SharedSlot :1;
> + 0, // PcCard16Supported :1;
> + 0, // CardBusSupported :1;
> + 0, // ZoomVideoSupported :1;
> + 0, // ModemRingResumeSupported:1;
> + 0, // PmeSignalSupported :1;
> + 0, // HotPlugDevicesSupported :1;
> + 0, // SmbusSignalSupported :1;
> + 0 // Reserved :21;
> + },
> + 0 // SlotDevicePath
> +};
> +
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DAT
> A, MiscSystemSlotPCIEx16Slot2) = {
> + STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX16_2), //
> SlotDesignation
> + EfiSlotTypePciExpress, // SlotType
> + EfiSlotDataBusWidth16xOrx16, // SlotDataBusWidth
> + EfiSlotUsageAvailable, // SlotUsage
> + EfiSlotLengthShort, // SlotLength
> + 0x04, // SlotId
> + { // SlotCharacteristics
> + 0, // CharacteristicsUnknown :1;
> + 0, // Provides50Volts :1;
> + 1, // Provides33Volts :1;
> + 0, // SharedSlot :1;
> + 0, // PcCard16Supported :1;
> + 0, // CardBusSupported :1;
> + 0, // ZoomVideoSupported :1;
> + 0, // ModemRingResumeSupported:1;
> + 0, // PmeSignalSupported :1;
> + 0, // HotPlugDevicesSupported :1;
> + 0, // SmbusSignalSupported :1;
> + 0 // Reserved :21;
> + },
> + 0 // SlotDevicePath
> +};
> +
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DAT
> A, MiscSystemSlotPCIEx4) = {
> + STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX4), // SlotDesignation
> + EfiSlotTypePciExpress, // SlotType
> + EfiSlotDataBusWidth4xOrx4, // SlotDataBusWidth
> + EfiSlotUsageAvailable, // SlotUsage
> + EfiSlotLengthShort, // SlotLength
> + 0x03, // SlotId
> + { // SlotCharacteristics
> + 0, // CharacteristicsUnknown :1;
> + 0, // Provides50Volts :1;
> + 1, // Provides33Volts :1;
> + 0, // SharedSlot :1;
> + 0, // PcCard16Supported :1;
> + 0, // CardBusSupported :1;
> + 0, // ZoomVideoSupported :1;
> + 0, // ModemRingResumeSupported:1;
> + 0, // PmeSignalSupported :1;
> + 0, // HotPlugDevicesSupported :1;
> + 0, // SmbusSignalSupported :1;
> + 0 // Reserved :21;
> + },
> + 0 // SlotDevicePath
> +};
> +
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DAT
> A, MiscSystemSlotPCIEx1Slot1) = {
> + STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX1_1), // SlotDesignation
> + EfiSlotTypePciExpress, // SlotType
> + EfiSlotDataBusWidth1xOrx1, // SlotDataBusWidth
> + EfiSlotUsageAvailable, // SlotUsage
> + EfiSlotLengthShort, // SlotLength
> + 0x02, // SlotId
> + { // SlotCharacteristics
> + 0, // CharacteristicsUnknown :1;
> + 0, // Provides50Volts :1;
> + 1, // Provides33Volts :1;
> + 0, // SharedSlot :1;
> + 0, // PcCard16Supported :1;
> + 0, // CardBusSupported :1;
> + 0, // ZoomVideoSupported :1;
> + 0, // ModemRingResumeSupported:1;
> + 1, // PmeSignalSupported :1;
> + 0, // HotPlugDevicesSupported :1;
> + 1, // SmbusSignalSupported :1;
> + 0 // Reserved :21;
> + },
> + 0 // SlotDevicePath
> +};
> +
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DAT
> A, MiscSystemSlotPCIEx1Slot2) = {
> + STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX1_2), // SlotDesignation
> + EfiSlotTypePciExpress, // SlotType
> + EfiSlotDataBusWidth1xOrx1, // SlotDataBusWidth
> + EfiSlotUsageAvailable, // SlotUsage
> + EfiSlotLengthShort, // SlotLength
> + 0x15, // SlotId
> + { // SlotCharacteristics
> + 0, // CharacteristicsUnknown :1;
> + 0, // Provides50Volts :1;
> + 1, // Provides33Volts :1;
> + 0, // SharedSlot :1;
> + 0, // PcCard16Supported :1;
> + 0, // CardBusSupported :1;
> + 0, // ZoomVideoSupported :1;
> + 0, // ModemRingResumeSupported:1;
> + 1, // PmeSignalSupported :1;
> + 0, // HotPlugDevicesSupported :1;
> + 1, // SmbusSignalSupported :1;
> + 0 // Reserved :21;
> + },
> + 0 // SlotDevicePath
> +};
> +
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DAT
> A, MiscSystemSlotPCIEx1Slot3) = {
> + STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX1_3), // SlotDesignation
> + EfiSlotTypePciExpress, // SlotType
> + EfiSlotDataBusWidth1xOrx1, // SlotDataBusWidth
> + EfiSlotUsageAvailable, // SlotUsage
> + EfiSlotLengthShort, // SlotLength
> + 0x16, // SlotId
> + { // SlotCharacteristics
> + 0, // CharacteristicsUnknown :1;
> + 0, // Provides50Volts :1;
> + 1, // Provides33Volts :1;
> + 0, // SharedSlot :1;
> + 0, // PcCard16Supported :1;
> + 0, // CardBusSupported :1;
> + 0, // ZoomVideoSupported :1;
> + 0, // ModemRingResumeSupported:1;
> + 1, // PmeSignalSupported :1;
> + 0, // HotPlugDevicesSupported :1;
> + 1, // SmbusSignalSupported :1;
> + 0 // Reserved :21;
> + },
> + 0 // SlotDevicePath
> +};
> +
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DAT
> A, MiscSystemSlotPCI1) = {
> + STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCI1), // SlotDesignation
> + EfiSlotTypePci, // SlotType
> + EfiSlotDataBusWidth32Bit, // SlotDataBusWidth
> + EfiSlotUsageAvailable, // SlotUsage
> + EfiSlotLengthLong , // SlotLength
> + 0x07, // SlotId
> + { // SlotCharacteristics
> + 0, // CharacteristicsUnknown :1;
> + 0, // Provides50Volts :1;
> + 1, // Provides33Volts :1;
> + 0, // SharedSlot :1;
> + 0, // PcCard16Supported :1;
> + 0, // CardBusSupported :1;
> + 0, // ZoomVideoSupported :1;
> + 0, // ModemRingResumeSupported:1;
> + 1, // PmeSignalSupported :1;
> + 0, // HotPlugDevicesSupported :1;
> + 1, // SmbusSignalSupported :1;
> + 0 // Reserved :21;
> + },
> + 0 // SlotDevicePath
> +};
> +
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DAT
> A, MiscSystemSlotPCI2) = {
> + STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCI2), // SlotDesignation
> + EfiSlotTypePci, // SlotType
> + EfiSlotDataBusWidth32Bit, // SlotDataBusWidth
> + EfiSlotUsageAvailable, // SlotUsage
> + EfiSlotLengthLong , // SlotLength
> + 0x18, // SlotId
> + { // SlotCharacteristics
> + 0, // CharacteristicsUnknown :1;
> + 0, // Provides50Volts :1;
> + 1, // Provides33Volts :1;
> + 0, // SharedSlot :1;
> + 0, // PcCard16Supported :1;
> + 0, // CardBusSupported :1;
> + 0, // ZoomVideoSupported :1;
> + 0, // ModemRingResumeSupported:1;
> + 1, // PmeSignalSupported :1;
> + 0, // HotPlugDevicesSupported :1;
> + 1, // SmbusSignalSupported :1;
> + 0 // Reserved :21;
> + },
> + 0 // SlotDevicePath
> +};
> +
> +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DAT
> A, MiscSystemSlotPCI3) = {
> + STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCI3), // SlotDesignation
> + EfiSlotTypePci, // SlotType
> + EfiSlotDataBusWidth32Bit, // SlotDataBusWidth
> + EfiSlotUsageAvailable, // SlotUsage
> + EfiSlotLengthLong , // SlotLength
> + 0x17, // SlotId
> + { // SlotCharacteristics
> + 0, // CharacteristicsUnknown :1;
> + 0, // Provides50Volts :1;
> + 1, // Provides33Volts :1;
> + 0, // SharedSlot :1;
> + 0, // PcCard16Supported :1;
> + 0, // CardBusSupported :1;
> + 0, // ZoomVideoSupported :1;
> + 0, // ModemRingResumeSupported:1;
> + 1, // PmeSignalSupported :1;
> + 0, // HotPlugDevicesSupported :1;
> + 1, // SmbusSignalSupported :1;
> + 0 // Reserved :21;
> + },
> + 0 // SlotDevicePath
> +};
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesigna
> tionFunction.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesign
> ationFunction.c
> new file mode 100644
> index 0000000000..7270ef826f
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesign
> ationFunction.c
> @@ -0,0 +1,127 @@
> +/*++
> +
> +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + MiscSystemSlotDesignatorFunction.c
> +
> +Abstract:
> +
> + BIOS system slot designator information boot time changes.
> + SMBIOS type 9.
> +
> +--*/
> +
> +#include "MiscSubclassDriver.h"
> +
> +/**
> + This function makes boot time changes to the contents of the
> + MiscSystemSlotDesignator structure (Type 9).
> +
> + @param RecordData Pointer to copy of RecordData from the Data
> Table.
> +
> + @retval EFI_SUCCESS All parameters were valid.
> + @retval EFI_UNSUPPORTED Unexpected RecordType value.
> + @retval EFI_INVALID_PARAMETER Invalid parameter was found.
> +
> +**/
> +MISC_SMBIOS_TABLE_FUNCTION(MiscSystemSlotDesignation)
> +{
> + CHAR8 *OptionalStrStart;
> + UINTN SlotDesignationStrLen;
> + EFI_STATUS Status;
> + EFI_STRING SlotDesignation;
> + STRING_REF TokenToGet;
> + SMBIOS_TABLE_TYPE9 *SmbiosRecord;
> + EFI_SMBIOS_HANDLE SmbiosHandle;
> + EFI_MISC_SYSTEM_SLOT_DESIGNATION* ForType9InputData;
> +
> + ForType9InputData = (EFI_MISC_SYSTEM_SLOT_DESIGNATION
> *)RecordData;
> +
> + //
> + // First check for invalid parameters.
> + //
> + if (RecordData == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + TokenToGet = 0;
> + switch (ForType9InputData->SlotDesignation) {
> + case STR_MISC_SYSTEM_SLOT_PCIEX16_1:
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX16_1);
> + break;
> + case STR_MISC_SYSTEM_SLOT_PCIEX16_2:
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX16_2);
> + break;
> + case STR_MISC_SYSTEM_SLOT_PCIEX4:
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX4);
> + break;
> + case STR_MISC_SYSTEM_SLOT_PCIEX1_1:
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX1_1);
> + break;
> + case STR_MISC_SYSTEM_SLOT_PCIEX1_2:
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX1_2);
> + break;
> + case STR_MISC_SYSTEM_SLOT_PCIEX1_3:
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX1_3);
> + break;
> + case STR_MISC_SYSTEM_SLOT_PCI1:
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCI1);
> + break;
> + case STR_MISC_SYSTEM_SLOT_PCI2:
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCI2);
> + break;
> + case STR_MISC_SYSTEM_SLOT_PCI3:
> + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCI3);
> + break;
> + default:
> + break;
> + }
> +
> + SlotDesignation = SmbiosMiscGetString (TokenToGet);
> + SlotDesignationStrLen = StrLen(SlotDesignation);
> + if (SlotDesignationStrLen > SMBIOS_STRING_MAX_LENGTH) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Two zeros following the last string.
> + //
> + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE9) +
> SlotDesignationStrLen + 1 + 1);
> + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE9)
> +SlotDesignationStrLen + 1 + 1);
> +
> + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_SLOTS;
> + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE9);
> + SmbiosRecord->Hdr.Handle = 0;
> + SmbiosRecord->SlotDesignation = 1;
> + SmbiosRecord->SlotType = (UINT8)ForType9InputData->SlotType;
> + SmbiosRecord->SlotDataBusWidth = (UINT8)ForType9InputData-
> >SlotDataBusWidth;
> + SmbiosRecord->CurrentUsage = (UINT8)ForType9InputData->SlotUsage;
> + SmbiosRecord->SlotLength = (UINT8)ForType9InputData->SlotLength;
> + SmbiosRecord->SlotID = ForType9InputData->SlotId;
> +
> + //
> + // Slot Characteristics
> + //
> + CopyMem ((UINT8 *) &SmbiosRecord->SlotCharacteristics1,(UINT8 *)
> &ForType9InputData->SlotCharacteristics,2);
> + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
> + UnicodeStrToAsciiStr(SlotDesignation, OptionalStrStart);
> + //
> + // Now we have got the full smbios record, call smbios protocol to add this
> record.
> + //
> + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
> + Status = Smbios-> Add(
> + Smbios,
> + NULL,
> + &SmbiosHandle,
> + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
> + );
> + FreePool(SmbiosRecord);
> + return Status;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf
> new file mode 100644
> index 0000000000..37e54a92a8
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf
> @@ -0,0 +1,139 @@
> +## @file
> +# Component name for module MiscSubclass
> +#
> +# FIX ME!
> +# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = MiscSubclass
> + FILE_GUID = 4EFFB560-B28B-4e57-9DAD-4344E32EA3BA
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = MiscSubclassDriverEntryPoint
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + MiscBaseBoardManufacturer.uni
> + MiscBaseBoardManufacturerData.c
> + MiscBaseBoardManufacturerFunction.c
> + MiscBiosVendor.uni
> + MiscBiosVendorData.c
> + MiscBiosVendorFunction.c
> + MiscBootInformationData.c
> + MiscBootInformationFunction.c
> + MiscChassisManufacturer.uni
> + MiscChassisManufacturerData.c
> + MiscChassisManufacturerFunction.c
> + MiscNumberOfInstallableLanguagesData.c
> + MiscNumberOfInstallableLanguagesFunction.c
> + MiscOemString.uni
> + MiscOemStringData.c
> + MiscOemStringFunction.c
> + MiscOnboardDevice.uni
> + MiscOnboardDeviceData.c
> + MiscOnboardDeviceFunction.c
> + MiscPortInternalConnectorDesignator.uni
> + MiscPortInternalConnectorDesignatorData.c
> + MiscPortInternalConnectorDesignatorFunction.c
> + MiscResetCapabilitiesData.c
> + MiscResetCapabilitiesFunction.c
> + MiscSystemLanguageString.uni
> + MiscSystemLanguageStringData.c
> + MiscSystemLanguageStringFunction.c
> + MiscSystemManufacturer.uni
> + MiscSystemManufacturerData.c
> + MiscSystemManufacturerFunction.c
> + MiscSystemOptionString.uni
> + MiscSystemOptionStringData.c
> + MiscSystemOptionStringFunction.c
> + MiscSystemSlotDesignation.uni
> + MiscSystemSlotDesignationData.c
> + MiscSystemSlotDesignationFunction.c
> + MiscSubclassDriver.h
> + MiscSubclassDriver.uni
> + MiscSubclassDriverDataTable.c
> + MiscSubclassDriverEntryPoint.c
> + CommonHeader.h
> + MiscOemType0x90Function.c
> + MiscOemType0x90Data.c
> + MiscOemType0x90.uni
> + MiscProcessorInformation.uni
> + MiscProcessorInformationData.c
> + MiscProcessorInformationFunction.c
> + MiscProcessorCache.uni
> + MiscProcessorCacheData.c
> + MiscProcessorCacheFunction.c
> + MiscPhysicalArray.uni
> + MiscPhysicalArrayData.c
> + MiscPhysicalArrayFunction.c
> + MiscMemoryDevice.uni
> + MiscMemoryDeviceData.c
> + MiscMemoryDeviceFunction.c
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + MdePkg/MdePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + HiiLib
> + DevicePathLib
> + UefiBootServicesTableLib
> + UefiRuntimeServicesTableLib
> + UefiDriverEntryPoint
> + BaseMemoryLib
> + DebugLib
> + BaseLib
> + MemoryAllocationLib
> + PcdLib
> + UefiLib
> + BiosIdLib
> + PrintLib
> + CpuIA32Lib
> + PchPlatformLib
> + I2cLib
> + NetLib
> + HobLib
> +
> +[Guids]
> + gEfiProcessorSubClassGuid
> + gEfiCacheSubClassGuid
> + gEfiNormalSetupGuid
> + gEfiPlatformInfoGuid
> + gEfiVlv2VariableGuid
> +
> +[Protocols]
> + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
> + gEfiDxeSmmReadyToLockProtocolGuid # PROTOCOL
> ALWAYS_CONSUMED
> + gEfiDataHubProtocolGuid
> + gEfiMpServiceProtocolGuid
> + gMemInfoProtocolGuid
> + gEfiTdtOperationProtocolGuid
> + gDxePchPlatformPolicyProtocolGuid
> + gEfiSpiProtocolGuid
> + gEfiSimpleNetworkProtocolGuid
> +
> +[Pcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang
> + gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId
> + gEfiVLVTokenSpaceGuid.PcdProductSerialNumber
> +
> +[Depex]
> + gEfiSmbiosProtocolGuid AND gMemInfoProtocolGuid AND
> gEfiMpServiceProtocolGuid AND gEfiSimpleNetworkProtocolGuid
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchTh
> unk/SmmSwDispatch2OnSmmSwDispatchThunk.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchTh
> unk/SmmSwDispatch2OnSmmSwDispatchThunk.c
> new file mode 100644
> index 0000000000..0dbd6f00e1
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchTh
> unk/SmmSwDispatch2OnSmmSwDispatchThunk.c
> @@ -0,0 +1,459 @@
> +/** @file
> + SMM SwDispatch2 Protocol on SMM SwDispatch Protocol Thunk driver.
> +
> + Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <FrameworkSmm.h>
> +
> +#include <Protocol/SmmSwDispatch2.h>
> +#include <Protocol/SmmSwDispatch.h>
> +#include <Protocol/SmmControl.h>
> +#include <Protocol/SmmCpu.h>
> +
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/SmmServicesTableLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/DebugLib.h>
> +
> +typedef struct {
> + LIST_ENTRY Link;
> + EFI_HANDLE DispatchHandle;
> + UINTN SwSmiInputValue;
> + UINTN DispatchFunction;
> +} EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT;
> +
> +/**
> + Register a child SMI source dispatch function for the specified software
> SMI.
> +
> + This service registers a function (DispatchFunction) which will be called
> when the software
> + SMI source specified by RegisterContext->SwSmiCpuIndex is detected. On
> return,
> + DispatchHandle contains a unique handle which may be used later to
> unregister the function
> + using UnRegister().
> +
> + @param[in] This Pointer to the
> EFI_SMM_SW_DISPATCH2_PROTOCOL instance.
> + @param[in] DispatchFunction Function to register for handler when the
> specified software
> + SMI is generated.
> + @param[in, out] RegisterContext Pointer to the dispatch function's
> context.
> + The caller fills this context in before calling
> + the register function to indicate to the register
> + function which Software SMI input value the
> + dispatch function should be invoked for.
> + @param[out] DispatchHandle Handle generated by the dispatcher to
> track the
> + function instance.
> +
> + @retval EFI_SUCCESS The dispatch function has been successfully
> + registered and the SMI source has been enabled.
> + @retval EFI_DEVICE_ERROR The SW driver was unable to enable the
> SMI source.
> + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The SW SMI
> input value
> + is not within valid range.
> + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system
> or SMM) to manage this
> + child.
> + @retval EFI_OUT_OF_RESOURCES A unique software SMI value could not
> be assigned
> + for this dispatch.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SmmSwDispatch2Register (
> + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This,
> + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
> + IN OUT EFI_SMM_SW_REGISTER_CONTEXT *RegisterContext,
> + OUT EFI_HANDLE *DispatchHandle
> + );
> +
> +/**
> + Unregister a child SMI source dispatch function for the specified software
> SMI.
> +
> + This service removes the handler associated with DispatchHandle so that it
> will no longer be
> + called in response to a software SMI.
> +
> + @param[in] This Pointer to the
> EFI_SMM_SW_DISPATCH2_PROTOCOL instance.
> + @param[in] DispatchHandle Handle of dispatch function to deregister.
> +
> + @retval EFI_SUCCESS The dispatch function has been successfully
> unregistered.
> + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SmmSwDispatch2UnRegister (
> + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This,
> + IN EFI_HANDLE DispatchHandle
> + );
> +
> +EFI_SMM_SW_DISPATCH2_PROTOCOL gSmmSwDispatch2 = {
> + SmmSwDispatch2Register,
> + SmmSwDispatch2UnRegister,
> + 0 // MaximumSwiValue
> +};
> +
> +EFI_SMM_SW_DISPATCH_PROTOCOL *mSmmSwDispatch;
> +UINT8 mSmiTriggerRegister;
> +UINT8 mSmiDataRegister;
> +
> +EFI_SMM_CPU_PROTOCOL *mSmmCpuProtocol;
> +LIST_ENTRY mSmmSwDispatch2ThunkQueue =
> INITIALIZE_LIST_HEAD_VARIABLE (mSmmSwDispatch2ThunkQueue);
> +
> +/**
> + This function find SmmSwDispatch2Context by SwSmiInputValue.
> +
> + @param SwSmiInputValue The SwSmiInputValue to indentify the
> SmmSwDispatch2 context
> +
> + @return SmmSwDispatch2 context
> +**/
> +EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *
> +FindSmmSwDispatch2ContextBySwSmiInputValue (
> + IN UINTN SwSmiInputValue
> + )
> +{
> + LIST_ENTRY *Link;
> + EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *ThunkContext;
> +
> + for (Link = mSmmSwDispatch2ThunkQueue.ForwardLink;
> + Link != &mSmmSwDispatch2ThunkQueue;
> + Link = Link->ForwardLink) {
> + ThunkContext = BASE_CR (
> + Link,
> + EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT,
> + Link
> + );
> + if (ThunkContext->SwSmiInputValue == SwSmiInputValue) {
> + return ThunkContext;
> + }
> + }
> + return NULL;
> +}
> +
> +/**
> + This function find SmmSwDispatch2Context by DispatchHandle.
> +
> + @param DispatchHandle The DispatchHandle to indentify the
> SmmSwDispatch2Thunk context
> +
> + @return SmmSwDispatch2Thunk context
> +**/
> +EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *
> +FindSmmSwDispatch2ContextByDispatchHandle (
> + IN EFI_HANDLE DispatchHandle
> + )
> +{
> + LIST_ENTRY *Link;
> + EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *ThunkContext;
> +
> + for (Link = mSmmSwDispatch2ThunkQueue.ForwardLink;
> + Link != &mSmmSwDispatch2ThunkQueue;
> + Link = Link->ForwardLink) {
> + ThunkContext = BASE_CR (
> + Link,
> + EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT,
> + Link
> + );
> + if (ThunkContext->DispatchHandle == DispatchHandle) {
> + return ThunkContext;
> + }
> + }
> + return NULL;
> +}
> +
> +/**
> + Framework dispatch function for a Software SMI handler.
> +
> + @param DispatchHandle The handle of this dispatch function.
> + @param DispatchContext The pointer to the dispatch function's
> context.
> + The SwSmiInputValue field is filled in
> + by the software dispatch driver prior to
> + invoking this dispatch function.
> + The dispatch function will only be called
> + for input values for which it is registered.
> +
> + @return None
> +
> +**/
> +VOID
> +EFIAPI
> +FrameworkDispatchFunction (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
> + )
> +{
> + EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *ThunkContext;
> + EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction;
> + EFI_SMM_SW_REGISTER_CONTEXT RegisterContext;
> + EFI_SMM_SW_CONTEXT SwContext;
> + UINTN Size;
> + UINTN Index;
> + EFI_SMM_SAVE_STATE_IO_INFO IoInfo;
> + EFI_STATUS Status;
> +
> + //
> + // Search context
> + //
> + ThunkContext = FindSmmSwDispatch2ContextBySwSmiInputValue
> (DispatchContext->SwSmiInputValue);
> + ASSERT (ThunkContext != NULL);
> + if (ThunkContext == NULL) {
> + return ;
> + }
> +
> + //
> + // Construct new context
> + //
> + RegisterContext.SwSmiInputValue = DispatchContext->SwSmiInputValue;
> + Size = sizeof(SwContext);
> + SwContext.CommandPort = IoRead8 (mSmiTriggerRegister);
> + SwContext.DataPort = IoRead8 (mSmiDataRegister);
> +
> + //
> + // Try to find which CPU trigger SWSMI
> + //
> + SwContext.SwSmiCpuIndex = 0;
> + for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
> + Status = mSmmCpuProtocol->ReadSaveState (
> + mSmmCpuProtocol,
> + sizeof(IoInfo),
> + EFI_SMM_SAVE_STATE_REGISTER_IO,
> + Index,
> + &IoInfo
> + );
> + if (EFI_ERROR (Status)) {
> + continue;
> + }
> + if (IoInfo.IoPort == mSmiTriggerRegister) {
> + //
> + // Great! Find it.
> + //
> + SwContext.SwSmiCpuIndex = Index;
> + break;
> + }
> + }
> +
> + //
> + // Dispatch
> + //
> + DispatchFunction = (EFI_SMM_HANDLER_ENTRY_POINT2)ThunkContext-
> >DispatchFunction;
> + DispatchFunction (
> + DispatchHandle,
> + &RegisterContext,
> + &SwContext,
> + &Size
> + );
> + return ;
> +}
> +
> +/**
> + Register a child SMI source dispatch function for the specified software
> SMI.
> +
> + This service registers a function (DispatchFunction) which will be called
> when the software
> + SMI source specified by RegisterContext->SwSmiCpuIndex is detected. On
> return,
> + DispatchHandle contains a unique handle which may be used later to
> unregister the function
> + using UnRegister().
> +
> + @param[in] This Pointer to the
> EFI_SMM_SW_DISPATCH2_PROTOCOL instance.
> + @param[in] DispatchFunction Function to register for handler when the
> specified software
> + SMI is generated.
> + @param[in, out] RegisterContext Pointer to the dispatch function's
> context.
> + The caller fills this context in before calling
> + the register function to indicate to the register
> + function which Software SMI input value the
> + dispatch function should be invoked for.
> + @param[out] DispatchHandle Handle generated by the dispatcher to
> track the
> + function instance.
> +
> + @retval EFI_SUCCESS The dispatch function has been successfully
> + registered and the SMI source has been enabled.
> + @retval EFI_DEVICE_ERROR The SW driver was unable to enable the
> SMI source.
> + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The SW SMI
> input value
> + is not within valid range.
> + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system
> or SMM) to manage this
> + child.
> + @retval EFI_OUT_OF_RESOURCES A unique software SMI value could not
> be assigned
> + for this dispatch.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SmmSwDispatch2Register (
> + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This,
> + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
> + IN OUT EFI_SMM_SW_REGISTER_CONTEXT *RegisterContext,
> + OUT EFI_HANDLE *DispatchHandle
> + )
> +{
> + EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *ThunkContext;
> + EFI_SMM_SW_DISPATCH_CONTEXT DispatchContext;
> + EFI_STATUS Status;
> + UINTN Index;
> +
> + if (RegisterContext->SwSmiInputValue == (UINTN)-1) {
> + //
> + // If SwSmiInputValue is set to (UINTN) -1 then a unique value will be
> assigned and returned in the structure.
> + //
> + Status = EFI_NOT_FOUND;
> + for (Index = 1; Index < gSmmSwDispatch2.MaximumSwiValue; Index++) {
> + DispatchContext.SwSmiInputValue = Index;
> + Status = mSmmSwDispatch->Register (
> + mSmmSwDispatch,
> + FrameworkDispatchFunction,
> + &DispatchContext,
> + DispatchHandle
> + );
> + if (!EFI_ERROR (Status)) {
> + RegisterContext->SwSmiInputValue = Index;
> + break;
> + }
> + }
> + if (RegisterContext->SwSmiInputValue == (UINTN)-1) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + } else {
> + DispatchContext.SwSmiInputValue = RegisterContext->SwSmiInputValue;
> + Status = mSmmSwDispatch->Register (
> + mSmmSwDispatch,
> + FrameworkDispatchFunction,
> + &DispatchContext,
> + DispatchHandle
> + );
> + }
> + if (!EFI_ERROR (Status)) {
> + //
> + // Register
> + //
> + Status = gSmst->SmmAllocatePool (
> + EfiRuntimeServicesData,
> + sizeof(*ThunkContext),
> + (VOID **)&ThunkContext
> + );
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + mSmmSwDispatch->UnRegister (mSmmSwDispatch, *DispatchHandle);
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + ThunkContext->SwSmiInputValue = RegisterContext->SwSmiInputValue;
> + ThunkContext->DispatchFunction = (UINTN)DispatchFunction;
> + ThunkContext->DispatchHandle = *DispatchHandle;
> + InsertTailList (&mSmmSwDispatch2ThunkQueue, &ThunkContext->Link);
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Unregister a child SMI source dispatch function for the specified software
> SMI.
> +
> + This service removes the handler associated with DispatchHandle so that it
> will no longer be
> + called in response to a software SMI.
> +
> + @param[in] This Pointer to the
> EFI_SMM_SW_DISPATCH2_PROTOCOL instance.
> + @param[in] DispatchHandle Handle of dispatch function to deregister.
> +
> + @retval EFI_SUCCESS The dispatch function has been successfully
> unregistered.
> + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SmmSwDispatch2UnRegister (
> + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This,
> + IN EFI_HANDLE DispatchHandle
> + )
> +{
> + EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *ThunkContext;
> + EFI_STATUS Status;
> +
> + Status = mSmmSwDispatch->UnRegister (mSmmSwDispatch,
> DispatchHandle);
> + if (!EFI_ERROR (Status)) {
> + //
> + // Unregister
> + //
> + ThunkContext = FindSmmSwDispatch2ContextByDispatchHandle
> (DispatchHandle);
> + ASSERT (ThunkContext != NULL);
> + if (ThunkContext != NULL) {
> + RemoveEntryList (&ThunkContext->Link);
> + gSmst->SmmFreePool (ThunkContext);
> + }
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Entry Point for this thunk driver.
> +
> + @param[in] ImageHandle Image handle of this driver.
> + @param[in] SystemTable A Pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The entry point is executed successfully.
> + @retval other Some error occurred when executing this entry point.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SmmSwDispatch2ThunkMain (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_SMM_CONTROL_PROTOCOL *SmmControl;
> + EFI_SMM_CONTROL_REGISTER RegisterInfo;
> +
> + //
> + // Locate Framework SMM SwDispatch Protocol
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiSmmSwDispatchProtocolGuid,
> + NULL,
> + (VOID **)&mSmmSwDispatch
> + );
> + ASSERT_EFI_ERROR (Status);
> + gSmmSwDispatch2.MaximumSwiValue = mSmmSwDispatch-
> >MaximumSwiValue;
> + if (gSmmSwDispatch2.MaximumSwiValue == 0x0) {
> + DEBUG ((EFI_D_ERROR, "BUGBUG: MaximumSwiValue is 0, work-around
> to make it 0xFF\n"));
> + gSmmSwDispatch2.MaximumSwiValue = 0xFF;
> + }
> +
> + //
> + // Locate Framework SMM Control Protocol
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiSmmControlProtocolGuid,
> + NULL,
> + (VOID **)&SmmControl
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> + Status = SmmControl->GetRegisterInfo (
> + SmmControl,
> + &RegisterInfo
> + );
> + ASSERT_EFI_ERROR (Status);
> + mSmiTriggerRegister = RegisterInfo.SmiTriggerRegister;
> + mSmiDataRegister = RegisterInfo.SmiDataRegister;
> +
> + //
> + // Locate PI SMM CPU protocol
> + //
> + Status = gSmst->SmmLocateProtocol (
> + &gEfiSmmCpuProtocolGuid,
> + NULL,
> + (VOID **)&mSmmCpuProtocol
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Publish PI SMM SwDispatch2 Protocol
> + //
> + ImageHandle = NULL;
> + Status = gSmst->SmmInstallProtocolInterface (
> + &ImageHandle,
> + &gEfiSmmSwDispatch2ProtocolGuid,
> + EFI_NATIVE_INTERFACE,
> + &gSmmSwDispatch2
> + );
> + ASSERT_EFI_ERROR (Status);
> + return Status;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchTh
> unk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchTh
> unk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
> new file mode 100644
> index 0000000000..4f95fc281e
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchTh
> unk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
> @@ -0,0 +1,54 @@
> +## @file
> +# Component description file for SMM SwDispatch2 Protocol on SMM
> SwDispatch Protocol Thunk driver.
> +#
> +# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SmmSwDispatch2OnSmmSwDispatchThunk
> + FILE_GUID = 1410C6AC-9F4B-495b-9C23-8A5AEB0165E9
> + MODULE_TYPE = DXE_SMM_DRIVER
> + VERSION_STRING = 1.0
> + PI_SPECIFICATION_VERSION = 0x0001000A
> + ENTRY_POINT = SmmSwDispatch2ThunkMain
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +[Sources]
> + SmmSwDispatch2OnSmmSwDispatchThunk.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> +
> +[LibraryClasses]
> + UefiDriverEntryPoint
> + UefiBootServicesTableLib
> + SmmServicesTableLib
> + BaseLib
> + IoLib
> + DebugLib
> +
> +[Protocols]
> + gEfiSmmControlProtocolGuid # PROTOCOL ALWAYS_CONSUMED
> + gEfiSmmSwDispatchProtocolGuid # PROTOCOL ALWAYS_CONSUMED
> + gEfiSmmCpuProtocolGuid # PROTOCOL ALWAYS_CONSUMED
> + gEfiSmmSwDispatch2ProtocolGuid # PROTOCOL ALWAYS_PRODUCED
> +
> +[Depex]
> + gEfiSmmSwDispatchProtocolGuid AND
> + gEfiSmmControlProtocolGuid AND
> + gEfiSmmCpuProtocolGuid
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSav
> eInfoHandlerSmm.c
> b/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSa
> veInfoHandlerSmm.c
> new file mode 100644
> index 0000000000..de257b35b5
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSa
> veInfoHandlerSmm.c
> @@ -0,0 +1,164 @@
> +/** @file
> + A helper driver to save information to SMRAM after SMRR is enabled.
> +
> + This driver is for ECP platforms.
> +
> + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +**/
> +
> +#include <PiSmm.h>
> +#include <Library/DebugLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Library/SmmServicesTableLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/IoLib.h>
> +#include <Protocol/SmmSwDispatch.h>
> +#include <Protocol/SmmReadyToLock.h>
> +#include <Protocol/SmmControl.h>
> +#include <Guid/Vlv2DeviceRefCodePkgTokenSpace.h>
> +
> +#define SMM_FROM_SMBASE_DRIVER 0x55
> +#define SMM_FROM_CPU_DRIVER_SAVE_INFO 0x81
> +
> +#define EFI_SMRAM_CPU_NVS_HEADER_GUID \
> + { \
> + 0x429501d9, 0xe447, 0x40f4, 0x86, 0x7b, 0x75, 0xc9, 0x3a, 0x1d, 0xb5,
> 0x4e \
> + }
> +
> +UINT8 mSmiDataRegister;
> +BOOLEAN mLocked = FALSE;
> +EFI_GUID mSmramCpuNvsHeaderGuid =
> EFI_SMRAM_CPU_NVS_HEADER_GUID;
> +
> +/**
> + Dispatch function for a Software SMI handler.
> +
> + @param DispatchHandle The handle of this dispatch function.
> + @param DispatchContext The pointer to the dispatch function's
> context.
> + The SwSmiInputValue field is filled in
> + by the software dispatch driver prior to
> + invoking this dispatch function.
> + The dispatch function will only be called
> + for input values for which it is registered.
> +
> + @return None
> +
> +**/
> +VOID
> +EFIAPI
> +SmramSaveInfoHandler (
> + IN EFI_HANDLE DispatchHandle,
> + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
> + )
> +{
> + ASSERT (DispatchContext != NULL);
> + ASSERT (DispatchContext->SwSmiInputValue ==
> SMM_FROM_SMBASE_DRIVER);
> +
> + if (!mLocked && IoRead8 (mSmiDataRegister) ==
> SMM_FROM_CPU_DRIVER_SAVE_INFO) {
> + CopyMem (
> + (VOID *)(UINTN)(PcdGetEx64 (&gEfiVLVTokenSpaceGuid,
> PcdCpuLockBoxDataAddress)),
> + (VOID *)(UINTN)(PcdGetEx64 (&gEfiVLVTokenSpaceGuid,
> PcdCpuSmramCpuDataAddress)),
> + (UINTN)(PcdGetEx64 (&gEfiVLVTokenSpaceGuid, PcdCpuLockBoxSize))
> + );
> + }
> +}
> +
> +/**
> + Smm Ready To Lock event notification handler.
> +
> + It sets a flag indicating that SMRAM has been locked.
> +
> + @param[in] Protocol Points to the protocol's unique identifier.
> + @param[in] Interface Points to the interface instance.
> + @param[in] Handle The handle on which the interface was installed.
> +
> + @retval EFI_SUCCESS Notification handler runs successfully.
> + **/
> +EFI_STATUS
> +EFIAPI
> +SmmReadyToLockEventNotify (
> + IN CONST EFI_GUID *Protocol,
> + IN VOID *Interface,
> + IN EFI_HANDLE Handle
> + )
> +{
> + mLocked = TRUE;
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Entry point function of this driver.
> +
> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
> + @param[in] SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The entry point is executed successfully.
> + @retval other Some error occurs when executing this entry point.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SmramSaveInfoHandlerSmmMain (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_SMM_SW_DISPATCH_PROTOCOL *SmmSwDispatch;
> + EFI_SMM_SW_DISPATCH_CONTEXT SmmSwDispatchContext;
> + EFI_HANDLE DispatchHandle;
> + EFI_SMM_CONTROL_PROTOCOL *SmmControl;
> + EFI_SMM_CONTROL_REGISTER SmmControlRegister;
> + VOID *Registration;
> +
> + //
> + // Get SMI data register
> + //
> + Status = SystemTable->BootServices->LocateProtocol (
> + &gEfiSmmControlProtocolGuid,
> + NULL,
> + (VOID **)&SmmControl
> + );
> + ASSERT_EFI_ERROR (Status);
> + Status = SmmControl->GetRegisterInfo (SmmControl,
> &SmmControlRegister);
> + ASSERT_EFI_ERROR (Status);
> + mSmiDataRegister = SmmControlRegister.SmiDataRegister;
> +
> + //
> + // Register software SMI handler
> + //
> +
> + Status = SystemTable->BootServices->LocateProtocol (
> + &gEfiSmmSwDispatchProtocolGuid,
> + NULL,
> + (VOID **)&SmmSwDispatch
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + SmmSwDispatchContext.SwSmiInputValue =
> SMM_FROM_SMBASE_DRIVER;
> + Status = SmmSwDispatch->Register (
> + SmmSwDispatch,
> + &SmramSaveInfoHandler,
> + &SmmSwDispatchContext,
> + &DispatchHandle
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Register SMM Ready To Lock Protocol notification
> + //
> + Status = gSmst->SmmRegisterProtocolNotify (
> + &gEfiSmmReadyToLockProtocolGuid,
> + SmmReadyToLockEventNotify,
> + &Registration
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSav
> eInfoHandlerSmm.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSa
> veInfoHandlerSmm.inf
> new file mode 100644
> index 0000000000..ec42c84472
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSa
> veInfoHandlerSmm.inf
> @@ -0,0 +1,60 @@
> +## @file
> +#
> +# A helper driver to save information to SMRAM after SMRR is enabled.
> +#
> +# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SmramSaveInfoHandlerSmm
> + FILE_GUID = 63296C52-01CF-4eea-A47C-782A14DA6894
> + MODULE_TYPE = DXE_SMM_DRIVER
> + VERSION_STRING = 1.0
> + PI_SPECIFICATION_VERSION = 0x0001000A
> +
> + ENTRY_POINT = SmramSaveInfoHandlerSmmMain
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +[Sources.common]
> + SmramSaveInfoHandlerSmm.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> +
> +[LibraryClasses]
> + UefiDriverEntryPoint
> + UefiRuntimeServicesTableLib
> + SmmServicesTableLib
> + BaseLib
> + BaseMemoryLib
> + IoLib
> +
> +[Protocols]
> + gEfiSmmSwDispatchProtocolGuid ## CONSUMED
> + gEfiSmmControlProtocolGuid ## CONSUMED
> + gEfiSmmReadyToLockProtocolGuid ## CONSUMED
> +
> +[Pcd.common]
> + gEfiVLVTokenSpaceGuid.PcdCpuLockBoxDataAddress
> + gEfiVLVTokenSpaceGuid.PcdCpuSmramCpuDataAddress
> + gEfiVLVTokenSpaceGuid.PcdCpuLockBoxSize
> +
> +[Depex]
> + gEfiSmmSwDispatchProtocolGuid AND
> + gEfiSmmControlProtocolGuid
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwSpare.bin
> b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwSpare.bin
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..7145947da44cf9920d9c593318
> 7dc96540ecd5ad
> GIT binary patch
> literal 262144
> zcmeIuF#!Mo0K%aDspoA6h(KY$fB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0
> RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
> Fkrxd
> z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
> 3>YwA
> zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
> 0|pEj
> zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKf
> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
> %*VK
> zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
> 1`HT5
> zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
> 0RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
> Fkrxd
> z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
> 3>YwA
> zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
> 0|pEj
> zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKf
> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
> %*VK
> zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
> 1`HT5
> zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
> 0RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
> Fkrxd
> z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
> 3>YwA
> Wz<>b*1`HT5V8DO at 0|pEj_<;c*e>=qh
>
> literal 0
> HcmV?d00001
>
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwWorking.bin
> b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwWorking.bin
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..dcb92498b93463a07d6dd695c
> f30ae9320414671
> GIT binary patch
> literal 8192
> zcmeIuu?;{_6hP6R7(<~Jr73J+0f`|PLyL*bAV$#hh$$53R<}M?+0OkiHtW`<Yssg
> h
> xKC?R__9A_~D*^-v5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAVA>f0uR>?&<Owl
>
> literal 0
> HcmV?d00001
>
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageVariable.bin
> b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageVariable.bin
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..7f8688b099f1e70491f16161a9
> 8c7b53c6b7a412
> GIT binary patch
> literal 253952
> zcmeI%O^8iV902hDdt-
> csBz8*8MwpQ%hEhIe#*B&i$RPO$VW}uzu_4JqQj&ZwrdW)P
> z5+x-IiKJ}A!oo+{Ai{p0^WKcd=;4Ktn%{Zd-
> g)Pq`#<OW?(M$r{YUgKN2h(ro!oU~
> zY4 at SY&BNBTcSH;?bXecCa&fL_NGy)2BT_ at Qw>48dcu)1GOZ!foY3SNNeSF*
> P-N&y#
> ztBBP-
> y}K{1m>(6zo~0|(Q}c#wMDyemXWJ%BX}wT)YkS<gHn$}@VrHz5hG>trXo{9-
> zj at tCQCDoUu@3vSOjj=G6r%fR+umZVUIoEP^n#7!;5yQIPWuKlJv*6T>rjZlspP
> bHL
> z%XQyf%dX^sJ!7I1AV6TS2$b{xG&W(Z8WnMOcGc!bvuc_TZW;Id!N<K-
> ^|3X58e?PZ
> zNSi`{009C72oNAZfB=C%7bxc$WlS2TI=wW0v8iU#&7Qlh=kDB?Hu3$rHBGU_6
> Uv{T
> z0uctAK&HHR*R{!IbJ{L;TwZtJ^~=^{XYb$aez<mgXDmuNm=!7KvMB0PE~Y(YT
> >58a
> z^8506n3h7OW&n7<CYy at E%Ue@=)e+~@y`<ss;kOswTwBuhYW}>sE2FzR)4g
> Oz?2K*2
> zc)zNYn8L3PDY^e|#VHy5A2pU<LrUQlOTI_xUd1l|NhR~cd1kI=Dr at 6j>hQDG^
> z9y~
> z)%1>?$qX-
> 45^7(GY&M&pSeja)B|m=tR{^~!pYPDymZ|*G`0Z)>omr<iUo*ND#Q}%(
> z#qXQK??f(jOim#{fB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
> z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs
> z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
> zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&U
> zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5FkK+009C7
> z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N
> z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5FkK+
> z009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
> zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF
> z5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
> z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs
> z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
> zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&U
> zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5FkK+009C7
> z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N
> z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5FkK+
> z009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
> zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF
> z5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
> z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs
> x0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-
> N0t5&UAV7cs0RjXF5Ev{1p8>TuLd5_8
>
> literal 0
> HcmV?d00001
>
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER.bin
> b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER.bin
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..ca10f7af61b91e1daf79e374c6
> c837ee06e6ea4c
> GIT binary patch
> literal 4096
> zcmezW9~DF`{lL%6z{14FB*3k}pva)gz`%g4LWMy9C;|Z>aWISJKRYACe`XN-
> zdWjX
> z5D!%Z*|dRYLwo`xSy+LDfCL}I0!K!u;9+(KhQmN#xdZtiJn*g^b-`!|jE2By2#kin
> zXb6mkz-S1JhQMeDjE2By2oN6vhZMvZSQS_m-
> a9~P11Oy!4i;B{%R~6`9t;ek3Ze=M
> WyCHnyZ5sS4?*qHCgWr|3bs+!{&RygH
>
> literal 0
> HcmV?d00001
>
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER_SPIL
> OCK.bin
> b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER_SPIL
> OCK.bin
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..f2dcb0067d1a48f08b4c404836
> 2443b5c7095aa9
> GIT binary patch
> literal 4096
> zcmezW9~DF`{lL%6z{14FB*3k}pva)gz`%g4LWMy9C;|Z>aWISJKRYACe`XN-
> zdWjX
> zAWsTa1lhEKXG44fBw1L2gn$Ge!vaS}sNi9C28P2xU%3PMAUyD{9d*HI2#kinX
> b6mk
> zz-
> S1JhQMeDjE2By2#kinXb2D=0*4gD7+4ip72Z2QX#*&oAPyE+fXhSp@*WHfq6(
> r4
> X3cDeE;%yrID(?fkvV-51v~?i>7>iv0
>
> literal 0
> HcmV?d00001
>
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/Vacant.bin
> b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIHeader/Vacant.bin
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..12d359146014baad9277a951b
> 237fd27e819db6e
> GIT binary patch
> literal 3928064
> zcmeIuF#!Mo0K%aDspo45h(KY$fB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0
> RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
> Fkrxd
> z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
> 3>YwA
> zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
> 0|pEj
> zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKf
> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
> %*VK
> zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
> 1`HT5
> zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
> 0RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
> Fkrxd
> z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
> 3>YwA
> zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
> 0|pEj
> zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKf
> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
> %*VK
> zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
> 1`HT5
> zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
> 0RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
> Fkrxd
> z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
> 3>YwA
> zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
> 0|pEj
> zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKf
> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
> %*VK
> zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
> 1`HT5
> zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
> 0RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
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> Fkrxd
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> B^#r
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> V8DO@
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> %*VK
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> 1`HT5
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> B^#r
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> B^#r
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> V8DO@
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> B^#r
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> V8DO@
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> %*VK
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> B^#r
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> V8DO@
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> %*VK
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> 1`HT5
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> 0|pEj
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> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
> %*VK
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> 1`HT5
> zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
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> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
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> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
> %*VK
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> 1`HT5
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> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
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> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
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> B^#r
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> V8DO@
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> 1`HT5
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> B^#r
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> B^#r
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> B^#r
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> B^#r
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> B^#r
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> zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
> 0RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
> Fkrxd
> z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
> 3>YwA
> zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
> 0|pEj
> zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKf
> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
> %*VK
> zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
> 1`HT5
> zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
> 0RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
> Fkrxd
> z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
> 3>YwA
> zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
> 0|pEj
> zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKf
> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
> %*VK
> zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
> 1`HT5
> zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
> 0RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
> Fkrxd
> z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
> 3>YwA
> zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
> 0|pEj
> zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKf
> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
> %*VK
> zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
> 1`HT5
> zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
> 0RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
> Fkrxd
> z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
> 3>YwA
> zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
> 0|pEj
> zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKf
> B^#r
> z3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5
> V8DO@
> z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7
> %*VK
> zfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*
> 1`HT5
> zV8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd
> 0RsjM
> z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA
> z<>b*
> z1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEj
> Fkrxd
> z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r
> 3>YwA
> zz<>b*1`HT5V8DO at 0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@
> 0|pEj
> rFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO at 0|pEjFz^EdVf>G}
>
> literal 0
> HcmV?d00001
>
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat
> b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat
> new file mode 100644
> index 0000000000..200ca05a23
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat
> @@ -0,0 +1,270 @@
> + at REM @file
> + at REM Windows batch file to build BIOS ROM
> + at REM
> + at REM Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> + at REM
> + at REM SPDX-License-Identifier: BSD-2-Clause-Patent
> + at REM
> +
> + at echo off
> +SetLocal EnableDelayedExpansion EnableExtensions
> +
> +set PLATFORM_BIN_PACKAGE=%WORKSPACE%\Vlv2SocBinPkg
> +if not exist %PLATFORM_BIN_PACKAGE% (
> + if defined PACKAGES_PATH (
> + for %%i IN (%PACKAGES_PATH%) DO (
> + if exist %%~fi\Vlv2SocBinPkg (
> + set PLATFORM_BIN_PACKAGE=%%~fi\Vlv2SocBinPkg
> + goto PlatformBinPackageFound
> + )
> + )
> + ) else (
> + echo.
> + echo !!! ERROR !!! Cannot find %PLATFORM_NAME% !!!
> + echo.
> + goto BldFail
> + )
> +)
> +:PlatformBinPackageFound
> +
> +
> +:: Set script defaults
> +set exitCode=0
> +set BackupRom=1
> +set UpdateVBios=1
> +set SpiLock=0
> +set Stitch_Config=Stitch_Config.txt
> +copy /y nul Stitching.log >nul
> +
> +:: Set default Suffix as: YYYY_MM_DD_HHMM
> +set hour=%time: =0%
> +reg copy "HKCU\Control Panel\International" "HKCU\Control
> Panel\International_Temp" /f >nul
> +reg add "HKCU\Control Panel\International" /v sShortDate /d
> "yyyy_MM_dd" /f >nul
> +for /f "tokens=1" %%i in ("%date%") do set today=%%i
> +reg copy "HKCU\Control Panel\International_Temp" "HKCU\Control
> Panel\International" /f >nul
> +reg delete "HKCU\Control Panel\International_Temp" /f >nul
> +set IFWI_Suffix=%today%_%hour:~0,2%%time:~3,2%
> +
> +:: Process input arguments
> +if "%~1"=="?" goto Usage
> +if "%~1"=="/?" goto Usage
> +if /i "%~1"=="Help" goto Usage
> +
> +:OptLoop
> +if /i "%~1"=="/nV" (
> + set UpdateVBios=0
> + shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/nB" (
> + set BackupRom=0
> + shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/yL" (
> + set SpiLock=1
> + shift
> + goto OptLoop
> +)
> +
> +if /i "%~1"=="/B" (
> + if "%~2"=="" goto Usage
> + if not exist %~2 echo BIOS not found. & goto Usage
> + set BIOS_Names=%~2
> + set BIOS_File_Name=%~n2
> + shift & shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/C" (
> + if "%~2"=="" goto Usage
> + if not exist %~2 echo ConfigFile not found. & goto Usage
> + set Stitch_Config=%~2
> + shift & shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/S" (
> + if "%~2"=="" goto Usage
> + set IFWI_Suffix=%~2
> + shift & shift
> + goto OptLoop
> +)
> +
> +if "%BIOS_File_Name:~0,4%"=="MNW2" (
> + set Stitch_Config= MNW2_Stitch_Config.txt
> +)
> +if "%BIOS_File_Name:~3,4%"=="MNW2" (
> + set Stitch_Config= MNW2_Stitch_Config.txt
> +)
> +
> +:: if no rom specified by user, search in ./ for ROM files
> +if "%BIOS_Names%"=="" (
> + set "BIOS_Names= "
> + for /f "tokens=*" %%i in ('dir /b *.rom') do set
> BIOS_Names=!BIOS_Names! %%i
> + if "!BIOS_Names!"==" " (
> + echo NO .ROM files found !!!
> + goto Usage
> + )
> +)
> +
> +:: Parse the Stitch_Config File
> +if not exist %Stitch_Config% (
> + echo Stitch Configuration File %Stitch_Config% not found.
> + goto ScriptFail
> +)
> +for /f "delims== tokens=1,2" %%i in (%Stitch_Config%) do (
> + if /i "%%i"=="HEADER" set IFWI_HEADER=%%j
> + if /i "%%i"=="SEC_VERSION" set SEC_VERSION=%%j
> + if /i "%%i"=="Source" (
> + if /i "%%j"=="ALPHA" set Source_Prefix=A_
> + if /i "%%j"=="BF" set Source_Prefix=BF_
> + if /i "%%j"=="BE" set Source_Prefix=BE_
> + if /i "%%j"=="PV" set Source_Prefix=PV_
> + if /i "%%j"=="PR1" set Source_Prefix=PR1_
> + )
> +)
> +
> +if %SpiLock% EQU 1 (
> + set IFWI_HEADER_FILE=IFWIHeader\!IFWI_HEADER!_SPILOCK.bin
> +) else (
> + set IFWI_HEADER_FILE=IFWIHeader\!IFWI_HEADER!.bin
> +)
> +
> +::
> **********************************************************
> ************
> +:: The Main Stitching Loop
> +::
> **********************************************************
> ************
> +echo %date% %time% >>Stitching.log 2>&1
> +echo %date% %time%
> +echo.
> +for %%i in (%BIOS_Names%) do (
> +
> + REM ----- Do NOT use :: for comments Inside of code blocks() -------
> + set BIOS_Rom=%%i
> + set BIOS_Name=%%~ni
> + set BIOS_Version=!BIOS_Name:~-7,7!
> +
> + REM extract PlatformType from BIOS filename
> + set Platform_Type=!BIOS_Name:~0,4!
> +
> + REM Special treat for BayLake FFD8
> + set Temp_Name=!BIOS_Name:~0,7!
> +
> +
> + REM Capitalize and validate the Platform_Type
> + if /i "!Platform_Type!"=="MNW2" (
> + set Platform_Type=MNW2
> + ) else (
> + echo Error - Unsupported PlatformType: !Platform_Type!
> + goto Usage
> + )
> +
> +
> + REM search BIOS_Name for Arch substring: either IA32 or X64
> + if not "!BIOS_Name!"=="!BIOS_Name:_IA32_=!" (
> + set Arch=IA32
> + ) else if not "!BIOS_Name!"=="!BIOS_Name:_X64_=!" (
> + set Arch=X64
> + ) else (
> + echo Error: Could not determine Architecture for !BIOS_Rom!
> + goto Usage
> + )
> + set
> IFWI_Prefix=!Platform_Type!_IFWI_%Source_Prefix%!Arch!_!!BIOS_Versio
> n!
> +
> + REM search BIOS_Name for Build_Target substring: either R or D
> + if not "!BIOS_Name!"=="!BIOS_Name:_R_=!" (
> + set Build_Target=Release
> + set IFWI_Prefix=!IFWI_Prefix!_R
> + ) else if not "!BIOS_Name!"=="!BIOS_Name:_D_=!" (
> + set Build_Target=Debug
> + set IFWI_Prefix=!IFWI_Prefix!_D
> + ) else (
> + echo Error: Could not determine Build Target for !BIOS_Rom!
> + goto Usage
> + )
> +
> + REM Create a BIOS backup before Stitching
> + if %BackupRom% EQU 1 (
> + echo Creating backup of original BIOS rom.
> + copy /y !BIOS_Rom! !BIOS_Rom!.orig >nul
> + )
> +
> + echo. >>Stitching.log
> + echo ********** Stitching !BIOS_Rom! ********** >>Stitching.log
> + echo. >>Stitching.log
> + echo.
> + echo Stitching IFWI for !BIOS_Rom! ...
> + echo ---------------------------------------------------------------------------
> + echo IFWI Header: !IFWI_HEADER_FILE!, SEC version: !SEC_VERSION!,
> + echo BIOS Version: !BIOS_Version!
> +
> + echo Platform Type: !Platform_Type!, IFWI Prefix: %BIOS_ID%
> + echo ---------------------------------------------------------------------------
> +
> + echo -----------------------------
> + echo.
> + echo Generating IFWI... %BIOS_ID%.bin
> + echo.
> +
> + copy /b/y !IFWI_HEADER_FILE!
> + %PLATFORM_BIN_PACKAGE%\SEC\!SEC_VERSION!\VLV_SEC_REGION.bin
> + %PLATFORM_BIN_PACKAGE%\SEC\!SEC_VERSION!\Vacant.bin
> + !BIOS_Rom! %BIOS_ID%.bin
> + echo.
> + echo
> ==========================================================
> =================
> +)
> + at echo off
> +
> +::********************************************************
> **************
> +:: end of main loop
> +::********************************************************
> **************
> +
> +echo.
> +echo -- All specified ROM files Stitched. --
> +echo.
> +goto Exit
> +
> +:Usage
> +echo.
> +echo
> **********************************************************
> ****************************************
> +echo This Script is used to Stitch together BIOS, GOP Driver, Microcode
> Patch and TXE FW
> +echo into a single Integrated Firmware Image (IFWI).
> +echo.
> +echo Usage: IFWIStitch.bat [flags] [/B BIOS.ROM] [/C Stitch_Config] [/S
> IFWI_Suffix]
> +echo.
> +echo This script has NO Required arguments, so that the user can just
> double click from the GUI.
> +echo However, this requires that the BIOS.ROM file name is formatted
> correctly.
> +echo.
> +echo /nG Do NOT update the GOP driver. (applies to all ROM files
> for this run)
> +echo /nV Do NOT update the VBIOS. (applies to all ROM files for
> this run)
> +echo /nM Do NOT update the Microcode. (applies to all ROM files
> for this run)
> +echo /nB Do NOT backup BIOS.ROMs. (Default will backup to
> BIOS.ROM.Orig)
> +echo.
> +echo BIOS.ROM: A single BIOS ROM file to use for stitching
> +echo (DEFAULT: ALL .ROM files inside the current directory)
> +echo Stitch_Config: Text file containing version info of each FW
> component
> +echo (DEFAULT: Stitch_Config.txt)
> +echo IFWI_Suffix: Suffix to append to the end of the IFWI filename
> +echo (DEFAULT: YYYY_MM_DD_HHMM)
> +echo.
> +echo Examples:
> +echo IFIWStitch.bat : Stitch all ROMs with defaults
> +echo IFIWStitch.bat /B C:/MyRoms/testBIOS.rom : Stitch single ROM
> with defaults
> +echo IFIWStitch.bat /B ../testBIOS.rom /S test123 : Stitch single ROM
> and add custom suffix
> +echo IFIWStitch.bat /nM /nB /B testBIOS.rom /S test456 : Stitch single
> ROM, keep uCode from .rom,
> +echo don't create backup, and add custom
> suffix.
> +echo
> **********************************************************
> ******************************************
> +pause
> +exit /b 1
> +
> +:ScriptFail
> +set exitCode=1
> +
> +:Exit
> +echo -- See Stitching.log for more info. --
> +echo.
> +echo %date% %time%
> +echo.
> +if "%Platform_Type%"=="MNW2" (
> + echo .
> +) else (
> + echo only support MNW2 for this project!
> +pause
> +)
> +exit /b %exitCode%
> +EndLocal
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt
> b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt
> new file mode 100644
> index 0000000000..82abe6548f
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt
> @@ -0,0 +1,10 @@
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +HEADER=IFWI_HEADER
> +SEC_VERSION=1.0.2.1060v5
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/UiApp/FrontPage.c
> b/Platform/Intel/Vlv2TbltDevicePkg/UiApp/FrontPage.c
> new file mode 100644
> index 0000000000..3e58a6d22a
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/UiApp/FrontPage.c
> @@ -0,0 +1,33 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +
> +**/
> +
> +/**
> + The user Entry Point for Application. The user code starts with this function
> + as the real entry point for the image goes into a library that calls this
> + function.
> +
> + @param[in] ImageHandle The firmware allocated handle for the EFI
> image.
> + @param[in] SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The entry point is executed successfully.
> + @retval other Some error occurs when executing this entry point.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeUserInterface (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/UiApp/UiApp.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/UiApp/UiApp.inf
> new file mode 100644
> index 0000000000..f7a0a83b80
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/UiApp/UiApp.inf
> @@ -0,0 +1,32 @@
> +#
> +#
> +# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = UiApp
> + FILE_GUID = 462CAA21-7614-4503-836E-8AB6F4662331
> + MODULE_TYPE = UEFI_APPLICATION
> + VERSION_STRING = 1.0
> + ENTRY_POINT = InitializeUserInterface
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 EBC
> +#
> +
> +[Sources]
> + FrontPage.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> + UefiApplicationEntryPoint
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.c
> b/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.c
> new file mode 100644
> index 0000000000..ba81bd9def
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.c
> @@ -0,0 +1,929 @@
> +
> +/*++
> +
> +Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + IgdOpRegion.c
> +
> +Abstract:
> +
> + This is part of the implementation of an Intel Graphics drivers OpRegion /
> + Software SCI interface between system BIOS, ASL code, and Graphics
> drivers.
> + The code in this file will load the driver and initialize the interface
> +
> + Supporting Specifiction: OpRegion / Software SCI SPEC 0.70
> +
> + Acronyms:
> + IGD: Internal Graphics Device
> + NVS: ACPI Non Volatile Storage
> + OpRegion: ACPI Operational Region
> + VBT: Video BIOS Table (OEM customizable data)
> +
> +--*/
> +
> +//
> +// Include files
> +//
> +
> +
> +#include "IgdOpRegion.h"
> +#include "VlvPlatformInit.h"
> +#include <FrameworkDxe.h>
> +#include <Uefi.h>
> +#include <PchRegs.h>
> +
> +#include <Guid/DataHubRecords.h>
> +
> +#include <Protocol/IgdOpRegion.h>
> +#include <Protocol/FrameworkHii.h>
> +#include <Protocol/FirmwareVolume2.h>
> +#include <Protocol/PlatformGopPolicy.h>
> +#include <Protocol/PciIo.h>
> +#include <Protocol/CpuIo.h>
> +#include <Protocol/GlobalNvsArea.h>
> +#include <Protocol/DxeSmmReadyToLock.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/S3BootScriptLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Protocol/DriverBinding.h>
> +#include <Library/PrintLib.h>
> +#include <Library/BaseMemoryLib.h>
> +
> +
> +
> +UINT8 gSVER[12] = "Intel";
> +
> +extern DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy;
> +
> +//
> +// Global variables
> +//
> +
> +IGD_OPREGION_PROTOCOL mIgdOpRegion;
> +EFI_GUID mMiscSubClass = EFI_MISC_SUBCLASS_GUID;
> +EFI_EVENT mConOutEvent;
> +EFI_EVENT mSetGOPverEvent;
> +VOID *mConOutReg;
> +
> +#define DEFAULT_FORM_BUFFER_SIZE 0xFFFF
> +#ifndef ECP_FLAG
> +#if 0
> +/**
> +
> + Get the HII protocol interface
> +
> + @param Hii HII protocol interface
> +
> + @retval Status code
> +
> +**/
> +static
> +EFI_STATUS
> +GetHiiInterface (
> + OUT EFI_HII_PROTOCOL **Hii
> + )
> +{
> + EFI_STATUS Status;
> +
> + //
> + // There should only be one HII protocol
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiHiiProtocolGuid,
> + NULL,
> + (VOID **) Hii
> + );
> +
> + return Status;;
> +}
> +#endif
> +#endif
> +
> +/**
> +
> + Get VBT data.
> +
> + @param[in] VbtFileBuffer Pointer to VBT data buffer.
> +
> + @retval EFI_SUCCESS VBT data was returned.
> + @retval EFI_NOT_FOUND VBT data not found.
> + @exception EFI_UNSUPPORTED Invalid signature in VBT data.
> +
> +**/
> +EFI_STATUS
> +GetIntegratedIntelVbtPtr (
> + OUT VBIOS_VBT_STRUCTURE **VbtFileBuffer
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PHYSICAL_ADDRESS VbtAddress = 0;
> + UINTN FvProtocolCount;
> + EFI_HANDLE *FvHandles;
> + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
> + UINTN Index;
> + UINT32 AuthenticationStatus;
> +
> + UINT8 *Buffer;
> + UINTN VbtBufferSize = 0;
> +
> + Buffer = 0;
> + FvHandles = NULL;
> + *VbtFileBuffer = NULL;
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiFirmwareVolume2ProtocolGuid,
> + NULL,
> + &FvProtocolCount,
> + &FvHandles
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + for (Index = 0; Index < FvProtocolCount; Index++) {
> + Status = gBS->HandleProtocol (
> + FvHandles[Index],
> + &gEfiFirmwareVolume2ProtocolGuid,
> + (VOID **) &Fv
> + );
> + VbtBufferSize = 0;
> + Status = Fv->ReadSection (
> + Fv,
> + &gBmpImageGuid,
> + EFI_SECTION_RAW,
> + 0,
> + (void **)&Buffer,
> + &VbtBufferSize,
> + &AuthenticationStatus
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
> + Status = EFI_SUCCESS;
> + break;
> + }
> + }
> + } else {
> + Status = EFI_NOT_FOUND;
> + }
> +
> + if (FvHandles != NULL) {
> + FreePool(FvHandles);
> + FvHandles = NULL;
> + }
> +
> +
> + //
> + // Check VBT signature
> + //
> + *VbtFileBuffer = (VBIOS_VBT_STRUCTURE *) (UINTN) VbtAddress;
> + if (*VbtFileBuffer != NULL) {
> + if ((*((UINT32 *) ((*VbtFileBuffer)->HeaderSignature))) !=
> VBT_SIGNATURE) {
> + if (*VbtFileBuffer != NULL) {
> + *VbtFileBuffer = NULL;
> + }
> + return EFI_UNSUPPORTED;
> + }
> + //
> + // Check VBT size
> + //
> + if ((*VbtFileBuffer)->HeaderVbtSize > VbtBufferSize) {
> + (*VbtFileBuffer)->HeaderVbtSize = (UINT16) VbtBufferSize;
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +//
> +// Function implementations.
> +//
> +/**
> +
> + Get a pointer to an uncompressed image of the Intel video BIOS.
> +
> + Note: This function would only be called if the video BIOS at 0xC000 is
> + missing or not an Intel video BIOS. It may not be an Intel video BIOS
> + if the Intel graphic contoller is considered a secondary adapter.
> +
> +
> + @param VBiosROMImage Pointer to an uncompressed Intel video BIOS.
> This pointer must
> + be set to NULL if an uncompressed image of the Intel Video
> BIOS
> + is not obtainable.
> +
> +
> + @retval EFI_SUCCESS VBiosPtr is updated.
> +
> +**/
> +EFI_STATUS
> +GetIntegratedIntelVBiosPtr (
> + INTEL_VBIOS_OPTION_ROM_HEADER **VBiosImage
> + )
> +{
> + EFI_HANDLE *HandleBuffer;
> + UINTN HandleCount;
> + UINTN Index;
> + INTEL_VBIOS_PCIR_STRUCTURE *PcirBlockPtr;
> + EFI_STATUS Status;
> + EFI_PCI_IO_PROTOCOL *PciIo;
> + INTEL_VBIOS_OPTION_ROM_HEADER *VBiosRomImage;
> +
> + //
> + // Set as if an umcompressed Intel video BIOS image was not obtainable.
> + //
> + VBiosRomImage = NULL;
> + *VBiosImage = NULL;
> +
> + //
> + // Get all PCI IO protocols
> + //
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + &gEfiPciIoProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Find the video BIOS by checking each PCI IO handle for an Intel video
> + // BIOS OPROM.
> + //
> + for (Index = 0; Index < HandleCount; Index++) {
> + Status = gBS->HandleProtocol (
> + HandleBuffer[Index],
> + &gEfiPciIoProtocolGuid,
> + (void **)&PciIo
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + VBiosRomImage = PciIo->RomImage;
> +
> + //
> + // If this PCI device doesn't have a ROM image, skip to the next device.
> + //
> + if (!VBiosRomImage) {
> + continue;
> + }
> +
> + //
> + // Get pointer to PCIR structure
> + //
> + PcirBlockPtr = (INTEL_VBIOS_PCIR_STRUCTURE *)((UINT8 *)
> VBiosRomImage + VBiosRomImage->PcirOffset);
> +
> + //
> + // Check if we have an Intel video BIOS OPROM.
> + //
> + if ((VBiosRomImage->Signature == OPTION_ROM_SIGNATURE) &&
> + (PcirBlockPtr->VendorId == IGD_VID) &&
> + (PcirBlockPtr->ClassCode[0] == 0x00) &&
> + (PcirBlockPtr->ClassCode[1] == 0x00) &&
> + (PcirBlockPtr->ClassCode[2] == 0x03)
> + ) {
> + //
> + // Found Intel video BIOS.
> + //
> + *VBiosImage = VBiosRomImage;
> + return EFI_SUCCESS;
> + }
> + }
> +
> + //
> + // No Intel video BIOS found.
> + //
> +
> + //
> + // Free any allocated buffers
> + //
> + return EFI_UNSUPPORTED;
> +}
> +
> +EFI_STATUS
> +SearchChildHandle(
> + EFI_HANDLE Father,
> + EFI_HANDLE *Child
> + )
> +{
> + EFI_STATUS Status;
> + UINTN HandleIndex;
> + EFI_GUID **ProtocolGuidArray = NULL;
> + UINTN ArrayCount;
> + UINTN ProtocolIndex;
> + UINTN OpenInfoCount;
> + UINTN OpenInfoIndex;
> + EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfo = NULL;
> + UINTN mHandleCount;
> + EFI_HANDLE *mHandleBuffer= NULL;
> +
> + //
> + // Retrieve the list of all handles from the handle database
> + //
> + Status = gBS->LocateHandleBuffer (
> + AllHandles,
> + NULL,
> + NULL,
> + &mHandleCount,
> + &mHandleBuffer
> + );
> +
> + for (HandleIndex = 0; HandleIndex < mHandleCount; HandleIndex++) {
> + //
> + // Retrieve the list of all the protocols on each handle
> + //
> + Status = gBS->ProtocolsPerHandle (
> + mHandleBuffer[HandleIndex],
> + &ProtocolGuidArray,
> + &ArrayCount
> + );
> + if (!EFI_ERROR (Status)) {
> + for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++) {
> + Status = gBS->OpenProtocolInformation (
> + mHandleBuffer[HandleIndex],
> + ProtocolGuidArray[ProtocolIndex],
> + &OpenInfo,
> + &OpenInfoCount
> + );
> + if (!EFI_ERROR (Status)) {
> + for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount;
> OpenInfoIndex++) {
> + if(OpenInfo[OpenInfoIndex].AgentHandle == Father) {
> + if ((OpenInfo[OpenInfoIndex].Attributes &
> EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) ==
> EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {
> + *Child = mHandleBuffer[HandleIndex];
> + Status = EFI_SUCCESS;
> + goto TryReturn;
> + }
> + }
> + }
> + Status = EFI_NOT_FOUND;
> + }
> + }
> + if(OpenInfo != NULL) {
> + FreePool(OpenInfo);
> + OpenInfo = NULL;
> + }
> + }
> + FreePool (ProtocolGuidArray);
> + ProtocolGuidArray = NULL;
> + }
> +TryReturn:
> + if(OpenInfo != NULL) {
> + FreePool (OpenInfo);
> + OpenInfo = NULL;
> + }
> + if(ProtocolGuidArray != NULL) {
> + FreePool(ProtocolGuidArray);
> + ProtocolGuidArray = NULL;
> + }
> + if(mHandleBuffer != NULL) {
> + FreePool (mHandleBuffer);
> + mHandleBuffer = NULL;
> + }
> + return Status;
> +}
> +
> +EFI_STATUS
> +JudgeHandleIsPCIDevice(
> + EFI_HANDLE Handle,
> + UINT8 Device,
> + UINT8 Funs
> + )
> +{
> + EFI_STATUS Status;
> + EFI_DEVICE_PATH *DPath;
> +
> + Status = gBS->HandleProtocol (
> + Handle,
> + &gEfiDevicePathProtocolGuid,
> + (VOID **) &DPath
> + );
> + if(!EFI_ERROR(Status)) {
> + while(!IsDevicePathEnd(DPath)) {
> + if((DPath->Type == HARDWARE_DEVICE_PATH) && (DPath->SubType ==
> HW_PCI_DP)) {
> + PCI_DEVICE_PATH *PCIPath;
> +
> + PCIPath = (PCI_DEVICE_PATH*) DPath;
> + DPath = NextDevicePathNode(DPath);
> + if(IsDevicePathEnd(DPath) && (PCIPath->Device == Device) &&
> (PCIPath->Function == Funs)) {
> + return EFI_SUCCESS;
> + }
> + } else {
> + DPath = NextDevicePathNode(DPath);
> + }
> + }
> + }
> + return EFI_UNSUPPORTED;
> +}
> +
> +EFI_STATUS
> +GetDriverName(
> + EFI_HANDLE Handle,
> + CHAR16 *GopVersion
> + )
> +{
> + EFI_DRIVER_BINDING_PROTOCOL *BindHandle = NULL;
> + EFI_STATUS Status;
> + UINT32 Version;
> + UINT16 *Ptr;
> +
> + Status = gBS->OpenProtocol(
> + Handle,
> + &gEfiDriverBindingProtocolGuid,
> + (VOID**)&BindHandle,
> + NULL,
> + NULL,
> + EFI_OPEN_PROTOCOL_GET_PROTOCOL
> + );
> + if (EFI_ERROR(Status)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + Version = BindHandle->Version;
> + Ptr = (UINT16*)&Version;
> + UnicodeSPrint(GopVersion, 40, L"7.0.%04d", *(Ptr));
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +GetGOPDriverVersion(
> + CHAR16 *GopVersion
> + )
> +{
> + UINTN HandleCount;
> + EFI_HANDLE *Handles= NULL;
> + UINTN Index;
> + EFI_STATUS Status;
> + EFI_HANDLE Child = 0;
> +
> + Status = gBS->LocateHandleBuffer(
> + ByProtocol,
> + &gEfiDriverBindingProtocolGuid,
> + NULL,
> + &HandleCount,
> + &Handles
> + );
> + for (Index = 0; Index < HandleCount ; Index++) {
> + Status = SearchChildHandle(Handles[Index], &Child);
> + if(!EFI_ERROR(Status)) {
> + Status = JudgeHandleIsPCIDevice(Child, 0x02, 0x00);
> + if(!EFI_ERROR(Status)) {
> + return GetDriverName(Handles[Index], GopVersion);
> + }
> + }
> + }
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +/**
> + Get Intel GOP driver version and copy it into IGD OpRegion GVER. This
> version
> + is picked up by IGD driver and displayed in CUI.
> +
> + @param Event A pointer to the Event that triggered the callback.
> + @param Context A pointer to private data registered with the
> callback function.
> +
> + @retval EFI_SUCCESS Video BIOS VBT information returned.
> + @retval EFI_UNSUPPORTED Could not find VBT information
> (*VBiosVbtPtr = NULL).
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SetGOPVersionCallback (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + CHAR16 GopVersion[16] = {0};
> + EFI_STATUS Status;
> +
> + Status = GetGOPDriverVersion(GopVersion);
> + if(!EFI_ERROR(Status)) {
> + StrCpy((CHAR16*)&(mIgdOpRegion.OpRegion->Header.GOPV[0]),
> GopVersion);
> + return Status;
> + }
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size).
> + The VBT (Video BIOS Table) is a block of customizable data that is built
> + within the video BIOS and edited by customers.
> +
> + @param Event A pointer to the Event that triggered the callback.
> + @param Context A pointer to private data registered with the
> callback function.
> +
> + @retval EFI_SUCCESS Video BIOS VBT information returned.
> + @retval EFI_UNSUPPORTED Could not find VBT information
> (*VBiosVbtPtr = NULL).
> +
> +**/
> +EFI_STATUS
> +GetVBiosVbtCallback (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + INTEL_VBIOS_PCIR_STRUCTURE *PcirBlockPtr;
> + UINT16 PciVenderId;
> + UINT16 PciDeviceId;
> + INTEL_VBIOS_OPTION_ROM_HEADER *VBiosPtr;
> + VBIOS_VBT_STRUCTURE *VBiosVbtPtr;
> + VBIOS_VBT_STRUCTURE *VbtFileBuffer = NULL;
> +
> + VBiosPtr = (INTEL_VBIOS_OPTION_ROM_HEADER
> *)(UINTN)(VBIOS_LOCATION_PRIMARY);
> + PcirBlockPtr = (INTEL_VBIOS_PCIR_STRUCTURE *)((UINT8 *)VBiosPtr +
> VBiosPtr->PcirOffset);
> + PciVenderId = PcirBlockPtr->VendorId;
> + PciDeviceId = PcirBlockPtr->DeviceId;
> +
> + //
> + // If the video BIOS is not at 0xC0000 or it is not an Intel video BIOS get
> + // the integrated Intel video BIOS (must be uncompressed).
> + //
> + if ((VBiosPtr->Signature != OPTION_ROM_SIGNATURE) || (PciVenderId !=
> IGD_VID) || (PciDeviceId != IGD_DID_VLV)) {
> + GetIntegratedIntelVBiosPtr (&VBiosPtr);
> +
> + if(VBiosPtr) {
> + //
> + // Video BIOS found.
> + //
> + PcirBlockPtr = (INTEL_VBIOS_PCIR_STRUCTURE *)((UINT8 *)VBiosPtr +
> VBiosPtr->PcirOffset);
> + PciVenderId = PcirBlockPtr->VendorId;
> + if( (VBiosPtr->Signature != OPTION_ROM_SIGNATURE) ||
> (PciVenderId != IGD_VID)) {
> + //
> + // Intel video BIOS not found.
> + //
> + VBiosVbtPtr = NULL;
> + return EFI_UNSUPPORTED;
> + }
> + } else {
> + //
> + // No Video BIOS found, try to get VBT from FV.
> + //
> + GetIntegratedIntelVbtPtr (&VbtFileBuffer);
> + if (VbtFileBuffer != NULL) {
> + //
> + // Video BIOS not found, use VBT from FV
> + //
> + DEBUG ((EFI_D_ERROR, "VBT data found\n"));
> + (gBS->CopyMem) (
> + mIgdOpRegion.OpRegion->VBT.GVD1,
> + VbtFileBuffer,
> + VbtFileBuffer->HeaderVbtSize
> + );
> + FreePool (VbtFileBuffer);
> + return EFI_SUCCESS;
> + }
> + }
> + if ((VBiosPtr == NULL) ) {
> + //
> + // Intel video BIOS not found.
> + //
> + VBiosVbtPtr = NULL;
> + return EFI_UNSUPPORTED;
> + }
> + }
> +
> + DEBUG ((EFI_D_ERROR, "VBIOS found at 0x%X\n", VBiosPtr));
> + VBiosVbtPtr = (VBIOS_VBT_STRUCTURE *) ((UINT8 *) VBiosPtr + VBiosPtr-
> >VbtOffset);
> +
> + if ((*((UINT32 *) (VBiosVbtPtr->HeaderSignature))) != VBT_SIGNATURE) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Initialize Video BIOS version with its build number.
> + //
> + mIgdOpRegion.OpRegion->Header.VVER[0] = VBiosVbtPtr-
> >CoreBlockBiosBuild[0];
> + mIgdOpRegion.OpRegion->Header.VVER[1] = VBiosVbtPtr-
> >CoreBlockBiosBuild[1];
> + mIgdOpRegion.OpRegion->Header.VVER[2] = VBiosVbtPtr-
> >CoreBlockBiosBuild[2];
> + mIgdOpRegion.OpRegion->Header.VVER[3] = VBiosVbtPtr-
> >CoreBlockBiosBuild[3];
> + (gBS->CopyMem) (
> + mIgdOpRegion.OpRegion->VBT.GVD1,
> + VBiosVbtPtr,
> + VBiosVbtPtr->HeaderVbtSize
> + );
> +
> + //
> + // Return final status
> + //
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Graphics OpRegion / Software SCI driver installation function.
> +
> + @param ImageHandle Handle for this drivers loaded image protocol.
> + @param SystemTable EFI system table.
> +
> + @retval EFI_SUCCESS The driver installed without error.
> + @retval EFI_ABORTED The driver encountered an error and could not
> complete
> + installation of the ACPI tables.
> +
> +**/
> +EFI_STATUS
> +IgdOpRegionInit (
> + void
> + )
> +{
> + EFI_HANDLE Handle;
> + EFI_STATUS Status;
> + EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
> + UINT32 DwordData;
> + EFI_CPU_IO_PROTOCOL *CpuIo;
> + UINT16 Data16;
> + UINT16 AcpiBase;
> + VOID *gConOutNotifyReg;
> +
> +
> + //
> + // Locate the Global NVS Protocol.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiGlobalNvsAreaProtocolGuid,
> + NULL,
> + (void **)&GlobalNvsArea
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Allocate an ACPI NVS memory buffer as the IGD OpRegion, zero initialize
> + // the first 1K, and set the IGD OpRegion pointer in the Global NVS
> + // area structure.
> + //
> + Status = (gBS->AllocatePool) (
> + EfiACPIMemoryNVS,
> + sizeof (IGD_OPREGION_STRUC),
> + (void **)&mIgdOpRegion.OpRegion
> + );
> + ASSERT_EFI_ERROR (Status);
> + (gBS->SetMem) (
> + mIgdOpRegion.OpRegion,
> + sizeof (IGD_OPREGION_STRUC),
> + 0
> + );
> + GlobalNvsArea->Area->IgdOpRegionAddress =
> (UINT32)(UINTN)(mIgdOpRegion.OpRegion);
> +
> + //
> + // If IGD is disabled return
> + //
> + if (IgdMmPci32 (0) == 0xFFFFFFFF) {
> + return EFI_SUCCESS;
> + }
> +
> + //
> + // Initialize OpRegion Header
> + //
> +
> + (gBS->CopyMem) (
> + mIgdOpRegion.OpRegion->Header.SIGN,
> + HEADER_SIGNATURE,
> + sizeof(HEADER_SIGNATURE)
> + );
> +
> +
> + //
> + // Set OpRegion Size in KBs
> + //
> + mIgdOpRegion.OpRegion->Header.SIZE = HEADER_SIZE/1024;
> +
> + //
> + // FIXME: Need to check Header OVER Field and the supported version.
> + //
> + mIgdOpRegion.OpRegion->Header.OVER = (UINT32) (LShiftU64
> (HEADER_OPREGION_VER, 16) + LShiftU64 (HEADER_OPREGION_REV, 8));
> +#ifdef ECP_FLAG
> + CopyMem(mIgdOpRegion.OpRegion->Header.SVER, gSVER,
> sizeof(gSVER));
> +#else
> + gBS->CopyMem(
> + mIgdOpRegion.OpRegion->Header.SVER,
> + gSVER,
> + sizeof(gSVER)
> + );
> +#endif
> + DEBUG ((EFI_D_ERROR, "System BIOS ID is %a\n",
> mIgdOpRegion.OpRegion->Header.SVER));
> +
> +
> + mIgdOpRegion.OpRegion->Header.MBOX = HEADER_MBOX_SUPPORT;
> +
> + if( 1 == DxePlatformSaPolicy->IdleReserve) {
> + mIgdOpRegion.OpRegion->Header.PCON = (mIgdOpRegion.OpRegion-
> >Header.PCON & 0xFFFC) | BIT1;
> + } else {
> + mIgdOpRegion.OpRegion->Header.PCON = (mIgdOpRegion.OpRegion-
> >Header.PCON & 0xFFFC) | (BIT1 | BIT0);
> + }
> +
> + //
> + //For graphics driver to identify if LPE Audio/HD Audio is enabled on the
> platform
> + //
> + mIgdOpRegion.OpRegion->Header.PCON &=
> AUDIO_TYPE_SUPPORT_MASK;
> + mIgdOpRegion.OpRegion->Header.PCON &= AUDIO_TYPE_FIELD_MASK;
> + if ( 1 == DxePlatformSaPolicy->AudioTypeSupport ) {
> + mIgdOpRegion.OpRegion->Header.PCON = HD_AUDIO_SUPPORT;
> + mIgdOpRegion.OpRegion->Header.PCON |= AUDIO_TYPE_FIELD_VALID;
> + }
> +
> + //
> + // Initialize OpRegion Mailbox 1 (Public ACPI Methods).
> + //
> + //<TODO> The initial setting of mailbox 1 fields is implementation specific.
> + // Adjust them as needed many even coming from user setting in setup.
> + //
> + //Workaround to solve LVDS is off after entering OS in desktop platform
> + //
> + mIgdOpRegion.OpRegion->MBox1.CLID = DxePlatformSaPolicy-
> >IgdPanelFeatures.LidStatus;
> +
> + //
> + // Initialize OpRegion Mailbox 3 (ASLE Interrupt and Power Conservation).
> + //
> + //<TODO> The initial setting of mailbox 3 fields is implementation specific.
> + // Adjust them as needed many even coming from user setting in setup.
> + //
> +
> + //
> + // Do not initialize TCHE. This field is written by the graphics driver only.
> + //
> +
> + //
> + // The ALSI field is generally initialized by ASL code by reading the
> embedded controller.
> + //
> +
> + mIgdOpRegion.OpRegion->MBox3.BCLP = BACKLIGHT_BRIGHTNESS;
> +
> + mIgdOpRegion.OpRegion->MBox3.PFIT = (FIELD_VALID_BIT |
> PFIT_STRETCH);
> + if ( DxePlatformSaPolicy->IgdPanelFeatures.PFITStatus == 2) {
> + //
> + // Center
> + //
> + mIgdOpRegion.OpRegion->MBox3.PFIT = (FIELD_VALID_BIT |
> PFIT_CENTER);
> + } else if (DxePlatformSaPolicy->IgdPanelFeatures.PFITStatus == 1) {
> + //
> + // Stretch
> + //
> + mIgdOpRegion.OpRegion->MBox3.PFIT = (FIELD_VALID_BIT |
> PFIT_STRETCH);
> + } else {
> + //
> + // Auto
> + //
> + mIgdOpRegion.OpRegion->MBox3.PFIT = (FIELD_VALID_BIT |
> PFIT_SETUP_AUTO);
> + }
> +
> + //
> + // Set Initial current Brightness
> + //
> + mIgdOpRegion.OpRegion->MBox3.CBLV = (INIT_BRIGHT_LEVEL |
> FIELD_VALID_BIT);
> +
> + //
> + // <EXAMPLE> Create a static Backlight Brightness Level Duty cycle
> Mapping Table
> + // Possible 20 entries (example used 10), each 16 bits as follows:
> + // [15] = Field Valid bit, [14:08] = Level in Percentage (0-64h), [07:00] =
> Desired duty cycle (0 - FFh).
> + //
> + // % Brightness
> + mIgdOpRegion.OpRegion->MBox3.BCLM[0] = ( ( 0 << 8 ) + ( 0xFF - 0xFC )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[1] = ( ( 1 << 8 ) + ( 0xFF - 0xFC )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[2] = ( ( 10 << 8 ) + ( 0xFF - 0xE5 )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[3] = ( ( 19 << 8 ) + ( 0xFF - 0xCE )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[4] = ( ( 28 << 8 ) + ( 0xFF - 0xB7 )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[5] = ( ( 37 << 8 ) + ( 0xFF - 0xA0 )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[6] = ( ( 46 << 8 ) + ( 0xFF - 0x89 )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[7] = ( ( 55 << 8 ) + ( 0xFF - 0x72 )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[8] = ( ( 64 << 8 ) + ( 0xFF - 0x5B )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[9] = ( ( 73 << 8 ) + ( 0xFF - 0x44 )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[10] = ( ( 82 << 8 ) + ( 0xFF - 0x2D )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[11] = ( ( 91 << 8 ) + ( 0xFF - 0x16 )
> + WORD_FIELD_VALID_BIT);
> + mIgdOpRegion.OpRegion->MBox3.BCLM[12] = ( (100 << 8 ) + ( 0xFF - 0x00 )
> + WORD_FIELD_VALID_BIT);
> +
> + mIgdOpRegion.OpRegion->MBox3.PCFT = ((UINT32) GlobalNvsArea-
> >Area->IgdPowerConservation) | BIT31;
> + //
> + // Create the notification and register callback function on the PciIo
> installation,
> + //
> + //
> + Status = gBS->CreateEvent (
> + EVT_NOTIFY_SIGNAL,
> + TPL_CALLBACK,
> + (EFI_EVENT_NOTIFY)GetVBiosVbtCallback,
> + NULL,
> + &mConOutEvent
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + return Status;
> +
> + }
> +
> + Status = gBS->RegisterProtocolNotify (
> +#ifdef ECP_FLAG
> + &gExitPmAuthProtocolGuid,
> +#else
> + &gEfiDxeSmmReadyToLockProtocolGuid,
> +#endif
> + mConOutEvent,
> + &gConOutNotifyReg
> + );
> +
> + Status = gBS->CreateEvent (
> + EVT_NOTIFY_SIGNAL,
> + TPL_CALLBACK,
> + (EFI_EVENT_NOTIFY)SetGOPVersionCallback,
> + NULL,
> + &mSetGOPverEvent
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + Status = gBS->RegisterProtocolNotify (
> + &gEfiGraphicsOutputProtocolGuid,
> + mSetGOPverEvent,
> + &gConOutNotifyReg
> + );
> +
> +
> + //
> + // Initialize hardware state:
> + // Set ASLS Register to the OpRegion physical memory address.
> + // Set SWSCI register bit 15 to a "1" to activate SCI interrupts.
> + //
> +
> + IgdMmPci32 (IGD_ASLS_OFFSET) =
> (UINT32)(UINTN)(mIgdOpRegion.OpRegion);
> + IgdMmPci16AndThenOr (IGD_SWSCI_OFFSET, ~(BIT0), BIT15);
> +
> + DwordData = IgdMmPci32 (IGD_ASLS_OFFSET);
> + S3BootScriptSavePciCfgWrite (
> + S3BootScriptWidthUint32,
> + (UINTN) (EFI_PCI_ADDRESS (IGD_BUS, IGD_DEV, IGD_FUN_0,
> IGD_ASLS_OFFSET)),
> + 1,
> + &DwordData
> + );
> +
> +
> + DwordData = IgdMmPci32 (IGD_SWSCI_OFFSET);
> + S3BootScriptSavePciCfgWrite (
> + S3BootScriptWidthUint32,
> + (UINTN) (EFI_PCI_ADDRESS (IGD_BUS, IGD_DEV, IGD_FUN_0,
> IGD_SWSCI_OFFSET)),
> + 1,
> + &DwordData
> + );
> +
> + AcpiBase = MmPci16 (
> + 0,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + R_PCH_LPC_ACPI_BASE
> + ) & B_PCH_LPC_ACPI_BASE_BAR;
> +
> + //
> + // Find the CPU I/O Protocol. ASSERT if not found.
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiCpuIoProtocolGuid,
> + NULL,
> + (void **)&CpuIo
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + CpuIo->Io.Read (
> + CpuIo,
> + EfiCpuIoWidthUint16,
> + AcpiBase + R_PCH_ACPI_GPE0a_STS,
> + 1,
> + &Data16
> + );
> + //
> + // Clear the B_PCH_ACPI_GPE0a_STS_GUNIT_SCI bit in
> R_PCH_ACPI_GPE0a_STS by writing a '1'.
> + //
> + Data16 |= B_PCH_ACPI_GPE0a_STS_GUNIT_SCI;
> +
> + CpuIo->Io.Write (
> + CpuIo,
> + EfiCpuIoWidthUint16,
> + AcpiBase + R_PCH_ACPI_GPE0a_STS,
> + 1,
> + &Data16
> + );
> +
> + //
> + // Install OpRegion / Software SCI protocol
> + //
> + Handle = NULL;
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Handle,
> + &gIgdOpRegionProtocolGuid,
> + &mIgdOpRegion,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Return final status
> + //
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.h
> b/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.h
> new file mode 100644
> index 0000000000..cd1d208d61
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.h
> @@ -0,0 +1,235 @@
> +
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + IgdOpRegion.h
> +
> +Abstract:
> +
> + This is part of the implementation of an Intel Graphics drivers OpRegion /
> + Software SCI interface between system BIOS, ASL code, and Graphics
> drivers.
> +
> + Supporting Specifiction: OpRegion / Software SCI SPEC 0.70
> +
> + Acronyms:
> + IGD: Internal Graphics Device
> + NVS: ACPI Non Volatile Storage
> + OpRegion: ACPI Operational Region
> + VBT: Video BIOS Table (OEM customizable data)
> +
> +--*/
> +
> +#ifndef _IGD_OPREGION_H_
> +#define _IGD_OPREGION_H_
> +
> +//
> +// Statements that include other header files.
> +//
> +#include "VlvPlatformInit.h"
> +#include "VlvCommonDefinitions.h"
> +#include <Uefi/UefiInternalFormRepresentation.h>
> +#include <FrameworkDxe.h>
> +
> +//
> +//
> +// OpRegion (Miscellaneous) #defines.
> +//
> +// OpRegion Header #defines.
> +//
> +
> +#define HEADER_SIGNATURE "IntelGraphicsMem"
> +#define HEADER_SIZE 0x2000
> +#define HEADER_OPREGION_VER 0x0200
> +#define HEADER_OPREGION_REV 0x00
> +
> +//
> +//For VLV Tablet, MailBOX2(SCI)is not supported.
> +//
> +#define HEADER_MBOX_SUPPORT (HD_MBOX4 + HD_MBOX3 +
> HD_MBOX1)
> +#define HD_MBOX1 BIT0
> +#define HD_MBOX2 BIT1
> +#define HD_MBOX3 BIT2
> +#define HD_MBOX4 BIT3
> +#define HD_MBOX5 BIT4
> +#define SVER_SIZE 32
> +
> +//
> +//Audio Type support for VLV2 A0
> +//
> +#define AUDIO_TYPE_SUPPORT_MASK 0xFFFFFFF3
> +#define NO_AUDIO_SUPPORT (0<<2)
> +#define HD_AUDIO_SUPPORT (1<<2)
> +#define LPE_AUDIO_SUPPORT (2<<2)
> +#define AUDIO_TYPE_FIELD_MASK 0xFFFFFFEF
> +#define AUDIO_TYPE_FIELD_VALID (1<<4)
> +#define AUDIO_TYPE_FIELD_INVALID (0<<4)
> +
> +//
> +// OpRegion Mailbox 1 EQUates.
> +//
> +// OpRegion Mailbox 3 EQUates.
> +//
> +#define ALS_ENABLE BIT0
> +#define BLC_ENABLE BIT1
> +#define BACKLIGHT_BRIGHTNESS 0xFF
> +#define FIELD_VALID_BIT BIT31
> +#define WORD_FIELD_VALID_BIT BIT15
> +#define PFIT_ENABLE BIT2
> +#define PFIT_OPRN_AUTO 0x00000000
> +#define PFIT_OPRN_SCALING 0x00000007
> +#define PFIT_OPRN_OFF 0x00000000
> +#define PFIT_SETUP_AUTO 0
> +#define PFIT_SETUP_SCALING 1
> +#define PFIT_SETUP_OFF 2
> +#define INIT_BRIGHT_LEVEL 0x64
> +#define PFIT_STRETCH 6
> +#define PFIT_CENTER 1
> +
> +//
> +// GMCH PCI register access #defines.
> +//
> +
> +#define IgdMmPci32(Register) MmPci32 (0, IGD_BUS, IGD_DEV,
> IGD_FUN_0, Register)
> +#define IgdMmPci16Or(Register, OrData) MmPci16Or (0, IGD_BUS,
> IGD_DEV, IGD_FUN_0, Register, OrData)
> +#define IgdMmPci16AndThenOr(Register,AndData,OrData)
> MmPci16AndThenOr (0, IGD_BUS, IGD_DEV, IGD_FUN_0, Register, AndData,
> OrData)
> +
> +//
> +// Video BIOS / VBT #defines
> +//
> +#define IGD_DID_VLV 0x0F31
> +#define OPTION_ROM_SIGNATURE 0xAA55
> +#define VBIOS_LOCATION_PRIMARY 0xC0000
> +
> +#define VBT_SIGNATURE SIGNATURE_32 ('$', 'V', 'B', 'T')
> +
> +//
> +// Typedef stuctures
> +//
> +#pragma pack (1)
> +typedef struct {
> + UINT16 Signature; // 0xAA55
> + UINT8 Size512;
> + UINT8 Reserved[21];
> + UINT16 PcirOffset;
> + UINT16 VbtOffset;
> +} INTEL_VBIOS_OPTION_ROM_HEADER;
> +#pragma pack ()
> +
> +#pragma pack (1)
> +typedef struct {
> + UINT32 Signature; // "PCIR"
> + UINT16 VendorId; // 0x8086
> + UINT16 DeviceId;
> + UINT16 Reserved0;
> + UINT16 Length;
> + UINT8 Revision;
> + UINT8 ClassCode[3];
> + UINT16 ImageLength;
> + UINT16 CodeRevision;
> + UINT8 CodeType;
> + UINT8 Indicator;
> + UINT16 Reserved1;
> +} INTEL_VBIOS_PCIR_STRUCTURE;
> +#pragma pack ()
> +
> +#pragma pack (1)
> +typedef struct {
> + UINT8 HeaderSignature[20];
> + UINT16 HeaderVersion;
> + UINT16 HeaderSize;
> + UINT16 HeaderVbtSize;
> + UINT8 HeaderVbtCheckSum;
> + UINT8 HeaderReserved;
> + UINT32 HeaderOffsetVbtDataBlock;
> + UINT32 HeaderOffsetAim1;
> + UINT32 HeaderOffsetAim2;
> + UINT32 HeaderOffsetAim3;
> + UINT32 HeaderOffsetAim4;
> + UINT8 DataHeaderSignature[16];
> + UINT16 DataHeaderVersion;
> + UINT16 DataHeaderSize;
> + UINT16 DataHeaderDataBlockSize;
> + UINT8 CoreBlockId;
> + UINT16 CoreBlockSize;
> + UINT16 CoreBlockBiosSize;
> + UINT8 CoreBlockBiosType;
> + UINT8 CoreBlockReleaseStatus;
> + UINT8 CoreBlockHWSupported;
> + UINT8 CoreBlockIntegratedHW;
> + UINT8 CoreBlockBiosBuild[4];
> + UINT8 CoreBlockBiosSignOn[155];
> +} VBIOS_VBT_STRUCTURE;
> +#pragma pack ()
> +
> +//
> +// Driver Private Function definitions
> +//
> +EFI_STATUS
> +GetSVER (
> + OUT UINT8 *SVER
> + );
> +
> +/**
> + Acquire the string associated with the ProducerGuid and return it.
> +
> + @param ProducerGuid The Guid to search the HII database for
> + @param Token The token value of the string to extract
> + @param String The string that is extracted
> +
> + @retval EFI_SUCCESS The function completed successfully
> + @retval EFI_NOT_FOUND The requested string was not found
> +
> +**/
> +EFI_STATUS
> +GetStringFromToken (
> + IN EFI_GUID *ProducerGuid,
> + IN STRING_REF Token,
> + OUT CHAR16 **String
> + );
> +
> +/**
> +
> + Graphics OpRegion / Software SCI driver installation function.
> +
> + @param Void
> +
> + @retval EFI_SUCCESS The driver installed without error.
> + @retval EFI_ABORTED The driver encountered an error and could not
> complete
> + installation of the ACPI tables.
> +**/
> +EFI_STATUS
> +IgdOpRegionInit (
> + void
> + );
> +
> +/**
> + Extract information pertaining to the HiiHandle
> +
> + @param HiiHandle Hii handle
> + @param ImageLength For input, length of DefaultImage;
> + For output, length of actually required
> +
> + @param DefaultImage Image buffer prepared by caller
> + @param Guid Guid information about the form
> +
> + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate
> + @retval EFI_BUFFER_TOO_SMALL DefualtImage has no enough
> ImageLength
> + @retval EFI_SUCCESS Successfully extract data from Hii database.
> +
> +**/
> +EFI_STATUS
> +ExtractDataFromHiiHandle (
> + IN EFI_HII_HANDLE HiiHandle,
> + IN OUT UINT16 *ImageLength,
> + OUT UINT8 *DefaultImage,
> + OUT EFI_GUID *Guid
> + );
> +#endif
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c
> b/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c
> new file mode 100644
> index 0000000000..75675fbf00
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c
> @@ -0,0 +1,287 @@
> +
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + VlvPlatformInit.c
> +
> +Abstract:
> +
> + This is the driver that initializes the Intel ValleyView.
> +
> +--*/
> +
> +#include "VlvPlatformInit.h"
> +#include <Protocol/VlvPlatformPolicy.h>
> +
> +extern DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy;
> +UINT64 GTTMMADR;
> +
> +DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy;
> +
> +/**
> + "Poll Status" for GT Readiness
> +
> + @param Base Base address of MMIO
> + @param Offset MMIO Offset
> + @param Mask Mask
> + @param Result Value to wait for
> +
> + @retval None
> +
> +**/
> +VOID
> +PollGtReady_hang (
> + UINT64 Base,
> + UINT32 Offset,
> + UINT32 Mask,
> + UINT32 Result
> + )
> +{
> + UINT32 GtStatus;
> +
> + //
> + // Register read
> + //
> + GtStatus = MmioRead32 ((UINTN)Base+ Offset);
> +
> + while (((GtStatus & Mask) != Result)) {
> +
> + GtStatus = MmioRead32 ((UINTN)Base + Offset);
> + }
> +
> +}
> +
> +/**
> + Do Post GT PM Init Steps after VBIOS Initialization.
> +
> + @param Event A pointer to the Event that triggered the callback.
> + @param Context A pointer to private data registered with the callback
> function.
> +
> + @retval EFI_SUCCESS GC_TODO
> +
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PostPmInitCallBack (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + UINT64 OriginalGTTMMADR;
> + UINT32 LoGTBaseAddress;
> + UINT32 HiGTBaseAddress;
> +
> + //
> + // Enable Bus Master, I/O and Memory access on 0:2:0
> + //
> + PciOr8 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_CMD), (BIT2 | BIT1));
> +
> + //
> + // only 32bit read/write is legal for device 0:2:0
> + //
> + OriginalGTTMMADR = (UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV,
> 0,IGD_R_GTTMMADR));
> + OriginalGTTMMADR = LShiftU64 ((UINT64) PciRead32 (PCI_LIB_ADDRESS(0,
> IGD_DEV, 0,IGD_R_GTTMMADR + 4)), 32) | (OriginalGTTMMADR);
> +
> + //
> + // 64bit GTTMADR does not work for S3 save script table since it is
> executed in PEIM phase
> + // Program temporarily 32bits GTTMMADR for POST and S3 resume
> + //
> + LoGTBaseAddress = (UINT32) (GTTMMADR & 0xFFFFFFFF);
> + HiGTBaseAddress = (UINT32) RShiftU64 ((GTTMMADR &
> 0xFFFFFFFF00000000), 32);
> + S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR),
> LoGTBaseAddress);
> + S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4),
> HiGTBaseAddress);
> +
> +
> +
> + //
> + // Restore original GTTMMADR
> + //
> + LoGTBaseAddress = (UINT32) (OriginalGTTMMADR & 0xFFFFFFFF);
> + HiGTBaseAddress = (UINT32) RShiftU64 ((OriginalGTTMMADR &
> 0xFFFFFFFF00000000), 32);
> +
> + S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR),
> LoGTBaseAddress);
> + S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4),
> HiGTBaseAddress);
> +
> +
> + //
> + // Lock the following registers, GGC, BDSM, BGSM
> + //
> + PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_MGGC_OFFSET), LockBit);
> + PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_BSM_OFFSET), LockBit);
> + PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_BGSM), LockBit);
> +
> + gBS->CloseEvent (Event);
> +
> + //
> + // Return final status
> + //
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +
> + Routine Description:
> +
> + Initialize GT Post Routines.
> +
> + @param ImageHandle Handle for the image of this driver
> + @param DxePlatformSaPolicy SA DxePlatformPolicy protocol
> +
> + @retval EFI_SUCCESS GT POST initialization complete
> +
> +**/
> +EFI_STATUS
> +IgdPmHook (
> + IN EFI_HANDLE ImageHandle,
> + IN DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicyParam
> + )
> +{
> +
> + EFI_EVENT mConOutEvent;
> + VOID *gConOutNotifyReg;
> +
> + EFI_STATUS Status;
> +
> + EFI_PHYSICAL_ADDRESS MemBaseAddress;
> + UINT32 LoGTBaseAddress;
> + UINT32 HiGTBaseAddress;
> +
> + GTTMMADR = 0;
> + Status = EFI_SUCCESS;
> +
> + //
> + // If device 0:2:0 (Internal Graphics Device, or GT) is enabled, then Program
> GTTMMADR,
> + //
> + if (PciRead16(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_VID)) != 0xFFFF) {
> +
> + ASSERT (gDS!=NULL);
> +
> + //
> + // Enable Bus Master, I/O and Memory access on 0:2:0
> + //
> + PciOr8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD), (BIT2 | BIT1 |
> BIT0));
> +
> + //
> + // Means Allocate 4MB for GTTMADDR
> + //
> + MemBaseAddress = 0x0ffffffff;
> +
> + Status = gDS->AllocateMemorySpace (
> + EfiGcdAllocateMaxAddressSearchBottomUp,
> + EfiGcdMemoryTypeMemoryMappedIo,
> + GTT_MEM_ALIGN,
> + GTTMMADR_SIZE_4MB,
> + &MemBaseAddress,
> + ImageHandle,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Program GT PM Settings if GTTMMADR allocation is Successful
> + //
> + GTTMMADR = (UINTN) MemBaseAddress;
> +
> + LoGTBaseAddress = (UINT32) (MemBaseAddress & 0xFFFFFFFF);
> + HiGTBaseAddress = (UINT32) RShiftU64 ((MemBaseAddress &
> 0xFFFFFFFF00000000), 32);
> +
> + PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR),
> LoGTBaseAddress);
> + PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR+4),
> HiGTBaseAddress);
> +
> +
> + S3PciRead32(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR));
> +
> +
> + S3MmioRead32(IGD_R_GTTMMADR + 4);
> +
> +
> + S3PciRead8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD));
> +
> + //
> + // Do POST GT PM Init Steps after VBIOS Initialization in
> DoPostPmInitCallBack
> + //
> + Status = gBS->CreateEvent (
> + EVT_NOTIFY_SIGNAL,
> + TPL_CALLBACK,
> + (EFI_EVENT_NOTIFY)PostPmInitCallBack,
> + NULL,
> + &mConOutEvent
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> +
> + Status = gBS->RegisterProtocolNotify (
> + &gEfiGraphicsOutputProtocolGuid,
> + mConOutEvent,
> + &gConOutNotifyReg
> + );
> +
> +
> +
> + MmioWrite64 (IGD_R_GTTMMADR, 0);
> +
> + //
> + // Free allocated resources
> + //
> + gDS->FreeMemorySpace (
> + MemBaseAddress,
> + GTTMMADR_SIZE_4MB
> + );
> +
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +
> + This is the standard EFI driver point that detects
> + whether there is an ICH southbridge in the system
> + and if so, initializes the chip.
> +
> + @param ImageHandle Handle for the image of this driver
> + @param SystemTable Pointer to the EFI System Table
> +
> + @retval EFI_SUCCESS The function completed successfully
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +VlvPlatformInitEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = gBS->LocateProtocol (&gDxeVlvPlatformPolicyGuid, NULL, (void
> **)&DxePlatformSaPolicy);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // GtPostInit Initialization
> + //
> + DEBUG ((EFI_D_ERROR, "Initializing GT PowerManagement and other GT
> POST related\n"));
> + IgdPmHook (ImageHandle, DxePlatformSaPolicy);
> +
> + //
> + // IgdOpRegion Install Initialization
> + //
> + DEBUG ((EFI_D_ERROR, "Initializing IGD OpRegion\n"));
> + IgdOpRegionInit ();
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.h
> b/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.h
> new file mode 100644
> index 0000000000..5caf54bb8a
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.h
> @@ -0,0 +1,65 @@
> +
> +/*++
> +
> +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + VlvPlatformInit.h
> +
> +Abstract:
> +
> + Header file for SA Initialization Driver.
> +
> +--*/
> +
> +#ifndef _VLV_PLATFORM_INIT_DXE_H_
> +#define _VLV_PLATFORM_INIT_DXE_H_
> +#include "PiDxe.h"
> +
> +#include <Protocol/VlvPlatformPolicy.h>
> +
> +#include "IgdOpRegion.h"
> +
> +#include <Library/DxeServicesTableLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include "Library/DebugLib.h"
> +#include "Library/S3IoLib.h"
> +#include "Library/S3PciLib.h"
> +#include "Library/IoLib.h"
> +#include "Library/PciLib.h"
> +#include "Library/S3BootScriptLib.h"
> +
> +//
> +// GT RELATED EQUATES
> +//
> +#define GTT_MEM_ALIGN 22
> +#define GTTMMADR_SIZE_4MB 0x400000
> +
> +#define IGD_BUS 0x00
> +#define IGD_DEV 0x02
> +#define IGD_FUN_0 0x00
> +
> +#define IGD_R_VID 0x00
> +#define IGD_R_CMD 0x04
> +#define IGD_R_GTTMMADR 0x10
> +
> +#define IGD_R_BGSM 0x70
> +#define LockBit BIT0
> +
> +#define IGD_VID 0x8086
> +#define IGD_DID 0xA001
> +#define IGD_MGGC_OFFSET 0x0050 //GMCH Graphics Control Register
> 0x50
> +#define IGD_BSM_OFFSET 0x005C //Base of Stolen Memory
> +#define IGD_SWSCI_OFFSET 0x00E0 //Software SCI 0xE0 2
> +#define IGD_ASLE_OFFSET 0x00E4 //System Display Event Register
> 0xE4 4
> +#define IGD_ASLS_OFFSET 0x00FC // ASL Storage
> +
> +#endif
> +
> diff --git
> a/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.i
> nf
> b/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.i
> nf
> new file mode 100644
> index 0000000000..9d277dd7cf
> --- /dev/null
> +++
> b/Platform/Intel/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.i
> nf
> @@ -0,0 +1,74 @@
> +#
> +#
> +#/*++
> +#
> +# Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +# Module Name:
> +#
> +# VlvPlatformInit.inf
> +#
> +# Abstract:
> +#
> +# Component description file for wrapper driver of Vlv platform init part.
> +#
> +#--*/
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = VlvPlatformInitDxe
> + FILE_GUID = 1EC0EFC9-C93A-4b62-9B27-C059ABD80E92
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = VlvPlatformInitEntryPoint
> +
> +[Sources]
> + VlvPlatformInit.c
> + IgdOpRegion.c
> +
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + UefiDriverEntryPoint
> + DebugLib
> + UefiBootServicesTableLib
> + S3BootScriptLib
> + DxeServicesTableLib
> + PchPlatformLib
> + S3PciLib
> + S3IoLib
> + PciLib
> + IoLib
> +
> +[Guids]
> + gBmpImageGuid
> + gEfiDxeServicesTableGuid
> +
> +[Protocols]
> + gDxeVlvPlatformPolicyGuid
> + gEfiDxeSmmReadyToLockProtocolGuid
> + gIgdOpRegionProtocolGuid
> + gEfiGlobalNvsAreaProtocolGuid
> + gEfiPciIoProtocolGuid
> + gEfiFirmwareVolume2ProtocolGuid
> + gEfiCpuIoProtocolGuid
> +
> +[Depex]
> + gDxeVlvPlatformPolicyGuid AND
> + gEfiPciRootBridgeIoProtocolGuid AND
> + gEfiCpuIoProtocolGuid AND
> + gEfiDataHubProtocolGuid AND
> + gEfiGlobalNvsAreaProtocolGuid AND
> + gEfiFirmwareVolume2ProtocolGuid AND
> + gEfiHiiDatabaseProtocolGuid
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcDriver.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcDriver.c
> new file mode 100644
> index 0000000000..f98265761b
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcDriver.c
> @@ -0,0 +1,340 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +
> +Module Name:
> +
> + LpcDriver.c
> +
> +Abstract:
> +
> + EFI Lpc Driver for a Generic PC Platform
> +
> +
> +
> +--*/
> +
> +#include "LpcDriver.h"
> +#include "IndustryStandard/Pci22.h"
> +
> +//
> +// This driver is for ACPI(PNP0A03,0)/PCI(0x1f,0)
> +//
> +
> +//
> +// Lpc Driver Global Variables
> +//
> +
> +EFI_DRIVER_BINDING_PROTOCOL gLpcDriver = {
> + LpcDriverSupported,
> + LpcDriverStart,
> + LpcDriverStop,
> + 0x10,
> + NULL,
> + NULL
> +};
> +
> +LPC_DEV mLpc = {
> + LPC_DEV_SIGNATURE,
> + NULL,
> + {
> + IsaDeviceEnumerate,
> + IsaDeviceSetPower,
> + IsaGetCurrentResource,
> + IsaGetPossibleResource,
> + IsaSetResource,
> + IsaEnableDevice,
> + IsaInitDevice,
> + LpcInterfaceInit
> + },
> + NULL
> +};
> +
> +BOOLEAN InitExecuted = FALSE;
> +
> +/**
> + the entry point of the Lpc driver
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LpcDriverEntryPoint(
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> +
> +
> + return EfiLibInstallDriverBinding (ImageHandle, SystemTable, &gLpcDriver,
> ImageHandle);
> +}
> +
> +/**
> +
> + ControllerDriver Protocol Method
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LpcDriverSupported (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE Controller,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PCI_IO_PROTOCOL *PciIo;
> + EFI_DEVICE_PATH_PROTOCOL *IsaBridgeDevicePath;
> +
> + ACPI_HID_DEVICE_PATH *AcpiNode;
> + PCI_DEVICE_PATH *PciNode;
> + PCI_TYPE00 Pci;
> +
> + //
> + // Get the ISA bridge's Device Path and test it
> + // the following code is specific
> + //
> + Status = gBS->OpenProtocol (
> + Controller,
> + &gEfiDevicePathProtocolGuid,
> + (VOID **)&IsaBridgeDevicePath,
> + This->DriverBindingHandle,
> + Controller,
> + EFI_OPEN_PROTOCOL_BY_DRIVER
> + );
> +
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + Status = EFI_SUCCESS;
> + AcpiNode = (ACPI_HID_DEVICE_PATH *)IsaBridgeDevicePath;
> + if (AcpiNode->Header.Type != ACPI_DEVICE_PATH ||
> + AcpiNode->Header.SubType != ACPI_DP ||
> + DevicePathNodeLength (&AcpiNode->Header) !=
> sizeof(ACPI_HID_DEVICE_PATH) ||
> + AcpiNode -> HID != EISA_PNP_ID(0x0A03) ||
> + AcpiNode -> UID != 0 ) {
> + Status = EFI_UNSUPPORTED;
> + } else {
> + //
> + // Get the next node
> + //
> + IsaBridgeDevicePath = NextDevicePathNode (IsaBridgeDevicePath);
> + PciNode = (PCI_DEVICE_PATH *)IsaBridgeDevicePath;
> + if (PciNode->Header.Type != HARDWARE_DEVICE_PATH ||
> + PciNode->Header.SubType != HW_PCI_DP ||
> + DevicePathNodeLength (&PciNode->Header) != sizeof
> (PCI_DEVICE_PATH) ||
> + PciNode -> Function != 0x00 ||
> + PciNode -> Device != 0x1f ) {
> + Status = EFI_UNSUPPORTED;
> + }
> + }
> +
> + gBS->CloseProtocol (
> + Controller,
> + &gEfiDevicePathProtocolGuid,
> + This->DriverBindingHandle,
> + Controller
> + );
> +
> + if (EFI_ERROR (Status)) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Get PciIo protocol instance
> + //
> + Status = gBS->OpenProtocol (
> + Controller,
> + &gEfiPciIoProtocolGuid,
> + (VOID **)&PciIo,
> + This->DriverBindingHandle,
> + Controller,
> + EFI_OPEN_PROTOCOL_BY_DRIVER
> + );
> +
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + Status = PciIo->Pci.Read (
> + PciIo,
> + EfiPciIoWidthUint32,
> + 0,
> + sizeof(Pci) / sizeof(UINT32),
> + &Pci
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + Status = EFI_SUCCESS; //TODO: force return success as temp solution
> EFI_UNSUPPORTED;
> + if ((Pci.Hdr.Command & 0x03) == 0x03) {
> + if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {
> + //
> + // See if this is a standard PCI to ISA Bridge from the Base Code
> + // and Class Code
> + //
> + if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA) {
> + Status = EFI_SUCCESS;
> + } else {
> + }
> +
> + //
> + // See if this is an Intel PCI to ISA bridge in Positive Decode Mode
> + //
> + if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE &&
> + Pci.Hdr.VendorId == 0x8086 &&
> + Pci.Hdr.DeviceId == 0x7110) {
> + Status = EFI_SUCCESS;
> + } else {
> + }
> + } else {
> + }
> + }
> + else {
> + }
> + }
> +
> + gBS->CloseProtocol (
> + Controller,
> + &gEfiPciIoProtocolGuid,
> + This->DriverBindingHandle,
> + Controller
> + );
> + return Status;
> +}
> +
> +
> +/**
> + Install EFI_ISA_ACPI_PROTOCOL
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LpcDriverStart (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE Controller,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PCI_IO_PROTOCOL *PciIo;
> +
> + //
> + // Get Pci IO
> + //
> + Status = gBS->OpenProtocol (
> + Controller,
> + &gEfiPciIoProtocolGuid,
> + (VOID **)&PciIo,
> + This->DriverBindingHandle,
> + Controller,
> + EFI_OPEN_PROTOCOL_BY_DRIVER
> + );
> +
> + if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
> + return Status;
> + }
> +
> + mLpc.PciIo = PciIo;
> +
> + //
> + // Install IsaAcpi interface, the Sio interface is not installed!
> + //
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Controller,
> + &gEfiIsaAcpiProtocolGuid,
> + &mLpc.IsaAcpi,
> + NULL
> + );
> + return Status;
> +}
> +
> +
> +EFI_STATUS
> +EFIAPI
> +LpcDriverStop (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE Controller,
> + IN UINTN NumberOfChildren,
> + IN EFI_HANDLE *ChildHandleBuffer
> + )
> +{
> + EFI_STATUS Status;
> + EFI_ISA_ACPI_PROTOCOL *IsaAcpi;
> + LPC_DEV *LpcDev;
> +
> + //
> + // Get EFI_ISA_ACPI_PROTOCOL interface
> + //
> + Status = gBS->OpenProtocol (
> + Controller,
> + &gEfiIsaAcpiProtocolGuid,
> + (VOID **)&IsaAcpi,
> + This->DriverBindingHandle,
> + Controller,
> + EFI_OPEN_PROTOCOL_GET_PROTOCOL
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + LpcDev = LPC_ISA_ACPI_FROM_THIS (IsaAcpi);
> +
> + //
> + // Uninstall protocol interface: EFI_ISA_ACPI_PROTOCOL
> + //
> + Status = gBS->UninstallProtocolInterface (
> + Controller,
> + &gEfiIsaAcpiProtocolGuid,
> + &LpcDev->IsaAcpi
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + gBS->CloseProtocol (
> + Controller,
> + &gEfiPciIoProtocolGuid,
> + This->DriverBindingHandle,
> + Controller
> + );
> +
> + return EFI_SUCCESS;
> +}
> +
> +VOID
> +LpcIoRead8 (
> + IN UINT16 Port,
> + OUT UINT8 *Data
> + )
> +{
> + mLpc.PciIo->Io.Read(
> + mLpc.PciIo,
> + EfiPciWidthUint8,
> + EFI_PCI_IO_PASS_THROUGH_BAR,
> + Port,
> + 1,
> + Data
> + );
> +}
> +
> +VOID
> +LpcIoWrite8 (
> + IN UINT16 Port,
> + IN UINT8 Data
> + )
> +{
> + mLpc.PciIo->Io.Write(
> + mLpc.PciIo,
> + EfiPciWidthUint8,
> + EFI_PCI_IO_PASS_THROUGH_BAR,
> + Port,
> + 1,
> + &Data
> + );
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcDriver.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcDriver.h
> new file mode 100644
> index 0000000000..5e264485e7
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcDriver.h
> @@ -0,0 +1,112 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + LpcDriver.h
> +
> +Abstract:
> +
> + EFI Lpc Driver for a Generic PC Platform
> +
> +
> +
> +--*/
> +
> +#ifndef _LPC_DRIVER_H
> +#define _LPC_DRIVER_H
> +
> + #include "LpcSio.h"
> + #include "LpcIsaAcpi.h"
> +
> +#include "Protocol/IsaAcpi.h"
> +#include "Protocol/PciIo.h"
> +#include "Protocol/DriverBinding.h"
> +#include "Library/UefiBootServicesTableLib.h"
> +#include "IsaAcpiDxe/PcatIsaAcpi.h"
> +#include "IndustryStandard/Pci22.h"
> +#include "Protocol/LpcWpce791Policy.h"
> +
> +#include <Library/DebugLib.h>
> +
> +#define ICH_LPC_BRIDGE_BUS_DEV_FUNC 0x1F0000
> +
> +//
> +// LPC device private data structure
> +//
> +//#define LPC_DEV_SIGNATURE 'W87X'
> +#define LPC_DEV_SIGNATURE SIGNATURE_32('X', '7', '8', 'W') //'W87X'
> +#define EFI_WPCE791_PS2_KEYBOARD_ENABLE 0x01
> +#define EFI_WPCE791_PS2_KEYBOARD_DISABLE 0x00
> +
> +#define EFI_WPCE791_PS2_MOUSE_ENABLE 0x01
> +#define EFI_WPCE791_PS2_MOUSE_DISABLE 0x00
> +
> +
> +
> +typedef struct {
> + UINTN Signature;
> + EFI_HANDLE Handle;
> + EFI_ISA_ACPI_PROTOCOL IsaAcpi;
> + EFI_PCI_IO_PROTOCOL *PciIo;
> +
> +} LPC_DEV;
> +
> +#define LPC_ISA_ACPI_FROM_THIS(a) BASE_CR (a, LPC_DEV, IsaAcpi)
> +
> +//
> +// Driver entry point
> +//
> +EFI_STATUS
> +EFIAPI
> +LpcDriverEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + );
> +
> +//
> +// Prototypes for Driver model protocol interface
> +//
> +EFI_STATUS
> +EFIAPI
> +LpcDriverSupported (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE Controller,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +LpcDriverStart (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE Controller,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +LpcDriverStop (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE Controller,
> + IN UINTN NumberOfChildren,
> + IN EFI_HANDLE *ChildHandleBuffer
> + );
> +
> +VOID
> +LpcIoRead8 (
> + IN UINT16 Port,
> + OUT UINT8 *Data
> + );
> +
> +VOID
> +LpcIoWrite8 (
> + IN UINT16 Port,
> + IN UINT8 Data
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.c
> new file mode 100644
> index 0000000000..9c0b79b15c
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.c
> @@ -0,0 +1,366 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + LpcIsaAcpi.c
> +
> +Abstract: IsaAcpi implementation
> +
> +
> +
> +--*/
> +
> +#include "LpcDriver.h"
> +
> +//
> +// PS/2 Keyboard Controller
> +//
> +static EFI_ISA_ACPI_RESOURCE
> mLpcWpce791Ps2KeyboardDeviceResources[] = {
> + {EfiIsaAcpiResourceIo, 0, 0x60, 0x64},
> + {EfiIsaAcpiResourceInterrupt, 0, 1, 0},
> + {EfiIsaAcpiResourceEndOfList, 0, 0, 0}
> +};
> +
> +//
> +// PS/2 Mouse Controller
> +//
> +static EFI_ISA_ACPI_RESOURCE mLpcWpce791Ps2MouseDeviceResources[]
> = {
> + {EfiIsaAcpiResourceIo, 0, 0x60, 0x64},
> + {EfiIsaAcpiResourceInterrupt, 0, 12, 0},
> + {EfiIsaAcpiResourceEndOfList, 0, 0, 0}
> +};
> +
> +//
> +// COM
> +//
> +static EFI_ISA_ACPI_RESOURCE mLpcWpce791ComDeviceResources[] = {
> + {EfiIsaAcpiResourceIo, 0, 0x3f8, 0x3ff},
> + {EfiIsaAcpiResourceInterrupt, 0, 4, 0},
> + {EfiIsaAcpiResourceEndOfList, 0, 0, 0}
> +};
> +
> +//
> +// Table of ISA Controllers
> +//
> +EFI_ISA_ACPI_RESOURCE_LIST mLpcWpce791DeviceList[] = {
> + {{EISA_PNP_ID(0x303), 0}, mLpcWpce791Ps2KeyboardDeviceResources },
> // PS/2 Keyboard Controller
> + {{EISA_PNP_ID(0xF03), 0}, mLpcWpce791Ps2MouseDeviceResources
> }, // PS/2 Mouse Controller
> + {{EISA_PNP_ID(0x501), 0}, mLpcWpce791ComDeviceResources },
> // COM
> + {{0, 0}, NULL } // End
> +};
> +
> +static ICH_DMA_INIT mIchDmaInitTable [] = {
> +//
> +//Register OFFSET, Value
> +//
> +
> + 0x0D8, 0x000, // Reset DMA Controller 2
> + 0x0D0, 0x000, // Enable DMA controller 2
> + 0x00C, 0x000, // Reset DMA Controller 1
> + 0x008, 0x000, // Enable DMA controller 1
> +
> + //
> + // Channel 4
> + //
> + 0x0D6, 0x0c0, // DMA contr. 2 Cascade mode, addr. increment,
> disable auto init.
> + 0x0D2, 0x000, // Clear write request register
> + 0x0d4, 0x000, // Enable DREQs for channel
> +
> + //
> + // Channel 0
> + //
> + 0x00B, 0x040, // DMA contr. 1 single mode, addr. increment,
> disable auto init.
> + 0x009, 0x000, // Clear write request register
> + 0x00A, 0x000, // Enable DREQs for channel
> +
> + //
> + // Channel 1
> + //
> + 0x00B, 0x041, // DMA contr. 1 single mode, addr. increment,
> disable auto init.
> + 0x009, 0x001, // Clear write request register
> + 0x00A, 0x001, // Enable DREQs for channel
> +
> + //
> + // Channel 2
> + //
> + 0x00B, 0x042, // DMA contr. 1 single mode, addr. increment,
> disable auto init.
> + 0x009, 0x002, // Clear write request register
> + 0x00A, 0x002, // Enable DREQs for channel
> +
> + //
> + // Channel 3
> + //
> + 0x00B, 0x043, // DMA contr. 1 single mode, addr. increment,
> disable auto init.
> + 0x009, 0x003, // Clear write request register
> + 0x00A, 0x003, // Enable DREQs for channel
> +
> + //
> + // Channel 5
> + //
> + 0x0D6, 0x041, // DMA contr. 2 single mode, addr. increment,
> disable auto init.
> + 0x0D2, 0x001, // Clear write request register
> + 0x0D4, 0x001, // Enable DREQs for channel
> +
> + //
> + // Channel 6
> + //
> + 0x0D6, 0x042, // DMA contr. 2 single mode, addr. increment,
> disable auto init.
> + 0x0D2, 0x002, // Clear write request register
> + 0x0D4, 0x002, // Enable DREQs for channel
> +
> + //
> + // Channel 7
> + //
> + 0x0D6, 0x043, // DMA contr. 2 single mode, addr. increment,
> disable auto init.
> + 0x0D2, 0x003, // Clear write request register
> + 0x0D4, 0x003 // Enable DREQs for channel
> +
> +};
> +
> +//
> +// ISA ACPI Protocol Functions
> +//
> +/**
> +
> + Enumerate the ISA devices on the ISA bus
> +
> +**/
> +VOID
> +IsaDeviceLookup (
> + IN EFI_ISA_ACPI_DEVICE_ID *Device,
> + OUT EFI_ISA_ACPI_RESOURCE_LIST **IsaAcpiDevice,
> + OUT EFI_ISA_ACPI_RESOURCE_LIST **NextIsaAcpiDevice
> + )
> +{
> + UINTN Index;
> +
> + *IsaAcpiDevice = NULL;
> + if (NextIsaAcpiDevice != NULL) {
> + *NextIsaAcpiDevice = NULL;
> + }
> + if (Device == NULL) {
> + Index = 0;
> + } else {
> + for(Index = 0; mLpcWpce791DeviceList[Index].Device.HID != 0; Index++) {
> + if (Device->HID == mLpcWpce791DeviceList[Index].Device.HID &&
> + Device->UID == mLpcWpce791DeviceList[Index].Device.UID ) {
> + break;
> + }
> + }
> + if (mLpcWpce791DeviceList[Index].Device.HID == 0) {
> + return;
> + }
> + *IsaAcpiDevice = &(mLpcWpce791DeviceList[Index]);
> + Index++;
> + }
> + if (NextIsaAcpiDevice != NULL &&
> mLpcWpce791DeviceList[Index].Device.HID != 0){
> + *NextIsaAcpiDevice = &(mLpcWpce791DeviceList[Index]);
> + }
> +}
> +
> +
> +/**
> + Enumerate the ISA devices on the ISA bus
> + It is hard code now and future it will get from ACPI table
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +IsaDeviceEnumerate (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + OUT EFI_ISA_ACPI_DEVICE_ID **Device
> + )
> +{
> + EFI_ISA_ACPI_RESOURCE_LIST *IsaAcpiDevice;
> + EFI_ISA_ACPI_RESOURCE_LIST *NextIsaAcpiDevice;
> +
> + IsaDeviceLookup (*Device, &IsaAcpiDevice, &NextIsaAcpiDevice);
> + if (NextIsaAcpiDevice == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + *Device = &(NextIsaAcpiDevice->Device);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Set ISA device power use sio
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +IsaDeviceSetPower (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device,
> + IN BOOLEAN OnOff
> + )
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +/**
> + Get current Resource of the specific ISA device
> + It is hardcode now and future will get from ACPI table
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +IsaGetCurrentResource (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device,
> + OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList
> + )
> +{
> + IsaDeviceLookup (Device, ResourceList, NULL);
> + if (*ResourceList == NULL || (*ResourceList)->ResourceItem == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +IsaGetPossibleResource (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device,
> + OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList
> + )
> +{
> + //
> + // Not supported yet
> + //
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +EFI_STATUS
> +EFIAPI
> +IsaSetResource (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device,
> + IN EFI_ISA_ACPI_RESOURCE_LIST *ResourceList
> + )
> +{
> + return EFI_UNSUPPORTED;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +IsaEnableDevice (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device,
> + IN BOOLEAN Enable
> + )
> +{
> +
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> +
> + Clear out Resource List if device is set to disable by platform policy
> +
> +**/
> +VOID
> +EmptyResourceList (
> + IN UINT32 DeviceHid
> + )
> +{
> + UINT8 Index;
> + for (Index = 0; mLpcWpce791DeviceList[Index].Device.HID != 0; Index++) {
> + if (DeviceHid == mLpcWpce791DeviceList[Index].Device.HID) {
> + mLpcWpce791DeviceList[Index].ResourceItem = NULL;
> + }
> + }
> + return;
> +}
> +
> +/**
> +
> + Clear out Resource List if device is set to disable by platform policy
> +
> +**/
> +VOID
> +EmptyResourceListHidUid (
> + IN UINT32 DeviceHid,
> + IN UINT32 DeviceUid
> + )
> +{
> + UINT8 Index;
> + for (Index = 0; mLpcWpce791DeviceList[Index].Device.HID != 0; Index++) {
> + if ((DeviceHid == mLpcWpce791DeviceList[Index].Device.HID) &&
> + (DeviceUid == mLpcWpce791DeviceList[Index].Device.UID)) {
> + mLpcWpce791DeviceList[Index].ResourceItem = NULL;
> + }
> + }
> + return;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +IsaInitDevice (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device
> + )
> +{
> + EFI_WPCE791_POLICY_PROTOCOL *LpcWpce791Policy;
> + EFI_STATUS Status;
> +
> + //
> + // Disable configuration according to platform protocol
> + //
> + Status = gBS->LocateProtocol (
> + &gEfiLpcWpce791PolicyProtocolGuid,
> + NULL,
> + (VOID **) &LpcWpce791Policy
> + );
> + if (!EFI_ERROR(Status)) {
> + if (LpcWpce791Policy->DeviceEnables.Ps2Keyboard ==
> EFI_WPCE791_PS2_KEYBOARD_DISABLE) {
> + EmptyResourceList(EISA_PNP_ID(0x303));
> + DisableLogicalDevice (SIO_KEYBOARD);
> + EmptyResourceList(EISA_PNP_ID(0xF03));
> + DisableLogicalDevice (SIO_KEYBOARD);
> + }
> + if (LpcWpce791Policy->DeviceEnables.Ps2Mouse ==
> EFI_WPCE791_PS2_MOUSE_DISABLE) {
> + EmptyResourceList(EISA_PNP_ID(0xF03));
> + DisableLogicalDevice (SIO_MOUSE);
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +LpcInterfaceInit (
> + IN EFI_ISA_ACPI_PROTOCOL *This
> + )
> +{
> + EFI_PCI_IO_PROTOCOL *PciIo;
> + UINTN Index;
> +
> + PciIo = (LPC_ISA_ACPI_FROM_THIS (This))->PciIo;
> +
> + //
> + // DMA controller initialize
> + //
> + for (Index=0; Index < (sizeof(mIchDmaInitTable)/sizeof(ICH_DMA_INIT));
> Index++) {
> + PciIo->Io.Write (
> + PciIo,
> + EfiPciIoWidthUint8,
> + EFI_PCI_IO_PASS_THROUGH_BAR,
> + mIchDmaInitTable[Index].Register,
> + 1,
> + &mIchDmaInitTable[Index].Value
> + );
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.h
> new file mode 100644
> index 0000000000..2291fd2c1d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.h
> @@ -0,0 +1,103 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + LpcIsaAcpi.h
> +
> +Abstract:
> +
> + Isa Acpi interface
> +
> +
> +
> +--*/
> +
> +#ifndef _LPC_ISA_ACPI_H
> +#define _LPC_ISA_ACPI_H
> +
> +
> +
> +#include "Protocol/IsaAcpi.h"
> +#include "Library/DevicePathLib.h"
> +
> +
> +typedef struct {
> + UINT8 Register;
> + UINT8 Value;
> +} ICH_DMA_INIT;
> +
> +//
> +// Prototypes for the ISA ACPI protocol interface
> +//
> +EFI_STATUS
> +EFIAPI
> +IsaDeviceEnumerate (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + OUT EFI_ISA_ACPI_DEVICE_ID **Device
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +IsaDeviceSetPower (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device,
> + IN BOOLEAN OnOff
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +IsaGetCurrentResource (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device,
> + OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +IsaGetPossibleResource (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device,
> + OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +IsaSetResource (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device,
> + IN EFI_ISA_ACPI_RESOURCE_LIST *ResourceList
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +IsaEnableDevice (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device,
> + IN BOOLEAN Enable
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +IsaInitDevice (
> + IN EFI_ISA_ACPI_PROTOCOL *This,
> + IN EFI_ISA_ACPI_DEVICE_ID *Device
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +LpcInterfaceInit (
> + IN EFI_ISA_ACPI_PROTOCOL *This
> +);
> +
> +VOID
> +EmptyResourceList (
> + IN UINT32 DeviceHid
> +);
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcSio.c
> b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcSio.c
> new file mode 100644
> index 0000000000..f23e48ccf2
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcSio.c
> @@ -0,0 +1,126 @@
> +/** @file
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> +Module Name:
> +
> + LpcSio.c
> +
> +Abstract: Sio implementation
> +
> +Revision History
> +
> +--*/
> +
> +#include "LpcDriver.h"
> +#include <Library/S3BootScriptLib.h>
> +
> +VOID
> +WriteRegister (
> + IN UINT8 Index,
> + IN UINT8 Data
> + );
> +
> +typedef struct {
> + UINT8 Register;
> + UINT8 Value;
> +} EFI_SIO_TABLE;
> +
> +EFI_SIO_TABLE mSioTable[] = {
> + //
> + // Init keyboard controller
> + //
> + { REG_LOGICAL_DEVICE, SIO_KEYBOARD },
> + { BASE_ADDRESS_HIGH, 0x00 },
> + { BASE_ADDRESS_LOW, 0x60 },
> + { BASE_ADDRESS_HIGH2, 0x00 },
> + { BASE_ADDRESS_LOW2, 0x64 },
> + { PRIMARY_INTERRUPT_SELECT, 0x01 },
> + { ACTIVATE, 0x1 },
> +
> + //
> + // Init Mouse controller
> + //
> + { REG_LOGICAL_DEVICE, SIO_MOUSE },
> + { BASE_ADDRESS_HIGH, 0x00 },
> + { BASE_ADDRESS_LOW, 0x60 },
> + { BASE_ADDRESS_HIGH2, 0x00 },
> + { BASE_ADDRESS_LOW2, 0x64 },
> + { PRIMARY_INTERRUPT_SELECT, 0x0c },
> + { ACTIVATE, 0x1 },
> +
> + { REG_LOGICAL_DEVICE, SIO_COM },
> + { BASE_ADDRESS_HIGH, 0x03 },
> + { BASE_ADDRESS_LOW, 0xf8 },
> + { PRIMARY_INTERRUPT_SELECT, 0x04 },
> + { ACTIVATE, 0x1 },
> +
> +
> +};
> +
> +VOID
> +LPCWPCE791SetDefault ()
> +{
> + UINT8 Index;
> +
> + for (Index = 0; Index < sizeof(mSioTable)/sizeof(EFI_SIO_TABLE); Index++)
> {
> + WriteRegisterAndSaveToScript (mSioTable[Index].Register,
> mSioTable[Index].Value);
> + }
> +
> + return;
> +}
> +
> +VOID
> +DisableLogicalDevice (
> + UINT8 DeviceId
> + )
> +{
> + WriteRegisterAndSaveToScript (REG_LOGICAL_DEVICE, DeviceId);
> + WriteRegisterAndSaveToScript (ACTIVATE, 0);
> + WriteRegisterAndSaveToScript (BASE_ADDRESS_HIGH, 0);
> + WriteRegisterAndSaveToScript (BASE_ADDRESS_LOW, 0);
> +
> + return;
> +}
> +
> +VOID
> +WriteRegister (
> + IN UINT8 Index,
> + IN UINT8 Data
> + )
> +{
> + LpcIoWrite8(CONFIG_PORT, Index);
> + LpcIoWrite8(DATA_PORT, Data);
> +
> + return;
> +}
> +
> +VOID
> +WriteRegisterAndSaveToScript (
> + IN UINT8 Index,
> + IN UINT8 Data
> + )
> +{
> + UINT8 Buffer[2];
> +
> + LpcIoWrite8(CONFIG_PORT, Index);
> + LpcIoWrite8(DATA_PORT, Data);
> +
> + Buffer[0] = Index;
> + Buffer[1] = Data;
> + S3BootScriptSaveIoWrite (
> + EfiBootScriptWidthUint8,
> + INDEX_PORT,
> + 2,
> + Buffer
> + );
> +
> + return;
> +}
> +
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcSio.h
> b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcSio.h
> new file mode 100644
> index 0000000000..52c1499e3d
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/LpcSio.h
> @@ -0,0 +1,101 @@
> +/*++
> +
> + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +
>
> +
> +Module Name:
> +
> + LpcSio.h
> +
> +Abstract:
> +
> + Lpc driver's sio interface
> +
> +
> +
> +--*/
> +
> +#ifndef _LPC_SIO_H
> +#define _LPC_SIO_H
> +
> +#include "Protocol/PciRootBridgeIo.h"
> +
> +#define VARSIOINSTALLED L"VarSIOProcotolInstalled"
> +
> +//
> +// Port address
> +//
> +#define CONFIG_PORT 0x04E
> +#define INDEX_PORT 0x04E
> +#define DATA_PORT INDEX_PORT + 1
> +
> +//
> +// Logical Device
> +//
> +#define SIO_COM 0x3
> +#define SIO_MSWC 0x4
> +#define SIO_MOUSE 0x5
> +#define SIO_KEYBOARD 0x6
> +#define SIO_SHM 0xF
> +#define SIO_PM1 0x11
> +#define SIO_PM2 0x12
> +#define SIO_PM3 0x17
> +#define SIO_ESHM 0x1D
> +
> +//
> +// Global register
> +//
> +#define REG_LOGICAL_DEVICE 0x07
> +#define REG_DEVICE_ID 0x20
> +#define SIO_CONFIG_1 0x21
> +#define REG_CHIP_REV 0x24
> +#define SIO_CONFIG_5 0x25
> +#define SIO_CONFIG_6 0x26
> +#define REG_DEVICE_REV 0x27
> +#define SIO_CONFIG_9 0x29
> +#define SIO_CONFIG_D 0x2D
> +
> +#define ACTIVATE 0x30
> +#define BASE_ADDRESS_HIGH 0x60
> +#define BASE_ADDRESS_LOW 0x61
> +#define BASE_ADDRESS_HIGH2 0x62
> +#define BASE_ADDRESS_LOW2 0x63
> +#define PRIMARY_INTERRUPT_SELECT 0x70
> +#define DMA_CHANNEL_SELECT 0x74
> +
> +EFI_STATUS
> +InitializeLpcSio (
> + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo
> + );
> +
> +//
> +// Prototypes for the sio internal function
> +//
> +//
> +// Internal function
> +//
> +VOID
> +LPCWPCE791SetDefault (
> + VOID
> + );
> +
> +VOID
> +WriteRegisterAndSaveToScript (
> + IN UINT8 Index,
> + IN UINT8 Data
> + );
> +
> +VOID
> +FloppyWriteProtect (
> + VOID
> + );
> +
> +VOID
> +DisableLogicalDevice (
> + UINT8 DeviceId
> + );
> +
> +#endif
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/Wpce791.inf
> b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/Wpce791.inf
> new file mode 100644
> index 0000000000..5fd458e265
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/Wpce791/Wpce791.inf
> @@ -0,0 +1,63 @@
> +#
> +#
> +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +#
>
> +#
> +#
> +#
> +# Module Name:
> +#
> +# SiO791.inf
> +#
> +# Abstract:
> +#
> +# Component description file for SIO791 module.
> +#
> +--*/
> +
> +[defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SIO791
> + FILE_GUID = 04A76C80-06B9-445e-B73E-CB8C61A6A964
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = LpcDriverEntryPoint
> +
> +[sources.common]
> + LpcIsaAcpi.h
> + LpcSio.h
> + LpcDriver.h
> + LpcIsaAcpi.c
> + LpcSio.c
> + LpcDriver.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Vlv2TbltDevicePkg/PlatformPkg.dec
> + IntelFrameworkPkg/IntelFrameworkPkg.dec
> + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
> + PcAtChipsetPkg/PcAtChipsetPkg.dec
> +
> +
> +[LibraryClasses]
> + UefiDriverEntryPoint
> + UefiBootServicesTableLib
> + DevicePathLib
> + UefiLib
> + S3BootScriptLib
> + DebugLib
> +
> +[Ppis]
> +
> +[Protocols]
> + gEfiPciIoProtocolGuid
> + gEfiIsaAcpiProtocolGuid
> + gEfiLpcWpce791PolicyProtocolGuid
> +
> +[Guids]
> +
> +[Depex]
> + TRUE
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/bld_vlv.bat
> b/Platform/Intel/Vlv2TbltDevicePkg/bld_vlv.bat
> new file mode 100644
> index 0000000000..d8594053b0
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/bld_vlv.bat
> @@ -0,0 +1,332 @@
> + at REM @file
> + at REM Windows batch file to build BIOS ROM
> + at REM
> + at REM Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> + at REM SPDX-License-Identifier: BSD-2-Clause-Patent
> + at REM
> +
> + at echo off
> +setlocal EnableDelayedExpansion EnableExtensions
> +echo.
> +echo %date% %time%
> +echo.
> +
> +
> +::********************************************************
> **************
> +:: Initial Setup
> +::********************************************************
> **************
> +if %WORKSPACE:~-1%==\ set WORKSPACE=%WORKSPACE:~0,-1%
> +set /a build_threads=1
> +set "Build_Flags= "
> +set exitCode=0
> +set Arch=X64
> +set Source=0
> +set PLATFORM_NAME=Vlv2TbltDevicePkg
> +
> +set CORE_PATH=%WORKSPACE%
> +if not exist %CORE_PATH%\edksetup.bat (
> + if defined PACKAGES_PATH (
> + for %%i IN (%PACKAGES_PATH%) DO (
> + if exist %%~fi\edksetup.bat (
> + set CORE_PATH=%%~fi
> + goto CorePathFound
> + )
> + )
> + ) else (
> + echo.
> + echo !!! ERROR !!! Cannot find edksetup.bat !!!
> + echo.
> + goto BldFail
> + )
> +)
> +:CorePathFound
> +
> +set PLATFORM_PACKAGE=%WORKSPACE%\%PLATFORM_NAME%
> +if not exist %PLATFORM_PACKAGE% (
> + if defined PACKAGES_PATH (
> + for %%i IN (%PACKAGES_PATH%) DO (
> + if exist %%~fi\%PLATFORM_NAME% (
> + set PLATFORM_PACKAGE=%%~fi\%PLATFORM_NAME%
> + goto PlatformPackageFound
> + )
> + )
> + ) else (
> + echo.
> + echo !!! ERROR !!! Cannot find %PLATFORM_NAME% !!!
> + echo.
> + goto BldFail
> + )
> +)
> +:PlatformPackageFound
> +
> +cd %CORE_PATH%
> +
> +:: Clean up previous build files.
> +if exist %WORKSPACE%\edk2.log del %WORKSPACE%\edk2.log
> +if exist %WORKSPACE%\unitool.log del %WORKSPACE%\unitool.log
> +if exist %WORKSPACE%\Conf\target.txt
> del %WORKSPACE%\Conf\target.txt
> +if exist %WORKSPACE%\Conf\tools_def.txt
> del %WORKSPACE%\Conf\tools_def.txt
> +if exist %WORKSPACE%\Conf\build_rule.txt
> del %WORKSPACE%\Conf\build_rule.txt
> +if exist %WORKSPACE%\Conf\.cache rmdir
> /q/s %WORKSPACE%\Conf\.cache
> +
> +:: Setup EDK environment. Edksetup puts new copies of target.txt,
> tools_def.txt, build_rule.txt in WorkSpace\Conf
> +:: Also run edksetup as soon as possible to avoid it from changing
> environment variables we're overriding
> +call %CORE_PATH%\edksetup.bat Rebuild
> + at echo off
> +
> +:: Define platform specific environment variables.
> +set config_file=%PLATFORM_PACKAGE%\PlatformPkgConfig.dsc
> +set auto_config_inc=%PLATFORM_PACKAGE%\AutoPlatformCFG.txt
> +
> +
> +
> +::create new AutoPlatformCFG.txt file
> +copy /y nul %auto_config_inc% >nul
> +
> +::********************************************************
> **************
> +:: Parse command line arguments
> +::********************************************************
> **************
> +
> +:: Optional arguments
> +:OptLoop
> +if /i "%~1"=="/?" goto Usage
> +
> +if /i "%~1"=="/l" (
> + set Build_Flags=%Build_Flags% -j EDK2.log
> + shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/y" (
> + set Build_Flags=%Build_Flags% -
> y %PLATFORM_PACKAGE%\EDK2_%PLATFORM_PACKAGE%.report
> + shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/m" (
> + if defined NUMBER_OF_PROCESSORS (
> + set /a build_threads=%NUMBER_OF_PROCESSORS%+1
> + )
> + shift
> + goto OptLoop
> +)
> +if /i "%~1" == "/c" (
> + echo Removing previous build files ...
> + if exist build (
> + del /f/s/q build > nul
> + rmdir /s/q build
> + )
> + if exist %WORKSPACE%\Conf\.cache (
> + del /f/s/q %WORKSPACE%\Conf\.cache > nul
> + rmdir /s/q %WORKSPACE%\Conf\.cache
> + )
> + echo.
> + shift
> + goto OptLoop
> +)
> +
> +if /i "%~1"=="/x64" (
> + set Arch=X64
> + shift
> + goto OptLoop
> +)
> +if /i "%~1"=="/IA32" (
> + set Arch=IA32
> + shift
> + goto OptLoop
> +)
> +
> +:: Required argument(s)
> +if "%~1"=="" goto Usage
> +
> +::Remove the values for Platform_Type and Build_Target from BiosIdX.env
> and stage in Conf\
> +if "%Arch%"=="IA32" (
> + findstr /b /v "BOARD_ID
> BUILD_TYPE" %PLATFORM_PACKAGE%\BiosIdR.env > %WORKSPACE%\Conf
> \BiosId.env
> + echo DEFINE X64_CONFIG = FALSE >> %auto_config_inc%
> +) else if "%Arch%"=="X64" (
> + findstr /b /v "BOARD_ID
> BUILD_TYPE" %PLATFORM_PACKAGE%\BiosIdx64R.env > %WORKSPACE%\C
> onf\BiosId.env
> + echo DEFINE X64_CONFIG = TRUE >> %auto_config_inc%
> +)
> +
> +:: -- Build flags settings for each Platform --
> +echo Setting %1 platform configuration and BIOS ID...
> +if /i "%~1" == "MNW2" (
> + echo BOARD_ID = MNW2MAX >> %WORKSPACE%\Conf\BiosId.env
> + echo DEFINE ENBDT_PF_BUILD = TRUE >> %auto_config_inc%
> +
> +) else (
> + echo Error - Unsupported PlatformType: %1
> + goto Usage
> +)
> +set Platform_Type=%~1
> +
> +if /i "%~2" == "RELEASE" (
> + set target=RELEASE
> + echo BUILD_TYPE = R >> %WORKSPACE%\Conf\BiosId.env
> +) else (
> + set target=DEBUG
> + echo BUILD_TYPE = D >> %WORKSPACE%\Conf\BiosId.env
> +)
> +
> +::********************************************************
> **************
> +:: Additional EDK Build Setup/Configuration
> +::********************************************************
> **************
> +echo.
> +echo Setting the Build environment for
> VS2015/VS2013/VS2012/VS2010/VS2008...
> +if defined VS140COMNTOOLS (
> + if not defined VSINSTALLDIR call "%VS140COMNTOOLS%\vsvars32.bat"
> + if /I "%VS140COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio
> 14.0\Common7\Tools\" (
> + set TOOL_CHAIN_TAG=VS2015
> + ) else (
> + set TOOL_CHAIN_TAG=VS2015x86
> + )
> +) else if defined VS120COMNTOOLS (
> + if not defined VSINSTALLDIR call "%VS120COMNTOOLS%\vsvars32.bat"
> + if /I "%VS120COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio
> 12.0\Common7\Tools\" (
> + set TOOL_CHAIN_TAG=VS2013
> + ) else (
> + set TOOL_CHAIN_TAG=VS2013x86
> + )
> +) else if defined VS110COMNTOOLS (
> + if not defined VSINSTALLDIR call "%VS110COMNTOOLS%\vsvars32.bat"
> + if /I "%VS110COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio
> 11.0\Common7\Tools\" (
> + set TOOL_CHAIN_TAG=VS2012
> + ) else (
> + set TOOL_CHAIN_TAG=VS2012x86
> + )
> +) else if defined VS100COMNTOOLS (
> + if not defined VSINSTALLDIR call "%VS100COMNTOOLS%\vsvars32.bat"
> + if /I "%VS100COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio
> 10.0\Common7\Tools\" (
> + set TOOL_CHAIN_TAG=VS2010
> + ) else (
> + set TOOL_CHAIN_TAG=VS2010x86
> + )
> +) else if defined VS90COMNTOOLS (
> + if not defined VSINSTALLDIR call "%VS90COMNTOOLS%\vsvars32.bat"
> + if /I "%VS90COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio
> 9.0\Common7\Tools\" (
> + set TOOL_CHAIN_TAG=VS2008
> + ) else (
> + set TOOL_CHAIN_TAG=VS2008x86
> + )
> +) else (
> + echo --ERROR: VS2015/VS2013/VS2012/VS2010/VS2008 not installed
> correctly.
> VS140COMNTOOLS/VS120COMNTOOLS/VS110COMNTOOLS/VS100COMNTO
> OLS/VS90COMNTOOLS not defined ^^!
> + echo.
> + goto :BldFail
> +)
> +
> +echo Ensuring correct build directory is present for GenBiosId...
> +set
> BUILD_PATH=%WORKSPACE%\Build\%PLATFORM_NAME%\%TARGET%_%T
> OOL_CHAIN_TAG%
> +
> +echo Modifing Conf files for this build...
> +:: Remove lines with these tags from target.txt
> +findstr /V "TARGET TARGET_ARCH TOOL_CHAIN_TAG BUILD_RULE_CONF
> ACTIVE_PLATFORM
> MAX_CONCURRENT_THREAD_NUMBER" %WORKSPACE%\Conf\target.txt >
> %WORKSPACE%\Conf\target.txt.tmp
> +
> +echo TARGET
> = %TARGET% >> %WORKSPACE%\Conf\target.txt.tmp
> +if "%Arch%"=="IA32" (
> + echo TARGET_ARCH =
> IA32 >> %WORKSPACE%\Conf\target.txt.tmp
> +) else if "%Arch%"=="X64" (
> + echo TARGET_ARCH = IA32
> X64 >> %WORKSPACE%\Conf\target.txt.tmp
> +)
> +echo TOOL_CHAIN_TAG
> = %TOOL_CHAIN_TAG% >> %WORKSPACE%\Conf\target.txt
> .tmp
> +echo BUILD_RULE_CONF =
> Conf/build_rule.txt >> %WORKSPACE%\Conf\target.txt.tmp
> +if %Source% == 0 (
> + echo ACTIVE_PLATFORM
> = %PLATFORM_PACKAGE%/PlatformPkg%Arch%.dsc >> %WORKSPACE%
> \Conf\target.txt.tmp
> +) else (
> + echo ACTIVE_PLATFORM
> = %PLATFORM_PACKAGE%/PlatformPkg%Arch%Source.dsc >> %WORKSPA
> CE%\Conf\target.txt.tmp
> +)
> +echo MAX_CONCURRENT_THREAD_NUMBER
> = %build_threads% >> %WORKSPACE%\Conf\target.txt.tmp
> +
> +move
> /Y %WORKSPACE%\Conf\target.txt.tmp %WORKSPACE%\Conf\target.txt >n
> ul
> +
> +::********************************************************
> **************
> +:: Build BIOS
> +::********************************************************
> **************
> +
> +echo Creating BiosId...
> +if not exist %BUILD_PATH%\IA32 mkdir %BUILD_PATH%\IA32
> +%PLATFORM_PACKAGE%\GenBiosId.exe -
> i %WORKSPACE%\Conf\BiosId.env -o %BUILD_PATH%\IA32\BiosId.bin -
> ob %WORKSPACE%\Conf\BiosId.bat
> +if "%Arch%"=="X64" (
> + if not exist %BUILD_PATH%\X64 mkdir %BUILD_PATH%\X64
> + %PLATFORM_PACKAGE%\GenBiosId.exe -
> i %WORKSPACE%\Conf\BiosId.env -o %BUILD_PATH%\X64\BiosId.bin -
> ob %WORKSPACE%\Conf\BiosId.bat
> +)
> +
> +if %ERRORLEVEL% NEQ 0 goto BldFail
> +
> +echo.
> +echo Invoking EDK2 build...
> +call build %Build_Flags%
> +
> +if %ERRORLEVEL% NEQ 0 goto BldFail
> +
> +::********************************************************
> **************
> +:: Post Build processing and cleanup
> +::********************************************************
> **************
> +
> +echo Running fce...
> +
> +pushd %PLATFORM_PACKAGE%
> +:: Extract Hii data from build and store in HiiDefaultData.txt
> +%PLATFORM_PACKAGE%\fce read -
> i %BUILD_PATH%\FV\Vlv.fd > %BUILD_PATH%\FV\HiiDefaultData.txt
> +
> +:: save changes to VlvXXX.fd
> +%PLATFORM_PACKAGE%\fce update -i %BUILD_PATH%\FV\Vlv.fd -
> s %BUILD_PATH%\FV\HiiDefaultData.txt -
> o %BUILD_PATH%\FV\Vlv%Arch%.fd
> +popd
> +
> +if %ERRORLEVEL% NEQ 0 goto BldFail
> +::echo FD successfully updated with default Hii values.
> +
> +:: Set the Board_Id, Build_Type, Version_Major, and Version_Minor
> environment variables
> +find /v "#" %WORKSPACE%\Conf\BiosId.env > ver_strings
> +for /f "tokens=1,3" %%i in (ver_strings) do set %%i=%%j
> +del /f/q ver_strings >nul
> +
> +set
> BIOS_Name=%BOARD_ID%_%Arch%_%BUILD_TYPE%_%VERSION_MAJOR%
> _%VERSION_MINOR%.ROM
> +copy
> /y/b %BUILD_PATH%\FV\Vlv%Arch%.fd %PLATFORM_PACKAGE%\Stitch\%
> BIOS_Name% >nul
> +copy
> /y/b %BUILD_PATH%\FV\Vlv%Arch%.fd %BUILD_PATH%\FV\Vlv.ROM >nul
> +
> +echo.
> +echo Build location: %BUILD_PATH%
> +echo BIOS ROM Created: %BIOS_Name%
> +echo.
> +echo -------------------- The EDKII BIOS build has successfully completed. -----
> ---------------
> +echo.
> +
> + at REM build capsule here
> +echo > %BUILD_PATH%\FV\SYSTEMFIRMWAREUPDATECARGO.Fv
> +build -p %PLATFORM_PACKAGE%\PlatformCapsule.dsc
> +
> +goto Exit
> +
> +:Usage
> +echo.
> +echo
> **********************************************************
> *****************
> +echo Build BIOS rom for VLV platforms.
> +echo.
> +echo Usage: bld_vlv.bat [options] PlatformType [Build Target]
> +echo.
> +echo /c CleanAll before building
> +echo /l Generate build log file
> +echo /y Generate build report file
> +echo /m Enable multi-processor build
> +echo /IA32 Set Arch to IA32 (default: X64)
> +echo /X64 Set Arch to X64 (default: X64)
> +echo.
> +echo Platform Types: MNW2
> +echo Build Targets: Debug, Release (default: Debug)
> +echo.
> +echo Examples:
> +echo bld_vlv.bat MNW2 : X64 Debug build for MinnowMax
> +echo bld_vlv.bat /IA32 MNW2 release : IA32 Release build for
> MinnowMax
> +echo.
> +echo
> **********************************************************
> *****************
> +set exitCode=1
> +goto Exit
> +
> +:BldFail
> +set exitCode=1
> +echo -- Error: EDKII BIOS Build has failed!
> +echo See EDK2.log for more details
> +
> +:Exit
> +echo %date% %time%
> +exit /b %exitCode%
> +
> +EndLocal
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/bld_vlv.sh
> b/Platform/Intel/Vlv2TbltDevicePkg/bld_vlv.sh
> new file mode 100644
> index 0000000000..ec3a325db7
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/bld_vlv.sh
> @@ -0,0 +1,256 @@
> +#!/usr/bin/env bash
> +##*******************************************************
> ***************
> +## Function define
> +##*******************************************************
> ***************
> +function Usage() {
> + echo
> + echo
> "**********************************************************
> *****************"
> + echo "Build BIOS rom for VLV platforms."
> + echo
> + echo "Usage: bld_vlv.bat PlatformType [Build Target]"
> + echo
> + echo
> + echo " Platform Types: MNW2"
> + echo " Build Targets: Debug, Release (default: Debug)"
> + echo
> + echo
> "**********************************************************
> *****************"
> + echo "Press any key......"
> + read
> + exit 0
> +}
> +
> +
> +echo -e $(date)
> +##*******************************************************
> ***************
> +## Initial Setup
> +##*******************************************************
> ***************
> +#WORKSPACE=$(pwd)
> +#build_threads=($NUMBER_OF_PROCESSORS)+1
> +Build_Flags=
> +exitCode=0
> +Arch=X64
> +SpiLock=0
> +
> +## Clean up previous build files.
> +if [ -e $(pwd)/EDK2.log ]; then
> + rm $(pwd)/EDK2.log
> +fi
> +
> +if [ -e $(pwd)/Unitool.log ]; then
> + rm $(pwd)/Unitool.log
> +fi
> +
> +if [ -e $(pwd)/Conf/target.txt ]; then
> + rm $(pwd)/Conf/target.txt
> +fi
> +
> +if [ -e $(pwd)/Conf/BiosId.env ]; then
> + rm $(pwd)/Conf/BiosId.env
> +fi
> +
> +if [ -e $(pwd)/Conf/tools_def.txt ]; then
> + rm $(pwd)/Conf/tools_def.txt
> +fi
> +
> +if [ -e $(pwd)/Conf/build_rule.txt ]; then
> + rm $(pwd)/Conf/build_rule.txt
> +fi
> +
> +
> +## Setup EDK environment. Edksetup puts new copies of target.txt,
> tools_def.txt, build_rule.txt in WorkSpace\Conf
> +## Also run edksetup as soon as possible to avoid it from changing
> environment variables we're overriding
> +. edksetup.sh BaseTools
> +make -C BaseTools
> +
> +## Define platform specific environment variables.
> +PLATFORM_PACKAGE=Vlv2TbltDevicePkg
> +config_file=$WORKSPACE/$PLATFORM_PACKAGE/PlatformPkgConfig.dsc
> +auto_config_inc=$WORKSPACE/$PLATFORM_PACKAGE/AutoPlatformCFG.t
> xt
> +
> +## default ECP (override with /ECP flag)
> +EDK_SOURCE=$WORKSPACE/EdkCompatibilityPkg
> +
> +## create new AutoPlatformCFG.txt file
> +if [ -f "$auto_config_inc" ]; then
> + rm $auto_config_inc
> +fi
> +touch $auto_config_inc
> +
> +##*******************************************************
> ***************
> +## Parse command line arguments
> +##*******************************************************
> ***************
> +
> +## Optional arguments
> +for (( i=1; i<=$#; ))
> + do
> + if [ "$1" == "/?" ]; then
> + Usage
> + elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/Q" ]; then
> + Build_Flags="$Build_Flags --quiet"
> + shift
> + elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/L" ]; then
> + Build_Flags="$Build_Flags -j EKD2.log"
> + shift
> + elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/C" ]; then
> + echo Removing previous build files ...
> + if [ -d "Build" ]; then
> + rm -r Build
> + fi
> + shift
> + elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/ECP" ]; then
> + ECP_SOURCE=$WORKSPACE/EdkCompatibilityPkgEcp
> + EDK_SOURCE=$WORKSPACE/EdkCompatibilityPkgEcp
> + echo DEFINE ECP_BUILD_ENABLE = TRUE >> $auto_config_inc
> + shift
> + elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/X64" ]; then
> + Arch=X64
> + shift
> + elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/YL" ]; then
> + SpiLock=1
> + shift
> + else
> + break
> + fi
> + done
> +
> +
> +
> +
> +
> +## Required argument(s)
> +if [ "$2" == "" ]; then
> + Usage
> +fi
> +
> +## Remove the values for Platform_Type and Build_Target from
> BiosIdX.env and stage in Conf
> +if [ $Arch == "IA32" ]; then
> + cp $PLATFORM_PACKAGE/BiosIdR.env Conf/BiosId.env
> + echo DEFINE X64_CONFIG = FALSE >> $auto_config_inc
> +else
> + cp $PLATFORM_PACKAGE/BiosIdx64R.env Conf/BiosId.env
> + echo DEFINE X64_CONFIG = TRUE >> $auto_config_inc
> +fi
> +sed -i '/^BOARD_ID/d' Conf/BiosId.env
> +sed -i '/^BUILD_TYPE/d' Conf/BiosId.env
> +
> +
> +
> +## -- Build flags settings for each Platform --
> +## AlpineValley (ALPV): SVP_PF_BUILD = TRUE, ENBDT_PF_BUILD =
> FALSE, TABLET_PF_BUILD = FALSE, BYTI_PF_BUILD = FALSE, IVI_PF_BUILD =
> FALSE
> +## BayleyBay (BBAY): SVP_PF_BUILD = FALSE, ENBDT_PF_BUILD = TRUE,
> TABLET_PF_BUILD = FALSE, BYTI_PF_BUILD = FALSE, IVI_PF_BUILD = FALSE
> +## BayLake (BLAK): SVP_PF_BUILD = FALSE, ENBDT_PF_BUILD = FALSE,
> TABLET_PF_BUILD = TRUE, BYTI_PF_BUILD = FALSE, IVI_PF_BUILD = FALSE
> +## Bakersport (BYTI): SVP_PF_BUILD = FALSE, ENBDT_PF_BUILD = FALSE,
> TABLET_PF_BUILD = FALSE, BYTI_PF_BUILD = TRUE, IVI_PF_BUILD = FALSE
> +## Crestview Hills (CVHS): SVP_PF_BUILD = FALSE, ENBDT_PF_BUILD =
> FALSE, TABLET_PF_BUILD = FALSE, BYTI_PF_BUILD = TRUE, IVI_PF_BUILD =
> TRUE
> +## FFD8 (BLAK): SVP_PF_BUILD = FALSE, ENBDT_PF_BUILD = FALSE,
> TABLET_PF_BUILD = TRUE, BYTI_PF_BUILD = FALSE, IVI_PF_BUILD = FALSE
> +echo "Setting $1 platform configuration and BIOS ID..."
> +if [ "$(echo $1 | tr 'a-z' 'A-Z')" == "MNW2" ]; then
> + echo BOARD_ID = MNW2MAX >> Conf/BiosId.env
> + echo DEFINE ENBDT_PF_BUILD = TRUE >> $auto_config_inc
> +else
> + echo "Error - Unsupported PlatformType: $1"
> + Usage
> +fi
> +
> +Platform_Type=$1
> +
> +if [ "$(echo $2 | tr 'a-z' 'A-Z')" == "RELEASE" ]; then
> + TARGET=RELEASE
> + BUILD_TYPE=R
> + echo BUILD_TYPE = R >> Conf/BiosId.env
> +else
> + TARGET=DEBUG
> + BUILD_TYPE=D
> + echo BUILD_TYPE = D >> Conf/BiosId.env
> +fi
> +
> +
> +##*******************************************************
> ***************
> +## Additional EDK Build Setup/Configuration
> +##*******************************************************
> ***************
> +echo "Ensuring correct build directory is present for GenBiosId..."
> +
> +echo Modifing Conf files for this build...
> +## Remove lines with these tags from target.txt
> +sed -i '/^ACTIVE_PLATFORM/d' Conf/target.txt
> +sed -i '/^TARGET /d' Conf/target.txt
> +sed -i '/^TARGET_ARCH/d' Conf/target.txt
> +sed -i '/^TOOL_CHAIN_TAG/d' Conf/target.txt
> +sed -i '/^MAX_CONCURRENT_THREAD_NUMBER/d' Conf/target.txt
> +
> +gcc_version=$(gcc -v 2>&1 | tail -1 | awk '{print $3}')
> +case $gcc_version in
> + 4.9.*|4.1[0-9].*|5.*.*|6.*.*)
> + TARGET_TOOLS=GCC49
> + ;;
> + *)
> + TARGET_TOOLS=GCC48
> + ;;
> +esac
> +
> +ACTIVE_PLATFORM=$PLATFORM_PACKAGE/PlatformPkgGcc"$Arch".dsc
> +TOOL_CHAIN_TAG=$TARGET_TOOLS
> +MAX_CONCURRENT_THREAD_NUMBER=1
> +echo ACTIVE_PLATFORM = $ACTIVE_PLATFORM >>
> Conf/target.txt
> +echo TARGET = $TARGET >> Conf/target.txt
> +echo TOOL_CHAIN_TAG = $TOOL_CHAIN_TAG >>
> Conf/target.txt
> +echo MAX_CONCURRENT_THREAD_NUMBER =
> $MAX_CONCURRENT_THREAD_NUMBER >> Conf/target.txt
> +if [ $Arch == "IA32" ]; then
> + echo TARGET_ARCH = IA32 >> Conf/target.txt
> +else
> + echo TARGET_ARCH = IA32 X64 >> Conf/target.txt
> +fi
> +
> +##*******************************************************
> ***************
> +## Build BIOS
> +##*******************************************************
> ***************
> +echo Skip "Running UniTool..."
> +echo "Make GenBiosId Tool..."
> +BUILD_PATH=Build/$PLATFORM_PACKAGE/"$TARGET"_"$TOOL_CHAIN_T
> AG"
> +if [ ! -d "$BUILD_PATH/$Arch" ]; then
> + mkdir -p $BUILD_PATH/$Arch
> +fi
> +if [ -e "$BUILD_PATH/$Arch/BiosId.bin" ]; then
> + rm -f $BUILD_PATH/$Arch/BiosId.bin
> +fi
> +
> +
> +./$PLATFORM_PACKAGE/GenBiosId -i Conf/BiosId.env -o
> $BUILD_PATH/$Arch/BiosId.bin
> +
> +
> +echo "Invoking EDK2 build..."
> +build
> +
> +if [ $SpiLock == "1" ]; then
> +
> IFWI_HEADER_FILE=./$PLATFORM_PACKAGE/Stitch/IFWIHeader/IFWI_HEA
> DER_SPILOCK.bin
> +else
> +
> IFWI_HEADER_FILE=./$PLATFORM_PACKAGE/Stitch/IFWIHeader/IFWI_HEA
> DER.bin
> +fi
> +
> +echo $IFWI_HEADER_FILE
> +
> +##*******************************************************
> ***************
> +## Post Build processing and cleanup
> +##*******************************************************
> ***************
> +
> +echo Skip "Running fce..."
> +
> +echo Skip "Running KeyEnroll..."
> +
> +## Set the Board_Id, Build_Type, Version_Major, and Version_Minor
> environment variables
> +VERSION_MAJOR=$(grep '^VERSION_MAJOR' Conf/BiosId.env | cut -d ' ' -f
> 3 | cut -c 1-4)
> +VERSION_MINOR=$(grep '^VERSION_MINOR' Conf/BiosId.env | cut -d ' ' -f
> 3 | cut -c 1-2)
> +BOARD_ID=$(grep '^BOARD_ID' Conf/BiosId.env | cut -d ' ' -f 3 | cut -c 1-7)
> +BIOS_Name="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"
> _"$VERSION_MINOR".ROM
> +BIOS_ID="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$
> VERSION_MINOR"_GCC.bin
> +SEC_VERSION=1.0.2.1060v5
> +cat
> $IFWI_HEADER_FILE ../Vlv2Binaries/Vlv2SocBinPkg/SEC/$SEC_VERSION/VLV
> _SEC_REGION.bin ../Vlv2Binaries/Vlv2SocBinPkg/SEC/$SEC_VERSION/Vacant
> .bin $BUILD_PATH/FV/VLV.fd > ./$PLATFORM_PACKAGE/Stitch/$BIOS_ID
> +
> +
> +echo Skip "Running BIOS_Signing ..."
> +
> +echo
> +echo Build location: $BUILD_PATH
> +echo BIOS ROM Created: $BIOS_Name
> +echo
> +echo -------------------- The EDKII BIOS build has successfully completed. -----
> ---------------
> +echo
> diff --git a/Platform/Intel/Vlv2TbltDevicePkg/cln.sh
> b/Platform/Intel/Vlv2TbltDevicePkg/cln.sh
> new file mode 100644
> index 0000000000..3511695f6f
> --- /dev/null
> +++ b/Platform/Intel/Vlv2TbltDevicePkg/cln.sh
> @@ -0,0 +1,62 @@
> +#!/usr/bin/env bash
> +echo
> +echo Run build cleanall...
> +echo
> +
> +echo
> +echo Directories to clean...
> +echo
> +
> +cd ..
> +
> +if [ -d "Build" ]; then
> + rm -r Build
> +fi
> +
> +if [ -d "Conf/.cache" ]; then
> + rm -r Conf/.cache
> +fi
> +
> +if [ -d "RomImages" ]; then
> + rm -r RomImages
> +fi
> +
> +echo
> +echo Files to clean...
> +echo
> +
> +if [ -e $(pwd)/EDK2.log ]; then
> + rm $(pwd)/EDK2.log
> +fi
> +
> +if [ -e $(pwd)/Unitool.log ]; then
> + rm $(pwd)/Unitool.log
> +fi
> +
> +if [ -e $(pwd)/Conf/target.txt ]; then
> + rm $(pwd)/Conf/target.txt
> +fi
> +
> +if [ -e $(pwd)/Conf/BiosId.env ]; then
> + rm $(pwd)/Conf/BiosId.env
> +fi
> +
> +if [ -e $(pwd)/Conf/tools_def.txt ]; then
> + rm $(pwd)/Conf/tools_def.txt
> +fi
> +
> +if [ -e $(pwd)/Conf/build_rule.txt ]; then
> + rm $(pwd)/Conf/build_rule.txt
> +fi
> +
> +if [ -e $(pwd)/Conf/BuildEnv.sh ]; then
> + rm $(pwd)/Conf/BuildEnv.sh
> +fi
> +
> +if [ -e $(pwd)/Vlv2TbltDevicePkg/AutoPlatformCFG.txt ]; then
> + rm $(pwd)/Vlv2TbltDevicePkg/AutoPlatformCFG.txt
> +fi
> +
> +echo
> +echo All done...
> +echo
> --
> 2.21.0.windows.1
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