[edk2-devel] [PATCH v3 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo

[Laszlo Ersek]

On 11/02/20 05:53, Sheng Wei wrote:
> Change the variable name from mInternalGr3 to mInternalCr3.
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015
> 
> Change-Id: I6a9df4836d4358405837b1ebbd2d5d4c85e3635f

With the "Change-Id" line removed:

Reviewed-by: Laszlo Ersek <lersek at redhat.com>

Thanks
Laszlo

> Signed-off-by: Sheng Wei <w.sheng at intel.com>
> Cc: Eric Dong <eric.dong at intel.com>
> Cc: Ray Ni <ray.ni at intel.com>
> Cc: Laszlo Ersek <lersek at redhat.com>
> Cc: Rahul Kumar <rahul1.kumar at intel.com>
> Cc: Jiewen Yao <jiewen.yao at intel.com>
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> index ebfc46ad45..d67f036aea 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> @@ -32,7 +32,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
>    {Page1G,  SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},
>  };
>  
> -UINTN  mInternalGr3;
> +UINTN  mInternalCr3;
>  
>  /**
>    Set the internal page table base address.
> @@ -46,7 +46,7 @@ SetPageTableBase (
>    IN UINTN   Cr3
>    )
>  {
> -  mInternalGr3 = Cr3;
> +  mInternalCr3 = Cr3;
>  }
>  
>  /**
> @@ -59,8 +59,8 @@ GetPageTableBase (
>    VOID
>    )
>  {
> -  if (mInternalGr3 != 0) {
> -    return mInternalGr3;
> +  if (mInternalCr3 != 0) {
> +    return mInternalCr3;
>    }
>    return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
>  }
> @@ -252,7 +252,7 @@ ConvertPageEntryAttribute (
>    if ((Attributes & EFI_MEMORY_RO) != 0) {
>      if (IsSet) {
>        NewPageEntry &= ~(UINT64)IA32_PG_RW;
> -      if (mInternalGr3 != 0) {
> +      if (mInternalCr3 != 0) {
>          // Environment setup
>          // ReadOnly page need set Dirty bit for shadow stack
>          NewPageEntry |= IA32_PG_D;
> 



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