[edk2-devel] [PATCH v4 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Return level paging type for Internal CR3

[Sheng Wei]

If mInternalCr3 is non zero, it will use the page table from mInternalCr3.
And it will use mInternalIs5LevelPaging to reflect the page table type.
If use page table from CR3, reflect the page table type by CR4 LA57 bit.
It is a fix for enable CET feature with 5 level paging.

PiCpuSmmEntry() will generate the page table of SMM shack memory.
If CET feature is enabled, it also includes the SMM shadows shack memory.
And we need to set some attributes on SMM shadows shack memory
 in PiCpuSmmEntry() when CET feature is enabled.
Since the page table of SMM shack memory is used in SMI entry, and it does not
 set to CR3 in PiCpuSmmEntry(). We use mInternalCr3 as page table root
 when PiCpuSmmEntry() calls ConvertMemoryPageAttributes(). We need to use
 mInternalIs5LevelPaging determining whether 5-level paging is enabled or not.
If mInternalCr3 is zero, ConvertMemoryPageAttributes() will use the page table
 in CR3, and refects the page table type by CR4 LA57 bit.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015

Signed-off-by: Sheng Wei <w.sheng at intel.com>
Cc: Eric Dong <eric.dong at intel.com>
Cc: Ray Ni <ray.ni at intel.com>
Cc: Laszlo Ersek <lersek at redhat.com>
Cc: Rahul Kumar <rahul1.kumar at intel.com>
Cc: Jiewen Yao <jiewen.yao at intel.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h         | 10 +++++
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 43 ++++++++++++++++++++--
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c            |  2 +
 3 files changed, 52 insertions(+), 3 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 7fb3a2d9e4..3eb6af62a7 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -951,6 +951,16 @@ GetPageTableBase (
   VOID
   );
 
+/**
+  This function set the internal page table type to 5 level paging or 4 level paging.
+
+  @param Is5LevelPaging TRUE means 5 level paging. FALSE means 4 level paging.
+**/
+VOID
+SetPageTableType (
+  IN BOOLEAN  Is5LevelPaging
+  );
+
 /**
   This function sets the attributes for the memory region specified by BaseAddress and
   Length from their current attributes to the attributes specified by Attributes.
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index d67f036aea..890782a394 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -33,6 +33,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
 };
 
 UINTN  mInternalCr3;
+BOOLEAN mInternalIs5LevelPaging = FALSE;
 
 /**
   Set the internal page table base address.
@@ -65,6 +66,44 @@ GetPageTableBase (
   return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
 }
 
+/**
+  This function set the internal page table type to 5 level paging or 4 level paging.
+
+  @param Is5LevelPaging TRUE means 5 level paging. FALSE means 4 level paging.
+**/
+VOID
+SetPageTableType (
+  IN BOOLEAN  Is5LevelPaging
+  )
+{
+  mInternalIs5LevelPaging = Is5LevelPaging;
+}
+
+/**
+  Return if the page table is 5 level paging.
+
+  @return TRUE  The page table base is 5 level paging.
+  @return FALSE The page table base is 4 level paging.
+**/
+STATIC
+BOOLEAN
+Is5LevelPageTableBase (
+  VOID
+  )
+{
+  IA32_CR4              Cr4;
+
+  // If mInternalCr3 is non zero, it will use the page table from mInternalCr3.
+  // And it will use mInternalIs5LevelPaging to reflect the page table type.
+  if (mInternalCr3 != 0) {
+    return mInternalIs5LevelPaging;
+  }
+
+  // If use page table from CR3, reflect the page table type by CR4 LA57 bit.
+  Cr4.UintN = AsmReadCr4 ();
+  return (BOOLEAN) (Cr4.Bits.LA57 == 1);
+}
+
 /**
   Return length according to page attributes.
 
@@ -131,7 +170,6 @@ GetPageTableEntry (
   UINT64                *L3PageTable;
   UINT64                *L4PageTable;
   UINT64                *L5PageTable;
-  IA32_CR4              Cr4;
   BOOLEAN               Enable5LevelPaging;
 
   Index5 = ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK;
@@ -140,8 +178,7 @@ GetPageTableEntry (
   Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;
   Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;
 
-  Cr4.UintN = AsmReadCr4 ();
-  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
+  Enable5LevelPaging = Is5LevelPageTableBase();
 
   if (sizeof(UINTN) == sizeof(UINT64)) {
     if (Enable5LevelPaging) {
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index 810985df20..6f2f4adb7d 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -387,6 +387,8 @@ SmmInitPageTable (
   SetSubEntriesNum (Pml4Entry, 3);
   PTEntry = Pml4Entry;
 
+  SetPageTableType(m5LevelPagingNeeded);
+
   if (m5LevelPagingNeeded) {
     //
     // Fill PML5 entry
-- 
2.16.2.windows.1



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