[edk2-devel] [edk2-platforms PATCH 1/6] Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config spaces

[Marcin Wojtas]

Until now the virtual memory map for the single PCIE configuration space
was hardcoded via PCDs and assumed adjacency to the SoC MMIO region
(0xf0000000 - 4GB). Remove this limitation by splitting the regions
and allowing to obtain the PCIE configuration space settings
from ArmadaBoardDescLib. It is a preparation patch for adding
support for multiple PCIE controllers.

Signed-off-by: Marcin Wojtas <mw at semihalf.com>
---
 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc                         |  3 ---
 Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc                       |  3 ---
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf  |  1 +
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 16 +++++++++++++++-
 4 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
index 756d875f6c..41d9cb9247 100644
--- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
@@ -100,8 +100,5 @@
   # RTC
   gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
 
-  # SoC Configuration Space
-  gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000
-
   # Variable store
   gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index d398d9432f..b1aa0ae4d0 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -400,9 +400,6 @@
   gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFF00000
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
 
-  # SoC Configuration Space
-  gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xE0000000
-
 !if $(CAPSULE_ENABLE)
 [PcdsDynamicExDefault.common.DEFAULT]
   gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
index 94427177ef..8b77a07ab3 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
@@ -20,6 +20,7 @@
   Silicon/Marvell/Marvell.dec
 
 [LibraryClasses]
+  ArmadaBoardDescLib
   ArmadaSoCDescLib
   ArmLib
   ArmSmcLib
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
index cc19694d37..853c1b4e56 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <IndustryStandard/ArmStdSmc.h>
 #include <IndustryStandard/MvSmc.h>
 
+#include <Library/ArmadaBoardDescLib.h>
 #include <Library/ArmadaSoCDescLib.h>
 #include <Library/ArmPlatformLib.h>
 #include <Library/ArmSmcLib.h>
@@ -81,6 +82,9 @@ ArmPlatformGetVirtualMemoryMap (
   UINT64                        MemHighStart;
   UINT64                        MemHighSize;
   UINT64                        ConfigSpaceBaseAddr;
+  UINTN                         PcieControllerCount;
+  UINTN                         PcieIndex;
+  MV_PCIE_CONTROLLER CONST      *PcieControllers;
   EFI_RESOURCE_ATTRIBUTE_TYPE   ResourceAttributes;
   EFI_STATUS                    Status;
 
@@ -125,12 +129,22 @@ ArmPlatformGetVirtualMemoryMap (
   mVirtualMemoryTable[Index].Length          = MemLowSize;
   mVirtualMemoryTable[Index].Attributes      = DDR_ATTRIBUTES_CACHED;
 
-  // Configuration space
+  // SoC MMIO configuration space
   mVirtualMemoryTable[++Index].PhysicalBase  = ConfigSpaceBaseAddr;
   mVirtualMemoryTable[Index].VirtualBase     = ConfigSpaceBaseAddr;
   mVirtualMemoryTable[Index].Length          = SIZE_4GB - ConfigSpaceBaseAddr;
   mVirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
+  // PCIE ECAM
+  Status = ArmadaBoardPcieControllerGet (&PcieControllers, &PcieControllerCount);
+  ASSERT_EFI_ERROR (Status);
+  for (PcieIndex = 0; PcieIndex < PcieControllerCount; PcieIndex++) {
+    mVirtualMemoryTable[++Index].PhysicalBase  = PcieControllers[PcieIndex].ConfigSpaceAddress;
+    mVirtualMemoryTable[Index].VirtualBase     = PcieControllers[PcieIndex].ConfigSpaceAddress;
+    mVirtualMemoryTable[Index].Length = SIZE_256MB;
+    mVirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+  }
+
   if (MemSize > MemLowSize) {
     //
     // If we have more than MemLowSize worth of DRAM, the remainder will be
-- 
2.29.0



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