[edk2-devel] [edk2-non-osi PATCH] SolidRun/Cn913xCEx7Eval: Add DeviceTree
Marcin Wojtas
mw at semihalf.com
Sat Aug 7 19:36:41 UTC 2021
This patch introduces the top device tree for the CN913x CEx7
Evaluation Board, based on the sources which are common for the
Cn913x SoCs. Also an .inf file is added to allow its compilation.
Signed-off-by: Marcin Wojtas <mw at semihalf.com>
---
Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf | 22 +
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts | 435 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts | 180 ++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts | 183 ++++++++
4 files changed, 820 insertions(+)
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf
new file mode 100644
index 0000000..3c99227
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf
@@ -0,0 +1,22 @@
+## @file
+#
+# Device tree description of the Marvell CN9130-DB-A platform
+#
+# Copyright (c) 2021, Semihalf. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn913xCEx7EvalDeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ cn9132-cex7.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
new file mode 100644
index 0000000..50e6d69
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
@@ -0,0 +1,435 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright SolidRun Ltd.
+ *
+ * Device tree for the CN9130 based COM Express type 7 board.
+ */
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+#include "cn9130.dtsi"
+
+/ {
+ model = "SolidRun CN9130 based COM Express type 7";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ i2c0 = &cp0_i2c0;
+ ethernet0 = &cp0_eth0; // SFP+ Port
+ ethernet1 = &cp0_eth1; // RGMII
+ ethernet2 = &cp0_eth2; // HS-SGMII
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ };
+
+ memory at 00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+ v_3_3: regulator-3-3v {
+ compatible = "regulator-fixed";
+ regulator-name = "v_3_3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ status = "okay";
+ };
+ ap0_reg_sd_vccq: ap0_sd_vccq at 0 {
+ compatible = "regulator-gpio";
+ regulator-name = "ap0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ states = <1800000 0x1 3300000 0x0>;
+ };
+
+ cp0_reg_usb3_vbus0: cp0_usb3_vbus at 0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ };
+
+ cp0_usb3_0_phy0: cp0_usb3_phy at 0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus0>;
+ };
+
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus at 1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ };
+
+ cp0_usb3_0_phy1: cp0_usb3_phy at 1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus1>;
+ };
+
+ cp0_reg_sd_vccq: cp0_sd_vccq at 0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+
+ cp0_reg_sd_vcc: cp0_sd_vcc at 0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ cp0_sfp_eth0: sfp-eth at 0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_sfp_i2c>;
+ mod-def0-gpio = <&cp0_gpio1 24 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sfp_present_pins>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&cp0_uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_uart2_pins>;
+ status = "okay";
+};
+
+/* on-board eMMC */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ bus-width = <8>;
+ vqmmc-supply = <&ap0_reg_sd_vccq>;
+ status = "okay";
+};
+
+&cp0_crypto {
+ status = "disabled";
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* SFP+ 10GE */
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-kr";
+ phys = <&cp0_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp0_sfp_eth0>;
+};
+
+/* RGMII 1GE */
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
+/* Switch uplink */
+&cp0_eth2 {
+ status = "okay";
+ phy-mode = "2500base-x";
+ phys = <&cp0_comphy5 2>;
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+};
+
+
+/* EEPROM */
+&cp0_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ clock-frequency = <100000>;
+ /* EEPROM */
+ eeprom0: eeprom at 50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+};
+
+/* I2C Master */
+&cp0_i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c1_pins>;
+
+ i2c-switch at 77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clk_gen_i2c: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*connected to clk generator*/
+ };
+ led_i2c: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* i2c_led connected to gpio expander on carrier according to com-ex type7 */
+ };
+ cp0_sfp_i2c: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /*connected to sfp cp0_eth0*/
+ };
+
+ smbus: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* smbus connected to com-ex type7 connector */
+ current_mon at 40 {
+ compatible = "ti,ina220";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40>;
+ };
+ };
+
+ therm_i2c: i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ fan-control-emc2301 at 2f {
+ compatible = "smsc,emc2305";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2f>;
+ fan at 0 {
+ reg = <0>;
+ pwm-enable = <0>;
+ fan-div = <4>;
+ };
+ };
+ };
+ };
+};
+&cp0_mdio {
+ status = "okay";
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
+ phy0: ethernet-phy at 0 {
+ marvell,reg-init = <3 16 0 0x1a4a>;
+ reg = <0>;
+ };
+
+ switch0: switch0 at 4 {
+ compatible = "marvell,mv88e6085";
+ reg = <4>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port at 1 {
+ reg = <1>;
+ label = "lan2";
+ phy-handle = <&switch0phy0>;
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan1";
+ phy-handle = <&switch0phy1>;
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan4";
+ phy-handle = <&switch0phy2>;
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "lan3";
+ phy-handle = <&switch0phy3>;
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&cp0_eth2>;
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy0: switch0phy0 at 11 {
+ reg = <0x11>;
+ };
+
+ switch0phy1: switch0phy1 at 12 {
+ reg = <0x12>;
+ };
+
+ switch0phy2: switch0phy2 at 13 {
+ reg = <0x13>;
+ };
+
+ switch0phy3: switch0phy3 at 14 {
+ reg = <0x14>;
+ };
+ };
+ };
+};
+
+/* PCIE X4 Slot */
+&cp0_pcie0 {
+ status = "okay";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy0 0
+ &cp0_comphy1 0
+ &cp0_comphy2 0
+ &cp0_comphy3 0>;
+};
+
+/* PCIE X1 Slot */
+/*
+*&cp0_pcie2 {
+* status = "okay";
+* phys = <&cp0_comphy5 2>;
+* num-lanes = <1>;
+*};
+*/
+
+/* SD Card */
+&cp0_sdhci0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins
+ &cp0_sdhci_cd_pins>;
+ bus-width = <4>;
+ cd-gpios = <&cp0_gpio2 24 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ vqmmc-supply = <&v_3_3>;
+ vmmc-supply = <&v_3_3>;
+};
+
+&cp0_spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi1_pins
+ &cp0_spi1_cs1_pins>;
+ reg = <0x700680 0x50>;
+ spi-flash at 0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <10000000>;
+ };
+ spi-flash at 1 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x1>;
+ /* On carrier MUX does not allow higher frequencies */
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_ge_mdio_pins: ge-mdio-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "ge";
+ };
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = "mpp0", "mpp1", "mpp2",
+ "mpp3", "mpp4", "mpp5",
+ "mpp6", "mpp7", "mpp8",
+ "mpp9", "mpp10", "mpp11";
+ marvell,function = "ge0";
+ };
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+ marvell,pins = "mpp55";
+ marvell,function = "sdio";
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ cp0_spi1_pins: cp0-spi-pins-1 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ cp0_spi1_cs1_pins: cp0-spi-cs1-pins-1 {
+ marvell,pins = "mpp12";
+ marvell,function = "spi1";
+ };
+
+ cp0_sfp_present_pins: sfp-present-pins {
+ marvell,pins = "mpp24";
+ marvell,function = "gpio";
+ };
+ cp0_uart2_pins: uart22-pins {
+ marvell,pins = "mpp50", "mpp51";
+ marvell,function = "uart2";
+ };
+
+ };
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts
new file mode 100644
index 0000000..7c33ff9
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright SolidRun Ltd.
+ *
+ * Device tree for the CN9131 COM Express Type 7 board.
+ */
+
+#include "cn9130-cex7.dts"
+
+/ {
+ model = "SolidRun CN9131 based COM Express type 7";
+ compatible = "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ aliases {
+ gpio3 = &cp1_gpio1;
+ gpio4 = &cp1_gpio2;
+ ethernet3 = &cp1_eth0;
+ };
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus at 0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ };
+ cp1_usb3_0_phy0: cp1_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp1_reg_usb3_vbus0>;
+ };
+ cp1_reg_usb3_vbus1: cp1_usb3_vbus at 1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp1-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ };
+ cp1_usb3_0_phy1: cp1_usb3_phy at 1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp1_reg_usb3_vbus1>;
+ };
+ cp1_sfp_eth0: sfp_eth0{
+ compatible = "sff,sfp";
+ i2c-bus = <&cp1_i2c1>;
+ mod-def0-gpio = <&cp1_gpio2 18 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_sfp_present_pins>;
+ status = "okay";
+ };
+};
+
+/* Instantiate the first slave CP115 */
+
+#define CP11X_NAME cp1
+#define CP11X_BASE f4000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x2000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f4600000
+#define CP11X_PCIE1_BASE f4620000
+#define CP11X_PCIE2_BASE f4640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp1_crypto {
+ status = "disabled";
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* 5GE PHY0 */
+&cp1_eth0 {
+ status = "okay";
+ phy-mode = "5gbase-r";
+ phys = <&cp1_comphy2 0>;
+ phy = <&phy1>;
+ sfp = <&cp1_sfp_eth0>;
+};
+
+&cp1_gpio1 {
+ status = "okay";
+};
+
+&cp1_gpio2 {
+ status = "okay";
+};
+
+&cp1_xmdio {
+ status = "okay";
+ pinctrl-0 = <&cp1_xmdio_pins>;
+ phy1: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+};
+
+&cp1_i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_i2c1_pins>;
+ clock-frequency = <100000>;
+};
+
+/* PCIE X2 NVME */
+&cp1_pcie0 {
+ pinctrl-names = "default";
+ num-lanes = <2>;
+ num-viewport = <8>;
+ status = "okay";
+ phys = <&cp1_comphy0 0
+ &cp1_comphy1 0>;
+};
+
+/* SATA 1 */
+&cp1_sata0 {
+ status = "okay";
+ sata-port at 1 {
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy3 1>;
+ };
+};
+
+/* PCIE X1 WIFI0 */
+&cp1_pcie1 {
+ pinctrl-names = "default";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ status = "okay";
+ phys = <&cp1_comphy4 1>;
+};
+
+/* PCIE X1 WIFI1 */
+&cp1_pcie2 {
+ pinctrl-names = "default";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ status = "okay";
+ phys = <&cp1_comphy5 2>;
+};
+
+/* PIN Definition */
+
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp1_i2c1_pins: cp1-i2c-pins-1 {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp1_xmdio_pins: cp1_xmdio_pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "xg";
+ };
+ cp1_sfp_present_pins: cp1_sfp_present_pins-0 {
+ marvell,pins = "mpp50";
+ marvell,function = "gpio";
+ };
+ };
+};
+
+&cp1_usb3_0 {
+ status = "okay";
+ sb-phy = <&cp1_usb3_0_phy0>;
+ phy-names = "usb";
+};
+&cp1_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp1_usb3_0_phy1>;
+ phy-names = "usb";
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts
new file mode 100644
index 0000000..aa4136c
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright SolidRun Ltd.
+ *
+ * Device tree for the CN9132 based COM Express type 7 board"
+ */
+
+#include "cn9131-cex7.dts"
+
+/ {
+ model = "SolidRun CN9132 based COM Express type 7";
+ compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ aliases {
+ gpio5 = &cp2_gpio1;
+ gpio6 = &cp2_gpio2;
+ ethernet5 = &cp2_eth0;
+ };
+
+ cp2_reg_usb3_vbus0: cp2_usb3_vbus at 0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ };
+
+ cp2_usb3_0_phy0: cp2_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus0>;
+ };
+
+ cp2_reg_usb3_vbus1: cp2_usb3_vbus at 1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ };
+
+ cp2_usb3_0_phy1: cp2_usb3_phy1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus1>;
+ };
+
+ cp2_sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp2_i2c1>;
+ mod-def0-gpio = <&cp2_gpio2 18 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_sfp_pins>;
+ status = "okay";
+ };
+};
+
+/* Instantiate the second slave CP115 */
+
+#define CP11X_NAME cp2
+#define CP11X_BASE f6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe9000000 + (iface * 0x2000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f6600000
+#define CP11X_PCIE1_BASE f6620000
+#define CP11X_PCIE2_BASE f6640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp2_crypto {
+ status = "disabled";
+};
+
+&cp2_ethernet {
+ status = "okay";
+};
+
+/* 10GE Port */
+&cp2_eth0 {
+ status = "okay";
+ phy-mode = "5gbase-r";
+ phys = <&cp2_comphy2 0>;
+ phy = <&phy2>;
+ sfp = <&cp2_sfp_eth0>;
+};
+
+&cp2_gpio1 {
+ status = "okay";
+};
+
+&cp2_gpio2 {
+ status = "okay";
+};
+
+&cp2_i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_i2c1_pins>;
+ clock-frequency = <100000>;
+};
+
+&cp2_xmdio {
+ status = "okay";
+ pinctrl-0 = <&cp2_xmdio_pins>;
+ phy2: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+};
+
+
+/* PCIE0 X1 */
+&cp2_pcie0 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ phys = <&cp2_comphy0 0>;
+};
+
+/* PCIE1 X1 */
+&cp2_pcie1 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ phys = <&cp2_comphy4 1>;
+};
+
+/* PCIE2 X1 */
+&cp2_pcie2 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ phys = <&cp2_comphy5 2>;
+};
+
+/* SATA 1 */
+&cp2_sata0 {
+ status = "okay";
+ sata-port at 0 {
+ phys = <&cp2_comphy3 1>;
+ };
+};
+
+&cp2_syscon0 {
+ cp2_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp2_xmdio_pins: cp2-xmdio-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "xg";
+ };
+
+ cp2_i2c1_pins: cp2-i2c-pins-1 {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp2_sfp_pins: sfp-pins {
+ marvell,pins = "mpp50";
+ marvell,function = "gpio";
+ };
+ };
+};
+
+&cp2_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp2_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+/* USB3 */
+&cp2_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp2_usb3_0_phy1>;
+ phy-names = "usb";
+ phys = <&cp2_comphy1 0>;
+};
--
2.29.0
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