[edk2-devel] [edk2-platforms][PATCH v2 5/5] KabylakeOpenBoardPkg/AspireVn7Dash572G: Add initial support
Nate DeSimone
nathaniel.l.desimone at intel.com
Mon Aug 16 05:21:29 UTC 2021
Hi Benjamin,
Please find my comments inline below.
Thanks,
Nate
> -----Original Message-----
> From: Benjamin Doron <benjamin.doron00 at gmail.com>
> Sent: Friday, August 13, 2021 5:25 PM
> To: devel at edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu at intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone at intel.com>; Michael Kubacki
> <michael.kubacki at microsoft.com>
> Subject: [edk2-platforms][PATCH v2 5/5]
> KabylakeOpenBoardPkg/AspireVn7Dash572G: Add initial support
>
> Add initial support for Acer Aspire VN7-572G (also, "Rayleigh"). Support
> for the somewhat similar Aspire VN7-792G ("Newgate") - using PCH-H - may
> be added in the future.
>
> This commit squashes local changes to ACPI tables, FSP configuration,
> flashmap, GPIOs and HDA verb tables.
>
> Working:
> - Board support should be taken as working at boot stage 5 - Security.
>
> Untested:
> - Dispatch mode: Until the necessary devices can be disabled or global
> reset requests are supported, dispatch mode is assumed not working.
>
> In progress:
> - ACPI and EC support in SMM.
> - Some specifics are given in the code.
>
> Additional patches:
> - VBT: https://github.com/benjamindoron/edk2-non-osi/commit/7bf736989159b74012d9bf3a13a9f941036be97a.
> Will elaborate on diff and push soon.
> - In-memory debug logging infrastructure uses libraries from
> https://github.com/benjamindoron/edk2/tree/master
>
> Not working:
> - OS drivers for the dGPU will also require ACPI _ROM method. I am
> (slowly) working on a driver to implement this.
>
> Cc: Chasel Chiu <chasel.chiu at intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
> Cc: Michael Kubacki <michael.kubacki at microsoft.com>
> Signed-off-by: Benjamin Doron <benjamin.doron00 at gmail.com>
> ---
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf | 18 +
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl | 34 +
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl | 16 +
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl | 408 +++++++++++
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl | 431 ++++++++++++
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl | 79 +++
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl | 117 ++++
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c | 17 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c | 288 ++++++++
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 7 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c | 37 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c | 18 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h | 3 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c | 5 -
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c | 7 -
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h | 15 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c | 13 -
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 21 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h | 5 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf | 60 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h | 112 +++
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.c | 662 ------------------
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.inf | 51 --
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeAspireVn7Dash572GAcpiTableLib.c | 28 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c | 12 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf | 7 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c | 43 --
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf | 49 --
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmAspireVn7Dash572GAcpiEnableLib.c | 51 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c | 17 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 8 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c | 81 ---
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf | 48 --
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 2 -
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf | 28 +
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c | 218 ++++++
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GGpioTable.c | 715 ++++++++++----------
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHdaVerbTables.c | 321 ++++-----
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHsioPtssTables.c | 97 +--
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GSpdTable.c | 541 ---------------
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GDetect.c | 133 ++--
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitLib.h | 33 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPostMemLib.c | 172 ++---
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c | 389 +++++------
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c | 11 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf | 21 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c | 29 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 41 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c | 40 --
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf | 56 --
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c | 82 ---
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf | 137 ----
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc | 213 +++++-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf | 24 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOption.dsc | 6 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 160 +++--
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c | 21 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c | 25 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c | 35 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf | 3 +-
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c | 332 +++++++++
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 41 ++
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 15 +
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py | 68 --
> Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg | 15 +-
> 65 files changed, 3548 insertions(+), 3244 deletions(-)
>
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf
> new file mode 100644
> index 000000000000..776b6de6ef3d
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf
> @@ -0,0 +1,18 @@
> +## @file
> +# Component description file for the Acer Aspire VN7-572G board ACPI tables
> +#
> +# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = BoardAcpiTables
> + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
> + MODULE_TYPE = USER_DEFINED
> + VERSION_STRING = 1.0
> +
> +[Sources]
> + BoardSsdt.asl
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl
> new file mode 100644
> index 000000000000..8d671c904c9c
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl
> @@ -0,0 +1,34 @@
> +/** @file
> + This file contains the Aspire VN7-572G SSDT Table ASL code.
> +
> +Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +DefinitionBlock (
> + "Board.aml",
> + "SSDT",
> + 0x02,
> + "ACRSKL",
> + "AcerSKL ",
> + 0x20141018
> + )
> +{
> + External (\MDBG, MethodObj)
> +
> + // Debug print helper
> + Method (DBGH, 1)
> + {
> + // If present, print to ACPI debug feature's buffer
> + If (CondRefOf (\MDBG))
> + {
> + \MDBG (Arg0)
> + }
> + // Always use "Debug" object for operating system
> + Debug = Arg0
> + }
> +
> + Include ("ec.asl")
> + Include ("mainboard.asl")
> +}
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl
> new file mode 100644
> index 000000000000..98f387a1485b
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: BSD-2-Clause-Patent */
> +
> +Device (ADP1)
> +{
> + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID
> + Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List
> +
> + Method (_PSR, 0, NotSerialized) // _PSR: Power Source
> + {
> +#ifdef LGMR_ENABLED
> + Return (MACS)
> +#else
> + Return (EACS)
> +#endif
> + }
> +}
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl
> new file mode 100644
> index 000000000000..46263670fe43
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl
> @@ -0,0 +1,408 @@
> +/* SPDX-License-Identifier: BSD-2-Clause-Patent */
> +
> +#ifndef LGMR_ENABLED
> +// TODO: Consider actually enforcing mutex?
> +Mutex (BMTX, 0)
> +#endif
> +Name (B0ST, 0) /* Battery 0 status */
> +
> +/*
> + * EC Registers
> + *
> + * "EBID" is the battery page selector.
> + *
> + *
> + * Data on the 128 bits following offset
> + * 0xE0 is accessed in the following order:
> + *
> + * Information:
> + * Page 0: EBCM # start on page 0 #
> + * Page 0: EBFC
> + * Page 1: EBDC # switch to page 1 #
> + * Page 1: EBDV
> + * Page 1: EBSN
> + * Page 3: EBDN # switch to page 3 #
> + * Page 4: EBCH # switch to page 4 #
> + * Page 2: EBMN # switch to page 2 #
> + *
> + * Status:
> + * Page 0: EBAC # start on page 0 #
> + * Page 0: EBRC
> + * Page 0: EBFC
> + * Page 0: EBVO
> + */
> +/* Page 0 */
> +Field (RAM, ByteAcc, Lock, Preserve)
> +{
> + Offset (0xE0),
> + EBRC, 16, /* Battery remaining capacity */
> + EBFC, 16, /* Battery full charge capacity */
> + EBPE, 16,
> + EBAC, 16, /* Battery present rate */
> + EBVO, 16, /* Battery voltage */
> + , 15,
> + EBCM, 1, /* Battery charging */
> + EBCU, 16,
> + EBTV, 16,
> +}
> +
> +/* Page 1 */
> +Field (RAM, ByteAcc, Lock, Preserve)
> +{
> + Offset (0xE0),
> + EBDC, 16, /* Battery design capacity */
> + EBDV, 16, /* Battery design voltage */
> + EBSN, 16, /* Battery serial number */
> +}
> +
> +/* Page 2 */
> +Field (RAM, ByteAcc, NoLock, Preserve)
> +{
> + Offset (0xE0),
> + EBMN, 128, /* Battery manufacturer */
> +}
> +
> +/* Page 3 */
> +Field (RAM, ByteAcc, NoLock, Preserve)
> +{
> + Offset (0xE0),
> + EBDN, 128, /* Battery model */
> +}
> +
> +/* Page 4 */
> +Field (RAM, ByteAcc, NoLock, Preserve)
> +{
> + Offset (0xE0),
> + EBCH, 128, /* Battery type */
> +}
> +
> +#ifdef LGMR_ENABLED
> +OperationRegion (MBB0, SystemMemory, (LGMR + 0x80), 0xFF)
> +Field (MBB0, ByteAcc, Lock, Preserve)
> +{
> + MBRC, 16,
> + MBFC, 16,
> + MBPE, 16,
> + MBAC, 16,
> + MBVO, 16,
> + , 15,
> + MBCM, 1,
> + MBCU, 16,
> + MBTV, 16,
> +}
> +
> +Field (MBB0, ByteAcc, Lock, Preserve)
> +{
> + Offset (0x10),
> + MBDC, 16,
> + MBDV, 16,
> + MBSN, 16,
> +}
> +
> +Field (MBB0, ByteAcc, Lock, Preserve)
> +{
> + Offset (0x40),
> + MBMN, 128,
> +}
> +
> +Field (MBB0, ByteAcc, Lock, Preserve)
> +{
> + Offset (0x50),
> + MBDN, 256,
> +}
> +
> +Field (MBB0, ByteAcc, Lock, Preserve)
> +{
> + Offset (0x70),
> + MBCH, 128,
> +}
> +#endif
> +
> +/*
> + * Arg0: Battery number
> + * Arg1: Battery Information Package
> + * Arg2: Status
> + */
> +#ifndef LGMR_ENABLED
> +Method (GBIF, 3, Serialized)
> +{
> + Acquire (BMTX, 0xFFFF) // Due to EC paging, don't run this with another function
> +#else
> +Method (GBIF, 3, NotSerialized)
> +{
> +#endif
> + If (Arg2)
> + {
> + Arg1[1] = 0xFFFFFFFF
> + Arg1[2] = 0xFFFFFFFF
> + Arg1[4] = 0xFFFFFFFF
> + Arg1[5] = 0
> + Arg1[6] = 0
> + }
> + Else
> + {
> +#ifdef LGMR_ENABLED
> + Local0 = MBCM
> +#else
> + EBID = 0 // We don't know which page was active
> + Local0 = EBCM
> +#endif
> + Arg1[0] = (Local0 ^ 1)
> +
> +#ifdef LGMR_ENABLED
> + Local2 = MBFC
> + Local1 = MBDC
> +#else
> + Local2 = EBFC
> + EBID = 1
> + Local1 = EBDC
> +#endif
> + If (Local0)
> + {
> + Local2 *= 10
> + Local1 *= 10
> + }
> +
> + Arg1[1] = Local1 // Design capacity
> + Arg1[2] = Local2 // Last full charge capacity
> +#ifdef LGMR_ENABLED
> + Arg1[4] = MBDV // Design voltage
> +#else
> + Arg1[4] = EBDV // Design voltage
> +#endif
> + Local6 = (Local2 / 100) // Warning capacities; Remainders ignored
> + Arg1[5] = (Local6 * 7) /* Low: 7% */
> + Arg1[6] = ((Local6 * 11) / 2) /* Very low: 5.5% */
> +#ifdef LGMR_ENABLED
> + Local7 = MBSN
> +#else
> + Local7 = EBSN
> +#endif
> + Name (SERN, Buffer (0x06) { " " })
> + Local6 = 4
> + While (Local7)
> + {
> + Divide (Local7, 10, Local5, Local7)
> + SERN[Local6] = (Local5 + 0x30) // Add ASCII 0x30 to get character
> + Local6--
> + }
> +
> + Arg1[10] = SERN // Serial number
> +#ifdef LGMR_ENABLED
> + Arg1[9] = MBDN // Model number
> + Arg1[11] = MBCH // Battery type
> + Arg1[12] = MBMN // OEM information
> +#else
> + EBID = 3
> + Arg1[9] = EBDN // Model number
> + EBID = 4
> + Arg1[11] = EBCH // Battery type
> + EBID = 2
> + Arg1[12] = EBMN // OEM information
> +#endif
> + }
> +
> +#ifndef LGMR_ENABLED
> + Release (BMTX)
> +#endif
> + Return (Arg1)
> +}
> +
> +/*
> + * Arg0: Battery number
> + * Arg1: State information
> + * Arg2: Power units
> + * Arg3: Battery Status Package
> + */
> +Method (GBST, 4, NotSerialized) // All on one page
> +{
> +#ifndef LGMR_ENABLED
> + Acquire (BMTX, 0xFFFF) // Due to EC paging, don't run this with another function
> +#endif
> + If (Arg1 & 0x02) // BIT1 in "MB0S/EB0S"
> + {
> + Local0 = 2
> + If (Arg1 & 0x20) // "EB0F"
> + {
> + Local0 = 0
> + }
> + }
> + ElseIf (Arg1 & 0x04) // BIT2 in "MB0S/EB0S"
> + {
> + Local0 = 1
> + }
> + Else
> + {
> + Local0 = 0
> + }
> +
> + If (Arg1 & 0x10) // "EB0L"
> + {
> + Local0 |= 0x04
> + }
> +
> + If (Arg1 & 1) // "EB0A"
> + {
> + /*
> + * Present rate is a 16bit signed int, positive while charging
> + * and negative while discharging.
> + */
> +#ifdef LGMR_ENABLED
> + Local1 = MBAC
> + Local2 = MBRC
> + If (MACS) // Charging
> +#else
> + EBID = 0 // We don't know which page was active
> + Local1 = EBAC
> + Local2 = EBRC
> + If (EACS) // Charging
> +#endif
> + {
> + If (Arg1 & 0x20) // "EB0F"
> + {
> +#ifdef LGMR_ENABLED
> + Local2 = MBFC
> +#else
> + Local2 = EBFC
> +#endif
> + }
> + }
> +
> + If (Arg2)
> + {
> + Local2 *= 10
> + }
> +
> +#ifdef LGMR_ENABLED
> + Local3 = MBVO
> +#else
> + Local3 = EBVO
> +#endif
> + /*
> + * The present rate value should be positive unless discharging. If so,
> + * negate present rate.
> + */
> + If (Local1 >= 0x8000)
> + {
> + If (Local0 & 1)
> + {
> + Local1 = (0x00010000 - Local1)
> + }
> + Else
> + {
> + Local1 = 0 // Full battery, force to 0
> + }
> + }
> + /*
> + * If that was not the case, we have an EC bug or inconsistency
> + * and force the value to 0.
> + */
> + ElseIf ((Local0 & 0x02) == 0)
> + {
> + Local1 = 0
> + }
> +
> + If (Arg2)
> + {
> + Local1 *= Local3
> + Local1 /= 1000 /* Remainder ignored */
> + }
> + }
> + Else
> + {
> + Local0 = 0
> + Local1 = 0xFFFFFFFF
> + Local2 = 0xFFFFFFFF
> + Local3 = 0xFFFFFFFF
> + }
> +
> + Arg3[0] = Local0
> + Arg3[1] = Local1
> + Arg3[2] = Local2
> + Arg3[3] = Local3
> +
> +#ifndef LGMR_ENABLED
> + Release (BMTX)
> +#endif
> + Return (Arg3)
> +}
> +
> +Device (BAT0)
> +{
> + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID
> + Name (_UID, 0) // _UID: Unique ID
> + Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List
> +
> + Name (B0IP, Package (0x0D)
> + {
> + 1, /* 0x00: Power Unit: mAh */
> + 0xFFFFFFFF, /* 0x01: Design Capacity */
> + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */
> + 1, /* 0x03: Battery Technology: Rechargeable */
> + 0xFFFFFFFF, /* 0x04: Design Voltage */
> + 0, /* 0x05: Design Capacity of Warning */
> + 0, /* 0x06: Design Capacity of Low */
> + 1, /* 0x07: Capacity Granularity 1 */
> + 1, /* 0x08: Capacity Granularity 2 */
> + "", /* 0x09: Model Number */
> + "100", /* 0x0a: Serial Number */
> + "Lion", /* 0x0b: Battery Type */
> + 0 /* 0x0c: OEM Information */
> + })
> + Name (B0SP, Package (0x04)
> + {
> + 0, /* 0x00: Battery State */
> + 0xFFFFFFFF, /* 0x01: Battery Present Rate */
> + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */
> + 0xFFFFFFFF /* 0x03: Battery Present Voltage */
> + })
> + Method (_STA, 0, NotSerialized) // _STA: Status
> + {
> + Local1 = EB0A
> + If (Local1 & 0x40)
> + {
> + Local1 = 0
> + }
> +
> + B0ST = Local1
> + If (Local1)
> + {
> + Return (0x1F)
> + }
> + Else
> + {
> + Return (0x0F)
> + }
> + }
> +
> + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
> + {
> + Local6 = B0ST
> + Local7 = 20
> + While (Local6 && Local7)
> + {
> + If (EB0R)
> + {
> + Local6 = 0
> + }
> + Else
> + {
> + Sleep (500)
> + Local7--
> + }
> + }
> +
> + Return (GBIF (0, B0IP, Local6))
> + }
> +
> + Method (_BST, 0, NotSerialized) // _BST: Battery Status
> + {
> + Local0 = (DerefOf (B0IP[0]) ^ 1)
> +#ifdef LGMR_ENABLED
> + Local5 = MB0S
> +#else
> + Local5 = EB0S
> +#endif
> + Return (GBST (0, Local5, Local0, B0SP))
> + }
> +}
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl
> new file mode 100644
> index 000000000000..ae4a26e543e1
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl
> @@ -0,0 +1,431 @@
> +/* SPDX-License-Identifier: BSD-2-Clause-Patent */
> +
> +/* Global TODO: TRPS, WMI, (externally: Optimus GC6 and GPS) */
> +/* TODO: Implement more features around reference code (except, check BoardAcpiDxe first) */
> +
> +// TODO: Testing
> +#undef LGMR_ENABLED
> +
> +// "DIDX" - "DeviceIdX" is uninitialised, cannot use "BRTN" method yet
> +External (\_SB.PCI0.GFX0.DD1F, DeviceObj)
> +// TODO: Might need fixed VBT - didn't port display toggle tables previously
> +External (\_SB.PCI0.GFX0.GHDS, MethodObj)
> +External (\_SB.PCI0.LPCB, DeviceObj)
> +
> +Device (\_SB.PCI0.LPCB.EC0)
> +{
> + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID
> + Name (_GPE, 0x50) // _GPE: General Purpose Events
> + Name (\ECOK, 0)
> +#ifdef LGMR_ENABLED
> + Name (LGMR, 0xFE800000) // Static, may depend on EC configuration. Unsure which register.
> +#endif
> +
> + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
> + {
> + IO (Decode16, 0x62, 0x62, 0, 1)
> + IO (Decode16, 0x66, 0x66, 0, 1)
> + })
> +
> + OperationRegion (ECO1, SystemIO, 0x62, 1)
> + Field (ECO1, ByteAcc, Lock, Preserve)
> + {
> + PX62, 8
> + }
> +
> + OperationRegion (ECO2, SystemIO, 0x66, 1)
> + Field (ECO2, ByteAcc, Lock, Preserve)
> + {
> + PX66, 8
> + }
> +
> +#ifdef LGMR_ENABLED
> + OperationRegion (ECMB, SystemMemory, LGMR, 0x200)
> +#endif
> + OperationRegion (RAM, EmbeddedControl, 0, 0xFF)
> + Field (RAM, ByteAcc, Lock, Preserve)
> + {
> + CMDB, 8, /* EC commands */
> + ETID, 8, /* Thermal page selector */
> + EBID, 8, /* Battery page selector */
> + Offset (0x06),
> + CMD2, 8, /* param 2: UNUSED */
> + CMD1, 8, /* param 1: UNUSED */
> + CMD0, 8, /* param 0 to EC command */
> + Offset (0x0A),
> + , 1,
> + , 1,
> + Offset (0x10),
> + EQEN, 1, /* EQ enable */
> + ETEE, 1, /* TODO */
> + Offset (0x4E),
> + ISEN, 1, /* TODO */
> + Offset (0x4F),
> + ECTP, 8, /* Touchpad ID */
> + Offset (0x51),
> + , 3,
> + TPEN, 1, /* Touchpad enable */
> + Offset (0x52),
> + WLEX, 1, /* WLAN present */
> + BTEX, 1, /* Bluetooth present */
> + EX3G, 1, /* 3G */
> + , 3,
> + RFEX, 1, /* RF present */
> +#if 0 // Merely a guess
> + Offset (0x55),
> + BTH0, 8, /* Battery threshold? TODO: Actually diff in modified vendor FW */
> +#endif
> + Offset (0x57),
> + , 7,
> + AHKB, 1, /* Hotkey triggered */
> + AHKE, 8, /* Hotkey data */
> + Offset (0x5C),
> + Offset (0x5D),
> + Offset (0x6C),
> + PWLT, 1, /* NVIDIA GPS: Panel? */
> + , 3,
> + GCON, 1, /* Enter Optimus GC6 */
> + Offset (0x70),
> + , 1,
> + ELID, 1, /* Lid state */
> + , 3,
> + EACS, 1, /* AC state */
> + Offset (0x71),
> + WLEN, 1, /* WLAN enable */
> + BTEN, 1, /* Bluetooth enable */
> + , 3,
> + ISS3, 1,
> + ISS4, 1,
> + ISS5, 1,
> + , 4,
> + EIDW, 1, /* Device wake */
> + Offset (0x74),
> + , 2,
> + , 1,
> + TPEX, 1, /* Touchpad present */
> + Offset (0x75),
> + BLST, 1, /* Bluetooth state */
> + LMIB, 1, /* TODO */
> + Offset (0x76),
> + ECSS, 4, /* EC Notify of power state */
> + EOSS, 4, /* EC Notify of power state */
> + Offset (0x88), /* TODO: Aliased to "EB0S" */
> + EB0A, 1,
> + , 2,
> + EB0R, 1,
> + EB0L, 1,
> + EB0F, 1,
> + EB0N, 1,
> + Offset (0x90),
> + SCPM, 1, /* Set cooling policy */
> + Offset (0x92), /* TODO: Aliased to "ETAF" */
> + ESSF, 1,
> + ECTT, 1,
> + EDTT, 1,
> + EOSD, 1, /* Trip */
> + EVTP, 1,
> + ECP1, 1,
> + , 1,
> + ECP2, 1,
> + Offset (0xA8),
> + ES0T, 8, /* Temperature */
> + ES1T, 8, /* Temperature */
> + Offset (0xD0),
> + ESP0, 8, /* Passive temp */
> + ESC0, 8, /* Critical temp */
> + ESP1, 8, /* Passive temp */
> + ESC1, 8, /* Critical temp */
> + }
> + /* Aliases several battery registers */
> + Field (RAM, ByteAcc, Lock, Preserve)
> + {
> + Offset (0x88),
> + EB0S, 8, /* Battery 0 state */
> + }
> + /* Aliases several thermal registers */
> + Field (RAM, ByteAcc, Lock, Preserve)
> + {
> + Offset (0x92),
> + ETAF, 8,
> + }
> +
> +#ifdef LGMR_ENABLED
> + Field (ECMB, ByteAcc, Lock, Preserve)
> + {
> + Offset (0x02),
> + , 1,
> + MLID, 1,
> + , 3,
> + MACS, 1,
> + Offset (0x06),
> + MBTP, 8,
> + Offset (0x08),
> + MB0S, 8,
> + Offset (0x20),
> + MS0T, 8,
> + MS1T, 8,
> + MS2T, 8,
> + MS3T, 8,
> + MS4T, 8,
> + MS5T, 8,
> + Offset (0x53),
> + MCSS, 1,
> + MCTT, 1,
> + MDTT, 1,
> + MOSD, 1,
> + MVTP, 1,
> + Offset (0x54),
> + MSP0, 8,
> + MSC0, 8,
> + MCC0, 8,
> + MSC1, 8,
> + }
> +#endif
> +
> + Method (_REG, 2, NotSerialized) // _REG: Region Availability
> + {
> + If (Arg0 == 3)
> + {
> + ECOK = Arg1 // OS can clear region availability
> + If (Arg1 == 1) // On initialise
> + {
> + TINI ()
> + EOSS = 0x05
> +// OSIN ()
> +
> + /* Other pages return valid data too, but this seems to be the page
> + * we are expecting - persistently in ectool dump with vendor firmware
> + * FIXME: Contents of other pages? */
> + ETID = 0x20
> + }
> + }
> + }
> +
> + Method (TINI, 0, NotSerialized)
> + {
> + If (ECOK)
> + {
> + ETAF = 0
> + ETEE = 1
> + }
> + Else
> + {
> + /* WBEC: Called SMI function 0x11 */
> +// EC_WRITE (0x92, 0) // ETAF = 0
> + /* MBEC: Called SMI function 0x12 */
> +// MBEC (0x10, 0xFD, 0x02) // ETEE = 1
> + }
> + }
> +
> + Name (RFST, 0) /* RF state */
> + Method (ECPS, 1, NotSerialized) // _PTS: Prepare To Sleep
> + {
> + ECSS = Arg0
> +// COSI = OSYS
> +// SPR1 = Arg0
> + /* TRPS: Generic SMI trap handler */
> +// TRPS (0x82, 0x02)
> + If ((Arg0 == 3) || (Arg0 == 4))
> + {
> + RFST = RFEX
> + }
> + }
> +
> + Method (ECWK, 1, NotSerialized) // _WAK: Wake
> + {
> + EQEN = 1
> + EOSS = Arg0
> + TINI ()
> + Notify (BAT0, 0x81) // Information Change
> +// COSI = OSYS
> +// SPR1 = Arg0
> + /* TRPS: Generic SMI trap handler */
> +// TRPS (0x82, 0x03)
> + If ((Arg0 == 3) || (Arg0 == 4))
> + {
> + RFEX = RFST
> + Notify (SLPB, 0x02) // Device Wake
> + }
> + }
> +
> +#if 0 // TODO: Figure out what this is for
> + Method (OSIN, 0, NotSerialized)
> + {
> + COSI = OSYS
> + /* TRPS: Generic SMI trap handler */
> + TRPS (0x82, 1)
> + }
> +#endif
> +
> +#if 0 // TODO: Implement
> + Method (MBEC, 3, Serialized) // Read-Modify-Write
> + {
> + /* Based on similar methods/tables at
> + * https://github.com/linuxhw/ACPI/blob/master/Notebook/Sony/SVE1713/SVE1713S1RW/506CDC50E671#L9359
> + * which use ASL instead of SMM calls */
> + Local0 = EC_READ (Arg0)
> + Local0 &= Arg1
> + Local0 |= Arg2
> + EC_WRITE (Arg0, Local0)
> + }
> +#endif
> +
> + /* Graphical hotkey */
> + Method (_Q19, 0, NotSerialized)
> + {
> + ^^^GFX0.GHDS (0x03)
> + }
> +
> + /* Increase brightness */
> + Method (_Q1C, 0, NotSerialized)
> + {
> + Notify (^^^GFX0.DD1F, 0x86)
> + }
> +
> + /* Decrease brightness */
> + Method (_Q1D, 0, NotSerialized)
> + {
> + Notify (^^^GFX0.DD1F, 0x87)
> + }
> +
> + /* Hotkeys */
> + Method (_Q2C, 0, NotSerialized)
> + {
> + If (LMIB)
> + {
> + If (!AHKB) /* Else, WMI clears its buffer? */
> + {
> + Local1 = AHKE
> + If ((Local1 > 0) && (Local1 < 0x80))
> + {
> + \DBGH ("Hotkeys - TODO: Airplane mode?")
> + /* WMI -> "GCMS" method */
> + }
> + ElseIf ((Local1 > 0x80) && (Local1 < 0xA0))
> + {
> + TPEN ^= 1 /* TODO: Not working. What else does WMI do here? */
> + }
> + }
> + }
> + }
> +
> + Method (_Q36, 0, NotSerialized)
> + {
> + If (ECOK)
> + {
> + EOSD = 1 // Thermal trip
> + }
> + Else
> + {
> + /* MBEC: Called SMI function 0x12 */
> +// MBEC (0x92, 0xF7, 0x08) // EOSD = 1
> + }
> +
> + Sleep (500)
> + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change
> + Notify (\_TZ.TZ00, 0x80) // Thermal Status Change
> + }
> +
> + Method (_Q3F, 0, NotSerialized)
> + {
> + \DBGH ("EC Query: 0x3F - TRPS")
> + /* TRPS: Generic SMI trap handler */
> +// TRPS (0x80, 0)
> + }
> +
> + Method (_Q40, 0, NotSerialized)
> + {
> + Notify (BAT0, 0x81) // Information Change
> + }
> +
> + Method (_Q41, 0, NotSerialized)
> + {
> + Notify (BAT0, 0x81) // Information Change
> + }
> +
> + /* Battery status change */
> + Method (_Q48, 0, NotSerialized)
> + {
> + Notify (BAT0, 0x80)
> + }
> +
> + /* Battery critical? */
> + Method (_Q4C, 0, NotSerialized)
> + {
> + If (B0ST)
> + {
> + Notify (BAT0, 0x80) // Status Change
> + }
> + }
> +
> + /* AC status change: present */
> + Method (_Q50, 0, NotSerialized)
> + {
> + Notify (ADP1, 0x80)
> + }
> +
> + /* AC status change: not present */
> + Method (_Q51, 0, NotSerialized)
> + {
> + Notify (ADP1, 0x80)
> + }
> +
> + /* Lid status change: open */
> + Method (_Q52, 0, NotSerialized)
> + {
> + Notify (LID0, 0x80)
> + }
> +
> + /* Lid status change: close */
> + Method (_Q53, 0, NotSerialized)
> + {
> + Notify (LID0, 0x80)
> + }
> +
> + Method (_Q60, 0, NotSerialized)
> + {
> + \DBGH ("EC Query: 0x60 -> WMI")
> + }
> +
> + Method (_Q61, 0, NotSerialized)
> + {
> + \DBGH ("EC Query: 0x61 -> WMI")
> + }
> +
> + Method (_Q62, 0, NotSerialized)
> + {
> + \DBGH ("EC Query: 0x62 -> Optimus GC6")
> + }
> +
> + Method (_Q63, 0, NotSerialized)
> + {
> + \DBGH ("EC Query: 0x63 -> Optimus GC6")
> + }
> +
> + Method (_Q67, 0, NotSerialized)
> + {
> + \DBGH ("EC Query: 0x67 -> NVIDIA GPS")
> + }
> +
> + Method (_Q68, 0, NotSerialized)
> + {
> + \DBGH ("EC Query: 0x68 -> NVIDIA GPS")
> + }
> +
> + Method (_Q6C, 0, NotSerialized)
> + {
> + \DBGH ("EC Query: 0x6C - TRPS")
> + /* TRPS: Generic SMI trap handler */
> +// TRPS (0x81, 0)
> + }
> +
> + Method (_Q6D, 0, NotSerialized)
> + {
> + \DBGH ("EC Query: 0x6D - TRPS")
> + /* TRPS: Generic SMI trap handler */
> +// TRPS (0x81, 1)
> + }
> +
> + #include "ac.asl"
> + #include "battery.asl"
> +}
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl
> new file mode 100644
> index 000000000000..572df17a9c56
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl
> @@ -0,0 +1,79 @@
> +/* SPDX-License-Identifier: BSD-2-Clause-Patent */
> +
> +// TODO: Add HID support for touchpad, etc.
> +#include "thermal.asl"
> +
> +External (\_SB.SLPB, DeviceObj)
> +
> +// TODO: Need hooks from BoardAcpiDxe
> +
> +Scope (_SB)
> +{
> + Method (MPTS, 1, NotSerialized) // _PTS: Prepare To Sleep
> + {
> + ^PCI0.LPCB.EC0.ECPS (Arg0)
> + }
> +
> + Method (MWAK, 1, Serialized) // _WAK: Wake
> + {
> + ^PCI0.LPCB.EC0.ECWK (Arg0)
> +
> + If ((Arg0 == 3) || (Arg0 == 4))
> + {
> + Notify (LID0, 0x80) // Status Change
> + }
> + }
> +
> + Method (MS0X, 1, NotSerialized) // S0ix hook. Porting "GUAM" method - "Global User Absent Mode"
> + {
> + If (Arg0 == 0)
> + {
> + /* Exit "Connected Standby" */
> +#if 1 // EC Notification
> + ^PCI0.LPCB.EC0.EOSS = 0
> +#endif
> + }
> + ElseIf (Arg0 == 1)
> + {
> + /* Enter "Connected Standby" */
> +#if 1 // EC Notification
> + ^PCI0.LPCB.EC0.ECSS = 0x08
> +#endif
> + }
> + }
> +
> + Device (LID0)
> + {
> + Name (_HID, EisaId ("PNP0C0D") /* Lid Device */) // _HID: Hardware ID
> + Method (_LID, 0, NotSerialized) // _LID: Lid Status
> + {
> +#ifdef LGMR_ENABLED
> + Return (^^PCI0.LPCB.EC0.MLID)
> +#else
> + Return (^^PCI0.LPCB.EC0.ELID)
> +#endif
> + }
> +
> + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake
> + {
> + ^^PCI0.LPCB.EC0.EIDW = Arg0
> + }
> +
> + Name (_PRW, Package () { 0x0A, 3 }) // _PRW: Power Resources for Wake
> + }
> +
> + // Add a GPE to device
> + Scope (SLPB)
> + {
> + Name (_PRW, Package () { 0x0A, 3 }) // _PRW: Power Resources for Wake
> + }
> +}
> +
> +Scope (_GPE)
> +{
> + /* TODO - Remaining Level-Triggered GPEs: PCH GPE, PCIe PME, TBT, DTS, GFX SCI and tier-2 (RTD3) */
> + Method (_L0A, 0, NotSerialized)
> + {
> + Notify (\_SB.SLPB, 0x02) // Device Wake
> + }
> +}
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl
> new file mode 100644
> index 000000000000..498c2f9c861c
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl
> @@ -0,0 +1,117 @@
> +/* SPDX-License-Identifier: BSD-2-Clause-Patent */
> +
> +Scope (_TZ)
> +{
> + Name (CRT0, 0)
> + Name (PSV0, 0)
> + ThermalZone (TZ01)
> + {
> + Method (_TMP, 0, Serialized) // _TMP: Temperature
> + {
> +#ifdef LGMR_ENABLED
> + Local0 = \_SB.PCI0.LPCB.EC0.MS0T
> +// Local1 = \_SB.PCI0.LPCB.EC0.MCSS
> + Local2 = \_SB.PCI0.LPCB.EC0.MOSD
> +#else
> + Local0 = \_SB.PCI0.LPCB.EC0.ES0T
> +// Local1 = \_SB.PCI0.LPCB.EC0.ESSF // "MCSS": Considering neighbouring bits, likely
> + // "ESSF" in thermals, not "ECSS" in notify
> + Local2 = \_SB.PCI0.LPCB.EC0.EOSD
> +#endif
> + If (Local2) // Thermal trip
> + {
> + If (Local0 <= CRT0)
> + {
> + Local0 = (CRT0 + 2)
> + }
> + }
> +
> + Return (C2K (Local0))
> + }
> +
> + Method (_CRT, 0, Serialized) // _CRT: Critical Temperature
> + {
> +#ifdef LGMR_ENABLED
> + Local0 = \_SB.PCI0.LPCB.EC0.MSC0
> +#else
> + Local0 = \_SB.PCI0.LPCB.EC0.ESC0
> +#endif
> + If ((Local0 >= 128) || (Local0 < 30))
> + {
> + Local0 = 120
> + }
> +
> + CRT0 = Local0
> + Return (C2K (Local0))
> + }
> +
> + Method (_SCP, 1, Serialized) // _SCP: Set Cooling Policy
> + {
> + If (ECOK)
> + {
> + \_SB.PCI0.LPCB.EC0.SCPM = Arg0
> + }
> + Else
> + {
> + /* MBEC: Called SMI function 0x12 */
> +// \_SB.PCI0.LPCB.EC0.MBEC (0x90, 0xFE, Arg0) // SCPM = Arg0
> + }
> + }
> +
> + Method (_PSV, 0, Serialized) // _PSV: Passive Temperature
> + {
> +#ifdef LGMR_ENABLED
> + Local0 = \_SB.PCI0.LPCB.EC0.MSP0
> +#else
> + Local0 = \_SB.PCI0.LPCB.EC0.ESP0
> +#endif
> + If ((Local0 >= 128) || (Local0 < 30))
> + {
> + Local0 = 30
> + }
> +
> + PSV0 = Local0
> + Return (C2K (Local0))
> + }
> + }
> +
> + ThermalZone (TZ00)
> + {
> + Method (_TMP, 0, Serialized) // _TMP: Temperature
> + {
> +#ifdef LGMR_ENABLED
> + Local0 = \_SB.PCI0.LPCB.EC0.MS1T
> +#else
> + Local0 = \_SB.PCI0.LPCB.EC0.ES1T
> +#endif
> + Return (C2K (Local0))
> + }
> +
> + Method (_CRT, 0, Serialized) // _CRT: Critical Temperature
> + {
> +#ifdef LGMR_ENABLED
> + Local0 = \_SB.PCI0.LPCB.EC0.MSC1
> +#else
> + Local0 = \_SB.PCI0.LPCB.EC0.ESC1
> +#endif
> + If ((Local0 >= 128) || (Local0 < 30))
> + {
> + Local0 = 120
> + }
> +
> + Return (C2K (Local0))
> + }
> + }
> +
> + Method (C2K, 1, NotSerialized)
> + {
> + Local0 = Arg0
> + If ((Local0 >= 127) || (Local0 <= 16))
> + {
> + Local0 = 30
> + }
> +
> + Local0 = ((Local0 * 10) + 2732) // Celsius to Kelvin
> + Return (Local0)
> + }
> +}
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c
> index 155dfdaf623f..205ca581c6f3 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c
> @@ -7,25 +7,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include "PeiPchPolicyUpdate.h"
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/HobLib.h>
> -#include <Guid/GlobalVariable.h>
> -#include <Library/PchGbeLib.h>
> -#include <Library/PchInfoLib.h>
> -#include <Library/PchPcrLib.h>
> -#include <Library/PchHsioLib.h>
> -#include <Library/PchSerialIoLib.h>
> #include <Library/PchPcieRpLib.h>
> -#include <GpioConfig.h>
> -#include <GpioPinsSklH.h>
> -#include <Library/DebugLib.h>
> -#include <Library/PchGbeLib.h>
>
> #define PCI_CLASS_NETWORK 0x02
> #define PCI_CLASS_NETWORK_ETHERNET 0x00
> #define PCI_CLASS_NETWORK_OTHER 0x80
>
> +/* BUGBUG: Tested, table entries cannot configure PCI config space
I think it would be a good idea to file a Bugzilla for this. Could you please do so?
> + * - FspsUpd.h: "only used in PostMem phase" */
> +
> GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
> //
> // Intel PRO/Wireless
> @@ -112,4 +102,3 @@ GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
> //
> { 0 }
> };
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c
> new file mode 100644
> index 000000000000..8bbf6c7480c1
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c
> @@ -0,0 +1,288 @@
A lot of this code in this file demonstrates that is probably makes sense to create a top level PolicyUpdateLib in KabylakeOpenBoardPkg that the various board ports import because most of these settings look either identical to RVP3/GalagoPro3 or they come from PCDs and hence the code will always be generic.
Definitely not something you need to do for this patch series, but something to think about for a future enhancement.
> +/** @file
> + This file configures Aspire VN7-572G board-specific FSP UPDs.
> +
> +Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "PeiPchPolicyUpdate.h"
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <PchPolicyCommon.h>
> +
> +/* TODO:
> + * - Validate Sample policies: only one used by default.
> + * - Remove likely fuse-disabled devices when reset handling is committed?
> + * - Remove duplicate policy
> + * - Consider updating some policies, rather than overriding. This could be factored into
> + * BoardInitLib for deduplication
> + * - Copy initialised array, where sane
> + * - Set IgdDvmt50PreAlloc? */
> +
> +#define SA_VR 0
> +#define IA_VR 1
> +#define GT_UNSLICED_VR 2
> +#define GT_SLICED_VR 3
> +
> +/**
> + Performs the remainder of board-specific FSP Policy initialization.
> +
> + @param[in][out] FspmUpd Pointer to FSP UPD Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspBoardPolicyUpdatePreMem (
> + IN OUT FSPM_UPD *FspmUpd
> + )
> +{
> + DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));
> +
> + // BUGBUG: Preserve FSP defaults - PeiSiliconPolicyInitLibFsp ultimately overrides to 0.
> + FspmUpd->FspmConfig.PchHpetBusNumber = 0xF0;
> + FspmUpd->FspmConfig.PchHpetDeviceNumber = 0x1F;
> +// FspmUpd->FspmConfig.PchHpetFunctionNumber = 0;
I find the whole situation with PchHpetBusNumber, PchHpetBusDeviceNumber, PchHpetFunctionNumber, PchHpetBdfValid to be very odd.
I looked though the FSP source code to see what these policy options do and it boils down to if(PchHpetBdfValid) then the FSP will program the following register:
https://edc.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/comet-lake-u/intel-400-series-chipset-on-package-platform-controller-hub-register-database/hpet-bus-device-function-hbdf-offset-70/
I can confirm that in the FSP source code that the default FSP UPD values differ from the default config block values. Moreover, the reference BIOS takes the config blocks and converts them into FSP UPDs just like the open source code, so most of the testing for KBL FSP was actually done without the default UPD values. We consider cases like this where the UPD and the config block defaults don't match to be a bug, but given the age of the KBL FSP getting that bug fixed is difficult at this point.
Have you tried booting these settings?
PchHpetBdfValid = 0
PchHpetBusNumber = 0
PchHpetBusDeviceNumber = 0
PchHpetFunctionNumber = 0
That is what the reference BIOS uses.
The equivalent UPD and Config Block defaults for I/O APIC do match.
> + FspmUpd->FspmConfig.PeciC10Reset = 1;
The default for PeciC10Reset should totally be 1. Good catch!
I have created a patch to fix the properly. Please merge https://edk2.groups.io/g/devel/message/79328
Then we should be able to remove this line.
> + FspmUpd->FspmConfig.RefClk = 1; // Maybe "auto" is safe, but that isn't the FSP default
> +
> + // TODO: Why should this be here?
> + FspmUpd->FspmConfig.TsegSize = PcdGet32 (PcdTsegSize);
> + // FSP should program it's default BDF value
> + FspmUpd->FspmConfig.PchHpetBdfValid = 1;
> +
> + /* System Agent config */
> + FspmUpd->FspmConfig.UserBd = PcdGet8 (PcdSaMiscUserBd);
> + FspmUpd->FspmConfig.DqPinsInterleaved = (UINT8) PcdGetBool (PcdMrcDqPinsInterleaved);
> + FspmUpd->FspmConfig.CaVrefConfig = PcdGet8 (PcdMrcCaVrefConfig);
> + FspmUpd->FspmConfig.SaGv = 3; // Enabled
> +
> + /* iGFX config */
> + FspmUpd->FspmConfig.PrimaryDisplay = 4; // Switchable Graphics
> +
> + /* PCIe config */
> + FspmUpd->FspmConfig.PcieRpEnableMask = 0x341; // Ports 1, 7, 9 and 10
> +
> + DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Performs the remainder of board-specific FSP Policy initialization.
> +
> + @param[in][out] FspsUpd Pointer to FSP UPD Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspBoardPolicyUpdate (
> + IN OUT FSPS_UPD *FspsUpd
> + )
> +{
> + INTN i;
> +
> + DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));
> +
> + // FIXME/NB: This is insecure and not production-ready!
> + // TODO: Configure SPI lockdown by variable on FrontPage?
> + // Later, also configure stronger protection: PRRs
> + FspsUpd->FspsConfig.PchLockDownBiosLock = 0; // Default. Enable, don't remove setting
> + FspsUpd->FspsConfig.PchLockDownSpiEiss = 0;
This is OK for your initial patch series but please make sure work on a follow up patch series that moves this to a setup option since it is insecure to have this be the default.
> + // This may be PWRM+0x18[BIT22], causing HSTI "PCH Security Configuration - Reserved Check failure"
> + // I think the intel_pmc_core kernel module requires this to populate debugfs?
> + FspsUpd->FspsTestConfig.PchPmPmcReadDisable = 0;
> +
> + // BUGBUG: Preserve FSP defaults - Pei*PolicyLib ultimately overrides
> + FspsUpd->FspsConfig.PchIoApicBusNumber = 0xF0;
> + FspsUpd->FspsConfig.PchIoApicDeviceNumber = 0x1F;
> +// FspsUpd->FspsConfig.PchIoApicFunctionNumber = 0;
> + // Requires HW support?
> + FspsUpd->FspsConfig.PchPmSlpS0VmEnable = 0;
>From what I remember the VN-572G only supports S3 and not S0ix. In which case setting PchPmSlpS0VmEnable = 0 would be mandatory because that feature only works in S0ix mode. Historically most systems with switchable graphics have opted for S3 instead of S0ix because power state transitions are more difficult to implement correctly in S0ix.
Please add a comment that describes this.
> + // Do not clear UART2, may be set by PeiPchPolicyUpdate.c:PeiFspPchPolicyUpdate()
> + // - Presently always set to PCI by policy
> + ZeroMem (&FspsUpd->FspsConfig.SerialIoDevMode, sizeof(FspsUpd->FspsConfig.SerialIoDevMode)-1);
> + // I2C controllers are PCI
> + // - Board has no GPIO expander on I2C4 (despite SetupUtility claim that it does - this would be static text)
> + FspsUpd->FspsConfig.SerialIoDevMode[0] = 2;
> + FspsUpd->FspsConfig.SerialIoDevMode[1] = 2;
> +
> + // TODO: Why should this be here?
> + // FSP should program it's default BDF value
> + FspsUpd->FspsConfig.PchIoApicBdfValid = 1;
> +
> + // Acer IDs (TODO: "Newgate" IDs)
> + FspsUpd->FspsConfig.DefaultSvid = 0x1025;
> + FspsUpd->FspsConfig.DefaultSid = 0x1037;
> + FspsUpd->FspsConfig.PchSubSystemVendorId = 0x1025;
> + FspsUpd->FspsConfig.PchSubSystemId = 0x1037;
> +
> + /* System Agent config */
> + // Set the Thermal Control Circuit (TCC) activation value to 97C
> + // even though FSP integration guide says to set it to 100C for SKL-U
> + // (offset at 0), because when the TCC activates at 100C, the CPU
> + // will have already shut itself down from overheating protection.
> + FspsUpd->FspsTestConfig.TccActivationOffset = 3;
> +
> + // VR Slew rate setting for improving audible noise
> + FspsUpd->FspsConfig.AcousticNoiseMitigation = 1;
> + FspsUpd->FspsConfig.SlowSlewRateForIa = 3; // Fast/16
> + FspsUpd->FspsConfig.SlowSlewRateForGt = 3; // Fast/16
> + FspsUpd->FspsConfig.SlowSlewRateForSa = 0; // Fast/2
> + FspsUpd->FspsConfig.FastPkgCRampDisableIa = 0;
> + FspsUpd->FspsConfig.FastPkgCRampDisableGt = 0;
> + FspsUpd->FspsConfig.FastPkgCRampDisableSa = 0;
> +
> + // VR domain configuration (copied from board port, before VR config moved
> + // to SoC. Should match SKL-U (GT2, 15W) in the SKL-U datasheet, vol. 1)
> + FspsUpd->FspsConfig.AcLoadline[SA_VR] = 1030; // 10.3mOhm (in 1/100 increments)
> + FspsUpd->FspsConfig.DcLoadline[SA_VR] = 1030; // 10.3mOhm (in 1/100 increments)
> + FspsUpd->FspsConfig.Psi1Threshold[SA_VR] = 80; // 20A (in 1/4 increments)
> + FspsUpd->FspsConfig.Psi2Threshold[SA_VR] = 16; // 4A (in 1/4 increments)
> + FspsUpd->FspsConfig.Psi3Threshold[SA_VR] = 4; // 1A (in 1/4 increments)
> + FspsUpd->FspsConfig.IccMax[SA_VR] = 18; // 4.5A (in 1/4 increments)
> + FspsUpd->FspsConfig.VrVoltageLimit[SA_VR] = 1520; // 1520mV
> +
> + FspsUpd->FspsConfig.AcLoadline[IA_VR] = 240; // 2.4mOhm (in 1/100 increments)
> + FspsUpd->FspsConfig.DcLoadline[IA_VR] = 240; // 2.4mOhm (in 1/100 increments)
> + FspsUpd->FspsConfig.Psi1Threshold[IA_VR] = 80; // 20A (in 1/4 increments)
> + FspsUpd->FspsConfig.Psi2Threshold[IA_VR] = 20; // 5A (in 1/4 increments)
> + FspsUpd->FspsConfig.Psi3Threshold[IA_VR] = 4; // 1A (in 1/4 increments)
> + FspsUpd->FspsConfig.IccMax[IA_VR] = 116; // 29A (in 1/4 increments)
> + FspsUpd->FspsConfig.VrVoltageLimit[IA_VR] = 1520; // 1520mV
> +
> + FspsUpd->FspsConfig.AcLoadline[GT_UNSLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
> + FspsUpd->FspsConfig.DcLoadline[GT_UNSLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
> + FspsUpd->FspsConfig.Psi1Threshold[GT_UNSLICED_VR] = 80; // 20A (in 1/4 increments)
> + FspsUpd->FspsConfig.Psi2Threshold[GT_UNSLICED_VR] = 20; // 5A (in 1/4 increments)
> + FspsUpd->FspsConfig.Psi3Threshold[GT_UNSLICED_VR] = 4; // 1A (in 1/4 increments)
> + FspsUpd->FspsConfig.IccMax[GT_UNSLICED_VR] = 124; // 31A (in 1/4 increments)
> + FspsUpd->FspsConfig.VrVoltageLimit[GT_UNSLICED_VR] = 1520; // 1520mV
> +
> + FspsUpd->FspsConfig.AcLoadline[GT_SLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
> + FspsUpd->FspsConfig.DcLoadline[GT_SLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
> + FspsUpd->FspsConfig.Psi1Threshold[GT_SLICED_VR] = 80; // 20A (in 1/4 increments)
> + FspsUpd->FspsConfig.Psi2Threshold[GT_SLICED_VR] = 20; // 5A (in 1/4 increments)
> + FspsUpd->FspsConfig.Psi3Threshold[GT_SLICED_VR] = 4; // 1A (in 1/4 increments)
> + FspsUpd->FspsConfig.IccMax[GT_SLICED_VR] = 124; // 31A (in 1/4 increments)
> + FspsUpd->FspsConfig.VrVoltageLimit[GT_SLICED_VR] = 1520; // 1520mV
> +
> + // PL1, PL2 override 35W, PL4 override 43W (converted to processor units, then 125 mW increments)
> + // BUGBUG: PL1 and PL2 not being configured in MSR 0x610. Requires additional UPD?
> + FspsUpd->FspsTestConfig.PowerLimit1 = 35000;
> + FspsUpd->FspsTestConfig.PowerLimit2Power = 35000;
> + FspsUpd->FspsTestConfig.PowerLimit4 = 43000;
> +
> + // ISL95857 VR
> + // Send VR specific command for PS4 exit issue
> + FspsUpd->FspsConfig.SendVrMbxCmd1 = 2;
> + // Send VR mailbox command for IA/GT/SA rails
> + FspsUpd->FspsConfig.IslVrCmd = 2;
> +
> + /* Skycam config */
> + FspsUpd->FspsConfig.SaImguEnable = 0;
> + FspsUpd->FspsConfig.PchCio2Enable = 0;
> +
> + /* Sensor hub config */
> + FspsUpd->FspsConfig.PchIshEnable = 0;
> +
> + /* xHCI config */
> + FspsUpd->FspsConfig.SsicPortEnable = 0;
> + // Configure USB2 ports in two sets
> + for (i = 0; i < 3; i++) {
Please create a #define for "3" that describes why these settings are significant for only the first 3 USB2 ports.
Also, using a variable called "i" as the index variable of a for loop does not comply with EDK II coding style guidelines, please use "Index" instead.
> + FspsUpd->FspsConfig.Usb2AfeTxiset[i] = 0x2; // 16.9mV
> + FspsUpd->FspsConfig.Usb2AfePredeemp[i] = 1; // De-emphasis on
> + FspsUpd->FspsConfig.Usb2AfePetxiset[i] = 0x3; // 28.15mV
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[i] = 1; // Half-bit
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[i] = PchUsbOverCurrentPinSkip;
> + }
> + for (i = 3; i < 9; i++) {
Please create a #define for "9" that describes why these settings are significant for USB2 ports 3-9.
Also, using a variable called "i" as the index variable of a for loop does not comply with EDK II coding style guidelines, please use "Index" instead.
> + FspsUpd->FspsConfig.Usb2AfeTxiset[i] = 0; // 0mV
> + FspsUpd->FspsConfig.Usb2AfePredeemp[i] = 0x2; // Pre-emphasis and de-emphasis on
> + FspsUpd->FspsConfig.Usb2AfePetxiset[i] = 0x7; // 56.3mV
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[i] = 1; // Half-bit
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[i] = PchUsbOverCurrentPinSkip;
> + }
> + // Configure all USB3 ports
> + for (i = 0; i < 4; i++) {
Please create a #define for the number of populated USB3 ports.
Also, using a variable called "i" as the index variable of a for loop does not comply with EDK II coding style guidelines, please use "Index" instead.
> + FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[i] = 1;
> + FspsUpd->FspsConfig.Usb3HsioTxDeEmph[i] = 0x29; // Default (approximately -3.5dB de-emphasis)
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[i] = PchUsbOverCurrentPinSkip;
> + }
> + // Disable supported, but not present, ports
> + for (i = 9; i < 12; i++) {
Please use PCH_LP_XHCI_MAX_USB2_PORTS instead of 12.
Also, using a variable called "i" as the index variable of a for loop does not comply with EDK II coding style guidelines, please use "Index" instead.
> + FspsUpd->FspsConfig.PortUsb20Enable[i] = 0;
> + }
> + for (i = 4; i < 6; i++) {
Please use PCH_LP_XHCI_MAX_USB3_PORTS instead of 6.
Also, using a variable called "i" as the index variable of a for loop does not comply with EDK II coding style guidelines, please use "Index" instead.
> + FspsUpd->FspsConfig.PortUsb30Enable[i] = 0;
> + }
> +
> + /* xDCI config */
> + FspsUpd->FspsConfig.XdciEnable = 0;
> +
> + /* SATA config */
> + // This is a hard silicon requirement, discovered several times by coreboot boards
> + FspsUpd->FspsConfig.SataPwrOptEnable = 1;
> + // Disable supported, but not present, ports
> + FspsUpd->FspsConfig.SataPortsEnable[0] = 0;
> +
> + /* PCIe config */
> + // Port 1 (dGPU; x4)
> + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[0] = 1;
> + FspsUpd->FspsConfig.PcieRpLtrEnable[0] = 1;
> + FspsUpd->FspsConfig.PcieRpClkReqSupport[0] = 1;
> + FspsUpd->FspsConfig.PcieRpClkReqNumber[0] = 0;
> + FspsUpd->FspsConfig.PcieRpMaxPayload[0] = PchPcieMaxPayload256;
> + FspsUpd->FspsConfig.PcieRpClkSrcNumber[0] = 0x1F; // CLKSRC pin invalid
> + // Port 7 (NGFF; x2)
> + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[6] = 1;
> + FspsUpd->FspsConfig.PcieRpLtrEnable[6] = 1;
> + FspsUpd->FspsConfig.PcieRpClkReqSupport[6] = 1;
> + FspsUpd->FspsConfig.PcieRpClkReqNumber[6] = 3;
> + FspsUpd->FspsConfig.PcieRpMaxPayload[6] = PchPcieMaxPayload256;
> + FspsUpd->FspsConfig.PcieRpClkSrcNumber[6] = 0x1F; // CLKSRC pin invalid
> + // Port 9 (LAN)
> + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[8] = 1;
> + FspsUpd->FspsConfig.PcieRpLtrEnable[8] = 1;
> + FspsUpd->FspsConfig.PcieRpClkReqSupport[8] = 1;
> + FspsUpd->FspsConfig.PcieRpClkReqNumber[8] = 1;
> + FspsUpd->FspsConfig.PcieRpMaxPayload[8] = PchPcieMaxPayload256;
> + FspsUpd->FspsConfig.PcieRpClkSrcNumber[8] = 0x1F; // CLKSRC pin invalid
> + // Port 10 (WLAN)
> + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[9] = 1;
> + FspsUpd->FspsConfig.PcieRpLtrEnable[9] = 1;
> + FspsUpd->FspsConfig.PcieRpClkReqSupport[9] = 1;
> + FspsUpd->FspsConfig.PcieRpClkReqNumber[9] = 2;
> + FspsUpd->FspsConfig.PcieRpMaxPayload[9] = PchPcieMaxPayload256;
> + FspsUpd->FspsConfig.PcieRpClkSrcNumber[9] = 0x1F; // CLKSRC pin invalid
> + // ASPM L0s is broken/unsupported on Qualcomm Atheros QCA6174 (AER: corrected errors)
> + // BUGBUG: PcieDeviceTable.c entries aren't setting PCI config space
> + FspsUpd->FspsConfig.PcieRpAspm[9] = PchPcieAspmL1;
> +
> + /* SCS config */
> + // Although platform NVS area shows this enabled, the SD card reader is connected over USB, not SCS
> + FspsUpd->FspsConfig.ScsEmmcEnabled = 0;
> + FspsUpd->FspsConfig.ScsSdCardEnabled = 0;
> +
> + /* LPC config */
> + // EC/KBC requires continuous mode
> + FspsUpd->FspsConfig.PchPmLpcClockRun = 1;
> + FspsUpd->FspsConfig.PchSirqMode = PchContinuousMode;
> +
> + /* HDA config */
> + // FIXME: DspEnable is set, per PeiPchPolicyLib, however it is disabled in the HOB produced by FSP
> + // Returned to DXE as HOB, used to select blob for NHLT
> + FspsUpd->FspsConfig.PchHdaDspEndpointDmic = PchHdaDmic1chArray;
> +
> + /* GbE config */
> + FspsUpd->FspsConfig.PchLanEnable = 0;
> +
> + DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
> index d8aff1960f0b..d8413d284e37 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
> @@ -9,17 +9,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <PiPei.h>
>
> #include <Library/DebugLib.h>
> +#include <Library/PciLib.h>
> #include <Library/PeiLib.h>
> -#include <Library/ConfigBlockLib.h>
>
> #include <FspEas.h>
> #include <FspmUpd.h>
> #include <FspsUpd.h>
>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/DebugPrintErrorLevelLib.h>
> -#include <Library/PciLib.h>
> #include <Guid/MemoryOverwriteControl.h>
> #include <PchAccess.h>
>
> @@ -84,4 +80,3 @@ PeiFspMiscUpdUpdatePreMem (
>
> return EFI_SUCCESS;
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
> index 55be16265e99..76dd837dd57c 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
> @@ -7,10 +7,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include <PiPei.h>
> -#include <Library/PcdLib.h>
> #include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> #include <Library/FspWrapperApiLib.h>
> #include <Library/SiliconPolicyUpdateLib.h>
>
> @@ -91,6 +88,36 @@ PeiFspSaPolicyUpdate (
> IN OUT FSPS_UPD *FspsUpd
> );
>
> +/**
> + Performs the remainder of board-specific FSP Policy initialization.
> +
> + @param[in][out] FspmUpd Pointer to FSP UPD Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspBoardPolicyUpdatePreMem (
> + IN OUT FSPM_UPD *FspmUpd
> + );
> +
> +/**
> + Performs the remainder of board-specific FSP Policy initialization.
> +
> + @param[in][out] FspsUpd Pointer to FSP UPD Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspBoardPolicyUpdate (
> + IN OUT FSPS_UPD *FspsUpd
> + );
> +
> VOID
> InternalPrintVariableData (
> IN UINT8 *Data8,
> @@ -140,6 +167,7 @@ SiliconPolicyUpdatePreMem (
> PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr);
> PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr);
> PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr);
> + PeiFspBoardPolicyUpdatePreMem (FspmUpdDataPtr);
>
> InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD));
>
> @@ -177,10 +205,9 @@ SiliconPolicyUpdatePostMem (
> FspsUpdDataPtr = FspsUpd;
> PeiFspSaPolicyUpdate (FspsUpdDataPtr);
> PeiFspPchPolicyUpdate (FspsUpdDataPtr);
> + PeiFspBoardPolicyUpdate (FspsUpdDataPtr);
>
> InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD));
>
> return FspsUpd;
> }
> -
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
> index b469720ac657..758deee47603 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
> @@ -9,18 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include "PeiPchPolicyUpdate.h"
> #include <Library/BaseMemoryLib.h>
> #include <Library/MemoryAllocationLib.h>
> -#include <Library/HobLib.h>
> -#include <Guid/GlobalVariable.h>
> -#include <Library/PchGbeLib.h>
> -#include <Library/PchInfoLib.h>
> -#include <Library/PchPcrLib.h>
> -#include <Library/PchHsioLib.h>
> #include <Library/PchSerialIoLib.h>
> -#include <Library/PchPcieRpLib.h>
> -#include <GpioConfig.h>
> -#include <GpioPinsSklH.h>
> -#include <Library/DebugLib.h>
> -#include <Library/PchGbeLib.h>
>
> extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[];
>
> @@ -103,6 +92,7 @@ InternalAddPlatformVerbTables (
> InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable));
> InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2));
> InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
> + DEBUG ((DEBUG_INFO, "HDA: No external codecs to install!\n"));
> }
> } else {
> DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n"));
> @@ -133,15 +123,12 @@ PeiFspPchPolicyUpdate (
> IN OUT FSPS_UPD *FspsUpd
> )
> {
> -
> - FspsUpd->FspsConfig.PchSubSystemVendorId = V_PCH_INTEL_VENDOR_ID;
> - FspsUpd->FspsConfig.PchSubSystemId = V_PCH_DEFAULT_SID;
> -
> FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable;
>
> InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard, PcdGet8 (PcdAudioConnector));
>
> DEBUG_CODE_BEGIN();
> +// FIXME: Policy sets to PCI
> if ((PcdGet8 (PcdSerialIoUartDebugEnable) == 1) &&
> FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled ) {
> FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoLegacyUart;
> @@ -150,4 +137,3 @@ DEBUG_CODE_END();
>
> return EFI_SUCCESS;
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
> index 30d2f99e1dde..5e720b0041e8 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
> @@ -16,9 +16,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #include <Library/DebugLib.h>
> #include <Library/IoLib.h>
> -#include <Library/PciLib.h>
> -#include <Ppi/SiPolicy.h>
> #include <Library/MmPciLib.h>
> +#include <Ppi/SiPolicy.h>
>
> #include <FspEas.h>
> #include <FspmUpd.h>
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
> index f6390ee12c17..2bc142c0e5ff 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
> @@ -8,15 +8,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #include "PeiPchPolicyUpdate.h"
> #include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> -#include <Library/HobLib.h>
> -#include <Guid/GlobalVariable.h>
> #include <Library/PchInfoLib.h>
> #include <Library/PchPcrLib.h>
> #include <Library/PchHsioLib.h>
> #include <Library/PchPcieRpLib.h>
> #include <PchHsioPtssTables.h>
> -#include <Library/DebugLib.h>
>
> VOID
> InstallPlatformHsioPtssTable (
> @@ -245,4 +241,3 @@ PeiFspPchPolicyUpdatePreMem (
> InstallPlatformHsioPtssTable (FspmUpd);
> return EFI_SUCCESS;
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
> index d6ec3e38dd7e..4621cbd3ca3a 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
> @@ -7,12 +7,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include "PeiSaPolicyUpdate.h"
> -#include <Guid/MemoryTypeInformation.h>
> -#include <Library/HobLib.h>
> -#include <PchAccess.h>
> -#include <SaAccess.h>
> -#include <Pi/PiFirmwareFile.h>
> -#include <Pi/PiPeiCis.h>
> #include <Library/BaseMemoryLib.h>
> #include <Library/MemoryAllocationLib.h>
> #include <Library/PeiSaPolicyLib.h>
> @@ -81,4 +75,3 @@ PeiFspSaPolicyUpdate (
>
> return EFI_SUCCESS;
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
> index 3abf3fc8fd2f..84910af67720 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
> @@ -12,19 +12,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> // External include files do NOT need to be explicitly specified in real EDKII
> // environment
> //
> -#include <SaPolicyCommon.h>
> -#include <Library/DebugPrintErrorLevelLib.h>
> -#include <CpuRegs.h>
> -#include <Library/CpuPlatformLib.h>
> -#include "PeiPchPolicyUpdate.h"
> -#include <Library/PcdLib.h>
> -#include <CpuAccess.h>
> +#include <PiPei.h>
> +
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/MmPciLib.h>
>
> #include <FspEas.h>
> #include <FspmUpd.h>
> #include <FspsUpd.h>
>
> +#include <SaPolicyCommon.h>
> +
> extern EFI_GUID gTianoLogoGuid;
>
> #endif
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
> index f95f82a25ca5..8c0bd8151e32 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
> @@ -7,20 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include "PeiSaPolicyUpdate.h"
> -#include <CpuRegs.h>
> -#include <Library/CpuPlatformLib.h>
> -#include <Guid/MemoryTypeInformation.h>
> -#include <Guid/MemoryOverwriteControl.h>
> -#include <Library/HobLib.h>
> -#include <PchAccess.h>
> -#include <SaAccess.h>
> -#include <Library/CpuMailboxLib.h>
> #include <Library/BaseMemoryLib.h>
> -#include <Library/MemoryAllocationLib.h>
> #include <Library/PeiSaPolicyLib.h>
> -#include <Library/GpioLib.h>
> -#include <GpioPinsSklH.h>
> -
>
> /**
> Performs FSP SA PEI Policy initialization in pre-memory.
> @@ -76,4 +64,3 @@ PeiFspSaPolicyUpdatePreMem (
> }
> return EFI_SUCCESS;
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> index f8bec0c852d6..332c96ee2ed6 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> @@ -41,6 +41,7 @@
> PeiSaPolicyUpdate.c
> PeiFspMiscUpdUpdateLib.c
> PcieDeviceTable.c
> + PeiBoardPolicyUpdate.c
>
> ################################################################################
> #
> @@ -55,43 +56,35 @@
> IntelFsp2Pkg/IntelFsp2Pkg.dec
> IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
> IntelSiliconPkg/IntelSiliconPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> KabylakeFspBinPkg/KabylakeFspBinPkg.dec
> + KabylakeSiliconPkg/SiPkg.dec
> KabylakeOpenBoardPkg/OpenBoardPkg.dec
> MinPlatformPkg/MinPlatformPkg.dec
>
> [LibraryClasses.IA32]
> FspWrapperApiLib
> - OcWdtLib
> - PchResetLib
> FspWrapperPlatformLib
> BaseMemoryLib
> - CpuPlatformLib
> DebugLib
> HobLib
> IoLib
> PcdLib
> - PostCodeLib
> - SmbusLib
> MmPciLib
> ConfigBlockLib
> PeiSaPolicyLib
> - PchGbeLib
> PchInfoLib
> PchHsioLib
> PchPcieRpLib
> MemoryAllocationLib
> - CpuMailboxLib
> - DebugPrintErrorLevelLib
> SiPolicyLib
> - PchGbeLib
> - TimerLib
> - GpioLib
> PeiLib
>
> [Pcd]
> + gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
>
> @@ -101,6 +94,9 @@
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES
>
> + # CA Vref Configuration
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSUMES
> +
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
>
> @@ -147,4 +143,3 @@
>
> [Depex]
> gEdkiiVTdInfoPpiGuid
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h
> index a4ab192d8ce1..0f01776a28a8 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h
> @@ -25,6 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> //
> // Status Port 0x62
> //
> +// FIXME: Some bits may be reserved
> #define EC_S_OVR_TMP 0x80 // Current CPU temperature exceeds the threshold
> #define EC_S_SMI_EVT 0x40 // SMI event is pending
> #define EC_S_SCI_EVT 0x20 // SCI event is pending
> @@ -39,7 +40,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> // New commands and command parameters should only be written by the host when IBF=0.
> // Data read from the EC data port is valid only when OBF=1.
> //
> -#define EC_C_FAB_ID 0x0D // Get the board fab ID in the lower 3 bits
> +// TODO: It's unclear if the EC has such a command. Currently, we read model ID from ADCs.
> +// As a definition is required for build, use a known safe command: EC query will do nicely.
> +#define EC_C_FAB_ID 0x84 // Get the board fab ID in the lower 3 bits
We have this in the original code for triggering some board-specific workarounds needed on old/early builds of RVP3 but not later ones.
Given that the AspireVn7Dash572G is now disconnected from the KabylakeRvp3, would it be possible to remove the command to EC for reading the Fab Id? That scenario seems non applicable to the VN-572G.
> #define EC_C_ACPI_READ 0x80 // Read a byte of EC RAM
> #define EC_C_ACPI_WRITE 0x81 // Write a byte of EC RAM
>
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf
> index b5e3f66ceafc..aac4d83f6480 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf
> @@ -1,5 +1,5 @@
> ## @file
> -# FDF file for the KabylakeRvp3 board.
> +# FDF file for the Acer Aspire VN7-572G board.
> #
> # Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> #
> @@ -8,41 +8,43 @@
> ##
>
> #=================================================================================#
> -# 8 M BIOS - for FSP wrapper
> +# 6 M BIOS - for FSP wrapper
> #=================================================================================#
> -DEFINE FLASH_BASE = 0xFF800000 #
> -DEFINE FLASH_SIZE = 0x00800000 #
> +DEFINE FLASH_BASE = 0xFFA00000 #
> +DEFINE FLASH_SIZE = 0x00600000 #
> DEFINE FLASH_BLOCK_SIZE = 0x00010000 #
> -DEFINE FLASH_NUM_BLOCKS = 0x00000080 #
> +DEFINE FLASH_NUM_BLOCKS = 0x00000060 #
> #=================================================================================#
>
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFF800000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFFA00000)
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFF800000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFFA00000)
> SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0001E000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFF81E000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFFA1E000)
> SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFF820000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFFA20000)
> SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x00020000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00040000 # Flash addr (0xFF840000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00050000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00090000 # Flash addr (0xFF890000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00100000 # Flash addr (0xFF900000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00090000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x00190000 # Flash addr (0xFF990000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x001E0000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x00370000 # Flash addr (0xFFB70000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00180000 #
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x004F0000 # Flash addr (0xFFCF0000)
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x00590000 # Flash addr (0xFFD90000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00060000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x005F0000 # Flash addr (0xFFDF0000)
> +SET gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageOffset= 0x00040000 # Flash addr (0xFFA40000)
> +SET gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize = 0x00010000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00050000 # Flash addr (0xFFA50000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x000C0000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00110000 # Flash addr (0xFFB10000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00080000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00190000 # Flash addr (0xFFB90000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x000B0000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x00240000 # Flash addr (0xFFC40000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x00180000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x003C0000 # Flash addr (0xFFDC0000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00020000 #
> +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x003E0000 # Flash addr (0xFFDE0000)
> +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x00080000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x00460000 # Flash addr (0xFFE60000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x0004C000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x004AC000 # Flash addr (0xFFEAC000)
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x000BC000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x006AC000 # Flash addr (0xFFEAC000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00014000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = 0x006C0000 # Flash addr (0xFFEC0000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x00568000 # Flash addr (0xFFF68000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00008000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = 0x00570000 # Flash addr (0xFFF70000)
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = 0x00010000 #
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006D0000 # Flash addr (0xFFED0000)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00130000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x00580000 # Flash addr (0xFFF80000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00080000 #
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h
> new file mode 100644
> index 000000000000..682492e7d1c9
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h
> @@ -0,0 +1,112 @@
> +/** @file
> + EC library functions and definitions.
> +
> + This library provides basic EC interface.
> +
> + There may be different libraries for different environments (PEI, BS, RT, SMM).
> + Make sure you meet the requirements for the library (protocol dependencies, use
> + restrictions, etc).
> +
> +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _BOARD_EC_LIB_H_
> +#define _BOARD_EC_LIB_H_
> +
> +/**
> + Reads a byte of EC RAM.
> +
> + @param[in] Address Address to read
> + @param[out] Data Data received
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> + @retval EFI_TIMEOUT Command timeout
> +**/
> +EFI_STATUS
> +EcCmd90Read (
> + IN UINT8 Address,
> + OUT UINT8 *Data
> + );
> +
> +/**
> + Writes a byte of EC RAM.
> +
> + @param[in] Address Address to write
> + @param[in] Data Data to write
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> + @retval EFI_TIMEOUT Command timeout
> +**/
> +EFI_STATUS
> +EcCmd91Write (
> + IN UINT8 Address,
> + IN UINT8 Data
> + );
> +
> +/**
> + Query the EC status.
> +
> + @param[out] Status EC status byte
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> + @retval EFI_TIMEOUT Command timeout
> +**/
> +EFI_STATUS
> +EcCmd94Query (
> + OUT UINT8 *Data
> + );
> +
> +/**
> + Reads a byte of EC (index) RAM.
> + TODO: Validate errors?
> +
> + @param[in] Address Address to read
> + @param[out] Data Data received
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> + @retval EFI_TIMEOUT Command timeout
> +**/
> +VOID
> +EcIdxRead (
> + IN UINT16 Address,
> + OUT UINT8 *Data
> + );
> +
> +/**
> + Writes a byte of EC (index) RAM.
> + TODO: Validate errors?
> +
> + @param[in] Address Address to read
> + @param[out] Data Data received
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> + @retval EFI_TIMEOUT Command timeout
> +**/
> +VOID
> +EcIdxWrite (
> + IN UINT16 Address,
> + IN UINT8 Data
> + );
> +
> +/**
> + Read EC analog-digital converter.
> +
> + @param[out] DataBuffer
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> +**/
> +EFI_STATUS
> +ReadEcAdcConverter (
> + IN UINT8 Adc,
> + OUT UINT16 *DataBuffer
> + );
> +
> +#endif
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.c
> deleted file mode 100644
> index c7fc6986f547..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.c
> +++ /dev/null
> @@ -1,662 +0,0 @@
> -/** @file
> - Platform Hook Library instances
> -
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi/UefiBaseType.h>
> -#include <Library/PlatformHookLib.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PciLib.h>
> -#include <Library/PcdLib.h>
> -#include <SystemAgent/Include/SaAccess.h>
> -#include <SioRegs.h>
> -#include <Library/MmPciLib.h>
> -#include <Library/PchCycleDecodingLib.h>
> -#include <Register/PchRegsLpc.h>
> -#include <PchAccess.h>
> -
> -#define COM1_BASE 0x3f8
> -#define COM2_BASE 0x2f8
> -
> -#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690
> -
> -#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E
> -#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F
> -#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20
> -
> -#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E
> -#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F
> -#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E
> -#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F
> -
> -typedef struct {
> - UINT8 Register;
> - UINT8 Value;
> -} EFI_SIO_TABLE;
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTable[] = {
> - {0x002, 0x88}, // Power On UARTs
> - {0x024, COM1_BASE >> 2},
> - {0x025, COM2_BASE >> 2},
> - {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4,
> - {0x029, 0x080}, // SIRQ_CLKRUN_EN
> - {0x02A, 0x000},
> - {0x02B, 0x0DE},
> - {0x00A, 0x040},
> - {0x00C, 0x00E},
> - {0x02c, 0x002},
> - {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},
> - {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},
> - {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},
> - {0x03a, 0x00A}, // LPC Docking Enabling
> - {0x031, 0x01f},
> - {0x032, 0x000},
> - {0x033, 0x004},
> - {0x038, 0x0FB},
> - {0x035, 0x0FE},
> - {0x036, 0x000},
> - {0x037, 0x0FF},
> - {0x039, 0x000},
> - {0x034, 0x001},
> - {0x012, FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & 0xFF}, // Relocate configuration ports base address
> - {0x013, (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) >> 8) & 0xFF} // to ensure SIO config address can be accessed in OS
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableSmsc1000[] = {
> - {0x002, 0x88}, // Power On UARTs
> - {0x007, 0x00},
> - {0x024, COM1_BASE >> 2},
> - {0x025, COM2_BASE >> 2},
> - {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4,
> - {0x029, 0x080}, // SIRQ_CLKRUN_EN
> - {0x02A, 0x000},
> - {0x02B, 0x0DE},
> - {0x00A, 0x040},
> - {0x00C, 0x00E},
> - {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},
> - {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},
> - {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},
> - {0x03a, 0x00A}, // LPC Docking Enabling
> - {0x031, 0x01f},
> - {0x032, 0x000},
> - {0x033, 0x004},
> - {0x038, 0x0FB},
> - {0x035, 0x0FE},
> - {0x036, 0x000},
> - {0x037, 0x0FE},
> - {0x039, 0x000},
> - {0x034, 0x001}
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] = {
> - {0x29, 0x0A0}, // Enable super I/O clock and set to 48MHz
> - {0x22, 0x003}, //
> - {0x07, 0x003}, // Select UART0 device
> - {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB
> - {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB
> - {0x70, 0x004}, // Set to IRQ4
> - {0x30, 0x001}, // Enable it with Activation bit
> - {0x07, 0x002}, // Select UART1 device
> - {0x60, (COM2_BASE >> 8)}, // Set Base Address MSB
> - {0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB
> - {0x70, 0x003}, // Set to IRQ3
> - {0x30, 0x001}, // Enable it with Activation bit
> - {0x07, 0x007}, // Select GPIO device
> - {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base Address MSB
> - {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base Address LSB
> - {0x30, 0x001}, // Enable it with Activation bit
> - {0x21, 0x001}, // Global Device Enable
> - {0x26, 0x000} // Fast Enable UART 0 & 1 as their enable & activation bit
> -};
> -
> -//
> -// National PC8374L
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mDesktopSioTable[] = {
> - {0x007, 0x03}, // Select Com1
> - {0x061, 0xF8}, // 0x3F8
> - {0x060, 0x03}, // 0x3F8
> - {0x070, 0x04}, // IRQ4
> - {0x030, 0x01} // Active
> -};
> -
> -//
> -// IT8628
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = {
> - {0x023, 0x09}, // Clock Selection register
> - {0x007, 0x01}, // Com1 Logical Device Number select
> - {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register
> - {0x060, 0x03}, // Serial Port 1 Base Address LSB Register
> - {0x070, 0x04}, // Serial Port 1 Interrupt Level Select
> - {0x030, 0x01}, // Serial Port 1 Activate
> - {0x007, 0x02}, // Com1 Logical Device Number select
> - {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register
> - {0x060, 0x02}, // Serial Port 2 Base Address MSB Register
> - {0x070, 0x03}, // Serial Port 2 Interrupt Level Select
> - {0x030, 0x01} // Serial Port 2 Activate
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableParallelPort[] = {
> - {0x007, 0x03}, // Parallel Port Logical Device Number select
> - {0x030, 0x00}, // Parallel port Activate
> - {0x061, 0x78}, // Parallel Port Base Address 1 MSB Register
> - {0x060, 0x03}, // Parallel Port Base Address 1 LSB Register
> - {0x063, 0x78}, // Parallel Port Base Address 2 MSB Register
> - {0x062, 0x07}, // Parallel Port Base Address 1 LSB Register
> - {0x0F0, 0x03} // Special Configuration register
> -};
> -
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbondX374[] = {
> - {0x07, 0x03}, // Select UART0 device
> - {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB
> - {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB
> - {0x70, 0x04}, // Set to IRQ4
> - {0x30, 0x01} // Enable it with Activation bit
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTablePilot3[] = {
> - {0x07, 0x02}, // Set logical device SP Serial port Com0
> - {0x61, 0xF8}, // Write Base Address LSB register 0x3F8
> - {0x60, 0x03}, // Write Base Address MSB register 0x3F8
> - {0x70, 0x04}, // Write IRQ1 value (IRQ 1) keyboard
> - {0x30, 0x01} // Enable serial port with Activation bit
> -};
> -
> -/**
> - Detect if a National 393 SIO is docked. If yes, enable the docked SIO
> - and its serial port, and disable the onboard serial port.
> -
> - @retval EFI_SUCCESS Operations performed successfully.
> -**/
> -STATIC
> -VOID
> -CheckNationalSio (
> - VOID
> - )
> -{
> - UINT8 Data8;
> -
> - //
> - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).
> - // We use (0x2e, 0x2f) which is determined by BADD default strapping
> - //
> -
> - //
> - // Read the Pc87393 signature
> - //
> - IoWrite8 (0x2e, 0x20);
> - Data8 = IoRead8 (0x2f);
> -
> - if (Data8 == 0xea) {
> - //
> - // Signature matches - National PC87393 SIO is docked
> - //
> -
> - //
> - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch
> - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at
> - // SIO_BASE_ADDRESS + 0x10)
> - //
> - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7F), 0x20);
> -
> - //
> - // Enable port switch
> - //
> - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);
> -
> - //
> - // Turn on docking power
> - //
> - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);
> -
> - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);
> -
> - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);
> -
> - //
> - // Enable port switch
> - //
> - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);
> -
> - //
> - // GPIO setting
> - //
> - IoWrite8 (0x2e, 0x24);
> - IoWrite8 (0x2f, 0x29);
> -
> - //
> - // Enable chip clock
> - //
> - IoWrite8 (0x2e, 0x29);
> - IoWrite8 (0x2f, 0x1e);
> -
> -
> - //
> - // Enable serial port
> - //
> -
> - //
> - // Select com1
> - //
> - IoWrite8 (0x2e, 0x7);
> - IoWrite8 (0x2f, 0x3);
> -
> - //
> - // Base address: 0x3f8
> - //
> - IoWrite8 (0x2e, 0x60);
> - IoWrite8 (0x2f, 0x03);
> - IoWrite8 (0x2e, 0x61);
> - IoWrite8 (0x2f, 0xf8);
> -
> - //
> - // Interrupt: 4
> - //
> - IoWrite8 (0x2e, 0x70);
> - IoWrite8 (0x2f, 0x04);
> -
> - //
> - // Enable bank selection
> - //
> - IoWrite8 (0x2e, 0xf0);
> - IoWrite8 (0x2f, 0x82);
> -
> - //
> - // Activate
> - //
> - IoWrite8 (0x2e, 0x30);
> - IoWrite8 (0x2f, 0x01);
> -
> - //
> - // Disable onboard serial port
> - //
> - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);
> -
> - //
> - // Power Down UARTs
> - //
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);
> -
> - //
> - // Dissable COM1 decode
> - //
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
> -
> - //
> - // Disable COM2 decode
> - //
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
> -
> - //
> - // Disable interrupt
> - //
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);
> -
> - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
> -
> - //
> - // Enable floppy
> - //
> -
> - //
> - // Select floppy
> - //
> - IoWrite8 (0x2e, 0x7);
> - IoWrite8 (0x2f, 0x0);
> -
> - //
> - // Base address: 0x3f0
> - //
> - IoWrite8 (0x2e, 0x60);
> - IoWrite8 (0x2f, 0x03);
> - IoWrite8 (0x2e, 0x61);
> - IoWrite8 (0x2f, 0xf0);
> -
> - //
> - // Interrupt: 6
> - //
> - IoWrite8 (0x2e, 0x70);
> - IoWrite8 (0x2f, 0x06);
> -
> - //
> - // DMA 2
> - //
> - IoWrite8 (0x2e, 0x74);
> - IoWrite8 (0x2f, 0x02);
> -
> - //
> - // Activate
> - //
> - IoWrite8 (0x2e, 0x30);
> - IoWrite8 (0x2f, 0x01);
> -
> - } else {
> -
> - //
> - // No National pc87393 SIO is docked, turn off dock power and
> - // disable port switch
> - //
> - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);
> - // IoWrite8 (0x690, 0);
> -
> - //
> - // If no National pc87393, just return
> - //
> - return;
> - }
> -}
> -
> -
> -/**
> -Check whether the IT8628 SIO present on LPC. If yes, enable its serial
> -ports, parallel port, and port 80.
> -
> - at retval EFI_SUCCESS Operations performed successfully.
> -**/
> -STATIC
> -VOID
> -It8628SioSerialPortInit (
> - VOID
> - )
> -{
> - UINT8 ChipId0 = 0;
> - UINT8 ChipId1 = 0;
> - UINT16 LpcIoDecondeRangeSet = 0;
> - UINT16 LpcIoDecoodeSet = 0;
> - UINT8 Index;
> - UINTN LpcBaseAddr;
> -
> -
> - //
> - // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh.
> - //
> - LpcBaseAddr = MmPciBase (
> - DEFAULT_PCI_BUS_NUMBER_PCH,
> - PCI_DEVICE_NUMBER_PCH_LPC,
> - PCI_FUNCTION_NUMBER_PCH_LPC
> - );
> -
> - LpcIoDecondeRangeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOD);
> - LpcIoDecoodeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOE);
> - MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOD), (LpcIoDecondeRangeSet | ((V_PCH_LPC_IOD_COMB_2F8 << 4) | V_PCH_LPC_IOD_COMA_3F8)));
> - MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOE), (LpcIoDecoodeSet | (B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE)));
> -
> - //
> - // Enter MB PnP Mode
> - //
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x87);
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x01);
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);
> -
> - //
> - // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21)
> - //
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20);
> - ChipId0 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
> -
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21);
> - ChipId1 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
> -
> - //
> - // Enable Serial Port 1, Port 2
> - //
> - if ((ChipId0 == 0x86) && (ChipId1 == 0x28)) {
> - for (Index = 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Register);
> - IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Value);
> - }
> - }
> -
> - //
> - // Exit MB PnP Mode
> - //
> - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x02);
> - IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, 0x02);
> -
> - return;
> -}
> -
> -
> -/**
> - Performs platform specific initialization required for the CPU to access
> - the hardware associated with a SerialPortLib instance. This function does
> - not initialize the serial port hardware itself. Instead, it initializes
> - hardware devices that are required for the CPU to access the serial port
> - hardware. This function may be called more than once.
> -
> - @retval RETURN_SUCCESS The platform specific initialization succeeded.
> - @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
> -
> -**/
> -RETURN_STATUS
> -EFIAPI
> -PlatformHookSerialPortInitialize (
> - VOID
> - )
> -{
> - UINT16 ConfigPort;
> - UINT16 IndexPort;
> - UINT16 DataPort;
> - UINT16 DeviceId;
> - UINT8 Index;
> - UINT16 AcpiBase;
> -
> - //
> - // Set the ICH ACPI Base Address (Reg#40h) and ACPI Enable bit
> - // in ACPI Controll (Reg#44h bit7) for PrePpiStall function use.
> - //
> - IndexPort = 0;
> - DataPort = 0;
> - Index = 0;
> - AcpiBase = 0;
> - PchAcpiBaseGet (&AcpiBase);
> - if (AcpiBase == 0) {
> - PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress));
> - }
> -
> - //
> - // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
> - //
> - PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
> - PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
> -
> - // Configure Sio IT8628
> - It8628SioSerialPortInit ();
> -
> - DeviceId = MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + R_SA_MC_DEVICE_ID);
> - if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) {
> - //
> - // if no EC, it is SV Bidwell Bar board
> - //
> - if ((IoRead8 (0x66) != 0xFF) && (IoRead8 (0x62) != 0xFF)) {
> - //
> - // Super I/O initialization for SMSC SI1007
> - //
> - ConfigPort = FixedPcdGet16 (PcdLpcSioConfigDefaultPort);
> - DataPort = PcdGet16 (PcdLpcSioDataDefaultPort);
> - IndexPort = PcdGet16 (PcdLpcSioIndexDefaultPort);
> -
> - //
> - // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
> - //
> - PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), 0x10);
> -
> - //
> - // Program and Enable Default Super IO Configuration Port Addresses and range
> - //
> - PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
> -
> - //
> - // Enter Config Mode
> - //
> - IoWrite8 (ConfigPort, 0x55);
> -
> - //
> - // Check for SMSC SIO1007
> - //
> - IoWrite8 (IndexPort, 0x0D); // SMSC SIO1007 Device ID register is 0x0D
> - if (IoRead8 (DataPort) == 0x20) { // SMSC SIO1007 Device ID is 0x20
> - //
> - // Configure SIO
> - //
> - for (Index = 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (IndexPort, mSioTable[Index].Register);
> - IoWrite8 (DataPort, mSioTable[Index].Value);
> - }
> -
> - //
> - // Exit Config Mode
> - //
> - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
> -
> - //
> - // GPIO 15-17:IN 10-14:OUT Enable RS232 ref: Page42 of CRB_SCH
> - //
> - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0c, 0x1f);
> - }
> -
> - //
> - // Check if a National Pc87393 SIO is docked
> - //
> - CheckNationalSio ();
> -
> - //
> - // Super I/O initialization for SMSC SIO1000
> - //
> - ConfigPort = PcdGet16 (PcdLpcSioIndexPort);
> - IndexPort = PcdGet16 (PcdLpcSioIndexPort);
> - DataPort = PcdGet16 (PcdLpcSioDataPort);
> -
> - //
> - // Enter Config Mode
> - //
> - IoWrite8 (ConfigPort, 0x55);
> -
> - //
> - // Check for SMSC SIO1000
> - //
> - if (IoRead8 (ConfigPort) != 0xFF) {
> - //
> - // Configure SIO
> - //
> - for (Index = 0; Index < sizeof (mSioTableSmsc1000) / sizeof (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (IndexPort, mSioTableSmsc1000[Index].Register);
> - IoWrite8 (DataPort, mSioTableSmsc1000[Index].Value);
> - }
> -
> - //
> - // Exit Config Mode
> - //
> - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
> - }
> -
> - //
> - // Super I/O initialization for Winbond WPCN381U
> - //
> - IndexPort = LPC_SIO_INDEX_DEFAULT_PORT_2;
> - DataPort = LPC_SIO_DATA_DEFAULT_PORT_2;
> -
> - //
> - // Check for Winbond WPCN381U
> - //
> - IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device ID register is 0x20
> - if (IoRead8 (DataPort) == 0xF4) { // Winbond WPCN381U Device ID is 0xF4
> - //
> - // Configure SIO
> - //
> - for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
> - IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
> - }
> - }
> - } //EC is not exist, skip mobile board detection for SV board
> -
> - //
> - //add for SV Bidwell Bar board
> - //
> - if (IoRead8 (COM1_BASE) == 0xFF) {
> - //
> - // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (LDC)
> - // Looking for LDC2 card first
> - //
> - IoWrite8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55);
> - if (IoRead8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) == 0x55) {
> - IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
> - DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;
> - } else {
> - IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;
> - DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;
> - }
> -
> - IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register is 0x20
> - if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is 0xF1
> - for (Index = 0; Index < sizeof (mSioTableWinbondX374) / sizeof (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (IndexPort, mSioTableWinbondX374[Index].Register);
> - IoWrite8 (DataPort, mSioTableWinbondX374[Index].Value);
> - }
> - }
> - }// end of Bidwell Bar SIO initialization
> - } else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) || IS_SA_DEVICE_ID_SERVER (DeviceId)) {
> - //
> - // If we are in debug mode, we will allow serial status codes
> - //
> -
> - //
> - // National PC8374 SIO & Winbond WPCD374 (LDC2)
> - //
> - IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
> -
> - IoWrite8 (IndexPort, 0x55);
> - if (IoRead8 (IndexPort) == 0x55) {
> - IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
> - DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;
> - } else {
> - IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;
> - DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;
> - }
> -
> - //
> - // Configure SIO
> - //
> - IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register is 0x20
> - if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is 0xF1
> - for (Index = 0; Index < sizeof (mDesktopSioTable) / sizeof (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (IndexPort, mDesktopSioTable[Index].Register);
> - //PrePpiStall (200);
> - IoWrite8 (DataPort, mDesktopSioTable[Index].Value);
> - //PrePpiStall (200);
> - }
> - return RETURN_SUCCESS;
> - }
> - //
> - // Configure Pilot3 SIO
> - //
> - IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_UNLOCK); //Enter config mode.
> - IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_CHIP_ID_REG); // Pilot3 SIO Device ID register is 0x20.
> - if (IoRead8 (PILOTIII_SIO_DATA_PORT) == PILOTIII_CHIP_ID) { // Pilot3 SIO Device ID register is 0x03.
> - //
> - // Configure SIO
> - //
> - for (Index = 0; Index < sizeof (mSioTablePilot3) / sizeof (EFI_SIO_TABLE); Index++) {
> - IoWrite8 (PILOTIII_SIO_INDEX_PORT, mSioTablePilot3[Index].Register);
> - IoWrite8 (PILOTIII_SIO_DATA_PORT, mSioTablePilot3[Index].Value);
> - }
> - }
> - IoWrite8 (PILOTIII_SIO_INDEX_PORT , PILOTIII_LOCK); //Exit config mode.
> - }
> -
> -
> - return RETURN_SUCCESS;
> -}
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.inf
> deleted file mode 100644
> index 7a5e290657f2..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.inf
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -### @file
> -# Platform Hook Library instance for Kaby Lake RVP3.
> -#
> -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = BasePlatformHookLib
> - FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
> - VERSION_STRING = 1.0
> - MODULE_TYPE = BASE
> - LIBRARY_CLASS = PlatformHookLib
> -#
> -# The following information is for reference only and not required by the build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> -#
> -
> -[LibraryClasses]
> - BaseLib
> - IoLib
> - MmPciLib
> - PciLib
> - PchCycleDecodingLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - KabylakeOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Pcd]
> - gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMES
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSUMES
> -
> -[FixedPcd]
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES
> -
> -[Sources]
> - BasePlatformHookLib.c
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeAspireVn7Dash572GAcpiTableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeAspireVn7Dash572GAcpiTableLib.c
> index d66283f7e830..5861ee9905d7 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeAspireVn7Dash572GAcpiTableLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeAspireVn7Dash572GAcpiTableLib.c
> @@ -1,5 +1,5 @@
> /** @file
> - Kaby Lake RVP 3 Board ACPI Library
> + Aspire VN7-572G Board ACPI Library
>
> Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -7,26 +7,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include <Base.h>
> -#include <Uefi.h>
> #include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> #include <Library/BoardAcpiTableLib.h>
> +#include <Library/EcLib.h>
> #include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/UefiBootServicesTableLib.h>
> -#include <Library/AslUpdateLib.h>
> #include <Protocol/GlobalNvsArea.h>
>
> -#include <PlatformBoardId.h>
> -
> GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
>
> VOID
> -KabylakeRvp3UpdateGlobalNvs (
> +AspireVn7Dash572GUpdateGlobalNvs (
> VOID
> )
> {
> + EFI_STATUS Status;
> + UINT8 PowerRegister;
>
> //
> // Allocate and initialize the NVS area for SMM and ASL communication.
> @@ -40,7 +35,11 @@ KabylakeRvp3UpdateGlobalNvs (
> //
> // Enable PowerState
> //
> - mGlobalNvsArea.Area->PowerState = 1; // AC =1; for mobile platform, will update this value in SmmPlatform.c
> + Status = EcRead (0x70, &PowerRegister);
> + if (EFI_ERROR(Status)) {
> + PowerRegister = 0;
> + }
> + mGlobalNvsArea.Area->PowerState = (PowerRegister & BIT5) == BIT5;
>
> mGlobalNvsArea.Area->NativePCIESupport = PcdGet8 (PcdPciExpNative);
>
> @@ -54,7 +53,7 @@ KabylakeRvp3UpdateGlobalNvs (
> //
> mGlobalNvsArea.Area->LowPowerS0Idle = PcdGet8 (PcdLowPowerS0Idle);
>
> - mGlobalNvsArea.Area->Ps2MouseEnable = FALSE;
> + mGlobalNvsArea.Area->Ps2MouseEnable = PcdGet8 (PcdPs2KbMsEnable);
> mGlobalNvsArea.Area->Ps2KbMsEnable = PcdGet8 (PcdPs2KbMsEnable);
>
> mGlobalNvsArea.Area->BoardId = (UINT8) LibPcdGetSku ();
> @@ -62,15 +61,14 @@ KabylakeRvp3UpdateGlobalNvs (
>
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardUpdateAcpiTable (
> +AspireVn7Dash572GBoardUpdateAcpiTable (
> IN OUT EFI_ACPI_COMMON_HEADER *Table,
> IN OUT EFI_ACPI_TABLE_VERSION *Version
> )
> {
> if (Table->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
> - KabylakeRvp3UpdateGlobalNvs ();
> + AspireVn7Dash572GUpdateGlobalNvs ();
> }
>
> return EFI_SUCCESS;
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
> index 8699f8d4033f..b87ca1106877 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
> @@ -1,5 +1,5 @@
> /** @file
> - Kaby Lake RVP 3 Board ACPI library
> + Aspire VN7-572G Board ACPI library
>
> Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -7,17 +7,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include <Base.h>
> -#include <Uefi.h>
> #include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> #include <Library/BoardAcpiTableLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
>
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardUpdateAcpiTable (
> +AspireVn7Dash572GBoardUpdateAcpiTable (
> IN OUT EFI_ACPI_COMMON_HEADER *Table,
> IN OUT EFI_ACPI_TABLE_VERSION *Version
> );
> @@ -29,8 +24,7 @@ BoardUpdateAcpiTable (
> IN OUT EFI_ACPI_TABLE_VERSION *Version
> )
> {
> - KabylakeRvp3BoardUpdateAcpiTable (Table, Version);
> + AspireVn7Dash572GBoardUpdateAcpiTable (Table, Version);
>
> return EFI_SUCCESS;
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
> index e0bf5823d8c6..0d8264554734 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
> @@ -1,5 +1,5 @@
> ### @file
> -# Kaby Lake RVP 3 Board ACPI library
> +# Acer Aspire VN7-572G Board ACPI library
> #
> # Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> #
> @@ -26,6 +26,7 @@
> IoLib
> PciLib
> AslUpdateLib
> + EcLib
>
> [Packages]
> MdePkg/MdePkg.dec
> @@ -38,11 +39,9 @@
> [Pcd]
> gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress
>
> [Sources]
> - DxeKabylakeRvp3AcpiTableLib.c
> + DxeAspireVn7Dash572GAcpiTableLib.c
> DxeBoardAcpiTableLib.c
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c
> deleted file mode 100644
> index dfb1b028f18f..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -/** @file
> - Kaby Lake RVP 3 Multi-Board ACPI Support library
> -
> -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi.h>
> -#include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardAcpiTableLib.h>
> -#include <Library/MultiBoardAcpiSupportLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -#include <PlatformBoardId.h>
> -
> -EFI_STATUS
> -EFIAPI
> -KabylakeRvp3BoardUpdateAcpiTable (
> - IN OUT EFI_ACPI_COMMON_HEADER *Table,
> - IN OUT EFI_ACPI_TABLE_VERSION *Version
> - );
> -
> -BOARD_ACPI_TABLE_FUNC mKabylakeRvp3BoardAcpiTableFunc = {
> - KabylakeRvp3BoardUpdateAcpiTable
> -};
> -
> -EFI_STATUS
> -EFIAPI
> -DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor (
> - VOID
> - )
> -{
> - if ((LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku () == BoardIdSkylakeRvp3)) {
> - return RegisterBoardAcpiTableFunc (&mKabylakeRvp3BoardAcpiTableFunc);
> - }
> - return EFI_SUCCESS;
> -}
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
> deleted file mode 100644
> index e5de9268e71e..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
> +++ /dev/null
> @@ -1,49 +0,0 @@
> -### @file
> -# Kaby Lake RVP 3 Multi-Board ACPI Support library
> -#
> -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = DxeKabylakeRvp3MultiBoardAcpiTableLib
> - FILE_GUID = 8E6A3B38-53E0-48C0-970F-058F380FCB80
> - VERSION_STRING = 1.0
> - MODULE_TYPE = BASE
> - LIBRARY_CLASS = NULL
> - CONSTRUCTOR = DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor
> -
> -#
> -# The following information is for reference only and not required by the build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> -#
> -
> -[LibraryClasses]
> - BaseLib
> - IoLib
> - PciLib
> - AslUpdateLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - KabylakeOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> - BoardModulePkg/BoardModulePkg.dec
> -
> -[Pcd]
> - gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress
> -
> -[Sources]
> - DxeKabylakeRvp3AcpiTableLib.c
> - DxeMultiBoardAcpiSupportLib.c
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmAspireVn7Dash572GAcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmAspireVn7Dash572GAcpiEnableLib.c
> index 54755dd17695..ffc38ea8f13a 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmAspireVn7Dash572GAcpiEnableLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmAspireVn7Dash572GAcpiEnableLib.c
> @@ -1,5 +1,5 @@
> /** @file
> - Kaby Lake RVP 3 SMM Board ACPI Enable library
> + Acer Aspire VN7-572G SMM Board ACPI Enable library
>
> Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -7,33 +7,58 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include <Base.h>
> -#include <Uefi.h>
> #include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardAcpiTableLib.h>
> -#include <Library/PcdLib.h>
> #include <Library/DebugLib.h>
> -
> -#include <PlatformBoardId.h>
> +#include <Library/EcLib.h>
>
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardEnableAcpi (
> +AspireVn7Dash572GBoardEnableAcpi (
> IN BOOLEAN EnableSci
> )
> {
> - // enable additional board register
> + EFI_STATUS Status;
> +
> + /* Tests at runtime show this re-enables charging and battery reporting */
> + Status = SendEcCommand(0xE9); /* Vendor implements using ACPI "CMDB" register" */
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): SendEcCommand(0xE9) failed!\n", __FUNCTION__));
> + return EFI_DEVICE_ERROR;
> + }
> +
> + Status = SendEcData(0x81);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): SendEcData(0x81) failed!\n", __FUNCTION__));
> + return EFI_DEVICE_ERROR;
> + }
> +
> + /* TODO: Set touchpad GPP owner to ACPI? */
> +
> return EFI_SUCCESS;
> }
>
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardDisableAcpi (
> +AspireVn7Dash572GBoardDisableAcpi (
> IN BOOLEAN DisableSci
> )
> {
> - // enable additional board register
> + EFI_STATUS Status;
> +
> + /* Tests at runtime show this disables charging and battery reporting */
> + Status = SendEcCommand(0xE9); /* Vendor implements using ACPI "CMDB" register" */
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): SendEcCommand(0xE9) failed!\n", __FUNCTION__));
> + return EFI_DEVICE_ERROR;
> + }
> +
> + Status = SendEcData(0x80);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): SendEcData(0x80) failed!\n", __FUNCTION__));
> + return EFI_DEVICE_ERROR;
> + }
> +
> + /* TODO: Set touchpad GPP owner to GPIO? */
> +
> return EFI_SUCCESS;
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
> index e89624ea0372..c6a3154d0657 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
> @@ -1,5 +1,5 @@
> /** @file
> - Kaby Lake RVP 3 SMM Board ACPI Enable library
> + Acer Aspire VN7-572G SMM Board ACPI Enable library
>
> Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -7,23 +7,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include <Base.h>
> -#include <Uefi.h>
> #include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> #include <Library/BoardAcpiEnableLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
>
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardEnableAcpi (
> +AspireVn7Dash572GBoardEnableAcpi (
> IN BOOLEAN EnableSci
> );
>
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardDisableAcpi (
> +AspireVn7Dash572GBoardDisableAcpi (
> IN BOOLEAN DisableSci
> );
>
> @@ -46,7 +41,7 @@ BoardEnableAcpi (
> )
> {
> SiliconEnableAcpi (EnableSci);
> - return KabylakeRvp3BoardEnableAcpi (EnableSci);
> + return AspireVn7Dash572GBoardEnableAcpi (EnableSci);
> }
>
> EFI_STATUS
> @@ -56,7 +51,5 @@ BoardDisableAcpi (
> )
> {
> SiliconDisableAcpi (DisableSci);
> - return KabylakeRvp3BoardDisableAcpi (DisableSci);
> + return AspireVn7Dash572GBoardDisableAcpi (DisableSci);
> }
> -
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
> index 46a714dc1d97..63a54e1830a5 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
> @@ -1,5 +1,5 @@
> ### @file
> -# Kaby Lake RVP 3 SMM Board ACPI Enable library
> +# Acer Aspire VN7-572G SMM Board ACPI Enable library
> #
> # Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> #
> @@ -23,6 +23,7 @@
>
> [LibraryClasses]
> BaseLib
> + EcLib
> IoLib
> PciLib
> MmPciLib
> @@ -38,10 +39,7 @@
> [Pcd]
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
>
> -[Protocols]
> -
> [Sources]
> - SmmKabylakeRvp3AcpiEnableLib.c
> + SmmAspireVn7Dash572GAcpiEnableLib.c
> SmmSiliconAcpiEnableLib.c
> SmmBoardAcpiEnableLib.c
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
> deleted file mode 100644
> index fb678a19bcf9..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
> +++ /dev/null
> @@ -1,81 +0,0 @@
> -/** @file
> - Kaby Lake RVP 3 SMM Multi-Board ACPI Support library
> -
> -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Uefi.h>
> -#include <PiDxe.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardAcpiEnableLib.h>
> -#include <Library/MultiBoardAcpiSupportLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -#include <PlatformBoardId.h>
> -
> -EFI_STATUS
> -EFIAPI
> -KabylakeRvp3BoardEnableAcpi (
> - IN BOOLEAN EnableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -KabylakeRvp3BoardDisableAcpi (
> - IN BOOLEAN DisableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -SiliconEnableAcpi (
> - IN BOOLEAN EnableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -SiliconDisableAcpi (
> - IN BOOLEAN DisableSci
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -KabylakeRvp3MultiBoardEnableAcpi (
> - IN BOOLEAN EnableSci
> - )
> -{
> - SiliconEnableAcpi (EnableSci);
> - return KabylakeRvp3BoardEnableAcpi (EnableSci);
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -KabylakeRvp3MultiBoardDisableAcpi (
> - IN BOOLEAN DisableSci
> - )
> -{
> - SiliconDisableAcpi (DisableSci);
> - return KabylakeRvp3BoardDisableAcpi (DisableSci);
> -}
> -
> -BOARD_ACPI_ENABLE_FUNC mKabylakeRvp3BoardAcpiEnableFunc = {
> - KabylakeRvp3MultiBoardEnableAcpi,
> - KabylakeRvp3MultiBoardDisableAcpi,
> -};
> -
> -EFI_STATUS
> -EFIAPI
> -SmmKabylakeRvp3MultiBoardAcpiSupportLibConstructor (
> - VOID
> - )
> -{
> - if ((LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku () == BoardIdSkylakeRvp3)) {
> - return RegisterBoardAcpiEnableFunc (&mKabylakeRvp3BoardAcpiEnableFunc);
> - }
> - return EFI_SUCCESS;
> -}
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
> deleted file mode 100644
> index fca63c831431..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -### @file
> -# Kaby Lake RVP 3 SMM Multi-Board ACPI Support library
> -#
> -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -###
> -
> -[Defines]
> - INF_VERSION = 0x00010017
> - BASE_NAME = SmmKabylakeRvp3MultiBoardAcpiSupportLib
> - FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
> - VERSION_STRING = 1.0
> - MODULE_TYPE = BASE
> - LIBRARY_CLASS = NULL
> - CONSTRUCTOR = SmmKabylakeRvp3MultiBoardAcpiSupportLibConstructor
> -
> -#
> -# The following information is for reference only and not required by the build tools.
> -#
> -# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> -#
> -
> -[LibraryClasses]
> - BaseLib
> - IoLib
> - PciLib
> - MmPciLib
> - PchCycleDecodingLib
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MinPlatformPkg/MinPlatformPkg.dec
> - KabylakeOpenBoardPkg/OpenBoardPkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> -
> -[Pcd]
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
> -
> -[Protocols]
> -
> -[Sources]
> - SmmKabylakeRvp3AcpiEnableLib.c
> - SmmSiliconAcpiEnableLib.c
> - SmmMultiBoardAcpiSupportLib.c
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
> index 7f63a12bf461..ca7e1326347e 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
> @@ -7,11 +7,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include <Base.h>
> -#include <Uefi.h>
> #include <PiDxe.h>
> #include <Library/BaseLib.h>
> #include <Library/IoLib.h>
> -#include <Library/BoardAcpiEnableLib.h>
> #include <Library/PcdLib.h>
> #include <Library/DebugLib.h>
> #include <PchAccess.h>
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf
> new file mode 100644
> index 000000000000..ffe6a64571a4
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf
> @@ -0,0 +1,28 @@
> +## @file
> +# Component information file for Aspire VN7-572G EC library
> +#
> +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010017
> + BASE_NAME = BoardEcLib
> + FILE_GUID = 2406A521-A06B-4B48-ADBF-81E737771979
> + VERSION_STRING = 1.0
> + MODULE_TYPE = BASE
> + LIBRARY_CLASS = BoardEcLib
> +
> +[LibraryClasses]
> + DebugLib
> + EcLib
> + IoLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + KabylakeOpenBoardPkg/OpenBoardPkg.dec
> +
> +[Sources]
> + EcCommands.c
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c
> new file mode 100644
> index 000000000000..d8a73d28f59b
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c
> @@ -0,0 +1,218 @@
> +/** @file
> + Board EC commands.
> +
> +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +#include <Library/DebugLib.h>
> +#include <Library/EcLib.h>
> +#include <Library/IoLib.h>
> +
> +/* TODO - Implement:
> + * - Commands: 0x58, 0xE1 and 0xE2
> + * - 0x51, 0x52: EC flash write?
> + * - ACPI CMDB: 0x63 and 0x64, 0xC7
> + * - 0x0B: Flash write (Boolean argument? Set in offset 0x0B?)
> + *
> + * NB: Consider that if UEFI driver consumes
> + * unimplemented PPI/protocol, the driver is dead code.
> + *
> + * NOTE: Check protocol use.
> + * - Commands delivered across modules
> + * - EC writes also control behaviour
> + */
> +
> +#define EC_INDEX_IO_PORT 0x1200
> +#define EC_INDEX_IO_HIGH_ADDR_PORT EC_INDEX_IO_PORT+1
> +#define EC_INDEX_IO_LOW_ADDR_PORT EC_INDEX_IO_PORT+2
> +#define EC_INDEX_IO_DATA_PORT EC_INDEX_IO_PORT+3
> +
> +/**
> + Reads a byte of EC RAM.
> +
> + @param[in] Address Address to read
> + @param[out] Data Data received
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> + @retval EFI_TIMEOUT Command timeout
> +**/
> +EFI_STATUS
> +EcCmd90Read (
> + IN UINT8 Address,
> + OUT UINT8 *Data
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = SendEcCommand (0x90);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): SendEcCommand(0x90) failed!\n", __FUNCTION__));
> + return Status;
> + }
> +
> + Status = SendEcData (Address);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): SendEcData(Address) failed!\n", __FUNCTION__));
> + return Status;
> + }
> +
> + Status = ReceiveEcData (Data);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): ReceiveEcData(Data) failed!\n", __FUNCTION__));
> + return Status;
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Writes a byte of EC RAM.
> +
> + @param[in] Address Address to write
> + @param[in] Data Data to write
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> + @retval EFI_TIMEOUT Command timeout
> +**/
> +EFI_STATUS
> +EcCmd91Write (
> + IN UINT8 Address,
> + IN UINT8 Data
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = SendEcCommand (0x91);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): SendEcCommand(0x91) failed!\n", __FUNCTION__));
> + return Status;
> + }
> +
> + Status = SendEcData (Address);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): SendEcData(Address) failed!\n", __FUNCTION__));
> + return Status;
> + }
> +
> + Status = SendEcData (Data);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): SendEcData(Data) failed!\n", __FUNCTION__));
> + return Status;
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Query the EC status.
> +
> + @param[out] Status EC status byte
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> + @retval EFI_TIMEOUT Command timeout
> +**/
> +EFI_STATUS
> +EcCmd94Query (
> + OUT UINT8 *Data
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = SendEcCommand (0x94);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): SendEcCommand(0x94) failed!\n", __FUNCTION__));
> + return Status;
> + }
> +
> + Status = ReceiveEcData (Data);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a(): ReceiveEcData(Data) failed!\n", __FUNCTION__));
> + return Status;
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Reads a byte of EC (index) RAM.
> +
> + @param[in] Address Address to read
> + @param[out] Data Data received
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> +**/
> +VOID
> +EcIdxRead (
> + IN UINT16 Address,
> + OUT UINT8 *Data
> + )
> +{
> + IoWrite8 (EC_INDEX_IO_HIGH_ADDR_PORT, Address >> 8);
> + IoWrite8 (EC_INDEX_IO_LOW_ADDR_PORT, Address);
> + *Data = IoRead8 (EC_INDEX_IO_DATA_PORT);
> +}
> +
> +/**
> + Writes a byte of EC (index) RAM.
> +
> + @param[in] Address Address to read
> + @param[out] Data Data received
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> +**/
> +VOID
> +EcIdxWrite (
> + IN UINT16 Address,
> + IN UINT8 Data
> + )
> +{
> + IoWrite8 (EC_INDEX_IO_HIGH_ADDR_PORT, Address >> 8);
> + IoWrite8 (EC_INDEX_IO_LOW_ADDR_PORT, Address);
> + IoWrite8 (EC_INDEX_IO_DATA_PORT, Data);
> +}
> +
> +/**
> + Read EC analog-digital converter.
> + TODO: Check if ADC is valid.
> +
> + @param[out] DataBuffer
> +
> + @retval EFI_SUCCESS Command success
> + @retval EFI_DEVICE_ERROR Command error
> +**/
> +EFI_STATUS
> +ReadEcAdcConverter (
> + IN UINT8 Adc,
> + OUT UINT16 *DataBuffer
> + )
> +{
> + UINT8 AdcConvertersEnabled; // Contains some ADCs and some DACs
> + UINT8 IdxData;
> +
> + // Backup enabled ADCs
> + EcIdxRead (0xff15, &AdcConvertersEnabled); // ADDAEN
> +
> + // Enable desired ADC in bitmask (not enabled by EC FW, not used by vendor FW)
> + EcIdxWrite (0xff15, AdcConvertersEnabled | ((1 << Adc) & 0xf)); // ADDAEN
> +
> + // Sample the desired ADC in binary field; OR the start bit
> + EcIdxWrite (0xff18, ((Adc << 1) & 0xf) | 1); // ADCTRL
> +
> + // Read the desired ADC
> + EcIdxRead (0xff19, &IdxData); // ADCDAT
> + *DataBuffer = (IdxData << 2);
> + // Lower 2-bits of 10-bit ADC are in high bits of next register
> + EcIdxRead (0xff1a, &IdxData); // ECIF
> + *DataBuffer |= ((IdxData & 0xc0) >> 6);
> +
> + // Restore enabled ADCs
> + EcIdxWrite (0xff15, AdcConvertersEnabled); // ADDAEN
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GGpioTable.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GGpioTable.c
> index 2439c6bc1edc..bbf6b75f4d9a 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GGpioTable.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GGpioTable.c
> @@ -1,381 +1,398 @@
> /** @file
> - GPIO definition table for KabylakeRvp3
> + GPIO definition table for Acer Aspire VN7-572G
>
> Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
>
> -#ifndef _KABYLAKE_RVP3_GPIO_TABLE_H_
> -#define _KABYLAKE_RVP3_GPIO_TABLE_H_
> +#ifndef _ASPIRE_VN7_572G_GPIO_TABLE_H_
> +#define _ASPIRE_VN7_572G_GPIO_TABLE_H_
>
> #include <PiPei.h>
> +#include <GpioConfig.h>
> #include <GpioPinsSklLp.h>
> #include <Library/GpioLib.h>
> -#include <GpioConfig.h>
> -#include <IoExpander.h>
>
>
> #define END_OF_GPIO_TABLE 0xFFFFFFFF
>
> -GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
> -{
> -//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N
> -//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
> -//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
> -//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
> -//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
> -//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
> -//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ
> - {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N
> -// skip for PM_CLKRUN_N {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N
> -//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
> -// skip for PCH_CLK_PCI_TPM {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
> - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR
> - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
> -//skip for SUS_PWR_ACK_R {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R
> -//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
> -//skip for SUSACK_R_N {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N
> - {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL
> - {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N
> - {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR
> - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR
> - {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR
> - {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ
> - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N
> - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY
> - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0
> - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1
> - {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB
> - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N
> - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N
> - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N
> - // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N
> - // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
> - // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
> - // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
> - // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
> - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB
> - {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N
> - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N
> - {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN
> - // {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU, NOT OWNED BY BIOS
> - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
> - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//TBT_CIO_PLUG_EVENT_N
> - {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
> - {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N
> - {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
> - {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
> - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
> - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
> - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK
> - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA
> - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
> - {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK
> - {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA
> - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
> - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK, OWNED BY ME
> - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA, OWNED BY ME
> - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD
> - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD
> - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N
> - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N
> - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
> - {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
> - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
> - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
> - {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA
> - {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL
> - {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA
> - {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL
> - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
> - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
> - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N
> - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N
> - {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N
> - {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK
> - {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO
> - {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI
> - {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE
> - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA
> - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL
> - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA
> - {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL
> - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN
> - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH
> - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH
> - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH
> - {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
> - {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
> - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N
> - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
> - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1
> - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_DATA_1
> - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0
> - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_DATA_0
> - {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2
> - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3
> - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK
> - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
> - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N
> - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
> - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N
> - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET
> - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
> - // {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R, NOT OWNED BY BIOS
> - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N
> - {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N
> - {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N
> - {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
> - // {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ, NOT OWNED BY BIOS
> - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q
> - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q
> - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N
> - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
> - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD
> - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK
> - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA
> - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK
> - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA
> - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ
> - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N
> - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK
> - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM
> - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD
> - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD
> - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
> - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
> - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
> - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
> - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
> - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
> - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
> - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
> - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
> - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
> - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
> - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
> - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
> - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
> - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
> - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
> - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
> - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
> - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
> - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
> - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD
> - {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0
> - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1
> - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2
> - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3
> - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB
> - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK
> - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP
> - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N
> - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R
> - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
> - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N
> - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N
> - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N
> - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N
> - {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
> - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK
> - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N
> - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N
> - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE
> - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table
> -};
>
> -UINT16 mGpioTableLpDdr3Rvp3Size = sizeof (mGpioTableLpDdr3Rvp3) / sizeof (GPIO_INIT_CONFIG) - 1;
> +/* TODO: Vendor configures many NC pads as _TERM_GPO. Why? */
> +/* TODO: Clean-up
> + * - On direction: Are some of these comments illusory? At least some pads
> + * are bidirectional on the other side of the GPIO.
> + * - Then, finalise whitespace */
> +/* NB: Do not reconfigure pads used by Optimus, their assertion state may be lost */
>
> -GPIO_INIT_CONFIG mGpioTableKabyLakeYLpddr3Rvp3[] =
> +GPIO_INIT_CONFIG mGpioTableAspireVn7Dash572G[] =
> {
> - { GPIO_SKL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone } },//REALSENSE_ISH_WAKE
> - { GPIO_SKL_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//IRIS_PROXI_INTR
> - { GPIO_SKL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
> - { GPIO_SKL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone } },//SD_CARD_WAKE
> - { GPIO_SKL_LP_GPP_D11, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//TYPEC_P1_DCI_CLK
> - { GPIO_SKL_LP_GPP_D12, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//TYPEC_P1_DCI_DATA
> -};
>
> -UINT16 mGpioTableKabyLakeYLpddr3Rvp3Size = sizeof (mGpioTableKabyLakeYLpddr3Rvp3) / sizeof (GPIO_INIT_CONFIG);
> + /* ------- GPIO Community 0 ------- */
>
> -GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[] =
> -{
> - { GPIO_SKL_LP_GPP_B0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone } }, //GPP_B0
> - { GPIO_SKL_LP_GPP_B1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone } }, //GPP_B1
> -};
> + /* ------- GPIO Group GPP_A ------- */
> + // RCIN# <= H_RCIN#
> + { GPIO_SKL_LP_GPP_A0, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // LAD0 (ESPI_IO0) <=> LPC_AD_CPU_P0
> + { GPIO_SKL_LP_GPP_A1, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNative } },
> + // LAD1 (ESPI_IO1) <=> LPC_AD_CPU_P1
> + { GPIO_SKL_LP_GPP_A2, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNative } },
> + // LAD2 (ESPI_IO2) <=> LPC_AD_CPU_P2
> + { GPIO_SKL_LP_GPP_A3, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNative } },
> + // LAD3 (ESPI_IO3) <=> LPC_AD_CPU_P3
> + { GPIO_SKL_LP_GPP_A4, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNative } },
> + // LFRAME# (ESPI_CS#) => LPC_FRAME#_CPU
> + { GPIO_SKL_LP_GPP_A5, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SERIRQ <=> INT_SERIRQ
> + { GPIO_SKL_LP_GPP_A6, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // PIRQA# = PIRQA#
> + { GPIO_SKL_LP_GPP_A7, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // CLKRUN# <= PM_CLKRUN#_EC
> + { GPIO_SKL_LP_GPP_A8, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // CLKOUT_LPC0 (ESPI_CLK) <= LPC_CLK_CPU_P0
> + { GPIO_SKL_LP_GPP_A9, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // CLKOUT_LPC1 <= LPC_CLK_CPU_P1
> + { GPIO_SKL_LP_GPP_A10, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (PME#) // NC
> + { GPIO_SKL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SX_EXIT_HOLDOFF#/BM_BUSY#/ISH_GP6) <= GC6_FB_EN
> + { GPIO_SKL_LP_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SUSWARN#/SUSPWRDNACK = PM_SUSACK#
> + { GPIO_SKL_LP_GPP_A13, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SUS_STAT# (ESPI_RESET#) => PM_SUS_STAT#
> + { GPIO_SKL_LP_GPP_A14, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SUS_ACK# = PM_SUSACK#
> + { GPIO_SKL_LP_GPP_A15, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SD_1P8_SEL) // NC
> + { GPIO_SKL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SD_PWR_EN#/ISH_GP7) // NC
> + { GPIO_SKL_LP_GPP_A17, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (ISH_GP0) => GSENSOR_INT#
> + { GPIO_SKL_LP_GPP_A18, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (ISH_GP1) // NC
> + { GPIO_SKL_LP_GPP_A19, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (ISH_GP3) // NC
> + { GPIO_SKL_LP_GPP_A21, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (ISH_GP4) <= GPU_EVENT#
> + { GPIO_SKL_LP_GPP_A22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (ISH_GP5) // NC
> + { GPIO_SKL_LP_GPP_A23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
>
> -UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize = sizeof (mGpioTableLpddr3Rvp3UcmcDevice) / sizeof (GPIO_INIT_CONFIG);
> + /* ------- GPIO Group GPP_B ------- */
> + // CORE_VID0 // V0.85A_VID0
> + { GPIO_SKL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // CORE_VID1 // V0.85A_VID1
> + { GPIO_SKL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (CPU_GP2) <= TP_IN#
> + // TODO: APIC-routed pads don't have host owners?
> + { GPIO_SKL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntApic | GpioIntLevel, GpioHostDeepReset, GpioTermNone } },
> + // SRCCLKREQ0# <= PEG_CLKREQ_CPU#
> + { GPIO_SKL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SRCCLKREQ1# <= LAN_CLKREQ_CPU#
> + { GPIO_SKL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SRCCLKREQ2# <= WLAN_CLKREQ_CPU#
> + { GPIO_SKL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SRCCLKREQ3# <= MSATA_CLKREQ_CPU#
> + { GPIO_SKL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SRCCLKREQ4# // SRCCLKREQ4# ("Remove TBT")
> + { GPIO_SKL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SRCCLKREQ5# // SRCCLKREQ5#
> + { GPIO_SKL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (EXT_PWR_GATE#) = EXT_PWR_GATE#
> + { GPIO_SKL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SLP_S0#) // NC
> + { GPIO_SKL_LP_GPP_B12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // PLTRST# => PLT_RST#
> + { GPIO_SKL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (SPKR) => HDA_SPKR (Strap - Top Swap Override)
> + { GPIO_SKL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (GSPI0_CS#) = TOUCH_DET#
> + { GPIO_SKL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (GSPI0_CLK) // NC
> + { GPIO_SKL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (GSPI0_MISO) // NC ("Remove TBT")
> + { GPIO_SKL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutLow, GpioIntSci | GpioIntEdge, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (GSPI0_MOSI) => GPP_B18/GSPI0_MOSI (Strap - No reboot)
> + { GPIO_SKL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (GSPI1_CS#) => RTC_DET#
> + { GPIO_SKL_LP_GPP_B19, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (GSPI1_CLK) <= PSW_CLR#
> + { GPIO_SKL_LP_GPP_B20, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (GSPI1_MOSI) => GPP_B22/GSPI1_MOSI (Strap - Boot BIOS strap)
> + { GPIO_SKL_LP_GPP_B22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SML1ALERT#/PCHHOT#) => GPP_B23 (Strap)
> + { GPIO_SKL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
>
> -GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel =
> - {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}};
> + /* ------- GPIO Community 1 ------- */
>
> -GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3SdhcSidebandCardDetect =
> - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntBothEdge, GpioHostDeepReset, GpioTermNone}}; //SD_CDB D3
> + /* ------- GPIO Group GPP_C ------- */
> + // SMBCLK <= SMB_CLK
> + { GPIO_SKL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SMBDATA = SMB_DATA
> + { GPIO_SKL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SMBALERT#) => GPP_C2 (Strap - TLS Confidentiality)
> + { GPIO_SKL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SML0CLK) // NC
> + { GPIO_SKL_LP_GPP_C3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SML0DATA) // NC
> + { GPIO_SKL_LP_GPP_C4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SML0ALERT#) // NC (Strap - eSPI or LPC)
> + { GPIO_SKL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // RESERVED (SML1CLK) <=> SML1_CLK (KBC)
> + // RESERVED (SML1DATA) <=> SML1_DATA (KBC)
> + // GPIO (UART0_RXD) // NC
> + { GPIO_SKL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (UART0_TXD) // NC
> + { GPIO_SKL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (UART0_RTS#) // NC
> + { GPIO_SKL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (UART0_CTS#) // NC
> + { GPIO_SKL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (UART1_RXD/ISH_UART1_RXD) // NC
> + { GPIO_SKL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (UART1_TXD/ISH_UART1_TXD) // NC
> + { GPIO_SKL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (UART1_RTS#/ISH_UART1_RTS#) // NC
> + { GPIO_SKL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (UART1_CTS#/ISH_UART1_CTS#) // NC
> + { GPIO_SKL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // I2C0_SDA <=> I2C0_DATA_CPU (Touch Panel)
> + { GPIO_SKL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // I2C0_SCL <=> I2C0_CLK_CPU (Touch Panel)
> + { GPIO_SKL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // I2C1_SDA <=> I2C1_DATA_CPU (Touch Pad)
> + { GPIO_SKL_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // I2C1_SCL <=> I2C1_CLK_CPU (Touch Pad)
> + { GPIO_SKL_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // UART2_RXD = LPSS_UART2_RXD
> + { GPIO_SKL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // UART2_TXD = LPSS_UART2_TXD
> + { GPIO_SKL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // UART2_RTS# = LPSS_UART2_RTS#
> + { GPIO_SKL_LP_GPP_C22, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // UART2_CTS# = LPSS_UART2_CTS#
> + { GPIO_SKL_LP_GPP_C23, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
>
> -//IO Expander Table for SKL RVP7, RVP13 and RVP15
> -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[] =
> -{
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED}//M.2_WIGIG_PWREN_IOEXP
> -};
> + /* ------- GPIO Group GPP_D ------- */
> + // GPIO (SPI1_CS#) // NC
> + { GPIO_SKL_LP_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SPI1_CLK) // NC
> + { GPIO_SKL_LP_GPP_D1, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // SPI1_MISO // NC
> + { GPIO_SKL_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SPI1_MOSI // NC
> + { GPIO_SKL_LP_GPP_D3, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (FLASHTRIG) // NC
> + { GPIO_SKL_LP_GPP_D4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (ISH_I2C0_SDA) // NC
> + { GPIO_SKL_LP_GPP_D5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (ISH_I2C0_SCL) // NC
> + { GPIO_SKL_LP_GPP_D6, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (ISH_I2C1_SDA) // NC
> + { GPIO_SKL_LP_GPP_D7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (ISH_I2C1_SCL) // NC
> + { GPIO_SKL_LP_GPP_D8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO // NC
> + { GPIO_SKL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO => TOUCH_S_RST#
> + { GPIO_SKL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO // NC
> + { GPIO_SKL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO // NC ("Remove TBT")
> + { GPIO_SKL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (ISH_UART0_RXD/SML0BDATA/I2C4B_SDA) // NC
> + { GPIO_SKL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (ISH_UART0_TXD/SML0BCLK/I2C4B_SCL) // NC
> + { GPIO_SKL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (ISH_UART0_RTS#) // NC
> + { GPIO_SKL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (ISH_UART0_CTS#/SML0BALERT#) // NC
> + { GPIO_SKL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (DMIC_CLK1) // NC
> + { GPIO_SKL_LP_GPP_D17, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (DMIC_DATA1) // NC
> + { GPIO_SKL_LP_GPP_D18, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // DMIC_CLK0 => DMIC_CLK_CON_R
> + { GPIO_SKL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // DMIC_DATA0 => DMIC_PCH_DATA
> + { GPIO_SKL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SPI1_IO2 // NC
> + { GPIO_SKL_LP_GPP_D21, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SPI1_IO3 // NC
> + { GPIO_SKL_LP_GPP_D22, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (I2S_MCLK) // NC
> + { GPIO_SKL_LP_GPP_D23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
>
> -UINT16 mGpioTableIoExpanderSize = sizeof (mGpioTableIoExpander) / sizeof (IO_EXPANDER_GPIO_CONFIG);
> + /* ------- GPIO Group GPP_E ------- */
> + // SATAXPCIE0 (SATAGP0) = SATAGP0
> + { GPIO_SKL_LP_GPP_E0, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SATAXPCIE1 (SATAGP1) // NC
> + { GPIO_SKL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // SATAXPCIE2 (SATAGP2) = SATAGP2
> + { GPIO_SKL_LP_GPP_E2, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (CPU_GP0) // NC
> + { GPIO_SKL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (DEVSLP0) // NC ("Remove DEVSLP_PCH")
> + { GPIO_SKL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (DEVSLP1) // NC
> + { GPIO_SKL_LP_GPP_E5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (DEVSLP2) // NC
> + { GPIO_SKL_LP_GPP_E6, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (CPU_GP1) <= TOUCH_INT#
> + { GPIO_SKL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutLow, GpioIntApic | GpioIntLevel, GpioHostDeepReset, GpioTermNone } },
> + // SATALED# = SATA_LED#
> + { GPIO_SKL_LP_GPP_E8, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // USB2_OC0# = USB_OC#
> + { GPIO_SKL_LP_GPP_E9, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // USB2_OC1# // USB_OC#
> + { GPIO_SKL_LP_GPP_E10, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // USB2_OC2# // USB_OC#
> + { GPIO_SKL_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // USB2_OC3# // USB_OC#
> + { GPIO_SKL_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // DDPB_HPD0 <= DDI1_HDMI_HPD_CPU
> + { GPIO_SKL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // DDPC_HPD1 // NC ("Remove HPD")
> + { GPIO_SKL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (DDPD_HPD2) <= EC_SMI#
> + // FIXME: Vendor configures as _TERM_GPO. Why?
> + { GPIO_SKL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutLow, GpioIntSmi | GpioIntLevel, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (DDPE_HPD3) <= EC_SCI#
> + { GPIO_SKL_LP_GPP_E16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutLow, GpioIntSci | GpioIntLevel, GpioPlatformReset, GpioTermNone } },
> + // EDP_HPD <= eDP_HPD_CPU
> + { GPIO_SKL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // DDPB_CTRLCLK <=> DDI1_HDMI_CLK_CPU
> + { GPIO_SKL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // DDPB_CTRLDATA <=> DDI1_HDMI_DATA_CPU (Strap - Display Port B Detected)
> + { GPIO_SKL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // DDPC_CTRLCLK // NC
> + { GPIO_SKL_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // DDPC_CTRLDATA => DDPC_CDA (Strap - Display Port C Detected)
> + { GPIO_SKL_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO // NC
> + // TODO: Vendor configures as _GPIO_BIDIRECT. Why?
> + { GPIO_SKL_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO => DDPD_CDA (Strap - Display Port D Detected)
> + { GPIO_SKL_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
>
> -//IO Expander Table for KBL -Refresh
> -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRDdr4[] =
> -{
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//Unused pin
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RTD3_USB_PD1_PWR_EN
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//HRESET_PD1_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
> - //{IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R
> - // We want the initial state to be high.
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_WAKE_CTRL_R_N
> - // Turn off WWAN power and will turn it on later.
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
> -};
> -UINT16 mGpioTableIoExpanderSizeKabylakeRDdr4 = sizeof (mGpioTableIoExpanderKabylakeRDdr4) / sizeof (IO_EXPANDER_GPIO_CONFIG);
> + /* ------- GPIO Community 2 ------- */
>
> -//IO Expander Table for KBL -kc
> -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeKcDdr3[] =
> -{
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_FLEX_PWREN
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB_UART_SEL
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_DOCK_PWREN_IOEXP_R
> + /* -------- GPIO Group GPD -------- */
> + // GPIO (BATLOW#) = BATLOW
> + { GPIO_SKL_LP_GPD0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioDswReset, GpioTermWpd20K } },
> + // ACPRESENT <= AC_PRESENT
> + { GPIO_SKL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioDswReset, GpioTermNone } },
> + // GPIO (LAN_WAKE#) = GPD2/LAN_WAKE#
> + { GPIO_SKL_LP_GPD2, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioDswReset, GpioTermWpd20K } },
> + // PWRBTN# <= PM_PWRBTN#
> + { GPIO_SKL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioDswReset, GpioTermWpu20K } },
> + // SLP_S3# => PM_SLP_S3#
> + { GPIO_SKL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioDswReset, GpioTermNone } },
> + // SLP_S4# => PM_SLP_S4#
> + { GPIO_SKL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioDswReset, GpioTermNone } },
> + // SLP_A# // NC
> + { GPIO_SKL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioDswReset, GpioTermWpd20K } },
> + // GPIO (RSVD#AT15) // NC
> + { GPIO_SKL_LP_GPD7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioDswReset, GpioTermWpd20K } },
> + // SUSCLK => SUS_CLK_CPU
> + { GPIO_SKL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioDswReset, GpioTermNone } },
> + // SLP_WLAN# // NC
> + { GPIO_SKL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioDswReset, GpioTermWpd20K } },
> + // SLP_S5# // NC
> + { GPIO_SKL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis, GpioDswReset, GpioTermWpd20K } },
> + // GPIO (LANPHYPC) // NC
> + { GPIO_SKL_LP_GPD11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioDswReset, GpioTermWpd20K } },
> +
> + /* ------- GPIO Community 3 ------- */
> +
> + /* ------- GPIO Group GPP_F ------- */
> + // GPIO (I2S2_SCLK) // NC
> + { GPIO_SKL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (I2S2_SFRM) // NC
> + { GPIO_SKL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (I2S2_TXD) // NC
> + { GPIO_SKL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (I2S2_RXD) // NC
> + { GPIO_SKL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (I2C2_SDA) // NC
> + { GPIO_SKL_LP_GPP_F4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (I2C2_SCL) // NC
> + { GPIO_SKL_LP_GPP_F5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (I2C3_SDA) // NC
> + { GPIO_SKL_LP_GPP_F6, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (I2C3_SCL) // NC
> + { GPIO_SKL_LP_GPP_F7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (I2C4_SDA) // NC
> + { GPIO_SKL_LP_GPP_F8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (I2C4_SCL) // NC
> + { GPIO_SKL_LP_GPP_F9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (I2C5_SDA/ISH_I2C2_SDA) // NC
> + { GPIO_SKL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (I2C5_SCL/ISH_I2C2_SCL) // NC
> + { GPIO_SKL_LP_GPP_F11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (EMMC_CMD) // NC
> + { GPIO_SKL_LP_GPP_F12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (EMMC_DATA0) // NC
> + { GPIO_SKL_LP_GPP_F13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (EMMC_DATA1) // NC
> + { GPIO_SKL_LP_GPP_F14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (EMMC_DATA2) // NC
> + { GPIO_SKL_LP_GPP_F15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (EMMC_DATA3) // NC
> + { GPIO_SKL_LP_GPP_F16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (EMMC_DATA4) // NC
> + { GPIO_SKL_LP_GPP_F17, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (EMMC_DATA5) // NC
> + { GPIO_SKL_LP_GPP_F18, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (EMMC_DATA6) // NC
> + { GPIO_SKL_LP_GPP_F19, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (EMMC_DATA7) // NC
> + { GPIO_SKL_LP_GPP_F20, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (EMMC_RCLK) // NC
> + { GPIO_SKL_LP_GPP_F21, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (EMMC_CLK) // NC
> + { GPIO_SKL_LP_GPP_F22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO // NC
> + { GPIO_SKL_LP_GPP_F23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntApic | GpioIntLevel, GpioHostDeepReset, GpioTermNone } },
> +
> + /* ------- GPIO Group GPP_G ------- */
> + // GPIO (SD_CMD) // NC
> + { GPIO_SKL_LP_GPP_G0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SD_DATA0) // NC
> + { GPIO_SKL_LP_GPP_G1, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SD_DATA1) // NC
> + { GPIO_SKL_LP_GPP_G2, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SD_DATA2) // NC
> + { GPIO_SKL_LP_GPP_G3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SD_DATA3) // NC
> + // TODO: Vendor configures as _GPO. Why?
> + { GPIO_SKL_LP_GPP_G4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (SD_CD#) // NC
> + { GPIO_SKL_LP_GPP_G5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SD_CLK) // NC
> + { GPIO_SKL_LP_GPP_G6, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + // GPIO (SD_WP) // NC
> + { GPIO_SKL_LP_GPP_G7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + //Marking End of Table
> + { END_OF_GPIO_TABLE, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone} },
> };
> -UINT16 mGpioTableIoExpanderSizeKabylakeKcDdr3 = sizeof (mGpioTableIoExpanderKabylakeKcDdr3) / sizeof (IO_EXPANDER_GPIO_CONFIG);
> -//IO Expander Table Full table for KBL RVP3
> -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRvp3[] =
> +
> +UINT16 mGpioTableAspireVn7Dash572GSize = sizeof (mGpioTableAspireVn7Dash572G) / sizeof (GPIO_INIT_CONFIG) - 1;
> +
> +GPIO_INIT_CONFIG mGpioTableAspireVn7Dash572G_early[] =
> {
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED },//SW_GFX_DGPU_SEL (KBL_RVP3_BOARD)
> -//{IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP (SKL_RVP3_BOARD)
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
> - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED },//Not Connected (KBK_RVP3_BOARD)
> -//{IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP (SKL_RVP3_BOARD)
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN (KBL_RVP3_BOARD)
> - {IO_EXPANDER_1, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N (KBL_RVP3_BOARD)
> + // GPIO (ISH_GP2) = DGPU_PRESENT
> + { GPIO_SKL_LP_GPP_A20, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (VRALERT#) <= DGPU_PWROK
> + { GPIO_SKL_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (CPU_GP3) => DGPU_HOLD_RST#
> + { GPIO_SKL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone } },
> + // GPIO (GSPI1_MISO) => DGPU_PWR_EN#
> + { GPIO_SKL_LP_GPP_B21, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },
> + //Marking End of Table
> + { END_OF_GPIO_TABLE, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone} },
> };
>
> -UINT16 mGpioTableIoExpanderKabylakeRvp3Size = sizeof (mGpioTableIoExpanderKabylakeRvp3) / sizeof (IO_EXPANDER_GPIO_CONFIG);
> +UINT16 mGpioTableAspireVn7Dash572G_earlySize = sizeof (mGpioTableAspireVn7Dash572G_early) / sizeof (GPIO_INIT_CONFIG) - 1;
>
> -#endif // _KABYLAKE_RVP3_GPIO_TABLE_H_
> +#endif // _ASPIRE_VN7_572G_GPIO_TABLE_H_
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHdaVerbTables.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHdaVerbTables.c
> index 92afcbab0653..d13a8af09107 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHdaVerbTables.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHdaVerbTables.c
> @@ -1,232 +1,203 @@
> /** @file
> - HDA Verb table for KabylakeRvp3
> + HDA Verb table for Acer Aspire VN7-572G
>
> Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
>
> -#ifndef _KABYLAKE_RVP3_HDA_VERB_TABLES_H_
> -#define _KABYLAKE_RVP3_HDA_VERB_TABLES_H_
> +#ifndef _ASPIRE_VN7_572G_HDA_VERB_TABLES_H_
> +#define _ASPIRE_VN7_572G_HDA_VERB_TABLES_H_
>
> #include <Ppi/SiPolicy.h>
>
> -HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3 = HDAUDIO_VERB_TABLE_INIT (
> +HDAUDIO_VERB_TABLE HdaVerbTableAlc255AspireVn7Dash572G = HDAUDIO_VERB_TABLE_INIT (
> //
> - // VerbTable: (Realtek ALC286) for RVP3
> + // VerbTable: (Realtek ALC255) for Aspire VN7-572G
> // Revision ID = 0xff
> // Codec Verb Table for SKL PCH boards
> // Codec Address: CAd value (0/1/2)
> - // Codec Vendor: 0x10EC0286
> + // Codec Vendor: 0x10EC0255
> //
> - 0x10EC, 0x0286,
> + 0x10EC, 0x0255,
> 0xFF, 0xFF,
> - //===================================================================================================
> - //
> - // Realtek Semiconductor Corp.
> - //
> - //===================================================================================================
>
> - //Realtek High Definition Audio Configuration - Version : 5.0.2.9
> - //Realtek HD Audio Codec : ALC286
> - //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
> - //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0286&SUBSYS_10EC108E
> - //The number of verb command block : 16
> -
> - // NID 0x12 : 0x411111F0
> - // NID 0x13 : 0x40000000
> - // NID 0x14 : 0x9017011F
> - // NID 0x17 : 0x90170110
> - // NID 0x18 : 0x03A11040
> + // The number of verb command block : 20
> + // NID 0x12 : 0x411111C0
> + // NID 0x14 : 0x90172120
> + // NID 0x17 : 0x40000000
> + // NID 0x18 : 0x411111F0
> // NID 0x19 : 0x411111F0
> // NID 0x1A : 0x411111F0
> - // NID 0x1D : 0x4066A22D
> + // NID 0x1B : 0x411111F0
> + // NID 0x1D : 0x40700001
> // NID 0x1E : 0x411111F0
> - // NID 0x21 : 0x03211020
> + // NID 0x21 : 0x02211030
>
>
> + // Codec Address: Bits 31:28
> + // Node ID: Bits 27:20
> + // Verb ID: Bits 19:8 / Bits 19:16
> + // Payload: Bits 7:0 / Bits 15:0
> +
> + //Widget node 0x01 : Reset Codec
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> +
> //===== HDA Codec Subsystem ID Verb-table =====
> - //HDA Codec Subsystem ID : 0x10EC108E
> - 0x0017208E,
> + //HDA Codec Subsystem ID : 0x10251037
> + 0x00172037,
> 0x00172110,
> - 0x001722EC,
> + 0x00172225,
> 0x00172310,
>
> //===== Pin Widget Verb-table =====
> - //Widget node 0x01 :
> - 0x0017FF00,
> - 0x0017FF00,
> - 0x0017FF00,
> - 0x0017FF00,
> - //Pin widget 0x12 - DMIC
> - 0x01271CF0,
> + //Pin widget 0x12
> + 0x01271CC0,
> 0x01271D11,
> 0x01271E11,
> 0x01271F41,
> - //Pin widget 0x13 - DMIC
> - 0x01371C00,
> - 0x01371D00,
> - 0x01371E00,
> - 0x01371F40,
> - //Pin widget 0x14 - SPEAKER-OUT (Port-D)
> - 0x01771C1F,
> - 0x01771D01,
> - 0x01771E17,
> - 0x01771F90,
> - //Pin widget 0x17 - I2S-OUT
> - 0x01771C10,
> - 0x01771D01,
> - 0x01771E17,
> - 0x01771F90,
> - //Pin widget 0x18 - MIC1 (Port-B)
> - 0x01871C40,
> - 0x01871D10,
> - 0x01871EA1,
> - 0x01871F03,
> - //Pin widget 0x19 - I2S-IN
> + //Pin widget 0x14 - Speaker
> + 0x01471C20,
> + 0x01471D21,
> + 0x01471E17,
> + 0x01471F90,
> + //Pin widget 0x17
> + 0x01771C00,
> + 0x01771D00,
> + 0x01771E00,
> + 0x01771F40,
> + //Pin widget 0x18 - NC
> + 0x01871CF0,
> + 0x01871D11,
> + 0x01871E11,
> + 0x01871F41,
> + //Pin widget 0x19 - NC
> 0x01971CF0,
> 0x01971D11,
> 0x01971E11,
> 0x01971F41,
> - //Pin widget 0x1A - LINE1 (Port-C)
> + //Pin widget 0x1A - NC
> 0x01A71CF0,
> 0x01A71D11,
> 0x01A71E11,
> 0x01A71F41,
> - //Pin widget 0x1D - PC-BEEP
> - 0x01D71C2D,
> - 0x01D71DA2,
> - 0x01D71E66,
> + //Pin widget 0x1B - NC
> + 0x01B71CF0,
> + 0x01B71D11,
> + 0x01B71E11,
> + 0x01B71F41,
> + //Pin widget 0x1D
> + 0x01D71C01,
> + 0x01D71D00,
> + 0x01D71E70,
> 0x01D71F40,
> - //Pin widget 0x1E - S/PDIF-OUT
> + //Pin widget 0x1E - NC
> 0x01E71CF0,
> 0x01E71D11,
> 0x01E71E11,
> 0x01E71F41,
> - //Pin widget 0x21 - HP-OUT (Port-A)
> - 0x02171C20,
> + //Pin widget 0x21 - Headphone
> + 0x02171C30,
> 0x02171D10,
> 0x02171E21,
> - 0x02171F03,
> - //Widget node 0x20 :
> - 0x02050071,
> - 0x02040014,
> - 0x02050010,
> - 0x02040C22,
> - //Widget node 0x20 - 1 :
> - 0x0205004F,
> - 0x02045029,
> - 0x0205004F,
> - 0x02045029,
> - //Widget node 0x20 - 2 :
> - 0x0205002B,
> - 0x02040DD0,
> - 0x0205002D,
> - 0x02047020,
> - //Widget node 0x20 - 3 :
> - 0x0205000E,
> - 0x02046C80,
> - 0x01771F90,
> - 0x01771F90,
> - //TI AMP settings :
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x02040000,
> - 0x02050025,
> - 0x02040000,
> - 0x02050026,
> - 0x0204B010,
> + 0x02171F02,
>
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> + /* See data blob in "InstallPchHdaVerbTablePei" of vendor firmware
> + * (some appear in https://github.com/torvalds/linux/blob/master/sound/pci/hda/patch_realtek.c).
> + * - Largely coefficient programming (undocumented): Select coeff; write data
> + * - Also programs speaker amplifier gain
> + * - Sets speaker output
> + * Note: NID 0x20 holds the "Realtek Defined Hidden registers" */
> + 0x02050038, /* Set coeff idx: 0x38 */
> + 0x02048981, /* Set processing coeff: 0x8981 */
> + 0x02050045, /* Set coeff idx: 0x45 */
> + 0x0204c489, /* Set processing coeff: 0xc489 */
>
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x02040002,
> - 0x02050025,
> - 0x02040011,
> - 0x02050026,
> - 0x0204B010,
> + 0x02050037, /* Set coeff idx: 0x37 */
> + 0x02044a05, /* Set processing coeff: 0x4a05 */
> + 0x05750003, /* Set coeff idx on NID 0x57?: 0x3 */
> + 0x057486a6, /* Set processing coeff on NID 0x57?: 0x86a6 */
>
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> + 0x02050046, /* Set coeff idx: 0x46 */
> + 0x02040004, /* Set processing coeff: 0x4 */
> + 0x0205001b, /* Set coeff idx: 0x1b */
> + 0x02040a0b, /* Set processing coeff: 0xa0b */
>
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x0204000D,
> - 0x02050025,
> - 0x02040010,
> - 0x02050026,
> - 0x0204B010,
> + 0x02050008, /* Set coeff idx: 0x8 */
> + 0x02046a0c, /* Set processing coeff: 0x6a0c */
> + 0x02050009, /* Set coeff idx: 0x9 */
> + 0x0204e003, /* Set processing coeff: 0xe003 */
>
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> + 0x0205000a, /* Set coeff idx: 0xa */
> + 0x02047770, /* Set processing coeff: 0x7770 */
> + 0x02050040, /* Set coeff idx: 0x40 */
> + 0x02049800, /* Set processing coeff: 0x9800 */
>
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x02040025,
> - 0x02050025,
> - 0x02040008,
> - 0x02050026,
> - 0x0204B010,
> + 0x02050010, /* Set coeff idx: 0x10 */
> + 0x02040e20, /* Set processing coeff: 0xe20 */
> + 0x0205000d, /* Set coeff idx: 0xd */
> + 0x02042801, /* Set processing coeff: 0x2801 */
>
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> + 0x0143b000, /* Set amplifier gain on speaker: Set output, L+R amp; Unmuted; No gain */
> + 0x0143b000, /* Repeated for units? */
> + 0x01470740, /* Set widget control on speaker: Out enabled; VrefEn: Hi-Z (disabled) */
> + 0x01470740, /* Repeated for units? */
>
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x02040002,
> - 0x02050025,
> - 0x02040000,
> - 0x02050026,
> - 0x0204B010,
> + 0x01470740, /* Repeated for units? */
> + 0x01470740, /* Repeated for units? */
> + 0x02050010, /* Set coeff idx: 0x10 */
> + 0x02040f20 /* Set processing coeff: 0xf20 */
> +);
> +
> +HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio = HDAUDIO_VERB_TABLE_INIT (
> + //
> + // VerbTable: Intel Skylake HDMI
> + // Revision ID = 0xFF
> + // Codec Vendor: 0x80862809
> + // Subsystem ID: 0x80860101
> + //
> + 0x8086, 0x2809,
> + 0xFF, 0xFF,
> +
> + // Codec Address: Bits 31:28
> + // Node ID: Bits 27:20
> + // Verb ID: Bits 19:8 / Bits 19:16
> + // Payload: Bits 7:0 / Bits 15:0
>
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> - 0x000F0000,
> + // Note: Corrected the table in vendor FW, codec address 0x2, not 0x0
>
> - 0x02050022,
> - 0x0204004C,
> - 0x02050023,
> - 0x02040003,
> - 0x02050025,
> - 0x02040000,
> - 0x02050026,
> - 0x0204B010
> + //
> + // Display Audio Verb Table
> + //
> + // For GEN9, the Vendor Node ID is 08h
> + // Enable the third converter and pin first
> + 0x20878101,
> + 0x20878101,
> + 0x20878101,
> + 0x20878101,
> + // Pin Widget 5 - PORT B - Configuration Default: 0x18560010
> + 0x20571C10,
> + 0x20571D00,
> + 0x20571E56,
> + 0x20571F18,
> + // Pin Widget 6 - PORT C - Configuration Default: 0x18560020
> + 0x20671C20,
> + 0x20671D00,
> + 0x20671E56,
> + 0x20671F18,
> + // Pin Widget 7 - PORT D - Configuration Default: 0x18560030
> + 0x20771C30,
> + 0x20771D00,
> + 0x20771E56,
> + 0x20771F18,
> + // Disable the third converter and third pin
> + 0x20878100,
> + 0x20878100,
> + 0x20878100,
> + 0x20878100
> );
>
> -#endif // _KABYLAKE_RVP3_HDA_VERB_TABLES_H_
> +#endif // _ASPIRE_VN7_572G_HDA_VERB_TABLES_H_
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHsioPtssTables.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHsioPtssTables.c
> index 8a9048fa4c88..af514625dbe5 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHsioPtssTables.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHsioPtssTables.c
> @@ -1,13 +1,13 @@
> /** @file
> - KabylakeRvp3 HSIO PTSS H File
> + Aspire VN7-572G HSIO PTSS H File
>
> Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
>
> -#ifndef KABYLAKE_RVP3_HSIO_PTSS_H_
> -#define KABYLAKE_RVP3_HSIO_PTSS_H_
> +#ifndef ASPIRE_VN7_572G_HSIO_PTSS_H_
> +#define ASPIRE_VN7_572G_HSIO_PTSS_H_
>
> #include <PchHsioPtssTables.h>
>
> @@ -15,91 +15,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #define HSIO_PTSS_TABLE_SIZE(A) A##_Size = sizeof (A) / sizeof (HSIO_PTSS_TABLES)
> #endif
>
> -//BoardId KabylakeRvp3
> -HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[] = {
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoM2},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
> - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F000000}, PchSataTopoDirectConnect},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
> - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
> - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
> - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}, PchSataTopoM2},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}, PchSataTopoDirectConnect},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}
> +//BoardId AspireVn7Dash572G
> +HSIO_PTSS_TABLES PchLpHsioPtss_AspireVn7Dash572G[] = {
> + /* PchSataHsioRxGen3EqBoostMag[1] = "1" */
> + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x01000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}
> };
>
> -UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size = sizeof(PchLpHsioPtss_Cx_KabylakeRvp3) / sizeof(HSIO_PTSS_TABLES);
> +UINT16 PchLpHsioPtss_AspireVn7Dash572G_Size = sizeof(PchLpHsioPtss_AspireVn7Dash572G) / sizeof(HSIO_PTSS_TABLES);
>
> -HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[] = {
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchPcieTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
> - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F000000}, PchSataTopoDirectConnect},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
> - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
> - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
> - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
> - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
> - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}, PchPcieTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
> - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}, PchSataTopoDirectConnect},
> - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
> - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
> - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
> - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
> - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
> -};
> -
> -UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size = sizeof(PchLpHsioPtss_Bx_KabylakeRvp3) / sizeof(HSIO_PTSS_TABLES);
> -
> -#endif // KABYLAKE_RVP3_HSIO_PTSS_H_
> +#endif // ASPIRE_VN7_572G_HSIO_PTSS_H_
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GSpdTable.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GSpdTable.c
> deleted file mode 100644
> index e4ad785bda20..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GSpdTable.c
> +++ /dev/null
> @@ -1,541 +0,0 @@
> -/** @file
> - GPIO definition table for KabylakeRvp3
> -
> -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef _KABYLAKE_RVP3_SPD_TABLE_H_
> -#define _KABYLAKE_RVP3_SPD_TABLE_H_
> -
> -//
> -// DQByteMap[0] - ClkDQByteMap:
> -// If clock is per rank, program to [0xFF, 0xFF]
> -// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
> -// If clock is shared by 2 ranks but does not go to all bytes,
> -// Entry[i] defines which DQ bytes Group i services
> -// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB
> -// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB
> -// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB
> -// For DDR, DQByteMap[3:1] = [0xFF, 0]
> -// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank
> -// Variable only exists to make the code easier to use
> -// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref
> -// Variable only exists to make the code easier to use
> -//
> -//
> -// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP3, SKL SDS - used by SKL/KBL MRC
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapSklRvp3[2][6][2] = {
> - // Channel 0:
> - {
> - { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
> - { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
> - { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
> - { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
> - { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
> - { 0xFF, 0x00 } // CA Vref is one for all bytes
> - },
> - // Channel 1:
> - {
> - { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
> - { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
> - { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
> - { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
> - { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
> - { 0xFF, 0x00 } // CA Vref is one for all bytes
> - }
> -};
> -
> -//
> -// DQS byte swizzling between CPU and DRAM - for SKL DOE RVP
> -//
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramSklRvp3[2][8] = {
> - { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0
> - { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1
> -};
> -
> -// Samsung K4E6E304ED-EGCF 178b QDP LPDDR3, 4Gb die (256Mx16), x16
> -// or Hynix H9CCNNNBLTALAR-NUD
> -// or similar
> -// 1867, 14-17-17-40
> -// 2 ranks per channel, 2 SDRAMs per rank, 8x4Gb = 4GB total per channel
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp16Spd[] = {
> - 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size
> - 0x20, ///< 1 SPD Revision
> - 0x0F, ///< 2 DRAM Device Type
> - 0x0E, ///< 3 Module Type
> - 0x14, ///< 4 SDRAM Density and Banks: 8 Banks, 4 Gb SDRAM density
> - 0x12, ///< 5 SDRAM Addressing: 14 Rows, 11 Columns
> - 0xB5, ///< 6 SDRAM Package Type: QDP, 1 Channel per die, Signal Loading Matrix 1
> - 0x00, ///< 7 SDRAM Optional Features
> - 0x00, ///< 8 SDRAM Thermal and Refresh Options
> - 0x00, ///< 9 Other SDRAM Optional Features
> - 0x00, ///< 10 Reserved - must be coded as 0x00
> - 0x03, ///< 11 Module Nominal Voltage, VDD
> - 0x0A, ///< 12 Module Organization, SDRAM width: 16 bits, 2 Ranks
> - 0x23, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width
> - 0x00, ///< 14 Module Thermal Sensor
> - 0x00, ///< 15 Extended Module Type
> - 0x00, ///< 16 Reserved - must be coded as 0x00
> - 0x00, ///< 17 Timebases
> - 0x09, ///< 18 SDRAM Minimum Cycle Time (tCKmin): tCKmin = 1.071ns (LPDDR3-1867)
> - 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax)
> - 0xD4, ///< 20 CAS Latencies Supported, First Byte (tCK): 14, 12, 10, 8
> - 0x00, ///< 21 CAS Latencies Supported, Second Byte
> - 0x00, ///< 22 CAS Latencies Supported, Third Byte
> - 0x00, ///< 23 CAS Latencies Supported, Fourth Byte
> - 0x78, ///< 24 Minimum CAS Latency Time (tAAmin) = 14.994 ns
> - 0x00, ///< 25 Read and Write Latency Set Options
> - 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab)
> - 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb)
> - 0x10, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte
> - 0x04, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte
> - 0xE0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
> - 0x01, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
> - 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping
> - 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping
> - 0, 0, ///< 78 - 79
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
> - 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb)
> - 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
> - 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0xFA, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)
> - 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax): 32.002 ns
> - 0xCA, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR-1867)
> - 0x00, ///< 126 CRC A
> - 0x00, ///< 127 CRC B
> - 0, 0, ///< 128 - 129
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
> - 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 322 Module Manufacturing Location
> - 0x00, ///< 323 Module Manufacturing Date Year
> - 0x00, ///< 324 Module Manufacturing Date Week
> - 0x55, ///< 325 Module Serial Number A
> - 0x00, ///< 326 Module Serial Number B
> - 0x00, ///< 327 Module Serial Number C
> - 0x00, ///< 328 Module Serial Number D
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
> - 0x00, ///< 349 Module Revision Code
> - 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 352 DRAM Stepping
> - 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
> - 0, 0 ///< 510 - 511
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp16SpdSize = sizeof (mSkylakeRvp16Spd);
> -
> -//Hynix H9CCNNNBJTMLAR-NUD, DDP, LPDDR3, 8Gb die
> -//1867
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd110[] = {
> - 0x91, ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
> - 0x20, ///< 1 SPD Revision
> - 0xF1, ///< 2 DRAM Device Type
> - 0x03, ///< 3 Module Type
> - 0x05, ///< 4 SDRAM Density and Banks, 8Gb
> - 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns
> - 0x05, ///< 6 Module Nominal Voltage
> - 0x0B, ///< 7 Module Organization: 32 bits, 2 Ranks
> - 0x03, ///< 8 Module Memory Bus Width
> - 0x11, ///< 9 Fine Timebase (FTB) Dividend / Divisor
> - 0x01, ///< 10 Medium Timebase (MTB) Dividend
> - 0x08, ///< 11 Medium Timebase (MTB) Divisor
> - 0x09, ///< 12 SDRAM Minimum Cycle Time (tCKmin): tCKmin = 1.071 ns (LPDDR3-1867)
> - 0x00, ///< 13 Reserved0
> - 0x50, ///< 14 CAS Latencies supported (tCK): 14, 12, 10, 8 (LSB)
> - 0x05, ///< 15 CAS Latencies supported (tCK): 14, 12, 10, 8 (LSB)
> - 0x78, ///< 16 Minimum CAS Latency (tAAmin) = 14.994 ns
> - 0x78, ///< 17 Minimum Write Recovery Time (tWRmin)
> - 0x90, ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0x50, ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
> - 0x90, ///< 20 Minimum Row Precharge Delay Time (tRPmin)
> - 0x11, ///< 21 Upper Nibbles for tRAS and tRC
> - 0x50, ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
> - 0xE0, ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
> - 0x90, ///< 24 Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
> - 0x06, ///< 25 Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte
> - 0x3C, ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
> - 0x3C, ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
> - 0x01, ///< 28 Upper Nibble for tFAW
> - 0x90, ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)
> - 0x00, ///< 30 SDRAM Optional Features
> - 0x00, ///< 31 SDRAMThermalAndRefreshOptions
> - 0x00, ///< 32 ModuleThermalSensor
> - 0x00, ///< 33 SDRAM Device Type
> - 0xCA, ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR3-1867)
> - 0xFA, ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)
> - 0x00, ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0x00, ///< 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
> - 0x00, ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
> - 0xA8, ///< 39 Row precharge time for all banks (tRPab)
> - 0x00, ///< 40 FTB for Row precharge time for all banks (tRPab)
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
> - 0, 0, ///< 60 - 61
> - 0x00, ///< 62 Reference Raw Card Used
> - 0x00, ///< 63 Address Mapping from Edge Connector to DRAM
> - 0x00, ///< 64 ThermalHeatSpreaderSolution
> - 0, 0, 0, 0, 0, ///< 65 - 69
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
> - 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116
> - 0x00, ///< 117 Module Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 118 Module Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 119 Module Manufacturing Location
> - 0x00, ///< 120 Module Manufacturing Date Year
> - 0x00, ///< 121 Module Manufacturing Date creation work week
> - 0x55, ///< 122 Module Serial Number A
> - 0x00, ///< 123 Module Serial Number B
> - 0x00, ///< 124 Module Serial Number C
> - 0x00, ///< 125 Module Serial Number D
> - 0x00, ///< 126 CRC A
> - 0x00 ///< 127 CRC B
> -};
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3Spd110Size = sizeof (mSkylakeRvp3Spd110);
> -
> -//
> -// Micron MT52L512M32D2PF 78b DDP LPDDR3, 8Gb die (256Mx32), x32
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mKblRSpdLpddr32133[] = {
> - 0x91, ///< 0 128 SPD bytes used, 256 total, CRC covers 0..116
> - 0x20, ///< 1 SPD Revision 2.0
> - 0xF1, ///< 2 DRAM Type: LPDDR3 SDRAM
> - 0x03, ///< 3 Module Type: SO-DIMM
> - 0x05, ///< 4 8 Banks, 8 Gb SDRAM density
> - 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns
> - 0x05, ///< 6 Module Nominal Voltage VDD: 1.2v
> - 0x0B, ///< 7 SDRAM width: 32 bits, 2 Ranks
> - 0x03, ///< 8 SDRAM bus width: 64 bits, no ECC
> - 0x11, ///< 9 Fine Timebase (FTB) granularity: 1 ps
> - 0x01, ///< 10 Medium Timebase (MTB) : 0.125 ns
> - 0x08, ///< 11 Medium Timebase Divisor
> - 0x08, ///< 12 tCKmin = 0.938 ns (LPDDR3-2133)
> - 0x00, ///< 13 Reserved
> - 0x50, ///< 14 CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (LSB)
> - 0x15, ///< 15 CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (MSB)
> - 0x78, ///< 16 Minimum CAS Latency (tAAmin) = 15.008 ns
> - 0x78, ///< 17 tWR = 15 ns
> - 0x90, ///< 18 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
> - 0x50, ///< 19 tRRD = 10 ns
> - 0x90, ///< 20 Minimum row precharge time (tRPmin) = 18 ns
> - 0x11, ///< 21 Upper nibbles for tRAS and tRC
> - 0x50, ///< 22 tRASmin = 42 ns
> - 0xE0, ///< 23 tRCmin = (tRASmin + tRPmin) = 60 ns
> - 0x90, ///< 24 tRFCmin = (tRFCab) = 210 ns (8Gb)
> - 0x06, ///< 25 tRFCmin MSB
> - 0x3C, ///< 26 tWTRmin = 7.5 ns
> - 0x3C, ///< 27 tRTPmin = 7.5 ns
> - 0x01, ///< 28 tFAWmin upper nibble
> - 0x90, ///< 29 tFAWmin = 50 ns
> - 0x00, ///< 30 SDRAM Optional Features - none
> - 0x00, ///< 31 SDRAM Thermal / Refresh options - none
> - 0x00, ///< 32 ModuleThermalSensor
> - 0x00, ///< 33 SDRAM Device Type
> - 0xC2, ///< 34 FTB for tCKmin = 0.938 ns (LPDDR3-2133)
> - 0x08, ///< 35 FTB for tAAmin = 15.008 ns (LPDDR3-2133)
> - 0x00, ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0x00, ///< 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
> - 0x00, ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
> - 0xA8, ///< 39 Row precharge time for all banks (tRPab)= 21 ns
> - 0x00, ///< 40 FTB for Row precharge time for all banks (tRPab) = 0
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
> - 0, 0, ///< 60 - 61
> - 0x00, ///< 62 Reference Raw Card Used
> - 0x00, ///< 63 Rank1 Mapping: Standard
> - 0x00, ///< 64 ThermalHeatSpreaderSolution
> - 0, 0, 0, 0, 0, ///< 65 - 69
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
> - 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116
> - 0x00, ///< 117 Module Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 118 Module Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 119 Module Manufacturing Location
> - 0x00, ///< 120 Module Manufacturing Date Year
> - 0x00, ///< 121 Module Manufacturing Date creation work week
> - 0x55, ///< 122 Module ID: Module Serial Number
> - 0x00, ///< 123 Module Serial Number B
> - 0x00, ///< 124 Module Serial Number C
> - 0x00, ///< 125 Module Serial Number D
> - 0x00, ///< 126 CRC A
> - 0x00 ///< 127 CRC B
> -};
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mKblRSpdLpddr32133Size = sizeof (mKblRSpdLpddr32133);
> -
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSpdLpddr32133[] = {
> - 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size
> - 0x01, ///< 1 SPD Revision
> - 0x0F, ///< 2 DRAM Device Type
> - 0x0E, ///< 3 Module Type
> - 0x15, ///< 4 SDRAM Density and Banks: 8 Banks, 8 Gb SDRAM density
> - 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns
> - 0x90, ///< 6 SDRAM Package Type: QDP, 1 Channel per die, Signal Loading Matrix 1
> - 0x00, ///< 7 SDRAM Optional Features
> - 0x00, ///< 8 SDRAM Thermal and Refresh Options
> - 0x00, ///< 9 Other SDRAM Optional Features
> - 0x00, ///< 10 Reserved - must be coded as 0x00
> - 0x0B, ///< 11 Module Nominal Voltage, VDD
> - 0x0B, ///< 12 Module Organization, SDRAM width: 32 bits, 2 Ranks
> - 0x03, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width
> - 0x00, ///< 14 Module Thermal Sensor
> - 0x00, ///< 15 Extended Module Type
> - 0x00, ///< 16 Reserved - must be coded as 0x00
> - 0x00, ///< 17 Timebases
> - 0x08, ///< 18 SDRAM Minimum Cycle Time (tCKmin)
> - 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax)
> - 0xD4, ///< 20 CAS Latencies Supported, First Byte
> - 0x01, ///< 21 CAS Latencies Supported, Second Byte
> - 0x00, ///< 22 CAS Latencies Supported, Third Byte
> - 0x00, ///< 23 CAS Latencies Supported, Fourth Byte
> - 0x78, ///< 24 Minimum CAS Latency Time (tAAmin)
> - 0x00, ///< 25 Read and Write Latency Set Options
> - 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab)
> - 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb)
> - 0x90, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte
> - 0x06, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte
> - 0xD0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
> - 0x02, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
> - 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping
> - 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping
> - 0, 0, ///< 78 - 79
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
> - 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb)
> - 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
> - 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0x08, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
> - 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
> - 0xC2, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
> - 0x00, ///< 126 CRC A
> - 0x00, ///< 127 CRC B
> - 0, 0, ///< 128 - 129
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
> - 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 322 Module Manufacturing Location
> - 0x00, ///< 323 Module Manufacturing Date Year
> - 0x00, ///< 324 Module Manufacturing Date Week
> - 0x55, ///< 325 Module Serial Number A
> - 0x00, ///< 326 Module Serial Number B
> - 0x00, ///< 327 Module Serial Number C
> - 0x00, ///< 328 Module Serial Number D
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
> - 0x00, ///< 349 Module Revision Code
> - 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 352 DRAM Stepping
> - 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
> - 0, 0 ///< 510 - 511
> -};
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSpdLpddr32133Size = sizeof (mSpdLpddr32133);
> -
> -/**
> - Hynix H9CCNNN8JTMLAR-NTM_178b_DDP LPDDR3, 4Gb die (128Mx32), x32
> - or Elpida EDF8132A1MC-GD-F
> - or Samsung K4E8E304EB-EGCE
> - 1600, 12-15-15-34
> - 2 rank per channel, 2 SDRAMs per rank, 4x4Gb = 2GB total per channel
> -**/
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd[] = {
> - 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size
> - 0x20, ///< 1 SPD Revision
> - 0x0F, ///< 2 DRAM Device Type
> - 0x0E, ///< 3 Module Type
> - 0x14, ///< 4 SDRAM Density and Banks: 8 Banks, 4 Gb SDRAM density
> - 0x11, ///< 5 SDRAM Addressing: 14 Rows, 10 Columns
> - 0x95, ///< 6 SDRAM Package Type: DDP, 1 Channel per die, Signal Loading Matrix 1
> - 0x00, ///< 7 SDRAM Optional Features
> - 0x00, ///< 8 SDRAM Thermal and Refresh Options
> - 0x00, ///< 9 Other SDRAM Optional Features
> - 0x00, ///< 10 Reserved - must be coded as 0x00
> - 0x03, ///< 11 Module Nominal Voltage, VDD
> - 0x0B, ///< 12 Module Organization, SDRAM width: 32 bits, 2 Ranks
> - 0x23, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width
> - 0x00, ///< 14 Module Thermal Sensor
> - 0x00, ///< 15 Extended Module Type
> - 0x00, ///< 16 Reserved - must be coded as 0x00
> - 0x00, ///< 17 Timebases
> - 0x0A, ///< 18 SDRAM Minimum Cycle Time (tCKmin)
> - 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax)
> - 0x54, ///< 20 CAS Latencies Supported, First Byte (tCk): 12 10 8
> - 0x00, ///< 21 CAS Latencies Supported, Second Byte
> - 0x00, ///< 22 CAS Latencies Supported, Third Byte
> - 0x00, ///< 23 CAS Latencies Supported, Fourth Byte
> - 0x78, ///< 24 Minimum CAS Latency Time (tAAmin)
> - 0x00, ///< 25 Read and Write Latency Set Options
> - 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab)
> - 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb)
> - 0x10, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte
> - 0x04, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte
> - 0xE0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
> - 0x01, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
> - 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping
> - 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping
> - 0, 0, ///< 78 - 79
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
> - 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb)
> - 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
> - 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
> - 0x00, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
> - 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
> - 0x00, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
> - 0x00, ///< 126 CRC A
> - 0x00, ///< 127 CRC B
> - 0, 0, ///< 128 - 129
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
> - 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 322 Module Manufacturing Location
> - 0x00, ///< 323 Module Manufacturing Date Year
> - 0x00, ///< 324 Module Manufacturing Date Week
> - 0x55, ///< 325 Module Serial Number A
> - 0x00, ///< 326 Module Serial Number B
> - 0x00, ///< 327 Module Serial Number C
> - 0x00, ///< 328 Module Serial Number D
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
> - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
> - 0x00, ///< 349 Module Revision Code
> - 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
> - 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
> - 0x00, ///< 352 DRAM Stepping
> - 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
> - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
> - 0, 0 ///< 510 - 511
> -};
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3SpdSize = sizeof (mSkylakeRvp3Spd);
> -#endif // _KABYLAKE_RVP3_SPD_TABLE_H_
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GDetect.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GDetect.c
> index 429f4316dd64..7dac213c6df0 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GDetect.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GDetect.c
> @@ -6,63 +6,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include <PiPei.h>
> -#include <SaPolicyCommon.h>
> +#include "PeiAspireVn7Dash572GInitLib.h"
> +#include <Library/BoardEcLib.h>
> #include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/HobLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PchCycleDecodingLib.h>
> -#include <Library/PciLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/BaseMemoryLib.h>
>
> -#include <Library/PeiSaPolicyLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <PchAccess.h>
> -#include <Library/GpioNativeLib.h>
> -#include <Library/GpioLib.h>
> -#include <GpioPinsSklLp.h>
> -#include <GpioPinsSklH.h>
> -#include <Library/GpioExpanderLib.h>
> -#include <SioRegs.h>
> -#include <Library/PchPcrLib.h>
> -#include <Library/SiliconInitLib.h>
> -
> -#include "PeiKabylakeRvp3InitLib.h"
> -
> -#include <ConfigBlock.h>
> -#include <ConfigBlock/MemoryConfig.h>
> -#include <Library/EcLib.h>
> -#include <EcCommands.h>
> -
> -#define BOARD_ID_MASK_8BIT 0xff
> -
> -/**
> - Get board fab ID.
> -
> - @param[out] DataBuffer
> -
> - @retval EFI_SUCCESS Command success
> - @retval EFI_DEVICE_ERROR Command error
> -**/
> -EFI_STATUS
> -GetBoardFabId (
> - OUT UINT8 *DataBuffer
> - )
> -{
> - UINT8 DataSize;
> -
> - //
> - // For 'EC_C_FAB_ID' command NumberOfSendData = 0, NumberOfReceiveData =2.
> - //
> - DataSize = 2;
> - return (LpcEcInterface (EC_C_FAB_ID, &DataSize, DataBuffer));
> -}
> +#define ADC_3V_10BIT_GRANULARITY_MAX (3005/1023)
> +#define PCB_VER_AD 1
> +#define MODEL_ID_AD 3
>
> /**
> - Get RVP3 board ID.
> - There are 2 different RVP3 boards having different ID.
> + Get Aspire V Nitro (Skylake) board ID.
> + There are 2 different boards having different ID.
> This function will return board ID to caller.
>
> @param[out] DataBuffer
> @@ -71,35 +25,57 @@ GetBoardFabId (
> @retval EFI_DEVICE_ERROR Command error
> **/
> EFI_STATUS
> -GetRvp3BoardId (
> - UINT8 *BoardId
> +GetAspireVn7Dash572GBoardId (
> + OUT UINT8 *BoardId
> )
> {
> EFI_STATUS Status;
> - UINT16 EcBoardInfo;
> - UINT8 DataBuffer[2];
> + UINT16 DataBuffer;
>
> - Status = GetBoardFabId (DataBuffer);
> - if (Status == EFI_SUCCESS) {
> - EcBoardInfo = DataBuffer[0];
> - EcBoardInfo = (EcBoardInfo << 8) | DataBuffer[1];
> - //
> - // Get the following data:
> - // [7:0] - BOARD_IDx
> - // [8] - GEN_ID
> - // [11:9] - REV_FAB_IDx
> - // [12] - TP_SPD_PRSNT
> - // [15:13] - BOM_IDx
> - //
> - *BoardId = (UINT8) (EcBoardInfo & BOARD_ID_MASK_8BIT);
> - DEBUG ((DEBUG_INFO, "BoardId = %X\n", *BoardId));
> + Status = ReadEcAdcConverter (MODEL_ID_AD, &DataBuffer);
> + if (!EFI_ERROR(Status)) {
> + DEBUG ((DEBUG_INFO, "BoardId (raw) = 0x%X\n", DataBuffer));
> + // Board by max millivoltage range (of 10-bit, 3.005 V ADC)
> + if (DataBuffer <= (1374/ADC_3V_10BIT_GRANULARITY_MAX)) {
> + // Consider returning an error
> + DEBUG ((DEBUG_ERROR, "BoardId is reserved?\n"));
> + } else if (DataBuffer <= (2017/ADC_3V_10BIT_GRANULARITY_MAX)) {
> + *BoardId = BoardIdNewgateSLx_dGPU;
> + } else {
> + *BoardId = BoardIdRayleighSLx_dGPU;
> + }
> + DEBUG ((DEBUG_INFO, "BoardId = 0x%X\n", *BoardId));
> + } else {
> + DEBUG ((DEBUG_ERROR, "Unable to detect BoardId!\n"));
> }
> +
> + Status = ReadEcAdcConverter (PCB_VER_AD, &DataBuffer);
> + if (!EFI_ERROR(Status)) {
> + DEBUG ((DEBUG_INFO, "PCB version (raw) = 0x%X\n", DataBuffer));
> + DEBUG ((DEBUG_INFO, "PCB version: "));
> + // PCB by max millivoltage range (of 10-bit, 3.005 V ADC)
> + if (DataBuffer <= (2017/ADC_3V_10BIT_GRANULARITY_MAX)) {
> + // Consider returning an error
> + DEBUG ((DEBUG_ERROR, "Reserved?\n"));
> + } else if (DataBuffer <= (2259/ADC_3V_10BIT_GRANULARITY_MAX)) {
> + DEBUG ((DEBUG_ERROR, "-1\n"));
> + } else if (DataBuffer <= (2493/ADC_3V_10BIT_GRANULARITY_MAX)) {
> + DEBUG ((DEBUG_ERROR, "SC\n"));
> + } else if (DataBuffer <= (2759/ADC_3V_10BIT_GRANULARITY_MAX)) {
> + DEBUG ((DEBUG_ERROR, "SB\n"));
> + } else {
> + DEBUG ((DEBUG_ERROR, "SA\n"));
> + }
> + } else {
> + DEBUG ((DEBUG_ERROR, "Unable to detect PCB version!\n"));
> + }
> +
> return Status;
> }
>
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardDetect (
> +AspireVn7Dash572GBoardDetect (
> VOID
> )
> {
> @@ -109,14 +85,11 @@ KabylakeRvp3BoardDetect (
> return EFI_SUCCESS;
> }
>
> - DEBUG ((DEBUG_INFO, "KabylakeRvp3DetectionCallback\n"));
> - if (GetRvp3BoardId (&BoardId) == EFI_SUCCESS) {
> - if (BoardId == BoardIdKabyLakeYLpddr3Rvp3) {
> - LibPcdSetSku (BoardIdKabyLakeYLpddr3Rvp3);
> - ASSERT (LibPcdGetSku() == BoardIdKabyLakeYLpddr3Rvp3);
> - } else if (BoardId == BoardIdSkylakeRvp3) {
> - LibPcdSetSku (BoardIdSkylakeRvp3);
> - ASSERT (LibPcdGetSku() == BoardIdSkylakeRvp3);
> + DEBUG ((DEBUG_INFO, "AspireVn7Dash572GDetectionCallback\n"));
> + if (GetAspireVn7Dash572GBoardId (&BoardId) == EFI_SUCCESS) {
> + if (BoardId == BoardIdNewgateSLx_dGPU || BoardId == BoardIdRayleighSLx_dGPU) {
> + LibPcdSetSku (BoardId);
> + ASSERT (LibPcdGetSku() == BoardId);
> }
> DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
> }
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitLib.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitLib.h
> index 5b2ccf6b0dea..83789c90becf 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitLib.h
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitLib.h
> @@ -5,8 +5,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
>
> -#ifndef _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_
> -#define _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_
> +#ifndef _PEI_ASPIRE_VN7_572G_BOARD_INIT_LIB_H_
> +#define _PEI_ASPIRE_VN7_572G_BOARD_INIT_LIB_H_
>
> #include <Uefi.h>
> #include <Library/BaseLib.h>
> @@ -16,29 +16,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <Library/GpioLib.h>
> #include <Ppi/SiPolicy.h>
> #include <PchHsioPtssTables.h>
> -#include <IoExpander.h>
>
> #include <PlatformBoardId.h>
>
> -extern const UINT8 mDqByteMapSklRvp3[2][6][2];
> -extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8];
> -extern const UINT8 mSkylakeRvp3Spd110[];
> -extern const UINT16 mSkylakeRvp3Spd110Size;
> -extern const UINT8 mSkylakeRvp3Spd[];
> -extern const UINT16 mSkylakeRvp3SpdSize;
> -extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[];
> -extern UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size;
> -extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[];
> -extern UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size;
> +extern HSIO_PTSS_TABLES PchLpHsioPtss_AspireVn7Dash572G[];
> +extern UINT16 PchLpHsioPtss_AspireVn7Dash572G_Size;
>
> -extern HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3;
> -extern GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[];
> -extern UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize;
> +extern HDAUDIO_VERB_TABLE HdaVerbTableAlc255AspireVn7Dash572G;
> +extern HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio;
>
> -extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[];
> -extern UINT16 mGpioTableIoExpanderSize;
> -extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel;
> -extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[];
> -extern UINT16 mGpioTableLpDdr3Rvp3Size;
> +extern GPIO_INIT_CONFIG mGpioTableAspireVn7Dash572G[];
> +extern UINT16 mGpioTableAspireVn7Dash572GSize;
> +extern GPIO_INIT_CONFIG mGpioTableAspireVn7Dash572G_early[];
> +extern UINT16 mGpioTableAspireVn7Dash572G_earlySize;
>
> -#endif // _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_
> +#endif // _PEI_ASPIRE_VN7_572G_BOARD_INIT_LIB_H_
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPostMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPostMemLib.c
> index 5d398ab6654e..2ff3e556a0cc 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPostMemLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPostMemLib.c
> @@ -6,32 +6,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include <PiPei.h>
> -#include <SaPolicyCommon.h>
> #include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/HobLib.h>
> +#include <Library/BoardEcLib.h>
> #include <Library/PcdLib.h>
> -#include <Library/PchCycleDecodingLib.h>
> -#include <Library/PciLib.h>
> -#include <Library/PeiSaPolicyLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <PchAccess.h>
> -#include <Library/GpioNativeLib.h>
> #include <Library/GpioLib.h>
> -#include <GpioPinsSklLp.h>
> -#include <GpioPinsSklH.h>
> -#include <Library/GpioExpanderLib.h>
> -#include <SioRegs.h>
> -#include <Library/PchPcrLib.h>
> -#include <IoExpander.h>
> -#include <Library/PcdLib.h>
> #include <Library/SiliconInitLib.h>
> +#include <GpioPinsSklLp.h>
>
> -#include "PeiKabylakeRvp3InitLib.h"
> +#include "PeiAspireVn7Dash572GInitLib.h"
>
> /**
> - SkylaeA0Rvp3 board configuration init function for PEI post memory phase.
> + Aspire VN7-572G board configuration init function for PEI post memory phase.
>
> PEI_BOARD_CONFIG_PCD_INIT
>
> @@ -42,147 +27,81 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3Init (
> +AspireVn7Dash572GInit (
> VOID
> )
> {
> - PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc286Rvp3);
> -
> - //
> - // Assign the GPIO table with pin configs to be used for UCMC
> - //
> - PcdSet32S (PcdBoardUcmcGpioTable, (UINTN)mGpioTableLpddr3Rvp3UcmcDevice);
> - PcdSet16S (PcdBoardUcmcGpioTableSize, mGpioTableLpddr3Rvp3UcmcDeviceSize);
> + PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc255AspireVn7Dash572G);
> + PcdSet32S (PcdDisplayAudioHdaVerbTable, (UINTN) &HdaVerbTableDisplayAudio);
>
> return EFI_SUCCESS;
> }
>
> -#define EXPANDERS 2 // defines expander's quantity
>
> /**
> Configures GPIO
>
> - @param[in] GpioTable Point to Platform Gpio table
> - @param[in] GpioTableCount Number of Gpio table entries
> -
> **/
> VOID
> -ConfigureGpio (
> - IN GPIO_INIT_CONFIG *GpioDefinition,
> - IN UINT16 GpioTableCount
> +GpioInitPostMem (
> + VOID
> )
> {
> - EFI_STATUS Status;
> -
> - DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
> + DEBUG ((DEBUG_INFO, "GpioInitPostMem() Start\n"));
>
> - Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
> + GpioConfigurePads (mGpioTableAspireVn7Dash572GSize, mGpioTableAspireVn7Dash572G);
>
> - DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
> + DEBUG ((DEBUG_INFO, "GpioInitPostMem() End\n"));
> }
>
Please add a header comment that describes what this ec_fills_time() function does.
> VOID
> -SetBit (
> - IN OUT UINT32 *Value,
> - IN UINT32 BitNumber,
> - IN BOOLEAN NewBitValue
> +ec_fills_time (
Function name doesn't follow EDK II coding style guidelines. Please rename to EcFillsTime().
> + VOID
> )
> {
> - if (NewBitValue) {
> - *Value |= 1 << BitNumber;
> - } else {
> - *Value &= ~(1 << BitNumber);
> +#if 0
Please don't commit commented out/#if 0 code.
> + struct rtc_time time;
> + rtc_get(&time);
> +
> + u8 ec_time_byte;
> + int ec_time = ((time.year << 26) + (time.mon << 22) + (time.mday << 17)
> + + (time.hour << 12) + (time.min << 6) + (time.sec)
> + /* 16 years */
> + - 0x40000000);
> +
> + printk(BIOS_DEBUG, "EC: reporting present time 0x%x\n", ec_time);
> + send_ec_command(0xE0);
> + for (int i = 0; i < 4; i++) {
> + ec_time_byte = ec_time >> (i*sizeof(ec_time_byte));
> + printk(BIOS_DEBUG, "EC: Sending 0x%x (iteration %d)\n", ec_time_byte, i);
> + send_ec_data(ec_time_byte);
> }
> -}
>
> -/**
> - Configures IO Expander GPIO device
> -
> - @param[in] IOExpGpioDefinition Point to IO Expander Gpio table
> - @param[in] IOExpGpioTableCount Number of Gpio table entries
> -
> -**/
> -void
> -ConfigureIoExpanderGpio (
> - IN IO_EXPANDER_GPIO_CONFIG *IoExpGpioDefinition,
> - IN UINT16 IoExpGpioTableCount
> - )
> -{
> - UINT8 Index;
> - UINT32 Direction[EXPANDERS] = {0x00FFFFFF, 0x00FFFFFF};
> - UINT32 Level[EXPANDERS] = {0};
> - UINT32 Polarity[EXPANDERS] = {0};
> -
> - // IoExpander {TCA6424A}
> - DEBUG ((DEBUG_INFO, "IO Expander Configuration Start\n"));
> - for (Index = 0; Index < IoExpGpioTableCount; Index++) { //Program IO Expander as per the table defined in PeiPlatformHooklib.c
> - SetBit(&Direction[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioDirection);
> - SetBit(&Level[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioLevel);
> - SetBit(&Polarity[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioInversion);
> - }
> - for (Index = 0; Index < EXPANDERS; Index++) {
> - GpioExpBulkConfig(Index, Direction[Index], Polarity[Index], Level[Index]);
> - }
> - DEBUG ((DEBUG_INFO, "IO Expander Configuration End\n"));
> - return;
> + printk(BIOS_DEBUG, "EC: response 0x%x\n", recv_ec_data());
> +#endif
> }
>
> /**
> - Configure GPIO behind IoExpander.
> -
> - @param[in] PeiServices General purpose services available to every PEIM.
> - @param[in] NotifyDescriptor
> - @param[in] Interface
> + Configure EC
> + FIXME: Move to DXE phase library (RTC protocol available).
> + Only use new module if required hook is unavailable.
>
> - @retval EFI_SUCCESS Operation success.
> **/
> VOID
> -ExpanderGpioInit (
> +EcInit (
> VOID
> )
> {
> - ConfigureIoExpanderGpio(mGpioTableIoExpander, mGpioTableIoExpanderSize);
> -}
> -
> -/**
> - Configure single GPIO pad for touchpanel interrupt
> + UINT8 Dat;
>
> -**/
> -VOID
> -TouchpanelGpioInit (
> - VOID
> - )
> -{
> - GPIO_INIT_CONFIG* TouchpanelPad;
> - GPIO_PAD_OWN PadOwnVal;
> -
> - PadOwnVal = 0;
> - TouchpanelPad = &mGpioTableLpDdr3Rvp3Touchpanel;
> -
> - GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal);
> - if (PadOwnVal == GpioPadOwnHost) {
> - GpioConfigurePads (1, TouchpanelPad);
> + /* UEFI modules "notify" this protocol in RtKbcDriver */
> + EcCmd90Read(0x79, &Dat);
> + if (Dat & 1) {
> + ec_fills_time();
> }
> }
>
>
> -/**
> - Configure GPIO
> -
> -**/
> -VOID
> -GpioInit (
> - VOID
> - )
> -{
> - ConfigureGpio (mGpioTableLpDdr3Rvp3, mGpioTableLpDdr3Rvp3Size);
> -
> - TouchpanelGpioInit();
> -
> - return;
> -}
> -
> -
> /**
> Configure GPIO and SIO
>
> @@ -190,14 +109,13 @@ GpioInit (
> **/
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardInitBeforeSiliconInit (
> +AspireVn7Dash572GBoardInitBeforeSiliconInit (
> VOID
> )
> {
> - KabylakeRvp3Init ();
> -
> - GpioInit ();
> - ExpanderGpioInit ();
> + EcInit ();
> + GpioInitPostMem ();
> + AspireVn7Dash572GInit ();
>
Please delete trailing whitespace
> ///
> /// Do Late PCH init
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
> index d34b0be3c7f6..e283373f1d19 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
> @@ -6,123 +6,56 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include <PiPei.h>
> -#include <SaPolicyCommon.h>
> +#include <Library/BoardEcLib.h>
> #include <Library/DebugLib.h>
> -#include <Library/BaseMemoryLib.h>
> +#include <Library/EcLib.h>
> #include <Library/IoLib.h>
> -#include <Library/HobLib.h>
> +#include <Library/MemoryAllocationLib.h>
> #include <Library/PcdLib.h>
> #include <Library/PchCycleDecodingLib.h>
> -#include <Library/PciLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/BaseMemoryLib.h>
> +#include <Library/PchResetLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/SiliconInitLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/PeiLib.h>
>
> -#include <Library/PeiSaPolicyLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <PchAccess.h>
> -#include <Library/GpioNativeLib.h>
> #include <Library/GpioLib.h>
> #include <GpioPinsSklLp.h>
> -#include <GpioPinsSklH.h>
> -#include <Library/GpioExpanderLib.h>
> -#include <SioRegs.h>
> -#include <Library/PchPcrLib.h>
> -#include <Library/SiliconInitLib.h>
> -#include <Library/PchResetLib.h>
> +#include <IndustryStandard/TpmPtp.h>
> +#include <PchAccess.h>
>
> -#include "PeiKabylakeRvp3InitLib.h"
> +#include "PeiAspireVn7Dash572GInitLib.h"
>
> #include <ConfigBlock.h>
> #include <ConfigBlock/MemoryConfig.h>
>
> +#ifndef STALL_ONE_MILLI_SECOND
> +#define STALL_ONE_MILLI_SECOND 1000
> +#endif
> +
> //
> -// Reference RCOMP resistors on motherboard - for SKL RVP1
> +// Reference RCOMP resistors on motherboard - for Aspire VN7-572G
> //
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 };
> +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorAspireVn7Dash572G[SA_MRC_MAX_RCOMP] = { 121, 80, 100 };
> //
> -// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP1
> +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for Aspire VN7-572G
> //
> -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
> -
> -/**
> - SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.
> +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetAspireVn7Dash572G[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
>
> - PEI_BOARD_CONFIG_PCD_INIT
> -
> - @param Content pointer to the buffer contain init information for board init.
> +//
> +// dGPU power GPIO definitions
> +#define DGPU_PRESENT GPIO_SKL_LP_GPP_A20 /* Active low */
> +#define DGPU_HOLD_RST GPIO_SKL_LP_GPP_B4 /* Active low */
> +#define DGPU_PWR_EN GPIO_SKL_LP_GPP_B21 /* Active low */
>
> - @retval EFI_SUCCESS The function completed successfully.
> - @retval EFI_INVALID_PARAMETER The parameter is NULL.
> -**/
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3InitPreMem (
> +AspireVn7Dash572GBoardDetect (
> VOID
> - )
> -{
> - PcdSet32S (PcdPcie0WakeGpioNo, 0);
> - PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
> - PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
> - PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
> - PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
> - PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
> - PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
> -
> - //
> - // HSIO PTSS Table
> - //
> - PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3);
> - PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3_Size);
> - PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3);
> - PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3_Size);
> -
> - //
> - // DRAM related definition
> - //
> - PcdSet8S (PcdSaMiscUserBd, 5);
> -
> - PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);
> - PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));
> - PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);
> - PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));
> - PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);
> - PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);
> - //
> - // Example policy for DIMM slots implementation boards:
> - // 1. Assign Smbus address of DIMMs and SpdData will be updated later
> - // by reading from DIMM SPD.
> - // 2. No need to apply hardcoded SpdData buffers here for such board.
> - // Example:
> - // PcdMrcSpdAddressTable0 = 0xA0
> - // PcdMrcSpdAddressTable1 = 0xA2
> - // PcdMrcSpdAddressTable2 = 0xA4
> - // PcdMrcSpdAddressTable3 = 0xA6
> - // PcdMrcSpdData = 0
> - // PcdMrcSpdDataSize = 0
> - //
> - // Kabylake RVP3 has 8GB Memory down implementation withouit SPD,
> - // So assign all SpdAddress to 0 and apply static SpdData buffers:
> - // PcdMrcSpdAddressTable0 = 0
> - // PcdMrcSpdAddressTable1 = 0
> - // PcdMrcSpdAddressTable2 = 0
> - // PcdMrcSpdAddressTable3 = 0
> - // PcdMrcSpdData = static data buffer
> - // PcdMrcSpdDataSize = sizeof (static data buffer)
> - //
> - PcdSet8S (PcdMrcSpdAddressTable0, 0);
> - PcdSet8S (PcdMrcSpdAddressTable1, 0);
> - PcdSet8S (PcdMrcSpdAddressTable2, 0);
> - PcdSet8S (PcdMrcSpdAddressTable3, 0);
> - PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110);
> - PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size);
> -
> - PcdSetBoolS (PcdIoExpanderPresent, TRUE);
> -
> - return EFI_SUCCESS;
> -}
> + );
>
> /**
> - SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.
> + Aspire VN7-572G board configuration init function for PEI pre-memory phase.
>
> PEI_BOARD_CONFIG_PCD_INIT
>
> @@ -133,37 +66,28 @@ KabylakeRvp3InitPreMem (
> **/
> EFI_STATUS
> EFIAPI
> -SkylakeRvp3InitPreMem (
> +AspireVn7Dash572GInitPreMem (
> VOID
> )
> {
> - PcdSet32S (PcdPcie0WakeGpioNo, 0);
> - PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
> - PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
> - PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
> - PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
> - PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
> - PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
> -
> //
> // HSIO PTSS Table
> //
> - PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3);
> - PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3_Size);
> - PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3);
> - PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3_Size);
> + PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_AspireVn7Dash572G);
> + PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_AspireVn7Dash572G_Size);
> + PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_AspireVn7Dash572G);
> + PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_AspireVn7Dash572G_Size);
>
> //
> // DRAM related definition
> //
> - PcdSet8S (PcdSaMiscUserBd, 5);
> + PcdSet8S (PcdSaMiscUserBd, 5); // ULT/ULX/Mobile Halo
> + PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4: "VREF_CA to CH_A and VREF_DQ_B to CH_B"
> + // TODO: Clear Dq/Dqs?
> + PcdSetBoolS (PcdMrcDqPinsInterleaved, TRUE);
>
> - PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);
> - PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));
> - PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);
> - PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));
> - PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);
> - PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);
> + PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorAspireVn7Dash572G);
> + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetAspireVn7Dash572G);
> //
> // Example policy for DIMM slots implementation boards:
> // 1. Assign Smbus address of DIMMs and SpdData will be updated later
> @@ -177,53 +101,18 @@ SkylakeRvp3InitPreMem (
> // PcdMrcSpdData = 0
> // PcdMrcSpdDataSize = 0
> //
> - // Skylake RVP3 has 4GB Memory down implementation withouit SPD,
> - // So assign all SpdAddress to 0 and apply static SpdData buffers:
> - // PcdMrcSpdAddressTable0 = 0
> - // PcdMrcSpdAddressTable1 = 0
> - // PcdMrcSpdAddressTable2 = 0
> - // PcdMrcSpdAddressTable3 = 0
> - // PcdMrcSpdData = static data buffer
> - // PcdMrcSpdDataSize = sizeof (static data buffer)
> - //
> - PcdSet8S (PcdMrcSpdAddressTable0, 0);
> + PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
> PcdSet8S (PcdMrcSpdAddressTable1, 0);
> - PcdSet8S (PcdMrcSpdAddressTable2, 0);
> + PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);
> PcdSet8S (PcdMrcSpdAddressTable3, 0);
> - PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd);
> - PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3SpdSize);
> -
> - PcdSetBoolS (PcdIoExpanderPresent, TRUE);
> + PcdSet32S (PcdMrcSpdData, 0);
> + PcdSet16S (PcdMrcSpdDataSize, 0);
>
> return EFI_SUCCESS;
> }
>
> -#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680
> -
> -/**
> - Configures GPIO.
> -
> - @param[in] GpioTable Point to Platform Gpio table
> - @param[in] GpioTableCount Number of Gpio table entries
> -
> -**/
> -VOID
> -ConfigureGpio (
> - IN GPIO_INIT_CONFIG *GpioDefinition,
> - IN UINT16 GpioTableCount
> - )
> -{
> - EFI_STATUS Status;
> -
> - DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
> -
> - Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
> -
> - DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
> -}
> -
> /**
> - Configure GPIO Before Memory is not ready.
> + Configures GPIO before memory is ready.
>
> **/
> VOID
> @@ -231,45 +120,96 @@ GpioInitPreMem (
> VOID
> )
> {
> - // ConfigureGpio ();
> + DEBUG ((DEBUG_INFO, "GpioInitPreMem() Start\n"));
> +
> + GpioConfigurePads (mGpioTableAspireVn7Dash572G_earlySize, mGpioTableAspireVn7Dash572G_early);
> +
> + DEBUG ((DEBUG_INFO, "GpioInitPreMem() End\n"));
> }
>
> /**
> - Configure Super IO.
> + Init based on PeiOemModule. KbcPeim does not appear to be used.
> + It implements commands also found in RtKbcDriver and SmmKbcDriver.
>
> **/
> VOID
> -SioInit (
> +EcInit (
> VOID
> )
> {
> - //
> - // Program and Enable Default Super IO Configuration Port Addresses and range
> - //
> - PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
> + EFI_BOOT_MODE BootMode;
> + UINT8 PowerRegister;
> + UINT8 OutData;
> + UINT32 GpeSts;
>
> - //
> - // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
> - //
> - PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);
> + /* This is called via a "$FNC" in a PeiOemModule pointer table */
> + IoWrite8(0x6C, 0x5A); // 6Ch is the EC sideband port
> + PeiServicesGetBootMode(&BootMode);
> + if (BootMode == BOOT_ON_S3_RESUME) {
> + /* "MLID" in LGMR-based memory map is equivalent to "ELID" in EC-based
> + * memory map. Vendor firmware accesses through LGMR; remapped */
> + EcRead(0x70, &PowerRegister);
> + if (!(PowerRegister & BIT1)) { // Lid is closed
> + EcCmd90Read(0x0A, &OutData); // Code executed, do not remap
> + if (!(OutData & BIT1))
> + EcCmd91Write(0x0A, OutData | BIT1); // Code executed, do not remap
> +
> + /* TODO: Clear events and go back to sleep */
> + // pmc_clear_pm1_status();
> + /* Clear GPE0_STS[127:96] */
> +// GpeSts = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
> +// outl(GpeSts, ACPI_BASE_ADDRESS + GPE0_STS(3));
> + /* TODO: Clear xHCI PM_CS[PME_Status] - 74h[15]? */
> +
> +// pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S3 << SLP_TYP_SHIFT));
> +// halt();
> + }
> + }
> +}
> +
> +/**
> + Initialises the dGPU.
>
> - return;
> +**/
> +VOID
> +DgpuPowerOn (
> + VOID
> + )
> +{
> + UINT32 OutputVal;
> +
> + GpioGetOutputValue(DGPU_PRESENT, &OutputVal);
> + if (!OutputVal) {
> + GpioSetOutputValue(DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#
> + MicroSecondDelay(2 * STALL_ONE_MILLI_SECOND);
> + GpioSetOutputValue(DGPU_PWR_EN, 0); // Assert dGPU_PWR_EN#
> + MicroSecondDelay(7 * STALL_ONE_MILLI_SECOND);
> + GpioSetOutputValue(DGPU_HOLD_RST, 1); // Deassert dGPU_HOLD_RST#
> + MicroSecondDelay(30 * STALL_ONE_MILLI_SECOND);
> + } else {
> + GpioSetOutputValue(DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#
> + GpioSetOutputValue(DGPU_PWR_EN, 1); // Deassert dGPU_PWR_EN#
> + }
> }
>
> /**
> - Configues the IC2 Controller on which GPIO Expander Communicates.
> - This Function is to enable the I2CGPIOExapanderLib to programm the Gpios
> - Complete intilization will be done in later Stage
> + Configure LPC.
>
> **/
> VOID
> -EFIAPI
> -I2CGpioExpanderInitPreMem(
> +LpcInit (
> VOID
> )
> {
> - ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden);
> - SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSerialIoIs33V);
> + //
> + // Program and Enable EC (sideband) Port Addresses and range
> + //
> + PchLpcGenIoRangeSet (0x68, 0x08);
> +
> + //
> + // Program and Enable EC (index) Port Addresses and range
> + //
> + PchLpcGenIoRangeSet (0x1200, 0x10);
> }
>
> /**
> @@ -279,33 +219,29 @@ I2CGpioExpanderInitPreMem(
> **/
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardInitBeforeMemoryInit (
> +AspireVn7Dash572GBoardInitBeforeMemoryInit (
> VOID
> )
> {
> EFI_STATUS Status;
>
> - if (LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) {
> - KabylakeRvp3InitPreMem ();
> - } else if (LibPcdGetSku () == BoardIdSkylakeRvp3) {
> - SkylakeRvp3InitPreMem ();
> - }
> -
> - //
> - // Configures the I2CGpioExpander
> - //
> - if (PcdGetBool (PcdIoExpanderPresent)) {
> - I2CGpioExpanderInitPreMem();
> - }
> -
> + EcInit ();
> GpioInitPreMem ();
> - SioInit ();
> + DgpuPowerOn ();
> + AspireVn7Dash572GInitPreMem ();
>
> ///
> /// Do basic PCH init
> ///
> SiliconInit ();
>
> + //
> + // Fix-up LPC configuration
> + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64h and 62h/66h.
> + //
> + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
> + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
> +
> //
> // Install PCH RESET PPI and EFI RESET2 PeiService
> //
> @@ -315,9 +251,31 @@ KabylakeRvp3BoardInitBeforeMemoryInit (
> return EFI_SUCCESS;
> }
>
> +/**
> + Configure GPIO and SIO before memory ready.
> +
> + @retval EFI_SUCCESS Operation success.
> +**/
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardDebugInit (
> +AspireVn7Dash572GBoardInitAfterMemoryInit (
> + VOID
> + )
> +{
> + // BUGBUG: Workaround for a misbehaving system firmware not setting goIdle
> + // - Based on prior investigation for coreboot, I suspect FSP
> + if ((MmioRead32(0xFED40044) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0) {
> + MmioWrite32(0xFED40040, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
> + }
> +
> + // Program the same 64K range of EC memory as vendor FW; ignore failures
> + PchLpcMemRangeSet(0xFE800000);
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +AspireVn7Dash572GBoardDebugInit (
> VOID
> )
> {
> @@ -325,15 +283,62 @@ KabylakeRvp3BoardDebugInit (
> /// Do Early PCH init
> ///
> EarlySiliconInit ();
> + LpcInit ();
> +
> + // NB: MinPlatform specification defines platform initialisation flow.
> + // Therefore, we defer board detection until we can program LPC.
> + // - Alternatively, move the preceding calls to BoardDetect()
> + AspireVn7Dash572GBoardDetect ();
> +
> return EFI_SUCCESS;
> }
>
> EFI_BOOT_MODE
> EFIAPI
> -KabylakeRvp3BoardBootModeDetect (
> +AspireVn7Dash572GBoardBootModeDetect (
> VOID
> )
> {
> - return BOOT_WITH_FULL_CONFIGURATION;
> + UINT16 ABase;
> + UINT32 SleepType;
> +// EFI_STATUS Status;
> +// EFI_GUID BoardBdsHookDxeFileGuid = { 0xEEA6491C, 0x0DC5, 0x48AB, { 0xB9, 0x9D, 0xCE, 0x77, 0xD1, 0x4D, 0x43, 0xF2 } };
> +// VOID *IsFirstBoot;
> +// UINTN VariableSize;
> +// EFI_BOOT_MODE BootMode;
> +
> + // TODO: Perform advanced detection (recovery/capsule)
> + // FIXME: This violates PI specification? But BOOT_WITH* would always take precedence
> + // over BOOT_ON_S{4,5}...
> + PchAcpiBaseGet (&ABase);
> + SleepType = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT_SLP_TYP;
> +
> + switch (SleepType) {
> + case V_PCH_ACPI_PM1_CNT_S3:
> + return BOOT_ON_S3_RESUME;
> + case V_PCH_ACPI_PM1_CNT_S4:
> + return BOOT_ON_S4_RESUME;
> +// case V_PCH_ACPI_PM1_CNT_S5:
> +// return BOOT_ON_S5_RESUME;
> + default:
> + return BOOT_WITH_FULL_CONFIGURATION;
> + }
> +
> +#if 0 // FIXME: Very broken.
> + IsFirstBoot = NULL;
> + VariableSize = 0;
> + Status = PeiGetVariable (
> + L"IsFirstBoot",
> + &BoardBdsHookDxeFileGuid,
> + &IsFirstBoot,
> + &VariableSize
> + );
> + if (!EFI_ERROR(Status)) {
> + BootMode = (*(UINT8 *)IsFirstBoot == 0) ? BOOT_ASSUMING_NO_CONFIGURATION_CHANGES : BOOT_WITH_FULL_CONFIGURATION;
> + FreePool (IsFirstBoot);
> + return BootMode;
> + } else {
> + return BOOT_WITH_FULL_CONFIGURATION;
> + }
> +#endif
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c
> index 2e079a0387a5..86350e1ba8ac 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c
> @@ -1,5 +1,5 @@
> /** @file
> - Kaby Lake RVP 3 Board Initialization Post-Memory library
> + Aspire VN7-572G Board Initialization Post-Memory library
>
> Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -7,15 +7,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include <PiPei.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> #include <Library/BoardInitLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
>
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardInitBeforeSiliconInit (
> +AspireVn7Dash572GBoardInitBeforeSiliconInit (
> VOID
> );
>
> @@ -25,8 +21,7 @@ BoardInitBeforeSiliconInit (
> VOID
> )
> {
> - KabylakeRvp3BoardInitBeforeSiliconInit ();
> - return EFI_SUCCESS;
> + return AspireVn7Dash572GBoardInitBeforeSiliconInit ();
> }
>
> EFI_STATUS
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
> index bdf481b9805c..d4cd577e8e98 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
> @@ -1,5 +1,5 @@
> ## @file
> -# Component information file for KabylakeRvp3InitLib in PEI post memory phase.
> +# Component information file for AspireVn7Dash572GInitLib in PEI post memory phase.
> #
> # Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>
> #
> @@ -20,9 +20,10 @@
> DebugLib
> BaseMemoryLib
> MemoryAllocationLib
> - GpioExpanderLib
> PcdLib
> + GpioLib
> SiliconInitLib
> + BoardEcLib
>
> [Packages]
> MinPlatformPkg/MinPlatformPkg.dec
> @@ -33,22 +34,14 @@
> IntelSiliconPkg/IntelSiliconPkg.dec
>
> [Sources]
> - PeiKabylakeRvp3InitPostMemLib.c
> - KabylakeRvp3GpioTable.c
> - KabylakeRvp3HdaVerbTables.c
> + PeiAspireVn7Dash572GInitPostMemLib.c
> + AspireVn7Dash572GGpioTable.c
> + AspireVn7Dash572GHdaVerbTables.c
> PeiBoardInitPostMemLib.c
>
> -[FixedPcd]
> -
> [Pcd]
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel
> -
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize
>
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable
> -
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c
> index f5c695ecff86..5f89d87e71f8 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c
> @@ -1,5 +1,5 @@
> /** @file
> - Kaby Lake RVP 3 Board Initialization Pre-Memory library
> + Aspire VN7-572G Board Initialization Pre-Memory library
>
> Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -7,34 +7,30 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
>
> #include <PiPei.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> #include <Library/BoardInitLib.h>
> -#include <Library/PcdLib.h>
> #include <Library/DebugLib.h>
> -#include <PlatformBoardId.h>
>
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardDetect (
> +AspireVn7Dash572GBoardDebugInit (
> VOID
> );
>
> EFI_BOOT_MODE
> EFIAPI
> -KabylakeRvp3BoardBootModeDetect (
> +AspireVn7Dash572GBoardBootModeDetect (
> VOID
> );
>
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardDebugInit (
> +AspireVn7Dash572GBoardInitBeforeMemoryInit (
> VOID
> );
>
> EFI_STATUS
> EFIAPI
> -KabylakeRvp3BoardInitBeforeMemoryInit (
> +AspireVn7Dash572GBoardInitAfterMemoryInit (
> VOID
> );
>
> @@ -44,7 +40,7 @@ BoardDetect (
> VOID
> )
> {
> - KabylakeRvp3BoardDetect ();
> + DEBUG ((DEBUG_INFO, "%a(): Deferred until LPC programming is complete\n", __FUNCTION__));
> return EFI_SUCCESS;
> }
>
> @@ -54,8 +50,7 @@ BoardDebugInit (
> VOID
> )
> {
> - KabylakeRvp3BoardDebugInit ();
> - return EFI_SUCCESS;
> + return AspireVn7Dash572GBoardDebugInit ();
> }
>
> EFI_BOOT_MODE
> @@ -64,7 +59,7 @@ BoardBootModeDetect (
> VOID
> )
> {
> - return KabylakeRvp3BoardBootModeDetect ();
> + return AspireVn7Dash572GBoardBootModeDetect ();
> }
>
> EFI_STATUS
> @@ -73,10 +68,7 @@ BoardInitBeforeMemoryInit (
> VOID
> )
> {
> - if ((LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku () == BoardIdSkylakeRvp3)) {
> - KabylakeRvp3BoardInitBeforeMemoryInit ();
> - }
> - return EFI_SUCCESS;
> + return AspireVn7Dash572GBoardInitBeforeMemoryInit ();
> }
>
> EFI_STATUS
> @@ -85,7 +77,7 @@ BoardInitAfterMemoryInit (
> VOID
> )
> {
> - return EFI_SUCCESS;
> + return AspireVn7Dash572GBoardInitAfterMemoryInit ();
> }
>
> EFI_STATUS
> @@ -105,4 +97,3 @@ BoardInitAfterTempRamExit (
> {
> return EFI_SUCCESS;
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
> index 850fc514188b..1fba6dec91ee 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
> @@ -1,5 +1,5 @@
> ## @file
> -# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem Library
> +# Component information file for PEI AspireVn7Dash572G Board Init Pre-Mem Library
> #
> # Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.<BR>
> #
> @@ -23,7 +23,14 @@
> PcdLib
> SiliconInitLib
> EcLib
> + BoardEcLib
> + TimerLib
> + PeiServicesLib
> + PchCycleDecodingLib
> PchResetLib
> + IoLib
> + GpioLib
> + PeiLib
>
> [Packages]
> MinPlatformPkg/MinPlatformPkg.dec
> @@ -34,14 +41,15 @@
> IntelSiliconPkg/IntelSiliconPkg.dec
>
> [Sources]
> - PeiKabylakeRvp3Detect.c
> - PeiKabylakeRvp3InitPreMemLib.c
> - KabylakeRvp3HsioPtssTables.c
> - KabylakeRvp3SpdTable.c
> + PeiAspireVn7Dash572GDetect.c
> + PeiAspireVn7Dash572GInitPreMemLib.c
> + AspireVn7Dash572GGpioTable.c
> + AspireVn7Dash572GHsioPtssTables.c
> PeiBoardInitPreMemLib.c
>
> [Pcd]
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding
>
> # PCH-LP HSIO PTSS Table
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
> @@ -59,23 +67,10 @@
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
>
> - # PEG Reset By GPIO
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive
> -
> -
> # SPD Address Table
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
> @@ -83,6 +78,7 @@
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
>
> # CA Vref Configuration
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig
>
> # Root Port Clock Info
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo
> @@ -128,8 +124,3 @@
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
> -
> - # Misc
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
> -
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
> deleted file mode 100644
> index 70e93e94da11..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -/** @file
> - Kaby Lake RVP 3 Multi-Board Initialization Post-Memory library
> -
> -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <PiPei.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <Library/MultiBoardInitSupportLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -#include <PlatformBoardId.h>
> -
> -EFI_STATUS
> -EFIAPI
> -KabylakeRvp3BoardInitBeforeSiliconInit (
> - VOID
> - );
> -
> -BOARD_POST_MEM_INIT_FUNC mKabylakeRvp3BoardInitFunc = {
> - KabylakeRvp3BoardInitBeforeSiliconInit,
> - NULL, // BoardInitAfterSiliconInit
> -};
> -
> -EFI_STATUS
> -EFIAPI
> -PeiKabylakeRvp3MultiBoardInitLibConstructor (
> - VOID
> - )
> -{
> - if ((LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku () == BoardIdSkylakeRvp3)) {
> - return RegisterBoardPostMemInit (&mKabylakeRvp3BoardInitFunc);
> - }
> - return EFI_SUCCESS;
> -}
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
> deleted file mode 100644
> index f955dd4ea966..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -## @file
> -# Component information file for KabylakeRvp3InitLib in PEI post memory phase.
> -#
> -# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x00010005
> - BASE_NAME = PeiKabylakeRvp3MultiBoardInitLib
> - FILE_GUID = C7D39F17-E5BA-41D9-8DFE-FF9017499280
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = NULL
> - CONSTRUCTOR = PeiKabylakeRvp3MultiBoardInitLibConstructor
> -
> -[LibraryClasses]
> - BaseLib
> - DebugLib
> - BaseMemoryLib
> - MemoryAllocationLib
> - GpioExpanderLib
> - PcdLib
> - SiliconInitLib
> - MultiBoardInitSupportLib
> -
> -[Packages]
> - MinPlatformPkg/MinPlatformPkg.dec
> - KabylakeOpenBoardPkg/OpenBoardPkg.dec
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> - IntelSiliconPkg/IntelSiliconPkg.dec
> -
> -[Sources]
> - PeiKabylakeRvp3InitPostMemLib.c
> - KabylakeRvp3GpioTable.c
> - KabylakeRvp3HdaVerbTables.c
> - PeiMultiBoardInitPostMemLib.c
> -
> -[FixedPcd]
> -
> -[Pcd]
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel
> -
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize
> -
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable
> -
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
> deleted file mode 100644
> index 59b3177201db..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
> +++ /dev/null
> @@ -1,82 +0,0 @@
> -/** @file
> - Kaby Lake RVP 3 Multi-Board Initialization Pre-Memory library
> -
> -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <PiPei.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/BoardInitLib.h>
> -#include <Library/MultiBoardInitSupportLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/DebugLib.h>
> -
> -#include <PlatformBoardId.h>
> -
> -EFI_STATUS
> -EFIAPI
> -KabylakeRvp3BoardDetect (
> - VOID
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -KabylakeRvp3MultiBoardDetect (
> - VOID
> - );
> -
> -EFI_BOOT_MODE
> -EFIAPI
> -KabylakeRvp3BoardBootModeDetect (
> - VOID
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -KabylakeRvp3BoardDebugInit (
> - VOID
> - );
> -
> -EFI_STATUS
> -EFIAPI
> -KabylakeRvp3BoardInitBeforeMemoryInit (
> - VOID
> - );
> -
> -BOARD_DETECT_FUNC mKabylakeRvp3BoardDetectFunc = {
> - KabylakeRvp3MultiBoardDetect
> -};
> -
> -BOARD_PRE_MEM_INIT_FUNC mKabylakeRvp3BoardPreMemInitFunc = {
> - KabylakeRvp3BoardDebugInit,
> - KabylakeRvp3BoardBootModeDetect,
> - KabylakeRvp3BoardInitBeforeMemoryInit,
> - NULL, // BoardInitAfterMemoryInit
> - NULL, // BoardInitBeforeTempRamExit
> - NULL, // BoardInitAfterTempRamExit
> -};
> -
> -EFI_STATUS
> -EFIAPI
> -KabylakeRvp3MultiBoardDetect (
> - VOID
> - )
> -{
> - KabylakeRvp3BoardDetect ();
> - if ((LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku () == BoardIdSkylakeRvp3)) {
> - RegisterBoardPreMemInit (&mKabylakeRvp3BoardPreMemInitFunc);
> - }
> - return EFI_SUCCESS;
> -}
> -
> -EFI_STATUS
> -EFIAPI
> -PeiKabylakeRvp3MultiBoardInitPreMemLibConstructor (
> - VOID
> - )
> -{
> - return RegisterBoardDetect (&mKabylakeRvp3BoardDetectFunc);
> -}
> \ No newline at end of file
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
> deleted file mode 100644
> index 23fe6b6f03c5..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
> +++ /dev/null
> @@ -1,137 +0,0 @@
> -## @file
> -# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem Library
> -#
> -# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.<BR>
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x00010005
> - BASE_NAME = PeiKabylakeRvp3MultiBoardInitPreMemLib
> - FILE_GUID = EA05BD43-136F-45EE-BBBA-27D75817574F
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = NULL
> - CONSTRUCTOR = PeiKabylakeRvp3MultiBoardInitPreMemLibConstructor
> -
> -[LibraryClasses]
> - BaseLib
> - DebugLib
> - BaseMemoryLib
> - MemoryAllocationLib
> - PcdLib
> - SiliconInitLib
> - MultiBoardInitSupportLib
> - EcLib
> - PchResetLib
> -
> -[Packages]
> - MinPlatformPkg/MinPlatformPkg.dec
> - KabylakeOpenBoardPkg/OpenBoardPkg.dec
> - MdePkg/MdePkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - KabylakeSiliconPkg/SiPkg.dec
> - IntelSiliconPkg/IntelSiliconPkg.dec
> -
> -[Sources]
> - PeiKabylakeRvp3InitPreMemLib.c
> - KabylakeRvp3HsioPtssTables.c
> - KabylakeRvp3SpdTable.c
> - PeiMultiBoardInitPreMemLib.c
> - PeiKabylakeRvp3Detect.c
> -
> -[Pcd]
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
> -
> - # PCH-LP HSIO PTSS Table
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
> -
> - # PCH-H HSIO PTSS Table
> - #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1
> - #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2
> - #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
> - #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
> -
> - # SA Misc Config
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
> -
> - # PEG Reset By GPIO
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive
> -
> -
> - # SPD Address Table
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
> -
> - # CA Vref Configuration
> -
> - # Root Port Clock Info
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo
> -
> - # USB 2.0 Port AFE
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe
> -
> - # USB 2.0 Port Over Current Pin
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
> -
> - # USB 3.0 Port Over Current Pin
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
> -
> - # Misc
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
> -
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
> index f64555e3910f..ef40a7ee20de 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
> @@ -1,5 +1,5 @@
> ## @file
> -# The main build description file for the KabylakeRvp3 board.
> +# The main build description file for the Aspire VN7-572G board.
> #
> # Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
> #
> @@ -11,7 +11,7 @@
> DEFINE PLATFORM_SI_PACKAGE = KabylakeSiliconPkg
> DEFINE PLATFORM_SI_BIN_PACKAGE = KabylakeSiliconBinPkg
> DEFINE PLATFORM_BOARD_PACKAGE = KabylakeOpenBoardPkg
> - DEFINE BOARD = KabylakeRvp3
> + DEFINE BOARD = AspireVn7Dash572G
> DEFINE PROJECT = $(PLATFORM_BOARD_PACKAGE)/$(BOARD)
> DEFINE PEI_ARCH = IA32
> DEFINE DXE_ARCH = X64
> @@ -20,10 +20,18 @@
> #
> # Default value for OpenBoardPkg.fdf use
> #
> - DEFINE BIOS_SIZE_OPTION = SIZE_70
> + DEFINE BIOS_SIZE_OPTION = SIZE_60
> +
> + #
> + # Debug logging
> + #
> + DEFINE USE_PEI_SPI_LOGGING = FALSE
> + DEFINE USE_MEMORY_LOGGING = TRUE
> + DEFINE RELEASE_LOGGING = ($(USE_PEI_SPI_LOGGING) || $(USE_MEMORY_LOGGING))
> + DEFINE TESTING = TRUE
>
> PLATFORM_NAME = $(PLATFORM_PACKAGE)
> - PLATFORM_GUID = 8470676C-18E8-467F-B126-28DB1941AA5A
> + PLATFORM_GUID = AEEEF17C-36B6-4B68-949A-1E54CB33492F
> PLATFORM_VERSION = 0.1
> DSC_SPECIFICATION = 0x00010005
> OUTPUT_DIRECTORY = Build/$(PROJECT)
> @@ -79,8 +87,9 @@
> ################################################################################
> [SkuIds]
> 0x00|DEFAULT # 0|DEFAULT is reserved and always required.
> - 0x04|KabylakeRvp3
> - 0x60|KabyLakeYLpddr3Rvp3
> + # For further details on specific SKUs (which dGPU installed), see EC page of schematics
> + 0x41|RayleighSLx_dGPU # Detect the UMA board by GPIO
> + 0x42|NewgateSLx_dGPU
>
> ################################################################################
> #
> @@ -126,12 +135,15 @@
> #
> ################################################################################
>
> +# TODO: Harden and tune platform by libraries
> [LibraryClasses.common]
> #######################################
> # Edk2 Packages
> #######################################
> FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
> FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf
> + # This board will set debugging library instances; FIXME: UART2 not used
> + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
>
> #######################################
> # Silicon Initialization Package
> @@ -168,6 +180,7 @@
> # Board Package
> #######################################
> EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf
> + BoardEcLib|$(PROJECT)/Library/BoardEcLib/BoardEcLib.inf
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> @@ -181,9 +194,16 @@
> #######################################
> # Board-specific
> #######################################
> - PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookLib.inf
> + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
>
> +# NB: MinPlatform sets a NULL DebugLib and only overrides it for DEBUG builds
> +# TODO: Now that all debug logging is routed through RSC, correct the defines
> [LibraryClasses.IA32.SEC]
> + #######################################
> + # Edk2 Packages
> + #######################################
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +
> #######################################
> # Platform Package
> #######################################
> @@ -191,7 +211,24 @@
> SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf
> SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
>
> +[LibraryClasses.common.PEI_CORE]
> + #######################################
> + # Edk2 Packages
> + #######################################
> +# SPI logging requires local patch: InitializeMemoryServices() before ProcessLibraryConstructorList()
> +# In-memory logging may require too many services for early core debug output
> +!if $(RELEASE_LOGGING) == TRUE
> + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
> +!endif
> +
> [LibraryClasses.common.PEIM]
> + #######################################
> + # Edk2 Packages
> + #######################################
> +!if $(RELEASE_LOGGING) == TRUE
> + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
> +!endif
> +
> #######################################
> # Silicon Package
> #######################################
> @@ -204,7 +241,7 @@
> FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf
> MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
> -!if $(TARGET) == DEBUG
> +!if ($(TARGET) == DEBUG || $(TESTING) == TRUE)
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
> !endif
> SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
> @@ -230,7 +267,23 @@
> PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
> !endif
>
> +[LibraryClasses.common.DXE_CORE]
> + #######################################
> + # Edk2 Packages
> + #######################################
> +# In-memory logging may require too many services for early core debug output
> +!if $(USE_MEMORY_LOGGING) == TRUE
> + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
> +!endif
> +
> [LibraryClasses.common.DXE_DRIVER]
> + #######################################
> + # Edk2 Packages
> + #######################################
> +!if $(USE_MEMORY_LOGGING) == TRUE
> + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
> +!endif
> +
> #######################################
> # Silicon Initialization Package
> #######################################
> @@ -246,7 +299,7 @@
> MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLib.inf
>
> -!if $(TARGET) == DEBUG
> +!if ($(TARGET) == DEBUG || $(TESTING) == TRUE)
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf
> !endif
> #######################################
> @@ -260,13 +313,36 @@
> #######################################
> SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
>
> -[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
> +[LibraryClasses.common.DXE_RUNTIME_DRIVER]
> + #######################################
> + # Edk2 Packages
> + #######################################
> +!if $(USE_MEMORY_LOGGING) == TRUE
> + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
> +!endif
> +
> #######################################
> # Silicon Initialization Package
> #######################################
> ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
>
> -[LibraryClasses.X64.DXE_SMM_DRIVER]
> +[LibraryClasses.common.SMM_CORE]
> + #######################################
> + # Edk2 Packages
> + #######################################
> +# In-memory logging may require too many services for early core debug output
> +!if $(USE_MEMORY_LOGGING) == TRUE
> + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
> +!endif
> +
> +[LibraryClasses.common.DXE_SMM_DRIVER]
> + #######################################
> + # Edk2 Packages
> + #######################################
> +!if $(USE_MEMORY_LOGGING) == TRUE
> + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
> +!endif
> +
> #######################################
> # Silicon Initialization Package
> #######################################
> @@ -278,10 +354,13 @@
> BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
> MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointLib.inf
> -!if $(TARGET) == DEBUG
> +!if ($(TARGET) == DEBUG || $(TESTING) == TRUE)
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
> !endif
>
> +# TODO: DebugLib override for UEFI_DRIVER and UEFI_APPLICATION?
> +
> +# TODO: Add and improve feature support
> #######################################
> # PEI Components
> #######################################
> @@ -296,6 +375,21 @@
> PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> }
>
> + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf {
> + <LibraryClasses>
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +!if $(USE_PEI_SPI_LOGGING) == TRUE
> + SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf
> +!else
> +!if $(USE_MEMORY_LOGGING) == TRUE
> + SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/PeiSerialPortLibMem.inf
> +!endif
> +!endif
> + <PcdsFixedAtBuild>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|$(RELEASE_LOGGING)
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|63
> + }
> +
> !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
> #
> # In FSP API mode the policy has to be installed before FSP Wrapper updating UPD.
> @@ -328,6 +422,15 @@
> }
> !endif
>
> +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> + SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf {
> + <LibraryClasses>
> + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf
> + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
> + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
> + }
> +!endif
> +
> #######################################
> # Silicon Initialization Package
> #######################################
> @@ -400,20 +503,54 @@
> # @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308
> # is completed
> [Components.X64]
> +# Compiled .efi but not in FV:
> +# - dpDynamicCommand, TestPointDumpApp
> +# Other apps; perhaps useful:
> +# - MdeModulePkg/{DumpDynPcd,*ProfileInfo,VariableInfo}, UefiCpuPkg/Cpuid
> +# - Also, ShellPkg/*DynamicCommand
> +
> #######################################
> # Edk2 Packages
> #######################################
> + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf {
> + <LibraryClasses>
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +!if $(USE_MEMORY_LOGGING) == TRUE
> + SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/DxeSerialPortLibMem.inf
> +!endif
> + <PcdsFixedAtBuild>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|$(USE_MEMORY_LOGGING)
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1024
> + }
> + # TODO: Still requires a little more thought
> + MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf {
> + <LibraryClasses>
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +!if $(USE_MEMORY_LOGGING) == TRUE
> + SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/SmmSerialPortLibMem.inf
> +!endif
> + <PcdsFixedAtBuild>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|$(USE_MEMORY_LOGGING)
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1024
> + }
> MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
> MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
> - MdeModulePkg/Universal/BdsDxe/BdsDxe.inf{
> + MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
> + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf {
> <LibraryClasses>
> NULL|BoardModulePkg/Library/BdsPs2KbcLib/BdsPs2KbcLib.inf
> }
> - UefiCpuPkg/CpuDxe/CpuDxe.inf
> + UefiCpuPkg/CpuDxe/CpuDxe.inf {
> + <LibraryClasses>
> +!if $(USE_MEMORY_LOGGING) == TRUE
> +# TODO/TEST
> +# SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/DxeSerialPortLibMem.inf
> +!endif
> + }
>
> !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
> #
> @@ -423,22 +560,23 @@
> !endif
>
> ShellPkg/Application/Shell/Shell.inf {
> - <PcdsFixedAtBuild>
> - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> - <LibraryClasses>
> - NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> - NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> - NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> - NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
> - NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> - NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
> - NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> - NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
> - ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> - HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> - BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> - ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> - ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + <PcdsFixedAtBuild>
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> + <LibraryClasses>
> + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> }
>
> !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> @@ -449,6 +587,20 @@
> !if $(TARGET) == DEBUG
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> !endif
> +!if $(USE_MEMORY_LOGGING) == TRUE
> +# TODO/TEST
> +# SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/SmmSerialPortLibMem.inf
> +!endif
> + }
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {
> + <LibraryClasses>
> + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.inf
> + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf
> + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
> + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
> }
> !endif
>
> @@ -516,6 +668,7 @@
> NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
> !endif
> }
> + $(PROJECT)/Acpi/BoardAcpiTables.inf
> !endif
> BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
> BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf
> index 6cdf4e2f9f1f..8e69676e70d9 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf
> @@ -23,7 +23,7 @@
> # existing system flash.
> #
> ################################################################################
> -[FD.KabylakeRvp3]
> +[FD.AspireVn7Dash572G]
> #
> # FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be
> # assigned with PCD values. Instead, it uses the definitions for its variety, which
> @@ -131,6 +131,10 @@ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTo
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> #NV_FTW_SPARE
>
> +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize
> +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageBase|gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize
> +#DEBUG_MESSAGE_AREA
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
> FV = FvAdvanced
> @@ -276,7 +280,7 @@ INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.in
>
> !if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
> FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 {
> - SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin
> + SECTION RAW = AspireVn7Dash572G/Vbt.bin
I think you could do:
SECTION RAW = $(PROJECT)/Vbt.bin
And have this be a little more generic.
> SECTION UI = "Vbt"
> }
> FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
> @@ -330,6 +334,13 @@ READ_LOCK_CAP = TRUE
> READ_LOCK_STATUS = TRUE
> FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
>
> +# NOTE: UefiDriverEntryPoint imports a dependency on the architectural protocols.
> +APRIORI DXE {
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> +}
> +
> !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
>
> INF UefiCpuPkg/CpuDxe/CpuDxe.inf
> @@ -341,6 +352,7 @@ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
> INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
> INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
> +INF MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
> INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
>
> INF ShellPkg/Application/Shell/Shell.inf
> @@ -401,6 +413,12 @@ READ_LOCK_CAP = TRUE
> READ_LOCK_STATUS = TRUE
> FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
>
> +# NOTE: UefiDriverEntryPoint imports a dependency on the architectural protocols.
> +APRIORI DXE {
> + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
> + INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
> +}
> +
> !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
>
> INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
> @@ -414,6 +432,7 @@ INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
> INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
>
> INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
> +INF RuleOverride = ACPITABLE $(PROJECT)/Acpi/BoardAcpiTables.inf
>
> INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
>
> @@ -712,4 +731,3 @@ FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
> ################################################################################
>
> !include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOption.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOption.dsc
> index 8e885cc6a4b8..3cedcb3e4be9 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOption.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOption.dsc
> @@ -57,7 +57,7 @@
>
> DEFINE EMB_BUILD_OPTIONS =
>
> - DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS = -DMEM_DOWN_FLAG=1
> + DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS =
>
> DEFINE DSC_KBCEMUL_BUILD_OPTIONS =
>
> @@ -86,6 +86,7 @@ DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(
> DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS)
> DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYPEC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION)
>
> +# FIXME: $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) is passed multiple times
> [BuildOptions.Common.EDKII]
>
> #
> @@ -144,8 +145,9 @@ MSFT: *_*_X64_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
>
> +# FIXME: Protection broken, but works on UefiPayload, and not related to
> +# FspWrapperNotifyDxe. Cannot be related to SMM?
> # Force PE/COFF sections to be aligned at 4KB boundaries to support NX protection
> [BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE, BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPLICATION]
> #MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> #GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
> index 725596cbf71e..a91559bd26b6 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
> @@ -1,5 +1,5 @@
> ## @file
> -# PCD configuration build description file for the KabylakeRvp3 board.
> +# PCD configuration build description file for the Aspire VN7-572G board.
> #
> # Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
> #
> @@ -13,6 +13,10 @@
> #
> ################################################################################
>
> +# TODO: Harden and tune platform by PCDs
> +# TODO: Consider removing PCDs declared by build report to be unused (but confirm first)
> +# - Also, consider more "fixed" and more "dynamic"/"patchable"
> +
> [PcdsFixedAtBuild.common]
> ######################################
> # Key Boot Stage and FSP configuration
> @@ -26,7 +30,7 @@
> # Stage 5 - boot to OS with security boot enabled
> # Stage 6 - boot with advanced features enabled
> #
> - gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
> + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6
>
> #
> # 0: FSP Wrapper is running in Dispatch mode.
> @@ -68,27 +72,27 @@
>
> gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
> gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
> - gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
> + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
> gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
> - gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
> + gSiPkgTokenSpaceGuid.PcdTsegSize|0x0800000 # Now hooked up
>
> !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
> #
> # FSP API mode does not share stack with the boot loader,
> # so FSP needs more temporary memory for FSP heap + stack size.
> #
> - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
> + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x28000 # FIXME: Confirm matches UPD default
> #
> # FSP API mode does not need to enlarge the boot loader stack size
> # since the stacks are separate.
> #
> - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
> + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 # Not hooked up, not used (functionally equivalent and equal to UefiCpuPkg)
> !else
> #
> # In FSP Dispatch mode boot loader stack size must be large
> # enough for executing both boot loader and FSP.
> #
> - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000
> + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000 # Not hooked up, not used (functionally equivalent but NOT equal to UefiCpuPkg)
> !endif
>
> !if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
> @@ -107,13 +111,42 @@
> # Edk2 Configuration
> ######################################
> gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE # Deprecated, only use GOP
> + gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|FALSE # TODO/TEST
> + gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
> - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> +
> +# TODO: Prune this list to relevant features only
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
> + # FIXME: SMM path also PatchAndLoadAcpiTable()
> + gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable |FALSE
> + # PcdIpmiFeatureEnable will not be enabled (no BMC)
> + # TODO: Can be build-time (user) choice
> + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |FALSE
> + # TODO: Continue developing support. Broken at present.
> + # - PeiSmmAccessLib in IntelSiliconPkg seems like a stub
> + # - May require a PeiSmmControlLib to SMM communicate
> + gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable |FALSE
> + # TODO: Definitions (now added SmbiosDxe)
> + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable |TRUE
> + # Requires actual hook-up
> + gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugFeatureEnable |FALSE
> + # FIXME: (Similar) DXE module is duplicate?
> + gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable |FALSE
> + # FIXME: Must BootLogoEnableLogo() to turn platform logo into boot logo
> + # - BGRT must be BMP, but this duplicates FSP logo. Can GetSectionFromAnyFv()?
> + gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable |FALSE
> + gLogoFeaturePkgTokenSpaceGuid.PcdJpgEnable |FALSE
> +!endif
>
> ######################################
> # Silicon Configuration
> ######################################
> + # TODO: Set FSP policy by switches? Otherwise, only FSP binary builds?
> # Build switches
> gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
>
> @@ -151,7 +184,7 @@
> gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
> gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
> gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE
> - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
> + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|$(RELEASE_LOGGING)
> gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
PcdSiCsmEnable is just tells the SiPkg that the platform code contains a CSM. It is one of many... many things you would need to do for proper CSM support in KabylakeOpenBoardPkg and is way beyond the scope of this GSoC project :)
> gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
> gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
> @@ -165,10 +198,10 @@
> gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
> gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
> gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
> - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
> + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE # FIXME: Define by PERFORMANCE_BUILD?
> gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
> gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
> - gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE
> + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE # FIXME: Define in build-system?
>
> !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
> gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
> @@ -193,6 +226,7 @@
> gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
> !endif
>
> +# TODO: Is TESTING setting, is not test point
> !if $(TARGET) == DEBUG
> gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
> !else
> @@ -202,50 +236,72 @@
> ######################################
> # Board Configuration
> ######################################
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE
> - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|FALSE
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE # TODO: Enable if supporting Newgate
>
> [PcdsFixedAtBuild.common]
> ######################################
> # Edk2 Configuration
> ######################################
> !if $(TARGET) == RELEASE
> +!if $(RELEASE_LOGGING) == TRUE
> +!if $(TESTING) == TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x07
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x03
> +!endif # $(TESTING)
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +!else
> gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
> gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
> +!endif # $(RELEASE_LOGGING)
> !else
> - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> + # FIXME: More than just compiler optimisation is hooked to DEBUG builds.
> + # Make asserts non-fatal for limited debugging system
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0F
> gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> -!endif
> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
> +!endif # $(TARGET)
> !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
> gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
> !endif
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
>
> gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
> gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
> gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
> + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE # TODO/TEST
> gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
> gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
> -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
> - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x8000
> +!if $(TESTING) == TRUE
> + # Test with non-stop mode, so not disabling for loader.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask|0x43
> +!else
> + # FIXME: Can be broken for CSM. At this time, be permissive for loader.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask|0x83
> !endif
> - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
> gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
> !if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
> gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
> !endif
> gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
> -!if $(TARGET) == DEBUG
> - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
> -!endif
> gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
> !if $(TARGET) == RELEASE
> gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> !else
> gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
> !endif
>
> + # UPDs are updated at runtime, don't bother measuring
> + # BUGBUG: FSP-S measurement returns DEVICE_ERROR from PtpCrbTpmCommand() - Step 0.
> + # - Similarly, Tcg2Dxe.c:Tpm2GetCapabilityManufactureID() - first command - fails?
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig|0x00000006
> +
> gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
> gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40
> gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
> @@ -267,7 +323,7 @@
> #
> ## Specifies max supported number of Logical Processors.
> # @Prompt Configure max supported number of Logical Processors
> - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|8
>
> ## Specifies the size of the microcode Region.
> # @Prompt Microcode Region size.
> @@ -287,14 +343,14 @@
> ######################################
>
> # Refer to HstiFeatureBit.h for bit definitions
> - gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
> + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 # FIXME: Boot Guard and BIOS Guard not present, measured boot enforcement checking code not present
> gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>
> ######################################
> # Platform Configuration
> ######################################
> gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
> - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
> + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|4
> gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
> gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
>
> @@ -309,13 +365,26 @@
> #
> gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
>
> + ## This PCD is to control which device is the potential trusted console input device.<BR><BR>
> + # For example:<BR>
> + # PS/2 keyboard: PciRoot(0x0)/Pci(0x1F,0x0)/Acpi(PNP0303,0x0)<BR>
> + # //Header HID UID<BR>
> + # {0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00,<BR>
> + # //Header Func Dev<BR>
> + # 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F,<BR>
> + # //Header HID UID<BR>
> + # 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00,<BR>
> + # //Header<BR>
> + # 0x7F, 0xFF, 0x04, 0x00}<BR>
> + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFF, 0x04, 0x00}
> +
> !if $(TARGET) == RELEASE
> - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
> + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x800
> !else
> - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B
> + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B # TODO
> !endif
> -
> - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
> + # TODO: Consider using reserved space instead for debug log
> + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x200
> !if $(TARGET) == RELEASE
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
> !else
> @@ -335,18 +404,17 @@
> !endif
>
> !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
> - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
> + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x3F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
> !endif
>
> !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
> - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
> + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x3F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
> !endif
>
> !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
> - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
> + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
> !endif
>
> -
> ######################################
> # Board Configuration
> ######################################
> @@ -357,7 +425,6 @@
> ######################################
> # Edk2 Configuration
> ######################################
> - gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
> gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
> gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
>
> @@ -378,8 +445,7 @@
> ######################################
> # Edk2 Configuration
> ######################################
> - gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
> - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 # 0x804800C7/0x806A15CF give useful information, but is very noisy
>
> ######################################
> # Silicon Configuration
> @@ -388,12 +454,21 @@
> gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
> !endif
>
> + ######################################
> + # Platform Configuration
> + ######################################
> +!if $(TARGET) == DEBUG
> + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable|1
> +!else
> + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable|0
> +!endif
> +
> [PcdsDynamicDefault]
> ######################################
> # Edk2 Configuration
> ######################################
> - gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
> - gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE # Why dynamic?
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE # Why dynamic?
> gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
> gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
> @@ -421,8 +496,11 @@
> ######################################
> # Board Configuration
> ######################################
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints|1
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle|1
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative|1
>
> - # Thunderbolt Configuration
> + # Thunderbolt Configuration (FIXME: Remove if not supporting Newgate)
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting|0
> @@ -462,3 +540,7 @@
> !else
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
> !endif
> +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> + gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x8|3|NV,BS
> +!endif
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c
> index 7744af6b3cfc..eff8ea0c1345 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c
> @@ -6,8 +6,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
>
> -#include "DxeGopPolicyInit.h"
> +#include <Library/EcLib.h>
> #include <Protocol/GopPolicy.h>
> +#include "DxeGopPolicyInit.h"
>
> GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy;
> GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize = 0;
> @@ -30,7 +31,18 @@ GetPlatformLidStatus (
> OUT LID_STATUS *CurrentLidStatus
> )
> {
> - return EFI_UNSUPPORTED;
> + EFI_STATUS Status;
> + UINT8 PowerRegister;
> +
> + Status = EcRead(0x70, &PowerRegister);
> + if (EFI_ERROR(Status)) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + // "ELID"
> + *CurrentLidStatus = (PowerRegister & BIT1) ? LidOpen : LidClosed;
> +
> + return EFI_SUCCESS;
> }
> /**
>
> @@ -45,7 +57,8 @@ GetPlatformDockStatus (
> OUT DOCK_STATUS CurrentDockStatus
> )
> {
> - return EFI_UNSUPPORTED;
> + // TODO: UnDocked or no dock
> + return EFI_UNSUPPORTED;
> }
>
>
> @@ -154,7 +167,7 @@ GopPolicyInitDxe (
> //
> // Initialize the EFI Driver Library
> //
> - SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);
> + ZeroMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL));
>
> mGOPPolicy.Revision = GOP_POLICY_PROTOCOL_REVISION_03;
> mGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus;
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c
> index fcd248fdf5cf..2070370e29b0 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c
> @@ -29,21 +29,19 @@ UpdateRmrrUsbAddress (
> Status = GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig);
> ASSERT_EFI_ERROR (Status);
>
> - if (1) {
> - mSize = EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH);
> - mAddress = SIZE_4GB;
> + mSize = EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH);
> + mAddress = SIZE_4GB;
>
> - Status = (gBS->AllocatePages) (
> - AllocateMaxAddress,
> - EfiReservedMemoryType,
> - mSize,
> - &mAddress
> - );
> - ASSERT_EFI_ERROR (Status);
> + Status = (gBS->AllocatePages) (
> + AllocateMaxAddress,
> + EfiReservedMemoryType,
> + mSize,
> + &mAddress
> + );
> + ASSERT_EFI_ERROR (Status);
>
> - MiscDxeConfig->RmrrUsbBaseAddress[0] = mAddress;
> - MiscDxeConfig->RmrrUsbBaseAddress[1] = mAddress + SA_VTD_RMRR_USB_LENGTH - 1;
> - }
> + MiscDxeConfig->RmrrUsbBaseAddress[0] = mAddress;
> + MiscDxeConfig->RmrrUsbBaseAddress[1] = mAddress + SA_VTD_RMRR_USB_LENGTH - 1;
> }
>
> /**
> @@ -63,4 +61,3 @@ UpdateDxeSaPolicy (
> UpdateRmrrUsbAddress (SaPolicy);
> return EFI_SUCCESS;
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c
> index d4dbb414a26f..22bad0190934 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c
> @@ -5,9 +5,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
>
> +#include <Library/ConfigBlockLib.h>
> #include <Library/SiliconPolicyUpdateLib.h>
> #include <Library/PcdLib.h>
> #include <Library/DebugLib.h>
> +#include <Protocol/GopPolicy.h>
> +#include <Protocol/SaPolicy.h>
>
> #include "DxeSaPolicyInit.h"
> #include "DxeGopPolicyInit.h"
> @@ -33,21 +36,39 @@ SiliconPolicyUpdateLate (
> IN VOID *Policy
> )
> {
> - SA_POLICY_PROTOCOL *SaPolicy;
> + SA_POLICY_PROTOCOL *SaPolicy = Policy;
> EFI_STATUS Status;
> + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
> + GOP_POLICY_PROTOCOL *GopPolicy;
> + EFI_PHYSICAL_ADDRESS VbtAddress;
> + UINT32 VbtSize;
> +
> + Status = GetConfigBlock ((VOID *)SaPolicy, &gGraphicsDxeConfigGuid, (VOID *) &GraphicsDxeConfig);
> + ASSERT_EFI_ERROR (Status);
>
> - SaPolicy = Policy;
> UpdateDxeSaPolicy (SaPolicy);
>
> - if (PcdGetBool(PcdIntelGopEnable)) {
> + if (PcdGetBool (PcdIntelGopEnable)) {
> //
> // GOP Dxe Policy Initialization
> //
> - Status = GopPolicyInitDxe(gImageHandle);
> - DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));
> - ASSERT_EFI_ERROR(Status);
> + Status = GopPolicyInitDxe (gImageHandle);
> + DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + // Copy VBT address to Policy
> + Status = gBS->LocateProtocol (&gGopPolicyProtocolGuid, NULL, (VOID **) &GopPolicy);
> + if (!EFI_ERROR(Status)) {
> + Status = GopPolicy->GetVbtData (&VbtAddress, &VbtSize);
> + if (!EFI_ERROR(Status) && GraphicsDxeConfig != NULL) {
> + GraphicsDxeConfig->VbtAddress = VbtAddress;
> + GraphicsDxeConfig->Size = VbtSize;
> + DEBUG ((DEBUG_INFO, "Located VBT at 0x%x with size 0x%x\n", VbtAddress, VbtSize));
> + } else {
> + DEBUG ((DEBUG_ERROR, "No VBT found, or Policy == NULL; Status - %r\n", Status));
> + }
> }
>
> return Policy;
> }
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
> index 2abf1aef805a..63ac194cd0d5 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
> @@ -20,6 +20,7 @@
> PcdLib
> DebugLib
> ConfigBlockLib
> + EcLib
>
> [Packages]
> MdePkg/MdePkg.dec
> @@ -44,8 +45,8 @@
> gGopPolicyProtocolGuid ## PRODUCES
>
> [Guids]
> + gGraphicsDxeConfigGuid
> gMiscDxeConfigGuid
>
> [Depex]
> gEfiVariableArchProtocolGuid
> -
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c
> new file mode 100644
> index 000000000000..eb28c0d70949
> --- /dev/null
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c
> @@ -0,0 +1,332 @@
> +/** @file
> + This file configures Aspire VN7-572G board-specific policies.
> +
> +Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <ConfigBlock.h>
> +#include <Library/ConfigBlockLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <CpuPolicyCommon.h>
> +#include <PchPolicyCommon.h>
> +#include <PchPreMemPolicyCommon.h>
> +#include <SaPolicyCommon.h>
> +
> +/* TODO: Some disabled devices are likely fuse-disabled. Remove such entries */
> +/* TODO/NB: The configs commented here but not in FspWrapper must be found! */
> +/*
> + IgdDvmt50PreAlloc = ?
> +*/
> +
> +#define SA_VR 0
> +#define IA_VR 1
> +#define GT_UNSLICED_VR 2
> +#define GT_SLICED_VR 3
> +
> +/**
> + Performs the remainder of board-specific FSP Policy initialization.
> +
> + @param[in] Policy Policy PPI pointer.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspBoardPolicyUpdatePreMem (
> + IN VOID *Policy
> + )
> +{
> + EFI_STATUS Status;
> + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
> + MEMORY_CONFIGURATION *MemConfig;
> + PCH_HPET_PREMEM_CONFIG *HpetPreMemConfig;
> +
> + // Retrieve the config blocks we depend on
> + Status = GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (MiscPeiPreMemConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gMemoryConfigGuid, (VOID *) &MemConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (MemConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gHpetPreMemConfigGuid, (VOID *) &HpetPreMemConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (HpetPreMemConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> +
> + /* System Agent config */
> + MiscPeiPreMemConfig->UserBd = PcdGet8(PcdSaMiscUserBd);
> + MemConfig->DqPinsInterleaved = (UINT8)PcdGetBool(PcdMrcDqPinsInterleaved);
> + MemConfig->CaVrefConfig = PcdGet8(PcdMrcCaVrefConfig);
> + MemConfig->SaGv = 3; // Enabled
> +
> + // TODO: Why should this be here?
> + // FSP should program it's default BDF value (but where is bus 0xF0?)
> + HpetPreMemConfig->BdfValid = 1;
> +
> + /* iGFX config */
> +//FIXME FspmUpd->FspmConfig.PrimaryDisplay = 4; // Switchable Graphics
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Performs the remainder of board-specific FSP Policy initialization.
> +
> + @param[in] Policy Policy PPI pointer.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspBoardPolicyUpdate (
> + IN VOID *Policy
> + )
> +{
> + EFI_STATUS Status;
> + PCH_LOCK_DOWN_CONFIG *LockDownConfig;
> + PCH_GENERAL_CONFIG *PchGeneralConfig;
> + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig;
> + CPU_POWER_MGMT_VR_CONFIG *CpuPowerMgmtVrConfig;
> + PCH_USB_CONFIG *UsbConfig;
> + PCH_SATA_CONFIG *SataConfig;
> + PCH_PCIE_CONFIG *PchPcieConfig;
> + PCH_PM_CONFIG *PmConfig;
> + PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
> + PCH_HDAUDIO_CONFIG *HdAudioConfig;
> + PCH_IOAPIC_CONFIG *IoApicConfig;
> +
> + // Retrieve the config blocks we depend on (all are expected to be installed)
> + Status = GetConfigBlock (Policy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (LockDownConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (PchGeneralConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gCpuPowerMgmtBasicConfigGuid, (VOID *) &CpuPowerMgmtBasicConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (CpuPowerMgmtBasicConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gCpuPowerMgmtVrConfigGuid, (VOID *) &CpuPowerMgmtVrConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (CpuPowerMgmtVrConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gUsbConfigGuid, (VOID *) &UsbConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (UsbConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gSataConfigGuid, (VOID *) &SataConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (SataConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gPcieRpConfigGuid, (VOID *) &PchPcieConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (PchPcieConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gPmConfigGuid, (VOID *) &PmConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (PmConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gSerialIrqConfigGuid, (VOID *) &SerialIrqConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (SerialIrqConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (HdAudioConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + Status = GetConfigBlock (Policy, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
> + ASSERT_EFI_ERROR(Status);
> + if (IoApicConfig == NULL) {
> + return EFI_NOT_FOUND;
> + }
> +
> + // FIXME/NB: This is insecure and not production-ready!
> + // TODO: Configure SPI lockdown by variable on FrontPage?
> + LockDownConfig->BiosLock = 0;
> + LockDownConfig->SpiEiss = 0;
> +
> + // TODO: Why should this be here?
> + // FSP should program it's default BDF value (but where is bus 0xF0?)
> + IoApicConfig->BdfValid = 1;
> +
> + // Note: SerialIoDevMode default is satisfactory, but not entirely accurate.
> + // Board has no GPIO expander on I2C4 (despite SetupUtility claim
> + // that it does - this appears to be static text?) and is UART0 merely supporting
> + // the UART2 devfn?
> +
> + // Acer IDs (TODO: "Newgate" IDs)
> +//FIXME FspsUpd->FspsConfig.DefaultSvid = 0x1025;
> +//FIXME FspsUpd->FspsConfig.DefaultSid = 0x1037;
> + PchGeneralConfig->SubSystemVendorId = 0x1025;
> + PchGeneralConfig->SubSystemId = 0x1037;
> +
> + /* System Agent config */
> + // Set the Thermal Control Circuit (TCC) activation value to 97C
> + // even though FSP integration guide says to set it to 100C for SKL-U
> + // (offset at 0), because when the TCC activates at 100C, the CPU
> + // will have already shut itself down from overheating protection.
> + CpuPowerMgmtBasicConfig->TccActivationOffset = 3;
> +
> + // VR Slew rate setting for improving audible noise
> + CpuPowerMgmtVrConfig->AcousticNoiseMitigation = 1;
> + CpuPowerMgmtVrConfig->SlowSlewRateForIa = 3; // Fast/16
> + CpuPowerMgmtVrConfig->SlowSlewRateForGt = 3; // Fast/16
> + CpuPowerMgmtVrConfig->SlowSlewRateForSa = 0; // Fast/2
> + CpuPowerMgmtVrConfig->FastPkgCRampDisableIa = 0;
> + CpuPowerMgmtVrConfig->FastPkgCRampDisableGt = 0;
> + CpuPowerMgmtVrConfig->FastPkgCRampDisableSa = 0;
> +
> + // VR domain configuration (copied from board port, before VR config moved
> + // to SoC. Should match SKL-U (GT2, 15W) in the SKL-U datasheet, vol. 1
> + CpuPowerMgmtVrConfig->AcLoadline[SA_VR] = 1030; // 10.3mOhm (in 1/100 increments)
> + CpuPowerMgmtVrConfig->DcLoadline[SA_VR] = 1030; // 10.3mOhm (in 1/100 increments)
> + CpuPowerMgmtVrConfig->Psi1Threshold[SA_VR] = 80; // 20A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->Psi2Threshold[SA_VR] = 16; // 4A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->Psi3Threshold[SA_VR] = 4; // 1A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->IccMax[SA_VR] = 18; // 4.5A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->VrVoltageLimit[SA_VR] = 1520; // 1520mV
> +
> + CpuPowerMgmtVrConfig->AcLoadline[IA_VR] = 240; // 2.4mOhm (in 1/100 increments)
> + CpuPowerMgmtVrConfig->DcLoadline[IA_VR] = 240; // 2.4mOhm (in 1/100 increments)
> + CpuPowerMgmtVrConfig->Psi1Threshold[IA_VR] = 80; // 20A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->Psi2Threshold[IA_VR] = 20; // 5A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->Psi3Threshold[IA_VR] = 4; // 1A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->IccMax[IA_VR] = 116; // 29A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->VrVoltageLimit[IA_VR] = 1520; // 1520mV
> +
> + CpuPowerMgmtVrConfig->AcLoadline[GT_UNSLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
> + CpuPowerMgmtVrConfig->DcLoadline[GT_UNSLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
> + CpuPowerMgmtVrConfig->Psi1Threshold[GT_UNSLICED_VR] = 80; // 20A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->Psi2Threshold[GT_UNSLICED_VR] = 20; // 5A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->Psi3Threshold[GT_UNSLICED_VR] = 4; // 1A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->IccMax[GT_UNSLICED_VR] = 124; // 31A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->VrVoltageLimit[GT_UNSLICED_VR] = 1520; // 1520mV
> +
> + CpuPowerMgmtVrConfig->AcLoadline[GT_SLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
> + CpuPowerMgmtVrConfig->DcLoadline[GT_SLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
> + CpuPowerMgmtVrConfig->Psi1Threshold[GT_SLICED_VR] = 80; // 20A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->Psi2Threshold[GT_SLICED_VR] = 20; // 5A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->Psi3Threshold[GT_SLICED_VR] = 4; // 1A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->IccMax[GT_SLICED_VR] = 124; // 31A (in 1/4 increments)
> + CpuPowerMgmtVrConfig->VrVoltageLimit[GT_SLICED_VR] = 1520; // 1520mV
> +
> + // PL1, PL2 override 35W, PL4 override 43W (in 125 mW increments)
> + CpuPowerMgmtBasicConfig->PowerLimit1 = 280;
> + CpuPowerMgmtBasicConfig->PowerLimit2Power = 280;
> + CpuPowerMgmtBasicConfig->PowerLimit4 = 344;
> +
> + // ISL95857 VR
> + // Send VR specific command for PS4 exit issue
> + CpuPowerMgmtVrConfig->SendVrMbxCmd1 = 2;
> + // Send VR mailbox command for IA/GT/SA rails
> +//FIXME FspsUpd->FspsConfig.IslVrCmd = 2;
> +
> + /* Skycam config */
> +// FspsUpd->FspsConfig.SaImguEnable = 0;
> +// FspsUpd->FspsConfig.PchCio2Enable = 0;
> +
> + /* Sensor hub config */
> +// FspsUpd->FspsConfig.PchIshEnable = 0;
> +
> + /* xHCI config */
> +// FspsUpd->FspsConfig.SsicPortEnable = 0;
> + // Configure USB2 ports in two blocks
> + for (int i = 0; i < 3; i++) {
> + UsbConfig->PortUsb20[i].Afe.Txiset = 0x2; // 16.9mV
> + UsbConfig->PortUsb20[i].Afe.Predeemp = 1; // De-emphasis on
> + UsbConfig->PortUsb20[i].Afe.Petxiset = 0x3;// 28.15mV
> + UsbConfig->PortUsb20[i].Afe.Pehalfbit = 1; // Half-bit
> + }
> + for (int i = 3; i < 9; i++) {
> + UsbConfig->PortUsb20[i].Afe.Txiset = 0; // 0mV
> + UsbConfig->PortUsb20[i].Afe.Predeemp = 0x2;// Pre-emphasis and de-emphasis on
> + UsbConfig->PortUsb20[i].Afe.Petxiset = 0x7;// 56.3mV
> + UsbConfig->PortUsb20[i].Afe.Pehalfbit = 1; // Half-bit
> + }
> + // Configure all USB3 ports
> + for (int i = 0; i < 4; i++) {
> + UsbConfig->PortUsb30[i].HsioTxDeEmphEnable = 1;
> + UsbConfig->PortUsb30[i].HsioTxDeEmph = 0x29; // Default (approximately -3.5dB de-emphasis)
> + }
> + // Disable all OC pins
> + for (int i = 0; i < 9; i++) {
> + UsbConfig->PortUsb20[i].OverCurrentPin = PchUsbOverCurrentPinSkip;
> + }
> + for (int i = 0; i < 4; i++) {
> + UsbConfig->PortUsb30[i].OverCurrentPin = PchUsbOverCurrentPinSkip;
> + }
> +
> + /* xDCI config */
> +// FspsUpd->FspsConfig.XdciEnable = 0;
> +
> + /* SATA config */
> + // This is a hard silicon requirement, discovered several times by coreboot boards
> + SataConfig->PwrOptEnable = 1;
> +
> + /* PCIe config */
> + // Port 1 (dGPU; x4)
> + PchPcieConfig->RootPort[0].AdvancedErrorReporting = 1;
> + PchPcieConfig->RootPort[0].LtrEnable = 1;
> + PchPcieConfig->RootPort[0].ClkReqSupported = 1;
> + PchPcieConfig->RootPort[0].ClkReqNumber = 0x0;
> + PchPcieConfig->RootPort[0].MaxPayload = PchPcieMaxPayload256;
> + // Port 7 (NGFF; x2)
> + PchPcieConfig->RootPort[6].AdvancedErrorReporting = 1;
> + PchPcieConfig->RootPort[6].LtrEnable = 1;
> + PchPcieConfig->RootPort[6].ClkReqSupported = 1;
> + PchPcieConfig->RootPort[6].ClkReqNumber = 0x3;
> + PchPcieConfig->RootPort[6].MaxPayload = PchPcieMaxPayload256;
> + // Port 9 (LAN)
> + PchPcieConfig->RootPort[8].AdvancedErrorReporting = 1;
> + PchPcieConfig->RootPort[8].LtrEnable = 1;
> + PchPcieConfig->RootPort[8].ClkReqSupported = 1;
> + PchPcieConfig->RootPort[8].ClkReqNumber = 0x1;
> + PchPcieConfig->RootPort[8].MaxPayload = PchPcieMaxPayload256;
> + // Port 10 (WLAN)
> + PchPcieConfig->RootPort[9].AdvancedErrorReporting = 1;
> + PchPcieConfig->RootPort[9].LtrEnable = 1;
> + PchPcieConfig->RootPort[9].ClkReqSupported = 1;
> + PchPcieConfig->RootPort[9].ClkReqNumber = 0x2;
> + PchPcieConfig->RootPort[9].MaxPayload = PchPcieMaxPayload256;
> + // ASPM L0s is broken/unsupported on Qualcomm Atheros QCA6174 (AER: corrected errors)
> + PchPcieConfig->RootPort[9].Aspm = PchPcieAspmL1;
> +
> + /* LPC config */
> + // EC/KBC requires continuous mode
> + PmConfig->LpcClockRun = 1;
> + SerialIrqConfig->SirqMode = PchContinuousMode;
> +
> + /* HDA config */
> + HdAudioConfig->DspEndpointDmic = PchHdaDmic1chArray;
> +
> + /* SCS config */
> + // Although platform NVS area shows this enabled, the SD card reader is connected over USB, not SCS
> +// FspsUpd->FspsConfig.ScsEmmcEnabled = 0;
> +// FspsUpd->FspsConfig.ScsSdCardEnabled = 0;
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
> index 2dce9be63c58..c9dfb17e0a4e 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
> @@ -28,6 +28,39 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <Library/MmPciLib.h>
> #include <Library/IoLib.h>
>
> +//
> +// Function prototypes
> +//
> +/**
> + Performs the remainder of board-specific FSP Policy initialization.
> +
> + @param[in] Policy - Policy PPI pointer.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspBoardPolicyUpdatePreMem (
> + IN VOID *Policy
> + );
> +
> +/**
> + Performs the remainder of board-specific FSP Policy initialization.
> +
> + @param[in] Policy - Policy PPI pointer.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspBoardPolicyUpdate (
> + IN VOID *Policy
> + );
> +
> /**
> Get the next microcode patch pointer.
>
> @@ -498,6 +531,9 @@ SiliconPolicyUpdatePreMem (
> // Update PCD policy
> //
> InstallPlatformHsioPtssTable (Policy);
> +
> + // Board-specific policy overrides
> + PeiFspBoardPolicyUpdatePreMem (Policy);
> }
>
> return Policy;
> @@ -580,6 +616,11 @@ SiliconPolicyUpdatePostMem (
> if (CpuConfig != NULL) {
> CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch ();
> }
> +
> + if (Policy != NULL) {
> + // Board-specific policy overrides
> + PeiFspBoardPolicyUpdate (Policy);
> + }
> return Policy;
> }
>
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
> index 5c2da68bf935..ad85326bf9fb 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
> @@ -41,8 +41,10 @@
>
> [Sources]
> PeiSiliconPolicyUpdateLib.c
> + PeiBoardPolicyUpdate.c
>
> [Guids]
> + gMemoryConfigGuid
> gMemoryConfigNoCrcGuid
> gTianoLogoGuid ## CONSUMES
> gGraphicsPeiConfigGuid ## CONSUMES
> @@ -51,6 +53,16 @@
> gHsioSataPreMemConfigGuid ## CONSUMES
> gSaMiscPeiPreMemConfigGuid ## CONSUMES
> gFspNonVolatileStorageHobGuid ## CONSUMES
> + gLockDownConfigGuid
> + gPchGeneralConfigGuid
> + gCpuPowerMgmtBasicConfigGuid
> + gCpuPowerMgmtVrConfigGuid
> + gUsbConfigGuid
> + gSataConfigGuid
> + gPcieRpConfigGuid
> + gPmConfigGuid
> + gSerialIrqConfigGuid
> + gHdAudioConfigGuid
>
> [Pcd]
> gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize
> @@ -60,6 +72,9 @@
> gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress
> gSiPkgTokenSpaceGuid.PcdTsegSize
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSUMES
> + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py
> deleted file mode 100644
> index 41668120f109..000000000000
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py
> +++ /dev/null
> @@ -1,68 +0,0 @@
> -# @ build_board.py
> -# This is a sample code provides Optional dynamic imports
> -# of build functions to the BuildBios.py script
> -#
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -
> -"""
> -This module serves as a sample implementation of the build extension
> -scripts
> -"""
> -
> -
> -def pre_build_ex(config, functions):
> - """Additional Pre BIOS build function
> -
> - :param config: The environment variables to be used in the build process
> - :type config: Dictionary
> - :param functions: A dictionary of function pointers
> - :type functions: Dictionary
> - :returns: nothing
> - """
> - print("pre_build_ex")
> - return None
> -
> -
> -def build_ex(config, functions):
> - """Additional BIOS build function
> -
> - :param config: The environment variables to be used in the build process
> - :type config: Dictionary
> - :param functions: A dictionary of function pointers
> - :type functions: Dictionary
> - :returns: config dictionary
> - :rtype: Dictionary
> - """
> - print("build_ex")
> - return None
> -
> -
> -def post_build_ex(config, functions):
> - """Additional Post BIOS build function
> -
> - :param config: The environment variables to be used in the post
> - build process
> - :type config: Dictionary
> - :param functions: A dictionary of function pointers
> - :type functions: Dictionary
> - :returns: config dictionary
> - :rtype: Dictionary
> - """
> - print("post_build_ex")
> - return None
> -
> -
> -def clean_ex(config, functions):
> - """Additional clean function
> -
> - :param config: The environment variables to be used in the build process
> - :type config: Dictionary
> - :param functions: A dictionary of function pointers
> - :type functions: Dictionary
> - :returns: config dictionary
> - :rtype: Dictionary
> - """
> - print("clean_ex")
> - return None
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg
> index f6ae4b342aa0..ea3cdb6d72a5 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg
> @@ -1,5 +1,5 @@
> # @ build_config.cfg
> -# This is the KabylakeRvp3 board specific build settings
> +# This is the Acer Aspire VN7-572G board specific build settings
> #
> # Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -7,16 +7,15 @@
>
>
> [CONFIG]
> -WORKSPACE_PLATFORM_BIN =
> +WORKSPACE_PLATFORM_BIN = edk2-non-osi/Platform/Intel/KabylakeOpenBoardBinPkg
> EDK_SETUP_OPTION =
> openssl_path =
> PLATFORM_BOARD_PACKAGE = KabylakeOpenBoardPkg
> -PROJECT = KabylakeOpenBoardPkg/KabylakeRvp3
> -BOARD = KabylakeRvp3
> -FLASH_MAP_FDF = KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapInclude.fdf
> -PROJECT_DSC = KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> -BOARD_PKG_PCD_DSC = KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> -ADDITIONAL_SCRIPTS = KabylakeOpenBoardPkg/KabylakeRvp3/build_board.py
> +PROJECT = KabylakeOpenBoardPkg/AspireVn7Dash572G
> +BOARD = AspireVn7Dash572G
> +FLASH_MAP_FDF = KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf
> +PROJECT_DSC = KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
> +BOARD_PKG_PCD_DSC = KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
> PrepRELEASE = DEBUG
> SILENT_MODE = FALSE
> EXT_CONFIG_CLEAR =
> --
> 2.31.1
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