[edk2-devel] [PATCH 32/40] TigerlakeSiliconPkg/Pch: Add Pch common library instances
Nate DeSimone
nathaniel.l.desimone at intel.com
Thu Feb 4 03:56:34 UTC 2021
Reviewed-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
> -----Original Message-----
> From: Luo, Heng <heng.luo at intel.com>
> Sent: Sunday, January 31, 2021 5:37 PM
> To: devel at edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty at intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone at intel.com>
> Subject: [PATCH 32/40] TigerlakeSiliconPkg/Pch: Add Pch common library
> instances
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
>
> Adds the following files:
> * Pch/Library/BasePchPciBdfLib
> * Pch/Library/BaseResetSystemLib
> * Pch/Library/DxePchPolicyLib
> * Pch/Library/PeiDxeSmmPchCycleDecodingLib
> * Pch/Library/PeiDxeSmmPchInfoLib
>
> Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
> Signed-off-by: Heng Luo <heng.luo at intel.com>
> ---
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBd
> fLib.inf | 33 +++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLib.
> c | 1092
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseReset
> SystemLib.c | 158
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseReset
> SystemLib.inf | 38 +++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLi
> b.c | 198
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLi
> b.inf | 43 +++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLi
> b/PchCycleDecodingLib.c | 587
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLi
> b/PeiDxeSmmPchCycleDecodingLib.inf | 42
> ++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfo
> Lib.c | 127
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfo
> LibPrivate.h | 58
> +++++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfo
> LibTgl.c | 715
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxeS
> mmPchInfoLibTgl.inf | 43
> +++++++++++++++++++++++++++++++++++
> 12 files changed, 3134 insertions(+)
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPci
> BdfLib.inf
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPci
> BdfLib.inf
> new file mode 100644
> index 0000000000..4f4096a409
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPci
> BdfLib.inf
> @@ -0,0 +1,33 @@
> +## @file
>
> +# PCH PCIe Bus Device Function Library.
>
> +#
>
> +# All functions from this library are available in PEI, DXE, and SMM,
>
> +# But do not support UEFI RUNTIME environment call.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +[Defines]
>
> +INF_VERSION = 0x00010017
>
> +BASE_NAME = PeiDxeSmmPchPciBdfLib
>
> +FILE_GUID = ED0C4241-40FA-4A74-B061-2E45E7AAD7BA
>
> +VERSION_STRING = 1.0
>
> +MODULE_TYPE = BASE
>
> +LIBRARY_CLASS = PchPciBdfLib
>
> +
>
> +[LibraryClasses]
>
> +BaseLib
>
> +IoLib
>
> +DebugLib
>
> +PciSegmentLib
>
> +PchInfoLib
>
> +PchPcieRpLib
>
> +
>
> +[Packages]
>
> +MdePkg/MdePkg.dec
>
> +TigerlakeSiliconPkg/SiPkg.dec
>
> +
>
> +[Sources]
>
> +PchPciBdfLib.c
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLi
> b.c
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLi
> b.c
> new file mode 100644
> index 0000000000..0db8cea4bb
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLi
> b.c
> @@ -0,0 +1,1092 @@
> +/** @file
>
> + PCH PCIe Bus Device Function Library.
>
> + All functions from this library are available in PEI, DXE, and SMM,
>
> + But do not support UEFI RUNTIME environment call.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#include <Base.h>
>
> +#include <Library/BaseLib.h>
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/PciSegmentLib.h>
>
> +#include <Library/PchInfoLib.h>
>
> +#include <Library/PchPcieRpLib.h>
>
> +#include <Register/PchRegs.h>
>
> +#include <PchBdfAssignment.h>
>
> +
>
> +/**
>
> + Check if a Device is present for PCH FRU
>
> + If the data is defined for PCH RFU return it
>
> + If the data is not defined (Device is NOT present) assert.
>
> +
>
> + @param[in] DataToCheck Device or Function number to check
>
> +
>
> + @retval Device or Function number value if defined for PCH FRU
>
> + 0xFF if not present in PCH FRU
>
> +**/
>
> +UINT8
>
> +CheckAndReturn (
>
> + UINT8 DataToCheck
>
> + )
>
> +{
>
> + if (DataToCheck == NOT_PRESENT) {
>
> + ASSERT (FALSE);
>
> + }
>
> + return DataToCheck;
>
> +}
>
> +
>
> +/**
>
> + Get eSPI controller address that can be passed to the PCI Segment Library
> functions.
>
> +
>
> + @retval eSPI controller address in PCI Segment Library representation
>
> +**/
>
> +UINT64
>
> +EspiPciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + ASSERT (PCI_DEVICE_NUMBER_PCH_ESPI != NOT_PRESENT);
>
> +
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + PCI_DEVICE_NUMBER_PCH_ESPI,
>
> + PCI_FUNCTION_NUMBER_PCH_ESPI,
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Returns Gigabit Ethernet PCI Device Number
>
> +
>
> + @retval GbE device number
>
> +**/
>
> +UINT8
>
> +GbeDevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_GBE);
>
> +}
>
> +
>
> +/**
>
> + Returns Gigabit Ethernet PCI Function Number
>
> +
>
> + @retval GbE function number
>
> +**/
>
> +UINT8
>
> +GbeFuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_GBE);
>
> +}
>
> +
>
> +/**
>
> + Get GbE controller address that can be passed to the PCI Segment Library
> functions.
>
> +
>
> + @retval GbE controller address in PCI Segment Library representation
>
> +**/
>
> +UINT64
>
> +GbePciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + GbeDevNumber (),
>
> + GbeFuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get HDA PCI device number
>
> +
>
> + @retval PCI dev number
>
> +**/
>
> +UINT8
>
> +HdaDevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_HDA);
>
> +}
>
> +
>
> +/**
>
> + Get HDA PCI function number
>
> +
>
> + @retval PCI fun number
>
> +**/
>
> +UINT8
>
> +HdaFuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_HDA);
>
> +}
>
> +
>
> +/**
>
> + Get HDA controller address that can be passed to the PCI Segment Library
> functions.
>
> +
>
> + @retval HDA controller address in PCI Segment Library representation
>
> +**/
>
> +UINT64
>
> +HdaPciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + HdaDevNumber (),
>
> + HdaFuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get P2SB PCI device number
>
> +
>
> + @retval PCI dev number
>
> +**/
>
> +UINT8
>
> +P2sbDevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_P2SB);
>
> +}
>
> +
>
> +/**
>
> + Get P2SB PCI function number
>
> +
>
> + @retval PCI fun number
>
> +**/
>
> +UINT8
>
> +P2sbFuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_P2SB);
>
> +}
>
> +
>
> +/**
>
> + Get P2SB controller address that can be passed to the PCI Segment Library
> functions.
>
> +
>
> + @retval P2SB controller address in PCI Segment Library representation
>
> +**/
>
> +UINT64
>
> +P2sbPciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + P2sbDevNumber (),
>
> + P2sbFuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Returns PCH SPI Device number
>
> +
>
> + @retval UINT8 PCH SPI Device number
>
> +**/
>
> +UINT8
>
> +SpiDevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SPI);
>
> +}
>
> +
>
> +/**
>
> + Returns PCH SPI Function number
>
> +
>
> + @retval UINT8 PCH SPI Function number
>
> +**/
>
> +UINT8
>
> +SpiFuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SPI);
>
> +}
>
> +
>
> +/**
>
> + Returns PCH SPI PCI Config Space base address
>
> +
>
> + @retval UINT64 PCH SPI Config Space base address
>
> +**/
>
> +UINT64
>
> +SpiPciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + SpiDevNumber (),
>
> + SpiFuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get XHCI controller PCIe Device Number
>
> +
>
> + @retval XHCI controller PCIe Device Number
>
> +**/
>
> +UINT8
>
> +PchXhciDevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_XHCI);
>
> +}
>
> +
>
> +/**
>
> + Get XHCI controller PCIe Function Number
>
> +
>
> + @retval XHCI controller PCIe Function Number
>
> +**/
>
> +UINT8
>
> +PchXhciFuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_XHCI);
>
> +}
>
> +
>
> +/**
>
> + Get XHCI controller address that can be passed to the PCI Segment Library
> functions.
>
> +
>
> + @retval XHCI controller address in PCI Segment Library representation
>
> +**/
>
> +UINT64
>
> +PchXhciPciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + PchXhciDevNumber (),
>
> + PchXhciFuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get XDCI controller PCIe Device Number
>
> +
>
> + @retval XDCI controller PCIe Device Number
>
> +**/
>
> +UINT8
>
> +PchXdciDevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_XDCI);
>
> +}
>
> +
>
> +/**
>
> + Get XDCI controller PCIe Function Number
>
> +
>
> + @retval XDCI controller PCIe Function Number
>
> +**/
>
> +UINT8
>
> +PchXdciFuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_XDCI);
>
> +}
>
> +
>
> +/**
>
> + Get XDCI controller address that can be passed to the PCI Segment Library
> functions.
>
> +
>
> + @retval XDCI controller address in PCI Segment Library representation
>
> +**/
>
> +UINT64
>
> +PchXdciPciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + PchXdciDevNumber (),
>
> + PchXdciFuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Return Smbus Device Number
>
> +
>
> + @retval Smbus Device Number
>
> +**/
>
> +UINT8
>
> +SmbusDevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SMBUS);
>
> +}
>
> +
>
> +/**
>
> + Return Smbus Function Number
>
> +
>
> + @retval Smbus Function Number
>
> +**/
>
> +UINT8
>
> +SmbusFuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SMBUS);
>
> +}
>
> +
>
> +/**
>
> + Get SMBUS controller address that can be passed to the PCI Segment
> Library functions.
>
> +
>
> + @retval SMBUS controller address in PCI Segment Library representation
>
> +**/
>
> +UINT64
>
> +SmbusPciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + SmbusDevNumber (),
>
> + SmbusFuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Return DMA Smbus Device Number
>
> +
>
> + @retval DMA Smbus Device Number
>
> +**/
>
> +UINT8
>
> +SmbusDmaDevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_DMA_SMBUS);
>
> +}
>
> +
>
> +/**
>
> + Return DMA Smbus Function Number
>
> +
>
> + @retval DMA Smbus Function Number
>
> +**/
>
> +UINT8
>
> +SmbusDmaFuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_DMA_SMBUS);
>
> +}
>
> +
>
> +/**
>
> + Get DMA SMBUS controller address that can be passed to the PCI Segment
> Library functions.
>
> +
>
> + @retval DMA SMBUS controller address in PCI Segment Library
> representation
>
> +**/
>
> +UINT64
>
> +SmbusDmaPciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + SmbusDmaDevNumber (),
>
> + SmbusDmaFuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get SATA controller PCIe Device Number
>
> +
>
> + @param[in] SataCtrlIndex SATA controller index
>
> +
>
> + @retval SATA controller PCIe Device Number
>
> +**/
>
> +UINT8
>
> +SataDevNumber (
>
> + IN UINT32 SataCtrlIndex
>
> + )
>
> +{
>
> + ASSERT (SataCtrlIndex < MAX_SATA_CONTROLLER);
>
> +
>
> + if (SataCtrlIndex == 0) {
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SATA_1);
>
> + } else if (SataCtrlIndex == 1) {
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SATA_2);
>
> + } else if (SataCtrlIndex == 2) {
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SATA_3);
>
> + } else {
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Get SATA controller PCIe Function Number
>
> +
>
> + @param[in] SataCtrlIndex SATA controller index
>
> +
>
> + @retval SATA controller PCIe Function Number
>
> +**/
>
> +UINT8
>
> +SataFuncNumber (
>
> + IN UINT32 SataCtrlIndex
>
> + )
>
> +{
>
> + ASSERT (SataCtrlIndex < MAX_SATA_CONTROLLER);
>
> +
>
> + if (SataCtrlIndex == 0) {
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SATA_1);
>
> + } else if (SataCtrlIndex == 1) {
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SATA_2);
>
> + } else if (SataCtrlIndex == 2) {
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SATA_3);
>
> + } else {
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Get SATA controller address that can be passed to the PCI Segment Library
> functions.
>
> +
>
> + @param[in] SataCtrlIndex SATA controller index
>
> +
>
> + @retval SATA controller address in PCI Segment Library representation
>
> +**/
>
> +UINT64
>
> +SataPciCfgBase (
>
> + IN UINT32 SataCtrlIndex
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + SataDevNumber (SataCtrlIndex),
>
> + SataFuncNumber (SataCtrlIndex),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get LPC controller PCIe Device Number
>
> +
>
> + @retval LPC controller PCIe Device Number
>
> +**/
>
> +UINT8
>
> +LpcDevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_LPC);
>
> +}
>
> +
>
> +/**
>
> + Get LPC controller PCIe Function Number
>
> +
>
> + @retval LPC controller PCIe Function Number
>
> +**/
>
> +UINT8
>
> +LpcFuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_LPC);
>
> +}
>
> +
>
> +/**
>
> + Returns PCH LPC device PCI base address.
>
> +
>
> + @retval PCH LPC PCI base address.
>
> +**/
>
> +UINT64
>
> +LpcPciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + LpcDevNumber (),
>
> + LpcFuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get Thermal Device PCIe Device Number
>
> +
>
> + @retval Thermal Device PCIe Device Number
>
> +**/
>
> +UINT8
>
> +ThermalDevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_THERMAL);
>
> +}
>
> +
>
> +/**
>
> + Get Thermal Device PCIe Function Number
>
> +
>
> + @retval Thermal Device PCIe Function Number
>
> +**/
>
> +UINT8
>
> +ThermalFuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_THERMAL);
>
> +}
>
> +
>
> +/**
>
> + Returns Thermal Device PCI base address.
>
> +
>
> + @retval Thermal Device PCI base address.
>
> +**/
>
> +UINT64
>
> +ThermalPciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + ThermalDevNumber (),
>
> + ThermalFuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get Serial IO I2C controller PCIe Device Number
>
> +
>
> + @param[in] I2cNumber Serial IO I2C controller index
>
> +
>
> + @retval Serial IO I2C controller PCIe Device Number
>
> +**/
>
> +UINT8
>
> +SerialIoI2cDevNumber (
>
> + IN UINT8 I2cNumber
>
> + )
>
> +{
>
> + if (GetPchMaxSerialIoI2cControllersNum () <= I2cNumber) {
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> + switch (I2cNumber) {
>
> + case 0:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0);
>
> + case 1:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1);
>
> + case 2:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2);
>
> + case 3:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3);
>
> + case 4:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4);
>
> + case 5:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5);
>
> + case 6:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C6);
>
> + case 7:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C7);
>
> + default:
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Get Serial IO I2C controller PCIe Function Number
>
> +
>
> + @param[in] I2cNumber Serial IO I2C controller index
>
> +
>
> + @retval Serial IO I2C controller PCIe Function Number
>
> +**/
>
> +UINT8
>
> +SerialIoI2cFuncNumber (
>
> + IN UINT8 I2cNumber
>
> + )
>
> +{
>
> + if (GetPchMaxSerialIoI2cControllersNum () <= I2cNumber) {
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> + switch (I2cNumber) {
>
> + case 0:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0);
>
> + case 1:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1);
>
> + case 2:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2);
>
> + case 3:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3);
>
> + case 4:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4);
>
> + case 5:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5);
>
> + case 6:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C6);
>
> + case 7:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C7);
>
> + default:
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Get Serial IO I2C controller address that can be passed to the PCI Segment
> Library functions.
>
> +
>
> + @param[in] I2cNumber Serial IO I2C controller index
>
> +
>
> + @retval Serial IO I2C controller address in PCI Segment Library
> representation
>
> +**/
>
> +UINT64
>
> +SerialIoI2cPciCfgBase (
>
> + IN UINT8 I2cNumber
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + SerialIoI2cDevNumber (I2cNumber),
>
> + SerialIoI2cFuncNumber (I2cNumber),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get Serial IO SPI controller PCIe Device Number
>
> +
>
> + @param[in] I2cNumber Serial IO SPI controller index
>
> +
>
> + @retval Serial IO SPI controller PCIe Device Number
>
> +**/
>
> +UINT8
>
> +SerialIoSpiDevNumber (
>
> + IN UINT8 SpiNumber
>
> + )
>
> +{
>
> + if (GetPchMaxSerialIoSpiControllersNum () <= SpiNumber) {
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> +
>
> + switch (SpiNumber) {
>
> + case 0:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0);
>
> + case 1:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1);
>
> + case 2:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI2);
>
> + case 3:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI3);
>
> + case 4:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI4);
>
> + case 5:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI5);
>
> + case 6:
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI6);
>
> + default:
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Get Serial IO SPI controller PCIe Function Number
>
> +
>
> + @param[in] SpiNumber Serial IO SPI controller index
>
> +
>
> + @retval Serial IO SPI controller PCIe Function Number
>
> +**/
>
> +UINT8
>
> +SerialIoSpiFuncNumber (
>
> + IN UINT8 SpiNumber
>
> + )
>
> +{
>
> + if (GetPchMaxSerialIoSpiControllersNum () <= SpiNumber) {
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> +
>
> + switch (SpiNumber) {
>
> + case 0:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0);
>
> + case 1:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1);
>
> + case 2:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI2);
>
> + case 3:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI3);
>
> + case 4:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI4);
>
> + case 5:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI5);
>
> + case 6:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI6);
>
> + default:
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Get Serial IO SPI controller address that can be passed to the PCI Segment
> Library functions.
>
> +
>
> + @param[in] SpiNumber Serial IO SPI controller index
>
> +
>
> + @retval Serial IO SPI controller address in PCI Segment Library
> representation
>
> +**/
>
> +UINT64
>
> +SerialIoSpiPciCfgBase (
>
> + IN UINT8 SpiNumber
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + SerialIoSpiDevNumber (SpiNumber),
>
> + SerialIoSpiFuncNumber (SpiNumber),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get Serial IO UART controller PCIe Device Number
>
> +
>
> + @param[in] UartNumber Serial IO UART controller index
>
> +
>
> + @retval Serial IO UART controller PCIe Device Number
>
> +**/
>
> +UINT8
>
> +SerialIoUartDevNumber (
>
> + IN UINT8 UartNumber
>
> + )
>
> +{
>
> + if (GetPchMaxSerialIoUartControllersNum () <= UartNumber) {
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> + switch (UartNumber) {
>
> + case 0:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0);
>
> + case 1:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1);
>
> + case 2:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2);
>
> + case 3:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART3);
>
> + case 4:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART4);
>
> + case 5:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART5);
>
> + case 6:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART6);
>
> + default:
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Get Serial IO UART controller PCIe Function Number
>
> +
>
> + @param[in] UartNumber Serial IO UART controller index
>
> +
>
> + @retval Serial IO UART controller PCIe Function Number
>
> +**/
>
> +UINT8
>
> +SerialIoUartFuncNumber (
>
> + IN UINT8 UartNumber
>
> + )
>
> +{
>
> + if (GetPchMaxSerialIoUartControllersNum () <= UartNumber) {
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> + switch (UartNumber) {
>
> + case 0:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0);
>
> + case 1:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1);
>
> + case 2:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2);
>
> + case 3:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART3);
>
> + case 4:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART4);
>
> + case 5:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART5);
>
> + case 6:
>
> + return CheckAndReturn
> (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART6);
>
> + default:
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Get Serial IO UART controller address that can be passed to the PCI
> Segment Library functions.
>
> +
>
> + @param[in] UartNumber Serial IO UART controller index
>
> +
>
> + @retval Serial IO UART controller address in PCI Segment Library
> representation
>
> +**/
>
> +UINT64
>
> +SerialIoUartPciCfgBase (
>
> + IN UINT8 UartNumber
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + SerialIoUartDevNumber (UartNumber),
>
> + SerialIoUartFuncNumber (UartNumber),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get PCH PCIe controller PCIe Device Number
>
> +
>
> + @param[in] RpIndex Root port physical number. (0-based)
>
> +
>
> + @retval PCH PCIe controller PCIe Device Number
>
> +**/
>
> +UINT8
>
> +PchPcieRpDevNumber (
>
> + IN UINTN RpIndex
>
> + )
>
> +{
>
> + if (RpIndex >= GetPchMaxPciePortNum ()) {
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> + switch (RpIndex) {
>
> + case 0:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1);
>
> + case 1:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2);
>
> + case 2:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3);
>
> + case 3:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4);
>
> + case 4:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5);
>
> + case 5:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6);
>
> + case 6:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7);
>
> + case 7:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8);
>
> + case 8:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9);
>
> + case 9:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10);
>
> + case 10:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11);
>
> + case 11:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12);
>
> + case 12:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13);
>
> + case 13:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14);
>
> + case 14:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15);
>
> + case 15:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16);
>
> + case 16:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17);
>
> + case 17:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18);
>
> + case 18:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19);
>
> + case 19:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20);
>
> + case 20:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21);
>
> + case 21:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22);
>
> + case 22:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23);
>
> + case 23:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24);
>
> + case 24:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25);
>
> + case 25:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26);
>
> + case 26:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27);
>
> + case 27:
>
> + return CheckAndReturn
> (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28);
>
> +
>
> + default:
>
> + ASSERT (FALSE);
>
> + return 0xFF;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Get PCH PCIe controller PCIe Function Number
>
> + Note:
>
> + For Client PCH generations Function Number can be various
>
> + depending on "Root Port Function Swapping". For such cases
>
> + Function Number MUST be obtain from proper register.
>
> + For Server PCHs we have no "Root Port Function Swapping"
>
> + and we can return fixed Function Number.
>
> + To address this difference in this, PCH generation independent,
>
> + library we should call specific function in PchPcieRpLib.
>
> +
>
> + @param[in] RpIndex Root port physical number. (0-based)
>
> +
>
> + @retval PCH PCIe controller PCIe Function Number
>
> +**/
>
> +UINT8
>
> +PchPcieRpFuncNumber (
>
> + IN UINTN RpIndex
>
> + )
>
> +{
>
> + UINTN Device;
>
> + UINTN Function;
>
> +
>
> + GetPchPcieRpDevFun (RpIndex, &Device, &Function);
>
> +
>
> + return (UINT8)Function;
>
> +}
>
> +
>
> +/**
>
> + Get PCH PCIe controller address that can be passed to the PCI Segment
> Library functions.
>
> +
>
> + @param[in] RpIndex PCH PCIe Root Port physical number. (0-based)
>
> +
>
> + @retval PCH PCIe controller address in PCI Segment Library representation
>
> +**/
>
> +UINT64
>
> +PchPcieRpPciCfgBase (
>
> + IN UINT32 RpIndex
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + PchPcieRpDevNumber (RpIndex),
>
> + PchPcieRpFuncNumber (RpIndex),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get HECI1 PCI device number
>
> +
>
> + @retval PCI dev number
>
> +**/
>
> +UINT8
>
> +PchHeci1DevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_HECI1);
>
> +}
>
> +
>
> +/**
>
> + Get HECI1 PCI function number
>
> +
>
> + @retval PCI fun number
>
> +**/
>
> +UINT8
>
> +PchHeci1FuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_HECI1);
>
> +}
>
> +
>
> +/**
>
> + Get HECI1 controller address that can be passed to the PCI Segment Library
> functions.
>
> +
>
> + @retval HECI1 controller address in PCI Segment Library representation
>
> +**/
>
> +UINT64
>
> +PchHeci1PciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + PchHeci1DevNumber (),
>
> + PchHeci1FuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Get HECI3 PCI device number
>
> +
>
> + @retval PCI dev number
>
> +**/
>
> +UINT8
>
> +PchHeci3DevNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_HECI3);
>
> +}
>
> +
>
> +/**
>
> + Get HECI3 PCI function number
>
> +
>
> + @retval PCI fun number
>
> +**/
>
> +UINT8
>
> +PchHeci3FuncNumber (
>
> + VOID
>
> + )
>
> +{
>
> + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_HECI3);
>
> +}
>
> +
>
> +/**
>
> + Get HECI3 controller address that can be passed to the PCI Segment Library
> functions.
>
> +
>
> + @retval HECI3 controller address in PCI Segment Library representation
>
> +**/
>
> +UINT64
>
> +PchHeci3PciCfgBase (
>
> + VOID
>
> + )
>
> +{
>
> + return PCI_SEGMENT_LIB_ADDRESS (
>
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
>
> + DEFAULT_PCI_BUS_NUMBER_PCH,
>
> + PchHeci3DevNumber (),
>
> + PchHeci3FuncNumber (),
>
> + 0
>
> + );
>
> +}
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRes
> etSystemLib.c
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRe
> setSystemLib.c
> new file mode 100644
> index 0000000000..2ede8e0021
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRe
> setSystemLib.c
> @@ -0,0 +1,158 @@
> +/** @file
>
> + System reset library services.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#include <Uefi.h>
>
> +#include <Library/IoLib.h>
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/ResetSystemLib.h>
>
> +#include <Library/PmcLib.h>
>
> +#include <Library/BaseLib.h>
>
> +#include <Register/PchRegsLpc.h>
>
> +#include <Register/PmcRegs.h>
>
> +
>
> +GLOBAL_REMOVE_IF_UNREFERENCED UINT16
> mBaseResetSystemABase;
>
> +
>
> +/**
>
> + Calling this function causes a system-wide reset. This sets
>
> + all circuitry within the system to its initial state. This type of reset
>
> + is asynchronous to system operation and operates without regard to
>
> + cycle boundaries.
>
> +
>
> + System reset should not return, if it returns, it means the system does
>
> + not support cold reset.
>
> +**/
>
> +VOID
>
> +EFIAPI
>
> +ResetCold (
>
> + VOID
>
> + )
>
> +{
>
> + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET);
>
> +}
>
> +
>
> +/**
>
> + Calling this function causes a system-wide initialization. The processors
>
> + are set to their initial state, and pending cycles are not corrupted.
>
> +
>
> + System reset should not return, if it returns, it means the system does
>
> + not support warm reset.
>
> +**/
>
> +VOID
>
> +EFIAPI
>
> +ResetWarm (
>
> + VOID
>
> + )
>
> +{
>
> + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET);
>
> +}
>
> +
>
> +/**
>
> + Calling this function causes the system to enter a power state equivalent
>
> + to the ACPI G2/S5 or G3 states.
>
> +
>
> + System shutdown should not return, if it returns, it means the system
> does
>
> + not support shut down reset.
>
> +**/
>
> +VOID
>
> +EFIAPI
>
> +ResetShutdown (
>
> + VOID
>
> + )
>
> +{
>
> + UINT16 ABase;
>
> + UINT32 Data32;
>
> +
>
> + ABase = mBaseResetSystemABase;
>
> + if (ABase == 0) {
>
> + ABase = PmcGetAcpiBase ();
>
> + }
>
> + ///
>
> + /// Firstly, GPE0_EN should be disabled to avoid any GPI waking up the
> system from S5
>
> + ///
>
> + IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);
>
> +
>
> + ///
>
> + /// Secondly, PwrSts register must be cleared
>
> + ///
>
> + /// Write a "1" to bit[8] of power button status register at
>
> + /// (PM_BASE + PM1_STS_OFFSET) to clear this bit
>
> + ///
>
> + IoWrite16 (ABase + R_ACPI_IO_PM1_STS,
> B_ACPI_IO_PM1_STS_PWRBTN);
>
> +
>
> + ///
>
> + /// Finally, transform system into S5 sleep state
>
> + ///
>
> + Data32 = IoRead32 (ABase + R_ACPI_IO_PM1_CNT);
>
> +
>
> + Data32 = (UINT32) ((Data32 &~(B_ACPI_IO_PM1_CNT_SLP_TYP +
> B_ACPI_IO_PM1_CNT_SLP_EN)) | V_ACPI_IO_PM1_CNT_S5);
>
> +
>
> + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32);
>
> +
>
> + Data32 = Data32 | B_ACPI_IO_PM1_CNT_SLP_EN;
>
> +
>
> + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32);
>
> +
>
> + return;
>
> +}
>
> +
>
> +/**
>
> + Calling this function causes the system to enter a power state for platform
> specific.
>
> +
>
> + @param[in] DataSize The size of ResetData in bytes.
>
> + @param[in] ResetData Optional element used to introduce a
> platform specific reset.
>
> + The exact type of the reset is defined by the EFI_GUID that
> follows
>
> + the Null-terminated Unicode string.
>
> +
>
> +**/
>
> +VOID
>
> +EFIAPI
>
> +ResetPlatformSpecific (
>
> + IN UINTN DataSize,
>
> + IN VOID *ResetData OPTIONAL
>
> + )
>
> +{
>
> + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET);
>
> +}
>
> +
>
> +/**
>
> + Calling this function causes the system to enter a power state for capsule
> update.
>
> +
>
> + Reset update should not return, if it returns, it means the system does
>
> + not support capsule update.
>
> +
>
> +**/
>
> +VOID
>
> +EFIAPI
>
> +EnterS3WithImmediateWake (
>
> + VOID
>
> + )
>
> +{
>
> + //
>
> + // In case there are pending capsules to process, need to flush the cache.
>
> + //
>
> + AsmWbinvd ();
>
> +
>
> + ResetWarm ();
>
> + ASSERT (FALSE);
>
> +}
>
> +
>
> +/**
>
> + The library constructuor.
>
> +
>
> + The function does the necessary initialization work for this library instance.
>
> +
>
> + @retval EFI_SUCCESS The function always return EFI_SUCCESS for
> now.
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +BaseResetSystemLibConstructor (
>
> + VOID
>
> + )
>
> +{
>
> + mBaseResetSystemABase = PmcGetAcpiBase ();
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRes
> etSystemLib.inf
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRe
> setSystemLib.inf
> new file mode 100644
> index 0000000000..a4f805035a
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRe
> setSystemLib.inf
> @@ -0,0 +1,38 @@
> +## @file
>
> +# Component description file for Intel Ich7 Reset System Library.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +[Defines]
>
> +INF_VERSION = 0x00010017
>
> +BASE_NAME = BaseResetSystemLib
>
> +FILE_GUID = D4FF05AA-3C7D-4B8A-A1EE-AA5EFA0B1732
>
> +VERSION_STRING = 1.0
>
> +MODULE_TYPE = BASE
>
> +UEFI_SPECIFICATION_VERSION = 2.00
>
> +LIBRARY_CLASS = ResetSystemLib
>
> +CONSTRUCTOR = BaseResetSystemLibConstructor
>
> +#
>
> +# The following information is for reference only and not required by the
> build tools.
>
> +#
>
> +# VALID_ARCHITECTURES = IA32 X64 IPF
>
> +#
>
> +
>
> +[LibraryClasses]
>
> +IoLib
>
> +BaseLib
>
> +DebugLib
>
> +PmcLib
>
> +
>
> +
>
> +[Packages]
>
> +MdePkg/MdePkg.dec
>
> +TigerlakeSiliconPkg/SiPkg.dec
>
> +
>
> +
>
> +[Sources]
>
> +BaseResetSystemLib.c
>
> +
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolic
> yLib.c
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolic
> yLib.c
> new file mode 100644
> index 0000000000..90aea8f420
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolic
> yLib.c
> @@ -0,0 +1,198 @@
> +/** @file
>
> + This file provide services for DXE phase policy default initialization
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#include <Uefi.h>
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/UefiBootServicesTableLib.h>
>
> +#include <ConfigBlock.h>
>
> +#include <Library/ConfigBlockLib.h>
>
> +#include <Library/SiConfigBlockLib.h>
>
> +#include <Protocol/PchPolicy.h>
>
> +#include <ScsConfig.h>
>
> +#include <Library/DxeGpioPolicyLib.h>
>
> +#include <Library/DxeHdaPolicyLib.h>
>
> +#include <Library/DxePchPcieRpPolicyLib.h>
>
> +
>
> +/**
>
> + Load DXE Config block default for eMMC
>
> +
>
> + @param[in] ConfigBlockPointer Pointer to config block
>
> +**/
>
> +VOID
>
> +LoadEmmcDxeConfigDefault (
>
> + IN VOID *ConfigBlockPointer
>
> + )
>
> +{
>
> + SCS_EMMC_DXE_CONFIG *EmmcDxeConfig;
>
> + EmmcDxeConfig = ConfigBlockPointer;
>
> +
>
> + DEBUG ((DEBUG_INFO, "EmmcDxeConfig->Header.GuidHob.Name =
> %g\n", &EmmcDxeConfig->Header.GuidHob.Name));
>
> + DEBUG ((DEBUG_INFO, "EmmcDxeConfig-
> >Header.GuidHob.Header.HobLength = 0x%x\n", EmmcDxeConfig-
> >Header.GuidHob.Header.HobLength));
>
> +
>
> + EmmcDxeConfig->DriverStrength = DriverStrength40Ohm;
>
> +}
>
> +
>
> +GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY
> mPchDxeIpBlocks [] = {
>
> + {&gEmmcDxeConfigGuid, sizeof (SCS_EMMC_DXE_CONFIG),
> SCS_EMMC_DXE_CONFIG_REVISION, LoadEmmcDxeConfigDefault}
>
> +};
>
> +
>
> +/**
>
> + Print SCS_EMMC_DXE_CONFIG.
>
> +
>
> + @param[in] EmmcDxeConfig Pointer to a SCS_EMMC_DXE_CONFIG
> that provides the eMMC settings
>
> +**/
>
> +VOID
>
> +PchPrintEmmcDxeConfig (
>
> + IN CONST SCS_EMMC_DXE_CONFIG *EmmcDxeConfig
>
> + )
>
> +{
>
> + DEBUG ((DEBUG_INFO, "------------------ PCH eMMC DXE Config -------------
> -----\n"));
>
> + DEBUG ((DEBUG_INFO, " DriverStrength : %d\n", EmmcDxeConfig-
> >DriverStrength));
>
> + DEBUG ((DEBUG_INFO, " EnableSoftwareHs400Tuning: %d\n",
> EmmcDxeConfig->EnableSoftwareHs400Tuning));
>
> + DEBUG ((DEBUG_INFO, " TuningLba : %X\n", EmmcDxeConfig-
> >TuningLba));
>
> + DEBUG ((DEBUG_INFO, " Previous tuning success : %d\n",
> EmmcDxeConfig->PreviousTuningResults.TuningSuccessful));
>
> + if (EmmcDxeConfig->PreviousTuningResults.TuningSuccessful) {
>
> + DEBUG ((DEBUG_INFO, " Hs400 Rx DLL value : %X\n", EmmcDxeConfig-
> >PreviousTuningResults.Hs400RxValue));
>
> + DEBUG ((DEBUG_INFO, " Hs400 Tx DLL value : %X\n", EmmcDxeConfig-
> >PreviousTuningResults.Hs400TxValue));
>
> + }
>
> +}
>
> +
>
> +/**
>
> + This function prints the PCH DXE phase policy.
>
> +
>
> + @param[in] PchPolicy - PCH DXE Policy protocol
>
> +**/
>
> +VOID
>
> +PchPrintPolicyProtocol (
>
> + IN PCH_POLICY_PROTOCOL *PchPolicy
>
> + )
>
> +{
>
> + DEBUG_CODE_BEGIN();
>
> + EFI_STATUS Status;
>
> + SCS_EMMC_DXE_CONFIG *EmmcDxeConfig;
>
> +
>
> + //
>
> + // Get requisite IP Config Blocks which needs to be used here
>
> + //
>
> + Status = GetConfigBlock ((VOID *) PchPolicy, &gEmmcDxeConfigGuid,
> (VOID *)&EmmcDxeConfig);
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + DEBUG ((DEBUG_INFO, "------------------------ PCH Policy (DXE) Print Start --
> ----------------------\n"));
>
> + DEBUG ((DEBUG_INFO, " Revision : %x\n", PchPolicy-
> >TableHeader.Header.Revision));
>
> +
>
> + PchPrintEmmcDxeConfig (EmmcDxeConfig);
>
> + GpioDxePrintConfig (PchPolicy);
>
> + HdaDxePrintConfig (PchPolicy);
>
> + PchPcieRpDxePrintConfig (PchPolicy);
>
> +
>
> + DEBUG ((DEBUG_INFO, "------------------------ PCH Policy (DXE) Print End ---
> -----------------------\n"));
>
> + DEBUG_CODE_END();
>
> +}
>
> +
>
> +/**
>
> + CreatePchDxeConfigBlocks generates the config blocksg of PCH DXE Policy.
>
> + It allocates and zero out buffer, and fills in the Intel default settings.
>
> +
>
> + @param[out] PchPolicy The pointer to get PCH DXE Protocol
> instance
>
> +
>
> + @retval EFI_SUCCESS The policy default is initialized.
>
> + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create
> buffer
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CreatePchDxeConfigBlocks (
>
> + IN OUT PCH_POLICY_PROTOCOL **DxePchPolicy
>
> + )
>
> +{
>
> + UINT16 TotalBlockSize;
>
> + EFI_STATUS Status;
>
> + PCH_POLICY_PROTOCOL *PchPolicyInit;
>
> + UINT16 RequiredSize;
>
> +
>
> +
>
> + DEBUG ((DEBUG_INFO, "PCH Create Dxe Config Blocks\n"));
>
> +
>
> + PchPolicyInit = NULL;
>
> +
>
> + TotalBlockSize = GetComponentConfigBlockTotalSize
> (&mPchDxeIpBlocks[0], sizeof (mPchDxeIpBlocks) / sizeof
> (COMPONENT_BLOCK_ENTRY));
>
> + TotalBlockSize += GpioDxeGetConfigBlockTotalSize();
>
> + TotalBlockSize += HdaDxeGetConfigBlockTotalSize();
>
> + TotalBlockSize += PchPcieRpDxeGetConfigBlockTotalSize();
>
> +
>
> + DEBUG ((DEBUG_INFO, "TotalBlockSize = 0x%x\n", TotalBlockSize));
>
> +
>
> + RequiredSize = sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize;
>
> +
>
> + Status = CreateConfigBlockTable (RequiredSize, (VOID *) &PchPolicyInit);
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + //
>
> + // General initialization
>
> + //
>
> + PchPolicyInit->TableHeader.Header.Revision =
> PCH_POLICY_PROTOCOL_REVISION;
>
> + //
>
> + // Add config blocks.
>
> + //
>
> + Status = AddComponentConfigBlocks ((VOID *) PchPolicyInit,
> &mPchDxeIpBlocks[0], sizeof (mPchDxeIpBlocks) / sizeof
> (COMPONENT_BLOCK_ENTRY));
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + Status = GpioDxeAddConfigBlock ((VOID *) PchPolicyInit);
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + Status = HdaDxeAddConfigBlock ((VOID *) PchPolicyInit);
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + Status = PchPcieRpDxeAddConfigBlock ((VOID *) PchPolicyInit);
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + //
>
> + // Assignment for returning SaInitPolicy config block base address
>
> + //
>
> + *DxePchPolicy = PchPolicyInit;
>
> + return Status;
>
> +}
>
> +
>
> +/**
>
> + PchInstallPolicyProtocol installs PCH Policy.
>
> + While installed, RC assumes the Policy is ready and finalized. So please
> update and override
>
> + any setting before calling this function.
>
> +
>
> + @param[in] ImageHandle Image handle of this driver.
>
> + @param[in] SaPolicy The pointer to SA Policy Protocol instance
>
> +
>
> + @retval EFI_SUCCESS The policy is installed.
>
> + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create
> buffer
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +PchInstallPolicyProtocol (
>
> + IN EFI_HANDLE ImageHandle,
>
> + IN PCH_POLICY_PROTOCOL *PchPolicy
>
> + )
>
> +{
>
> +
>
> + EFI_STATUS Status;
>
> +
>
> + ///
>
> + /// Print PCH DXE Policy
>
> + ///
>
> + PchPrintPolicyProtocol (PchPolicy);
>
> +
>
> + ///
>
> + /// Install protocol to to allow access to this Policy.
>
> + ///
>
> + Status = gBS->InstallMultipleProtocolInterfaces (
>
> + &ImageHandle,
>
> + &gPchPolicyProtocolGuid,
>
> + PchPolicy,
>
> + NULL
>
> + );
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + return Status;
>
> +}
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolic
> yLib.inf
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolic
> yLib.inf
> new file mode 100644
> index 0000000000..50e5cdacfd
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolic
> yLib.inf
> @@ -0,0 +1,43 @@
> +## @file
>
> +# Component description file for the PeiPchPolicy library.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +
>
> +[Defines]
>
> +INF_VERSION = 0x00010017
>
> +BASE_NAME = DxePchPolicyLib
>
> +FILE_GUID = E2179D04-7026-48A5-9475-309CEA2F21A3
>
> +VERSION_STRING = 1.0
>
> +MODULE_TYPE = BASE
>
> +LIBRARY_CLASS = DxePchPolicyLib
>
> +
>
> +
>
> +[LibraryClasses]
>
> +BaseMemoryLib
>
> +UefiBootServicesTableLib
>
> +DebugLib
>
> +ConfigBlockLib
>
> +SiConfigBlockLib
>
> +PchInfoLib
>
> +DxeGpioPolicyLib
>
> +DxeHdaPolicyLib
>
> +DxePchPcieRpPolicyLib
>
> +
>
> +[Packages]
>
> +MdePkg/MdePkg.dec
>
> +TigerlakeSiliconPkg/SiPkg.dec
>
> +
>
> +
>
> +[Sources]
>
> +DxePchPolicyLib.c
>
> +
>
> +
>
> +[Guids]
>
> +gEmmcDxeConfigGuid
>
> +
>
> +[Protocols]
>
> +gPchPolicyProtocolGuid ## PRODUCES
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin
> gLib/PchCycleDecodingLib.c
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin
> gLib/PchCycleDecodingLib.c
> new file mode 100644
> index 0000000000..0927cd1ced
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin
> gLib/PchCycleDecodingLib.c
> @@ -0,0 +1,587 @@
> +/** @file
>
> + PCH cycle decoding configuration and query library.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#include <Base.h>
>
> +#include <Uefi/UefiBaseType.h>
>
> +#include <Library/IoLib.h>
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/BaseLib.h>
>
> +#include <Library/PciSegmentLib.h>
>
> +#include <Library/PchInfoLib.h>
>
> +#include <Library/PchPcrLib.h>
>
> +#include <Library/PchCycleDecodingLib.h>
>
> +#include <Library/PchDmiLib.h>
>
> +#include <Library/BaseMemoryLib.h>
>
> +#include <Register/PchRegs.h>
>
> +#include <Register/PchRegsLpc.h>
>
> +#include <Register/SpiRegs.h>
>
> +#include <Register/SmbusRegs.h>
>
> +#include <Library/EspiLib.h>
>
> +#include <Library/PchPciBdfLib.h>
>
> +
>
> +typedef enum {
>
> + SlaveLpcEspiCS0,
>
> + SlaveEspiCS1,
>
> + SlaveId_Max
>
> +} SLAVE_ID_INDEX;
>
> +
>
> +/**
>
> + Get PCH TCO base address.
>
> +
>
> + @param[out] Address Address of TCO base address.
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_INVALID_PARAMETER Invalid pointer passed.
>
> +**/
>
> +EFI_STATUS
>
> +PchTcoBaseGet (
>
> + OUT UINT16 *Address
>
> + )
>
> +{
>
> + if (Address == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "PchTcoBaseGet Error. Invalid pointer.\n"));
>
> + ASSERT (FALSE);
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> + //
>
> + // Read "TCO Base Address" from DMI
>
> + // Don't read TCO base address from SMBUS PCI register since SMBUS
> might be disabled.
>
> + //
>
> + *Address = PchDmiGetTcoBase ();
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Set PCH LPC/eSPI and eSPI CS1# generic IO range decoding.
>
> +
>
> + Steps of programming generic IO range:
>
> + 1. Program LPC/eSPI PCI Offset 84h ~ 93h (LPC, eSPI CS0#) or A4h (eSPI
> CS1#) of Mask, Address, and Enable.
>
> + 2. Program LPC/eSPI Generic IO Range in DMI
>
> +
>
> + @param[in] Address Address for generic IO range decoding.
>
> + @param[in] Length Length of generic IO range.
>
> + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDEX)
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_INVALID_PARAMETER Invalid base address or length
> passed.
>
> + @retval EFI_OUT_OF_RESOURCES No more generic range available.
>
> + @retval EFI_UNSUPPORTED DMI configuration is locked,
>
> + GenIO range conflicting with other eSPI CS
>
> +**/
>
> +STATIC
>
> +EFI_STATUS
>
> +LpcEspiGenIoRangeSetHelper (
>
> + IN UINT32 Address,
>
> + IN UINT32 Length,
>
> + IN SLAVE_ID_INDEX SlaveId
>
> + )
>
> +{
>
> + return EFI_UNSUPPORTED;
>
> +}
>
> +
>
> +/**
>
> + Set PCH LPC/eSPI generic IO range.
>
> + For generic IO range, the base address must align to 4 and less than
> 0xFFFF, and the length must be power of 2
>
> + and less than or equal to 256. Moreover, the address must be length
> aligned.
>
> + This function basically checks the address and length, which should not
> overlap with all other generic ranges.
>
> + If no more generic range register available, it returns out of resource error.
>
> + This cycle decoding is also required on DMI side
>
> + Some IO ranges below 0x100 have fixed target. The target might be
> ITSS,RTC,LPC,PMC or terminated inside P2SB
>
> + but all predefined and can't be changed. IO range below 0x100 will be
> rejected in this function except below ranges:
>
> + 0x00-0x1F,
>
> + 0x44-0x4B,
>
> + 0x54-0x5F,
>
> + 0x68-0x6F,
>
> + 0x80-0x8F,
>
> + 0xC0-0xFF
>
> + Steps of programming generic IO range:
>
> + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.
>
> + 2. Program LPC/eSPI Generic IO Range in DMI
>
> +
>
> + @param[in] Address Address for generic IO range base address.
>
> + @param[in] Length Length of generic IO range.
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_INVALID_PARAMETER Invalid base address or length
> passed.
>
> + @retval EFI_OUT_OF_RESOURCES No more generic range available.
>
> + @retval EFI_UNSUPPORTED DMIC.SRL is set.
>
> +**/
>
> +EFI_STATUS
>
> +PchLpcGenIoRangeSet (
>
> + IN UINT16 Address,
>
> + IN UINTN Length
>
> + )
>
> +{
>
> + return LpcEspiGenIoRangeSetHelper ((UINT32)Address, (UINT32)Length,
> SlaveLpcEspiCS0);
>
> +}
>
> +
>
> +
>
> +/**
>
> + Set PCH LPC/eSPI and eSPI CS1# memory range decoding.
>
> + This cycle decoding is required to be set on DMI side
>
> + Programming steps:
>
> + 1. Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) [0]
> to [0] to disable memory decoding first before changing base address.
>
> + 2. Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#)
> [31:16, 0] to [Address, 1].
>
> + 3. Program LPC/eSPI Memory Range in DMI
>
> +
>
> + @param[in] Address Address for memory for decoding.
>
> + @param[in] RangeIndex Slave ID (refer to SLAVE_ID_INDEX)
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_INVALID_PARAMETER Invalid base address or length
> passed.
>
> +**/
>
> +STATIC
>
> +EFI_STATUS
>
> +LpcEspiMemRangeSetHelper (
>
> + IN UINT32 Address,
>
> + IN SLAVE_ID_INDEX SlaveId
>
> + )
>
> +{
>
> + UINT64 LpcBase;
>
> + EFI_STATUS Status;
>
> + UINT32 GenMemReg;
>
> + UINT32 MemRangeAddr;
>
> +
>
> + if (((Address & (~B_LPC_CFG_LGMR_MA)) != 0) || (SlaveId >=
> SlaveId_Max)) {
>
> + DEBUG ((DEBUG_ERROR, "%a Error. Invalid Address: %x or invalid
> SlaveId\n", __FUNCTION__, Address));
>
> + ASSERT (FALSE);
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + LpcBase = LpcPciCfgBase ();
>
> +
>
> + MemRangeAddr = ~Address;
>
> + if (SlaveId == SlaveEspiCS1) {
>
> + GenMemReg = R_ESPI_CFG_CS1GMR1;
>
> + // Memory Range already decoded for LPC/eSPI?
>
> + Status = PchLpcMemRangeGet (&MemRangeAddr);
>
> + if (MemRangeAddr != Address) {
>
> + Status = PchDmiSetEspiCs1MemRange (Address);
>
> + if (EFI_ERROR (Status)) {
>
> + ASSERT_EFI_ERROR (Status);
>
> + return Status;
>
> + }
>
> + }
>
> + } else {
>
> + GenMemReg = R_LPC_CFG_LGMR;
>
> + // Memory Range already decoded for eSPI CS1?
>
> + Status = PchEspiCs1MemRangeGet (&MemRangeAddr);
>
> + if (MemRangeAddr != Address) {
>
> + Status = PchDmiSetLpcMemRange (Address);
>
> + if (EFI_ERROR (Status)) {
>
> + ASSERT_EFI_ERROR (Status);
>
> + return Status;
>
> + }
>
> + }
>
> + }
>
> +
>
> + //
>
> + // Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) [0]
> to [0] to disable memory decoding first before changing base address.
>
> + //
>
> + PciSegmentAnd32 (
>
> + LpcBase + GenMemReg,
>
> + (UINT32) ~B_LPC_CFG_LGMR_LMRD_EN
>
> + );
>
> + //
>
> + // Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#)
> [31:16, 0] to [Address, 1].
>
> + //
>
> + PciSegmentWrite32 (
>
> + LpcBase + GenMemReg,
>
> + (Address | B_LPC_CFG_LGMR_LMRD_EN)
>
> + );
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +/**
>
> + Set PCH LPC/eSPI memory range decoding.
>
> + This cycle decoding is required to be set on DMI side
>
> + Programming steps:
>
> + 1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding first
> before changing base address.
>
> + 2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1].
>
> + 3. Program LPC Memory Range in DMI
>
> +
>
> + @param[in] Address Address for memory base address.
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_INVALID_PARAMETER Invalid base address or length
> passed.
>
> + @retval EFI_OUT_OF_RESOURCES No more generic range available.
>
> + @retval EFI_UNSUPPORTED DMIC.SRL is set.
>
> +**/
>
> +EFI_STATUS
>
> +PchLpcMemRangeSet (
>
> + IN UINT32 Address
>
> + )
>
> +{
>
> + return LpcEspiMemRangeSetHelper (Address, SlaveLpcEspiCS0);
>
> +}
>
> +
>
> +/**
>
> + Set PCH eSPI CS1# memory range decoding.
>
> + This cycle decoding is required to be set on DMI side
>
> + Programming steps:
>
> + 1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memory
> decoding first before changing base address.
>
> + 2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1].
>
> + 3. Program eSPI Memory Range in DMI
>
> +
>
> + @param[in] Address Address for memory for decoding.
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_INVALID_PARAMETER Invalid base address or length
> passed.
>
> + @retval EFI_UNSUPPORTED eSPI secondary slave not supported
>
> +**/
>
> +EFI_STATUS
>
> +PchEspiCs1MemRangeSet (
>
> + IN UINT32 Address
>
> + )
>
> +{
>
> + if (!IsEspiSecondSlaveSupported ()) {
>
> + return EFI_UNSUPPORTED;
>
> + }
>
> +
>
> + return LpcEspiMemRangeSetHelper (Address, SlaveEspiCS1);
>
> +}
>
> +
>
> +/**
>
> + Get PCH LPC/eSPI and eSPI CS1# memory range decoding address.
>
> +
>
> + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDEX)
>
> + @param[out] Address Address of LPC/eSPI or eSPI CS1# memory
> decoding base address.
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_INVALID_PARAMETER Invalid base address passed.
>
> + @retval EFI_UNSUPPORTED eSPI secondary slave not supported
>
> +**/
>
> +STATIC
>
> +EFI_STATUS
>
> +LpcEspiMemRangeGetHelper (
>
> + IN SLAVE_ID_INDEX SlaveId,
>
> + OUT UINT32 *Address
>
> + )
>
> +{
>
> + UINT32 GenMemReg;
>
> +
>
> + if ((Address == NULL) || (SlaveId >= SlaveId_Max)) {
>
> + DEBUG ((DEBUG_ERROR, "%a Error. Invalid pointer or SlaveId.\n",
> __FUNCTION__));
>
> + ASSERT (FALSE);
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + if (SlaveId == SlaveEspiCS1) {
>
> + GenMemReg = R_ESPI_CFG_CS1GMR1;
>
> + } else {
>
> + GenMemReg = R_LPC_CFG_LGMR;
>
> + }
>
> + *Address = PciSegmentRead32 (LpcPciCfgBase () + GenMemReg) &
> B_LPC_CFG_LGMR_MA;
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Get PCH LPC/eSPI memory range decoding address.
>
> +
>
> + @param[out] Address Address of LPC/eSPI memory decoding
> base address.
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_INVALID_PARAMETER Invalid base address passed.
>
> +**/
>
> +EFI_STATUS
>
> +PchLpcMemRangeGet (
>
> + OUT UINT32 *Address
>
> + )
>
> +{
>
> + return LpcEspiMemRangeGetHelper (SlaveLpcEspiCS0, Address);
>
> +}
>
> +
>
> +/**
>
> + Get PCH eSPI CS1# memory range decoding address.
>
> +
>
> + @param[out] Address Address of eSPI CS1# memory decoding
> base address.
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_INVALID_PARAMETER Invalid base address passed.
>
> + @retval EFI_UNSUPPORTED eSPI secondary slave not supported
>
> +**/
>
> +EFI_STATUS
>
> +PchEspiCs1MemRangeGet (
>
> + OUT UINT32 *Address
>
> + )
>
> +{
>
> + if (!IsEspiSecondSlaveSupported ()) {
>
> + return EFI_UNSUPPORTED;
>
> + }
>
> +
>
> + return LpcEspiMemRangeGetHelper (SlaveEspiCS1, Address);
>
> +}
>
> +
>
> +/**
>
> + Set PCH BIOS range deocding.
>
> + This will check General Control and Status bit 10 (GCS.BBS) to identify SPI
> or LPC/eSPI and program BDE register accordingly.
>
> + Please check EDS for detail of BiosDecodeEnable bit definition.
>
> + bit 15: F8-FF Enable
>
> + bit 14: F0-F8 Enable
>
> + bit 13: E8-EF Enable
>
> + bit 12: E0-E8 Enable
>
> + bit 11: D8-DF Enable
>
> + bit 10: D0-D7 Enable
>
> + bit 9: C8-CF Enable
>
> + bit 8: C0-C7 Enable
>
> + bit 7: Legacy F Segment Enable
>
> + bit 6: Legacy E Segment Enable
>
> + bit 5: Reserved
>
> + bit 4: Reserved
>
> + bit 3: 70-7F Enable
>
> + bit 2: 60-6F Enable
>
> + bit 1: 50-5F Enable
>
> + bit 0: 40-4F Enable
>
> + This cycle decoding is also required in DMI
>
> + Programming steps:
>
> + 1. if GCS.BBS is 0 (SPI), program SPI offset D8h to BiosDecodeEnable.
>
> + if GCS.BBS is 1 (LPC/eSPi), program LPC offset D8h to BiosDecodeEnable.
>
> + 2. program LPC BIOS Decode Enable in DMI
>
> +
>
> + @param[in] BiosDecodeEnable Bios decode enable setting.
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_UNSUPPORTED DMIC.SRL is set.
>
> +**/
>
> +EFI_STATUS
>
> +PchBiosDecodeEnableSet (
>
> + IN UINT16 BiosDecodeEnable
>
> + )
>
> +{
>
> + UINT64 BaseAddr;
>
> + EFI_STATUS Status;
>
> +
>
> + Status = PchDmiSetBiosDecodeEnable (BiosDecodeEnable);
>
> + if (EFI_ERROR (Status)) {
>
> + ASSERT_EFI_ERROR (Status);
>
> + return Status;
>
> + }
>
> +
>
> + //
>
> + // Check Boot BIOS Strap in DMI
>
> + //
>
> + if (PchDmiIsBootBiosStrapSetForSpi ()) {
>
> + BaseAddr = SpiPciCfgBase ();
>
> + //
>
> + // If SPI, Program SPI offset D8h to BiosDecodeEnable.
>
> + //
>
> + PciSegmentWrite16 (BaseAddr + R_SPI_CFG_BDE, BiosDecodeEnable);
>
> + } else {
>
> + BaseAddr = LpcPciCfgBase ();
>
> + //
>
> + // If LPC/eSPi, program LPC offset D8h to BiosDecodeEnable.
>
> + //
>
> + PciSegmentWrite16 (BaseAddr + R_LPC_CFG_BDE, BiosDecodeEnable);
>
> + }
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +/**
>
> + Set PCH LPC/eSPI IO decode ranges.
>
> + Program LPC/eSPI I/O Decode Ranges in DMI to the same value
> programmed in LPC/eSPI PCI offset 80h.
>
> + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
>
> + Bit 12: FDD range
>
> + Bit 9:8: LPT range
>
> + Bit 6:4: ComB range
>
> + Bit 2:0: ComA range
>
> +
>
> + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit
> settings.
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_UNSUPPORTED DMIC.SRL is set.
>
> +**/
>
> +EFI_STATUS
>
> +PchLpcIoDecodeRangesSet (
>
> + IN UINT16 LpcIoDecodeRanges
>
> + )
>
> +{
>
> + UINT64 LpcBaseAddr;
>
> + EFI_STATUS Status;
>
> +
>
> + //
>
> + // Note: Inside this function, don't use debug print since it's could used
> before debug print ready.
>
> + //
>
> +
>
> + LpcBaseAddr = LpcPciCfgBase ();
>
> +
>
> + //
>
> + // check if setting is identical
>
> + //
>
> + if (LpcIoDecodeRanges == PciSegmentRead16 (LpcBaseAddr +
> R_LPC_CFG_IOD)) {
>
> + return EFI_SUCCESS;
>
> + }
>
> +
>
> + Status = PchDmiSetLpcIoDecodeRanges (LpcIoDecodeRanges);
>
> + if (EFI_ERROR (Status)) {
>
> + ASSERT_EFI_ERROR (Status);
>
> + return Status;
>
> + }
>
> +
>
> + //
>
> + // program LPC/eSPI PCI offset 80h.
>
> + //
>
> + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOD,
> LpcIoDecodeRanges);
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +/**
>
> + Set PCH LPC/eSPI and eSPI CS1# IO enable decoding.
>
> + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset
> 82h (LPC, eSPI CS0#) or A0h (eSPI CS1#).
>
> + Note: Bit[15:10] of the source decode register is Read-Only. The IO range
> indicated by the Enables field
>
> + in LPC/eSPI PCI offset 82h[13:10] or A0h[13:10] is always forwarded by DMI
> to subtractive agent for handling.
>
> + Please check EDS for detail of Lpc/eSPI IO decode ranges bit definition.
>
> +
>
> + @param[in] IoEnableDecoding LPC/eSPI IO enable decoding bit
> settings.
>
> + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDEX)
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_UNSUPPORTED DMI configuration is locked
>
> +**/
>
> +EFI_STATUS
>
> +LpcEspiIoEnableDecodingSetHelper (
>
> + IN UINT16 IoEnableDecoding,
>
> + IN SLAVE_ID_INDEX SlaveId
>
> + )
>
> +{
>
> + UINT64 LpcBaseAddr;
>
> + EFI_STATUS Status;
>
> + UINT16 Cs1IoEnableDecodingOrg;
>
> + UINT16 Cs0IoEnableDecodingOrg;
>
> + UINT16 IoEnableDecodingMerged;
>
> +
>
> + LpcBaseAddr = LpcPciCfgBase ();
>
> +
>
> + Cs0IoEnableDecodingOrg = PciSegmentRead16 (LpcBaseAddr +
> R_LPC_CFG_IOE);
>
> +
>
> + if (IsEspiSecondSlaveSupported ()) {
>
> + Cs1IoEnableDecodingOrg = PciSegmentRead16 (LpcBaseAddr +
> R_ESPI_CFG_CS1IORE);
>
> + } else {
>
> + Cs1IoEnableDecodingOrg = 0;
>
> + }
>
> +
>
> + if (SlaveId == SlaveEspiCS1) {
>
> + if (IoEnableDecoding == Cs1IoEnableDecodingOrg) {
>
> + return EFI_SUCCESS;
>
> + } else {
>
> + IoEnableDecodingMerged = (Cs0IoEnableDecodingOrg |
> IoEnableDecoding);
>
> + }
>
> + } else {
>
> + if ((IoEnableDecoding | Cs1IoEnableDecodingOrg) ==
> Cs0IoEnableDecodingOrg) {
>
> + return EFI_SUCCESS;
>
> + } else {
>
> + IoEnableDecodingMerged = (Cs1IoEnableDecodingOrg |
> IoEnableDecoding);
>
> + }
>
> + }
>
> +
>
> + Status = PchDmiSetLpcIoEnable (IoEnableDecodingMerged);
>
> + if (EFI_ERROR (Status)) {
>
> + ASSERT_EFI_ERROR (Status);
>
> + return Status;
>
> + }
>
> +
>
> + //
>
> + // program PCI offset 82h for LPC/eSPI.
>
> + //
>
> + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOE,
> IoEnableDecodingMerged);
>
> +
>
> + if (SlaveId == SlaveEspiCS1) {
>
> + //
>
> + // For eSPI CS1# device program eSPI PCI offset A0h.
>
> + //
>
> + PciSegmentWrite16 (LpcBaseAddr + R_ESPI_CFG_CS1IORE,
> IoEnableDecoding);
>
> + }
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +/**
>
> + Set PCH LPC and eSPI CS0# IO enable decoding.
>
> + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset
> 82h.
>
> + Note: Bit[15:10] of the source decode register is Read-Only. The IO range
> indicated by the Enables field
>
> + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to
> subtractive agent for handling.
>
> + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
>
> +
>
> + @param[in] LpcIoEnableDecoding LPC IO enable decoding bit settings.
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_UNSUPPORTED DMIC.SRL is set.
>
> +**/
>
> +EFI_STATUS
>
> +PchLpcIoEnableDecodingSet (
>
> + IN UINT16 LpcIoEnableDecoding
>
> + )
>
> +{
>
> + return LpcEspiIoEnableDecodingSetHelper (LpcIoEnableDecoding,
> SlaveLpcEspiCS0);
>
> +}
>
> +
>
> +/**
>
> + Set PCH eSPI CS1# IO enable decoding.
>
> + Setup I/O Enables in DMI to the same value program in eSPI PCI offset A0h
> (eSPI CS1#).
>
> + Note: Bit[15:10] of the source decode register is Read-Only. The IO range
> indicated by the Enables field
>
> + in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractive
> agent for handling.
>
> + Please check EDS for detail of eSPI IO decode ranges bit definition.
>
> +
>
> + @param[in] IoEnableDecoding eSPI IO enable decoding bit settings.
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_UNSUPPORTED DMI configuration is locked
>
> +**/
>
> +EFI_STATUS
>
> +PchEspiCs1IoEnableDecodingSet (
>
> + IN UINT16 IoEnableDecoding
>
> + )
>
> +{
>
> + if (!IsEspiSecondSlaveSupported ()) {
>
> + return EFI_UNSUPPORTED;
>
> + }
>
> +
>
> + return LpcEspiIoEnableDecodingSetHelper (IoEnableDecoding,
> SlaveEspiCS1);
>
> +}
>
> +
>
> +
>
> +/**
>
> + Get IO APIC regsiters base address.
>
> +
>
> + @param[out] IoApicBase Buffer of IO APIC regsiter address
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> +**/
>
> +EFI_STATUS
>
> +PchIoApicBaseGet (
>
> + OUT UINT32 *IoApicBase
>
> + )
>
> +{
>
> + *IoApicBase = PcdGet32 (PcdSiIoApicBaseAddress);
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Get HPET base address.
>
> +
>
> + @param[out] HpetBase Buffer of HPET base address
>
> +
>
> + @retval EFI_SUCCESS Successfully completed.
>
> + @retval EFI_INVALID_PARAMETER Invalid offset passed.
>
> +**/
>
> +EFI_STATUS
>
> +PchHpetBaseGet (
>
> + OUT UINT32 *HpetBase
>
> + )
>
> +{
>
> + if (HpetBase == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "PchHpetBaseGet Error. Invalid pointer.\n"));
>
> + ASSERT (FALSE);
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + *HpetBase = PcdGet32 (PcdSiHpetBaseAddress);
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin
> gLib/PeiDxeSmmPchCycleDecodingLib.inf
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin
> gLib/PeiDxeSmmPchCycleDecodingLib.inf
> new file mode 100644
> index 0000000000..ea6b434f29
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin
> gLib/PeiDxeSmmPchCycleDecodingLib.inf
> @@ -0,0 +1,42 @@
> +## @file
>
> +# PCH cycle decoding Lib.
>
> +#
>
> +# All function in this library is available for PEI, DXE, and SMM,
>
> +# But do not support UEFI RUNTIME environment call.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +
>
> +[Defines]
>
> +INF_VERSION = 0x00010017
>
> +BASE_NAME = PeiDxeSmmPchCycleDecodingLib
>
> +FILE_GUID = 676C749F-9CD1-46B7-BAFD-4B1BC36B4C8E
>
> +VERSION_STRING = 1.0
>
> +MODULE_TYPE = BASE
>
> +LIBRARY_CLASS = PchCycleDecodingLib
>
> +
>
> +
>
> +[LibraryClasses]
>
> +BaseLib
>
> +IoLib
>
> +DebugLib
>
> +PciSegmentLib
>
> +PchInfoLib
>
> +PchPcrLib
>
> +PchDmiLib
>
> +EspiLib
>
> +PchPciBdfLib
>
> +
>
> +[Packages]
>
> +MdePkg/MdePkg.dec
>
> +TigerlakeSiliconPkg/SiPkg.dec
>
> +
>
> +[Sources]
>
> +PchCycleDecodingLib.c
>
> +
>
> +[Pcd]
>
> +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress ## CONSUMES
>
> +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress ## CONSUMES
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInf
> oLib.c
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn
> foLib.c
> new file mode 100644
> index 0000000000..df8a23d5a3
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn
> foLib.c
> @@ -0,0 +1,127 @@
> +/** @file
>
> + Pch information library.
>
> +
>
> + All function in this library is available for PEI, DXE, and SMM,
>
> + But do not support UEFI RUNTIME environment call.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#include <Base.h>
>
> +#include <Uefi/UefiBaseType.h>
>
> +#include <Library/IoLib.h>
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/BaseLib.h>
>
> +#include <Library/PciSegmentLib.h>
>
> +#include <Library/PchInfoLib.h>
>
> +#include <Library/PchPcrLib.h>
>
> +#include <Library/PrintLib.h>
>
> +#include <Library/PcdLib.h>
>
> +#include "PchInfoLibPrivate.h"
>
> +#include <Register/PchRegs.h>
>
> +#include <Register/PchRegsLpc.h>
>
> +#include <PchPcieRpInfo.h>
>
> +#include <IndustryStandard/Pci30.h>
>
> +#include <Library/PchPciBdfLib.h>
>
> +
>
> +/**
>
> + Return Pch Series
>
> +
>
> + @retval PCH_SERIES Pch Series
>
> +**/
>
> +PCH_SERIES
>
> +PchSeries (
>
> + VOID
>
> + )
>
> +{
>
> + return PCH_LP;
>
> +}
>
> +
>
> +/**
>
> + Return Pch stepping type
>
> +
>
> + @retval PCH_STEPPING Pch stepping type
>
> +**/
>
> +PCH_STEPPING
>
> +PchStepping (
>
> + VOID
>
> + )
>
> +{
>
> + return 0;
>
> +}
>
> +
>
> +/**
>
> + Check if this is TGL PCH generation
>
> +
>
> + @retval TRUE It's TGL PCH
>
> + @retval FALSE It's not TGL PCH
>
> +**/
>
> +BOOLEAN
>
> +IsTglPch (
>
> + VOID
>
> + )
>
> +{
>
> + return (PchGeneration () == TGL_PCH);
>
> +}
>
> +
>
> +/**
>
> + Get PCH stepping ASCII string.
>
> + Function determines major and minor stepping versions and writes them
> into a buffer.
>
> + The return string is zero terminated
>
> +
>
> + @param [out] Buffer Output buffer of string
>
> + @param [in] BufferSize Buffer size.
>
> + Must not be less then
> PCH_STEPPING_STR_LENGTH_MAX
>
> +
>
> + @retval EFI_SUCCESS String copied successfully
>
> + @retval EFI_INVALID_PARAMETER The stepping is not supported, or
> parameters are NULL
>
> + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small
>
> +**/
>
> +EFI_STATUS
>
> +PchGetSteppingStr (
>
> + OUT CHAR8 *Buffer,
>
> + IN UINT32 BufferSize
>
> + )
>
> +{
>
> + PCH_STEPPING PchStep;
>
> +
>
> + PchStep = PchStepping ();
>
> +
>
> + if ((Buffer == NULL) || (BufferSize == 0)) {
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> + if (BufferSize < PCH_STEPPING_STR_LENGTH_MAX) {
>
> + return EFI_BUFFER_TOO_SMALL;
>
> + }
>
> +
>
> + PchPrintSteppingStr (Buffer, BufferSize, PchStep);
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Pcie Controller Number
>
> +
>
> + @retval Pch Maximum Pcie Root Port Number
>
> +**/
>
> +UINT8
>
> +GetPchMaxPcieControllerNum (
>
> + VOID
>
> + )
>
> +{
>
> + return GetPchMaxPciePortNum () / PCH_PCIE_CONTROLLER_PORTS;
>
> +}
>
> +
>
> +/**
>
> + return support status for P2SB PCR 20-bit addressing
>
> +
>
> + @retval TRUE
>
> + @retval FALSE
>
> +**/
>
> +BOOLEAN
>
> +IsP2sb20bPcrSupported (
>
> + VOID
>
> + )
>
> +{
>
> + return FALSE;
>
> +}
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInf
> oLibPrivate.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn
> foLibPrivate.h
> new file mode 100644
> index 0000000000..a93c3dbafd
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn
> foLibPrivate.h
> @@ -0,0 +1,58 @@
> +/** @file
>
> + Private header for PCH Info Lib.
>
> +
>
> + All function in this library is available for PEI, DXE, and SMM,
>
> + But do not support UEFI RUNTIME environment call.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +/**
>
> + Structure for PCH SKU string mapping
>
> +**/
>
> +struct PCH_SKU_STRING {
>
> + UINT16 Id;
>
> + CHAR8 *String;
>
> +};
>
> +
>
> +/**
>
> + Determine Pch Series based on Device Id
>
> +
>
> + @param[in] LpcDeviceId Lpc Device Id
>
> +
>
> + @retval PCH_SERIES Pch Series
>
> +**/
>
> +PCH_SERIES
>
> +PchSeriesFromLpcDid (
>
> + IN UINT16 LpcDeviceId
>
> + );
>
> +
>
> +/**
>
> +Determine Pch Generation based on Device Id
>
> +
>
> + at param[in] LpcDeviceId Lpc Device Id
>
> +
>
> + at retval PCH_GENERATION Pch Generation
>
> +**/
>
> +PCH_GENERATION
>
> +PchGenerationFromDid (
>
> + IN UINT16 LpcDeviceId
>
> + );
>
> +
>
> +/**
>
> + Print Pch Stepping String
>
> +
>
> + @param[out] Buffer Output buffer of string
>
> + @param[in] BufferSize Buffer Size
>
> + @param[in] PchStep Pch Stepping Type
>
> +
>
> + @retval VOID
>
> +**/
>
> +VOID
>
> +PchPrintSteppingStr (
>
> + OUT CHAR8 *Buffer,
>
> + IN UINT32 BufferSize,
>
> + IN PCH_STEPPING PchStep
>
> + );
>
> +
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInf
> oLibTgl.c
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn
> foLibTgl.c
> new file mode 100644
> index 0000000000..bb3c7975e8
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn
> foLibTgl.c
> @@ -0,0 +1,715 @@
> +/** @file
>
> + Pch information library for TGL.
>
> +
>
> + All function in this library is available for PEI, DXE, and SMM,
>
> + But do not support UEFI RUNTIME environment call.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#include <Uefi/UefiBaseType.h>
>
> +#include <Library/PchInfoLib.h>
>
> +#include "PchInfoLibPrivate.h"
>
> +#include <Library/PrintLib.h>
>
> +#include <Register/PchRegsLpc.h>
>
> +
>
> +/**
>
> + Print Pch Stepping String
>
> +
>
> + @param[out] Buffer Output buffer of string
>
> + @param[in] BufferSize Buffer Size
>
> + @param[in] PchStep Pch Stepping Type
>
> +
>
> + @retval VOID
>
> +**/
>
> +VOID
>
> +PchPrintSteppingStr (
>
> + OUT CHAR8 *Buffer,
>
> + IN UINT32 BufferSize,
>
> + IN PCH_STEPPING PchStep
>
> + )
>
> +{
>
> + AsciiSPrint (Buffer, BufferSize, "%c%c", 'A' + (PchStep >> 4), '0' + (PchStep
> & 0xF));
>
> +}
>
> +
>
> +/**
>
> + Return Pch Generation
>
> +
>
> + @retval PCH_GENERATION Pch Generation
>
> +**/
>
> +PCH_GENERATION
>
> +PchGeneration (
>
> + VOID
>
> + )
>
> +{
>
> + return TGL_PCH;
>
> +}
>
> +
>
> +
>
> +/**
>
> + Get PCH series ASCII string.
>
> +
>
> + @retval PCH Series string
>
> +**/
>
> +CHAR8*
>
> +PchGetSeriesStr (
>
> + VOID
>
> + )
>
> +{
>
> + switch (PchSeries ()) {
>
> +
>
> + case PCH_LP:
>
> + return "TGL PCH-LP";
>
> +
>
> + default:
>
> + return NULL;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Pcie Clock Number
>
> +
>
> + @retval Pch Maximum Pcie Clock Number
>
> +**/
>
> +UINT8
>
> +GetPchMaxPcieClockNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 7;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Pcie ClockReq Number
>
> +
>
> + @retval Pch Maximum Pcie ClockReq Number
>
> +**/
>
> +UINT8
>
> +GetPchMaxPcieClockReqNum (
>
> + VOID
>
> + )
>
> +{
>
> + return GetPchMaxPcieClockNum ();
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Type C Port Number
>
> +
>
> + @retval Pch Maximum Type C Port Number
>
> +**/
>
> +UINT8
>
> +GetPchMaxTypeCPortNum (
>
> + VOID
>
> + )
>
> +{
>
> + switch (PchSeries ()) {
>
> + case PCH_LP:
>
> + return 4;
>
> + default:
>
> + return 0;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Check whether integrated LAN controller is supported by PCH Series.
>
> +
>
> + @retval TRUE GbE is supported in current PCH
>
> + @retval FALSE GbE is not supported on current PCH
>
> +**/
>
> +BOOLEAN
>
> +PchIsGbeSupported (
>
> + VOID
>
> + )
>
> +{
>
> + return TRUE;
>
> +}
>
> +
>
> +/**
>
> + Check whether integrated TSN is supported by PCH Series.
>
> +
>
> + @retval TRUE TSN is supported in current PCH
>
> + @retval FALSE TSN is not supported on current PCH
>
> +**/
>
> +BOOLEAN
>
> +PchIsTsnSupported (
>
> + VOID
>
> + )
>
> +{
>
> +#if FixedPcdGet8(PcdEmbeddedEnable) == 0x1
>
> + return TRUE;
>
> +#else
>
> + return FALSE;
>
> +#endif
>
> +}
>
> +
>
> +/**
>
> + Check whether ISH is supported by PCH Series.
>
> +
>
> + @retval TRUE ISH is supported in current PCH
>
> + @retval FALSE ISH is not supported on current PCH
>
> +**/
>
> +BOOLEAN
>
> +PchIsIshSupported (
>
> + VOID
>
> + )
>
> +{
>
> + return TRUE;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Pcie Root Port Number
>
> +
>
> + @retval Pch Maximum Pcie Root Port Number
>
> +**/
>
> +UINT8
>
> +GetPchMaxPciePortNum (
>
> + VOID
>
> + )
>
> +{
>
> + switch (PchSeries ()) {
>
> + case PCH_LP:
>
> + return 12;
>
> + default:
>
> + return 0;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Hda Dmic Link
>
> +
>
> + @retval Pch Maximum Hda Dmic Link
>
> +**/
>
> +UINT8
>
> +GetPchHdaMaxDmicLinkNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 2;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Hda Sndw Link
>
> +
>
> + @retval Pch Maximum Hda Sndw Link
>
> +**/
>
> +UINT8
>
> +GetPchHdaMaxSndwLinkNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 4;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Hda Ssp Link
>
> +
>
> + @retval Pch Maximum Hda Ssp Link
>
> +**/
>
> +UINT8
>
> +GetPchHdaMaxSspLinkNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 3;
>
> +}
>
> +
>
> +/**
>
> + Check if given Audio Interface is supported
>
> +
>
> + @param[in] AudioLinkType Link type support to be checked
>
> + @param[in] AudioLinkIndex Link number
>
> +
>
> + @retval TRUE Link supported
>
> + @retval FALSE Link not supported
>
> +**/
>
> +BOOLEAN
>
> +IsAudioInterfaceSupported (
>
> + IN HDAUDIO_LINK_TYPE AudioLinkType,
>
> + IN UINT32 AudioLinkIndex
>
> + )
>
> +{
>
> + //
>
> + // Interfaces supported:
>
> + // 1. HDA Link (SDI0/SDI1)
>
> + // 2. Display Audio Link (SDI2)
>
> + // 3. SSP[0-5]
>
> + // 4. SNDW[1-4]
>
> + //
>
> + switch (AudioLinkType) {
>
> + case HdaLink:
>
> + case HdaIDispLink:
>
> + return TRUE;
>
> + case HdaDmic:
>
> + if (AudioLinkIndex < 2) {
>
> + return TRUE;
>
> + } else {
>
> + return FALSE;
>
> + }
>
> + case HdaSsp:
>
> + if (AudioLinkIndex < 6) {
>
> + return TRUE;
>
> + } else {
>
> + return FALSE;
>
> + }
>
> + case HdaSndw:
>
> + if (AudioLinkIndex < 1) {
>
> + return TRUE;
>
> + } else if (AudioLinkIndex < 4) {
>
> + return TRUE;
>
> + } else {
>
> + return FALSE;
>
> + }
>
> + default:
>
> + return FALSE;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Check if given Display Audio Link T-Mode is supported
>
> +
>
> + @param[in] Tmode T-mode support to be checked
>
> +
>
> + @retval TRUE T-mode supported
>
> + @retval FALSE T-mode not supported
>
> +**/
>
> +BOOLEAN
>
> +IsAudioIDispTmodeSupported (
>
> + IN HDAUDIO_IDISP_TMODE Tmode
>
> + )
>
> +{
>
> + //
>
> + // iDisplay Audio Link T-mode support per PCH Generation/Series:
>
> + // 1. 2T - TGL-LP/H/N
>
> + // 2. 4T - TGL-LP (default), TGL-H, TGL-N
>
> + // 3. 8T - TGL-H, TGL-N (default)
>
> + // 4. 16T - TGL-H, TGL-N (not-POR)
>
> + //
>
> + switch (Tmode) {
>
> + case HdaIDispMode1T:
>
> + return FALSE;
>
> + case HdaIDispMode2T:
>
> + case HdaIDispMode4T:
>
> + case HdaIDispMode8T:
>
> + return TRUE;
>
> + case HdaIDispMode16T:
>
> + return FALSE;
>
> + default:
>
> + return FALSE;
>
> + }
>
> +}
>
> +
>
> +/**
>
> +Get Pch Usb2 Maximum Physical Port Number
>
> +
>
> + at retval Pch Usb2 Maximum Physical Port Number
>
> +**/
>
> +UINT8
>
> +GetPchUsb2MaxPhysicalPortNum(
>
> + VOID
>
> + )
>
> +{
>
> + switch (PchSeries()) {
>
> + case PCH_LP:
>
> + return 10;
>
> + default:
>
> + return 0;
>
> + }
>
> +}
>
> +
>
> +/**
>
> +Get Pch Maximum Usb2 Port Number of XHCI Controller
>
> +
>
> + at retval Pch Maximum Usb2 Port Number of XHCI Controller
>
> +**/
>
> +UINT8
>
> +GetPchXhciMaxUsb2PortNum(
>
> + VOID
>
> + )
>
> +{
>
> + switch (PchSeries()) {
>
> + case PCH_LP:
>
> + return 12;
>
> + default:
>
> + return 0;
>
> + }
>
> +}
>
> +
>
> +/**
>
> +Get Pch Maximum Usb3 Port Number of XHCI Controller
>
> +
>
> + at retval Pch Maximum Usb3 Port Number of XHCI Controller
>
> +**/
>
> +UINT8
>
> +GetPchXhciMaxUsb3PortNum(
>
> + VOID
>
> + )
>
> +{
>
> + switch (PchSeries()) {
>
> + case PCH_LP:
>
> + return 4;
>
> + default:
>
> + return 0;
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Gets the maximum number of UFS controller supported by this chipset.
>
> +
>
> + @return Number of supported UFS controllers
>
> +**/
>
> +UINT8
>
> +PchGetMaxUfsNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 2;
>
> +}
>
> +
>
> +/**
>
> + Check if this chipset supports eMMC controller
>
> +
>
> + @retval BOOLEAN TRUE if supported, FALSE otherwise
>
> +**/
>
> +BOOLEAN
>
> +IsPchEmmcSupported (
>
> + VOID
>
> + )
>
> +{
>
> + return FALSE;
>
> +}
>
> +
>
> +/**
>
> + Check if this chipset supports SD controller
>
> +
>
> + @retval BOOLEAN TRUE if supported, FALSE otherwise
>
> +**/
>
> +BOOLEAN
>
> +IsPchSdCardSupported (
>
> + VOID
>
> + )
>
> +{
>
> + return FALSE;
>
> +}
>
> +
>
> +/**
>
> + Check if this chipset supports THC controller
>
> +
>
> + @retval BOOLEAN TRUE if supported, FALSE otherwise
>
> +**/
>
> +BOOLEAN
>
> +IsPchThcSupported (
>
> + VOID
>
> + )
>
> +{
>
> + return TRUE;
>
> +}
>
> +
>
> +/**
>
> + Check if this chipset supports HSIO BIOS Sync
>
> +
>
> + @retval BOOLEAN TRUE if supported, FALSE otherwise
>
> +**/
>
> +BOOLEAN
>
> +IsPchChipsetInitSyncSupported (
>
> + VOID
>
> + )
>
> +{
>
> + return TRUE;
>
> +}
>
> +
>
> +/**
>
> + Check if link between PCH and CPU is an P-DMI
>
> +
>
> + @retval TRUE P-DMI link
>
> + @retval FALSE Not an P-DMI link
>
> +**/
>
> +BOOLEAN
>
> +IsPchWithPdmi (
>
> + VOID
>
> + )
>
> +{
>
> + return FALSE;
>
> +}
>
> +
>
> +/**
>
> + Check whether ATX Shutdown (PS_ON) is supported.
>
> +
>
> + @retval TRUE ATX Shutdown (PS_ON) is supported in PCH
>
> + @retval FALSE ATX Shutdown (PS_ON) is not supported by PCH
>
> +**/
>
> +BOOLEAN
>
> +IsPchPSOnSupported (
>
> + VOID
>
> + )
>
> +{
>
> + return FALSE;
>
> +}
>
> +
>
> +/**
>
> + Check if link between PCH and CPU is an OP-DMI
>
> +
>
> + @retval TRUE OP-DMI link
>
> + @retval FALSE Not an OP-DMI link
>
> +**/
>
> +BOOLEAN
>
> +IsPchWithOpdmi (
>
> + VOID
>
> + )
>
> +{
>
> + return TRUE;
>
> +}
>
> +
>
> +/**
>
> + Check if link between PCH and CPU is an F-DMI
>
> +
>
> + @retval TRUE F-DMI link
>
> + @retval FALSE Not an F-DMI link
>
> +**/
>
> +BOOLEAN
>
> +IsPchWithFdmi (
>
> + VOID
>
> + )
>
> +{
>
> + return FALSE;
>
> +}
>
> +/**
>
> + Get Pch Maximum ISH UART Controller number
>
> +
>
> + @retval Pch Maximum ISH UART controllers number
>
> +**/
>
> +UINT8
>
> +GetPchMaxIshUartControllersNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 2;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum ISH I2C Controller number
>
> +
>
> + @retval Pch Maximum ISH I2C controllers number
>
> +**/
>
> +UINT8
>
> +GetPchMaxIshI2cControllersNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 3;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum ISH I3C Controller number
>
> +
>
> + @retval Pch Maximum ISH I3C controllers number
>
> +**/
>
> +UINT8
>
> +GetPchMaxIshI3cControllersNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 0;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum ISH SPI Controller number
>
> +
>
> + @retval Pch Maximum ISH SPI controllers number
>
> +**/
>
> +UINT8
>
> +GetPchMaxIshSpiControllersNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 1;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum ISH SPI Controller Cs pins number
>
> +
>
> + @retval Pch Maximum ISH SPI controller Cs pins number
>
> +**/
>
> +UINT8
>
> +GetPchMaxIshSpiControllerCsPinsNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 1;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum ISH GP number
>
> +
>
> + @retval Pch Maximum ISH GP number
>
> +**/
>
> +UINT8
>
> +GetPchMaxIshGpNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 8;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Serial IO I2C controllers number
>
> +
>
> + @retval Pch Maximum Serial IO I2C controllers number
>
> +**/
>
> +UINT8
>
> +GetPchMaxSerialIoI2cControllersNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 6;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Serial IO SPI controllers number
>
> +
>
> + @retval Pch Maximum Serial IO SPI controllers number
>
> +**/
>
> +UINT8
>
> +GetPchMaxSerialIoSpiControllersNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 4;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Serial IO UART controllers number
>
> +
>
> + @retval Pch Maximum Serial IO UART controllers number
>
> +**/
>
> +UINT8
>
> +GetPchMaxSerialIoUartControllersNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 4;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum Serial IO SPI Chip Selects count
>
> +
>
> + @retval Pch Maximum Serial IO SPI Chip Selects number
>
> +**/
>
> +UINT8
>
> +GetPchMaxSerialIoSpiChipSelectsNum (
>
> + VOID
>
> + )
>
> +{
>
> + return 2;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum ME Applet count
>
> +
>
> + @retval Pch Maximum ME Applet number
>
> +**/
>
> +UINT8
>
> +GetPchMaxMeAppletCount (
>
> + VOID
>
> + )
>
> +{
>
> + return 31;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum ME Session count
>
> +
>
> + @retval Pch Maximum ME Sesion number
>
> +**/
>
> +UINT8
>
> +GetPchMaxMeSessionCount (
>
> + VOID
>
> + )
>
> +{
>
> + return 16;
>
> +}
>
> +
>
> +/**
>
> + Get Pch Maximum THC count
>
> +
>
> + @retval Pch Maximum THC count number
>
> +**/
>
> +UINT8
>
> +GetPchMaxThcCount (
>
> + VOID
>
> + )
>
> +{
>
> + return 2;
>
> +}
>
> +
>
> +/**
>
> + Returns a frequency of the sosc_clk signal.
>
> + All SATA controllers on the system are assumed to
>
> + work on the same sosc_clk frequency.
>
> +
>
> + @retval Frequency of the sosc_clk signal.
>
> +**/
>
> +SATA_SOSC_CLK_FREQ
>
> +GetSataSoscClkFreq (
>
> + VOID
>
> + )
>
> +{
>
> + return SataSosc100Mhz;
>
> +}
>
> +
>
> +/**
>
> + Check if SATA support should be awake after function disable
>
> +
>
> + @retval TRUE
>
> + @retval FALSE
>
> +**/
>
> +BOOLEAN
>
> +IsSataSupportWakeAfterFunctionDisable (
>
> + VOID
>
> + )
>
> +{
>
> + return TRUE;
>
> +}
>
> +
>
> +/**
>
> + Returns USB2 PHY Reference Clock frequency value used by PCH
>
> + This defines what electrical tuning parameters shall be used
>
> + during USB2 PHY initialization programming
>
> +
>
> + @retval Frequency reference clock for USB2 PHY
>
> +**/
>
> +USB2_PHY_REF_FREQ
>
> +GetUsb2PhyRefFreq (
>
> + VOID
>
> + )
>
> +{
>
> + return FREQ_19_2;
>
> +}
>
> +
>
> +/**
>
> + Check if SPI in a given PCH generation supports an Extended BIOS Range
> Decode
>
> +
>
> + @retval TRUE or FALSE if PCH supports Extended BIOS Range Decode
>
> +**/
>
> +BOOLEAN
>
> +IsExtendedBiosRangeDecodeSupported (
>
> + VOID
>
> + )
>
> +{
>
> + return TRUE;
>
> +}
>
> +
>
> +#define SPI_PCH_LP_DMI_TARGET 0x23A8
>
> +
>
> +/**
>
> + Returns DMI target for current PCH SPI
>
> +
>
> + @retval PCH SPI DMI target value
>
> +**/
>
> +UINT16
>
> +GetPchSpiDmiTarget (
>
> + VOID
>
> + )
>
> +{
>
> + return SPI_PCH_LP_DMI_TARGET;
>
> +}
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDx
> eSmmPchInfoLibTgl.inf
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDx
> eSmmPchInfoLibTgl.inf
> new file mode 100644
> index 0000000000..4b3fb988d2
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDx
> eSmmPchInfoLibTgl.inf
> @@ -0,0 +1,43 @@
> +## @file
>
> +# PCH information library for TigerLake PCH.
>
> +#
>
> +# All function in this library is available for PEI, DXE, and SMM,
>
> +# But do not support UEFI RUNTIME environment call.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +
>
> +[Defines]
>
> +INF_VERSION = 0x00010017
>
> +BASE_NAME = PeiDxeSmmPchInfoLibTgl
>
> +FILE_GUID = 253B9BFC-026F-4BB4-AC2C-AC167BC0F43C
>
> +VERSION_STRING = 1.0
>
> +MODULE_TYPE = BASE
>
> +LIBRARY_CLASS = PchInfoLib
>
> +
>
> +
>
> +[LibraryClasses]
>
> +BaseLib
>
> +IoLib
>
> +DebugLib
>
> +PrintLib
>
> +PciSegmentLib
>
> +PchPcrLib
>
> +PcdLib
>
> +PchPciBdfLib
>
> +
>
> +
>
> +[Packages]
>
> +MdePkg/MdePkg.dec
>
> +TigerlakeSiliconPkg/SiPkg.dec
>
> +
>
> +
>
> +[Sources]
>
> +PchInfoLib.c
>
> +PchInfoLibTgl.c
>
> +
>
> +[Pcd]
>
> +gSiPkgTokenSpaceGuid.PcdEmbeddedEnable ## CONSUMES
>
> --
> 2.24.0.windows.2
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