[edk2-devel] [PATCH edk2-platforms v1 1/2] TigerlakeSiliconPkg: Fix build error with GCC5
Takuto Naito
naitaku at gmail.com
Wed Feb 24 01:37:35 UTC 2021
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224
Fix build errors caused by "-Werror=unused-but-set-variable" with GCC5.
These build errors occur only with DEBUG target because
RELEASE_GCC5_X64_CC_FLAGS has "-Wno-unused-but-set-variable",
but DEBUG_GCC5_X64_CC_FLAGS doesn't.
Cc: Sai Chaganty <rangasai.v.chaganty at intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
Cc: Heng Luo <heng.luo at intel.com>
Signed-off-by: Takuto Naito <naitaku at gmail.com>
---
.../PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c | 2 --
.../IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c | 5 -----
.../Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c | 2 --
3 files changed, 9 deletions(-)
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c
index 15d295a573..231cb367bc 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c
@@ -104,12 +104,10 @@ ConfigureRpLtrOverride (
UINT32 OvrEn;
UINT32 OvrVal;
BOOLEAN IsCpuPcie;
- UINT32 LtrCfgLock;
IsCpuPcie = FALSE;
OvrEn = 0;
OvrVal = 0;
- LtrCfgLock = 0;
if (DevNum == SA_PEG0_DEV_NUM || DevNum == SA_PEG3_DEV_NUM) {
IsCpuPcie = TRUE;
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c
index faac07c45d..e88abe550f 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c
@@ -313,8 +313,6 @@ DmarTableUpdate (
UINTN Offset;
UINTN StructureLen;
UINT64 McD0BaseAddress;
- UINT32 GttMmAdr;
- UINT64 McD2BaseAddress;
UINT16 IgdMode;
UINT16 GttMode;
UINT32 IgdMemSize;
@@ -381,9 +379,6 @@ DmarTableUpdate (
GttMemSize = (1 << GttMode) * (1024) * (1024);
}
- McD2BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, 0);
- GttMmAdr = (PciSegmentRead32 (McD2BaseAddress + R_SA_IGD_GTTMMADR)) & 0xFFFFFFF0;
-
DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionBaseAddress = (PciSegmentRead32 (McD0BaseAddress + R_SA_BGSM) & ~(0x01));
DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionLimitAddress = DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionBaseAddress + IgdMemSize + GttMemSize - 1;
DEBUG ((DEBUG_INFO, "RMRR Base address IGD %016lX\n", DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionBaseAddress));
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c b/Silicon/Intel/TigerlakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c
index 7693e76683..3adc05ce89 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c
@@ -29,8 +29,6 @@ GetPcieRpNumber (
OUT UINTN *RpNumber
)
{
- UINT64 RpBase;
- RpBase = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, RpDev, RpFun, 0);
GetPchPcieRpNumber (RpDev, RpFun, RpNumber);
}
--
2.30.1
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