[edk2-devel] [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in high 32bit of MEM64.

[Zhong, Zarcd]

Hi Ray,

Attached patch is updated with below add. Thanks for your remind.

PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;


From: Ni, Ray <ray.ni at intel.com>
Sent: Wednesday, January 13, 2021 3:01 PM
To: Zhong, Zarcd <zarcd.zhong at intel.com>; devel at edk2.groups.io
Cc: Wu, Hao A <hao.a.wu at intel.com>; Kinney, Michael D <michael.d.kinney at intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in high 32bit of MEM64.

Zarcd,
I can understand that this patch is needed for some buggy pci devices whose
VF bar behaves strangely. Incompatible PCI protocol can only deal with normal
PCI bar. And this patch is just to enhance the error handling logic.

Can you please use below code for error handling?
+        PciIoDevice->VfPciBar[BarIndex].BarType     = PciBarTypeUnknown

I understand that your change is aligned to existing error handling in the beginning
of PciIovParseVfBar().
But that logic runs before PciIoDevice->VfPciBar[BarIndex].BarType is assigned.
The key is to reset the BarType to PciBarTypeUnknown so that the resource summary
code doesn't count this bar.

Thanks,
Ray

From: Zhong, Zarcd <zarcd.zhong at intel.com<mailto:zarcd.zhong at intel.com>>
Sent: Monday, January 4, 2021 5:48 PM
To: devel at edk2.groups.io<mailto:devel at edk2.groups.io>
Cc: Ni, Ray <ray.ni at intel.com<mailto:ray.ni at intel.com>>; Wu, Hao A <hao.a.wu at intel.com<mailto:hao.a.wu at intel.com>>
Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in high 32bit of MEM64.

>From 7518212a85269e486d06dcea927a3d34e23372c2 Mon Sep 17 00:00:00 2001
From: Zarcd Zhong <zarcd.zhong at intel.com<mailto:zarcd.zhong at intel.com>>
Date: Mon, 4 Jan 2021 17:32:54 +0800
Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in high 32bit of MEM64.

    REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3149

    Clear length and alignment for low 32bit of MEM64 BAR if sizing fail in high 32bit.

    Cc: Ray Ni <ray.ni at intel.com<mailto:ray.ni at intel.com>>
    Cc: Hao A Wu <hao.a.wu at intel.com<mailto:hao.a.wu at intel.com>>


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