[edk2-devel] [PATCH v1 08/10] Silicon/Phytium: Added flash driver support to Phytium Silicon
Ling Jia
jialing at phytium.com.cn
Fri Jan 15 08:48:00 UTC 2021
From: Ling <jialing at phytium.com.cn>
The PhytiumSpiNorFlashDxe provided norflash initialization,
read-write, erase and other interfaces.
Cc: Leif Lindholm <leif at nuviainc.com>
Signed-off-by: Ling Jia <jialing at phytium.com.cn>
Signed-off-by: Peng Xie <xiepeng at phytium.com.cn>
Reviewed-by: Yiqi Shu <shuyiqi at phytium.com.cn>
---
Platform/Phytium/Durian/DurianPkg.dsc | 5 +
Platform/Phytium/Durian/DurianPkg.fdf | 5 +
Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf | 54 +++
Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.h | 106 +++++
Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h | 74 ++++
Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.c | 435 ++++++++++++++++++++
6 files changed, 679 insertions(+)
diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
index a23c1d52cece..d34432e95049 100644
--- a/Platform/Phytium/Durian/DurianPkg.dsc
+++ b/Platform/Phytium/Durian/DurianPkg.dsc
@@ -261,6 +261,11 @@ [Components.common]
#
Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf
+ #
+ # NOR Flash driver
+ #
+ Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf
+
#
# Usb Support
#
diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
index ad0406b3133b..703537033944 100644
--- a/Platform/Phytium/Durian/DurianPkg.fdf
+++ b/Platform/Phytium/Durian/DurianPkg.fdf
@@ -110,6 +110,11 @@ [FV.FvMain]
#
INF Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf
+ #
+ # NOR Flash driver
+ #
+ INF Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf
+
# Variable services
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
diff --git a/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf
new file mode 100644
index 000000000000..2979dad60c1e
--- /dev/null
+++ b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf
@@ -0,0 +1,54 @@
+#/** @file
+# Phytium NorFlash Drivers.
+#
+# Copyright (C) 2020, Phytium Technology Co,Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = PhytiumSpiNorFlashDxe
+ FILE_GUID = f37ef706-187c-48fd-9102-ddbf86f551be
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = NorFlashPlatformEntryPoint
+
+[Sources.common]
+ PhytiumSpiNorFlashDxe.c
+ PhytiumSpiNorFlashDxe.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/Phytium/Phytium.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ PcdLib
+ IoLib
+ UefiBootServicesTableLib
+ DxeServicesTableLib
+ UefiRuntimeLib
+ UefiLib
+ UefiDriverEntryPoint
+
+[FixedPcd]
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize
+
+[Guids]
+ gEfiEventVirtualAddressChangeGuid
+
+[Protocols]
+ gPhytiumSpiMasterProtocolGuid
+ gPhytiumFlashProtocolGuid
+
+ [Depex]
+ TRUE
+ #gPhytiumSpiMasterProtocolGuid
diff --git a/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.h b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.h
new file mode 100644
index 000000000000..caee5591f3bd
--- /dev/null
+++ b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.h
@@ -0,0 +1,106 @@
+/** @file
+ Phytium NorFlash Drivers Header.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PHYTIUM_SPI_NORFALSH_DXE_H__
+#define __PHYTIUM_SPI_NORFALSH_DXE_H__
+
+#include <PiDxe.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Guid/EventGroup.h>
+
+#include <PhytiumSystemServiceInterface.h>
+#include <Protocol/PhytiumSpiNorFlash.h>
+#include <Protocol/PhytiumSpi.h>
+
+/**
+ Phytium Norflash registers
+**/
+#define REG_FLASH_CAP 0x000
+#define REG_RD_CFG 0x004
+#define REG_WR_CFG 0x008
+#define REG_FLUSH_REG 0x00C
+#define REG_CMD_PORT 0x010
+#define REG_ADDR_PORT 0x014
+#define REG_HD_PORT 0x018
+#define REG_LD_PORT 0x01C
+#define REG_CS_CFG 0x020
+#define REG_WIP_CFG 0x024
+#define REG_WP_REG 0x028
+
+#define NORFLASH_SIGNATURE SIGNATURE_32 ('P', 'T', 'Y', 'T')
+
+//
+// Platform Nor Flash Functions
+//
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEraseSingleBlock (
+ IN UINTN BlockAddress
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformErase (
+ IN UINT64 Offset,
+ IN UINT64 Length
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformRead (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ OUT UINT32 Len
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformWrite (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ IN UINT32 Len
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformGetDevices (
+ OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformInitialization (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+typedef struct {
+ EFI_NORFLASH_DRV_PROTOCOL FlashProtocol;
+ UINTN Signature;
+ EFI_HANDLE Handle;
+} PHYT_NorFlash_Device;
+
+#endif /* __PHYTIUM_SPI_NORFALSH_DXE_H__ */
diff --git a/Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h b/Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h
new file mode 100644
index 000000000000..84c83dbd88eb
--- /dev/null
+++ b/Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h
@@ -0,0 +1,74 @@
+/** @file
+ The Header of Protocol For NorFlash.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PHYTIUM_SPI_NORFALSH_H__
+#define __PHYTIUM_SPI_NORFALSH_H__
+
+typedef struct _EFI_NORFLASH_DRV_PROTOCOL EFI_NORFLASH_DRV_PROTOCOL;
+extern EFI_GUID gPhytiumFlashProtocolGuid;
+
+typedef struct {
+ UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA)
+ UINTN RegionBaseAddress; // Start address of one single region
+ UINTN Size;
+ UINTN BlockSize;
+ EFI_GUID Guid;
+} NOR_FLASH_DEVICE_DESCRIPTION;
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_ERASE_INTERFACE) (
+ IN UINT64 Offset,
+ IN UINT64 Length
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE) (
+ IN UINTN BlockAddress
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_READ_INTERFACE) (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ OUT UINT32 Len
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_WRITE_INTERFACE) (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ IN UINT32 Len
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_GETDEVICE_INTERFACE) (
+ OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_INIT_INTERFACE) (
+ VOID
+ );
+
+struct _EFI_NORFLASH_DRV_PROTOCOL{
+ NORFLASH_PLATFORM_INIT_INTERFACE Initialization;
+ NORFLASH_PLATFORM_GETDEVICE_INTERFACE GetDevices;
+ NORFLASH_PLATFORM_ERASE_INTERFACE Erase;
+ NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE EraseSingleBlock;
+ NORFLASH_PLATFORM_READ_INTERFACE Read;
+ NORFLASH_PLATFORM_WRITE_INTERFACE Write;
+};
+
+#endif /* __PHYTIUM_SPI_NORFALSH_H__*/
diff --git a/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.c b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.c
new file mode 100644
index 000000000000..2614035e0714
--- /dev/null
+++ b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.c
@@ -0,0 +1,435 @@
+/** @file
+ Phytium NorFlash Drivers.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PhytiumSpiNorFlashDxe.h"
+
+typedef struct {
+ UINT32 Flash_Index;
+ UINT32 Flash_Write;
+ UINT32 Flash_Erase;
+ UINT32 Flash_Pp;
+}FLASH_CMD_INFO;
+
+STATIC EFI_EVENT mSpiNorFlashVirtualAddrChangeEvent;
+STATIC UINTN mNorFlashControlBase;
+STATIC UINT32 mCmd_Write;
+STATIC UINT32 mCmd_Eares;
+STATIC UINT32 mCmd_Pp;
+
+#define SPI_FLASH_BASE FixedPcdGet64 (PcdSpiFlashBase)
+#define SPI_FLASH_SIZE FixedPcdGet64 (PcdSpiFlashSize)
+
+EFI_SPI_DRV_PROTOCOL *pSpiMasterProtocol;
+extern EFI_GUID gPhytiumSpiMasterProtocolGuid;
+PHYT_NorFlash_Device *flash_Instance;
+extern EFI_GUID gPhytiumFlashProtocolGuid;
+
+NOR_FLASH_DEVICE_DESCRIPTION mNorFlashDevices = {
+ SPI_FLASH_BASE, /* Device Base Address */
+ SPI_FLASH_BASE, /* Region Base Address */
+ SIZE_1MB * 16, /* Size */
+ SIZE_64KB, /* Block Size */
+ {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59 } }
+};
+
+
+/**
+ This function writed up to 256 bytes to flash through spi driver.
+
+ @param[in] Address The address of the flash.
+ @param[in] Buffer The pointer of buffer to be writed.
+ @param[in] BufferSizeInBytes The bytes to be writed.
+
+ @retval EFI_SUCCESS NorFlashWrite256() is executed successfully.
+
+**/
+STATIC
+EFI_STATUS
+NorFlashWrite256 (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ IN UINT32 BufferSizeInBytes
+ )
+{
+ UINT32 Index;
+ UINT8 Cmd_id;
+ UINT32 *TemBuffer;
+
+ TemBuffer= Buffer;
+
+ if(BufferSizeInBytes > 256) {
+ DEBUG((DEBUG_ERROR, "The max length is 256 bytes.\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(BufferSizeInBytes % 4 != 0) {
+ DEBUG((DEBUG_ERROR, "The length must four bytes aligned.\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(Address % 4 != 0) {
+ DEBUG((DEBUG_ERROR, "The address must four bytes aligned.\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Cmd_id = (UINT8)(mCmd_Pp & 0xff);
+ pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x400000, REG_CMD_PORT);
+ pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);
+
+ asm volatile ("isb sy":::"cc");
+
+ Cmd_id = (UINT8)(mCmd_Write & 0xff);
+ pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x000208, REG_WR_CFG);
+
+ for(Index = 0; Index < BufferSizeInBytes / 4; Index++) {
+ MmioWrite32(Address + Index * 4, TemBuffer[Index]);
+ }
+
+ asm volatile ("isb sy":::"cc");
+
+ pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_FLUSH_REG);
+
+ asm volatile ("isb sy":::"cc");
+
+ pSpiMasterProtocol->SpiSetConfig (0, 0x0, REG_WR_CFG);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function erased a sector of flash through spi driver.
+
+ @param[in] BlockAddress The sector address to be erased.
+
+ @retval None.
+
+**/
+STATIC
+inline void
+NorFlashPlatformEraseSector (
+ IN UINTN BlockAddress
+ )
+{
+ UINT8 Cmd_id = 0;
+
+ Cmd_id = (UINT8)(mCmd_Pp & 0xff);
+ pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x400000, REG_CMD_PORT);
+ pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);
+
+ asm volatile ("isb sy":::"cc");
+
+ Cmd_id = (UINT8)(mCmd_Eares & 0xff);
+ pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x408000, REG_CMD_PORT);
+ pSpiMasterProtocol->SpiSetConfig (0, BlockAddress, REG_ADDR_PORT);
+ pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);
+
+ asm volatile ("isb sy":::"cc");
+}
+
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed.
+
+ @param[in] Context Event Context.
+
+ @retval None.
+
+**/
+VOID
+EFIAPI
+PlatformNorFlashVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EfiConvertPointer (0x0, (VOID **)&mNorFlashControlBase);
+ EfiConvertPointer (0x0, (VOID**)&pSpiMasterProtocol->SpiGetConfig);
+ EfiConvertPointer (0x0, (VOID**)&pSpiMasterProtocol->SpiSetConfig);
+ EfiConvertPointer (0x0, (VOID**)&pSpiMasterProtocol);
+}
+
+
+/**
+ This function inited the flash platform.
+
+ @param None.
+
+ @retval EFI_SUCCESS NorFlashPlatformInitialization() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformInitialization (
+ VOID
+ )
+{
+
+ mCmd_Write = 0x2;
+ mCmd_Eares = 0xD8;
+ mCmd_Pp = 0x6;
+
+ mNorFlashControlBase = FixedPcdGet64 (PcdSpiControllerBase);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function geted the flash device information.
+
+ @param[out] NorFlashDevices the pointer to store flash device information.
+ @param[out] Count the number of the flash device.
+
+ @retval EFI_SUCCESS NorFlashPlatformGetDevices() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformGetDevices (
+ OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices
+ )
+{
+
+ *NorFlashDevices = mNorFlashDevices;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function readed flash content form the specified area of flash.
+
+ @param[in] Address The address of the flash.
+ @param[in] Buffer The pointer of the Buffer to be stored.
+ @param[out] Len The bytes readed form flash.
+
+ @retval EFI_SUCCESS NorFlashPlatformRead() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformRead (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ OUT UINT32 Len
+ )
+{
+
+ DEBUG((DEBUG_BLKIO, "NorFlashPlatformRead: Address: 0x%lx Buffer:0x%p Len:0x%x\n", Address, Buffer, Len));
+
+ CopyMem ((VOID *)Buffer, (VOID *)Address, Len);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function erased one block flash content.
+
+ @param[in] BlockAddress the BlockAddress to be erased.
+
+ @retval EFI_SUCCESS NorFlashPlatformEraseSingleBlock() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEraseSingleBlock (
+ IN UINTN BlockAddress
+ )
+{
+
+ NorFlashPlatformEraseSector (BlockAddress);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function erased the flash content of the specified area.
+
+ @param[in] Offset the offset of the flash.
+ @param[in] Length length to be erased.
+
+ @retval EFI_SUCCESS NorFlashPlatformErase() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformErase (
+ IN UINT64 Offset,
+ IN UINT64 Length
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Index;
+ UINT64 Count;
+
+ Status = EFI_SUCCESS;
+ if ((Length % SIZE_64KB) == 0) {
+ Count = Length / SIZE_64KB;
+ for (Index = 0; Index < Count; Index++) {
+ NorFlashPlatformEraseSingleBlock (Offset);
+ Offset += SIZE_64KB;
+ }
+ } else {
+ Status = EFI_INVALID_PARAMETER;
+ }
+
+ return Status;
+}
+
+
+/**
+ This function writed data to flash.
+
+ @param[in] Address the address of the flash.
+
+ @param[in] Buffer the pointer of the Buffer to be writed.
+
+ @param[in] BufferSizeInBytes the bytes of the Buffer.
+
+ @retval EFI_SUCCESS NorFlashPlatformWrite() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformWrite (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ IN UINT32 BufferSizeInBytes
+ )
+{
+ UINT32 Index;
+ UINT32 Remainder;
+ UINT32 Quotient;
+ EFI_STATUS Status;
+ UINTN TmpAddress;
+
+ DEBUG((DEBUG_BLKIO, "NorFlashPlatformWrite: Address: 0x%x Len:0x%x.\n", Address, BufferSizeInBytes));
+
+ Index = 0;
+ Remainder = 0;
+ Quotient = 0;
+ TmpAddress = Address;
+ Remainder = BufferSizeInBytes % 256;
+ Quotient = BufferSizeInBytes / 256;
+
+ if(BufferSizeInBytes <= 256) {
+ Status = NorFlashWrite256 (TmpAddress, Buffer, BufferSizeInBytes);
+ } else {
+ for(Index = 0; Index < Quotient; Index++) {
+ Status = NorFlashWrite256 (TmpAddress, Buffer, 256);
+ TmpAddress += 256;
+ Buffer += 256;
+ }
+
+ if(Remainder != 0) {
+ Status = NorFlashWrite256 (TmpAddress, Buffer, Remainder);
+ }
+ }
+
+ if(EFI_ERROR(Status)) {
+ ASSERT_EFI_ERROR(Status);
+ }
+
+ return EFI_SUCCESS;
+
+}
+
+
+/**
+ This function inited the flash driver protocol.
+
+ @param[in] NorFlashProtocol A pointer to the norflash protocol struct.
+
+ @retval EFI_SUCCESS NorFlashPlatformInitProtocol() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformInitProtocol (
+ IN EFI_NORFLASH_DRV_PROTOCOL *NorFlashProtocol
+ )
+{
+ NorFlashProtocol->Initialization = NorFlashPlatformInitialization;
+ NorFlashProtocol->GetDevices = NorFlashPlatformGetDevices;
+ NorFlashProtocol->Erase = NorFlashPlatformErase;
+ NorFlashProtocol->EraseSingleBlock = NorFlashPlatformEraseSingleBlock;
+ NorFlashProtocol->Read = NorFlashPlatformRead;
+ NorFlashProtocol->Write = NorFlashPlatformWrite;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function is the entrypoint of the norflash driver.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->LocateProtocol (
+ &gPhytiumSpiMasterProtocolGuid,
+ NULL,
+ (VOID **)&pSpiMasterProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ flash_Instance = AllocateRuntimeZeroPool (sizeof (PHYT_NorFlash_Device));
+ if (flash_Instance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ NorFlashPlatformInitProtocol (&flash_Instance->FlashProtocol);
+
+ flash_Instance->Signature = NORFLASH_SIGNATURE;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &(flash_Instance->Handle),
+ &gPhytiumFlashProtocolGuid,
+ &(flash_Instance->FlashProtocol),
+ NULL
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ //Register for the virtual address change event
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ PlatformNorFlashVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mSpiNorFlashVirtualAddrChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
--
2.25.1
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