[edk2-devel] [edk2-platforms] [PATCH V1 14/17] WhitleyOpenBoardPkg: Add build scripts and package metadata
Nate DeSimone
nathaniel.l.desimone at intel.com
Tue Jul 13 00:41:28 UTC 2021
Signed-off-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
Co-authored-by: Isaac Oram <isaac.w.oram at intel.com>
Co-authored-by: Mohamed Abbas <mohamed.abbas at intel.com>
Cc: Chasel Chiu <chasel.chiu at intel.com>
Cc: Michael D Kinney <michael.d.kinney at intel.com>
Cc: Isaac Oram <isaac.w.oram at intel.com>
Cc: Mohamed Abbas <mohamed.abbas at intel.com>
Cc: Liming Gao <gaoliming at byosoft.com.cn>
Cc: Eric Dong <eric.dong at intel.com>
Cc: Michael Kubacki <Michael.Kubacki at microsoft.com>
---
.../CooperCityRvp/build_board.py | 111 +
.../CooperCityRvp/build_config.cfg | 36 +
.../WhitleyOpenBoardPkg/DynamicExPcd.dsc | 19 +
.../WhitleyOpenBoardPkg/FspFlashOffsets.fdf | 21 +
.../Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 781 ++
.../Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 931 ++
.../Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 827 ++
.../WhitleyOpenBoardPkg/PlatformPkgConfig.dsc | 45 +
.../WhitleyOpenBoardPkg/StructurePcd.dsc | 8553 +++++++++++++++++
.../WhitleyOpenBoardPkg/StructurePcdCpx.dsc | 3796 ++++++++
.../WilsonCityRvp/build_board.py | 111 +
.../WilsonCityRvp/build_config.cfg | 36 +
12 files changed, 15267 insertions(+)
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_board.py
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/DynamicExPcd.dsc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/FspFlashOffsets.fdf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_board.py b/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_board.py
new file mode 100644
index 0000000000..87b49b32c8
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_board.py
@@ -0,0 +1,111 @@
+# @ build_board.py
+# Extensions for building CooperCityRvp using build_bios.py
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+"""
+This module serves as a sample implementation of the build extension
+scripts
+"""
+
+import os
+import sys
+
+def pre_build_ex(config, functions):
+ """Additional Pre BIOS build function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: nothing
+ """
+ print("pre_build_ex")
+ config["BUILD_DIR_PATH"] = os.path.join(config["WORKSPACE"],
+ 'Build',
+ config["PLATFORM_BOARD_PACKAGE"],
+ "{}_{}".format(
+ config["TARGET"],
+ config["TOOL_CHAIN_TAG"]))
+ # set BUILD_DIR path
+ config["BUILD_DIR"] = os.path.join('Build',
+ config["PLATFORM_BOARD_PACKAGE"],
+ "{}_{}".format(
+ config["TARGET"],
+ config["TOOL_CHAIN_TAG"]))
+ config["BUILD_X64"] = os.path.join(config["BUILD_DIR_PATH"], 'X64')
+ config["BUILD_IA32"] = os.path.join(config["BUILD_DIR_PATH"], 'IA32')
+
+ if not os.path.isdir(config["BUILD_DIR_PATH"]):
+ try:
+ os.makedirs(config["BUILD_DIR_PATH"])
+ except OSError:
+ print("Error while creating Build folder")
+ sys.exit(1)
+
+ #@todo: Replace this with PcdFspModeSelection
+ if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+ config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=0"
+ else:
+ config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=1"
+ return None
+
+def _merge_files(files, ofile):
+ with open(ofile, 'wb') as of:
+ for x in files:
+ if not os.path.exists(x):
+ return
+
+ with open(x, 'rb') as f:
+ of.write(f.read())
+
+def build_ex(config, functions):
+ """Additional BIOS build function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("build_ex")
+ fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV")
+ binary_fd = os.path.join(fv_path, "BINARY.fd")
+ main_fd = os.path.join(fv_path, "MAIN.fd")
+ secpei_fd = os.path.join(fv_path, "SECPEI.fd")
+ board_fd = config["BOARD"].upper()
+ final_fd = os.path.join(fv_path, "{}.fd".format(board_fd))
+ _merge_files((binary_fd, main_fd, secpei_fd), final_fd)
+ return None
+
+
+def post_build_ex(config, functions):
+ """Additional Post BIOS build function
+
+ :param config: The environment variables to be used in the post
+ build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("post_build_ex")
+ return None
+
+
+def clean_ex(config, functions):
+ """Additional clean function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("clean_ex")
+ return None
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg b/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg
new file mode 100644
index 0000000000..6399818e78
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg
@@ -0,0 +1,36 @@
+# @ build_config.cfg
+# This is the CooperCityRvp board specific build settings
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[CONFIG]
+WORKSPACE_PLATFORM_BIN =
+EDK_SETUP_OPTION =
+openssl_path =
+PLATFORM_BOARD_PACKAGE = WhitleyOpenBoardPkg
+PROJECT = WhitleyOpenBoardPkg/CooperCityRvp
+BOARD = CooperCityRvp
+FLASH_MAP_FDF = WhitleyOpenBoardPkg/FspFlashOffsets.fdf
+PROJECT_DSC = WhitleyOpenBoardPkg/PlatformPkg.dsc
+BOARD_PKG_PCD_DSC = WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
+ADDITIONAL_SCRIPTS = WhitleyOpenBoardPkg/CooperCityRvp/build_board.py
+PrepRELEASE = DEBUG
+SILENT_MODE = FALSE
+EXT_CONFIG_CLEAR =
+CapsuleBuild = FALSE
+EXT_BUILD_FLAGS = -D CPUTARGET=CPX -D RP_PKG=WhitleyOpenBoardPkg -D SILICON_PKG=WhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=64 -D MAX_THREAD=2 -D PLATFORM_PKG=MinPlatformPkg
+MAX_SOCKET = 8
+CAPSULE_BUILD = 0
+TARGET = DEBUG
+TARGET_SHORT = D
+PERFORMANCE_BUILD = FALSE
+FSP_WRAPPER_BUILD = TRUE
+FSP_BIN_PKG = CedarIslandFspBinPkg
+FSP_PKG_NAME = CedarIslandFspPkg
+FSP_BINARY_BUILD = FALSE
+FSP_TEST_RELEASE = FALSE
+SECURE_BOOT_ENABLE = FALSE
+BIOS_INFO_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/DynamicExPcd.dsc b/Platform/Intel/WhitleyOpenBoardPkg/DynamicExPcd.dsc
new file mode 100644
index 0000000000..ebeda4e8c7
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/DynamicExPcd.dsc
@@ -0,0 +1,19 @@
+## @file
+# FSP DynamicEx PCDs
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[PcdsDynamicExDefault]
+ gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag
+ gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE
+ gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable
+ gPlatformTokenSpaceGuid.PcdBoardTypeBitmask
+ gPlatformTokenSpaceGuid.PcdImr3Enable
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/FspFlashOffsets.fdf b/Platform/Intel/WhitleyOpenBoardPkg/FspFlashOffsets.fdf
new file mode 100644
index 0000000000..a14afd693b
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/FspFlashOffsets.fdf
@@ -0,0 +1,21 @@
+## @file
+# FDF file for calculation of FSP rebase addresses for WhitleyOpenBoardPkg
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+# @todo: This file is currently only used to enable RebaseFspBinBaseAddress.py to function.
+# The FDF file for WhitleyOpenBoardPkg should be adapted to leverage FlashMapInclude.fdf
+# format found in other OpenBoardPkgs.
+
+DEFINE FLASH_BASE = 0xFF000000 #
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x00020000 # Flash addr (0xFF020000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00040000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x00060000 # Flash addr (0xFF060000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x00221000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x00281000 # Flash addr (0xFF281000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00006000 #
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
new file mode 100644
index 0000000000..8e0b674505
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
@@ -0,0 +1,781 @@
+## @file
+# Platform Package
+# Cross Platform Modules for Tiano
+#
+# @copyright
+# Copyright 2008 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = PlatformPkg
+ PACKAGE_GUID = 9A29FD32-8C72-4b25-A7C4-767F7A2838EB
+ PACKAGE_VERSION = 0.91
+
+[Includes]
+ Include
+ Include/Protocol
+
+#TODO: Move these generated temp files into include.
+ Uba/BoardInit/Dxe
+
+[Guids]
+ gBiosInfoGuid = { 0x1b453c67, 0xcb1a, 0x46ec, { 0x86, 0x4b, 0xe2, 0x24, 0xa6, 0xb7, 0xfe, 0xe8 } }
+ gClvBootTimeTestExecution = { 0x3ff7d152, 0xef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 } }
+ gUbaCurrentConfigHobGuid = { 0xe4b2025b, 0xc7db, 0x4e5d, { 0xa6, 0x5e, 0x2b, 0x25, 0x7e, 0xb1, 0x5, 0x8e } }
+
+ gCommonSystemConfigurationGuid = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 } }
+ gEfiSetupVariableGuid = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } }
+ gEfiSetupVariableDefaultGuid = { 0x8d247131, 0x385e, 0x491f, { 0xba, 0x68, 0x8d, 0xe9, 0x55, 0x30, 0xb3, 0xa6 } }
+ gEfiGlobalVariableControlGuid = { 0x99a96812, 0x4730, 0x4290, { 0x8b, 0xfe, 0x7b, 0x4e, 0x51, 0x4f, 0xf9, 0x3b } }
+ gMainPkgListGuid = { 0x6205c3a4, 0x1149, 0x491a, { 0xa6, 0xd6, 0x1e, 0x72, 0x3b, 0x87, 0x83, 0xb1 } }
+ gAdvancedPkgListGuid = { 0xc09c81cb, 0x31e9, 0x4de6, { 0xa9, 0xf9, 0x17, 0xa1, 0x44, 0x35, 0x42, 0x45 } }
+ gTpmPkgListGuid = { 0x7da45aa9, 0x6dbf, 0x4f1b, { 0xa4, 0x3e, 0x32, 0x87, 0xcb, 0xe5, 0x13, 0x51 } }
+ gSecurityPkgListGuid = { 0x3a885aae, 0x3e30, 0x42b9, { 0xa9, 0x76, 0x2f, 0x1f, 0x13, 0xbd, 0x70, 0x15 } }
+ gBootOptionsPkgListGuid = { 0x62197ef0, 0x7b7e, 0x11e2, { 0xb9, 0x2a, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 } }
+ gEfiOcDataGuid = { 0x4af92599, 0x8e76, 0x4bb4, { 0xbf, 0xd2, 0xf5, 0xa6, 0x6e, 0x30, 0x41, 0xd4 } }
+ gEfiDprRegsProgrammedGuid = { 0x4b844201, 0x6fe9, 0x41d1, { 0xb4, 0x6f, 0xdf, 0xfc, 0x34, 0xe4, 0x92, 0xa2 } }
+ gPlatformModuleTokenSpaceGuid = { 0x69d13bf0, 0xaf91, 0x4d96, { 0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0 } }
+ gCpPlatFlashTokenSpaceGuid = { 0xc9c39664, 0x96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } }
+ gPchSetupVariableGuid = { 0x4570b7f1, 0xade8, 0x4943, { 0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84 } }
+
+#
+# UBA_START
+#
+ #OEM SKU
+ gOemSkuTokenSpaceGuid = { 0x9e37d253, 0xabf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } }
+ gPlatformKtiEparamUpdateDataGuid = { 0x7bc065cf, 0xafe8, 0x4396, { 0xae, 0x9f, 0xba, 0x27, 0xdf, 0xbe, 0xcf, 0x3d } }
+ gPlatformGpioInitDataGuid = { 0x9282563e, 0xae17, 0x4e12, { 0xb1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } }
+#
+# UBA_END
+#
+ gReserveMemFlagVariableGuid = { 0xb87aa73f, 0xdcb3, 0x4533, { 0x83, 0x98, 0x6c, 0x12, 0x84, 0x27, 0x28, 0x40 } }
+ gEfiOpaSocketMapHobGuid = { 0x829d41d2, 0x6ca5, 0x485b, { 0xa1, 0xa2, 0xd1, 0xb7, 0x96, 0x27, 0xab, 0xcd } }
+ gEfiPlatformTxtPolicyDataGuid = { 0xa353290b, 0x867d, 0x4cd3, { 0xa8, 0x1b, 0x4b, 0x7e, 0x5e, 0x10, 0x0e, 0x16 } }
+ gEfiSmmPeiSmramMemoryReserveGuid = { 0x6dadf1d1, 0xd4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } }
+ gSystemBoardInfoConfigDataGuid = { 0x68B046F7, 0x15A0, 0x4778, { 0xBE, 0xA3, 0x9B, 0xA2, 0xDB, 0xD1, 0x3B, 0x82 } }
+
+ # Fce multi mode support
+ gPlatformVariableHobGuid = { 0x71e6d4bc, 0x4837, 0x45f1, { 0xa2, 0xd7, 0x3f, 0x93, 0x08, 0xb1, 0x7e, 0xd7 } }
+ gDefaultDataFileGuid = { 0x1ae42876, 0x008f, 0x4161, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 } }
+
+ gCpPlatIpmiTokenSpaceGuid = { 0xd1112ebf, 0xd82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } }
+ gEfiIpmiFormatFruGuid = { 0x3531fdc6, 0xeae, 0x4cd2, { 0xb0, 0xa6, 0x5f, 0x48, 0xa0, 0xdf, 0xe3, 0x8 } }
+ gServerCommonIpmiTokenSpaceGuid = { 0xd1112ebf, 0xd82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } }
+
+ gServerMgmtPkgListGuid = { 0x35dcfcd1, 0xc14e, 0x45e9, { 0xbe, 0xd3, 0xbb, 0x1, 0x64, 0xf8, 0x80, 0x7b } }
+
+
+ ## Include/Guid/CpPlatPkgTokenSpace.h
+ gCpPlatTokenSpaceGuid = { 0xc9c39664, 0x96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } }
+ gEfiSetupEnterGuid = { 0x71202EEE, 0x5F53, 0x40d9, { 0xAB, 0x3D, 0x9E, 0x0C, 0x26, 0xD9, 0x66, 0x57 } }
+ gEfiSetupExitGuid = { 0xD6E335EC, 0x0336, 0x4CB1, { 0x87, 0xA2, 0xDA, 0x87, 0xD7, 0xE9, 0x99, 0x40 }}
+
+ gPlatformTokenSpaceGuid = { 0x07dfa0d2, 0x2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } }
+
+[Ppis]
+#
+# UBA_START
+#
+ gEfiPeiPlatformTypeWolfPassPpiGuid = { 0xd2a92001, 0x22ad, 0x43b9, { 0xbe, 0xbc, 0x1b, 0x15, 0x21, 0x00, 0xd8, 0xcc } }
+ gEfiPeiPlatformTypeNeonCityEPRPPpiGuid = { 0xa2e5609e, 0x8c2d, 0x42e6, { 0xa2, 0xfc, 0x12, 0xbc, 0x74, 0xbd, 0x43, 0x7f } }
+ gEfiPeiPlatformTypeTennesseePassPpiGuid = { 0xf7b87a79, 0xa640, 0x4aa5, { 0x8c, 0x1e, 0x45, 0x3f, 0xb2, 0x6e, 0xf3, 0x76 } }
+ gEfiPeiPlatformTypeNeonCityEPECBPpiGuid = { 0x21877e2f, 0xf86e, 0x4e8a, { 0x9c, 0x9b, 0xd7, 0xb1, 0x52, 0xdd, 0x40, 0xd8 } }
+ gEfiPeiPlatformTypeOpalCitySTHIPpiGuid = { 0xa07b3bdf, 0xb78a, 0x41ee, { 0xa2, 0x76, 0x55, 0xc2, 0x25, 0xa0, 0x7b, 0x0b } }
+ gEfiPeiPlatformTypePurleyLBGEPDVPPpiGuid = { 0x3c234470, 0x69d3, 0x42e1, { 0xb3, 0x23, 0xc8, 0x09, 0x30, 0x0f, 0x39, 0x25 } }
+ gEfiPeiPlatformTypeCrescentCityPpiGuid = { 0x4ad920ef, 0x4d6f, 0x4915, { 0x98, 0x2a, 0xdc, 0x16, 0x67, 0x71, 0x31, 0xd5 } }
+ gEfiPeiPlatformTypeHedtEVPpiGuid = { 0x41781f4f, 0xa3cd, 0x4750, { 0x8a, 0x2c, 0x21, 0x92, 0xb4, 0xdf, 0xe5, 0x2b } }
+ gEfiPeiPlatformTypeHedtCRBPpiGuid = { 0x9bb6e29a, 0x2272, 0x426a, { 0xab, 0x77, 0x9b, 0x7f, 0xe5, 0xef, 0xea, 0x84 } }
+ gEfiPeiPlatformTypeLightningRidgeEXRPPpiGuid = { 0xaf2417f4, 0x7b7e, 0x4c2e, { 0x94, 0xbb, 0x7a, 0x33, 0x89, 0xa1, 0x57, 0xca } }
+ gEfiPeiPlatformTypeLightningRidgeEXECB1PpiGuid = { 0xf70a4116, 0xfdf6, 0x45fb, { 0x93, 0xcd, 0x84, 0xcd, 0xdd, 0x73, 0xdf, 0xd4 } }
+ gEfiPeiPlatformTypeLightningRidgeEXECB2PpiGuid = { 0x0c04b0ff, 0x227d, 0x479a, { 0x93, 0x5a, 0xf6, 0xe5, 0xa8, 0xb5, 0x19, 0x8c } }
+ gEfiPeiPlatformTypeLightningRidgeEXECB3PpiGuid = { 0x94c0203b, 0x54c9, 0x416e, { 0xa6, 0xe0, 0x47, 0xe8, 0xd4, 0x78, 0x69, 0x01 } }
+ gEfiPeiPlatformTypeLightningRidgeEXECB4PpiGuid = { 0x4284a11c, 0x18c1, 0x4c10, { 0xb2, 0xd9, 0x58, 0x6a, 0x01, 0x60, 0xa5, 0x23 } }
+ gEfiPeiPlatformTypeLightningRidgeEX8S1NPpiGuid = { 0x4f51c243, 0x7cee, 0x4144, { 0x8e, 0xed, 0x23, 0x4a, 0xc2, 0xda, 0xbd, 0x53 } }
+ gEfiPeiPlatformTypeLightningRidgeEX8S2NPpiGuid = { 0x5d9516d3, 0xbc49, 0x4337, { 0x9f, 0xc7, 0x29, 0xdf, 0x35, 0x26, 0xec, 0x87 } }
+ gEfiPeiPlatformTypeKyanitePpiGuid = { 0xb23ce2c1, 0x16a0, 0x4f69, { 0x98, 0x0a, 0x95, 0xc7, 0x72, 0x16, 0xf9, 0xa2 } }
+ gEfiPeiPlatformTypeNeonCityFPGAPpiGuid = { 0x48e796bd, 0x4ed3, 0x4755, { 0xa8, 0xca, 0x4c, 0xf4, 0x37, 0x25, 0x82, 0x41 } }
+ gEfiPeiPlatformTypeOpalCityFPGAPpiGuid = { 0xe5434b26, 0xaedf, 0x43de, { 0x89, 0x35, 0xd1, 0xc4, 0x85, 0xa9, 0x12, 0xb9 } }
+ gEfiPeiPlatformTypeWilsonCityRPPpiGuid = { 0x0629aff2, 0x4e23, 0x45c6, { 0x90, 0xc5, 0xb3, 0x21, 0x7b, 0x00, 0x09, 0x23 } }
+ gEfiPeiPlatformTypeWilsonCityModularPpiGuid = { 0x3170ea7b, 0x6784, 0x4366, { 0xb4, 0xc6, 0xfe, 0x69, 0x9f, 0x69, 0x42, 0x21 } }
+ gEfiPlatformTypeIsoscelesPeakPpiGuid = { 0xfc7b089f, 0x5395, 0x40c0, { 0x9e, 0xfb, 0xca, 0x90, 0x59, 0xe2, 0x7f, 0xea } }
+
+ gPeiIpmiTransportPpiGuid = { 0x7bf5fecc, 0xc5b5, 0x4b25, { 0x81, 0x1b, 0xb4, 0xb5, 0xb, 0x28, 0x79, 0xf7 } }
+
+#
+# UBA_END
+#
+
+ gBoardInitGuid = { 0xecc07551, 0xd64c, 0x4c07, { 0xab, 0x95, 0x94, 0x5, 0x66, 0xed, 0x31, 0xf1 } }
+ gUbaConfigDatabasePpiGuid = { 0xc1176733, 0x159f, 0x42d5, { 0xbc, 0xb9, 0x32, 0x6, 0x60, 0xb1, 0x73, 0x10 } }
+
+ gPeiSpiSoftStrapsPpiGuid = { 0x7F19E716, 0x419C, 0x4E79, { 0x8E, 0x37, 0xC2, 0xBD, 0x84, 0xEB, 0x65, 0x28 } }
+ gUpdatePcdGuid = { 0xa08e4c6b, 0xff28, 0x4fff, { 0x93, 0x56, 0x78, 0x36, 0x26, 0xc3, 0xe0, 0x38 } }
+ gPlatformVariableInitPpiGuid = { 0x9b1b911b, 0x4259, 0x4539, { 0xaf, 0x86, 0xe5, 0xf3, 0x61, 0xca, 0x09, 0x02 } }
+ gUpdateBootModePpiGuid = { 0x927186a0, 0xa13e, 0x4b53, { 0xad, 0x41, 0xad, 0xd1, 0x65, 0x6f, 0x62, 0x62 } }
+
+ gEfiPeiExStatusCodeHandlerPpiGuid = { 0x4e942617, 0xbbca, 0x4726, { 0x77, 0xb9, 0x49, 0x68, 0x85, 0xf9, 0xc4, 0xf4 } }
+
+
+[Protocols]
+ gEfiPlatformTypeProtocolGuid = { 0x171e9398, 0x269c, 0x4081, { 0x90, 0x99, 0x38, 0x44, 0xe2, 0x60, 0x46, 0x6c } }
+ gUbaConfigDatabaseProtocolGuid = { 0xe03e0d46, 0x5263, 0x4845, { 0xb0, 0xa4, 0x58, 0xd5, 0x7b, 0x31, 0x77, 0xe2 } }
+#
+# UBA_START
+#
+ gEfiPlatformTypeNeonCityEPRPProtocolGuid = { 0xc0cd2d36, 0xa81b, 0x450d, { 0xa5, 0x02, 0x37, 0x67, 0xdf, 0xa2, 0x98, 0x26 } }
+ gEfiPlatformTypeHedtCRBProtocolGuid = { 0x2c824f87, 0x0f2c, 0x45d7, { 0x81, 0xa6, 0x4f, 0x39, 0xe0, 0x42, 0xbd, 0xdf } }
+ gEfiPlatformTypeLightningRidgeEXRPProtocolGuid = { 0x1b4ae0f8, 0xed1f, 0x4fd1, { 0x9b, 0x18, 0xb0, 0x82, 0x29, 0x0f, 0x86, 0xf5 } }
+ gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid = { 0x45b59855, 0x500c, 0x443b, { 0xb5, 0x04, 0x9a, 0xb4, 0xca, 0x29, 0xbc, 0x68 } }
+ gEfiPlatformTypeWilsonCityRPProtocolGuid = { 0x8430776f, 0xbd75, 0x4fc8, { 0xa5, 0x4f, 0x7f, 0x6b, 0xf6, 0x18, 0x9c, 0x13 } }
+ gEfiPlatformTypeIsoscelesPeakProtocolGuid = { 0xcff3f211, 0x5d51, 0x4f87, { 0x94, 0xb0, 0x9b, 0x94, 0xf8, 0x4e, 0x8a, 0x48 } }
+ gEfiPlatformTypeWilsonCityModularProtocolGuid = { 0x28e862f4, 0xa4ed, 0x4acb, { 0x9a, 0x35, 0x36, 0xd0, 0x90, 0x2d, 0xf7, 0x82 } }
+
+ gEfiPlatformTypeWilsonCitySMTProtocolGuid = { 0xEE55562D, 0x4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } }
+ gEfiPlatformTypeCooperCityRPProtocolGuid = { 0x45c302e1, 0x4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } }
+
+#
+# UBA_END
+#
+
+ gEfiPciIovPlatformProtocolGuid = { 0xf3a4b484, 0x9b26, 0x4eea, { 0x90, 0xe5, 0xa2, 0x06, 0x54, 0x0c, 0xa5, 0x25 } }
+ gEfiWindowsInt10Workaround = { 0x387f555, 0x20a8, 0x4fc2, { 0xbb, 0x94, 0xcd, 0x30, 0xda, 0x1b, 0x40, 0x08 } }
+ gEfiVMDDriverProtocolGuid = { 0x5a676ae9, 0xdb23, 0x4a68, { 0xa2, 0x4d, 0xaa, 0x5f, 0xec, 0xd5, 0x74, 0x86 } }
+ gEfiHfiPcieGen3ProtocolGuid = { 0x7b59316e, 0xe9df, 0x435f, { 0x98, 0xcd, 0x57, 0x26, 0x64, 0x5b, 0xe8, 0x63 } }
+ gEfiLegacyBiosProtocolGuid = { 0xdb9a1e3d, 0x45cb, 0x4abb, { 0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d } }
+
+ gEfiIpmiSolStatusProtocolGuid = { 0xe790848e, 0xb6ab, 0x44ab, { 0x84, 0x91, 0xdc, 0xa5, 0xc, 0x39, 0x7, 0xc6 } }
+ gEfiIpmiTransportProtocolGuid = { 0x6bb945e8, 0x3743, 0x433e, { 0xb9, 0xe, 0x29, 0xb3, 0xd, 0x5d, 0xc6, 0x30 } }
+ gSmmIpmiTransportProtocolGuid = { 0x8bb070f1, 0xa8f3, 0x471d, { 0x86, 0x16, 0x77, 0x4b, 0xa3, 0xf4, 0x30, 0xa0 } }
+ gEfiIpmiBootGuid = { 0x5c9b75ec, 0x8ec7, 0x45f2, { 0x8f, 0x8f, 0xc1, 0xd8, 0x8f, 0x3b, 0x93, 0x45 } }
+ gEfiGenericIpmiDriverInstalledGuid = { 0x7cdad61a, 0x3df8, 0x4425, { 0x96, 0x8c, 0x66, 0x28, 0xc8, 0x35, 0xff, 0xce } }
+
+
+[PcdsFixedAtBuild]
+
+#SKX_TODO: add a new GUID, and replace the 'gPlatformTokenSpaceGuid' used here to it, or move these values to the SocketPkg where the GUID is defined
+# Using a GUID defined in another .DEC file is a violation of the UEFI packaging standards.
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashBase|0x00000000 |UINT32|0x3000000E
+ gCpPlatFlashTokenSpaceGuid.PcdFlashSize|0x00000000 |UINT32|0x3000000F
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase|0x00000000|UINT32|0x3000001A
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize|0x00000000|UINT32|0x3000001B
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize|0x00000000|UINT32|0x3000001C
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase|0x00000000|UINT32|0x3000001D
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize|0x00000000|UINT32|0x3000001E
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase|0x00000000|UINT32|0x3000001F
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize|0x00000000|UINT32|0x30000020
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase|0x00000000|UINT32|0x30000021
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|0x0000000|UINT32|0x30000027
+
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize|0x0000000|UINT32|0x30000001
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|0x0000000|UINT32|0x30000004
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|0x0000000|UINT32|0x30000006
+ gPlatformModuleTokenSpaceGuid.PcdFlashFreeSpaceOffset|0x0000000|UINT32|0x30000008
+
+ gPlatformTokenSpaceGuid.PcdSupportLegacyStack|TRUE|BOOLEAN|0x30000030
+ gPlatformTokenSpaceGuid.PcdMaxOptionRomNumber|0x4|UINT8|0x30000031
+
+ gPlatformTokenSpaceGuid.PcdCmosDebugPrintLevelReg|0x4C|UINT8|0x30000032
+
+ # Choose the default serial debug message level when CMOS is bad; in the later BIOS phase, the setup default is applied
+ # 0 - Disable; 1 - Minimum; 2 - Normal; 3 - Max
+ gPlatformTokenSpaceGuid.PcdSerialDbgLvlAtBadCmos|0x1|UINT8|0x30000033
+ gPlatformTokenSpaceGuid.PcdWilsonPointSvidVrP1V8|0x05|UINT8|0x30000000 #BIT4 => SVID BUS 0, BIT3-BIT0 => VR ADDRESS
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8|0x15|UINT8|0x30000002
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna|0x16|UINT8|0x30000003
+
+ # PCD for failsafe variable ffs in other FV rather than bb1
+ # by default, FCE will insert into SECPEI, and you don't need to set these two PCD if bb1(secpei)is used
+ gPlatformTokenSpaceGuid.PcdFailSafeVarFfsSize|0|UINT32|0x30000034
+ gPlatformTokenSpaceGuid.PcdFailSafeVarFvBase|0|UINT32|0x30000035
+
+ gPlatformTokenSpaceGuid.PcdSetupVariableGuid|{ 0x43,0xd6,0x87,0xec,0xa4, 0xeb, 0xb5,0x4b, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9}|VOID*|0x30000036
+
+ #
+ # These need to move to MinPlatformPkg.dec
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize|0|UINT32|0xF00000A9
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase|0|UINT32|0xF00000AA
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|0|UINT32|0xF00000AB
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize|0|UINT32|0xF00000AC
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase|0|UINT32|0xF00000AD
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|0|UINT32|0xF00000AE
+
+ #IIO configuration data for socket 3 will be used for sockets 4..7
+ gPlatformTokenSpaceGuid.PcdSocketCopy|FALSE|BOOLEAN|0xF00000AF
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionSize|0x01000000|UINT32|0xF00000B0
+ gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionBase|0xFF900000|UINT32|0xF00000B1
+
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+ gPlatformTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 0xC5, 0x15, 0x05, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }|VOID*|0x40000004
+ ## Specify memory size with page number for a pre-allocated reserved memory to be used
+ # by PEI in S3 phase. The default size 32K. When changing the value make sure the memory size
+ # is large enough to meet PEI requirement in the S3 phase.
+ # @Prompt Reserved S3 Boot ACPI Memory Size
+ gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x8000|UINT32|0x90010039
+ gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012
+ gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013
+ gPlatformModuleTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015
+ gPlatformModuleTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016
+ gPlatformModuleTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0x90000017
+ gPlatformModuleTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90000018
+
+
+ gPlatformModuleTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90000021
+ gPlatformModuleTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000022
+ gPlatformModuleTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90000023
+ gPlatformModuleTokenSpaceGuid.PcdHpetTimerBlockId|0x8086A201|UINT32|0x90000024
+
+ gPlatformModuleTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x90000025
+ gPlatformModuleTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x90000026
+ gPlatformModuleTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027
+ gPlatformModuleTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x9000000B
+ gPlatformModuleTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x9000000D
+ gPlatformModuleTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014
+ gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006
+
+[PcdsDynamicEx]
+
+#
+# PAL
+#
+ gPlatformTokenSpaceGuid.PcdOemSkuPcieSlotOpromBitMap|0xFF|UINT32|0x00000008
+
+#SKX_TODO: gPlatformTokenSpaceGuid are not correct GUIDs to use here, use local GUID...
+ gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|FALSE|BOOLEAN|0x00000048
+
+ ## This value is used to save memory address of MRC data structure.
+ gPlatformTokenSpaceGuid.PcdBoardTypeBitmask|0x00000000|UINT32|0x30000041
+
+#
+# IMR0 programming values
+#
+ gPlatformTokenSpaceGuid.PcdImr0Enable|FALSE|BOOLEAN|0xA5000000
+ gPlatformTokenSpaceGuid.PcdImr0Base|0x0|UINT64|0xA5000001
+ gPlatformTokenSpaceGuid.PcdImr0Mask|0x0|UINT64|0xA5000002
+ gPlatformTokenSpaceGuid.PcdImr0Rac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000003
+ gPlatformTokenSpaceGuid.PcdImr0Wac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000004
+
+#
+# IMR3 programming values
+#
+ gPlatformTokenSpaceGuid.PcdImr3Enable|FALSE|BOOLEAN|0xA5000022
+
+#
+# Server common Hot Key binding
+#
+ # EFI Scan codes
+ # SCAN_F2 0x000C
+ # SCAN_F6 0x0010
+ # SCAN_F7 0x0011
+ gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x00|UINT16|0x00000009
+ gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x00|UINT16|0x0000000A
+
+
+ gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }|VOID*|0x0000000B
+
+#Indicate whether to perform LT Config lock
+# The PCD can be set to false when there is the debug request
+# TRUE - Force the LT config lock
+# FALSE - Allow the LT config unlock for debug
+ gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE|BOOLEAN|0x3000000e
+
+#Indicate whether LTSX enabled
+# TRUE - Intel (R) TXT feature enabled on the platform
+# FALSE - Disable Intel(R) TXT feature on the platform
+ gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable | TRUE|BOOLEAN|0x3000000f
+
+[PcdsFeatureFlag]
+ gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE|BOOLEAN|0x00000020
+
+ ##
+ ## High Speed UART
+ ##
+ gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE|BOOLEAN|0x0000002C
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
+ ## MemoryCheck value for checking memory before boot OS.
+ # To save the boot performance, the default MemoryCheck is set to 0.
+ gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|0|UINT8|0x40000005
+
+
+ ## following PCDs should remove if CORE accept the fix
+ gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x0|UINT32|4
+
+ ## Vendor ID and Device ID of device producing onboard video
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0|UINT16|0x00000013
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0|UINT16|0x00000014
+ gPlatformModuleTokenSpaceGuid.PcdPlatformMemoryCheckLevel|0|UINT32|0x30000009
+ ## This PCD is to control which device is the potential trusted console input device.<BR><BR>
+ # For example:<BR>
+ # USB Short Form: UsbHID(0xFFFF,0xFFFF,0x1,0x1)<BR>
+ # //Header VendorId ProductId Class SubClass Protocol<BR>
+ # {0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01,<BR>
+ # //Header<BR>
+ # 0x7F, 0xFF, 0x04, 0x00}<BR>
+ gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x300000A
+
+ ## This PCD is to control which device is the potential trusted console output device.<BR><BR>
+ # For example:<BR>
+ # Integrated Graphic: PciRoot(0x0)/Pci(0x2,0x0)<BR>
+ # //Header HID UID<BR>
+ # {0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00,<BR>
+ # //Header Func Dev<BR>
+ # 0x01, 0x01, 0x06, 0x00, 0x00, 0x02,
+ # //Header<BR>
+ # 0x7F, 0xFF, 0x04, 0x00}<BR>
+ gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x300000C
+
+
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x1800|UINT16|0x00010035
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0x0000|UINT16|0x00010036
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x1804|UINT16|0x0001037
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0x0000|UINT16|0x00010038
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x1850|UINT16|0x00010039
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x1808|UINT16|0x0001003A
+ gPlatformModuleTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x1880|UINT16|0x0001003B
+ gPlatformModuleTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0x0000|UINT16|0x0001003C
+
+#
+# UBA_START
+#
+[PcdsDynamicEx]
+
+#
+#Board Definitions
+#
+#Integer for BoardID, must match the SKU number and be unique.
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardID|0x0|UINT16|0x00000000
+#Integer for BoardFamily, must be unique
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily|0x0|UINT16|0x00000001
+# Zero terminated unicode string to ID family
+ gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName|L"DEFAULT "|VOID*|0x0000002
+# Zero terminated unicode string to Board Name
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardName|L"DEFAULT "|VOID*|0x00000003
+# Number of Sockets on Board.
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount|0x0|UINT32|0x00000004
+
+# Number of DIMM slots per channel for each Socket
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel|0x0|UINT32|0x00000005
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel|0x0|UINT32|0x00000006
+ gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout|FALSE|BOOLEAN|0x00000007
+ gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID|0x0|UINT16|0x00000008
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmSize|0x100|UINT32|0x00000009
+
+#
+# USB
+#
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00|0x0|UINT16|0x00000010
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01|0x0|UINT16|0x00000011
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02|0x0|UINT16|0x00000012
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03|0x0|UINT16|0x00000013
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04|0x0|UINT16|0x00000014
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05|0x0|UINT16|0x00000015
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06|0x0|UINT16|0x00000016
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07|0x0|UINT16|0x00000017
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08|0x0|UINT16|0x00000018
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09|0x0|UINT16|0x00000019
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10|0x0|UINT16|0x0000001A
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11|0x0|UINT16|0x0000001B
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12|0x0|UINT16|0x0000001C
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13|0x0|UINT16|0x0000001D
+
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00|0x0|UINT16|0x00000020
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01|0x0|UINT16|0x00000021
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02|0x0|UINT16|0x00000022
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03|0x0|UINT16|0x00000023
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04|0x0|UINT16|0x00000024
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05|0x0|UINT16|0x00000025
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06|0x0|UINT16|0x00000026
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07|0x0|UINT16|0x00000027
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08|0x0|UINT16|0x00000028
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09|0x0|UINT16|0x00000029
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10|0x0|UINT16|0x0000002A
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11|0x0|UINT16|0x0000002B
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12|0x0|UINT16|0x0000002C
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13|0x0|UINT16|0x0000002D
+
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00|0x0|UINT16|0x00000100
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01|0x0|UINT16|0x00000101
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02|0x0|UINT16|0x00000102
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03|0x0|UINT16|0x00000103
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04|0x0|UINT16|0x00000104
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05|0x0|UINT16|0x00000105
+
+#
+# ACPI items
+#
+# Acpi Name, MUST be 8 chars long
+ gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName|"DEFAULT "|VOID*|0x00000030
+ gOemSkuTokenSpaceGuid.PcdOemTableIdXhci|"DEFAULT "|VOID*|0x00000031
+#
+# Misc.
+#
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag|0x0|UINT8|0x00000039
+ gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed|0x0|UINT16|0x00000040
+
+#
+# GPIO
+#
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL|0xFF3DB93D|UINT32|0x00000050
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL|0x0382F03F|UINT32|0x00000051
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL|0xFFFFF30F|UINT32|0x00000052
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL|0x91E3EFFF|UINT32|0x00000053
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL|0xFFFD0FF3|UINT32|0x00000054
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL|0xFFFFFDF0|UINT32|0x00000055
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL|0x661C1000|UINT32|0x00000056
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL|0x0002F004|UINT32|0x00000057
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL|0x0000020D|UINT32|0x00000058
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL|0x00000000|UINT32|0x00000059
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL|0x00000000|UINT32|0x0000005a
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE|0x00000000|UINT32|0x0000005c
+
+#
+# SATA registers
+#
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32|0x99990000|UINT32|0x0000005b
+
+#
+# Clock generator settings
+#
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00|0xFF|UINT8|0x00000060
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01|0x9E|UINT8|0x00000061
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02|0x3F|UINT8|0x00000062
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03|0x00|UINT8|0x00000063
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04|0x00|UINT8|0x00000064
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05|0x0F|UINT8|0x00000065
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06|0x08|UINT8|0x00000066
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07|0x11|UINT8|0x00000067
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08|0x0A|UINT8|0x00000068
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09|0x17|UINT8|0x00000069
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10|0xFF|UINT8|0x0000006a
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11|0xFE|UINT8|0x0000006b
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGeneratorAddress|0xD2|UINT8|0x0000006c
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName|L"DEFAULT "|VOID*|0x00000201
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize|0x0|UINT32|0x00000202
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag|0x0|UINT32|0x00000203
+
+#
+# If PcdOemSkuAssertPostGPIO value is 0xFFFFFFFF, current platform don't set related GPIO.
+#
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO|0x01010014|UINT32|0x00000204
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue|0x0|UINT32|0x00000205
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber|0xFF|UINT8|0x00000206
+ gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0xFF|UINT8|0x00000207
+#
+# UBA_END
+#
+
+ gCpPlatIpmiTokenSpaceGuid.PcdIpmiIoBaseAddress|0xCA2|UINT16|0x10000022
+ gCpPlatIpmiTokenSpaceGuid.PcdIpmiSmmIoBaseAddress|0xCA4|UINT16|0x10000023
+ gCpPlatIpmiTokenSpaceGuid.PcdSioMailboxBaseAddress|0x600|UINT32|0x10000021
+ gCpPlatIpmiTokenSpaceGuid.PcdFRB2EnabledFlag|TRUE|BOOLEAN|0x10000030
+ gCpPlatIpmiTokenSpaceGuid.PcdIpmiBmcReadyDelayTimer|0|UINT8|0x00000208
+
+
+## This PCD replaces the original one gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState
+ gPlatformModuleTokenSpaceGuid.PcdBootState|TRUE|BOOLEAN|0x300000AC
+ gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x00000208
+
+[PcdsDynamicEx]
+ gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|FALSE|BOOLEAN|0x10000026
+ gCpPlatTokenSpaceGuid.PcdUefiOptimizedBootEx|FALSE|BOOLEAN|0x10000024
+
+[PcdsFixedAtBuild]
+#
+# Flash map related PCD.
+#
+# Note: most values here are overridden in the .fdf file
+#
+#
+# Note: FlashNv PCD naming conventions are as follows:
+#
+# PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
+# PcdFlash*Size is a hex count of the length of the FD or FV
+# All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
+#
+# Also all values will have a PCD assigned so that they can be used in the system, and
+# the FlashMap edit tool can be used to change the values here, without effecting the code.
+# This requires all code to only use the PCD tokens to recover the values.
+#
+
+
+
+# PCD's that are for the whole SPI part
+
+
+#Block size of SPI
+gCpPlatFlashTokenSpaceGuid.PcdFlashBlockSize |0x00010000 |UINT32|0x50000102
+
+
+#AJW rename this to be more in keeping with the function
+gCpPlatFlashTokenSpaceGuid.PcdFlashAreaBase |0xfff00000 |UINT32|0x50000105
+
+
+
+# for PeiSec FD
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize |0x00100000 |UINT32|0x50000221
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase |0x00000000 |UINT32|0x50000222
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase |0x00000000 |UINT32|0x50000260
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize |0x00040000 |UINT32|0x50000261
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase |0x00000000 |UINT32|0x50000211
+gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize |0x00100000 |UINT32|0x50000212
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize |0x00100000 |UINT32|0x50000233
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase |0x00000000 |UINT32|0x50000234
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset |0x00000000 |UINT32|0x50000235
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize |0x00100000 |UINT32|0x50000241
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase |0x00000000 |UINT32|0x50000242
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize |0x00100000 |UINT32|0x50000251
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase |0x00000000 |UINT32|0x50000252
+
+
+# for Main FD
+
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase |0xfff00000 |UINT32|0x50000300
+gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize |0x00400000 |UINT32|0x50000301
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainSize |0x00200000 |UINT32|0x50000311
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainBase |0xFF820000 |UINT32|0x50000312
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize |0x00200000 |UINT32|0x50000341
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase |0xFF820000 |UINT32|0x50000342
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset |0xFF820000 |UINT32|0x50000343
+
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize |0x00200000 |UINT32|0x50000351
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase |0xFF820000 |UINT32|0x50000352
+
+## This PCD specifies the size of the physical device containing the BIOS, SMBIOS will use it.
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionBase |0xFF800000 |UINT32|0x50000001
+gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionSize |0x00000000 |UINT32|0x50000002
+
+[PcdsFeatureFlag.common]
+
+##
+## Those PCDs are used to control build process.
+##
+
+ #
+ # SV Tools
+ #
+ gPlatformFeatureTokenSpaceGuid.PcdXmlCliEnable|TRUE|BOOLEAN|0xE0000000
+ gPlatformFeatureTokenSpaceGuid.PcdSvBiosEnable|TRUE|BOOLEAN|0xE000002E
+ #
+ #
+ #
+
+[PcdsDynamicEx]
+ ### Sample implementation...No real data. Use this PCD to override a platform with Interposer ###
+ gPlatformTokenSpaceGuid.PcdMemInterposerMap|{0}|INTERPOSER_MAP|0x80000015 {
+ <HeaderFiles>
+ Guid/PlatformInfo.h
+ <Packages>
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ }
+ # Interposer A MC 0 mapped to original MC1
+ # Enum values for Interposer
+ # Interposer A => 1
+ # Interposer B => 2
+ # Interposer Unknown => 0
+ gPlatformTokenSpaceGuid.PcdMemInterposerMap.Interposer[1].MappedMcId[0] |1
+
+### Sample implementation...No real data. Use this PCD to override a platform with Interposer ###
+
+[Guids]
+ gStructPcdTokenSpaceGuid = {0x3f1406f4, 0x2b, 0x487a, {0x8b, 0x69, 0x74, 0x29, 0x1b, 0x36, 0x16, 0xf4}}
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
+gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig|{0}|EMULATION_DFX_CONFIGURATION|0XFCD0000C{
+ <HeaderFiles>
+ Include/Guid/EmulationDfxVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|{0}|FPGA_SOCKET_CONFIGURATION|0XFCD00010{
+ <HeaderFiles>
+ Include/Guid/FpgaSocketVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdIeRcConfiguration|{0}|IE_RC_CONFIGURATION|0XFCD00004{
+ <HeaderFiles>
+ Include/Guid/IeRcVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration|{0}|ME_RC_CONFIGURATION|0XFCD0000B{
+ <HeaderFiles>
+ Include/Guid/MeRcVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig|{0}|MEM_BOOT_HEALTH_CONFIG|0XFCD00002{
+ <HeaderFiles>
+ Include/Guid/MemBootHealthGuid.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdPchSetup|{0}|PCH_SETUP|0XFCD00007{
+ <HeaderFiles>
+ Include/PchSetupVariableLbg.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSetup|{0}|SYSTEM_CONFIGURATION|0XFCD0000F{
+ <HeaderFiles>
+ Include/Guid/SetupVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|{0}|SOCKET_COMMONRC_CONFIGURATION|0XFCD00001{
+ <HeaderFiles>
+ Include/Guid/SocketCommonRcVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig|{0}|SOCKET_IIO_CONFIGURATION|0XFCD00006{
+ <HeaderFiles>
+ Include/Guid/SocketIioVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|{0}|SOCKET_MEMORY_CONFIGURATION|0XFCD0000D{
+ <HeaderFiles>
+ Include/Guid/SocketMemoryVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|{0}|SOCKET_MP_LINK_CONFIGURATION|0XFCD00008{
+ <HeaderFiles>
+ Include/Guid/SocketMpLinkVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|{0}|SOCKET_POWERMANAGEMENT_CONFIGURATION|0XFCD00005{
+ <HeaderFiles>
+ Include/Guid/SocketPowermanagementVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|{0}|SOCKET_PROCESSORCORE_CONFIGURATION|0XFCD00003{
+ <HeaderFiles>
+ Include/Guid/SocketProcessorCoreVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSvConfiguration|{0}|SV_CONFIGURATION|0XFCD00009{
+ <HeaderFiles>
+ Include/Guid/SetupVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdTCG2_CONFIGURATION|{0}|TCG2_CONFIGURATION|0XFCD0000A{
+ <HeaderFiles>
+ Include/Tcg2ConfigNvData.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdTCG2_VERSION|{0}|TCG2_VERSION|0XFCD0000E{
+ <HeaderFiles>
+ Include/Tcg2ConfigNvData.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ SecurityPkg/SecurityPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+}
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
+ gOemSkuTokenSpaceGuid.PcdTurboPowerLimitLock|0x01|UINT8|0x00000209
+ gOemSkuTokenSpaceGuid.PcdNumberOfCoresToDisable|0x0|UINT16|0x0000020A
+
+[LibraryClasses]
+ ServerManagementTimeStampLib|Include/Library/ServerManagementTimeStampLib.inf
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
new file mode 100644
index 0000000000..41dc55a14d
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
@@ -0,0 +1,931 @@
+## @file
+# X64 Platform with 64-bit DXE.
+#
+# @copyright
+# Copyright 2008 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = $(RP_PKG)
+ PLATFORM_GUID = D7EAF54D-C9B9-4075-89F0-71943DBCFA61
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(RP_PKG)
+ SUPPORTED_ARCHITECTURES = IA32|X64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08
+ FLASH_DEFINITION = $(RP_PKG)/PlatformPkg.fdf
+ PLATFORM_SI_PACKAGE = ClientOneSiliconPkg
+ DEFINE PLATFORM_SI_BIN_PACKAGE = WhitleySiliconBinPkg
+ PEI_ARCH = IA32
+ DXE_ARCH = X64
+
+!if $(CPUTARGET) == "CPX"
+ DEFINE FSP_BIN_PKG = CedarIslandFspBinPkg
+ DEFINE IIO_INSTANCE = Skx
+!elseif $(CPUTARGET) == "ICX"
+ DEFINE FSP_BIN_PKG = WhitleyFspBinPkg
+ DEFINE IIO_INSTANCE = Icx
+!else
+ DEFINE IIO_INSTANCE = UnknownCpu
+!endif
+
+ #
+ # Platform On/Off features are defined here
+ #
+ !include $(RP_PKG)/PlatformPkgConfig.dsc
+
+ #
+ # MRC common configuration options defined here
+ #
+ !include $(SILICON_PKG)/MrcCommonConfig.dsc
+
+ !include $(FSP_BIN_PKG)/DynamicExPcd.dsc
+ !include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc
+ !include $(RP_PKG)/DynamicExPcd.dsc
+
+ !include $(RP_PKG)/Uba/UbaCommon.dsc
+ !include $(RP_PKG)/Uba/UbaRpBoards.dsc
+
+ !include $(RP_PKG)/Include/Dsc/EnablePerformanceMonitoringInfrastructure.dsc
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+# Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
+
+[DefaultStores]
+ 0|STANDARD
+ 1|MANUFACTURING
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag]
+ #
+ # MinPlatform control flags
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE
+
+ # don't degrade 64bit MMIO space to 32-bit
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE
+
+ # Server doesn't support capsule update on Reset.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+
+ gEfiCpRcPkgTokenSpaceGuid.Reserved15|TRUE
+
+!if ($(CPUTARGET) == "ICX")
+ gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|FALSE
+!endif # $(CPUTARGET) == "ICX"
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE
+ gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|TRUE
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE
+
+ ## Uncomment for better boot performance
+# gPerfOptTokenSpaceGuid.PcdPreUefiLegacyEnable|FALSE
+# gPerfOptTokenSpaceGuid.PcdLocalVideoEnable|FALSE
+
+ gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE
+
+ ## This PCD specified whether ACPI SDT protocol is installed.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+ ## This PCD specifies whether FPGA routine will be active
+ gSocketPkgFpgaGuid.PcdSktFpgaActive|TRUE
+
+!if $(CPU_SKX_ONLY_SUPPORT) == TRUE
+ gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|TRUE
+!endif
+
+ ## This PCD specifies whether or not to enable the High Speed UART
+ gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
+
+[PcdsFixedAtBuild]
+ gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption|2
+
+ ## MinPlatform Boot Stage Selector
+ # Stage 1 - enable debug (system deadloop after debug init)
+ # Stage 2 - mem init (system deadloop after mem init)
+ # Stage 3 - boot to shell only
+ # Stage 4 - boot to OS
+ # Stage 5 - boot to OS with security boot enabled
+ # Stage 6 - boot with advanced features enabled
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6
+
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # Enable asserts, prints, code, clear memory, and deadloops on asserts.
+ gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # Built in messages: Error, MTRR, info, load, warn, init
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # This is set to INT3 (0x2) for Simics source level debugging
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4449204C45544E49 # "INTEL ID"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x2100000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
+
+ gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
+ gCpuPkgTokenSpaceGuid.PcdPlatformType|2
+ gCpuPkgTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000
+
+ #PcdCpuMicrocodePatchRegionSize = PcdFlashNvStorageMicrocodeSize - (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x1FFF70
+
+ #
+ # This controls the NEM code region cached during SEC
+ # It usually isn't necessary to match exactly the FV layout in the FDF file.
+ # It is a performance optimization to have it match the flash region exactly
+ # as then no extra reads are done to load unused flash into cache.
+ #
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0xFFC00000
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x00400000
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000
+
+!if ($(FSP_MODE) == 0)
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000
+!endif
+ gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
+
+ #
+ # These will be initialized during build
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x00000000
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase|0x00000000
+
+ ## Specifies delay value in microseconds after sending out an INIT IPI.
+ # @Prompt Configure delay value after send an INIT IPI
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10
+ ## Specifies max supported number of Logical Processors.
+ # @Prompt Configure max supported number of Logical Processorss
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000
+
+ gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x2
+
+ gPlatformTokenSpaceGuid.PcdUboDev|0x08
+ gPlatformTokenSpaceGuid.PcdUboFunc|0x02
+ gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC
+
+ gCpuPkgTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
+ gPlatformTokenSpaceGuid.PcdSupportLegacyStack|FALSE
+
+ ## Defines the ACPI register set base address.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Timer IO Port Address
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500
+
+ ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # @Prompt ACPI Hardware PCI Bus Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00
+
+ ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Device Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F
+
+ ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Function Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02
+
+ ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044
+
+ ## Defines the bit mask that must be set to enable the APIC hardware register BAR.
+ # @Prompt ACPI Hardware PCI Bar Enable BitMask
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80
+
+ ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Bar Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040
+
+ ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.
+ # @Prompt Offset to 32-bit Timer register in ACPI BAR
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008
+
+!if $(CPUTARGET) == "ICX"
+ #
+ # ACPI PCD custom override
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013
+!endif
+
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET)
+ gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
+
+ # Enable DDRT scheduler debug features for power on
+ gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault|TRUE
+
+ # Disable Fast Warm Boot for Whitley Openboard Package
+ gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault|FALSE
+
+!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
+ gCpuUncoreTokenSpaceGuid.PcdWaSerializationEn|FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable|FALSE
+!endif
+
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x74
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x75
+
+ #
+ # PlatformInitPreMem
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA30
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x100
+
+ gEfiCpRcPkgTokenSpaceGuid.PcdReserved15|0
+
+ !include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc
+
+[PcdsFixedAtBuild.IA32]
+!if ($(FSP_MODE) == 0)
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0
+!endif
+
+[PcdsFixedAtBuild.X64]
+ # Change PcdBootManagerMenuFile to UiApp
+ ##
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+ gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0xC00000
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
+
+ #
+ # AcpiPlatform
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5
+ gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08
+
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|FALSE
+
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{ 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04, 0x00}
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{ 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}
+ gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x0, 0x0, 0x1F, 0x0}
+ gBoardModulePkgTokenSpaceGuid.PcdUart1Enable|0x01
+
+[PcdsPatchableInModule]
+ #
+ # These debug options are patcheable so that they can be manipulated during debug (if memory is updateable)
+ #
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 # Enable status codes for debug, progress, and errors
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 # Displayed messages: Error, Info, warn
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0
+
+!if $(PREMEM_PAGE_ALLOC_SUPPORT) == FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0x130000
+!endif
+
+[PcdsDynamicExDefault.IA32]
+!if ($(FSP_MODE) == 0)
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000
+!endif
+
+
+[PcdsDynamicExHii]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|L"1GPageTable"|gEfiGenericVariableGuid|0x0|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0 # Variable: L"Timeout"
+ gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|L"MemoryCheck"|gPlatformTokenSpaceGuid|0x0|0
+ gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|L"UefiOptimizedBoot"|gCpPlatTokenSpaceGuid|0x0|TRUE
+ gPlatformModuleTokenSpaceGuid.PcdBootState|L"BootState"|gEfiGenericVariableGuid|0x0|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+ gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|L"BootDeviceScratchPad"|gEfiGenericVariableGuid|0x0|FALSE
+
+[PcdsDynamicExDefault]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmPhysicalPresence|TRUE
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmAutoDetection|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE
+ gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable|FALSE
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE
+
+ gSiPkgTokenSpaceGuid.PcdWakeOnRTCS5|FALSE
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeHour|0
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeMinute|0
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeSecond|0
+
+ #Platform should change it to by code
+ gSiPkgTokenSpaceGuid.PcdPchSataInitReg78Data|0xAAAA0000
+ gSiPkgTokenSpaceGuid.PcdPchSataInitReg88Data|0xAA33AA22
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE
+
+ #
+ # CPU features related PCDs.
+ #
+ gCpuPkgTokenSpaceGuid.PcdCpuEnergyPolicy
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle
+ gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x01
+
+ ## Put fTPM guid here: e.g. { 0xf9c6a62f, 0xc60f, 0x4b44, { 0xa6, 0x29, 0xed, 0x3d, 0x40, 0xae, 0xfa, 0x5f } }
+ ## TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67, 0x1b, 0x90, 0xcc } }
+ ## TPM2.0Dtpm { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17 } }
+
+ #TPM2.0#
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|0
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|0
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE
+
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0x102b
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0x0522
+
+ gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x000C
+ gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x0011
+ gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0
+
+[PcdsDynamicExDefault.X64]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
+
+ #
+ # Set video to 1024x768 resolution
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768
+
+[PcdsDynamicExDefault]
+
+!if $(CPUTARGET) == "CPX"
+ !include $(RP_PKG)/StructurePcdCpx.dsc
+!else
+ !include $(RP_PKG)/StructurePcd.dsc
+!endif
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
+!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
+!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
+
+[LibraryClasses]
+
+ #
+ # Simics source level debugging requires the non-null version of PeCoffExtraActionLib
+ #
+!if $(TARGET) == "DEBUG"
+ PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
+!else
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+!endif
+
+ #
+ # Basic
+ #
+
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+ #
+ # Framework
+ #
+ S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
+ FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
+
+ SiliconPolicyInitLib|WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.inf
+!if ($(FSP_MODE) == 0)
+ SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.inf
+!else
+ SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf
+!endif
+
+ SetupLib|WhitleySiliconPkg/Library/SetupLib/SetupLib.inf
+
+ #
+ # ToDo: Can we use BaseAcpiTimerLib from MinPlatform?
+ #
+ TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf
+
+ MultiPlatSupportLib|$(RP_PKG)/Library/MultiPlatSupportLib/MultiPlatSupportLib.inf
+ ReadFfsLib|$(RP_PKG)/Library/ReadFfsLib/ReadFfsLib.inf
+ PlatformSetupVariableSyncLib|$(RP_PKG)/Library/PlatformSetupVariableSyncLibNull/PlatformSetupVariableSyncLibNull.inf
+ PlatformVariableHookLib |$(RP_PKG)/Library/PlatformVariableHookLibNull/PlatformVariableHookLibNull.inf
+
+ PlatformBootManagerLib|$(PLATFORM_PKG)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
+ SerialPortLib|$(RP_PKG)/Library/SerialPortLib/SerialPortLib.inf
+ PlatformHooksLib|$(RP_PKG)/Library/PlatformHooksLib/PlatformHooksLib.inf
+
+ CmosAccessLib|BoardModulePkg/Library/CmosAccessLib/CmosAccessLib.inf
+ PlatformCmosAccessLib|$(RP_PKG)/Library/PlatformCmosAccessLib/PlatformCmosAccessLib.inf
+ SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
+ TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf
+
+ #
+ # MinPlatform uses port 80, we don't want to assume HW
+ #
+ PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
+
+ TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull.inf
+ Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibNull.inf
+ AslUpdateLib|$(PLATFORM_PKG)/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
+ PciSegmentInfoLib|$(PLATFORM_PKG)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
+ PlatformOpromPolicyLib|$(RP_PKG)/Library/PlatformOpromPolicyLibNull/PlatformOpromPolicyLibNull.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
+
+[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+!if ($(FSP_MODE) == 0)
+ FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
+ FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf
+ FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
+ FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+!endif
+ FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
+ FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
+ FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
+
+[LibraryClasses.Common.SEC]
+ #
+ # SEC phase
+ #
+ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+
+[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+ #
+ # ToDo: Can we remove
+ #
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+
+
+ PeiPlatformHookLib|$(RP_PKG)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
+ PlatformClocksLib|$(RP_PKG)/Library/PlatformClocksLib/Pei/PlatformClocksLib.inf
+
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf
+
+ ReportFvLib|$(RP_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf
+
+[LibraryClasses.Common.PEIM]
+ #
+ # Library instance consumed by MinPlatformPkg PlatformInit modules.
+ #
+ ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+ SetCacheMtrrLib|$(RP_PKG)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
+
+[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, LibraryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION]
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+
+ Tcg2PhysicalPresenceLib|$(RP_PKG)/Library/Tcg2PhysicalPresenceLibNull/DxeTcg2PhysicalPresenceLib.inf
+ TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf
+
+ BiosIdLib|BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.inf
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+
+ TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+
+ Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm.inf
+
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.inf
+ BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf
+ BoardBootManagerLib|MinPlatformPkg/Bds/Library/BoardBootManagerLibNull/BoardBootManagerLibNull.inf
+
+ CompressDxeLib|MinPlatformPkg/Library/CompressLib/CompressLib.inf
+
+[LibraryClasses.Common.DXE_SMM_DRIVER]
+ SpiFlashCommonLib|$(RP_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
+
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.inf
+ MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf
+
+[LibraryClasses.Common.SMM_CORE]
+ S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
+
+[LibraryClasses.Common]
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+
+[Components.IA32]
+ !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ #
+ # Beware of circular dependencies on PCD if you want to use another DebugLib instance.
+ #
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf # Include FSP DynamicEx PCD
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateSilicon.inf # Include FvLateSilicon DynamicEx PCD
+ }
+ $(RP_PKG)/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
+ $(RP_PKG)/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
+ $(RP_PKG)/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
+
+ $(RP_PKG)/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
+
+ $(RP_PKG)/Platform/Pei/PlatformInfo/PlatformInfo.inf
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ <LibraryClasses>
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitPreMemLib.inf
+ }
+ $(PLATFORM_PKG)/PlatformInit/ReportFv/ReportFvPei.inf
+
+ $(PLATFORM_PKG)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf{
+ <LibraryClasses>
+ SiliconWorkaroundLib|WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.inf
+ }
+ $(RP_PKG)/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
+ <LibraryClasses>
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
+ }
+
+!if ($(FSP_MODE) == 0)
+ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+ IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+ $(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
+!endif
+
+ $(RP_PKG)/BiosInfo/BiosInfo.inf
+
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+
+ UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf {
+ <LibraryClasses>
+ !if $(PERFORMANCE_ENABLE) == TRUE
+ TimerLib|UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf
+ !endif
+ }
+
+[Components.X64]
+ !include WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
+
+ $(RP_PKG)/Platform/Dxe/PlatformType/PlatformType.inf
+
+ MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf
+
+ MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
+
+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
+
+ $(RP_PKG)/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
+ UefiCpuPkg/CpuDxe/CpuDxe.inf
+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+ $(RP_PKG)/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
+ $(PLATFORM_PKG)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+ $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+
+ $(PLATFORM_PKG)/Acpi/AcpiTables/AcpiPlatform.inf {
+ <LibraryClasses>
+ BoardAcpiTableLib|$(RP_PKG)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
+ }
+
+ $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf {
+ <LibraryClasses>
+ BoardAcpiEnableLib|$(RP_PKG)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
+ }
+
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf {
+ <LibraryClasses>
+ BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitDxeLib.inf
+ }
+ $(RP_PKG)/Platform/Dxe/S3NvramSave/S3NvramSave.inf {
+!if ($(FSP_MODE) == 0)
+ <BuildOptions>
+ *_*_*_CC_FLAGS = -D FSP_API_MODE
+!endif
+ }
+
+ $(PLATFORM_PKG)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+
+ $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
+ $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
+
+ MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+ BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
+
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+
+ #
+ # SiliconPkg code for Platform Integration are defined here
+ #
+!if $(CPUTARGET) == "CPX"
+ DEFINE CPU_CPX_SUPPORT = TRUE
+!else
+ DEFINE CPU_CPX_SUPPORT = FALSE
+!endif
+[PcdsFixedAtBuild]
+!if ($(CPU_SKX_ONLY_SUPPORT) == TRUE)
+ gSiPkgTokenSpaceGuid.PcdPostedCsrAccessSupported |FALSE
+!endif
+[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION]
+ ResetSystemLib|MdeModulePkg/Library/DxeResetSystemLib/DxeResetSystemLib.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ ResetSystemLib|MdeModulePkg/Library/RuntimeResetSystemLib/RuntimeResetSystemLib.inf
+
+
+###################################################################################################
+#
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+# the default flags for a module. These flags are appended to any
+# standard flags that are defined by the build process. They can be
+# applied for any modules or only those modules with the specific
+# module style (EDK or EDKII) specified in [Components] section.
+#
+###################################################################################################
+[BuildOptions.Common.EDKII]
+# Append build options for EDK and EDKII drivers (= is Append, == is Replace)
+!if $(CRB_FLAG_ENABLE) == TRUE
+ DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG
+!else
+ DEFINE CRB_EDKII_BUILD_OPTIONS =
+!endif
+
+!if $(DEBUG_FLAGS_ENABLE) == TRUE
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D DEBUG_CODE_BLOCK=1 -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!else
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D SILENT_MODE -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!endif
+
+!if $(SPARING_SCRATCHPAD_ENABLE) == TRUE
+ DEFINE SPARING_SCRATCHPAD_OPTION = -D SPARING_SCRATCHPAD_SUPPORT
+!else
+ DEFINE SPARING_SCRATCHPAD_OPTIONS =
+!endif
+
+!if $(SCRATCHPAD_DEBUG) == TRUE
+ DEFINE SCRATCHPAD_DEBUG_OPTION = -D SCRATCHPAD_DEBUG
+!else
+ DEFINE SCRATCHPAD_DEBUG_OPTION =
+!endif
+
+!if $(PCH_SERVER_BIOS_ENABLE) == TRUE
+ DEFINE PCH_BUILD_OPTION = -DPCH_SERVER_BIOS_FLAG=1
+!else
+ DEFINE PCH_BUILD_OPTION =
+!endif
+
+!if $(SERVER_BIOS_ENABLE) == TRUE
+ DEFINE SERVER_BUILD_OPTION = -DSERVER_BIOS_FLAG=1
+!else
+ DEFINE SERVER_BUILD_OPTION =
+!endif
+
+DEFINE SC_PATH = -D SC_PATH="Pch/SouthClusterLbg"
+
+DEFINE ME_PATH = -D ME_PATH="Me/MeSps.4"
+
+DEFINE IE_PATH = -D IE_PATH="Ie/v1"
+
+DEFINE NVDIMM_OPTIONS =
+
+!if $(CPUTARGET) == "ICX"
+ DEFINE CPU_TYPE_OPTIONS = -D ICX_HOST -D A0_HOST -D B0_HOST
+!elseif $(CPUTARGET) == "CPX"
+ DEFINE CPU_TYPE_OPTIONS = -D SKX_HOST -D CLX_HOST -D CPX_HOST -D A0_HOST -D B0_HOST
+!endif
+
+DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS = -D MAX_SOCKET=$(MAX_SOCKET) -D MAX_CORE=$(MAX_CORE) -D MAX_THREAD=$(MAX_THREAD)
+
+DEFINE MRC_OPTIONS = -D LRDIMM_SUPPORT -D DDRT_SUPPORT
+
+!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=4 -D MAX_MC_CH=2
+!else
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=2 -D MAX_MC_CH=3
+!endif
+
+DEFINE MAX_SAD_RULE_OPTION = -D MAX_SAD_RULES=24 -D MAX_DRAM_CLUSTERS=1
+
+DEFINE LT_BUILD_OPTIONS = -D LT_FLAG
+
+DEFINE FSP_BUILD_OPTIONS = -D FSP_DISPATCH_MODE_ENABLE=1
+
+#
+# MAX_KTI_PORTS needs to be updated based on the silicon type
+#
+!if $(CPUTARGET) == "CPX"
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=6
+!else
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=3
+!endif
+
+DEFINE IIO_STACK_OPTIONS = -D MAX_IIO_STACK=6 -D MAX_LOGIC_IIO_STACK=8
+
+DEFINE PCH_BIOS_BUILD_OPTIONS = $(PCH_BUILD_OPTION) $(SC_PATH) $(SERVER_BUILD_OPTION)
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(CRB_EDKII_BUILD_OPTIONS) $(EDKII_DEBUG_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(MAX_SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS) $(MAX_SAD_RULE_OPTION) $(KTI_OPTIONS) $(IIO_STACK_OPTIONS) $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS) $(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION) $(NVDIMM_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT $(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADDRESS=0x80000000 -D DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS) $(FSP_BUILD_OPTIONS)
+
+DEFINE IE_OPTIONS = $(IE_PATH) -DIE_SUPPORT=0
+
+!if $(LINUX_GCC_BUILD) == TRUE
+ DEFINE EDK2_LINUX_BUILD_OPTIONS = -D EDK2_CTE_BUILD
+!else
+ DEFINE EDK2_LINUX_BUILD_OPTIONS =
+!endif
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(EDK2_LINUX_BUILD_OPTIONS) $(IE_OPTIONS)
+
+DEFINE ME_OPTIONS = -DSPS_VERSION=4 $(ME_PATH)
+
+DEFINE ASPEED_ENABLE_BUILD_OPTIONS = -D ASPEED_ENABLE -D ESPI_ENABLE
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(ME_OPTIONS) $(ASPEED_ENABLE_BUILD_OPTIONS)
+
+ MSFT:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS) /wd4819
+ GCC:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+#
+# Enable source level debugging for RELEASE build
+#
+!if $(TARGET) == "RELEASE"
+ DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =
+
+ MSFT:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi
+ MSFT:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7
+ MSFT:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /DEBUG
+ GCC:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
+ GCC:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
+ GCC:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
+!endif
+
+#
+# Override ASL Compiler parameters in tools_def.template.
+#
+ MSFT:*_*_*_ASL_PATH == $(WORKSPACE)/../FDBin/Tools/IaslCompiler/6.3/iasl.exe
+ GCC:*_*_*_ASL_PATH == $(WORKSPACE)/../FDBin/Tools/IaslCompiler/6.3/iasl
+ *_*_*_ASL_FLAGS == -vr -we -oi
+#
+# Override the VFR compile flags to speed the build time
+#
+
+*_*_*_VFR_FLAGS == -n
+
+#
+# add to the build options for DXE/SMM drivers to remove the log message:
+# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!!
+#
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+
+[BuildOptions]
+ GCC:*_GCC5_*_CC_FLAGS = -Wno-overflow -Wno-discarded-qualifiers -Wno-unused-variable -Wno-unused-but-set-variable -Wno-incompatible-pointer-types -mabi=ms
+ GCC:*_GCC5_IA32_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ GCC:*_GCC5_X64_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ MSFT:*_*_*_CC_FLAGS = /FAsc
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
new file mode 100644
index 0000000000..927db9e210
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
@@ -0,0 +1,827 @@
+## @file
+# FDF file of platform with 64-bit DXE
+# This package provides platform specific modules and flash layout information.
+#
+# @copyright
+# Copyright 2006 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+DEFINE PLATFORM_PKG = MinPlatformPkg
+
+# 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
+DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060
+
+DEFINE MICROCODE_HEADER_SIZE = 0x00000090
+
+DEFINE VPD_HEADER_SIZE = 0x00000090
+
+!if $(FSP_MODE) == 0
+ DEFINE FSP_BIN_DIR = Api
+!else
+ DEFINE FSP_BIN_DIR = Dispatch
+!endif
+
+#
+# Note: FlashNv PCD naming conventions are as follows:
+# Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for
+# Others should be examined with an effort to work toward this guideline.
+# PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
+# PcdFlash*Size is a hex count of the length of the FD or FV
+# All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
+#
+# Also all values will have a PCD assigned so that they can be used in the system, and
+# the FlashMap edit tool can be used to change the values here, without effecting the code.
+# This requires all code to only use the PCD tokens to recover the values.
+
+
+#
+# 16MiB Total FLASH Image (visible in memory mapped IO)
+#
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
+
+################################################################################
+#
+# FD SECPEI
+#
+# Contains all the SEC and PEI modules
+#
+# Layout: (Low address to high address)
+#
+# FvBsp for board specific components
+# FvPostMemory for compressed post memory MinPlatform spec required components
+# FvFspS for compressed post memory silicon initialization components
+# FvPostMemorySilicon for silicon components
+# FvFspM for pre memory silicon initialization components
+# FvPreMemorySilicon for silicon components
+# FvFspT for temp RAM silicon initilization components
+# FvBspPreMemory for board specific components required to intialize memory
+# FvAdvancedPreMemory FV for advanced features components
+# FvPreMemory for components required by MinPlatform spec and to initialize memory
+# FvPreMemorySecurity FV for stage 6 required components
+# Contains reset vector
+#
+################################################################################
+
+[FD.SecPei]
+ BaseAddress = 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase #The base address of the FLASH Device
+ Size = 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize #The size in bytes of the FLASH Device
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x360
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ # At this time, the FSP FV must be aligned at the same address they were built to, 0xFFD00000
+ # This will be corrected in the future.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00040000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x00221000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00006000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize = 0x00001000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # Calculate Offsets Once (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset = 0x00000000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # FV Layout (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ FV = FvBsp
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ FV = FvPostMemory
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_S.fd
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_M.fd
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_T.fd
+
+ #
+ # Shared FV layout
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+ FV = FvBspPreMemory
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+ FV = FvPreMemory
+
+ #
+ # Calculate base addresses (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # Set duplicate PCD
+ # These should not need to be changed
+ #
+
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+
+ #
+ # For FSP Dispatch Mode, specify the FV containing the PEI core.
+ #
+ !if $(FSP_MODE) == 1
+ #
+ # Tell SEC to use PEI Core from outside FSP for additional debug message control.
+ #
+ SET gSiPkgTokenSpaceGuid.PcdPeiCoreFv = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
+ !endif
+
+ #
+ # For API mode, wrappers have some duplicate PCD as well
+ #
+ !if $(FSP_MODE) == 0
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
+ !endif
+
+################################################################################
+#
+# FD Main
+#
+# All DXE modules and other regions
+#
+# Layout: (Low address to high address)
+#
+# FvAdvanced for advanced feature components
+# Assorted advanced feature FV
+# FvSecurity for MinPlatform spec required components needed to boot securely
+# FvOsBoot for MinPlatform spec required components needed to boot OS
+# FvLateSilicon for silicon specific components
+# FvUefiBoot for MinPlatform spec required components needed to boot to UEFI shell
+#
+################################################################################
+[FD.Main]
+ BaseAddress = 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase # The base address of the FLASH Device
+ Size = 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize # The size in bytes of the FLASH Device
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x9C0
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ # These are out of flash layout order because FvAdvanced gets any remaining space
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00010000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00230000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x0004C000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+
+ #
+ # Calculate Offsets Once (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00000000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+ #
+ # FV Layout (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ FV = FvAdvanced
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ FV = FvSecurity
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+ FV = FvOsBoot
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+ FV = FvUefiBoot
+
+ #
+ # Calculate base addresses (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+################################################################################
+#
+# FD BINARY
+#
+# Contains the OPROM and other binary modules
+#
+# Layout: (Low address to high address)
+#
+# FvOpRom containing pre-built components
+# FvAcmRegion containing ACM related content
+# FV Header + Blank Space (1K)
+# Policy block (3K)
+# Blank space to align ACM on 64K boundary (60K)
+# ACM binary
+# FvMicrocode containing microcode update patches
+# Unformatted region for PCI Gen 3 Data
+# FvVpd containing PCD VPD data
+# FvWhea for WHEA data recording
+# FvNvStorageVariable for UEFI Variable storage
+# FvNvStorageEventLog for NV Store management
+# FvNvStorageFtwWorking for Fault Tolerant Write solution
+# FvNvStorageFtwSpare for Fault Tolerant Write solution
+#
+################################################################################
+[FD.Binary]
+ BaseAddress = 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase
+ Size = 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x2E0
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize = 0x00100000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize = 0x00050000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = 0x000D0000
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize = 0x00010000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize = 0x00030000
+ #
+ # These four items are tightly coupled.
+ # The spare area size must be >= the first three areas.
+ #
+ # There isn't really a benefit to a larger spare area unless the FLASH device
+ # block size is larger than the size specified.
+ #
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0003C000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize = 0x00002000
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # Calculate Offsets Once (You should not need to modify this section)
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = 0x00000000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically
+ #
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + $(MICROCODE_HEADER_SIZE)
+
+ #
+ # FV Layout (You should not need to modify this section)
+ #
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ FV = FvOprom
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ FV = FvAcm
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ FV = FvMicrocode
+
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
+ FV = FvVPD
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ FV = FvWhea
+
+ #
+ # Do not modify.
+ # See comments in size discussion above. These four areas are tightly coupled and should be modified with utmost care.
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
+
+ #
+ # Calculate base addresses (You should not need to modify this section)
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE)
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE)
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # ACM details
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize = 0x3000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize = 0x00040000
+
+ #
+ # Other duplicate PCD
+ #
+ SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+
+################################################################################
+#
+# FD FPGA
+#
+# Contains the FPGA modules
+#
+################################################################################
+
+[FD.Fpga]
+ BaseAddress = 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase #The base address of the FPGA Device ( 4G - 48M )
+ Size = 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize #The size in bytes of the FPGA Device ( 32M )
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x2000
+
+ 0x00000000|0x02000000
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize
+ FV = FvFpga
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvSecurityPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 40ab290f-8494-41cf-b302-31b178b4ce0b
+
+[FV.FvPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
+
+ FILE SEC = 1BA0062E-C779-4582-8566-336AE8F78F09 {
+ SECTION UI = "SecCore"
+ SECTION VERSION = "1.0"
+ SECTION Align = 16 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/1BA0062E-C779-4582-8566-336AE8F78F09SecCore.efi
+ SECTION Align = 16 RAW = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ResetVec.bin
+ }
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
+ INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
+
+ INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf
+
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+
+ INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf
+
+ FILE PEIM = 0043A734-CB11-4274-B363-E165F958CB5F {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/0043A734-CB11-4274-B363-E165F958CB5FMultiPch.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/0043A734-CB11-4274-B363-E165F958CB5FMultiPch.efi
+ SECTION UI = "MultiPch"
+ }
+
+ FILE PEIM = ac4b7f1b-e057-47d3-b2b5-1137493c0f38 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi
+ SECTION UI = "DynamicSiLibraryPei"
+ }
+
+ INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
+
+ INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
+
+ INF WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
+
+ #
+ # UBA common and board specific components
+ #
+ !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf
+
+ INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+
+ INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
+
+ FILE PEIM = ca8efb69-d7dc-4e94-aad6-9fb373649161 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi
+ SECTION UI = "SiliconPolicyInitPreAndPostMem"
+ }
+
+ INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+
+ !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePreMemory.fdf
+
+ INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
+
+ INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+ !if $(FSP_MODE) == 0
+ FILE PEIM = 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi
+ SECTION UI = "CsrPseudoOffsetInitPeim"
+ }
+ FILE PEIM = 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi
+ SECTION UI = "RegAccessPeim"
+ }
+ FILE PEIM = C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi
+ SECTION UI = "SiliconDataInitPeim"
+ }
+ INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+ INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+ INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
+ !endif
+
+ FILE FV_IMAGE = 40ab290f-8494-41cf-b302-31b178b4ce0b {
+ SECTION FV_IMAGE = FvSecurityPreMemory
+ }
+
+[FV.FvAdvancedPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 09f25d44-b2ef-4225-8b2e-e0e094b51775
+
+[FV.FvBspPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = e6c65995-8c2d-4119-a52d-7dbf1acb45a1
+
+ FILE FV_IMAGE = 09f25d44-b2ef-4225-8b2e-e0e094b51775 {
+ SECTION FV_IMAGE = FvAdvancedPreMemory
+ }
+
+#
+# FvPostMemory includes common hardware, common core variable services, load and invoke DXE etc
+#
+[FV.FvPostMemoryUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA
+
+[FV.FvPostMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 3298afc4-c484-47f1-a65a-5917a54b5e8c
+
+ FILE FV_IMAGE = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvPostMemoryUncompressed
+ }
+ }
+
+#
+# FvBsp includes board specific components
+#
+[FV.FvBspUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = e4c65347-fd90-4143-8a41-113e1015fe07
+
+[FV.FvBsp]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 9e151cf3-ca90-444f-b33b-a9941cbc772f
+
+ FILE FV_IMAGE = e4c65347-fd90-4143-8a41-113e1015fe07 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvBspUncompressed
+ }
+ }
+
+[FV.FvUefiBootUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = C4D3B0E2-FB26-44f8-A05B-E95895FCB960
+
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
+
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
+ #ATA for IDE/AHCI/RAID support
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+ INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+
+[FV.FvUefiBoot]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = ab9fe87b-1e37-440c-91cc-9aea03ce7bec
+
+ FILE FV_IMAGE = C4D3B0E2-FB26-44f8-A05B-E95895FCB960 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvUefiBootUncompressed
+ }
+ }
+
+[FV.FvOsBootUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
+
+ #
+ # DXE Phase modules
+ #
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+
+ FILE FV_IMAGE = B7C9F0CB-15D8-26FC-CA3F-C63947B12831 {
+ SECTION UI = "FvLateSilicon"
+ SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateSilicon.fv
+ }
+
+ INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+
+ !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePostMemory.fdf
+
+ #
+ # UBA DXE common and board specific components
+ #
+ !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf
+ !include WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
+ INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf
+ INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+
+ !if ($(FSP_MODE) == 1)
+ INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf
+ !else
+ INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+ !endif
+
+ INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
+ INF UefiCpuPkg/CpuDxe/CpuDxe.inf
+ INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+ FILE FV_IMAGE = a0277d07-a725-4823-90f9-6cba00782111 {
+ SECTION UI = "FvLateOpenBoard"
+ SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateOpenBoard.fv
+ }
+
+ INF MdeModulePkg/Universal/Metronome/Metronome.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
+ INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf
+ INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV.
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+ INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+ INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
+
+ INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+
+ INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+
+ INF MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
+
+ INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf
+
+ INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+
+ INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
+
+ # UEFI USB stack
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+ INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
+ INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+
+ INF MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
+
+ INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
+
+[FV.FvOsBoot]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = c7488640-5f51-4969-b63b-89fc369e1725
+
+ FILE FV_IMAGE = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvOsBootUncompressed
+ }
+ }
+
+[FV.FvSecuritySilicon]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = AD262F8D-BDED-4668-A8D4-8BC73516652F
+
+[FV.FvSecurityUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 03E25550-89A5-4ee6-AF60-DB0553D91FD2
+
+ FILE FV_IMAGE = 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecuritySilicon
+ }
+ }
+
+[FV.FvSecurity]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 68134833-2ff6-4d22-973b-575d0eae8ffd
+
+ FILE FV_IMAGE = 03E25550-89A5-4ee6-AF60-DB0553D91FD2 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecurityUncompressed
+ }
+ }
+
+[FV.FvAdvancedUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 70aeaf57-4997-49ce-a4f7-122980745670
+
+[FV.FvAdvanced]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = f21ee7a1-53a9-453d-aee3-b6a5c25bada5
+
+ FILE FV_IMAGE = 70aeaf57-4997-49ce-a4f7-122980745670 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvAdvancedUncompressed
+ }
+ }
+
+#
+# FV for all Microcode Updates.
+#
+[FV.FvMicrocode]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ LOCK_STATUS = FALSE
+ FvNameGuid = D2C29BA7-3809-480F-9C3D-DE389C61425A
+
+!if $(CPUTARGET) == "CPX"
+ INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
+!else
+ INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
+!endif
+
+
+[FV.FvVPD]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ LOCK_STATUS = FALSE
+ FvNameGuid = FFC29BA7-3809-480F-9C3D-DE389C61425A
+ FILE RAW = FF7DB236-F856-4924-90F8-CDF12FB875F3 {
+ $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin
+ }
+
+#
+# Various Vendor UEFI Drivers (OROMs).
+#
+[FV.FvOpromUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = B6EDE22C-DE30-45fa-BB09-CA202C1654B7
+
+[FV.FvOprom]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD
+
+ FILE FV_IMAGE = B6EDE22C-DE30-45fa-BB09-CA202C1654B7 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvOpromUncompressed
+ }
+ }
+
+[FV.FvWhea]
+ BlockSize = 0x1000
+ NumBlocks = 0x30
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = d6a1cd70-4b33-4994-a6ea-375f2ccc5437
+
+#
+# FV For ACM Binary.
+#
+[FV.FvAcm]
+ BlockSize = 0x1000
+ NumBlocks = 0x50
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 11668261-8A8D-47ca-9893-052D24435E59
+
+[FV.FvFpga]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 974650E7-6DFE-4998-A124-CEDEC5C9B47D
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
new file mode 100644
index 0000000000..ecfdb895ba
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
@@ -0,0 +1,45 @@
+## @file
+# platform configuration file for DEBUG build.
+#
+# @copyright
+# Copyright 2011 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# TRUE is ENABLE. FALSE is DISABLE.
+#
+
+DEFINE CRB_FLAG_ENABLE = TRUE
+DEFINE DEBUG_FLAGS_ENABLE = FALSE
+
+DEFINE PERFORMANCE_ENABLE = TRUE
+
+DEFINE SERVER_BIOS_ENABLE = TRUE
+DEFINE PCH_SERVER_BIOS_ENABLE = TRUE
+
+!if $(CPUTARGET) == "CPX"
+ DEFINE CPU_SKX_ONLY_SUPPORT = TRUE
+!else
+ DEFINE CPU_SKX_ONLY_SUPPORT = FALSE
+!endif
+
+!if $(CPUTARGET) == "CPX"
+ DEFINE CPU_CPX_SUPPORT = TRUE
+!else
+ DEFINE CPU_CPX_SUPPORT = FALSE
+!endif
+
+DEFINE RAS_CPU_ONLINE_OFFLINE_ENABLE = FALSE
+
+DEFINE SPARING_SCRATCHPAD_ENABLE = TRUE
+DEFINE SCRATCHPAD_DEBUG = TRUE
+
+DEFINE TPM2_ENABLE = FALSE
+
+DEFINE ME_PATH_CONFIG = Me/MeSps.4
+
+DEFINE SECURE_BOOT_ENABLE = FALSE
+
+DEFINE PLATFORMX64_ENABLE = TRUE
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc
new file mode 100644
index 0000000000..e356c917fe
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc
@@ -0,0 +1,8553 @@
+## @file
+# @copyright
+# Copyright 2019 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08
+
+[SkuIds]
+ 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
+
+[DefaultStores]
+ 0|STANDARD # UEFI Standard default 0|STANDARD is reserved.
+ 1|MANUFACTURING # UEFI Manufacturing default 1|MANUFACTURING is reserved.
+
+[PcdsDynamicExVpd.common.DEFAULT]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdNvStoreDefaultValueBuffer|*
+
+[PcdsDynamicExHii.common.DEFAULT.STANDARD]
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|L"FpgaSocketConfig"|gFpgaSocketVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdPchSetup|L"PchSetup"|gPchSetupVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSetup|L"Setup"|gEfiSetupVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|L"SocketCommonRcConfig"|gEfiSocketCommonRcVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig|L"SocketIioConfig"|gEfiSocketIioVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|L"SocketMemoryConfig"|gEfiSocketMemoryVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|L"SocketMpLinkConfig"|gEfiSocketMpLinkVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|L"SocketPowerManagementConfig"|gEfiSocketPowermanagementVarGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|L"SocketProcessorCoreConfig"|gEfiSocketProcessorCoreVarGuid|0x00||NV, BS, RT
+
+!if $(TARGET) == "DEBUG"
+gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvl|0x4
+gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvlTrainResults|0x8
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DebugPrintLevel|0xF
+!else
+gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvl|0x0
+gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvlTrainResults|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DebugPrintLevel|0x0
+!endif
+
+gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig.DfxHybridSystemLevelEmulation|0x0 # Hybrid SLE Mode
+gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig.DfxPmMsrTrace|0x0 # MSR Trace for PM
+gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig.DfxUbiosGeneration|0x0 # uBIOS Generation
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaSetupEnabled|0x3 # Sockets Enable Bitmap(Hex)
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaSocketGuid[0]|0x0 # Socket 0 BitStream
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaSocketGuid[1]|0x0 # Socket 1 BitStream
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH1[0]|0x5a # Socket 0 Threshold 1
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH1[1]|0x5a # Socket 1 Threshold 1
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH2[0]|0x5d # Socket 0 Threshold 2
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH2[1]|0x5d # Socket 1 Threshold 2
+gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeDidEnabled|0x1 # DRAM Init Done Enable
+gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeHeci1Enabled|0x0 # HECI-1 Enable
+gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeHeci2Enabled|0x0 # HECI-2 Enable
+gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeHeci3Enabled|0x0 # HECI-3 Enable
+gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeIderEnabled|0x0 # IDER Enable
+gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeKtEnabled|0x0 # KT Enable
+gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.SubsystemId|0x7270 # Subsystem ID
+gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.SubsystemVendorId|0x8086 # Subsystem Vendor ID
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtCiraRequest|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtCiraTimeout|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtbxHotKeyPressed|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtbxSelectionScreen|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Amt|0x1
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Asf|0x1
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BiosPause|0x1 # BIOS Pause Before Booting Capability State
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BiosReflash|0x1 # BIOS Reflash Capability State
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BiosSetup|0x1 # BIOS Boot to Setup Capability State
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BreakRtcEnabled|0x0 # Break RTC Configuration
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.CLINKDisableOverride|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.CoreBiosDoneEnabled|0x1 # Core Bios Done Message
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.CpuTypeEmulation|0xa
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DelayedAuthenticationModeOverride|0x0 # Delayed Authentication Mode (DAM) Override
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DelayedAuthenticationMode|0x0 # Delayed Authentication Mode (DAM)
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DidInitStat|0x0 # DRAM Initialization Status
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DisableD0I3SettingForHeci|0x0 # D0I3 Setting for HECI Disable
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.EndOfPostMessage|0x2 # END_OF_POST Message
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HeciCommunication2|0x2 # HECI-2 Enable
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HeciCommunication3|0x2 # HECI-3 Enable
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HeciCommunication|0x2 # HECI-1 Enable
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.FWProgress|0x1
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Frequency[0]|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Frequency[1]|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HideUnConfigureMeConfirm|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HostResetNotification|0x1 # Host Reset Warning
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HsioMessagingEnabled|0x0 # Enable HSIO Messaging
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.IccClkOverride|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.IccProfile|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.KtDeviceEnable|0x2 # KT Enable
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.LocalFwUpdEnabled|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MdesCapability|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeEnableHeciTraces|0x0 # Enable HECI Dump
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeFirmwareMode|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeFwDowngrade|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeGrLockEnabled|0x1 # Global Reset Lock
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeGrPromotionEnabled|0x0 # CF9 global reset promotion
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHeci1HideInMe|0x0 # HECI-1 Hide in ME
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHeci2HideInMe|0x0 # HECI-2 Hide in ME
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHeci3HideInMe|0x0 # HECI-3 Hide in ME
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHmrfpoEnableEnabled|0x0 # HMRFPO_ENABLE Message
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHmrfpoLockEnabled|0x1 # HMRFPO_LOCK Message
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeIderEnabled|0x2 # IDEr Enable
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeImageType|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MePttEnabled|0x0 # PTT Support
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MePttSupported|0x0 # ME PTT Supported
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MePttSuppressCommandSend|0x0 # Suppress PTT Commands
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeRegionSelectEnabled|0x0 # REGION_SELECT Message
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeStateControl|0x1
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeTimeout|0x2 # ME Initialization Complete Timeout
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeType|0xee # ME Firmware Type
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeWatchdogControlEnabled|0x1 # WATCHDOG_CONTROL Message
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxDebugMsg|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxGraphicsMode|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxNonUiTextMode|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxUiTextMode|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MngState|0x1
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmCores2DisableOverride|0x0 # Cores Disable Override
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmCores2Disable|0x0 # Cores To Disable
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmHwChangeOverride|0x0 # Hardware Change Override
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmHwChangeStatus|0x0 # Hardware Changed
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPowerMsmtOverride|0x0 # Power Measurement Override
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPowerMsmtSupport|0x0 # Power Measurement
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPtuLoadOverride|0x0 # PTU Load Override
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPwrOptBootOverride|0x0 # Boot Mode Override
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPwrOptBoot|0x0 # Boot Mode
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.PreDidMeResetEnabled|0x0 # Pre-DramInitDone ME Reset
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.RegLock|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.RemoteSessionActive|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SecureBootExposureToFw|0x1 # BIOS Secure Boot Capability Exposure to FW State
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Spread[0]|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Spread[1]|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SendDidMsg|0x1 # DRAM Init Done Enable
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsAltitude|0x8000 # Altitude
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsMctpBusOwner|0x0 # MCTP Bus Owner
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[0]|0x58 # PSU #1
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[1]|0x59 # PSU #2
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[2]|0x0 # PSU #3
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[3]|0x0 # PSU #4
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.USBProvision|0x1
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.UnConfigureMe|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.VproAllowed|0x1
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDogOs|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDogTimerBios|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDogTimerOs|0x0
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDog|0x0
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxDqsDelayLeftEdge|0x2 # RxDqsDelay Left Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxDqsDelayRightEdge|0x2 # RxDqsDelay Right Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxVrefLeftEdge|0x2 # RxVref Left Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxVrefRightEdge|0x2 # RxVref Right Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxDqDelayLeftEdge|0x2 # TxDqDelay Left Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxDqDelayRightEdge|0x2 # TxDqDelay Right Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxVrefLeftEdge|0x2 # TxVref Left Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxVrefRightEdge|0x2 # TxVref Right Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.MemBootHealthCheck|0x2 # Memory Boot Health Check
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.ResetOnCriticalError|0x1 # Reboot On Critical Failure
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxDqsDelayLeftEdge|0x5 # RxDqsDelay Left Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxDqsDelayRightEdge|0x5 # RxDqsDelay Right Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxVrefLeftEdge|0x5 # RxVref Left Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxVrefRightEdge|0x5 # RxVref Right Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxDqDelayLeftEdge|0x5 # TxDqDelay Left Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxDqDelayRightEdge|0x5 # TxDqDelay Right Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxVrefLeftEdge|0x5 # TxVref Left Edge
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxVrefRightEdge|0x5 # TxVref Right Edge
+gStructPcdTokenSpaceGuid.PcdPchSetup.AdrCpuThermalWdt|0x0 # CPU Thermal WDT ADR Enable
+gStructPcdTokenSpaceGuid.PcdPchSetup.AdrGpioSel|0x0 # ADR GPIO
+gStructPcdTokenSpaceGuid.PcdPchSetup.AdrHostPartitionReset|0x0 # Host Partition Reset ADR Enable
+gStructPcdTokenSpaceGuid.PcdPchSetup.AdrMultiplierVal|0x63 # ADR timer multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.AdrOverClockingWdt|0x0 # Over-Clocking WDT ADR Enable
+gStructPcdTokenSpaceGuid.PcdPchSetup.AdrPmcParityError|0x0 # PMC Parity Error ADR Enable
+gStructPcdTokenSpaceGuid.PcdPchSetup.AdrSysPwrOk|0x0 # SYS_PWROK Failure ADR Enable
+gStructPcdTokenSpaceGuid.PcdPchSetup.AdrTimerEn|0x0 # Enable/Disable ADR Timer
+gStructPcdTokenSpaceGuid.PcdPchSetup.AdrTimerVal|0x4 # ADR timer expire time
+gStructPcdTokenSpaceGuid.PcdPchSetup.AetEnableMode|0x0 # AET Enable Mode
+gStructPcdTokenSpaceGuid.PcdPchSetup.Btcg|0x1 # Trunk Clock Gating (BTCG)
+gStructPcdTokenSpaceGuid.PcdPchSetup.DciEn|0x0 # DCI enable (HDCIEN)
+gStructPcdTokenSpaceGuid.PcdPchSetup.DeepSxMode|0x0 # DeepSx Power Policies
+gStructPcdTokenSpaceGuid.PcdPchSetup.DfxHdaVcType|0x0 # Virtual Channel for HD Audio
+gStructPcdTokenSpaceGuid.PcdPchSetup.DmiLinkDownHangBypass|0x0 # DMI Link Down Hang Bypass (DLDHB)
+gStructPcdTokenSpaceGuid.PcdPchSetup.DwrEn_IEWDT|0x0 # IE FW Watchdog Timer
+gStructPcdTokenSpaceGuid.PcdPchSetup.DwrEn_MEWDT|0x0 # ME FW Watchdog Timer
+gStructPcdTokenSpaceGuid.PcdPchSetup.DwrEn_PMCGBL|0x1 # Host Reset Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_BmcRootPort|0x5 # BMC RootPort
+gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_Enable|0x0 # Dirty Warm Reset
+gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_IeResetPrepDone|0x1 # IE Reset Prep Done
+gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_MeResetPrepDone|0x1 # ME Reset Prep Done
+gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_Stall|0x0 # Dirty Warm Reset Stall
+gStructPcdTokenSpaceGuid.PcdPchSetup.EnableClockSpreadSpec|0x1 # External SSC Enable - CK420
+gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[0]|0x0 # USB 3.0 pin #1
+gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[1]|0x0 # USB 3.0 pin #2
+gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[2]|0x0 # USB 3.0 pin #3
+gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[3]|0x0 # USB 3.0 pin #4
+gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[4]|0x0 # USB 3.0 pin #5
+gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[5]|0x0 # USB 3.0 pin #6
+gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[6]|0x0 # USB 3.0 pin #7
+gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[7]|0x0 # USB 3.0 pin #8
+gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[8]|0x0 # USB 3.0 pin #9
+gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[9]|0x0 # USB 3.0 pin #10
+gStructPcdTokenSpaceGuid.PcdPchSetup.FirmwareConfiguration|0x0 # Firmware Configuration
+gStructPcdTokenSpaceGuid.PcdPchSetup.FlashLockDown|0x0 # Flash Lock-Down
+gStructPcdTokenSpaceGuid.PcdPchSetup.GbeRegionInvalid|0x0 # Gbe Region Valid
+gStructPcdTokenSpaceGuid.PcdPchSetup.Gp27WakeFromDeepSx|0x0 # GP27 Wake From DeepSx
+gStructPcdTokenSpaceGuid.PcdPchSetup.IchPort80Route|0x0 # Port 80h Redirection
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchAdrEn|0x0 # Enable/Disable ADR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchAllUnLock|0x0 # Unlock All PCH registers
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchBiosLock|0x1 # BIOS Lock
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchCrossThrottling|0x1 # PCH Cross Throttling
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchDciAutoDetect|0x0 # DCI Auto Detect Enable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaLockDown|0x1 # EVA registers LOCK
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaMrom0HookEnable|0x1 # MROM 0 Hook
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaMrom1HookEnable|0x1 # MROM 1 Hook
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchGpioLockDown|0x1 # GPIO Lockdown
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchHdAudio|0x1 # Azalia
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchHdAudioCodecSelect|0x0 # HDA-Link Codec Select
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchHdAudioPme|0x0 # Azalia PME Enable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchIoApic24119Entries|0x1 # IO-APIC 24-119 RTE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchLanK1Off|0x0 # K1 off
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchP2sbDevReveal|0x0 # Reveal PCH P2SB device
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchP2sbUnlock|0x0 # Unlock PCH P2SB
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[0]|0x0 # Force LTR Override PCIE1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[1]|0x0 # Force LTR Override PCIE2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[2]|0x0 # Force LTR Override PCIE3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[3]|0x0 # Force LTR Override PCIE4
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[4]|0x0 # Force LTR Override PCIE5
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[5]|0x0 # Force LTR Override PCIE6
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[6]|0x0 # Force LTR Override PCIE7
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[7]|0x0 # Force LTR Override PCIE8
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[8]|0x0 # Force LTR Override PCIE9
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[9]|0x0 # Force LTR Override PCIE10
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[10]|0x0 # Force LTR Override PCIE11
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[11]|0x0 # Force LTR Override PCIE12
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[12]|0x0 # Force LTR Override PCIE13
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[13]|0x0 # Force LTR Override PCIE14
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[14]|0x0 # Force LTR Override PCIE15
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[15]|0x0 # Force LTR Override PCIE16
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[16]|0x0 # Force LTR Override PCIE17
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[17]|0x0 # Force LTR Override PCIE18
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[18]|0x0 # Force LTR Override PCIE19
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[19]|0x0 # Force LTR Override PCIE20
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieGlobalAspm|0x2 # PCI-E ASPM Support (Global)
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[0]|0x1 # PCH PCIE1 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[1]|0x1 # PCH PCIE2 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[2]|0x1 # PCH PCIE3 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[3]|0x1 # PCH PCIE4 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[4]|0x1 # PCH PCIE5 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[5]|0x1 # PCH PCIE6 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[6]|0x1 # PCH PCIE7 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[7]|0x1 # PCH PCIE8 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[8]|0x1 # PCH PCIE9 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[9]|0x1 # PCH PCIE10 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[10]|0x1 # PCH PCIE11 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[11]|0x1 # PCH PCIE12 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[12]|0x1 # PCH PCIE13 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[13]|0x1 # PCH PCIE14 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[14]|0x1 # PCH PCIE15 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[15]|0x1 # PCH PCIE16 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[16]|0x1 # PCH PCIE17 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[17]|0x1 # PCH PCIE18 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[18]|0x1 # PCH PCIE19 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[19]|0x1 # PCH PCIE20 LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[0]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[1]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[2]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[3]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[4]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[5]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[6]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[7]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[8]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[9]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[10]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[11]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[12]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[13]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[14]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[15]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[16]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[17]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[18]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[19]|0x2 # Non Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[0]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[1]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[2]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[3]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[4]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[5]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[6]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[7]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[8]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[9]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[10]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[11]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[12]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[13]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[14]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[15]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[16]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[17]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[18]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[19]|0x2 # Non Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[0]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[2]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[3]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[4]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[5]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[6]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[7]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[8]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[9]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[10]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[11]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[12]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[13]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[14]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[15]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[16]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[17]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[18]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[19]|0x3c # Non Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[0]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[1]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[2]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[3]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[4]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[5]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[6]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[7]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[8]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[9]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[10]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[11]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[12]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[13]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[14]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[15]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[16]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[17]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[18]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[19]|0x2 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[0]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[1]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[2]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[3]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[4]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[5]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[6]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[7]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[8]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[9]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[10]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[11]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[12]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[13]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[14]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[15]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[16]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[17]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[18]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[19]|0x2 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[0]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[1]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[2]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[3]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[4]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[5]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[6]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[7]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[8]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[9]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[10]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[11]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[12]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[13]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[14]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[15]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[16]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[17]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[18]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[19]|0x3c # Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX16CompletionTimeout|0x0 # CTO for Uplink x16
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX16MaxPayloadSize|0x2 # MPL for Uplink x16
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX8CompletionTimeout|0x0 # CTO for Uplink x8
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX8MaxPayloadSize|0x2 # MPL for Uplink x8
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchRtcLock|0x1 # RTC Lock
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataLtrConfigLock|0x1 # sSATA LTR Lock
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataLtrEnable|0x1 # PCH sSATA LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataLtrOverride|0x0 # sSATA LTR Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataSnoopLatencyOverrideMultiplier|0x2 # sSATA Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataSnoopLatencyOverrideValue|0x28 # sSATA Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSata|0x1 # SATA Controller
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataLtrConfigLock|0x1 # SATA LTR Lock
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataLtrEnable|0x1 # PCH SATA LTR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataLtrOverride|0x0 # SATA LTR Override
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataSnoopLatencyOverrideMultiplier|0x2 # SATA Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataSnoopLatencyOverrideValue|0x28 # SATA Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSirqMode|0x0 # Serial IRQ Mode
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSlpLanLowDc|0x1 # SLP_LAN# Low on DC Power
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchThermalUnlock|0x0 # Unlock Thermal Registers
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubHide|0x1 # Hide Trace Hub
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubMemReg0Size|0x0 # MemRegion 0 Buffer Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubMemReg1Size|0x0 # MemRegion 1 Buffer Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubMode|0x2 # TraceHub Enable Mode
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbDegradeBar|0x0 # Place XHCI BAR below 4GB
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[0]|0x1 # USB HS Physical Connector #0 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[1]|0x1 # USB HS Physical Connector #1 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[2]|0x1 # USB HS Physical Connector #2 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[3]|0x1 # USB HS Physical Connector #3 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[4]|0x1 # USB HS Physical Connector #4 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[5]|0x1 # USB HS Physical Connector #5 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[6]|0x1 # USB HS Physical Connector #6 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[7]|0x1 # USB HS Physical Connector #7 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[8]|0x1 # USB HS Physical Connector #8 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[9]|0x1 # USB HS Physical Connector #9 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[10]|0x1 # USB HS Physical Connector #10 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[11]|0x1 # USB HS Physical Connector #11 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[12]|0x1 # USB HS Physical Connector #12 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[13]|0x1 # USB HS Physical Connector #13 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbManualMode|0x0 # XHCI Manual Mode
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbPerPortCtl|0x0 # USB Per-Connector Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[0]|0x1 # USB SS Physical Connector #0 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[1]|0x1 # USB SS Physical Connector #1 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[2]|0x1 # USB SS Physical Connector #2 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[3]|0x1 # USB SS Physical Connector #3 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[4]|0x1 # USB SS Physical Connector #4 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[5]|0x1 # USB SS Physical Connector #5 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[6]|0x1 # USB SS Physical Connector #6 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[7]|0x1 # USB SS Physical Connector #7 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[8]|0x1 # USB SS Physical Connector #8 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[9]|0x1 # USB SS Physical Connector #9 Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchWakeOnLan|0x0 # Wake on LAN
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchsSata|0x1 # sSATA Controller
+gStructPcdTokenSpaceGuid.PcdPchSetup.PciDelayOptimizationEcr|0x0 # PCI Delay Optimization
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieComplianceTestMode|0x0 # Compliance Test Mode
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieDmiExtSync|0x0 # DMI Link Extended Synch Control
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieDmiStopAndScreamEnable|0x0 # Stop and Scream
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[0]|0x6 # PCIE1 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[1]|0x6 # PCIE2 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[2]|0x6 # PCIE3 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[3]|0x6 # PCIE4 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[4]|0x6 # PCIE5 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[5]|0x6 # PCIE6 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[6]|0x6 # PCIE7 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[7]|0x6 # PCIE8 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[8]|0x6 # PCIE9 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[9]|0x6 # PCIE10 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[10]|0x6 # PCIE11 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[11]|0x6 # PCIE12 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[12]|0x6 # PCIE13 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[13]|0x6 # PCIE14 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[14]|0x6 # PCIE15 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[15]|0x6 # PCIE16 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[16]|0x6 # PCIE17 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[17]|0x6 # PCIE18 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[18]|0x6 # PCIE19 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[19]|0x6 # PCIE20 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[0]|0x6 # PCIE1 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[1]|0x6 # PCIE2 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[2]|0x6 # PCIE3 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[3]|0x6 # PCIE4 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[4]|0x6 # PCIE5 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[5]|0x6 # PCIE6 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[6]|0x6 # PCIE7 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[7]|0x6 # PCIE8 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[8]|0x6 # PCIE9 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[9]|0x6 # PCIE10 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[10]|0x6 # PCIE11 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[11]|0x6 # PCIE12 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[12]|0x6 # PCIE13 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[13]|0x6 # PCIE14 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[14]|0x6 # PCIE15 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[15]|0x6 # PCIE16 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[16]|0x6 # PCIE17 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[17]|0x6 # PCIE18 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[18]|0x6 # PCIE19 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[19]|0x6 # PCIE20 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PciePllSsc|0xfe # Pcie Pll SSC
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[0]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[1]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[2]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[3]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[4]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[5]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[6]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[7]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[8]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[9]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[10]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[11]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[12]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[13]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[14]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[15]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[16]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[17]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[18]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[19]|0x1 # ACS
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[0]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[1]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[2]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[3]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[4]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[5]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[6]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[7]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[8]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[9]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[10]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[11]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[12]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[13]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[14]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[15]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[16]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[17]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[18]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[19]|0x1 # Advanced Error Reporting
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[0]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[1]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[2]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[3]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[4]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[5]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[6]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[7]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[8]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[9]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[10]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[11]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[12]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[13]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[14]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[15]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[16]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[17]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[18]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[19]|0x0 # PCIE ASPM
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[0]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[1]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[2]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[3]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[4]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[5]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[6]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[7]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[8]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[9]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[10]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[11]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[12]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[13]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[14]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[15]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[16]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[17]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[18]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[19]|0x0 # CER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[0]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[1]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[2]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[3]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[4]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[5]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[6]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[7]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[8]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[9]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[10]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[11]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[12]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[13]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[14]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[15]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[16]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[17]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[18]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[19]|0x0 # Compl. Timeout
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[0]|0x1 # PCI Express Root Port 1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[1]|0x1 # PCI Express Root Port 2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[2]|0x1 # PCI Express Root Port 3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[3]|0x1 # PCI Express Root Port 4
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[4]|0x1 # PCI Express Root Port 5
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[5]|0x1 # PCI Express Root Port 6
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[6]|0x1 # PCI Express Root Port 7
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[7]|0x1 # PCI Express Root Port 8
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[8]|0x1 # PCI Express Root Port 9
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[9]|0x1 # PCI Express Root Port 10
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[10]|0x1 # PCI Express Root Port 11
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[11]|0x1 # PCI Express Root Port 12
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[12]|0x1 # PCI Express Root Port 13
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[13]|0x1 # PCI Express Root Port 14
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[14]|0x1 # PCI Express Root Port 15
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[15]|0x1 # PCI Express Root Port 16
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[16]|0x1 # PCI Express Root Port 17
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[17]|0x1 # PCI Express Root Port 18
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[18]|0x1 # PCI Express Root Port 19
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[19]|0x1 # PCI Express Root Port 20
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[0]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[1]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[2]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[3]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[4]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[5]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[6]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[7]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[8]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[9]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[10]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[11]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[12]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[13]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[14]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[15]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[16]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[17]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[18]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[19]|0x1 # Gen3 Eq Phase3 Method
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[0]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[1]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[2]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[3]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[4]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[5]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[6]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[7]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[8]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[9]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[10]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[11]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[12]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[13]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[14]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[15]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[16]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[17]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[18]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[19]|0x0 # FER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFunctionSwapping|0x1 # PCIe Root Port Function Swapping
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[0]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[1]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[2]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[3]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[4]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[5]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[6]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[7]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[8]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[9]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[10]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[11]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[12]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[13]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[14]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[15]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[16]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[17]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[18]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[19]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[0]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[1]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[2]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[3]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[4]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[5]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[6]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[7]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[8]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[9]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[10]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[11]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[12]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[13]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[14]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[15]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[16]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[17]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[18]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[19]|0x3 # L1 Substates
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[0]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[1]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[2]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[3]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[4]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[5]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[6]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[7]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[8]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[9]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[10]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[11]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[12]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[13]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[14]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[15]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[16]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[17]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[18]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[19]|0x1 # Max Payload Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxReadRequestSize|0x5 # Max Read Request Size
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[0]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[1]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[2]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[3]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[4]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[5]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[6]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[7]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[8]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[9]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[10]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[11]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[12]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[13]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[14]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[15]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[16]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[17]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[18]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[19]|0x0 # NFER
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[0]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[1]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[2]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[3]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[4]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[5]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[6]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[7]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[8]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[9]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[10]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[11]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[12]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[13]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[14]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[15]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[16]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[17]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[18]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[19]|0x0 # PME SCI
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSBDE|0x0 # Subtractive Decode
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[0]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[1]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[2]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[3]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[4]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[5]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[6]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[7]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[8]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[9]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[10]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[11]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[12]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[13]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[14]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[15]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[16]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[17]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[18]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[19]|0x0 # SECE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[0]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[1]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[2]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[3]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[4]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[5]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[6]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[7]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[8]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[9]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[10]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[11]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[12]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[13]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[14]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[15]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[16]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[17]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[18]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[19]|0x0 # SEFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[0]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[1]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[2]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[3]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[4]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[5]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[6]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[7]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[8]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[9]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[10]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[11]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[12]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[13]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[14]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[15]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[16]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[17]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[18]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[19]|0x0 # SENFE
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[0]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[1]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[2]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[3]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[4]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[5]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[6]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[7]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[8]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[9]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[10]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[11]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[12]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[13]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[14]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[15]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[16]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[17]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[18]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[19]|0x0 # PCIe Speed
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[0]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[1]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[2]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[3]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[4]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[5]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[6]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[7]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[8]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[9]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[10]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[11]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[12]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[13]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[14]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[15]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[16]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[17]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[18]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[19]|0x0 # URR
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSBDEPort|0x0 # Subtractive Decode Port#
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[0]|0x6 # Coeff0 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[1]|0x4 # Coeff1 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[2]|0x8 # Coeff2 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[3]|0x2 # Coeff3 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[4]|0xa # Coeff4 Cm
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[0]|0x2 # Coeff0 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[1]|0x2 # Coeff1 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[2]|0x2 # Coeff2 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[3]|0x2 # Coeff3 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[4]|0x2 # Coeff4 Cp
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqOverride|0x0 # Override SW/HW EQ settings
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[0]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[1]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[2]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[3]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[4]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[5]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[6]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[7]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[8]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[9]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[10]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[11]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[12]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[13]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[14]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[15]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[16]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[17]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[18]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[19]|0x0 # PCIE Lane Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.PmcReadDisable|0x1 # PMC Read Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.PxDevSlp[2]|0x0 # SATA Port 2 DevSlp
+gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemap[0]|0x0 # NVRAM CYCLE ROUTER 0 ENABLE
+gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemap[1]|0x0 # NVRAM CYCLE ROUTER 1 ENABLE
+gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemap[2]|0x0 # NVRAM CYCLE ROUTER 2 ENABLE
+gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemapPort[0]|0x0 # NVRAM CR0 PCIE Root Port Number
+gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemapPort[1]|0x0 # NVRAM CR1 PCIE Root Port Number
+gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemapPort[2]|0x0 # NVRAM CR2 PCIE Root Port Number
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataAlternateId|0x0 # Alternate Device ID on RAID
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[0]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[1]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[2]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[3]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[4]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[5]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[6]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[7]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataHddlk|0x1 # SATA HDD Unlock
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[0]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[1]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[2]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[3]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[4]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[5]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[6]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[7]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataInterfaceMode|0x0 # Configure SATA as
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataLedl|0x1 # SATA Led locate
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[0]|0x0 # Mechanical Presence Switch
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[1]|0x0 # Mechanical Presence Switch
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[2]|0x0 # Mechanical Presence Switch
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[3]|0x0 # Mechanical Presence Switch
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[4]|0x0 # Mechanical Presence Switch
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[5]|0x0 # Mechanical Presence Switch
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[6]|0x0 # Mechanical Presence Switch
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[7]|0x0 # Mechanical Presence Switch
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[0]|0x1 # Port 0
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[1]|0x1 # Port 1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[2]|0x1 # Port 2
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[3]|0x1 # Port 3
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[4]|0x1 # Port 4
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[5]|0x1 # Port 5
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[6]|0x1 # Port 6
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[7]|0x1 # Port 7
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidIooe|0x1 # IRRT Only on ESATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidIrrt|0x1 # Intel Rapid Recovery Technology
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidLoadEfiDriver[0]|0x0 # Load EFI Driver for RAID
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidLoadEfiDriver[1]|0x0 # Load EFI Driver for RAID
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidOromDelay|0x0 # RAID OROM prompt delay
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidOub|0x1 # RAID Option ROM UI banner
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR0|0x1 # RAID 0
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR1|0x1 # RAID 1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR10|0x1 # RAID 10
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR5|0x1 # RAID 5
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidSrt|0x1 # Smart Response Technology
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataSalp|0x1 # Support Aggressive Link Power Management
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[0]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[1]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[2]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[3]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[4]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[5]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[6]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[7]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataTestMode|0x0 # SATA test mode
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[0]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[1]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[2]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[3]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[4]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[5]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[6]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[7]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[0]|0x0 # SATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[1]|0x0 # SATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[2]|0x0 # SATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[3]|0x0 # SATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[4]|0x0 # SATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[5]|0x0 # SATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[6]|0x0 # SATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[7]|0x0 # SATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.ShutdownPolicySelect|0x1 # Shutdown Policy
+gStructPcdTokenSpaceGuid.PcdPchSetup.StateAfterG3|0x0 # PCH state after G3
+gStructPcdTokenSpaceGuid.PcdPchSetup.TestDmiAspmCtrl|0x1 # PCH DMI ASPM Testing
+gStructPcdTokenSpaceGuid.PcdPchSetup.TestMctpBroadcastCycle|0x0 # MCTP Broadcast Cycle
+gStructPcdTokenSpaceGuid.PcdPchSetup.TestSmbusSpdWriteDisable|0x1 # SPD Write Disable
+gStructPcdTokenSpaceGuid.PcdPchSetup.ThermalDeviceEnable|0x3 # PCH Thermal Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.Usb3PinsTermination|0x1 # Enable USB 3.0 pins
+gStructPcdTokenSpaceGuid.PcdPchSetup.UsbPrecondition|0x0 # USB Precondition
+gStructPcdTokenSpaceGuid.PcdPchSetup.XTpmLen|0x1 # Expanded SPI TPM Transaction Length Enable
+gStructPcdTokenSpaceGuid.PcdPchSetup.XhciDisMSICapability|0x0 # USB XHCI MSI Disable WA
+gStructPcdTokenSpaceGuid.PcdPchSetup.XhciIdleL1|0x1 # XHCI Idle L1
+gStructPcdTokenSpaceGuid.PcdPchSetup.XhciOcMapEnabled|0x1 # XHCI Over Current Pins
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataAlternateId|0x0 # Alternate Device ID on RAID
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[0]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[1]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[2]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[3]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[4]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[5]|0x0 # Configure as eSATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHddlk|0x1 # SATA HDD Unlock
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[0]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[1]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[2]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[3]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[4]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[5]|0x0 # Hot Plug
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataInterfaceMode|0x0 # Configure sSATA as
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataLedl|0x1 # SATA Led locate
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[0]|0x1 # Port 0
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[1]|0x1 # Port 1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[2]|0x1 # Port 2
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[3]|0x1 # Port 3
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[4]|0x1 # Port 4
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[5]|0x1 # Port 5
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidIooe|0x1 # IRRT Only on ESATA
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidIrrt|0x1 # Intel Rapid Recovery Technology
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidOromDelay|0x0 # RAID OROM prompt delay
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidOub|0x1 # RAID Option ROM UI banner
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR0|0x1 # RAID 0
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR1|0x1 # RAID 1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR10|0x1 # RAID 10
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR5|0x1 # RAID 5
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidSrt|0x1 # Smart Response Technology
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSalp|0x1 # Support Aggressive Link Power Management
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[0]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[1]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[2]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[3]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[4]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[5]|0x0 # Spin Up Device
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTestMode|0x0 # SATA test mode
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[0]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[1]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[2]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[3]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[4]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[5]|0x0 # SATA Topology
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[0]|0x0 # sSATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[1]|0x0 # sSATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[2]|0x0 # sSATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[3]|0x0 # sSATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[4]|0x0 # sSATA Device Type
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[5]|0x0 # sSATA Device Type
+gStructPcdTokenSpaceGuid.PcdSetup.AEPErrorInjEn|0x0 # PMem Error Injection
+gStructPcdTokenSpaceGuid.PcdSetup.ARIEnable|0x1 # ARI Support
+gStructPcdTokenSpaceGuid.PcdSetup.ARIForward|0x0 # ARI Forward
+gStructPcdTokenSpaceGuid.PcdSetup.AntiFlashWearoutSupported|0x0 # Anti Flash Wearout Supported
+gStructPcdTokenSpaceGuid.PcdSetup.ApplicationProfile|0xff # Application Profile Configuration
+gStructPcdTokenSpaceGuid.PcdSetup.BaudRate|0x5
+gStructPcdTokenSpaceGuid.PcdSetup.BiosGuardEnabled|0x0 # BIOS Guard
+gStructPcdTokenSpaceGuid.PcdSetup.BiosGuardPlatformSupported|0x0 # Bios Guard Supported
+gStructPcdTokenSpaceGuid.PcdSetup.BootAllOptions|0x0 # Boot All Options
+gStructPcdTokenSpaceGuid.PcdSetup.BootNetwork|0x0 # Boot to Network
+gStructPcdTokenSpaceGuid.PcdSetup.Ce2LmLoggingEn|0x1 # 2LM Correctable Error Logging in m2mem
+gStructPcdTokenSpaceGuid.PcdSetup.ClearViralStatus|0x0 # Clear Viral Status
+gStructPcdTokenSpaceGuid.PcdSetup.CloakDevHideRegistersOs|0x0 # Cloak Devhide registers from being accessible from OS
+gStructPcdTokenSpaceGuid.PcdSetup.CloakingEn|0x0 # System Cloaking
+gStructPcdTokenSpaceGuid.PcdSetup.ClrExtraTurboVoltage|0x0 # CLR Extra Turbo Voltage
+gStructPcdTokenSpaceGuid.PcdSetup.ClrMaxOcRatio|0x0 # CLR Max OC Ratio
+gStructPcdTokenSpaceGuid.PcdSetup.ClrVoltageMode|0x0 # CLR Voltage Mode
+gStructPcdTokenSpaceGuid.PcdSetup.ClrVoltageOffset|0x0 # CLR Voltage Offset
+gStructPcdTokenSpaceGuid.PcdSetup.ClrVoltageOffsetPrefix|0x0 # Offset Prefix
+gStructPcdTokenSpaceGuid.PcdSetup.ClrVoltageOverride|0x0 # CLR Voltage Override
+gStructPcdTokenSpaceGuid.PcdSetup.ConsoleRedirection|0x1 # Console Redirection
+gStructPcdTokenSpaceGuid.PcdSetup.CoreExtraTurboVoltage|0x0 # Core Extra Turbo Voltage
+gStructPcdTokenSpaceGuid.PcdSetup.CoreMaxOcRatio|0x0 # Core Max OC Ratio
+gStructPcdTokenSpaceGuid.PcdSetup.CoreVoltageMode|0x0 # Core Voltage Mode
+gStructPcdTokenSpaceGuid.PcdSetup.CoreVoltageOffset|0x0 # Core Voltage Offset
+gStructPcdTokenSpaceGuid.PcdSetup.CoreVoltageOffsetPrefix|0x0 # Offset Prefix
+gStructPcdTokenSpaceGuid.PcdSetup.CoreVoltageOverride|0x0 # Core Voltage Override
+gStructPcdTokenSpaceGuid.PcdSetup.CorrMemErrEn|0x1 # Memory Corrected Error
+gStructPcdTokenSpaceGuid.PcdSetup.CpuVccInVoltage|0x167 # CPU VCCin Voltage Level
+gStructPcdTokenSpaceGuid.PcdSetup.CsmiDynamicDisable|0x1 # CSMI Dynamic Disable
+gStructPcdTokenSpaceGuid.PcdSetup.DataBits|0x8 # Data Bits
+gStructPcdTokenSpaceGuid.PcdSetup.DcpmmUncPoison|0x1 # PMem UNC Poison
+gStructPcdTokenSpaceGuid.PcdSetup.DdrtInternalAlertEn|0x1 # PMem Host Alert Policy
+gStructPcdTokenSpaceGuid.PcdSetup.ReservedS2|0x2
+gStructPcdTokenSpaceGuid.PcdSetup.ReservedS1|0x0
+gStructPcdTokenSpaceGuid.PcdSetup.ReservedS3|0x2
+gStructPcdTokenSpaceGuid.PcdSetup.DisableMAerrorLoggingDueToLER|0x1 # LER MA Error Logging
+gStructPcdTokenSpaceGuid.PcdSetup.EdpcEn|0x0 # IIO eDPC Support
+gStructPcdTokenSpaceGuid.PcdSetup.EdpcErrCorMsg|0x1 # IIO eDPC ERR_COR Message
+gStructPcdTokenSpaceGuid.PcdSetup.EdpcInterrupt|0x1 # IIO eDPC Interrupt
+gStructPcdTokenSpaceGuid.PcdSetup.EfiNetworkSupport|0x0 # EFI Network
+gStructPcdTokenSpaceGuid.PcdSetup.ElogCorrErrEn|0x1 # Corrected Error eLog
+gStructPcdTokenSpaceGuid.PcdSetup.ElogMemErrEn|0x1 # Memory Error eLog
+gStructPcdTokenSpaceGuid.PcdSetup.ElogProcErrEn|0x1 # Processor Error eLog
+gStructPcdTokenSpaceGuid.PcdSetup.EmcaCsmiEn|0x2 # EMCA CMCI-SMI Morphing
+gStructPcdTokenSpaceGuid.PcdSetup.EmcaCsmiThreshold|0x0 # EMCA CMCI-SMI Threshold
+gStructPcdTokenSpaceGuid.PcdSetup.EmcaEn|0x1 # EMCA Logging Support
+gStructPcdTokenSpaceGuid.PcdSetup.EmcaIgnOptin|0x0 # Ignore OS EMCA Opt-in
+gStructPcdTokenSpaceGuid.PcdSetup.EmcaMsmiEn|0x2 # EMCA MCE-SMI Enable
+gStructPcdTokenSpaceGuid.PcdSetup.EnableAntiFlashWearout|0x0 # Flash Wear Out Protection
+gStructPcdTokenSpaceGuid.PcdSetup.ExpectedBer|0x7ffffffff # Expected BER
+gStructPcdTokenSpaceGuid.PcdSetup.FanPwmOffset|0x0 # Fan PWM Offset
+gStructPcdTokenSpaceGuid.PcdSetup.FatalErrSpinLoopEn|0x0 # FatalErrDebugHalt
+gStructPcdTokenSpaceGuid.PcdSetup.FilterPll|0x0 # Filter Pll
+gStructPcdTokenSpaceGuid.PcdSetup.FivrEfficiencyEnable|0x1 # FIVR Efficiency Management
+gStructPcdTokenSpaceGuid.PcdSetup.FivrFaultsEnable|0x1 # FIVR Faults
+gStructPcdTokenSpaceGuid.PcdSetup.FlowControl|0x0 # Flow Control
+gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorEn|0x1 # PMem CTLR Errors
+gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorHighPrioritySignal|0x1 # PMem CTLR High Priority Error Signaling
+gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorLowPrioritySignal|0x1 # PMem CTLR Low Priority Error Signaling
+gStructPcdTokenSpaceGuid.PcdSetup.ForceSetup|0x0 # Force Setup
+gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[0]|0x1 # FPK Port 1
+gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[1]|0x1 # FPK Port 2
+gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[2]|0x1 # FPK Port 3
+gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[3]|0x1 # FPK Port 4
+gStructPcdTokenSpaceGuid.PcdSetup.GbeEnabled|0x0 # PCH Internal LAN
+gStructPcdTokenSpaceGuid.PcdSetup.GbePciePortNum|0x0 # PCIE Port assigned to LAN
+gStructPcdTokenSpaceGuid.PcdSetup.Gen12ErrorThreshold|0x0 # Error Threshold (Gen1/2)
+gStructPcdTokenSpaceGuid.PcdSetup.Gen12TimeWindow|0xffff # Time Window (Gen1/2)
+gStructPcdTokenSpaceGuid.PcdSetup.Gen2LinkDegradation|0x1 # Gen2 Link Degradation
+gStructPcdTokenSpaceGuid.PcdSetup.Gen34ErrorThreshold|0x10 # Error Threshold (Gen3/4)
+gStructPcdTokenSpaceGuid.PcdSetup.Gen34ReEqualization|0x1 # Gen3/4 Re-Equalization
+gStructPcdTokenSpaceGuid.PcdSetup.Gen34TimeWindow|0x2 # Time Window (Gen3/4)
+gStructPcdTokenSpaceGuid.PcdSetup.Gen3LinkDegradation|0x1 # Gen3 Link Degradation
+gStructPcdTokenSpaceGuid.PcdSetup.Gen4LinkDegradation|0x1 # Gen4 Link Degradation
+gStructPcdTokenSpaceGuid.PcdSetup.IioDmaErrorEn|0x1 # IIO Dma Error
+gStructPcdTokenSpaceGuid.PcdSetup.IioDmiErrorEn|0x1 # IIO Dmi Error
+gStructPcdTokenSpaceGuid.PcdSetup.IioErrRegistersClearEn|0x1 # IIO Error Registers Clear
+gStructPcdTokenSpaceGuid.PcdSetup.IioErrorEn|0x1 # IIO/PCH Global Error Support
+gStructPcdTokenSpaceGuid.PcdSetup.IioErrorPin0En|0x0 # IIO Error Pin0 Enable
+gStructPcdTokenSpaceGuid.PcdSetup.IioErrorPin1En|0x0 # IIO Error Pin1 Enable
+gStructPcdTokenSpaceGuid.PcdSetup.IioErrorPin2En|0x0 # IIO Error Pin2 Enable
+gStructPcdTokenSpaceGuid.PcdSetup.IioIrpErrorEn|0x1 # IIO Coherent Interface Error
+gStructPcdTokenSpaceGuid.PcdSetup.IioMiscErrorEn|0x1 # IIO Misc. Error
+gStructPcdTokenSpaceGuid.PcdSetup.IioOOBMode|0x1 # IIO OOB Mode
+gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAddCorrErrorEn|0x1 # IIO PCIE Additional Corrected Error
+gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAddRcvComWithUr|0x0 # IIO PCIE Additional Received Completion With UR
+gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAddUnCorrEn|0x1 # IIO PCIE Additional Uncorrected Error
+gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAerSpecCompEn|0x0 # IIO PCIE AER Spec Compliant
+gStructPcdTokenSpaceGuid.PcdSetup.IioSev1Pcc|0x0 # Clear PCC for IIO Non-Fatal Error
+gStructPcdTokenSpaceGuid.PcdSetup.IioVtdErrorEn|0x1 # IIO Vtd Error
+gStructPcdTokenSpaceGuid.PcdSetup.IoMcaEn|0x1 # IIO MCA Support
+gStructPcdTokenSpaceGuid.PcdSetup.IoaVoltageOffset|0x0 # IOA Voltage Offset
+gStructPcdTokenSpaceGuid.PcdSetup.IoaVoltageOffsetPrefix|0x0 # Offset Prefix
+gStructPcdTokenSpaceGuid.PcdSetup.IodVoltageOffset|0x0 # IOD Voltage Offset
+gStructPcdTokenSpaceGuid.PcdSetup.IodVoltageOffsetPrefix|0x0 # Offset Prefix
+gStructPcdTokenSpaceGuid.PcdSetup.ItcOtcCaMaEnable|0x0 # ITC/OTC CA/MA Errors
+gStructPcdTokenSpaceGuid.PcdSetup.KTIFailoverSmiEn|0x0
+gStructPcdTokenSpaceGuid.PcdSetup.KcsAccessPolicy|0x3 # KCS Access Control Policy
+gStructPcdTokenSpaceGuid.PcdSetup.KtiFirstCeLatchEn|0x0 # Latch First Corrected Error in KTI
+gStructPcdTokenSpaceGuid.PcdSetup.LegacyOsRedirection|0x1 # Legacy OS Redirection
+gStructPcdTokenSpaceGuid.PcdSetup.LegacyPxeRom|0x0 # Legacy Option ROMs support
+gStructPcdTokenSpaceGuid.PcdSetup.LerEn|0x0 # IIO LER Support
+gStructPcdTokenSpaceGuid.PcdSetup.LmceEn|0x1 # LMCE Support
+gStructPcdTokenSpaceGuid.PcdSetup.LomDisableByGpio|0x1 # LOM
+gStructPcdTokenSpaceGuid.PcdSetup.MRIOVEnable|0x0 # MR-IOV Support
+gStructPcdTokenSpaceGuid.PcdSetup.McBankWarmBootClearError|0x1 # Mca Bank Warm Boot Clear Errors
+gStructPcdTokenSpaceGuid.PcdSetup.McaBankErrInjEn|0x0 # Mca Bank Error Injection Support
+gStructPcdTokenSpaceGuid.PcdSetup.McaSpinLoop|0x0 # MCA Spin Loop
+gStructPcdTokenSpaceGuid.PcdSetup.MeSegErrorInjEn|0x0 # ME Seg Error Injection Support
+gStructPcdTokenSpaceGuid.PcdSetup.MemErrEn|0x1 # Memory Error
+gStructPcdTokenSpaceGuid.PcdSetup.NgnAddressRangeScrub|0x0 # Set PMem Address Range Scrub
+gStructPcdTokenSpaceGuid.PcdSetup.NgnHostAlertDpa|0x0 # Set PMem Host Alert Policy for DPA Error
+gStructPcdTokenSpaceGuid.PcdSetup.NgnHostAlertPatrolScrubUNC|0x1 # Set PMem Host Alert Policy for Patrol Scrub
+gStructPcdTokenSpaceGuid.PcdSetup.Numlock|0x0 # NumLock
+gStructPcdTokenSpaceGuid.PcdSetup.OsNativeAerSupport|0x0 # Os Native AER Support
+gStructPcdTokenSpaceGuid.PcdSetup.OverclockingSupport|0x0 # OverClocking Feature
+gStructPcdTokenSpaceGuid.PcdSetup.Parity|0x1 # Parity
+gStructPcdTokenSpaceGuid.PcdSetup.PatrolScrubErrorReporting|0x1 # Patrol Scrub Error Reporting
+gStructPcdTokenSpaceGuid.PcdSetup.PchStepping|0x0 # PCH Stepping
+gStructPcdTokenSpaceGuid.PcdSetup.PcieAerAdNfatErrEn|0x1 # PCIE AER Advisory Nonfatal Error
+gStructPcdTokenSpaceGuid.PcdSetup.PcieAerCorrErrEn|0x1 # PCIE AER Corrected Errors
+gStructPcdTokenSpaceGuid.PcdSetup.PcieAerEcrcEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PcieAerFatErrEn|0x1 # PCIE AER Fatal Error
+gStructPcdTokenSpaceGuid.PcdSetup.PcieAerNfatErrEn|0x1 # PCIE AER NonFatal Error
+gStructPcdTokenSpaceGuid.PcdSetup.PcieAerSurpriseLinkDownEn|0x0 # PCIE Surprise Link Down Error
+gStructPcdTokenSpaceGuid.PcdSetup.PcieAerUreEn|0x0 # PCIE Unsupported Request Error
+gStructPcdTokenSpaceGuid.PcdSetup.PcieClockGatingDisabled|0x0 # PCIE Clock Gating
+gStructPcdTokenSpaceGuid.PcdSetup.PcieCorErrCntr|0x0 # PCIE Corrected Error Threshold Counter
+gStructPcdTokenSpaceGuid.PcdSetup.PcieCorErrLimit|0x50 # PCIe Corrected Error Limit
+gStructPcdTokenSpaceGuid.PcdSetup.PcieCorErrLimitEn|0x0 # PCIe Corrected Error Limit Check
+gStructPcdTokenSpaceGuid.PcdSetup.PcieCorErrThres|0x1 # PCIE Corrected Error Threshold
+gStructPcdTokenSpaceGuid.PcdSetup.PcieCorrErrEn|0x1 # Corrected Error
+gStructPcdTokenSpaceGuid.PcdSetup.PcieDmiAspm|0x0 # PCH DMI ASPM
+gStructPcdTokenSpaceGuid.PcdSetup.PcieErrEn|0x1 # PCIE Error
+gStructPcdTokenSpaceGuid.PcdSetup.PcieErrInjActionTable|0x0 # Whea PCIe Error Injection Action Table
+gStructPcdTokenSpaceGuid.PcdSetup.PcieFatalErrEn|0x1 # Fatal Error Enable
+gStructPcdTokenSpaceGuid.PcdSetup.PcieUncorrErrEn|0x1 # Uncorrected Error
+gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfmActiveMajorVersion|0x0 # BMC PFM Active Major Version
+gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfmActiveMinorVersion|0x0 # BMC PFM Active Minor Version
+gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfmRecoveryMajorVersion|0x0 # BMC PFM Recovery Major Version
+gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfmRecoveryMinorVersion|0x0 # BMC PFM Recovery Minor Version
+gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfrActiveSvn|0x0 # BMC PFR Active SVN
+gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfrRecoverySvn|0x0 # BMC PFR Recovery SVN
+gStructPcdTokenSpaceGuid.PcdSetup.PfrCpldRotReleaseVersion|0x0 # CPLD RoT Release Version
+gStructPcdTokenSpaceGuid.PcdSetup.PfrCpldRotSvn|0x0 # CPLD RoT SVN
+gStructPcdTokenSpaceGuid.PcdSetup.PfrLock|0x0 # PFR Lock
+gStructPcdTokenSpaceGuid.PcdSetup.PfrLockStatus|0x0 # PFR Status: Locked
+gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfmActiveMajorVersion|0x0 # PCH PFM Active Major Version
+gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfmActiveMinorVersion|0x0 # PCH PFM Active Minor Version
+gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfmRecoveryMajorVersion|0x0 # PCH PFM Recovery Major Version
+gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfmRecoveryMinorVersion|0x0 # PCH PFM Recovery Minor Version
+gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfrActiveSvn|0x0 # PCH PFR Active SVN
+gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfrRecoverySvn|0x0 # PCH PFR Recovery SVN
+gStructPcdTokenSpaceGuid.PcdSetup.PfrPitL1|0x0 # PFR PIT Level-1 Protection
+gStructPcdTokenSpaceGuid.PcdSetup.PfrPitL1Status|0x0 # PFR Status: PIT Level-1 Protection Enabled
+gStructPcdTokenSpaceGuid.PcdSetup.PfrPitL2|0x0 # PFR PIT Level-2 Protection
+gStructPcdTokenSpaceGuid.PcdSetup.PfrPitL2Status|0x0 # PFR Status: PIT Level-2 Protection Enabled
+gStructPcdTokenSpaceGuid.PcdSetup.PfrProvision|0x0 # PFR Provision
+gStructPcdTokenSpaceGuid.PcdSetup.PfrProvisionStatus|0x0 # PFR Status: Provisioned
+gStructPcdTokenSpaceGuid.PcdSetup.PfrSupported|0x0 # PFR Supported
+gStructPcdTokenSpaceGuid.PcdSetup.PfrUnProvision|0x0 # PFR UnProvision
+gStructPcdTokenSpaceGuid.PcdSetup.PlatformOCSupport|0x0 # Platform Over Clocking Support
+gStructPcdTokenSpaceGuid.PcdSetup.PmsbRouterParityErrEn|0x1 # PMSB Router Parity Error
+gStructPcdTokenSpaceGuid.PcdSetup.PoisonEn|0x1 # System Memory Poison
+gStructPcdTokenSpaceGuid.PcdSetup.PropagatePerr|0x1 # Assert NMI on PERR
+gStructPcdTokenSpaceGuid.PcdSetup.PropagateSerr|0x1 # Assert NMI on SERR
+gStructPcdTokenSpaceGuid.PcdSetup.Ps2PortSwap|0x0 # PS2 Port Swap
+gStructPcdTokenSpaceGuid.PcdSetup.PsfUrEnable|0x1 # PSF UR Error
+gStructPcdTokenSpaceGuid.PcdSetup.PublishSetupPgPtr|0x0 # Publish Setup page Pointer
+gStructPcdTokenSpaceGuid.PcdSetup.RTCWakeupTimeHour|0x0 # Wake up hour
+gStructPcdTokenSpaceGuid.PcdSetup.RTCWakeupTimeMinute|0x0 # Wake up minute
+gStructPcdTokenSpaceGuid.PcdSetup.RTCWakeupTimeSecond|0x0 # Wake up second
+gStructPcdTokenSpaceGuid.PcdSetup.RasLogLevel|0x1 # RAS Log Level
+gStructPcdTokenSpaceGuid.PcdSetup.ReportAlertSPA|0x1 # Enable Reporting SPA to OS
+gStructPcdTokenSpaceGuid.PcdSetup.ReserveMem|0x0 # Reserve Memory Range
+gStructPcdTokenSpaceGuid.PcdSetup.ReserveStartAddr|0x100000 # Start Address
+gStructPcdTokenSpaceGuid.PcdSetup.ResetOnMemMapChange|0x0 # Reset Platform on Memory Map Change
+gStructPcdTokenSpaceGuid.PcdSetup.RsaSupport|0x0 # RSA Support
+gStructPcdTokenSpaceGuid.PcdSetup.SRIOVEnable|0x1 # SR-IOV Support
+gStructPcdTokenSpaceGuid.PcdSetup.SerialBaudRate|0x1c200 # BIOS Serial Port Baud Rate
+gStructPcdTokenSpaceGuid.PcdSetup.SetShellFirst|0x0 # Boot Shell First
+gStructPcdTokenSpaceGuid.PcdSetup.SgxErrorInjEn|0x0 # SGX Memory Error Injection Support
+gStructPcdTokenSpaceGuid.PcdSetup.ShellEntryTime|0x5 # System Shell Timeout
+gStructPcdTokenSpaceGuid.PcdSetup.ShutdownSuppression|0x0 # Shutdown Suppression
+gStructPcdTokenSpaceGuid.PcdSetup.SkipXmlComprs|0x0 # Skip XML Compression
+gStructPcdTokenSpaceGuid.PcdSetup.SpareIntSelect|0x1 # Spare Interrupt
+gStructPcdTokenSpaceGuid.PcdSetup.StopBits|0x1 # Stop Bits
+gStructPcdTokenSpaceGuid.PcdSetup.StorageOpROMSuppression|0x0 # Storage OPROM Suppression
+gStructPcdTokenSpaceGuid.PcdSetup.SvidEnable|0x1 # SVID Support
+gStructPcdTokenSpaceGuid.PcdSetup.SvidVoltageOverride|0x0 # SVID Voltage Override
+gStructPcdTokenSpaceGuid.PcdSetup.SystemErrorEn|0x1 # System Errors
+gStructPcdTokenSpaceGuid.PcdSetup.SystemPageSize|0x0 # SR-IOV SystemPageSize
+gStructPcdTokenSpaceGuid.PcdSetup.TagecMem|0x0 # Reserve TAGEC Memory
+gStructPcdTokenSpaceGuid.PcdSetup.TerminalResolution|0x0 # Terminal Resolution
+gStructPcdTokenSpaceGuid.PcdSetup.TerminalType|0x2 # Terminal Type
+gStructPcdTokenSpaceGuid.PcdSetup.UboxErrorMask|0x0 # Ubox Error Mask
+gStructPcdTokenSpaceGuid.PcdSetup.UboxToPcuMcaEn|0x1 # UboxToPcuMca Enabling
+gStructPcdTokenSpaceGuid.PcdSetup.UncoreVoltageOffset|0x0 # Uncore Voltage Offset
+gStructPcdTokenSpaceGuid.PcdSetup.UncoreVoltageOffsetPrefix|0x0 # Offset Prefix
+gStructPcdTokenSpaceGuid.PcdSetup.UsbEmul6064|0x0 # Port 60/64 Emulation
+gStructPcdTokenSpaceGuid.PcdSetup.UsbLegacySupport|0x0 # Legacy USB Support
+gStructPcdTokenSpaceGuid.PcdSetup.UsbMassResetDelay|0x1 # Device Reset timeout
+gStructPcdTokenSpaceGuid.PcdSetup.UsbNonBoot|0x0 # Make USB Devices Non-Bootable
+gStructPcdTokenSpaceGuid.PcdSetup.Use1GPageTable|0x1 # Max Page Table Size Select
+gStructPcdTokenSpaceGuid.PcdSetup.ValidationBreakpointType|0x0 # Breakpoint Type
+gStructPcdTokenSpaceGuid.PcdSetup.VccIoVoltage|0x0 # VccIo Voltage Control
+gStructPcdTokenSpaceGuid.PcdSetup.VideoSelect|0x0 # Active Video
+gStructPcdTokenSpaceGuid.PcdSetup.ViralEn|0x0 # Viral Status
+gStructPcdTokenSpaceGuid.PcdSetup.WakeOnLanS5|0x0 # Wake On Lan from S5
+gStructPcdTokenSpaceGuid.PcdSetup.WakeOnLanSupport|0x0 # Wake On Lan Support
+gStructPcdTokenSpaceGuid.PcdSetup.WakeOnRTCS4S5|0x0 # RTC Wake system from S4/S5
+gStructPcdTokenSpaceGuid.PcdSetup.WheaErrInjEn|0x1 # WHEA Error Injection 5.0 Extension
+gStructPcdTokenSpaceGuid.PcdSetup.WheaErrorInjSupportEn|0x0 # WHEA Error Injection Support
+gStructPcdTokenSpaceGuid.PcdSetup.WheaLogMemoryEn|0x1 # Whea Log Memory Error
+gStructPcdTokenSpaceGuid.PcdSetup.WheaLogPciEn|0x1 # Whea Log PCI Error
+gStructPcdTokenSpaceGuid.PcdSetup.WheaLogProcEn|0x1 # Whea Log Processor Error
+gStructPcdTokenSpaceGuid.PcdSetup.WheaPcieErrInjEn|0x0 # Whea PCIE Error Injection Support
+gStructPcdTokenSpaceGuid.PcdSetup.WheaSupportEn|0x1 # WHEA Support
+gStructPcdTokenSpaceGuid.PcdSetup.XhciWakeOnUsbEnabled|0x1 # XHCI Wake On Usb Enable
+gStructPcdTokenSpaceGuid.PcdSetup.XmlCliSupport|0x1 # Xml Cli Support
+gStructPcdTokenSpaceGuid.PcdSetup.bsdBreakpoint|0x0 # BsdBreakPoint
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_crreccCs0|0x1 # IIO IRP0 wrcache correcccs0 error
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_crreccCs1|0x1 # IIO IRP0 wrcache correcccs1 error
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_csraccunaligned|0x1 # IIO IRP0 csr acc 32b unaligned
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_parityError|0x1 # IIO IRP0 protocol parity error
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_qtOverflow|0x1 # IIO IRP0 protocol qt overflow underflow error
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_rcvdpoison|0x1 # IIO IRP0 protocol rcvd poison error
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unceccCs0|0x1 # IIO IRP0 wrcache uncecccs0 error
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unceccCs1|0x1 # IIO IRP0 wrcache uncecccs1 error
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unexprsp|0x1 # IIO IRP0 protocol rcvd unexprsp
+gStructPcdTokenSpaceGuid.PcdSetup.serialDebugTrace|0x0 # Trace Messages
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS8|0x0
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[0]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[1]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[2]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[3]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[4]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[5]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[6]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[7]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[8]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[9]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[10]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[11]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[12]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[13]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[14]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[15]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[16]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[17]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[18]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[19]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[20]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[21]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[22]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[23]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[24]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[25]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[26]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[27]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[28]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[29]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[30]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[31]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS6|0xf
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.IsocEn|0x2 # Isoc Mode
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MirrorMode|0x0 # Mirror Mode
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmcfgBase|0x6 # MMCFG Base
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmcfgSize|0x6 # MMCFG Size
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmiohBase|0x2 # MMIO High Base
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmiohSize|0x3 # MMIO High Granularity Size
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.NumaEn|0x1 # Numa
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.SystemRasType|0x0 # System RAS Type
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.UmaBasedClustering|0x2 # UMA-Based Clustering
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.VirtualNumaEnable|0x0 # Virtual Numa
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[1]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[2]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[3]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[4]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[5]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[6]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[7]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[8]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[9]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[10]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[11]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[12]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[13]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[14]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[15]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[16]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[17]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[18]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[19]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[20]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[21]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[22]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[23]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[24]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[25]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[26]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[27]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[28]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[29]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[30]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[31]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[32]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[33]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[34]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[35]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[36]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[37]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[38]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[39]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[40]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[41]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[42]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[43]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[44]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[45]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[46]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[47]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[48]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[49]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[50]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[51]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[52]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[53]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[54]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[55]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[56]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[57]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[58]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[59]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[60]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[61]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[62]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[63]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[64]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[65]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[66]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[67]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[68]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[69]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[70]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[71]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[72]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[73]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[74]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[75]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[76]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[77]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[78]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[79]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[80]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[81]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[82]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[83]|0x0 # HotPlug ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[1]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[2]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[3]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[4]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[5]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[6]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[7]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[8]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[9]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[10]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[11]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[12]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[13]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[14]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[15]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[16]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[17]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[18]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[19]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[20]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[21]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[22]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[23]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[24]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[25]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[26]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[27]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[28]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[29]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[30]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[31]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[32]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[33]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[34]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[35]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[36]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[37]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[38]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[39]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[40]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[41]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[42]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[43]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[44]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[45]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[46]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[47]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[48]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[49]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[50]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[51]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[52]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[53]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[54]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[55]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[56]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[57]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[58]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[59]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[60]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[61]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[62]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[63]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[64]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[65]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[66]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[67]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[68]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[69]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[70]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[71]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[72]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[73]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[74]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[75]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[76]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[77]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[78]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[79]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[80]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[81]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[82]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[83]|0x0 # PM ACPI Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[0]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[1]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[2]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[3]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[4]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[5]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[6]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[7]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[8]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[9]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[10]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[11]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[12]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[13]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[14]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[15]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[16]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[17]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[18]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[19]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[20]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[21]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[22]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[23]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[24]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[25]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[26]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[27]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[28]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[29]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[30]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[31]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[32]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[33]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[34]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[35]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[36]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[37]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[38]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[39]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[40]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[41]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[42]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[43]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[44]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[45]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[46]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[47]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[48]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[49]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[50]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[51]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[52]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[53]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[54]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[55]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[56]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[57]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[58]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[59]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[60]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[61]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[62]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[63]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[64]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[65]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[66]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[67]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[68]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[69]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[70]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[71]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[72]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[73]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[74]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[75]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[76]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[77]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[78]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[79]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[80]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[81]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[82]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[83]|0x0 # ACPI PME Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ATS|0x1 # ATS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[0]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[1]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[2]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[3]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[4]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[5]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[6]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[7]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[8]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[9]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[10]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[11]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[12]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[13]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[14]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[15]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[16]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[17]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[18]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[19]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[20]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[21]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[22]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[23]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[24]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[25]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[26]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[27]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[28]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[29]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[30]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[31]|0x1 # DMA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[0]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[1]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[2]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[3]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[4]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[5]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[6]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[7]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[8]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[9]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[10]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[11]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[12]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[13]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[14]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[15]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[16]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[17]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[18]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[19]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[20]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[21]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[22]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[23]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[24]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[25]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[26]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[27]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[28]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[29]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[30]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[31]|0x0 # No Snoop
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CbDmaMultiCastEnable|0x1 # CbDma MultiCast Enable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CbRelaxedOrdering|0x0 # Relaxed Ordering
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CoherencySupport|0x1 # Coherency Support (Non-Isoch)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CoherentReadFull|0x0 # PCIE Coherent Read Full
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CoherentReadPart|0x0 # PCIE Coherent Read Partial
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobal|0x1 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobalValue|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[0]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[1]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[2]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[3]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[0]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[1]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[2]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[3]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[4]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[5]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[6]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[7]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[8]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[9]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[10]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[11]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[12]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[13]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[14]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[15]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[16]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[17]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[18]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[19]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[20]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[21]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[22]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[23]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[24]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[25]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[26]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[27]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[28]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[29]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[30]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[31]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[32]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[33]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[34]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[35]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[36]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[37]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[38]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[39]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[40]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[41]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[42]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[43]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[44]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[45]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[46]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[47]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[48]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[49]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[50]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[51]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[52]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[53]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[54]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[55]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[56]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[57]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[58]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[59]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[60]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[61]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[62]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[63]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[64]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[65]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[66]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[67]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[68]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[69]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[70]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[71]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[72]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[73]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[74]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[75]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[76]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[77]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[78]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[79]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[80]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[81]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[82]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[83]|0x0 # Compliance Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[0]|0xff # IOU0 (IIO PCIe Port 1)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[1]|0xff # IOU0 (IIO PCIe Port 1)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[2]|0xff # IOU0 (IIO PCIe Port 1)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[3]|0xff # IOU0 (IIO PCIe Port 1)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[0]|0xff # IOU1 (IIO PCIe Port 2)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[1]|0xff # IOU1 (IIO PCIe Port 2)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[2]|0xff # IOU1 (IIO PCIe Port 2)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[3]|0xff # IOU1 (IIO PCIe Port 2)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[0]|0xff # IOU2 (IIO PCIe Port 3)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[1]|0xff # IOU2 (IIO PCIe Port 3)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[2]|0xff # IOU2 (IIO PCIe Port 3)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[3]|0xff # IOU2 (IIO PCIe Port 3)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[0]|0xff # IOU3 (IIO PCIe Port 4)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[1]|0xff # IOU3 (IIO PCIe Port 4)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[2]|0xff # IOU3 (IIO PCIe Port 4)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[3]|0xff # IOU3 (IIO PCIe Port 4)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[0]|0xff # IOU4 (IIO PCIe Port 5)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[1]|0xff # IOU4 (IIO PCIe Port 5)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[2]|0xff # IOU4 (IIO PCIe Port 5)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[3]|0xff # IOU4 (IIO PCIe Port 5)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ControlIommu|0x0 # Pre-boot DMA Protection
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS9|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[0]|0x0 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[1]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[2]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[3]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[4]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[5]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[6]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[7]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[8]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[9]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[10]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[11]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[12]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[13]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[14]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[15]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[16]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[17]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[18]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[19]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[20]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[21]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[22]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[23]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[24]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[25]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[26]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[27]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[28]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[29]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[30]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[31]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[32]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[33]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[34]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[35]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[36]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[37]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[38]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[39]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[40]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[41]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[42]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[43]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[44]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[45]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[46]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[47]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[48]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[49]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[50]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[51]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[52]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[53]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[54]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[55]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[56]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[57]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[58]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[59]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[60]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[61]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[62]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[63]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[64]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[65]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[66]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[67]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[68]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[69]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[70]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[71]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[72]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[73]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[74]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[75]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[76]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[77]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[78]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[79]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[80]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[81]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[82]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[83]|0x1 # PCI-E Port DeEmphasis
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DelayBeforePCIeLinkTraining|0x0 # Delay before link training
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[0]|0x0 # IIO IOAPIC Stack 0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS19|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS10|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[0]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[1]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[2]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[3]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[4]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[5]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[6]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[7]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[8]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[9]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[10]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[11]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[12]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[13]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[14]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[15]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[16]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[17]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[18]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[19]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[20]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[21]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[22]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[23]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[24]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[25]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[26]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[27]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[28]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[29]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[30]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[31]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[32]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[33]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[34]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[35]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[36]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[37]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[38]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[39]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[40]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[41]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[42]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[43]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[44]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[45]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[46]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[47]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[48]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[49]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[50]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[51]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[52]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[53]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[54]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[55]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[56]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[57]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[58]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[59]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[60]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[61]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[62]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[63]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[64]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[65]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[66]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[67]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[68]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[69]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[70]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[71]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[72]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[73]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[74]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[75]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[76]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[77]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[78]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[79]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[80]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[81]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[82]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[83]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[0]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[1]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[2]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[3]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[4]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[5]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[6]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[7]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[8]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[9]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[10]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[11]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[12]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[13]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[14]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[15]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[16]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[17]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[18]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[19]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[20]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[21]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[22]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[23]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[24]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[25]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[26]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[27]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[28]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[29]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[30]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[31]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[32]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[33]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[34]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[35]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[36]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[37]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[38]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[39]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[40]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[41]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[42]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[43]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[44]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[45]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[46]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[47]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[48]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[49]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[50]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[51]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[52]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[53]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[54]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[55]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[56]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[57]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[58]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[59]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[60]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[61]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[62]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[63]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[64]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[65]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[66]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[67]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[68]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[69]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[70]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[71]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[72]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[73]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[74]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[75]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[76]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[77]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[78]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[79]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[80]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[81]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[82]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS42[83]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[30]|0x18
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[42]|0x29
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[48]|0x18
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[60]|0x18
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[72]|0x18
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[66]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[67]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[68]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[69]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[70]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[71]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[72]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[73]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[74]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[76]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[77]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[78]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[79]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[80]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[81]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[82]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[83]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[0]|0xb
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[2]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[27]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[33]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[35]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[36]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[37]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[38]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[39]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[40]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[41]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[42]|0xb
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[44]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[45]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[46]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[47]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[48]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[49]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[50]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[51]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[52]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[53]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[54]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[55]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[56]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[57]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[58]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[59]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[60]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[61]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[62]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[63]|0xb
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[64]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[65]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[66]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[67]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[68]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[69]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[70]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[71]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[72]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[73]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[74]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[75]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[76]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[77]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[78]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[79]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[80]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[81]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[82]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[83]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[0]|0x29
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[63]|0x29
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[5]|0xb
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[7]|0xb
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[9]|0xb
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[13]|0xb
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[14]|0xb
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[16]|0xb
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[17]|0xb
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[18]|0xb
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[19]|0xb
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[20]|0xb
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[21]|0xb
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[22]|0xb
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[23]|0xb
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[24]|0xb
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[0]|0xb
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[26]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[30]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[65]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[66]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[67]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[68]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[69]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[70]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[71]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[72]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[73]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[74]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[75]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[76]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[77]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[78]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[79]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[80]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[82]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS23[83]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[0]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[4]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[5]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[6]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[7]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[8]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[9]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[10]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[11]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[12]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[13]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[15]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[16]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[18]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[20]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[21]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[22]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[23]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[24]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[25]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[26]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[27]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[28]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[29]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[30]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[33]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[34]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[35]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[36]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[37]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[38]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[39]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[40]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[41]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[42]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[43]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[44]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[45]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[46]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[47]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[48]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[49]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[50]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[51]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[52]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[53]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[54]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS24[55]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS33[64]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS33[65]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS33[66]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS33[70]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS33[76]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS33[77]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS33[78]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS33[80]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS38[13]|0xb
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[30]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[66]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[67]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[68]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[69]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[70]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[71]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[72]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[74]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[75]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[76]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[77]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[78]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[79]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[80]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[81]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[82]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS31[83]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[3]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[4]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[5]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[6]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[7]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[8]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[9]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[10]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[11]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[12]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[13]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[14]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[15]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[16]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[17]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[18]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[19]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[20]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[23]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[24]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[25]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[26]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[27]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[28]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[29]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[30]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[31]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[32]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[33]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[34]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[37]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[38]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[39]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[40]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[41]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[43]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[44]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[45]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[46]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[47]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[48]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[49]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[50]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[51]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[52]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[53]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[54]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[55]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[56]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[57]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[58]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[59]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[60]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS32[61]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS16|0x2
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[53]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[54]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[57]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[68]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[69]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[70]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[71]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[72]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[74]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[75]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[76]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[77]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[78]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[79]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[80]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[81]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[82]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[83]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[84]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[85]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[86]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[251]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[252]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[253]|0x0
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[255]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[0]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[36]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[37]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[38]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[40]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[42]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[44]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[46]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[47]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[53]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[54]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[55]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[56]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[59]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[62]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[63]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[64]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[65]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[66]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[67]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[68]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[69]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[71]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[72]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[75]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[76]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[77]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[78]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[79]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[80]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[81]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[82]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[83]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[0]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[13]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[17]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[21]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[22]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[23]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[24]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[25]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[26]|0xff
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[28]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[29]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[30]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[31]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[32]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[33]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[34]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[35]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[36]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[37]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[38]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[39]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[40]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[41]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[42]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[43]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[44]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[45]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[46]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[47]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[48]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[49]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[50]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[51]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[52]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[53]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[54]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[55]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[56]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[57]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[58]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[59]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[60]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[61]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[62]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[63]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[64]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[65]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[66]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[67]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[68]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[69]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[70]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[71]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[72]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[73]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[74]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[75]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[76]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[77]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[78]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[79]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[80]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[81]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[82]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[83]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[0]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[1]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[2]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[3]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[4]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[5]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[6]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[7]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[8]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[9]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[10]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[11]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[12]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[13]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[14]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[15]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[16]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[17]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[18]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[19]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[20]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[21]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[22]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[23]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[24]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[25]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[26]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[27]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[28]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[29]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[30]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[31]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[32]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[33]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[34]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[35]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[36]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[37]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[38]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[39]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[40]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[41]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[42]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[43]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[44]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[45]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[46]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[47]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[48]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[49]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[50]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[51]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[52]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[53]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[54]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[55]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[56]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[57]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[58]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[59]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[60]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[61]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[62]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[63]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[64]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[65]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[66]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[67]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[68]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[69]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[70]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[71]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[72]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[73]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[74]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[75]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[76]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[77]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[78]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[79]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[80]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[81]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[82]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[83]|0x0 # PME to ACK
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisableTPH|0x0 # Disable TPH
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DmaCtrlOptIn|0x0 # DMA Control Opt-In Flag
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DmiAllocatingFlow|0x1 # DMI Allocating Write Flows
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DualCvIoFlow|0x1 # Dual CV IO Flow
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EN1K|0x0 # EN1K
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[0]|0x1 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[1]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[2]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[3]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[4]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[5]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[6]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[7]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[8]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[9]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[10]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[11]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[12]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[13]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[14]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[15]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[16]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[17]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[18]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[19]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[20]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[21]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[22]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[23]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[24]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[25]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[26]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[27]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[28]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[29]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[30]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[31]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[32]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[33]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[34]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[35]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[36]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[37]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[38]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[39]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[40]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[41]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[42]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[43]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[44]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[45]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[46]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[47]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[48]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[49]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[50]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[51]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[52]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[53]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[54]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[55]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[56]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[57]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[58]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[59]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[60]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[61]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[62]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[63]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[64]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[65]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[66]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[67]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[68]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[69]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[70]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[71]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[72]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[73]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[74]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[75]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[76]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[77]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[78]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[79]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[80]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[81]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[82]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[83]|0x0 # EOI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[0]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[1]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[2]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[3]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[4]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[5]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[6]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[7]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[8]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[9]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[10]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[11]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[12]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[13]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[14]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[15]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[16]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[17]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[18]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[19]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[20]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[21]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[22]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[23]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[24]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[25]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[26]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[27]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[28]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[29]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[30]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[31]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[32]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[33]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[34]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[35]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[36]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[37]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[38]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[39]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[40]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[41]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[42]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[43]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[44]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[45]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[46]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[47]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[48]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[49]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[50]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[51]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[52]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[53]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[54]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[55]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[56]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[57]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[58]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[59]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[60]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[61]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[62]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[63]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[64]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[65]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[66]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[67]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[68]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[69]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[70]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[71]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[72]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[73]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[74]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[75]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[76]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[77]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[78]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[79]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[80]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[81]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[82]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[83]|0x0 # ECRC Check
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[0]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[1]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[2]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[3]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[4]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[5]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[6]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[7]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[8]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[9]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[10]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[11]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[12]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[13]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[14]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[15]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[16]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[17]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[18]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[19]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[20]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[21]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[22]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[23]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[24]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[25]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[26]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[27]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[28]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[29]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[30]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[31]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[32]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[33]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[34]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[35]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[36]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[37]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[38]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[39]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[40]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[41]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[42]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[43]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[44]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[45]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[46]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[47]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[48]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[49]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[50]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[51]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[52]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[53]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[54]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[55]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[56]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[57]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[58]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[59]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[60]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[61]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[62]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[63]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[64]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[65]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[66]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[67]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[68]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[69]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[70]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[71]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[72]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[73]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[74]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[75]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[76]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[77]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[78]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[79]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[80]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[81]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[82]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[83]|0x0 # ECRC Generation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[0]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[1]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[2]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[3]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[4]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[5]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[6]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[7]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[8]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[9]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[10]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[11]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[12]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[13]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[14]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[15]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[16]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[17]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[18]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[19]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[20]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[21]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[22]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[23]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[24]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[25]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[26]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[27]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[28]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[29]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[30]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[31]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[32]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[33]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[34]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[35]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[36]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[37]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[38]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[39]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[40]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[41]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[42]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[43]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[44]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[45]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[46]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[47]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[48]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[49]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[50]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[51]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[52]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[53]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[54]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[55]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[56]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[57]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[58]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[59]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[60]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[61]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[62]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[63]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[64]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[65]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[66]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[67]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[68]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[69]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[70]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[71]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[72]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[73]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[74]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[75]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[76]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[77]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[78]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[79]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[80]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[81]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[82]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[83]|0x0 # PCI-E Extended Sync
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.GlobalPme2AckTOCtrl|0x0 # PME2ACK Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HaltOnDmiDegraded|0x0 # Skip Halt On DMI Degradation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[0]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[1]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[2]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[3]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[4]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[5]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[6]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[7]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[8]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[9]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[10]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[11]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[12]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[13]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[14]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[15]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[16]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[17]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[18]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[19]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[20]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[21]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[22]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[23]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[24]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[25]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[26]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[27]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[28]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[29]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[30]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[31]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[32]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[33]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[34]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[35]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[36]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[37]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[38]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[39]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[40]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[41]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[42]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[43]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[44]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[45]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[46]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[47]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[48]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[49]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[50]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[51]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[52]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[53]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[54]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[55]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[56]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[57]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[58]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[59]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[60]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[61]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[62]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[63]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[64]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[65]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[66]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[67]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[68]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[69]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[70]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[71]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[72]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[73]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[74]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[75]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[76]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[77]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[78]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[79]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[80]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[81]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[82]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[83]|0x6 # IODC Configuration
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[0]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[1]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[2]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[3]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[4]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[5]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[6]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[7]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[8]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[9]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[10]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[11]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[12]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[13]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[14]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[15]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[16]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[17]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[18]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[19]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[20]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[21]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[22]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[23]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[24]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[25]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[26]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[27]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[28]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[29]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[30]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[31]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[32]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[33]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[34]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[35]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[36]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[37]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[38]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[39]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[40]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[41]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[42]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[43]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[44]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[45]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[46]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[47]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[48]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[49]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[50]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[51]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[52]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[53]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[54]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[55]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[56]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[57]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[58]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[59]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[60]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[61]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[62]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[63]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[64]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[65]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[66]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[67]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[68]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[69]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[70]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[71]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[72]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[73]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[74]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[75]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[76]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[77]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[78]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[79]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[80]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[81]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[82]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[83]|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.InterruptRemap|0x2 # Interrupt Remapping
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[0]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[1]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[2]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[3]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[4]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[5]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[6]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[7]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[8]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[9]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[10]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[11]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[12]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[13]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[14]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[15]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[16]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[17]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[18]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[19]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[20]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[21]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[22]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[23]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[24]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[25]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[26]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[27]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[28]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[29]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[30]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[31]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[32]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[33]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[34]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[35]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[36]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[37]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[38]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[39]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[40]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[41]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[42]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[43]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[44]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[45]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[46]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[47]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[48]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[49]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[50]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[51]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[52]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[53]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[54]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[55]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[56]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[57]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[58]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[59]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[60]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[61]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[62]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[63]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[64]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[65]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[66]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[67]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[68]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[69]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[70]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[71]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[72]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[73]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[74]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[75]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[76]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[77]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[78]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[79]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[80]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[81]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[82]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[83]|0x0 # Corr Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[0]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[1]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[2]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[3]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[4]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[5]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[6]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[7]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[8]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[9]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[10]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[11]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[12]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[13]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[14]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[15]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[16]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[17]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[18]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[19]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[20]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[21]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[22]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[23]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[24]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[25]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[26]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[27]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[28]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[29]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[30]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[31]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[32]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[33]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[34]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[35]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[36]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[37]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[38]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[39]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[40]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[41]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[42]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[43]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[44]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[45]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[46]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[47]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[48]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[49]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[50]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[51]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[52]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[53]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[54]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[55]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[56]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[57]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[58]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[59]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[60]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[61]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[62]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[63]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[64]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[65]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[66]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[67]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[68]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[69]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[70]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[71]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[72]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[73]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[74]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[75]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[76]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[77]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[78]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[79]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[80]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[81]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[82]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[83]|0x0 # Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[0]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[1]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[2]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[3]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[4]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[5]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[6]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[7]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[8]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[9]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[10]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[11]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[12]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[13]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[14]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[15]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[16]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[17]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[18]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[19]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[20]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[21]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[22]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[23]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[24]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[25]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[26]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[27]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[28]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[29]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[30]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[31]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[32]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[33]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[34]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[35]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[36]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[37]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[38]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[39]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[40]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[41]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[42]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[43]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[44]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[45]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[46]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[47]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[48]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[49]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[50]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[51]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[52]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[53]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[54]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[55]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[56]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[57]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[58]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[59]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[60]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[61]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[62]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[63]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[64]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[65]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[66]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[67]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[68]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[69]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[70]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[71]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[72]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[73]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[74]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[75]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[76]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[77]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[78]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[79]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[80]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[81]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[82]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[83]|0x0 # Non-Fatal Err Over
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MaxReadCompCombSize|0x0 # Max Read Comp Comb Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.McastBaseAddrRegion|0x0 # MC BaseAddress Range
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.McastIndexPosition|0xc # MC Index Position
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.McastNumGroup|0x8 # MC Num Group
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[0]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[1]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[2]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[3]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[4]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[5]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[6]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[7]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[8]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[9]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[10]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[11]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[12]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[13]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[14]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[15]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[16]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[17]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[18]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[19]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[20]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[21]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[22]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[23]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[24]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[25]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[26]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[27]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[28]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[29]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[30]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[31]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[32]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[33]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[34]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[35]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[36]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[37]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[38]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[39]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[40]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[41]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[42]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[43]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[44]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[45]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[46]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[47]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[48]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[49]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[50]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[51]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[52]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[53]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[54]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[55]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[56]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[57]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[58]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[59]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[60]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[61]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[62]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[63]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[64]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[65]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[66]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[67]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[68]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[69]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[70]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[71]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[72]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[73]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[74]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[75]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[76]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[77]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[78]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[79]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[80]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[81]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[82]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[83]|0x1 # MCTP
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[0]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[1]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[2]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[3]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[4]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[5]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[6]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[7]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[8]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[9]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[10]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[11]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[12]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[13]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[14]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[15]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[16]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[17]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[18]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[19]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[20]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[21]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[22]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[23]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[24]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[25]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[26]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[27]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[28]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[29]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[30]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[31]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[32]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[33]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[34]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[35]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[36]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[37]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[38]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[39]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[40]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[41]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[42]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[43]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[44]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[45]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[46]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[47]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[48]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[49]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[50]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[51]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[52]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[53]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[54]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[55]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[56]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[57]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[58]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[59]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[60]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[61]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[62]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[63]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[64]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[65]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[66]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[67]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[68]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[69]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[70]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[71]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[72]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[73]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[74]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[75]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[76]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[77]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[78]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[79]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[80]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[81]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[82]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[83]|0x0 # MSI
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MultiCastEnable|0x0 # MultiCast Enable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NoSnoopRdCfg|0x0 # NoSnoop Read Config
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NoSnoopWrCfg|0x1 # NoSnoop Write Config
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg0Size[0]|0x0 # North TH Mem Buffer Size 0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg0Size[1]|0x0 # North TH Mem Buffer Size 0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg0Size[2]|0x0 # North TH Mem Buffer Size 0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg0Size[3]|0x0 # North TH Mem Buffer Size 0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg1Size[0]|0x0 # North TH Mem Buffer Size 1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg1Size[1]|0x0 # North TH Mem Buffer Size 1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg1Size[2]|0x0 # North TH Mem Buffer Size 1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg1Size[3]|0x0 # North TH Mem Buffer Size 1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMode[0]|0x0 # North Trace Hub Enable Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMode[1]|0x0 # North Trace Hub Enable Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMode[2]|0x0 # North Trace Hub Enable Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMode[3]|0x0 # North Trace Hub Enable Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[0]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[1]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[2]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[3]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[4]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[5]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[6]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[7]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[8]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[9]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[10]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[11]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[12]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[13]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[14]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[15]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[16]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[17]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[18]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[19]|0x16 # Embar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[0]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[1]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[2]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[3]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[4]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[5]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[6]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[7]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[8]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[9]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[10]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[11]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[12]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[13]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[14]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[15]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[16]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[17]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[18]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[19]|0x16 # Embar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[0]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[1]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[2]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[3]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[4]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[5]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[6]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[7]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[8]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[9]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[10]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[11]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[12]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[13]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[14]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[15]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[16]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[17]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[18]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[19]|0xc # Embar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[0]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[1]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[2]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[3]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[4]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[5]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[6]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[7]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[8]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[9]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[10]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[11]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[12]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[13]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[14]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[15]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[16]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[17]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[18]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[19]|0xc # Embar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[0]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[1]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[2]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[3]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[4]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[5]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[6]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[7]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[8]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[9]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[10]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[11]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[12]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[13]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[14]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[15]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[16]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[17]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[18]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[19]|0x16 # Imbar1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[0]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[1]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[2]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[3]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[4]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[5]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[6]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[7]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[8]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[9]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[10]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[11]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[12]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[13]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[14]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[15]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[16]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[17]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[18]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[19]|0x16 # Imbar2 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[0]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[1]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[2]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[3]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[4]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[5]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[6]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[7]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[8]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[9]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[10]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[11]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[12]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[13]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[14]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[15]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[16]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[17]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[18]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[19]|0xc # Imbar2_0 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[0]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[1]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[2]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[3]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[4]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[5]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[6]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[7]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[8]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[9]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[10]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[11]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[12]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[13]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[14]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[15]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[16]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[17]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[18]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[19]|0xc # Imbar2_1 Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[0]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[1]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[2]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[3]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[4]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[5]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[6]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[7]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[8]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[9]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[10]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[11]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[12]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[13]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[14]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[15]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[16]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[17]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[18]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[19]|0x0 # Enable NTB BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbLinkBiosTrainEn|0x2 # NTB Link Train by BIOS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[0]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[1]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[2]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[3]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[4]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[5]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[6]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[7]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[8]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[9]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[10]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[11]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[12]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[13]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[14]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[15]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[16]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[17]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[18]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[19]|0x0 # Non-Transparent Bridge PCIe Port Definition
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[0]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[1]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[2]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[3]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[4]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[5]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[6]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[7]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[8]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[9]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[10]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[11]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[12]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[13]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[14]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[15]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[16]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[17]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[18]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[19]|0x0 # Enable SPLIT BARs
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[0]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[1]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[2]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[3]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[4]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[5]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[6]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[7]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[8]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[9]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[10]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[11]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[12]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[13]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[14]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[15]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[16]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[17]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[18]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[19]|0x3 # Crosslink control Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[0]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[1]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[2]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[3]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[4]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[5]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[6]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[7]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[8]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[9]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[10]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[11]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[12]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[13]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[14]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[15]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[16]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[17]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[18]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[19]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[20]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[21]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[22]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[23]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[24]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[25]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[26]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[27]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[28]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[29]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[30]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[31]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[32]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[33]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[34]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[35]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[36]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[37]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[38]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[39]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[40]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[41]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[42]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[43]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[44]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[45]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[46]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[47]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[48]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[49]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[50]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[51]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[52]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[53]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[54]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[55]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[56]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[57]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[58]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[59]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[60]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[61]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[62]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[63]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[64]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[65]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[66]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[67]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[68]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[69]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[70]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[71]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[72]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[73]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[74]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[75]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[76]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[77]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[78]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[79]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[80]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[81]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[82]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[83]|0x0 # P2P Memory Read
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_AtomicOpReq|0x1 # PCIe Atomic Operation Request Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_LTR|0x2 # PCIe Latency Tolerance Reporting
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCUF6Hide|0x0 # Hide PCU Func 6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[1]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[2]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[3]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[4]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[5]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[6]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[7]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[8]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[9]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[10]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[11]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[12]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[13]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[14]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[15]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[16]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[17]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[18]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[19]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[20]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[21]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[22]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[23]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[24]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[25]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[26]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[27]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[28]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[29]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[30]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[31]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[32]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[33]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[34]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[35]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[36]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[37]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[38]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[39]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[40]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[41]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[42]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[43]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[44]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[45]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[46]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[47]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[48]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[49]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[50]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[51]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[52]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[53]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[54]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[55]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[56]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[57]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[58]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[59]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[60]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[61]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[62]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[63]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[64]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[65]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[66]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[67]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[68]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[69]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[70]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[71]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[72]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[73]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[74]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[75]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[76]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[77]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[78]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[79]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[80]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[81]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[82]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[83]|0x0 # Hide Port?
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Pci64BitResourceAllocation|0x1 # PCI 64-Bit Resource Allocation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Pcie10bitTag|0x1 # PCIe 10-bit Tag Enable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[0]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[1]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[2]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[3]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[4]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[5]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[6]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[7]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[8]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[9]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[10]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[11]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[12]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[13]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[14]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[15]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[16]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[17]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[18]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[19]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[0]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[1]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[2]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[3]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[4]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[5]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[6]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[7]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[8]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[9]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[10]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[11]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[12]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[13]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[14]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[15]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[16]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[17]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[18]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[19]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[0]|0x0 # Port 1A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[1]|0x0 # Port 1B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[2]|0x0 # Port 1C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[3]|0x0 # Port 1D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[4]|0x0 # Port 2A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[5]|0x0 # Port 2B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[6]|0x0 # Port 2C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[7]|0x0 # Port 2D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[8]|0x0 # Port 3A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[9]|0x0 # Port 3B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[10]|0x0 # Port 3C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[11]|0x0 # Port 3D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[12]|0x0 # Port 4A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[13]|0x0 # Port 4B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[14]|0x0 # Port 4C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[15]|0x0 # Port 4D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[16]|0x0 # Port 5A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[17]|0x0 # Port 5B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[18]|0x0 # Port 5C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[19]|0x0 # Port 5D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[20]|0x0 # Port 1A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[21]|0x0 # Port 1B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[22]|0x0 # Port 1C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[23]|0x0 # Port 1D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[24]|0x0 # Port 2A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[25]|0x0 # Port 2B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[26]|0x0 # Port 2C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[27]|0x0 # Port 2D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[28]|0x0 # Port 3A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[29]|0x0 # Port 3B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[30]|0x0 # Port 3C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[31]|0x0 # Port 3D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[32]|0x0 # Port 4A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[33]|0x0 # Port 4B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[34]|0x0 # Port 4C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[35]|0x0 # Port 4D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[36]|0x0 # Port 5A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[37]|0x0 # Port 5B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[38]|0x0 # Port 5C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[39]|0x0 # Port 5D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[40]|0x0 # Port 1A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[41]|0x0 # Port 1B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[42]|0x0 # Port 1C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[43]|0x0 # Port 1D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[44]|0x0 # Port 2A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[45]|0x0 # Port 2B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[46]|0x0 # Port 2C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[47]|0x0 # Port 2D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[48]|0x0 # Port 3A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[49]|0x0 # Port 3B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[50]|0x0 # Port 3C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[51]|0x0 # Port 3D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[52]|0x0 # Port 4A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[53]|0x0 # Port 4B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[54]|0x0 # Port 4C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[55]|0x0 # Port 4D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[56]|0x0 # Port 5A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[57]|0x0 # Port 5B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[58]|0x0 # Port 5C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[59]|0x0 # Port 5D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[60]|0x0 # Port 1A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[61]|0x0 # Port 1B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[62]|0x0 # Port 1C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[63]|0x0 # Port 1D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[64]|0x0 # Port 2A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[65]|0x0 # Port 2B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[66]|0x0 # Port 2C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[67]|0x0 # Port 2D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[68]|0x0 # Port 3A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[69]|0x0 # Port 3B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[70]|0x0 # Port 3C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[71]|0x0 # Port 3D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[72]|0x0 # Port 4A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[73]|0x0 # Port 4B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[74]|0x0 # Port 4C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[75]|0x0 # Port 4D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[76]|0x0 # Port 5A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[77]|0x0 # Port 5B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[78]|0x0 # Port 5C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[79]|0x0 # Port 5D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAcpiHotPlugEnable|0x0 # PCIe ACPI Hot Plug
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAllocatingFlow|0x1 # PCIe Allocating Write Flows
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[0]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[1]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[2]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[3]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[4]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[5]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[6]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[7]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[8]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[9]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[10]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[11]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[12]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[13]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[14]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[15]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[16]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[17]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[18]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[19]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[20]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[21]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[22]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[23]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[24]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[25]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[26]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[27]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[28]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[29]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[30]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[31]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[32]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[33]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[34]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[35]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[36]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[37]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[38]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[39]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[40]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[41]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[42]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[43]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[44]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[45]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[46]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[47]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[48]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[49]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[50]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[51]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[52]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[53]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[54]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[55]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[56]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[57]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[58]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[59]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[60]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[61]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[62]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[63]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[64]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[65]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[66]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[67]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[68]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[69]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[70]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[71]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[72]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[73]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[74]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[75]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[76]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[77]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[78]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[79]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[80]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[81]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[82]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[83]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieBiosTrainEnable|0x1 # PCIe Train by BIOS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[0]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[1]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[2]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[3]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[4]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[5]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[6]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[7]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[8]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[9]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[10]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[11]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[12]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[13]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[14]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[15]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[16]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[17]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[18]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[19]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[20]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[21]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[22]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[23]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[24]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[25]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[26]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[27]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[28]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[29]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[30]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[31]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[32]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[33]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[34]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[35]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[36]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[37]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[38]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[39]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[40]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[41]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[42]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[43]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[44]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[45]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[46]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[47]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[48]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[49]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[50]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[51]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[52]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[53]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[54]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[55]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[56]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[57]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[58]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[59]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[60]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[61]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[62]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[63]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[64]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[65]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[66]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[67]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[68]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[69]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[70]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[71]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[72]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[73]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[74]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[75]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[76]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[77]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[78]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[79]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[80]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[81]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[82]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[83]|0x1 # PCI-E Port Clocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[0]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[1]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[2]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[3]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[4]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[5]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[6]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[7]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[8]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[9]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[10]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[11]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[12]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[13]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[14]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[15]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[16]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[17]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[18]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[19]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[20]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[21]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[22]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[23]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[24]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[25]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[26]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[27]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[28]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[29]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[30]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[31]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[32]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[33]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[34]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[35]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[36]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[37]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[38]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[39]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[40]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[41]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[42]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[43]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[44]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[45]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[46]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[47]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[48]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[49]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[50]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[51]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[52]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[53]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[54]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[55]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[56]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[57]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[58]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[59]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[60]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[61]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[62]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[63]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[64]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[65]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[66]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[67]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[68]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[69]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[70]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[71]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[72]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[73]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[74]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[75]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[76]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[77]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[78]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[79]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[80]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[81]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[82]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[83]|0x0 # PCI-E Port D-state
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[0]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[1]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[2]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[3]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[4]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[5]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[6]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[7]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[8]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[9]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[10]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[11]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[12]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[13]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[14]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[15]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[16]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[17]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[18]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[19]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[20]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[21]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[22]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[23]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[24]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[25]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[26]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[27]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[28]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[29]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[30]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[31]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[32]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[33]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[34]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[35]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[36]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[37]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[38]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[39]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[40]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[41]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[42]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[43]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[44]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[45]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[46]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[47]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[48]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[49]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[50]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[51]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[52]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[53]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[54]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[55]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[56]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[57]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[58]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[59]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[60]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[61]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[62]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[63]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[64]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[65]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[66]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[67]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[68]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[69]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[70]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[71]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[72]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[73]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[74]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[75]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[76]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[77]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[78]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[79]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[80]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[81]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[82]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[83]|0x1 # Data Link Feature Exchange
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieExtendedTagField|0x1 # PCIe Extended Tag Enable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieGlobalAspm|0x1 # PCI-E ASPM Support (Global)
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugEnable|0x0 # PCIe Hot Plug
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[1]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[2]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[3]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[4]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[5]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[6]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[7]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[8]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[9]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[10]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[11]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[12]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[13]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[14]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[15]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[16]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[17]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[18]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[19]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[20]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[21]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[22]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[23]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[24]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[25]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[26]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[27]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[28]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[29]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[30]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[31]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[32]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[33]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[34]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[35]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[36]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[37]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[38]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[39]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[40]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[41]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[42]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[43]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[44]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[45]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[46]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[47]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[48]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[49]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[50]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[51]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[52]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[53]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[54]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[55]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[56]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[57]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[58]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[59]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[60]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[61]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[62]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[63]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[64]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[65]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[66]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[67]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[68]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[69]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[70]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[71]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[72]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[73]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[74]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[75]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[76]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[77]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[78]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[79]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[80]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[81]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[82]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[83]|0x2 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[0]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[1]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[2]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[3]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[4]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[5]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[6]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[7]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[8]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[9]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[10]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[11]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[12]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[13]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[14]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[15]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[16]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[17]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[18]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[19]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[20]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[21]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[22]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[23]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[24]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[25]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[26]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[27]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[28]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[29]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[30]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[31]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[32]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[33]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[34]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[35]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[36]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[37]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[38]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[39]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[40]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[41]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[42]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[43]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[44]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[45]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[46]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[47]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[48]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[49]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[50]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[51]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[52]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[53]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[54]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[55]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[56]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[57]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[58]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[59]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[60]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[61]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[62]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[63]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[64]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[65]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[66]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[67]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[68]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[69]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[70]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[71]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[72]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[73]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[74]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[75]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[76]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[77]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[78]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[79]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[80]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[81]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[82]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[83]|0x4 # PCI-E Port L1 Exit Latency
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[1]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[2]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[3]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[4]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[5]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[6]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[7]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[8]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[9]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[10]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[11]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[12]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[13]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[14]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[15]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[16]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[17]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[18]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[19]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[20]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[21]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[22]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[23]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[24]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[25]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[26]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[27]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[28]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[29]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[30]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[31]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[32]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[33]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[34]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[35]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[36]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[37]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[38]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[39]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[40]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[41]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[42]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[43]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[44]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[45]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[46]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[47]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[48]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[49]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[50]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[51]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[52]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[53]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[54]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[55]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[56]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[57]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[58]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[59]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[60]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[61]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[62]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[63]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[64]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[65]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[66]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[67]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[68]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[69]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[70]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[71]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[72]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[73]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[74]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[75]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[76]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[77]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[78]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[79]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[80]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[81]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[82]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[83]|0x0 # PCI-E Port Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLowLatencyRetimersEnabled|0x0 # PCIe Low Latency Retimers
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[0]|0x7 # DMI Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[1]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[2]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[3]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[4]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[5]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[6]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[7]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[8]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[9]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[10]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[11]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[12]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[13]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[14]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[15]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[16]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[17]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[18]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[19]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[20]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[21]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[22]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[23]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[24]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[25]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[26]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[27]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[28]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[29]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[30]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[31]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[32]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[33]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[34]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[35]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[36]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[37]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[38]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[39]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[40]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[41]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[42]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[43]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[44]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[45]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[46]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[47]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[48]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[49]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[50]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[51]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[52]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[53]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[54]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[55]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[56]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[57]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[58]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[59]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[60]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[61]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[62]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[63]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[64]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[65]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[66]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[67]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[68]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[69]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[70]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[71]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[72]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[73]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[74]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[75]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[76]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[77]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[78]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[79]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[80]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[81]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[82]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[83]|0x7 # PCI-E Port MPSS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxReadRequestSize|0x5 # PCIe Max Read Request Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePhyTestMode|0x0 # PCIe PHY test mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[0]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[1]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[2]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[3]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[4]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[5]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[6]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[7]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[8]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[9]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[10]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[11]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[12]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[13]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[14]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[15]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[16]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[17]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[18]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[19]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[20]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[21]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[22]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[23]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[24]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[25]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[26]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[27]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[28]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[29]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[30]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[31]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[32]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[33]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[34]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[35]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[36]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[37]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[38]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[39]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[40]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[41]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[42]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[43]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[44]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[45]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[46]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[47]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[48]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[49]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[50]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[51]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[52]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[53]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[54]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[55]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[56]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[57]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[58]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[59]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[60]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[61]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[62]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[63]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[64]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[65]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[66]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[67]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[68]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[69]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[70]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[71]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[72]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[73]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[74]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[75]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[76]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[77]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[78]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[79]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[80]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[81]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[82]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[83]|0x1 # PCI-E Port Clock Gating
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[1]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[2]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[3]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[4]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[5]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[6]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[7]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[8]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[9]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[10]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[11]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[12]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[13]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[14]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[15]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[16]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[17]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[18]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[19]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[20]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[21]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[22]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[23]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[24]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[25]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[26]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[27]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[28]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[29]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[30]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[31]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[32]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[33]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[34]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[35]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[36]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[37]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[38]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[39]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[40]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[41]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[42]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[43]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[44]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[45]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[46]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[47]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[48]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[49]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[50]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[51]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[52]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[53]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[54]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[55]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[56]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[57]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[58]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[59]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[60]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[61]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[62]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[63]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[64]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[65]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[66]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[67]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[68]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[69]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[70]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[71]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[72]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[73]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[74]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[75]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[76]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[77]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[78]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[79]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[80]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[81]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[82]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[83]|0x2 # PCI-E Port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[0]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[1]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[2]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[3]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[4]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[5]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[6]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[7]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[8]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[9]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[10]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[11]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[12]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[13]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[14]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[15]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[16]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[17]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[18]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[19]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[20]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[21]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[22]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[23]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[24]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[25]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[26]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[27]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[28]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[29]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[30]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[31]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[32]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[33]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[34]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[35]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[36]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[37]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[38]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[39]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[40]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[41]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[42]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[43]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[44]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[45]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[46]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[47]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[48]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[49]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[50]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[51]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[52]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[53]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[54]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[55]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[56]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[57]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[58]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[59]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[60]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[61]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[62]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[63]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[64]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[65]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[66]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[67]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[68]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[69]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[70]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[71]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[72]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[73]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[74]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[75]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[76]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[77]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[78]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[79]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[80]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[81]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[82]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[83]|0x0 # Override Max Link Width
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[0]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[1]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[2]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[3]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[4]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[5]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[6]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[7]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[8]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[9]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[10]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[11]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[12]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[13]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[14]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[15]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[16]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[17]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[18]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[19]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[20]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[21]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[22]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[23]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[24]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[25]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[26]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[27]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[28]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[29]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[30]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[31]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[32]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[33]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[34]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[35]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[36]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[37]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[38]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[39]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[40]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[41]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[42]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[43]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[44]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[45]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[46]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[47]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[48]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[49]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[50]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[51]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[52]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[53]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[54]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[55]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[56]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[57]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[58]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[59]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[60]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[61]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[62]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[63]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[64]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[65]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[66]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[67]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[68]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[69]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[70]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[71]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[72]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[73]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[74]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[75]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[76]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[77]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[78]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[79]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[80]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[81]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[82]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[83]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePtm|0x0 # PCIe PTM Enable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieRelaxedOrdering|0x1 # Pcie Relaxed Ordering
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotItemCtrl|0x0 # PCIe Slot Item Control
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom1|0x1 # PCIe Slot 1 OpROM
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom2|0x1 # PCIe Slot 2 OpROM
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom3|0x1 # PCIe Slot 3 OpROM
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom4|0x1 # PCIe Slot 4 OpROM
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom5|0x1 # PCIe Slot 5 OpROM
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom6|0x1 # PCIe Slot 6 OpROM
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom7|0x1 # PCIe Slot 7 OpROM
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom8|0x1 # PCIe Slot 8 OpROM
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[1]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[2]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[3]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[4]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[5]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[6]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[7]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[8]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[9]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[10]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[11]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[12]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[13]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[14]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[15]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[16]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[17]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[18]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[19]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[20]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[21]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[22]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[23]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[24]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[25]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[26]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[27]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[28]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[29]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[30]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[31]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[32]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[33]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[34]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[35]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[36]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[37]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[38]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[39]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[40]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[41]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[42]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[43]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[44]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[45]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[46]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[47]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[48]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[49]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[50]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[51]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[52]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[53]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[54]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[55]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[56]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[57]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[58]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[59]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[60]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[61]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[62]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[63]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[64]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[65]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[66]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[67]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[68]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[69]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[70]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[71]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[72]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[73]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[74]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[75]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[76]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[77]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[78]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[79]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[80]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[81]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[82]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[83]|0x2 # PCI-E Detect Wait Time
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[0]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[1]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[2]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[3]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[4]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[5]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[6]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[7]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[8]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[9]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[10]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[11]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[12]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[13]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[14]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[15]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[16]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[17]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[18]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[19]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[20]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[21]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[22]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[23]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[24]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[25]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[26]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[27]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[28]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[29]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[30]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[31]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[32]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[33]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[34]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[35]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[36]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[37]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[38]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[39]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[40]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[41]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[42]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[43]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[44]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[45]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[46]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[47]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[48]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[49]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[50]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[51]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[52]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[53]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[54]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[55]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[56]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[57]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[58]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[59]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[60]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[61]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[62]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[63]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[64]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[65]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[66]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[67]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[68]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[69]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[70]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[71]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[72]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[73]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[74]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[75]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[76]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[77]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[78]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[79]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[80]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[81]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[82]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[83]|0x0 # Unsupported Request
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PerformanceTuningMode|0x1 # Performance Tuning Mode
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[0]|0x0 # Enable MMIO read cmpl poison for STACK_0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[1]|0x0 # Enable MMIO read cmpl poison for STACK_1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[2]|0x0 # Enable MMIO read cmpl poison for STACK_2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[3]|0x0 # Enable MMIO read cmpl poison for STACK_3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[4]|0x0 # Enable MMIO read cmpl poison for STACK_4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[5]|0x0 # Enable MMIO read cmpl poison for STACK_5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[6]|0x0 # Enable MMIO read cmpl poison for STACK_0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[7]|0x0 # Enable MMIO read cmpl poison for STACK_1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[8]|0x0 # Enable MMIO read cmpl poison for STACK_2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[9]|0x0 # Enable MMIO read cmpl poison for STACK_3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[10]|0x0 # Enable MMIO read cmpl poison for STACK_4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[11]|0x0 # Enable MMIO read cmpl poison for STACK_5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[12]|0x0 # Enable MMIO read cmpl poison for STACK_0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[13]|0x0 # Enable MMIO read cmpl poison for STACK_1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[14]|0x0 # Enable MMIO read cmpl poison for STACK_2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[15]|0x0 # Enable MMIO read cmpl poison for STACK_3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[16]|0x0 # Enable MMIO read cmpl poison for STACK_4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[17]|0x0 # Enable MMIO read cmpl poison for STACK_5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[18]|0x0 # Enable MMIO read cmpl poison for STACK_0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[19]|0x0 # Enable MMIO read cmpl poison for STACK_1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[20]|0x0 # Enable MMIO read cmpl poison for STACK_2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[21]|0x0 # Enable MMIO read cmpl poison for STACK_3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[22]|0x0 # Enable MMIO read cmpl poison for STACK_4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[23]|0x0 # Enable MMIO read cmpl poison for STACK_5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PostedInterrupt|0x1 # Posted Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PrioritizeTPH|0x0 # Prioritize TPH
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ProblematicPort|0x0 # Problematic port
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[2]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[3]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[4]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[5]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[6]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[7]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[8]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[9]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[10]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[11]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[14]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[15]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[16]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[17]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[18]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[19]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[20]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[21]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[22]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[23]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[2]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[3]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[4]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[5]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[6]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[7]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[8]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[9]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[10]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[11]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[14]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[15]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[16]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[17]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[18]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[19]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[20]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[21]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[22]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override[23]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[2]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[3]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[4]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[5]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[6]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[7]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[8]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[9]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[10]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[11]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[14]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[15]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[16]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[17]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[18]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[19]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[20]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[21]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[22]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override[23]|0x0 # - Override
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpCorrectableErrorEsc[0]|0x0 # Sck0 RP Correctable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpCorrectableErrorEsc[1]|0x0 # Sck1 RP Correctable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpCorrectableErrorEsc[2]|0x0 # Sck2 RP Correctable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpCorrectableErrorEsc[3]|0x0 # Sck3 RP Correctable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableFatalErrorEsc[0]|0x0 # Sck0 RP Fatal Uncorrectable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableFatalErrorEsc[1]|0x0 # Sck1 RP Fatal Uncorrectable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableFatalErrorEsc[2]|0x0 # Sck2 RP Fatal Uncorrectable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableFatalErrorEsc[3]|0x0 # Sck3 RP Fatal Uncorrectable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableNonFatalErrorEsc[0]|0x0 # Sck0 RP NonFatal Uncorrectable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableNonFatalErrorEsc[1]|0x0 # Sck1 RP NonFatal Uncorrectable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableNonFatalErrorEsc[2]|0x0 # Sck2 RP NonFatal Uncorrectable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableNonFatalErrorEsc[3]|0x0 # Sck3 RP NonFatal Uncorrectable Err
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RxClockWA|0x0 # Rx Clock WA
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[0]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[1]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[2]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[3]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[4]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[5]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[6]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[7]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[8]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[9]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[10]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[11]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[12]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[13]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[14]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[15]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[16]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[17]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[18]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[19]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[20]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[21]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[22]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[23]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[24]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[25]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[26]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[27]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[28]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[29]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[30]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[31]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[32]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[33]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[34]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[35]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[36]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[37]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[38]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[39]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[40]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[41]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[42]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[43]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[44]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[45]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[46]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[47]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[48]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[49]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[50]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[51]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[52]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[53]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[54]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[55]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[56]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[57]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[58]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[59]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[60]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[61]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[62]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[63]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[64]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[65]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[66]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[67]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[68]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[69]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[70]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[71]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[72]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[73]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[74]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[75]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[76]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[77]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[78]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[79]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[80]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[81]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[82]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[83]|0x0 # SERRE
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[1]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[2]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[3]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[4]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[5]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[6]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[7]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[8]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[9]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[10]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[11]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[12]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[13]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[14]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[15]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[16]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[17]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[18]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[19]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[20]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[21]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[22]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[23]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[24]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[25]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[26]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[27]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[28]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[29]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[30]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[31]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[32]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[33]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[34]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[35]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[36]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[37]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[38]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[39]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[40]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[41]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[42]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[43]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[44]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[45]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[46]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[47]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[48]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[49]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[50]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[51]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[52]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[53]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[54]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[55]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[56]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[57]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[58]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[59]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[60]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[61]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[62]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[63]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[64]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[65]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[66]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[67]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[68]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[69]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[70]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[71]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[72]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[73]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[74]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[75]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[76]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[77]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[78]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[79]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[80]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[81]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[82]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[83]|0x0 # Surprise Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[0]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[1]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[2]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[3]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[4]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[5]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[6]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[7]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[8]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[9]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[10]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[11]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[12]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[13]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[14]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[15]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[16]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[17]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[18]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[19]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[20]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[21]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[22]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[23]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[24]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[25]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[26]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[27]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[28]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[29]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[30]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[31]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[32]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[33]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[34]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[35]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[36]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[37]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[38]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[39]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[40]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[41]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[42]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[43]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[44]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[45]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[46]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[47]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[48]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[49]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[50]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[51]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[52]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[53]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[54]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[55]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[56]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[57]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[58]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[59]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[60]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[61]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[62]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[63]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[64]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[65]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[66]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[67]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[68]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[69]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[70]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[71]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[72]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[73]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[74]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[75]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[76]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[77]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[78]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[79]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[80]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[81]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[82]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[83]|0x0 # SRIS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SierraPeakMemBufferSize[0]|0x0 # Sierra Peak Memory Region Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SierraPeakMemBufferSize[1]|0x0 # Sierra Peak Memory Region Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SierraPeakMemBufferSize[2]|0x0 # Sierra Peak Memory Region Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SierraPeakMemBufferSize[3]|0x0 # Sierra Peak Memory Region Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS46|0x0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SkipRetimersDetection|0x0 # Skip PCIe retimers detection
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SnoopResponseHoldOff|0x9 # Snoop Response Hold Off
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.StopAndScream|0x0 # PCIE Stop & Scream Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[0]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[1]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[2]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[3]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[4]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[5]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[6]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[7]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[8]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[9]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[10]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[11]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[12]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[13]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[14]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[15]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[16]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[17]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[18]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[19]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[20]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[21]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[22]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[23]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[24]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[25]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[26]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[27]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[28]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[29]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[30]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[31]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[32]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[33]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[34]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[35]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[36]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[37]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[38]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[39]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[40]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[41]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[42]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[43]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[44]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[45]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[46]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[47]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[48]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[49]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[50]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[51]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[52]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[53]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[54]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[55]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[56]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[57]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[58]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[59]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[60]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[61]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[62]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[63]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[64]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[65]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[66]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[67]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[68]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[69]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[70]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[71]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[72]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[73]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[74]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[75]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[76]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[77]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[78]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[79]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[80]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[81]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[82]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[83]|0x0 # Alternate TxEq
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[0]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[1]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[2]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[3]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[4]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[5]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[6]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[7]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[8]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[9]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[10]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[11]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[12]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[13]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[14]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[15]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[16]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[17]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[18]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[19]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[20]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[21]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[22]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[23]|0x2 # CfgBar attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[0]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[1]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[2]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[3]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[4]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[5]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[6]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[7]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[8]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[9]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[10]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[11]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[12]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[13]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[14]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[15]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[16]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[17]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[18]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[19]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[20]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[21]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[22]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[23]|0x19 # CfgBar size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[0]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[1]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[2]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[3]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[4]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[5]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[6]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[7]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[8]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[9]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[10]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[11]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[12]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[13]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[14]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[15]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[16]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[17]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[18]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[19]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[20]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[21]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[22]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[23]|0x0 # VMD for Direct Assign
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[0]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[1]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[2]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[3]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[4]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[5]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[6]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[7]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[8]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[9]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[10]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[11]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[12]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[13]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[14]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[15]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[16]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[17]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[18]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[19]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[20]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[21]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[22]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[23]|0x0 # Enable/Disable VMD
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[0]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[1]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[2]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[3]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[4]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[5]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[6]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[7]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[8]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[9]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[10]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[11]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[12]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[13]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[14]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[15]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[16]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[17]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[18]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[19]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[20]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[21]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[22]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[23]|0x0 # Hot Plug Capable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[0]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[1]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[2]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[3]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[4]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[5]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[6]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[7]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[8]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[9]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[10]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[11]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[12]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[13]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[14]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[15]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[16]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[17]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[18]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[19]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[20]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[21]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[22]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[23]|0x0 # MemBar1 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[0]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[1]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[2]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[3]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[4]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[5]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[6]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[7]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[8]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[9]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[10]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[11]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[12]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[13]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[14]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[15]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[16]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[17]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[18]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[19]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[20]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[21]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[22]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[23]|0x1 # MemBar2 attribute
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[0]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[1]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[2]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[3]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[4]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[5]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[6]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[7]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[8]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[9]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[10]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[11]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[12]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[13]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[14]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[15]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[16]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[17]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[18]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[19]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[20]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[21]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[22]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[23]|0x19 # MemBar1 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[0]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[1]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[2]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[3]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[4]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[5]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[6]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[7]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[8]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[9]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[10]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[11]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[12]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[13]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[14]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[15]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[16]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[17]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[18]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[19]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[20]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[21]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[22]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[23]|0x14 # MemBar2 size
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[0]|0x0 # PCH Root Port 0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[1]|0x0 # PCH Root Port 1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[2]|0x0 # PCH Root Port 2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[3]|0x0 # PCH Root Port 3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[4]|0x0 # PCH Root Port 4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[5]|0x0 # PCH Root Port 5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[6]|0x0 # PCH Root Port 6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[7]|0x0 # PCH Root Port 7
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[8]|0x0 # PCH Root Port 8
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[9]|0x0 # PCH Root Port 9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[10]|0x0 # PCH Root Port 10
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[11]|0x0 # PCH Root Port 11
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[12]|0x0 # PCH Root Port 12
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[13]|0x0 # PCH Root Port 13
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[14]|0x0 # PCH Root Port 14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[15]|0x0 # PCH Root Port 15
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[16]|0x0 # PCH Root Port 16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[17]|0x0 # PCH Root Port 17
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[18]|0x0 # PCH Root Port 18
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[19]|0x0 # PCH Root Port 19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[20]|0x0 # PCH Root Port 0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[21]|0x0 # PCH Root Port 1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[22]|0x0 # PCH Root Port 2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[23]|0x0 # PCH Root Port 3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[24]|0x0 # PCH Root Port 4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[25]|0x0 # PCH Root Port 5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[26]|0x0 # PCH Root Port 6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[27]|0x0 # PCH Root Port 7
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[28]|0x0 # PCH Root Port 8
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[29]|0x0 # PCH Root Port 9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[30]|0x0 # PCH Root Port 10
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[31]|0x0 # PCH Root Port 11
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[32]|0x0 # PCH Root Port 12
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[33]|0x0 # PCH Root Port 13
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[34]|0x0 # PCH Root Port 14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[35]|0x0 # PCH Root Port 15
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[36]|0x0 # PCH Root Port 16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[37]|0x0 # PCH Root Port 17
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[38]|0x0 # PCH Root Port 18
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[39]|0x0 # PCH Root Port 19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[40]|0x0 # PCH Root Port 0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[41]|0x0 # PCH Root Port 1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[42]|0x0 # PCH Root Port 2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[43]|0x0 # PCH Root Port 3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[44]|0x0 # PCH Root Port 4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[45]|0x0 # PCH Root Port 5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[46]|0x0 # PCH Root Port 6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[47]|0x0 # PCH Root Port 7
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[48]|0x0 # PCH Root Port 8
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[49]|0x0 # PCH Root Port 9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[50]|0x0 # PCH Root Port 10
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[51]|0x0 # PCH Root Port 11
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[52]|0x0 # PCH Root Port 12
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[53]|0x0 # PCH Root Port 13
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[54]|0x0 # PCH Root Port 14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[55]|0x0 # PCH Root Port 15
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[56]|0x0 # PCH Root Port 16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[57]|0x0 # PCH Root Port 17
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[58]|0x0 # PCH Root Port 18
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[59]|0x0 # PCH Root Port 19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[60]|0x0 # PCH Root Port 0
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[61]|0x0 # PCH Root Port 1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[62]|0x0 # PCH Root Port 2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[63]|0x0 # PCH Root Port 3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[64]|0x0 # PCH Root Port 4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[65]|0x0 # PCH Root Port 5
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[66]|0x0 # PCH Root Port 6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[67]|0x0 # PCH Root Port 7
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[68]|0x0 # PCH Root Port 8
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[69]|0x0 # PCH Root Port 9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[70]|0x0 # PCH Root Port 10
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[71]|0x0 # PCH Root Port 11
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[72]|0x0 # PCH Root Port 12
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[73]|0x0 # PCH Root Port 13
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[74]|0x0 # PCH Root Port 14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[75]|0x0 # PCH Root Port 15
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[76]|0x0 # PCH Root Port 16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[77]|0x0 # PCH Root Port 17
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[78]|0x0 # PCH Root Port 18
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[79]|0x0 # PCH Root Port 19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[4]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[5]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[6]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[7]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[8]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[9]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[10]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[11]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[12]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[13]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[14]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[15]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[16]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[17]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[18]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[19]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[20]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[21]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[22]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[23]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[28]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[29]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[30]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[31]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[32]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[33]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[34]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[35]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[36]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[37]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[38]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[39]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[40]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[41]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[42]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[43]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[44]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[45]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[46]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[47]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[52]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[53]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[54]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[55]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[56]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[57]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[58]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[59]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[60]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[61]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[62]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[63]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[64]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[65]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[66]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[67]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[68]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[69]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[70]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[71]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[76]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[77]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[78]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[79]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[80]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[81]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[82]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[83]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[84]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[85]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[86]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[87]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[88]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[89]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[90]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[91]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[92]|0x0 # VMD port A
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[93]|0x0 # VMD port B
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[94]|0x0 # VMD port C
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[95]|0x0 # VMD port D
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VTdSupport|0x1 # Intel� VT for Directed I/O
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdDisabledBitmask[0]|0x0 # Intel� VT-d Disable Mask
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdDisabledBitmask[1]|0x0 # Intel� VT-d Disable Mask
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdDisabledBitmask[2]|0x0 # Intel� VT-d Disable Mask
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdDisabledBitmask[3]|0x0 # Intel� VT-d Disable Mask
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlBit0|0x0 # Source Validation
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlBit1|0x0 # Translation Blocking
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlBit2|0x1 # P2P Request Redirect
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlBit3|0x1 # P2P Completion Redirect
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlBit4|0x1 # Upstream Forwarding Enable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlWaEn|0x0 # PCIe ACSCTL
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.X2ApicOptOut|0x0 # X2APIC Opt Out
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Xppdef|0x0 # Retimer workaround
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADDDCEn|0x0 # ADDDC Sparing
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADRDataSaveMode|0x2 # ADR Data Save Mode
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADREn|0x1 # Enable ADR
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdddcErrInjEn|0x1 # Enable ADDDC Error Injection
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondPause|0x186a0 # Adv MemTest Pause
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTrefi|0x3cf0 # Adv MemTest tREFI
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTwr|0xa # Adv MemTest tWR
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondVdd|0x4c4 # Adv MemTest VDD Level
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondition|0x1 # Adv MemTest Conditions
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestOptions|0x0 # Adv MemTest Options
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestPpr|0x1 # Adv MemTest PPR
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[0]|0xffffffff # Rank location entry 0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[1]|0xffffffff # Rank location entry 1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[2]|0xffffffff # Rank location entry 2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[3]|0xffffffff # Rank location entry 3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[4]|0xffffffff # Rank location entry 4
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[5]|0xffffffff # Rank location entry 5
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[6]|0xffffffff # Rank location entry 6
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[7]|0xffffffff # Rank location entry 7
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankListNumEntries|0x0 # Number of Ranks to Test
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestResetList|0x0 # Adv MemTest Reset Failure Tracking List
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRetryAfterRepair|0x1 # Adv MemTest Retry After Repair
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AepNotSupportedException|0x0 # 100 series PMem Not Supported Exception
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ApdEn|0x0 # APD
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AppDirectMemoryHole|0x0 # App Direct Memory Hole
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AttemptFastBoot|0x1 # Attempt Fast Boot
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AttemptFastBootCold|0x1 # Attempt Fast Cold Boot
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS92|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS99|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS100|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS101|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS104|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS89|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS93|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS102|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS103|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS91|0x10
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS88|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS90|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS95|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS96|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS94|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS97|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS98|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Blockgnt2cmd1cyc|0x1 # BLOCK GNT2CMD1CYC
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.BwLimitTfOvrd|0x0 # Override BW_LIMIT_TF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CacheMemType|0x0 # 2LM Memory Type
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CkMode|0x2 # CK in SR
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CkeIdleTimer|0x14 # CKE Idle Timer
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CkeProgramming|0x0 # CKE Throttling
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmdNormalization|0x1 # Command Normalization
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmdTxEqCalibration|0x0 # CMD Tx Eq Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmdVrefEnable|0x1 # Command Vref Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmiInitOption|0x0 # CMI Init Option
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmsEnableDramPm|0x1 # CMS ENABLE DRAM PM
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ColumnCorrectionDisable|0x0 # Column Correction Disable
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CustomRefreshRate|0x14 # Custom Refresh Rate
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CustomRefreshRateEn|0x0 # Custom Refresh Enable
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DataDllOff|0x1 # Data DLL Off EN
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmAveragePowerLimit|0x3a98 # 200 Series PMem Average Power Limit (in mW)
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmAveragePowerTimeConstant|0x6 # 200 Series PMem Turbo Average Power Time Constant (in mSec)
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmEccModeSwitch|0x1 # ECC Mode Switch
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbAveragePowerTimeConstant|0x3a98 # 200 Series PMem Memory Bandwidth Boost(MBB) Average Power Time Constant (in mSec)
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbFeature|0x1 # 200 Series PMem Turbo/Memory Bandwidth Boost(MBB) Feature
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbMaxPowerLimit|0x4650 # 200 Series PMem Turbo/Memory Bandwidth Boost Feature(MBB) Power Limit (in mW)
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdjcTraining|0x1 # DDJC Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrCacheSize|0xff # DDR Cache Size
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrFreqLimit|0x0 # Memory Frequency
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrMemoryType|0x2 # Memory Type
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrtCkeEn|0x1 # PMem CKE
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrtSrefEn|0x0 # PMem SELF REFRESH
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DfeGainBias|0x0 # DfeGainBias
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS48|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS127|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS122|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS121|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS135|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS129|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS120|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS136|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS139|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS132|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS63|0x7
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS62|0xf
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS67|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS65|0x7ff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS66|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS73|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS109|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS78|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS124|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS112|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS110|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS111|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS140|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS141|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS142|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS146|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS147|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS148|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS131|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS57|0x7ff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS56|0x7ff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS61|0x1ff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS51|0x1f
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS52|0x7f
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS50|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS60|0x3f
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS58|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS59|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS55|0x7ff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS53|0x7ff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS54|0x7ff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS70|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS79|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS117|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS119|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS118|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS137|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS128|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS123|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS80|0x8
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS125|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS64|0x7ff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS113|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS126|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS134|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS130|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS145|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS49|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS69|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS133|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DieSparing|0x1 # Set PMem Die Sparing
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DisableDirForAppDirect|0x0 # Snoopy mode for AD
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Disddrtopprd|0x1 # Disable DDRT DIMM OPPRD
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplEnable|0x1 # DRAM RAPL
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplExtendedRange|0x1 # DRAM RAPL Extended Range
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplPwrLimitLockCsr|0x1 # DRAM RAPL Power Limit Lock CSR
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRonEn|0x0 # DRAM RON Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DutyCycleTraining|0x1 # Duty Cycle Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EadrCacheFlushMode|0x1 # CPU Cache Flush Mode
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EadrSupport|0x0 # eADR Support
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EccEnable|0x1 # ECC Enable
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EccSupport|0x1 # ECC Check
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EliminateDirectoryInFarMemory|0x1 # Snoopy mode for 2LM
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS84|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS85|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS87|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnableNgnBcomMargining|0x0 # DDRT DIMM BCOM Margining Support
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnableTapSweep|0x0 # Enable Tap Sweep
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnableTwoWayNmCache|0x0 # Enable biased 2-way near memory cache
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnforcePOR|0x0 # Enforce POR
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnforcePopulationPor|0x1 # Enforce Population POR
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EsddcEn|0x0 # Enhanced SDDC
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ExtendedType17|0x1 # Extended Type 17 Structure
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FactoryResetClear|0x0 # PMem Factory Reset/Clear
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FadrSupport|0x0 # fADR Support
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FastGoConfig|0x6 # PMem FastGo Configuration
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FastZeroMemSupport|0x0 # Boot-time Fast Zero Memory
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FourxRefreshValue|0x5f # Set FOURx Temperature Refresh
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.HalfxRefreshValue|0x19 # Set Halfx Temperature Refresh
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.HwMemTest|0x1 # MemTest
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LatchSystemShutdownState|0x1 # PMem Latch System Shutdown State
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LegacyADRModeEn|0x0 # Legacy ADR Mode
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LegacyRmt|0x0 # Rank Margin Tool
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LockNgnCsr|0x0 # Lock PMem CSRs
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmBacksideVrefEn|0x1 # LRDIMM Backside Vref
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmRdVrefEn|0x1 # LRDIMM Read Vref
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmRxDqCentering|0x1 # LRDIMM RX DQ Centering
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmTxDqCentering|0x1 # LRDIMM TX DQ Centering
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmWrVrefEn|0x1 # LRDIMM Write Vref
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrdimmDbDfeTraining|0x1 # LRDIMM DB DFE Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LsxImplementation|0x1 # LSx implementation
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.McRonEn|0x0 # MC RON Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MdllOffEn|0x1 # MDLL OFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemCeFloodPolicy|0x2 # Memory Correctable Error Flood Policy
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemHotIn|0x1 # MemHot Input Pin
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemHotOuputAssertThreshold|0x1 # MEMHOT Output Throttling Mode Options
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemHotOut|0x1 # MemHot Output Pin
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemTestLoops|0x1 # MemTest Loops
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemTestOnColdFastBoot|0x0 # MemTest On Cold Fast Boot
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemTripReporting|0x0 # MEMTRIP REPORTING
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MinNormalMemSize|0x2 # Minimum System Memory Size
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MultiThreaded|0x1 # Multi-Threaded MRC
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NfitPublishMailboxStructs|0x0 # NVDIMM Mailbox in NFIT
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnArsPublish|0x1 # Publish ARS capability
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnCmdTime|0x2 # PMem CMD Time
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnDebugLock|0x0 # Debug lock for PMem
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccCorr|0x2 # PMem ECC Correctable error
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccExitCorr|0x2 # PMem ECC Write Retry Flow Exit
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccRdChk|0x1 # PMem ECC Read Check
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccWrChk|0x2 # PMem ECC Write Check
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NonPreferredWayMask|0x1 # Non-preferred way mask
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NsddcEn|0x1 # New SDDC Mode
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvDimmEnergyPolicy|0x0 # NVDIMM Energy Policy
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvdimmSmbusMaxAccessTime|0x15e # SMBus Max Access Time
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvdimmSmbusReleaseDelay|0x96 # SMBus Release Delay
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmMediaStatusException|0x1 # PMem MediaStatus Exception
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmQos|0x0 # PMem QoS
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmdimmPerfConfig|0x0 # PMem Performance Setting
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmdimmPowerCyclePolicy|0x1 # Power Cycle on PMem Surprise Clock Stop
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffPkgMemToMemTrip|0x0 # OFF PKG MEM TO MEMTRIP
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffPkgMemToThermTrip|0x0 # OFF PKG MEM TO THERMTRIP
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCmdAll|0x64 # Offset CmdAll
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCmdVref|0x64 # Offset CmdVref
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCtlAll|0x64 # Offset CtlAll
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetRecEn|0x64 # Offset RecEnDelay
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetRxDq|0x64 # Offset RxDq
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetRxVref|0x64 # Offset RxVref
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetTxDq|0x64 # Offset TxDq
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetTxVref|0x64 # Offset TxVref
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OppSrefEn|0x0 # Opportunistic SR
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PagePolicy|0x2 # Page Policy
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PanicWm|0x0 # Refresh Watermarks
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PartialMirrorUefi|0x0 # UEFI ARM Mirror
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PartialMirrorUefiPercent|0x0 # ARM Mirror percentage
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrub|0x2 # Patrol Scrub
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrubAddrMode|0x1 # Patrol Scrub Address Mode
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrubDuration|0x18 # Patrol Scrub Interval
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PclsEn|0x1 # Partial Cache Line Sparing PCLS
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PeriodicRcomp|0x2 # Periodic Rcomp
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PeriodicRcompInterval|0xf # Periodic Rcomp Interval
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PkgcSrefEn|0x1 # PKGC SREF EN
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PlusOneEn|0x0 # Plus One | SDDC
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PmemCaching|0x0 # AppDirect cache
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PpdEn|0x1 # PPD
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PreferredReadFirst|0x1 # Preferred read first
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PxcTraining|0x1 # PXC Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RankSparing|0x0 # Memory Rank Sparing
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReadPreamble|0xff # Read Preamble TCLK
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RecEnDelayAverage|0x2 # Rank Switch Configuration
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RmtMinimumMarginCheck|0x1 # RMT Minimum Margin Check
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS86|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RmtOnColdFastBoot|0x0 # RMT On Cold Fast Boot
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RoundTripLatency|0x1 # RoundTrip Latency Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RxCtleTrnEn|0x1 # Rx CTLE Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RxDfe|0x0 # Rx Dfe Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RxOdtEn|0x1 # Rx ODT Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SaiPolicyGroupWaBiosW|0x0 # Enable Pcode WA for SAI PG
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleEn|0x1 # Data Scrambling for DDR4/5
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleEnDDRT|0x1 # Data Scrambling for PMem
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleSeedHigh|0xd395 # Scrambling Seed High
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleSeedLow|0xa02b # Scrambling Seed Low
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SetMemTested|0x1 # Allow Untested Memory for DXE Drivers
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ShortStroke2GB|0x0 # 2GB Short Stroke Configuration
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SmartTestKey|0x0 # SmartTestKey
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SmbSpdAccess|0x0 # SPD-SMBUS Access
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpareSwErrTh|0x4 # Sparing SW Error Match Threshold
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpdPrintEn|0x0 # SPD Print
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpdPrintLength|0x0 # SPD Print Length
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Srat|0x1 # Publish SRAT
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SratCpuHotPlug|0x0 # SRAT CPU Hot Plug
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SratMemoryHotPlug|0x0 # SRAT Memory Hot Plug
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SrefProgramming|0x0 # SREF Feature
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1End|0xa # Tap1End
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1Size|0x1 # Tap1Step
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1Start|0x8c # Tap1Start
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2End|0xf # Tap2End
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2Size|0x1 # Tap2Step
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2Start|0x73 # Tap2Start
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3End|0xc # Tap3End
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3Size|0x1 # Tap3Step
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3Start|0x70 # Tap3Start
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4End|0x9 # Tap4End
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4Size|0x1 # Tap4Step
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4Start|0x6d # Tap4Start
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TcoCompTraining|0x0 # Tco Comp Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TempRefreshOption|0x0 # Select Temperature Refresh Value
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrainingCompOptions|0x0 # Training Compensation Options Values
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrainingResultOffsetFunctionEnable|0x0 # Training Result Offset
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrefiDelay|0x0 # Additional TREFI Delay
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrefiNumofRank|0x1 # The Number of Ranks for Stagger TREFI
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrefiPerChannel|0x0 # Stagger TREFI Per Available Channel
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TriggerSWErrThEn|0x0 # Trigger SW Error Threshold
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TwoxRefreshValue|0x53 # Set TWOx Temperature Refresh
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TxRiseFallSlewRate|0x2 # TX Rise Fall Slew Rate Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Vdd|0x4b0 # Memory Voltage
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.WrCRC|0x0 # WR CRC feature Control
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.WritePreamble|0xff # Write Preamble TCLK
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.XMPMode|0x0 # XMP Profile
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.XMPProfilesSup|0x0 # XMP Profiles Supported
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.allowCorrectableError|0x0 # Allow Memory Training Correctable Error
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.allowCorrectableMemTestError|0x1 # Allow Memory Test Correctable Error
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.bdatEn|0x1 # BDAT
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.check_platform_detect|0x0 # Check PlatformDetectADR
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.check_pm_sts|0x0 # Check PCH_PM_STS
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.cmdSetupPercentOffset|0x32 # Cmd Setup % Offset
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.commandTiming|0x0 # Command Timing
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS83|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS77|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS72|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS68|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS106|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS108|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS105|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS71|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[0]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[1]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[2]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[3]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[4]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[5]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[6]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[7]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[8]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[9]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[10]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[11]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[12]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[13]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[14]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[15]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS75|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[0]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[1]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[3]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[4]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[6]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[7]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[9]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[10]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[12]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[13]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[15]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[16]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[18]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[19]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[21]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[22]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[24]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[25]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[27]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[28]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[30]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[31]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[33]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[34]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[36]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[37]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[39]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[40]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[42]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[43]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[45]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[46]|0xff
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS82|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS107|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.dimmIsolation|0x0 # DIMM Isolation Enable
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.dllResetTestLoops|0x0 # DLL Reset Test
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.eraseArmNVDIMMS|0x1 # Erase-Arm NVDIMMs
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.eyeDiagram|0x0 # Eye Diagrams
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.haltOnMemErr|0x1 # Halt on mem Training Error
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.iModeTraining|0x1 # iMode Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.imcBclk|0x0 # IMC BCLK
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.interNVDIMMS|0x1 # Interleave NVDIMMs
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktHi|0x29 # Leaky bucket high bit
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktHour|0x18 # Leaky bucket time window based interface Hour
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktLo|0x28 # Leaky bucket low bit
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktMinute|0x0 # Leaky bucket time window based interface Minute
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktTimeWindow|0x0 # Leaky bucket time window based interface
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.logParsing|0x0 # Enhanced Log Parsing
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.lrdimmModuleDelay|0x0 # LRDIMM Module Delay
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.mdllSden|0x2 # MDLL Off
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlows|0xffffffff # Mem Flows
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt|0xffffffff # Mem FlowsExt
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt2|0xffffffff # Mem FlowsExt2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt3|0xffffffff # Mem FlowsExt3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memInterleaveGran1LM|0x3 # 1LM Memory Interleave Granularity
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memhotSupport|0x1 # MEMHOT Throttling Mode
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.mrcRepeatTest|0x0 # DDR Cycling
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.multiSparingRanks|0x2 # Multi Rank Sparing
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.normOppInterval|0x400 # Normal Operation Duration
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oneRankTimingMode|0x1 # One Rank Timing Mode
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oppReadInWmm|0x1 # Opp read during WMM
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsad0|0x0 # Mirror TAD0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[0]|0x0 # Partial Mirror 1 Size (GB)
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[1]|0x0 # Partial Mirror 2 Size (GB)
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[2]|0x0 # Partial Mirror 3 Size (GB)
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[3]|0x0 # Partial Mirror 4 Size (GB)
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pda|0x1 # PDA
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pprErrInjTest|0x0 # PPR Error Injection test
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pprType|0x2 # PPR Type
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteMrcWarnings|0x1 # MRC Promote Warnings
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteWarnings|0x1 # Promote Warnings
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.readVrefCenter|0x1 # Read Vref Centering
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.refreshMode|0x2 # 2x Refresh Enable
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.restoreNVDIMMS|0x1 # Restore NVDIMMs
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseAllDIMMs|0x0 # Erase All DIMMs
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[0]|0x0 # S0 CH0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[1]|0x0 # S0 CH1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[2]|0x0 # S0 CH2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[3]|0x0 # S0 CH3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[4]|0x0 # S0 CH4
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[5]|0x0 # S0 CH5
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[6]|0x0 # S0 CH6
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[7]|0x0 # S0 CH7
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[8]|0x0 # S1 CH0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[9]|0x0 # S1 CH1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[10]|0x0 # S1 CH2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[11]|0x0 # S1 CH3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[12]|0x0 # S1 CH4
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[13]|0x0 # S1 CH5
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[14]|0x0 # S1 CH6
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[15]|0x0 # S1 CH7
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[16]|0x0 # S2 CH0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[17]|0x0 # S2 CH1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[18]|0x0 # S2 CH2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[19]|0x0 # S2 CH3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[20]|0x0 # S2 CH4
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[21]|0x0 # S2 CH5
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[22]|0x0 # S2 CH6
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[23]|0x0 # S2 CH7
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[24]|0x0 # S3 CH0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[25]|0x0 # S3 CH1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[26]|0x0 # S3 CH2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[27]|0x0 # S3 CH3
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[28]|0x0 # S3 CH4
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[29]|0x0 # S3 CH5
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[30]|0x0 # S3 CH6
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[31]|0x0 # S3 CH7
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.smbSpeed|0x2 # SMB Clock Frequency
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.spareErrTh|0x7fff # Correctable Error Threshold
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.spdCrcCheck|0x2 # SPD CRC Check
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tCAS|0x0 # CAS Latency
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tCWL|0x0 # tCWL
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tFAW|0x0 # tFAW
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRAS|0x0 # tRAS
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRC|0x0 # tRC
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRCD|0x0 # tRCD
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tREFI|0x0 # Refresh Rate
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRFC|0x0 # tRFC
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRP|0x0 # tRP
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRRD|0x0 # tRRD
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRRD_L|0x0 # tRRD_L
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRTP|0x0 # tRTP
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tWR|0x0 # tWR
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tWTR|0x0 # tWTR
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.thermalthrottlingsupport|0x2 # Throttling Mode
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.timeWindow|0x0 # Correctable Error Time Window
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOpt|0x1 # Turnaround Time Optimization
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOptDdrt|0x1 # Turnaround Time Optimization PMem
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.txEqCalibration|0x1 # Tx Eq Training
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.volMemMode|0x1 # Volatile Memory Mode
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.wrVrefCenter|0x1 # Write Vref Centering
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[0]|0x1 # Bus Resources Allocation Ratio
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[1]|0x1 # Bus Resources Allocation Ratio
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[2]|0x1 # Bus Resources Allocation Ratio
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[3]|0x1 # Bus Resources Allocation Ratio
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2KtiLinkSpeed|0x3 # Current UPI Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2KtiPortDisable|0x0 # Link Disable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.D2KCreditConfig|0x2 # D2K Credit configuration
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Degrade4SPreference|0x0 # Degraded 4S Topology Preference
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DegradePrecedence|0x0 # Degrade Precedence
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS154|0x5
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS159|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS176|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS181|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS182|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS180|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS178|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS179|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS183|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS167|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS168|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS158|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS164|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS157|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS163|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS151|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS156|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS162|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS187|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS186|0xffffffff
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS152|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS153|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS169|0x4
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS185|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS173|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS177|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS160|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS161|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS170|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS171|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS172|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS184|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS174|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS155|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS165|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS166|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS175|0x5
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DirectoryModeEn|0x2 # Directory Mode Enable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.IoDcMode|0x1 # IO Directory Cache (IODC)
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.IrqThreshold|0x1 # Local/Remote Threshold
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiAdaptationEn|0x2 # UPI Adaptation Enable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiAdaptationSpeed|0x3 # UPI Adaptation Speed
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiCpuSktHotPlugTopology|0x0 # CPU Hot Plug Topology
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiCrcMode|0x2 # CRC Mode
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiFailoverEn|0x2 # UPI Dynamic Link Width Reduction Support
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLbEn|0x0 # UPI Load Board for Failed Links
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkL0pEn|0x2 # Link L0p Enable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkL1En|0x2 # Link L1 Enable
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkVnaOverride|0x7f # UPI VNA Credit Override
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiPrefetchEn|0x2 # KTI Prefetch
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiSkuMismatchCheck|0x1 # CPU SKU Type Mismatch check
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.LLCDeadLineAlloc|0x1 # LLC dead line alloc
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.LegacyVgaSoc|0x0 # Legacy VGA Socket
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.LegacyVgaStack|0x0 # Legacy VGA Stack
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.MbeBwCal|0x3 # MBA BW Calibration
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.P2pRelaxedOrdering|0x0 # PCIe Remote P2P Relaxed Ordering
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.QpiCpuSktHotPlugEn|0x0 # CPU Hot Plug
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.QpiLinkSpeed|0x3 # Link Frequency Select
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.QpiLinkSpeedMode|0x1 # Link Speed Mode
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.RdCurForXptPrefetchEn|0x2 # RdCur for XPT Prefetch
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.SncEn|0x0 # SNC (Sub NUMA)
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.SnoopAllCores|0x2 # Snoop All Cores Configuration
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.SnoopThrottleConfig|0x4 # Snoop Throttle Configuration
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.SplitLock|0x0 # SplitLock
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.StaleAtoSOptEn|0x2 # Stale AtoS
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TorThresLoctoremEmpty|0x1 # Loctorem Thresholds Empty
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TorThresLoctoremNorm|0x1 # Loctorem Thresholds Normal
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TscSyncEn|0x2 # TSC Sync support
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.XptPrefetchEn|0x2 # XPT Prefetch
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.XptRemotePrefetchEn|0x2 # XPT Remote Prefetch
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AcpiS3Enable|0x0 # ACPI S3
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AcpiS4Enable|0x0 # ACPI S4
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AllowLpStateMdfs[0]|0x0 # Allow LP state
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AllowLpStateMdfs[1]|0x0 # Allow LP state
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AllowLpStateMdfs[2]|0x0 # Allow LP state
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AllowLpStateMdfs[3]|0x0 # Allow LP state
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AltEngPerfBIAS|0x7 # ENERGY_PERF_BIAS_CFG mode
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AvxIccpLevel|0x1 # AVX ICCP pre-grant level
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AvxLicensePreGrant|0x0 # AVX Licence Pre-Grant Override
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AvxSupport|0x1 # AVX Support
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.BootPState|0x0 # Boot performance mode
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C1AutoDemotion|0x1 # CPU C1 auto demotion
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C1AutoUnDemotion|0x1 # CPU C1 auto undemotion
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C2C3TT|0x0 # C2C3TT
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C6Enable|0xff # CPU C6 report
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlMultiplier[0]|0x0 # MULTIPLIER:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlMultiplier[1]|0x0 # MULTIPLIER:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlMultiplier[2]|0x0 # MULTIPLIER:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlValid[0]|0x0 # VALID:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlValid[1]|0x0 # VALID:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlValid[2]|0x0 # VALID:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlValue[0]|0x0 # VALUE:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlValue[1]|0x0 # VALUE:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlValue[2]|0x0 # VALUE:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ConfigTdpLevel|0x0 # AVX P1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ConfigTdpLock|0x1 # Config TDP Lock
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CurrentConfig|0x0 # Current Limit Override
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CurrentLimit|0x438 # Current Limitation
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.DynamicIss|0x0 # Dynamic SST-PP
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.DynamicL1|0x0 # Dynamic L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EETurboDisable|0x0 # Energy Efficient Turbo
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EetOverrideEn|0x0 # EET Mode
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Iio[0]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Iio[1]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Iio[2]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Iio[3]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Kti[0]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Kti[1]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Kti[2]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Kti[3]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Rlink[0]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Rlink[1]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Rlink[2]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Rlink[3]|0x0 # Link in L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLowerLatencyMode|0x0 # Register Access Low Latency Mode
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaDino[0]|0x0 # PKGC_CRITERIA DINO
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaDino[1]|0x0 # PKGC_CRITERIA DINO
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaDino[2]|0x0 # PKGC_CRITERIA DINO
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaDino[3]|0x0 # PKGC_CRITERIA DINO
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaFxr[0]|0x0 # PKGC_CRITERIA FXR
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaFxr[1]|0x0 # PKGC_CRITERIA FXR
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaFxr[2]|0x0 # PKGC_CRITERIA FXR
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaFxr[3]|0x0 # PKGC_CRITERIA FXR
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHbm[0]|0x1 # PKGC_CRITERIA HBMx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHbm[1]|0x1 # PKGC_CRITERIA HBMx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHbm[2]|0x1 # PKGC_CRITERIA HBMx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHbm[3]|0x1 # PKGC_CRITERIA HBMx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHcx[0]|0x0 # PKGC_CRITERIA HCX
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHcx[1]|0x0 # PKGC_CRITERIA HCX
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHcx[2]|0x0 # PKGC_CRITERIA HCX
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHcx[3]|0x0 # PKGC_CRITERIA HCX
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHqm[0]|0x0 # PKGC_CRITERIA HQM
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHqm[1]|0x0 # PKGC_CRITERIA HQM
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHqm[2]|0x0 # PKGC_CRITERIA HQM
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaHqm[3]|0x0 # PKGC_CRITERIA HQM
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaIio[0]|0x0 # PKGC_CRITERIA IIOx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaIio[1]|0x0 # PKGC_CRITERIA IIOx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaIio[2]|0x0 # PKGC_CRITERIA IIOx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaIio[3]|0x0 # PKGC_CRITERIA IIOx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaKti[0]|0x0 # PKGC_CRITERIA KTI
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaKti[1]|0x0 # PKGC_CRITERIA KTI
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaKti[2]|0x0 # PKGC_CRITERIA KTI
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaKti[3]|0x0 # PKGC_CRITERIA KTI
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[0]|0xff # PKGC_CRITERIA MCDDRx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[1]|0xff # PKGC_CRITERIA MCDDRx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[2]|0xff # PKGC_CRITERIA MCDDRx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[3]|0xff # PKGC_CRITERIA MCDDRx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMdfs[0]|0x0 # PKGC_CRITERIA MDFS
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMdfs[1]|0x0 # PKGC_CRITERIA MDFS
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMdfs[2]|0x0 # PKGC_CRITERIA MDFS
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMdfs[3]|0x0 # PKGC_CRITERIA MDFS
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaNac[0]|0x0 # PKGC_CRITERIA NAC
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaNac[1]|0x0 # PKGC_CRITERIA NAC
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaNac[2]|0x0 # PKGC_CRITERIA NAC
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaNac[3]|0x0 # PKGC_CRITERIA NAC
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaRlink[0]|0x0 # PKGC_CRITERIA Rlink
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaRlink[1]|0x0 # PKGC_CRITERIA Rlink
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaRlink[2]|0x0 # PKGC_CRITERIA Rlink
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaRlink[3]|0x0 # PKGC_CRITERIA Rlink
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaTip[0]|0x0 # PKGC_CRITERIA TIP
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaTip[1]|0x0 # PKGC_CRITERIA TIP
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaTip[2]|0x0 # PKGC_CRITERIA TIP
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaTip[3]|0x0 # PKGC_CRITERIA TIP
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgcCriteria|0xff # Enable PKGC_SA_PS_CRITERIA
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableProcHot|0x3 # PROCHOT Modes
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableThermalMonitor|0x1 # Thermal Monitor
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableXe|0x1 # Extreme Edition
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EngAvgTimeWdw1|0x1a # Averaging Time Window
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnhancedPmaxDetector|0x1 # PMAX Detector Enhancement
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.FastRaplDutyCycle|0x40 # FAST_RAPL_NSTRIKE_PL2_DUTY_CYCLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.GpssTimer|0x32 # GPSS timer
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio0PkgcClkGateDis[0]|0x0 # IIO0_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio0PkgcClkGateDis[1]|0x0 # IIO0_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio0PkgcClkGateDis[2]|0x0 # IIO0_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio0PkgcClkGateDis[3]|0x0 # IIO0_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio1PkgcClkGateDis[0]|0x0 # IIO1_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio1PkgcClkGateDis[1]|0x0 # IIO1_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio1PkgcClkGateDis[2]|0x0 # IIO1_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio1PkgcClkGateDis[3]|0x0 # IIO1_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio2PkgcClkGateDis[0]|0x0 # IIO2_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio2PkgcClkGateDis[1]|0x0 # IIO2_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio2PkgcClkGateDis[2]|0x0 # IIO2_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio2PkgcClkGateDis[3]|0x0 # IIO2_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.InputUncoreFreq|0x7f # Uncore Freq:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.IoBwPlmtOvrdEn|0x0 # IO_BW_PLIMIT_OVRD_EN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.IomApmOvrdEn|0x0 # IOM_APM_OVERRIDE_ENABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.IssTdpLevel|0x0 # Intel SST-PP
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01PkgcClkGateDis[0]|0x0 # UPI01_PKGC_CLK_GATE_DISABL
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01PkgcClkGateDis[1]|0x0 # UPI01_PKGC_CLK_GATE_DISABL
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01PkgcClkGateDis[2]|0x0 # UPI01_PKGC_CLK_GATE_DISABL
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01PkgcClkGateDis[3]|0x0 # UPI01_PKGC_CLK_GATE_DISABL
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[0]|0x1 # UPI01 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[1]|0x1 # UPI01 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[2]|0x1 # UPI01 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[3]|0x1 # UPI01 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[0]|0x1 # UPI_0_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[1]|0x1 # UPI_0_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[2]|0x1 # UPI_0_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[3]|0x1 # UPI_0_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[0]|0x1 # UPI_1_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[1]|0x1 # UPI_1_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[2]|0x1 # UPI_1_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[3]|0x1 # UPI_1_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23PkgcClkGateDis[0]|0x0 # UPI23_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23PkgcClkGateDis[1]|0x0 # UPI23_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23PkgcClkGateDis[2]|0x0 # UPI23_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23PkgcClkGateDis[3]|0x0 # UPI23_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[0]|0x1 # UPI23 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[1]|0x1 # UPI23 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[2]|0x1 # UPI23 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[3]|0x1 # UPI23 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[0]|0x1 # UPI_2_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[1]|0x1 # UPI_2_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[2]|0x1 # UPI_2_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[3]|0x1 # UPI_2_IN_L1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45PkgcClkGateDis[0]|0x0 # UPI45_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45PkgcClkGateDis[1]|0x0 # UPI45_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45PkgcClkGateDis[2]|0x0 # UPI45_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45PkgcClkGateDis[3]|0x0 # UPI45_PKGC_CLK_GATE_DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[0]|0x1 # UPI45 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[1]|0x1 # UPI45 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[2]|0x1 # UPI45 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[3]|0x1 # UPI45 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.KtiApmOvrdEn|0x0 # UPI_APM_OVERRIDE_ENABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.LTRSwInput|0x1 # LTR IIO Input
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0PkgcClkGateDis[0]|0x0 # MC0 PKGC CLK GATE DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0PkgcClkGateDis[1]|0x0 # MC0 PKGC CLK GATE DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0PkgcClkGateDis[2]|0x0 # MC0 PKGC CLK GATE DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0PkgcClkGateDis[3]|0x0 # MC0 PKGC CLK GATE DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[0]|0x1 # MC0 PLLs Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[1]|0x1 # MC0 PLLs Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[2]|0x1 # MC0 PLLs Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[3]|0x1 # MC0 PLLs Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1PkgcClkGateDis[0]|0x0 # MC1 PKGC CLK GATE DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1PkgcClkGateDis[1]|0x0 # MC1 PKGC CLK GATE DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1PkgcClkGateDis[2]|0x0 # MC1 PKGC CLK GATE DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1PkgcClkGateDis[3]|0x0 # MC1 PKGC CLK GATE DISABLE
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[0]|0x1 # MC1 PLLs Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[1]|0x1 # MC1 PLLs Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[2]|0x1 # MC1 PLLs Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[3]|0x1 # MC1 PLLs Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.MonitorMWait|0x1 # Enable Monitor MWAIT
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NativeAspmEnable|0x2 # Native ASPM
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NonSnpLatMult|0x0 # Non-Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NonSnpLatOvrd|0x0 # Non-Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NonSnpLatVal|0x0 # Non-Snoop Latency Value
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NonSnpLatVld|0x0 # Non-Snoop Latency Override Valid
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.OSCx|0x0 # OS ACPI Cx
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.OnDieThermalThrottling|0x0 # T-State Throttle Level
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.OverclockingLock|0x1 # Overclocking Lock
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0TtlTimeHigh1|0x3f # P0 TotalTimeThreshold High
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0TtlTimeLow1|0x28 # P0 TotalTimeThreshold Low
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[0]|0x1 # PCIe IIO0 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[1]|0x1 # PCIe IIO0 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[2]|0x1 # PCIe IIO0 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[3]|0x1 # PCIe IIO0 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[0]|0x1 # PCIe IIO1 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[1]|0x1 # PCIe IIO1 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[2]|0x1 # PCIe IIO1 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[3]|0x1 # PCIe IIO1 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[0]|0x1 # PCIe IIO2 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[1]|0x1 # PCIe IIO2 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[2]|0x1 # PCIe IIO2 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[3]|0x1 # PCIe IIO2 PLL Shutdown En
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PackageCState|0xff # Package C State
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[0]|0x1 # PCIE Port0 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[1]|0x1 # PCIE Port0 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[2]|0x1 # PCIE Port0 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[3]|0x1 # PCIE Port0 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[0]|0x1 # PCIE Port1 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[1]|0x1 # PCIE Port1 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[2]|0x1 # PCIE Port1 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[3]|0x1 # PCIE Port1 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[0]|0x1 # PCIE Port2 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[1]|0x1 # PCIE Port2 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[2]|0x1 # PCIE Port2 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[3]|0x1 # PCIE Port2 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[0]|0x1 # PCIE Port3 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[1]|0x1 # PCIE Port3 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[2]|0x1 # PCIE Port3 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[3]|0x1 # PCIE Port3 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[0]|0x1 # PCIE Port4 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[1]|0x1 # PCIE Port4 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[2]|0x1 # PCIE Port4 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[3]|0x1 # PCIE Port4 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[0]|0x1 # PCIE Port5 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[1]|0x1 # PCIE Port5 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[2]|0x1 # PCIE Port5 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[3]|0x1 # PCIE Port5 PCIE_IN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcodeWdogTimerEn|0x2 # Pcode Dispatcher Watchdog Timer
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLimitClipC|0x1f # Perf P-Limit Clip
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLimitEn|0x1 # Perf P Limit
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLmtThshld|0xf # Perf P-Limit Threshold
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPlimitDifferential|0x1 # Perf P-Limit Differential
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskDino[0]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskDino[1]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskDino[2]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskDino[3]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskFxr[0]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskFxr[1]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskFxr[2]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskFxr[3]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskHcx[0]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskHcx[1]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskHcx[2]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskHcx[3]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskHqm[0]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskHqm[1]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskHqm[2]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskHqm[3]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskNac[0]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskNac[1]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskNac[2]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskNac[3]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskTip[0]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskTip[1]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskTip[2]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowedPsMaskTip[3]|0x0 # PKGC_ALLOWED_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoDino[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoDino[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoDino[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoDino[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoFxr[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoFxr[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoFxr[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoFxr[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHbm[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHbm[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHbm[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHbm[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHcx[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHcx[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHcx[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHcx[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHqm[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHqm[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHqm[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoHqm[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoIio[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoIio[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoIio[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoIio[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoKti[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoKti[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoKti[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoKti[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoMcddr[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoMcddr[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoMcddr[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoMcddr[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoMdfs[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoMdfs[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoMdfs[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoMdfs[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoNac[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoNac[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoNac[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoNac[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoRlink[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoRlink[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoRlink[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoRlink[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoTip[0]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoTip[1]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoTip[2]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstanceNoTip[3]|0x0 # Instance_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpType[0]|0x0 # CPU0 Logical_ip_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpType[1]|0x0 # CPU1 Logical_ip_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpType[2]|0x0 # CPU2 Logical_ip_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpType[3]|0x0 # CPU3 Logical_ip_type
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeHbm[0]|0x18 # HBM:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeHbm[1]|0x18 # HBM:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeHbm[2]|0x18 # HBM:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeHbm[3]|0x18 # HBM:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[0]|0x20 # IIO:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[1]|0x20 # IIO:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[2]|0x20 # IIO:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[3]|0x20 # IIO:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[0]|0x10 # MCDDR:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[1]|0x10 # MCDDR:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[2]|0x10 # MCDDR:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[3]|0x10 # MCDDR:
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCLatNeg|0x1 # PKG C-state Lat. Neg.
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCstEntryValCtl|0x0 # PKGC_ENTRY_CRITERIA OVRD
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskDino[0]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskDino[1]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskDino[2]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskDino[3]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskFxr[0]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskFxr[1]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskFxr[2]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskFxr[3]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskHcx[0]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskHcx[1]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskHcx[2]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskHcx[3]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskHqm[0]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskHqm[1]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskHqm[2]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskHqm[3]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskNac[0]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskNac[1]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskNac[2]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskNac[3]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskTip[0]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskTip[1]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskTip[2]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskTip[3]|0x0 # PKGC_CRITERIA_PS_MASK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOptionHbm[0]|0x0 # HBM Option
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOptionHbm[1]|0x0 # HBM Option
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOptionHbm[2]|0x0 # HBM Option
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOptionHbm[3]|0x0 # HBM Option
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOptionMcddr[0]|0x0 # MCDDR Option
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOptionMcddr[1]|0x0 # MCDDR Option
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOptionMcddr[2]|0x0 # MCDDR Option
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOptionMcddr[3]|0x0 # MCDDR Option
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxAutoAdjustment|0x0 # BIOS Auto Adjustment
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxDetector|0x1 # Detector
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxLoadLine|0x0 # DC LL Select
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxOffset|0x0 # PMAX Config Positive Offset
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxOffsetNegative|0x0 # PMAX Config Negative Offset
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxSign|0x0 # PMAX Config Sign
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxTriggerSetup|0x0 # Trigger Setup
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit1En|0x1 # PL1 Limit
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit1Power|0x0 # PL1 Power Limit
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit1Time|0x1 # PL1 Time Window
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit2En|0x1 # PL2 Limit
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit2Power|0x0 # PL2 Power Limit
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit2Time|0x1 # PL2 Time Window
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PpcccLock|0x1 # Lock Indication
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorAPSrocketing|0x0 # APS rocketing
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorActivePbf|0x0 # Activate SST-BF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorC1eEnable|0x1 # Enhanced Halt State (C1E)
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorConfigurePbf|0x1 # Configure SST-BF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEPPEnable|0x1 # EPP Enable
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEistEnable|0x1 # SpeedStep (Pstates)
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEistPsdFunc|0x0 # EIST PSD Function
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEppProfile|0x80 # EPP profile
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorHWPMEnable|0x1 # Hardware P-States
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorHWPMInterrupt|0x0 # HardwarePM Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorOutofBandAlternateEPB|0x0 # PECI PCS EPB
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorRaplPrioritization|0x0 # RAPL Prioritization
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorScalability|0x0 # Scalability
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProchotLock|0x1 # PROCHOT LOCK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProchotResponseRatio|0x0 # PROCHOT RATIO
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PwrPerfSwitch|0x1 # Dynamic Loadline Switch
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PwrPerfTuning|0x0 # Power Performance Tuning
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.RunCpuPpmInPei|0x0 # Run CPU PPM code in PEI
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SAPMControl|0x0 # SAPM Control
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[0]|0x1 # SAPMCTL_CFG LOCK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[1]|0x1 # SAPMCTL_CFG LOCK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[2]|0x1 # SAPMCTL_CFG LOCK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[3]|0x1 # SAPMCTL_CFG LOCK
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SetvidDecayDisable[0]|0x0 # SetVID Decay Disable
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SetvidDecayDisable[1]|0x0 # SetVID Decay Disable
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SetvidDecayDisable[2]|0x0 # SetVID Decay Disable
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SetvidDecayDisable[3]|0x0 # SetVID Decay Disable
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SnpLatMult|0x0 # Snoop Latency Multiplier
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SnpLatOvrd|0x0 # Force Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SnpLatVal|0x0 # Force Non-Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SnpLatVld|0x0 # Snoop Latency Override
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SwLtrOvrdCtl|0x0 # PCIe LTR Override Control
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TCCActivationOffset|0x0 # TCC Activation Offset
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TStateEnable|0x0 # Software Controlled T-States
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ThermalMonitorStatusFilter|0x0 # Therm-Monitor-Status Filter
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ThermalMonitorStatusFilterTimeWindow|0x9 # Therm-Monitor-Status Filter Time Window
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboMode|0x1 # Turbo Mode
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboPowerLimitCsrLock|0x1 # Package RAPL Limit CSR Lock
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboPowerLimitLock|0x0 # Package RAPL Limit MSR Lock
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[0]|0xff # TurboRatioCores0
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[1]|0xff # TurboRatioCores1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[2]|0xff # TurboRatioCores2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[3]|0xff # TurboRatioCores3
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[4]|0xff # TurboRatioCores4
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[5]|0xff # TurboRatioCores5
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[6]|0xff # TurboRatioCores6
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[7]|0xff # TurboRatioCores7
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRatio[0]|0x0 # TurboRatioLimit0
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRatio[1]|0x0 # TurboRatioLimit1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRatio[2]|0x0 # TurboRatioLimit2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRatio[3]|0x0 # TurboRatioLimit3
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRatio[4]|0x0 # TurboRatioLimit4
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRatio[5]|0x0 # TurboRatioLimit5
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRatio[6]|0x0 # TurboRatioLimit6
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRatio[7]|0x0 # TurboRatioLimit7
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.UncoreFreqRaplLimit|0x1 # Uncore Freq RAPL
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.UncoreFreqScaling|0x1 # Uncore Freq Scaling
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.UncrPerfPlmtOvrdEn|0x1 # UNCORE_PERF_PLIMIT_OVRD_EN
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.VccSAandVccIOdisable|0x0 # VccSA/VccIO Disable
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.WFRWAEnable|0x0
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.WorkLdConfig|0x0 # Workload Configuration
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AcExceptionOnSplitLockEnable|0x0 # #AC Exception On Split Lock
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AcmType|0x0 # ACM Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AesEnable|0x1 # AES-NI
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AllowMixedPowerOnCpuRatio|0x0 # Skip Flex Ratio Override
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AmpPrefetchEnable|0x0 # AMP Prefetch
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.BiosAcmErrorReset|0x0 # BIOS ACM Error Reset
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.BspSelection|0xff # Bsp Selection
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CFRPucodeEnable|0x0 # Processor Pcode/Ucode CFR
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CFRPucodeManualCommit|0x0 # Manual Commit Pcode/Ucode CFR
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CFRS3mEnable|0x0 # Processor S3M CFR
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CFRS3mManualCommit|0x0 # Manual Commit S3M FW CFR
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CheckCpuBist|0x1 # Check CPU BIST Result
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[0]|0x0 # Disable Bitmap
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[1]|0x0 # Disable Bitmap
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[2]|0x0 # Disable Bitmap
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[3]|0x0 # Disable Bitmap
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreFailover|0x1 # Core Failover
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuCrashLogGprs|0x0 # Cpu CrashLog Gprs
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuDbpEnable|0x0 # DBP-F
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuL1NextPagePrefetcherDisable|0x0 # L1 Next Page Prefetcher
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuMtoIWa|0x1 # MtoI Workaround
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuPaLimit|0x1 # Limit CPU PA to 46 bits
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuidMaxValue|0x0 # Max CPUID Value Limit
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CrDimmsPresent|0x0 # SW Guard Extensions (SGX)
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DCUIPPrefetcherEnable|0x1 # DCU IP Prefetcher
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DCUModeSelection|0x0 # DCU Mode
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DCUStreamerPrefetcherEnable|0x1 # DCU Streamer Prefetcher
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DebugInterface|0x0 # DEBUG INTERFACE
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS245|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS192|0x0
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS234|0x0
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS241|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS238|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS242|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS244|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS240|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS243|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS236|0x0
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS237|0x0
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS235|0x0 # TME key restore
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EnableMktme|0x0 # Total Memory Encryption Multi-Tenant(TME-MT)
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EnableSaf|0x0 # Enable FuSa (SAF) - variable to handle dynamic BIOS menu
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EnableSgx|0x0 # SW Guard Extensions (SGX)
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EnableTme|0x0 # Total Memory Encryption (TME)
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EpochUpdate|0x2 # Select Owner EPOCH input type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.FastStringEnable|0x1 # Fast String
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ForcePhysicalModeEnable|0x0 # APIC Physical Mode
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.GlobalPsmiEnable|0x1 # Global PSMI Enable
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IedTraceSize|0x0 # IED Trace memory
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IioLlcWaysMask|0x0 # IIO LLC Ways [19:0](Hex)
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IotEn[0]|0x0 # IOT Cfg
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IotEn[1]|0x0 # IOT Cfg
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IotEn[2]|0x0 # IOT Cfg
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IotEn[3]|0x0 # IOT Cfg
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.L2RfoPrefetchDisable|0x0 # L2 RFO Prefetch Disable
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.LlcPrefetchEnable|0x1 # LLC Prefetch
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.LockChipset|0x1 # Lock Chipset
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MachineCheckEnable|0x1 # Machine Check
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MlcSpatialPrefetcherEnable|0x1 # Adjacent Cache Prefetch
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MlcStreamerPrefetcherEnable|0x1 # Hardware Prefetcher
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[0]|0x1 # OCLA Tor IDs
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[1]|0x1 # OCLA Tor IDs
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[2]|0x1 # OCLA Tor IDs
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[3]|0x1 # OCLA Tor IDs
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[0]|0x1 # Num of OCLA ways
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[1]|0x1 # Num of OCLA Ways
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[2]|0x1 # Num of OCLA Ways
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[3]|0x1 # Num of OCLA Ways
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PCIeDownStreamPECIWrite|0x0 # Down Stream PECI
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciAgtEspiTrustBit|0x0 # eSPI Agent
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciAgtGenericTrustBit|0x0 # Generic Agent
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciAgtIeTrustBit|0x1 # IE Agent
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciAgtLegacyTrustBit|0x1 # Legacy Agent
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciAgtSmbusTrustBit|0x0 # SMBus Agent
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciInTrustControlBit|0x1 # PECI
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PpinControl|0x1 # PPIN Control
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PrmrrSize|0x80000000 # PRMRR Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorFlexibleRatio|0x17 # CPU Core Flex Ratio
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorFlexibleRatioOverrideEnable|0x0 # CPU Flex Ratio Override
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorHyperThreadingDisable|0x0 # Hyper-Threading [ALL]
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorLtsxEnable|0x0 # Enable Intel(R) TXT
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorMsrLockControl|0x1 # MSR Lock Control
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorMsrPkgCstConfigControlLock|0x1 # PKG CST CONFIG CONTROL MSR Lock
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorSmxEnable|0x0 # Enable SMX
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorVmxEnable|0x1 # VMX
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorX2apic|0x1 # Extended APIC
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[0]|0x1 # PSMI Handler Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[1]|0x1 # PSMI Handler Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[2]|0x1 # PSMI Handler Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[3]|0x1 # PSMI Handler Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTrace[0]|0x0 # PSMI Enable
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTrace[1]|0x0 # PSMI Enable
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTrace[2]|0x0 # PSMI Enable
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTrace[3]|0x0 # PSMI Enable
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[0]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[1]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[2]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[3]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[0]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[1]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[2]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[3]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[0]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[1]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[2]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[3]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[0]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[1]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[2]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[3]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[0]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[1]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[2]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[3]|0x1 # Buffer Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion0[0]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion0[1]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion0[2]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion0[3]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion1[0]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion1[1]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion1[2]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion1[3]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion2[0]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion2[1]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion2[2]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion2[3]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion3[0]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion3[1]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion3[2]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion3[3]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion4[0]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion4[1]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion4[2]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegion4[3]|0x0 # Cache Type
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion0[0]|0x0 # PSMI Trace Region 0
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion0[1]|0x0 # PSMI Trace Region 0
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion0[2]|0x0 # PSMI Trace Region 0
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion0[3]|0x0 # PSMI Trace Region 0
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion1[0]|0x0 # PSMI Trace Region 1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion1[1]|0x0 # PSMI Trace Region 1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion1[2]|0x0 # PSMI Trace Region 1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion1[3]|0x0 # PSMI Trace Region 1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion2[0]|0x0 # PSMI Trace Region 2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion2[1]|0x0 # PSMI Trace Region 2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion2[2]|0x0 # PSMI Trace Region 2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion2[3]|0x0 # PSMI Trace Region 2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion3[0]|0x0 # PSMI Trace Region 3
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion3[1]|0x0 # PSMI Trace Region 3
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion3[2]|0x0 # PSMI Trace Region 3
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion3[3]|0x0 # PSMI Trace Region 3
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion4[0]|0x0 # PSMI Trace Region 4
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion4[1]|0x0 # PSMI Trace Region 4
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion4[2]|0x0 # PSMI Trace Region 4
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion4[3]|0x0 # PSMI Trace Region 4
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.RdtCatOpportunisticTuning|0x0 # RDT CAT Opportunistic Tuning
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.RemoteWaysMask|0x0 # Remote Ways [22:12](Hex)
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxAutoRegistrationAgent|0x0 # Enable/Disable SGX Auto MP Registration Agent
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxDebugMode|0x0 # Enable/Disable SGX Debug Mode
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxEpoch0|0x0 # Software Guard Extensions Epoch 0
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxEpoch1|0x0 # Software Guard Extensions Epoch 1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxFactoryReset|0x0 # SGX Factory Reset
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLePubKeyHash0|0x0 # SGXLEPUBKEYHASH0
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLePubKeyHash1|0x0 # SGXLEPUBKEYHASH1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLePubKeyHash2|0x0 # SGXLEPUBKEYHASH2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLePubKeyHash3|0x0 # SGXLEPUBKEYHASH3
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLeWr|0x1 # SGXLEPUBKEYHASHx Write Enable
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxPackageInfoInBandAccess|0x0 # SGX Package Info In-Band Access
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxQoS|0x1 # SGX QoS
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SmbusErrorRecovery|0x1 # Smbus Error Recovery
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SmmBlockedDelayed|0x0 # SMM Blocked and Delayed
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ThreeStrikeTimer|0x1 # 3StrikeTimer
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.TscResetEnable|0x0 # TSC Reset
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.TsegSize|0x5 # TSEG Smram Size
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.eSmmSaveState|0x0 # eSMM Save State
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.BaseAboveFourGiga|0x100000000 # Mega-Block base above 4GB
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.BaseAboveOneMega|0x100000 # Mega-Block base above 1MB
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.BaseBelowOneMega|0x50000 # Mega-Block base below 1MB
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.CoreMegaBlock|0x0 # Core Mega Block Support
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUnUsedAboveFourGiga|0x0 # Mega-Block non-used policy above 4GB
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUnUsedAboveOneMega|0x0 # Mega-Block non-used policy above 1MB
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUnUsedBelowOneMega|0x0 # Mega-Block non-used policy below 1MB
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUsedAboveFourGiga|0x4 # Mega-Block policy above 4GB
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUsedAboveOneMega|0x4 # Mega-Block policy above 1MB
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUsedBelowOneMega|0x4 # Mega-Block policy below 1MB
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.SizeAboveFourGiga|0x0 # Mega-Block size above 4GB
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.SizeAboveOneMega|0x0 # Mega-Block size above 1MB
+gStructPcdTokenSpaceGuid.PcdSvConfiguration.SizeBelowOneMega|0x0 # Mega-Block size below 1MB
+gStructPcdTokenSpaceGuid.PcdTCG2_CONFIGURATION.TpmDevice|0x1 # Attempt TPM Device
+gStructPcdTokenSpaceGuid.PcdTCG2_VERSION.PpiVersion|0x332e31 # Attempt PPI Version
+gStructPcdTokenSpaceGuid.PcdTCG2_VERSION.Tpm2AcpiTableRev|0x4 # Attempt Rev of TPM2 ACPI Table
+
+[PcdsDynamicHii.common.DEFAULT.MANUFACTURING]
+gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_IeResetPrepDone|0x0 # IE Reset Prep Done
+gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_MeResetPrepDone|0x0 # ME Reset Prep Done
+gStructPcdTokenSpaceGuid.PcdSetup.StorageOpROMSuppression|0x1 # Storage OPROM Suppression
+gStructPcdTokenSpaceGuid.PcdSetup.TagecMem|0x1 # Reserve TAGEC Memory
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS117|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemHotOuputAssertThreshold|0x0 # MEMHOT Output Throttling Mode Options
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PCIeDownStreamPECIWrite|0x1 # Down Stream PECI
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorMsrLockControl|0x0 # MSR Lock Control
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorVmxEnable|0x0 # VMX
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc
new file mode 100644
index 0000000000..0c166ade00
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc
@@ -0,0 +1,3796 @@
+## @file
+# @copyright
+# Copyright 2019 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08
+
+[SkuIds]
+ 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
+
+[DefaultStores]
+ 0|STANDARD # UEFI Standard default 0|STANDARD is reserved.
+ 1|MANUFACTURING # UEFI Manufacturing default 1|MANUFACTURING is reserved.
+
+[PcdsDynamicExVpd.common.DEFAULT]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdNvStoreDefaultValueBuffer|*
+
+[PcdsDynamicExHii.common.DEFAULT.STANDARD]
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|L"FpgaSocketConfig"|gFpgaSocketVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|L"SocketMemoryConfig"|gEfiSocketMemoryVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdPchSetup|L"PchSetup"|gPchSetupVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|L"SocketProcessorCoreConfig"|gEfiSocketProcessorCoreVarGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSetup|L"Setup"|gCommonSystemConfigurationGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|L"SocketCommonRcConfig"|gEfiSocketCommonRcVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|L"SocketPowerManagementConfig"|gEfiSocketPowermanagementVarGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|L"SocketMpLinkConfig"|gEfiSocketMpLinkVariableGuid|0x00||NV, BS, RT
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig|L"SocketIioConfig"|gEfiSocketIioVariableGuid|0x00||NV, BS, RT
+
+!if $(TARGET) == "DEBUG"
+gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvl|0x4
+gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvlTrainResults|0x8
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DebugPrintLevel|0xF
+!else
+gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvl|0x0
+gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvlTrainResults|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DebugPrintLevel|0x0
+!endif
+
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ATS|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[8]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[9]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[10]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[11]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[12]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[13]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[14]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[15]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[16]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[17]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[18]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[19]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[20]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[21]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[22]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[23]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[24]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[25]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[26]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[27]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[28]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[29]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[30]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[31]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CbDmaMultiCastEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CoherencySupport|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobal|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobalValue|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[0]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[1]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[2]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[3]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[0]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[1]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[2]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[3]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[0]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[1]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[2]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[3]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[0]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[1]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[2]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[3]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[0]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[1]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[2]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[3]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[0]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[1]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[2]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[3]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[8]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[9]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[10]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[11]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[12]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[13]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[14]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[15]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[16]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[17]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[18]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[19]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[20]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[21]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[22]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[23]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[24]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[25]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[26]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[27]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[28]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[29]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[30]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[31]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[32]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[33]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[34]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[35]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[36]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[37]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[38]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[39]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[40]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[41]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[42]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[43]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[44]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[45]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[46]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[47]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[48]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[49]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[50]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[51]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[52]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[53]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[54]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[55]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[56]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[57]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[58]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[59]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[60]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[61]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[62]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[63]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[64]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[65]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[66]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[67]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[68]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[69]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[70]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[71]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[72]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[73]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[74]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[75]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[76]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[77]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[78]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[79]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[80]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[81]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[82]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[83]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[8]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[9]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[10]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[11]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[12]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[13]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[14]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[15]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[16]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[17]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[18]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[19]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[20]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[21]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[22]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[23]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS19|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[0]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[1]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[2]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[3]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[4]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[5]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[6]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[7]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[8]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[9]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[10]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[11]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[12]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[13]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[14]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[15]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[16]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[17]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[18]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[19]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[20]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[21]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[22]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[23]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[24]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[25]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[26]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[27]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[28]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[29]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[30]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[31]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[32]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[33]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[34]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[35]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[36]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[37]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[38]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[39]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[40]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[41]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[42]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[43]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[44]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[45]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[46]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[47]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[48]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[49]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[50]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[51]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[52]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[53]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[54]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[55]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[56]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[57]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[58]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[59]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[60]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[61]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[62]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[63]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[64]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[65]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[66]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[67]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[68]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[69]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[70]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[71]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[72]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[73]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[74]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[75]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[76]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[77]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[78]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[79]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[80]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[81]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[82]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[83]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[0]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[1]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[2]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[3]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[4]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[5]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[6]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[7]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[8]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[9]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[10]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[11]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[12]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[13]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[14]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[15]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[16]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[17]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[18]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[19]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[20]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[21]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[22]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[23]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[24]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[25]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[26]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[27]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[28]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[29]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[30]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[31]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[32]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[33]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[34]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[35]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[36]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[37]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[38]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[39]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[40]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[41]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[42]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[43]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[44]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[45]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[46]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[47]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[48]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[49]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[50]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[51]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[52]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[53]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[54]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[55]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[56]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[57]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[58]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[59]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[60]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[61]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[62]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[63]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[64]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[65]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[66]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[67]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[68]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[69]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[70]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[71]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[72]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[73]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[74]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[75]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[76]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[77]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[78]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[79]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[80]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[81]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[82]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[83]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[0]|0xB
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[2]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[3]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[4]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[5]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[6]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[7]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[8]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[9]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[10]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[11]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[12]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[13]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[14]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[15]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[16]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[17]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[18]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[19]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[20]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[21]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[22]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[23]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[24]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[25]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[26]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[27]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[28]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[29]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[30]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[31]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[32]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[33]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[34]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[35]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[36]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[37]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[38]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[39]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[40]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[41]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[42]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[43]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[44]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[45]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[46]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[47]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[48]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[49]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[50]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[51]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[52]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[53]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[54]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[55]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[56]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[57]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[58]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[59]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[60]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[61]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[62]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[63]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[64]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[65]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[66]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[67]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[68]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[69]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[70]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[71]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[72]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[73]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[74]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[75]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[76]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[77]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[78]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[79]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[80]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[81]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[82]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS27[83]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[0]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[1]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[2]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[3]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[4]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[5]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[6]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[7]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[8]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[9]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[10]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[11]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[12]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[13]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[14]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[15]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[16]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[17]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[18]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[19]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[20]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[21]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[22]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[23]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[24]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[25]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[26]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[27]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[28]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[29]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[30]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[31]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[32]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[33]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[34]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[35]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[36]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[37]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[38]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[39]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[40]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[41]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[42]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[43]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[44]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[45]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[46]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[47]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[48]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[49]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[50]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[51]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[52]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[53]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[54]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[55]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[56]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[57]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[58]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[59]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[60]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[61]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[62]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[63]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[64]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[65]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[66]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[67]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[68]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[69]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[70]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[71]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[72]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[73]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[74]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[75]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[76]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[77]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[78]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[79]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[80]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[81]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[82]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS25[83]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[0]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[1]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[2]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[3]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[4]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[5]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[6]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[7]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[8]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[9]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[10]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[11]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[12]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[13]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[14]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[15]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[16]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[17]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[18]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[19]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[20]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[21]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[22]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[23]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[24]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[25]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[26]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[27]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[28]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[29]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[30]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[31]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[32]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[33]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[34]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[35]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[36]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[37]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[38]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[39]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[40]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[41]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[42]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[43]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[44]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[45]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[46]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[47]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[48]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[49]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[50]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[51]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[52]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[53]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[54]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[55]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[56]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[57]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[58]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[59]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[60]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[61]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[62]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[63]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[64]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[65]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[66]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[67]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[68]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[69]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[70]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[71]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[72]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[73]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[74]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[75]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[76]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[77]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[78]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[79]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[80]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[81]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[82]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS29[83]|0x29
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[0]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[1]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[2]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[3]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[4]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[5]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[6]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[7]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[8]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[9]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[10]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[11]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[12]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[13]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[14]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[15]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[16]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[17]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[18]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[19]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[20]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[21]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[22]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[23]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[24]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[25]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[26]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[27]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[28]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[29]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[30]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[31]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[32]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[33]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[34]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[35]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[36]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[37]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[38]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[39]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[40]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[41]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[42]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[43]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[44]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[45]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[46]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[47]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[48]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[49]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[50]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[51]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[52]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[53]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[54]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[55]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[56]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[57]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[58]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[59]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[60]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[61]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[62]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[63]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[64]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[65]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[66]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[67]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[68]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[69]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[70]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[71]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[72]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[73]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[74]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[75]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[76]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[77]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[78]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[79]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[80]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[81]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[82]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS30[83]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[0]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[1]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[2]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[3]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[4]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[5]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[6]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[7]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[8]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[9]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[10]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[11]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[12]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[13]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[14]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[15]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[16]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[17]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[18]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[19]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[20]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[21]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[22]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[23]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[24]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[25]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[26]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[27]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[28]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[29]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[30]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[31]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[32]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[33]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[34]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[35]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[36]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[37]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[38]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[39]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[40]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[41]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[42]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[43]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[44]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[45]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[46]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[47]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[48]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[49]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[50]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[51]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[52]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[53]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[54]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[55]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[56]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[57]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[58]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[59]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[60]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[61]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[62]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[63]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[64]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[65]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[66]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[67]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[68]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[69]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[70]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[71]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[72]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[73]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[74]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[75]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[76]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[77]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[78]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[79]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[80]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[81]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[82]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS28[83]|0xB
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS17|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS16|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS14|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS13|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS12|0x99
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS18|0x4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[0]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[1]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[2]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[3]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[4]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[5]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[6]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[7]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[8]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[9]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[10]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[11]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[12]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[13]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[14]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[15]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[16]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[17]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[18]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[19]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[20]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[21]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[22]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[23]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[24]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[25]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[26]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[27]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[28]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[29]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[30]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[31]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[32]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[33]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[34]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[35]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[36]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[37]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[38]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[39]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[40]|0xFF
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS40[64]|0xFF
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[0]|0xFF
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[4]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[5]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[6]|0xFF
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DmiAllocatingFlow|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DualCvIoFlow|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[58]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[60]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[61]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[63]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[64]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[65]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[66]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[67]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[68]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[69]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[70]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[71]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[72]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[74]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[75]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[76]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[77]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[78]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[79]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[80]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[82]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HidePEXPMenu[83]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.InterruptRemap|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[0]|0x6
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[19]|0x6
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[21]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[22]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[23]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[24]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[25]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[26]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[27]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[28]|0x6
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[30]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[31]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[32]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[33]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[34]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[35]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[36]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[37]|0x6
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[40]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[41]|0x6
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[43]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[44]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[45]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[46]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[47]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[48]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[49]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[50]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[51]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[52]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[53]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[54]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[55]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[56]|0x6
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[59]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[60]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[61]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[62]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[63]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[64]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[65]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[66]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[67]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[68]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[69]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[70]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[71]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[72]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[73]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[74]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[75]|0x6
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[78]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[79]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[80]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[81]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[82]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[83]|0x6
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.McastIndexPosition|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.McastNumGroup|0x8
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[0]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[5]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[7]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[9]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[14]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[15]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[16]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[17]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[18]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[19]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[20]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[22]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[24]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[25]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[28]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[30]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[32]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[33]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[34]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[35]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[36]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[37]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[38]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[39]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[40]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[41]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[42]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[43]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[45]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[46]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[47]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[48]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[49]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[50]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[51]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[52]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[53]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[54]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[55]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[56]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[57]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[58]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[59]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[60]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[61]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[62]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[63]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[64]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[65]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[66]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[67]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[68]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[69]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[70]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[71]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[72]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[73]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[74]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[75]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[76]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[77]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[78]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[79]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[80]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[81]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[82]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[83]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NoSnoopWrCfg|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[0]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[1]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[2]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[3]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[4]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[5]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[6]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[7]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[8]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[9]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[10]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[11]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[12]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[13]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[14]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[15]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[16]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[17]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[18]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[19]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[0]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[1]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[2]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[3]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[4]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[5]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[6]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[7]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[8]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[9]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[10]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[11]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[12]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[13]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[14]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[15]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[16]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[17]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[18]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[19]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[0]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[1]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[2]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[3]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[4]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[5]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[6]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[7]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[8]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[9]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[10]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[11]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[12]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[13]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[14]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[15]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[16]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[17]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[18]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[19]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[0]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[1]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[2]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[3]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[4]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[5]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[6]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[7]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[8]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[9]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[10]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[11]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[12]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[13]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[14]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[15]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[16]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[17]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[18]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[19]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[0]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[1]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[2]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[3]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[4]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[5]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[6]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[7]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[8]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[9]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[10]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[11]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[12]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[13]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[14]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[15]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[16]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[17]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[18]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[19]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[0]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[1]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[2]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[3]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[4]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[5]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[6]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[7]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[8]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[9]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[10]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[11]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[12]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[13]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[14]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[15]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[16]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[17]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[18]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[19]|0x16
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[0]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[1]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[2]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[3]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[4]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[5]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[6]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[7]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[8]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[9]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[10]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[11]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[12]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[13]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[14]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[15]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[16]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[17]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[18]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[19]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[0]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[1]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[2]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[3]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[4]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[5]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[6]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[7]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[8]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[9]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[10]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[11]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[12]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[13]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[14]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[15]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[16]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[17]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[18]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[19]|0xC
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbLinkBiosTrainEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[0]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[1]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[2]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[3]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[4]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[5]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[6]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[7]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[8]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[9]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[10]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[11]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[12]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[13]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[14]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[15]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[16]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[17]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[18]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[19]|0x3
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Pci64BitResourceAllocation|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_LTR|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAllocatingFlow|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[0]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[1]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[2]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[3]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[4]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[5]|0x2
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[7]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[8]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[9]|0x2
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[14]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[15]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[16]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[17]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[18]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[19]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[20]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[21]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[22]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[23]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[24]|0x2
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[26]|0x2
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[32]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[33]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[34]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[35]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[36]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[37]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[38]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[39]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[40]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[41]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[42]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[43]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[44]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[45]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[46]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[47]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[48]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[49]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[50]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[51]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[52]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[53]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[54]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[55]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[56]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[57]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[58]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[59]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[60]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[61]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[62]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[63]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[64]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[65]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[66]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[67]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[68]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[69]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[70]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[71]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[72]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[73]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[74]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[75]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[76]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[77]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[78]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[79]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[80]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[81]|0x2
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[83]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieBiosTrainEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[8]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[9]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[10]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[11]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[12]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[13]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[14]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[15]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[16]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[17]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[18]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[19]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[20]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[21]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[22]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[23]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[24]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[25]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[26]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[27]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[28]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[29]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[30]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[31]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[32]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[33]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[34]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[35]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[36]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[37]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[38]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[39]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[40]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[41]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[42]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[43]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[44]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[45]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[46]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[47]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[48]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[49]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[50]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[51]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[52]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[53]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[54]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[55]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[56]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[57]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[58]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[59]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[60]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[61]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[62]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[63]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[64]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[65]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[66]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[67]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[68]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[69]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[70]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[71]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[72]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[73]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[74]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[75]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[76]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[77]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[78]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[79]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[80]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[81]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[82]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[83]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[2]|0x1
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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[10]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[11]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[12]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[13]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[14]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[15]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[16]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[17]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[18]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[19]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[20]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[21]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[22]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[23]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[24]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[25]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[26]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[27]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[28]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[29]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[30]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[31]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[32]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[33]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[34]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[35]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[36]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[37]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[38]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[39]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[40]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[41]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[42]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[43]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[44]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[45]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[46]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[47]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[48]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[49]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[50]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[51]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[52]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[53]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[54]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[55]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[56]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[57]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[58]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[59]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[60]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[61]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[62]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[63]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[64]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[65]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[66]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[67]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[68]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[69]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[70]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[71]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[72]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[73]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[74]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[75]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[76]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[77]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[78]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[79]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[80]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[81]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[82]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[83]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[1]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[2]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[3]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[4]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[5]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[6]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[7]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[8]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[9]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[10]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[11]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[12]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[13]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[14]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[15]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[16]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[17]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[18]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[19]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[20]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[21]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[22]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[23]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[24]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[25]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[26]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[27]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[28]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[29]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[30]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[31]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[32]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[33]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[34]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[35]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[36]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[37]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[38]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[39]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[40]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[41]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[42]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[43]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[44]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[45]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[46]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[47]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[48]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[49]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[50]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[51]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[52]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[53]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[54]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[55]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[56]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[57]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[58]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[59]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[60]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[61]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[62]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[63]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[64]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[65]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[66]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[67]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[68]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[69]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[70]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[71]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[72]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[73]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[74]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[75]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[76]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[77]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[78]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[79]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[80]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[81]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[82]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[83]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePtm|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieRelaxedOrdering|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom1|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom2|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom3|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom4|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom5|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom6|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom7|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom8|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PerformanceTuningMode|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PostedInterrupt|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SnoopResponseHoldOff|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[1]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[2]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[3]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[4]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[5]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[7]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[8]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[9]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[10]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[11]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[13]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[14]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[15]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[16]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[17]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[19]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[20]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[21]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[22]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[23]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[1]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[2]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[3]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[4]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[5]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[7]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[8]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[9]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[10]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[11]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[13]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[14]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[15]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[16]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[17]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[19]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[20]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[21]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[22]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[23]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[8]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[9]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[10]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[11]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[13]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[14]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[15]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[16]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[17]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[19]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[20]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[21]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[22]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[23]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[1]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[2]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[3]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[4]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[5]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[7]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[8]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[9]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[10]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[11]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[13]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[14]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[15]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[16]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[17]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[19]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[20]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[21]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[22]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[23]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[1]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[2]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[3]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[4]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[5]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[7]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[8]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[9]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[10]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[11]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[13]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[14]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[15]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[16]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[17]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[19]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[20]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[21]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[22]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[23]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdAcsWa|0x1
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmiohBase|0x2
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmiohSize|0x3
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmcfgBase|0x6
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmcfgSize|0x6
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.IsocEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.NumaEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS6|0xF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[0]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[1]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[2]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[3]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[4]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[5]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[6]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[7]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[8]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[9]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[10]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[11]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[12]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[13]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[14]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[15]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[16]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[17]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[18]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[19]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[20]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[21]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[22]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[23]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[24]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[25]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[26]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[27]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[28]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[29]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[30]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[31]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.D2KCreditConfig|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS154|0x5
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS159|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS176|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS177|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS181|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS182|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS180|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS178|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS179|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS167|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS168|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS158|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS164|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS157|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS163|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS151|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS156|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS162|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS152|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS153|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS169|0x8
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS173|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS160|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS161|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS170|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS171|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS172|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS184|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS174|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS155|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS165|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS166|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS175|0x5
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DirectoryModeEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.IoDcMode|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.IrqThreshold|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiAdaptationSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiCrcMode|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiFailoverEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkL0pEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkL1En|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiPrefetchEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiSkuMismatchCheck|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.LLCDeadLineAlloc|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.QpiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.QpiLinkSpeedMode|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.RdCurForXptPrefetchEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.StaleAtoSOptEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TorThresLoctoremEmpty|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TorThresLoctoremNorm|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.MbeBwCal|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TscSyncEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.XptPrefetchEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.XptRemotePrefetchEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdddcErrInjEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADRDataSaveMode|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADREn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondition|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondPause|0x186A0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTrefi|0x3CF0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTwr|0xA
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondVdd|0x4EC
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.allowCorrectableMemTestError|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AttemptFastBootCold|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS99|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS100|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS101|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS104|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS89|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS102|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS103|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS91|0x10
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS88|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS90|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS95|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS96|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS97|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS98|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Blockgnt2cmd1cyc|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CkeIdleTimer|0x14
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CkMode|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmdNormalization|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.cmdSetupPercentOffset|0x32
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmdTxEqCalibration|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmsEnableDramPm|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CustomRefreshRate|0x14
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DataDllOff|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmAveragePowerLimit|0x2EE0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmAveragePowerTimeConstant|0x6
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmEccModeSwitch|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbAveragePowerTimeConstant|0x3A98
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbFeature|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbMaxPowerLimit|0x3A98
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdjcTraining|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrMemoryType|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrtCkeEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS48|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS83|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS122|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS121|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS120|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS136|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS63|0x7
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS62|0xF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS67|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS65|0x7FF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS66|0x40
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS73|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS109|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS78|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS68|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS110|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS57|0x7FF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS56|0x7FF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS61|0x1FF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS51|0x1F
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS52|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS50|0x40
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS60|0x3F
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS58|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS59|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS55|0x7FF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS53|0x7FF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS54|0x7FF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS108|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS70|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS79|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS117|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS118|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS140|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS141|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS142|0x0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS75|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS80|0x4
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[0]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[1]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[2]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[3]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[4]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[5]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[12]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[13]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[14]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[15]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[16]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[17]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[24]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[25]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[26]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[27]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[28]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[29]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[36]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[37]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[38]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[39]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[40]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[41]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS64|0x7FF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS113|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS134|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS69|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS133|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DieSparing|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Disddrtopprd|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplExtendedRange|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplPwrLimitLockCsr|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRonEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DutyCycleTraining|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EccEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EccSupport|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EliminateDirectoryInFarMemory|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS84|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS85|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnforcePopulationPor|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnforcePOR|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.eraseArmNVDIMMS|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EsddcEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FastGoConfig|0x6
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FourxRefreshValue|0x5F
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.HalfxRefreshValue|0x19
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.haltOnMemErr|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.HwMemTest|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.iModeTraining|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LatchSystemShutdownState|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktHi|0x29
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktHour|0x18
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktLo|0x28
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmBacksideVrefEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmRdVrefEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmRxDqCentering|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmTxDqCentering|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmWrVrefEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LsxImplementation|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.McRonEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MdllOffEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.mdllSden|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemCeFloodPolicy|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlows|0xFFFFFFFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt|0xFFFFFFFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt2|0xFFFFFFFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt3|0xFFFFFFFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemHotOuputAssertThreshold|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memInterleaveGran1LM|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemTestLoops|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.multiSparingRanks|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MultiThreaded|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnArsPublish|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnCmdTime|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccCorr|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccExitCorr|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccRdChk|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccWrChk|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NonPreferredWayMask|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.normOppInterval|0x400
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvdimmSmbusMaxAccessTime|0x15E
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvdimmSmbusReleaseDelay|0x96
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmdimmPowerCyclePolicy|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmMediaStatusException|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCmdAll|0x64
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCmdVref|0x64
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCtlAll|0x64
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetRxDq|0x64
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetRxVref|0x64
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetTxDq|0x64
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetTxVref|0x64
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oneRankTimingMode|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oppReadInWmm|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PagePolicy|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrub|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrubAddrMode|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrubDuration|0x18
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pda|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PeriodicRcomp|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PeriodicRcompInterval|0xF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PkgcSrefEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PpdEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pprType|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PreferredReadFirst|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteMrcWarnings|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteWarnings|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PxcTraining|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.readVrefCenter|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.refreshMode|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.restoreNVDIMMS|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RoundTripLatency|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RxCtleTrnEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleEnDDRT|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleSeedHigh|0xD395
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleSeedLow|0xA02B
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.smbSpeed|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.spareErrTh|0x7FFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.spdCrcCheck|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Srat|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1End|0xA
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1Size|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1Start|0x8C
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2End|0xF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2Size|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2Start|0x73
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3End|0xC
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3Size|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3Start|0x70
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4End|0x9
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4Size|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4Start|0x6D
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TempRefreshOption|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.thermalthrottlingsupport|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrefiNumofRank|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOpt|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOptDdrt|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TwoxRefreshValue|0x53
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.txEqCalibration|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Vdd|0x4B0
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.volMemMode|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.wrVrefCenter|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CurrentLimit|0x438
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EngAvgTimeWdw1|0x17
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit1Time|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit2Time|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AcpiS3Enable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AcpiS4Enable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AltEngPerfBIAS|0x7
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AvxIccpLevel|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AvxSupport|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C1AutoDemotion|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C1AutoUnDemotion|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ConfigTdpLock|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgcCriteria|0x2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[0]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[1]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[2]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[3]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableProcHot|0x3
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableThermalMonitor|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableXe|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnhancedPmaxDetector|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.FastRaplDutyCycle|0x40
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.GpssTimer|0x32
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.LTRSwInput|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.MonitorMWait|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NativeAspmEnable|0x2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.OverclockingLock|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0TtlTimeHigh1|0x3A
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0TtlTimeLow1|0x23
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PackageCState|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcodeWdogTimerEn|0x2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLimitClipC|0x1F
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPlimitDifferential|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLimitEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLmtThshld|0xF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[0]|0x20
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[1]|0x20
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[2]|0x20
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[3]|0x20
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[0]|0x10
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[1]|0x10
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[2]|0x10
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[3]|0x10
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxDetector|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit1En|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit2En|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PpcccLock|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorC1eEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorConfigurePbf|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEistEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEPPEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEppProfile|0x55
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorHWPMEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProchotLock|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PwrPerfSwitch|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboMode|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboPowerLimitCsrLock|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[0]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[1]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[2]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[3]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[4]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[5]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[6]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCores[7]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.UncrPerfPlmtOvrdEn|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PrmrrSize|0x80000000
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AesEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.BspSelection|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CheckCpuBist|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreFailover|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DCUIPPrefetcherEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DCUStreamerPrefetcherEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS245|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS241|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS242|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS240|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EpochUpdate|0x2
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.FastStringEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.GlobalPsmiEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.KeySplit|0x7
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.LockChipset|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MachineCheckEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MlcSpatialPrefetcherEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MlcStreamerPrefetcherEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciInTrustControlBit|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PpinControl|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorFlexibleRatio|0x17
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorVmxEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxAutoRegistrationAgent|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLeWr|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxPackageInfoInBandAccess|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxQoS|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SmbusErrorRecovery|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ThreeStrikeTimer|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.TsegSize|0x5
+gStructPcdTokenSpaceGuid.PcdSetup.PcieCorErrThres|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.CpuVccInVoltage|0x167
+gStructPcdTokenSpaceGuid.PcdSetup.SerialBaudRate|0x1C200
+gStructPcdTokenSpaceGuid.PcdSetup.Gen12TimeWindow|0xFFFF
+gStructPcdTokenSpaceGuid.PcdSetup.ReserveStartAddr|0x100000
+gStructPcdTokenSpaceGuid.PcdSetup.BaudRate|0x5
+gStructPcdTokenSpaceGuid.PcdSetup.ExpectedBer|0x7FFFFFFFF
+gStructPcdTokenSpaceGuid.PcdSetup.XmlCliSupport|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.ApplicationProfile|0xFF
+gStructPcdTokenSpaceGuid.PcdSetup.LomDisableByGpio|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[0]|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[1]|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[2]|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[3]|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.XhciWakeOnUsbEnabled|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.SystemErrorEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.RasLogLevel|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PoisonEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.UboxToPcuMcaEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.EmcaEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.EmcaCsmiEn|0x2
+gStructPcdTokenSpaceGuid.PcdSetup.CsmiDynamicDisable|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.EmcaMsmiEn|0x2
+gStructPcdTokenSpaceGuid.PcdSetup.ElogCorrErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.ElogMemErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.ElogProcErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.LmceEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.WheaSupportEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.WheaLogMemoryEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.WheaLogProcEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.WheaLogPciEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.WheaErrInjEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.MemErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.CorrMemErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.SpareIntSelect|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorLowPrioritySignal|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorHighPrioritySignal|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.NgnHostAlertPatrolScrubUNC|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.ReportAlertSPA|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.IioErrorEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.IoMcaEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.IioSev1Pcc|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.IioErrRegistersClearEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.DisableMAerrorLoggingDueToLER|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.EdpcInterrupt|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.EdpcErrCorMsg|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.IioIrpErrorEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.IioMiscErrorEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.IioVtdErrorEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.IioDmaErrorEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.IioDmiErrorEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAddCorrErrorEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAddUnCorrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PsfUrEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PmsbRouterParityErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PcieErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PcieCorrErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PcieUncorrErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PcieFatalErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PcieAerCorrErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PcieAerNfatErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PcieAerFatErrEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PcieAerEcrcEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.McBankWarmBootClearError|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_parityError|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_qtOverflow|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unexprsp|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_csraccunaligned|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unceccCs1|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unceccCs0|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_rcvdpoison|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_crreccCs1|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.irpp0_crreccCs0|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PropagateSerr|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PropagatePerr|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.Use1GPageTable|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.UsbMassResetDelay|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.ConsoleRedirection|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.LegacyOsRedirection|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.DataBits|0x8
+gStructPcdTokenSpaceGuid.PcdSetup.Parity|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.StopBits|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.ARIEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.SRIOVEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.SvidEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.FivrFaultsEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.FivrEfficiencyEnable|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.ReservedS2|0x2
+gStructPcdTokenSpaceGuid.PcdSetup.ReservedS3|0x2
+gStructPcdTokenSpaceGuid.PcdSetup.Gen34TimeWindow|0x2
+gStructPcdTokenSpaceGuid.PcdSetup.Gen34ErrorThreshold|0x10
+gStructPcdTokenSpaceGuid.PcdSetup.Gen34ReEqualization|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.Gen2LinkDegradation|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.Gen3LinkDegradation|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.Gen4LinkDegradation|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.Ce2LmLoggingEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.KtiFirstCeLatchEn|0x1
+gStructPcdTokenSpaceGuid.PcdSetup.PatrolScrubErrorReporting|0x0
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[0]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[2]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[3]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[4]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[5]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[6]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[7]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[8]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[9]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[10]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[11]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[12]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[13]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[14]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[15]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[16]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[17]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[18]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[19]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[0]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[1]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[2]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[3]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[4]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[5]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[6]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[7]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[8]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[9]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[10]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[11]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[12]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[13]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[14]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[15]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[16]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[17]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[18]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[19]|0x3C
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataSnoopLatencyOverrideValue|0x28
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataSnoopLatencyOverrideValue|0x28
+gStructPcdTokenSpaceGuid.PcdPchSetup.AdrMultiplierVal|0x63
+gStructPcdTokenSpaceGuid.PcdPchSetup.AdrTimerVal|0x4
+gStructPcdTokenSpaceGuid.PcdPchSetup.Btcg|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_BmcRootPort|0x5
+gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_IeResetPrepDone|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_MeResetPrepDone|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.DwrEn_PMCGBL|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchBiosLock|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchCrossThrottling|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaLockDown|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaMrom0HookEnable|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaMrom1HookEnable|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchGpioLockDown|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchHdAudio|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieGlobalAspm|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[0]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[1]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[2]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[3]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[4]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[5]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[6]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[7]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[8]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[9]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[10]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[11]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[12]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[13]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[14]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[15]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[16]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[17]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[18]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[19]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[0]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[1]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[2]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[3]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[4]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[5]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[6]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[7]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[8]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[9]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[10]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[11]|0x2
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+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[13]|0x2
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+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[0]|0x2
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+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[3]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[4]|0x2
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+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[6]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[7]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[8]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[9]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[10]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[11]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[12]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[13]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[14]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[15]|0x2
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+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[17]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[18]|0x2
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+gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX16MaxPayloadSize|0x2
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+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[0]|0x1
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+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[2]|0x1
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+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[5]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[6]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[7]|0x1
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+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[19]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFunctionSwapping|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[0]|0x3
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+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[2]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[3]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[4]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[5]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[6]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[7]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[8]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[9]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[10]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[11]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[12]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[13]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[14]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[15]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[16]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[17]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[18]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[19]|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxReadRequestSize|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[0]|0x6
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[1]|0x4
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[2]|0x8
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[3]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[4]|0xA
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[0]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[1]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[2]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[3]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[4]|0x2
+gStructPcdTokenSpaceGuid.PcdPchSetup.PmcReadDisable|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataHddlk|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataLedl|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[0]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[1]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[2]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[3]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[4]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[5]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[6]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[7]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[0]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[1]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[2]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[3]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[4]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[5]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[6]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[7]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidIooe|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidIrrt|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidOub|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR0|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR1|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR10|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR5|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidSrt|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.SataSalp|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHddlk|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataLedl|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[0]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[1]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[2]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[3]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[4]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[5]|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidIooe|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidIrrt|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidOub|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR0|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR1|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR10|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR5|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidSrt|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSalp|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.TestSmbusSpdWriteDisable|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.ThermalDeviceEnable|0x3
+gStructPcdTokenSpaceGuid.PcdPchSetup.Usb3PinsTermination|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.XhciIdleL1|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.XhciOcMapEnabled|0x1
+gStructPcdTokenSpaceGuid.PcdPchSetup.XTpmLen|0x1
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaSetupEnabled|0x3
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH1[0]|0x5A
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH1[1]|0x5A
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH2[0]|0x5D
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH2[1]|0x5D
+
+!if $(MAX_SOCKET) > 4
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[32]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[33]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[34]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[35]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[36]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[37]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[38]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[39]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[40]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[41]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[42]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[43]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[44]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[45]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[46]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[47]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[48]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[49]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[50]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[51]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[52]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[53]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[54]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[55]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[56]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[57]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[58]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[59]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[60]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[61]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[62]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[63]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[25]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[26]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[27]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[28]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[29]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[31]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[32]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[33]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[34]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[35]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[37]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[38]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[39]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[40]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[41]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[43]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[44]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[45]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[46]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[47]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[25]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[26]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[27]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[28]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[29]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[31]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[32]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[33]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[34]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[35]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[37]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[38]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[39]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[40]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[41]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[43]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[44]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[45]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[46]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[47]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[25]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[26]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[27]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[28]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[29]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[31]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[32]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[33]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[34]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[35]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[37]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[38]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[39]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[40]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[41]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[43]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[44]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[45]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[46]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[47]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[25]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[26]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[27]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[28]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[29]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[31]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[32]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[33]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[34]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[35]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[37]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[38]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[39]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[40]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[41]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[43]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[44]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[45]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[46]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[47]|0x19
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[25]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[26]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[27]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[28]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[29]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[31]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[32]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[33]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[34]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[35]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[37]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[38]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[39]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[40]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[41]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[43]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[44]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[45]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[46]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[47]|0x14
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5KtiLinkSpeed|0x3
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5KtiLinkVnaOverride|0x7F
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5ReservedS189|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5ReservedS190|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5ReservedS191|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5ReservedS246|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[48]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[49]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[50]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[51]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[52]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[53]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[60]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[61]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[62]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[63]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[64]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[65]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[72]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[73]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[74]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[75]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[76]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[77]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[84]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[85]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[86]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[87]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[88]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[89]|0xFF
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[4]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[5]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[6]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteriaMcddr[7]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[4]|0x20
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[5]|0x20
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[6]|0x20
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeIio[7]|0x20
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[4]|0x10
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[5]|0x10
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[6]|0x10
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogicalIpTypeMcddr[7]|0x10
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion0[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion1[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion2[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion3[7]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[4]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[5]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[6]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeRegion4[7]|0x1
+!endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
new file mode 100644
index 0000000000..7d0716172e
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
@@ -0,0 +1,111 @@
+# @ build_board.py
+# Extensions for building WilsonCityRvp using build_bios.py
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+"""
+This module serves as a sample implementation of the build extension
+scripts
+"""
+
+import os
+import sys
+
+def pre_build_ex(config, functions):
+ """Additional Pre BIOS build function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: nothing
+ """
+ print("pre_build_ex")
+ config["BUILD_DIR_PATH"] = os.path.join(config["WORKSPACE"],
+ 'Build',
+ config["PLATFORM_BOARD_PACKAGE"],
+ "{}_{}".format(
+ config["TARGET"],
+ config["TOOL_CHAIN_TAG"]))
+ # set BUILD_DIR path
+ config["BUILD_DIR"] = os.path.join('Build',
+ config["PLATFORM_BOARD_PACKAGE"],
+ "{}_{}".format(
+ config["TARGET"],
+ config["TOOL_CHAIN_TAG"]))
+ config["BUILD_X64"] = os.path.join(config["BUILD_DIR_PATH"], 'X64')
+ config["BUILD_IA32"] = os.path.join(config["BUILD_DIR_PATH"], 'IA32')
+
+ if not os.path.isdir(config["BUILD_DIR_PATH"]):
+ try:
+ os.makedirs(config["BUILD_DIR_PATH"])
+ except OSError:
+ print("Error while creating Build folder")
+ sys.exit(1)
+
+ #@todo: Replace this with PcdFspModeSelection
+ if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+ config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=0"
+ else:
+ config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=1"
+ return None
+
+def _merge_files(files, ofile):
+ with open(ofile, 'wb') as of:
+ for x in files:
+ if not os.path.exists(x):
+ return
+
+ with open(x, 'rb') as f:
+ of.write(f.read())
+
+def build_ex(config, functions):
+ """Additional BIOS build function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("build_ex")
+ fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV")
+ binary_fd = os.path.join(fv_path, "BINARY.fd")
+ main_fd = os.path.join(fv_path, "MAIN.fd")
+ secpei_fd = os.path.join(fv_path, "SECPEI.fd")
+ board_fd = config["BOARD"].upper()
+ final_fd = os.path.join(fv_path, "{}.fd".format(board_fd))
+ _merge_files((binary_fd, main_fd, secpei_fd), final_fd)
+ return None
+
+
+def post_build_ex(config, functions):
+ """Additional Post BIOS build function
+
+ :param config: The environment variables to be used in the post
+ build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("post_build_ex")
+ return None
+
+
+def clean_ex(config, functions):
+ """Additional clean function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("clean_ex")
+ return None
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
new file mode 100644
index 0000000000..42bbb852d5
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
@@ -0,0 +1,36 @@
+# @ build_config.cfg
+# This is the WilsonCityRvp board specific build settings
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[CONFIG]
+WORKSPACE_PLATFORM_BIN =
+EDK_SETUP_OPTION =
+openssl_path =
+PLATFORM_BOARD_PACKAGE = WhitleyOpenBoardPkg
+PROJECT = WhitleyOpenBoardPkg/WilsonCityRvp
+BOARD = WilsonCityRvp
+FLASH_MAP_FDF = WhitleyOpenBoardPkg/FspFlashOffsets.fdf
+PROJECT_DSC = WhitleyOpenBoardPkg/PlatformPkg.dsc
+BOARD_PKG_PCD_DSC = WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
+ADDITIONAL_SCRIPTS = WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
+PrepRELEASE = DEBUG
+SILENT_MODE = FALSE
+EXT_CONFIG_CLEAR =
+CapsuleBuild = FALSE
+EXT_BUILD_FLAGS = -D CPUTARGET=ICX -D RP_PKG=WhitleyOpenBoardPkg -D SILICON_PKG=WhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=64 -D MAX_THREAD=2 -D PLATFORM_PKG=MinPlatformPkg
+MAX_SOCKET = 4
+CAPSULE_BUILD = 0
+TARGET = DEBUG
+TARGET_SHORT = D
+PERFORMANCE_BUILD = FALSE
+FSP_WRAPPER_BUILD = TRUE
+FSP_BIN_PKG = WhitleyFspBinPkg
+FSP_PKG_NAME = WhitleyFspPkg
+FSP_BINARY_BUILD = FALSE
+FSP_TEST_RELEASE = FALSE
+SECURE_BOOT_ENABLE = FALSE
+BIOS_INFO_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
--
2.27.0.windows.1
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