[edk2-devel] [edk2-platforms] [PATCH V1 01/18] PurleyRefreshSiliconPkg: Add DEC and DSC files.
Nate DeSimone
nathaniel.l.desimone at intel.com
Tue May 11 09:48:09 UTC 2021
Cc: Chasel Chiu <chasel.chiu at intel.com>
Cc: Mike Kinney <michael.d.kinney at intel.com>
Cc: Isaac Oram <isaac.w.oram at intel.com>
Cc: Mohamed Abbas <mohamed.abbas at intel.com>
Cc: Michael Kubacki <michael.kubacki at microsoft.com>
Cc: Zachary Bobroff <zacharyb at ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad at ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
---
.../Intel/PurleyRefreshSiliconPkg/SiPkg.dec | 390 ++++++++++++++++++
.../SiPkgCommonLib.dsc | 33 ++
.../PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc | 22 +
.../PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc | 12 +
4 files changed, 457 insertions(+)
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgCommonLib.dsc
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec
new file mode 100644
index 0000000000..1ec91ee25a
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec
@@ -0,0 +1,390 @@
+## @file
+# Component description file for the Purley Refresh Silicon Reference Code.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = PurleyRefreshSiliconPkg
+ PACKAGE_GUID = 0BF28B71-A81D-4029-BEC2-A4BE58A0D0D5
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ Include
+ Include/Library
+ Include/Guid
+
+ Library/BaseMemoryCoreLib/Core
+ Library/BaseMemoryCoreLib/Core/Include
+ Library/BaseMemoryCoreLib/Platform/Purley/Include
+
+ Library/BaseMemoryCoreLib/Chip/Skx
+ Library/BaseMemoryCoreLib/Chip/Skx/Include
+ Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio
+ Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol
+ Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup
+
+ Library/ProcMemInit/Chip/Include
+ Override/IA32FamilyCpuPkg
+ Override/IA32FamilyCpuPkg/Include
+
+ Iio/Include
+ Iio/Include/Protocol
+
+ Pch
+ Pch/Include
+ Pch/IncludePrivate
+ Pch/AcpiTables/Dsdt
+
+[LibraryClasses]
+
+ ## @libraryclass Provides services to get the silicon access library.
+ SiliconAccessLib|Include/Library/UsraAccessApi.h
+
+ ## @libraryclass Provides services to convert CSR to PCIE address library.
+ CsrToPcieLib|PurleyRefreshSiliconPkg/Include/Library/CsrToPcieAddress.h
+
+ ## @libraryclass Provides services to PCIE address library.
+ PcieAddrLib|PurleyRefreshSiliconPkg/Include/Library/PcieAddress.h
+
+ ## @libraryclass Provides services to get PCI Express Address Base library.
+ MmPciLib|PurleyRefreshSiliconPkg/Include/Library/MmPciBaseLib.h
+
+ ## @libraryclass Provides services to get the silicon access library.
+ UsraLib|PurleyRefreshSiliconPkg/Include/Protocol/SiliconRegAccess.h
+
+[Guids]
+
+ ## Include/Guid/CpRcPkgTokenSpace.h
+ gEfiCpRcPkgTokenSpaceGuid = { 0xfcdd2efc, 0x6ca8, 0x4d0b, { 0x9d, 0x00, 0x6f, 0x9c, 0xfa, 0x57, 0x8f, 0x98 }}
+ gRcPkgTokenSpaceGuid = { 0x86cf2b1a, 0xb3da, 0x4642, { 0x95, 0xf5, 0xd0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }}
+ gEfiPchTokenSpaceGuid = { 0x89a1b278, 0xa1a1, 0x4df7, { 0xb1, 0x37, 0xde, 0x5a, 0xd7, 0xc4, 0x79, 0x13 }}
+ gEfiCommonPkgTokenSpaceGuid = { 0x86cf2b1a, 0xb3da, 0x4642, { 0x95, 0xf5, 0xd0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }}
+ gEfiPchTokenSpaceGuid = { 0x977c97c1, 0x47e1, 0x4b6b, { 0x96, 0x69, 0x43, 0x66, 0x99, 0xcb, 0xe4, 0x5b }}
+ gCpuUncoreTokenSpaceGuid = { 0x9044434c, 0x40e8, 0x47a1, { 0xa3, 0xba, 0x85, 0x07, 0xf3, 0xc0, 0xe2, 0x56 }}
+ gPlatformTokenSpaceGuid = { 0x07dfa0d2, 0x2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 }}
+
+ #
+ # Uncore
+ #
+ gProcessorProducerGuid = { 0x1bf06aea, 0x5bec, 0x4a8d, { 0x95, 0x76, 0x74, 0x9b, 0x09, 0x56, 0x2d, 0x30 }}
+ gEfiCpuHtCapableGuid = { 0x0d1b9c8e, 0xf77b, 0x4632, { 0x83, 0x43, 0x91, 0xf4, 0x3d, 0x9a, 0x85, 0x60 }}
+ gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }}
+ gEfiMemoryConfigDataHobGuid = { 0x1de25879, 0x6e2a, 0x4d72, { 0xa7, 0x68, 0x28, 0x8c, 0xcb, 0x9f, 0xa7, 0x19 }}
+ gEfiMemorySetupGuid = { 0x3eeff35f, 0x147c, 0x4cd1, { 0xa2, 0x34, 0x92, 0xa0, 0x69, 0x70, 0x0d, 0xb6 }}
+ gEfiMemoryMapGuid = { 0xf8870015, 0x6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f }}
+ gEfiMemoryMapDataHobBdatGuid = { 0x3417b225, 0x916a, 0x49f5, { 0x9a, 0xf5, 0xc9, 0xc7, 0xbf, 0x93, 0x7e, 0xa2 }}
+ gEfiMpstNodeDataGuid = { 0x418bc604, 0xf15e, 0x4843, { 0x85, 0xd0, 0x2d, 0x24, 0x80, 0xb7, 0xe4, 0x88 }}
+ gReadyForLockProtocolGuid = { 0x8d6f1add, 0x45a5, 0x45a8, { 0x8b, 0xb8, 0x0c, 0x3a, 0x95, 0x31, 0x48, 0xfa }}
+
+ gEfiSocketIioVariableGuid = { 0xdd84017e, 0x7f52, 0x48f9, { 0xb1, 0x6e, 0x50, 0xed, 0x9e, 0x0d, 0xbe, 0x27 }}
+ gEfiSocketCommonRcVariableGuid = { 0x4402ca38, 0x808f, 0x4279, { 0xbc, 0xec, 0x5b, 0xaf, 0x8d, 0x59, 0x09, 0x2f }}
+ gEfiSocketMpLinkVariableGuid = { 0x2b9b22de, 0x2ad4, 0x4abc, { 0x95, 0x7d, 0x5f, 0x18, 0xc5, 0x04, 0xa0, 0x5c }}
+ gEfiSocketPciResourceDataGuid = { 0xca3ff937, 0xd646, 0x4936, { 0x90, 0xe8, 0x1b, 0x95, 0x06, 0x49, 0xb3, 0x89 }}
+ gEfiSocketMemoryVariableGuid = { 0x98cf19ed, 0x4109, 0x4681, { 0xb7, 0x9d, 0x91, 0x96, 0x75, 0x7c, 0x78, 0x24 }}
+ gEfiSocketPowermanagementVarGuid = { 0xA1047342, 0xBDBA, 0x4DAE, { 0xA6, 0x7A, 0x40, 0x97, 0x9B, 0x65, 0xC7, 0xF8 }}
+ gEfiSocketProcessorCoreVarGuid = { 0x07013588, 0xC789, 0x4E12, { 0xA7, 0xC3, 0x88, 0xFA, 0xFA, 0xE7, 0x9F, 0x7C }}
+ gSocketPkgListGuid = { 0x5c0083db, 0x3f7d, 0x4b20, { 0xac, 0x9b, 0x73, 0xfc, 0x65, 0x1b, 0x25, 0x03 }}
+ gEfiVolatileMemModeVariableGuid = { 0x0633a0f1, 0x78fe, 0x4139, { 0xb8, 0x78, 0x00, 0x45, 0xe8, 0x1c, 0xb8, 0xab }}
+ gEfiQpiRcParmGuid = { 0x8149fbb8, 0xa2cf, 0x4234, { 0xb5, 0x06, 0xb7, 0x62, 0x55, 0xf7, 0xa3, 0x6d }}
+ gAddressBasedMirrorGuid = { 0x7b9be2e0, 0xe28a, 0x4197, { 0xad, 0x3e, 0x32, 0xf0, 0x62, 0xf9, 0x46, 0x2c }}
+ gClvBootTimeTestExecution = { 0x3ff7d152, 0xef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 }}
+ gEfiRasClvTesterGuid = { 0x9bd36f4f, 0x08dc, 0x4eab, { 0x86, 0x37, 0x2b, 0xc1, 0xbd, 0x5e, 0x0d, 0x95 }}
+ gSocketPkgFpgaGuid = { 0x624b948f, 0x6eba, 0x4dfd, { 0x9d, 0xda, 0x10, 0xb0, 0x07, 0x3a, 0x37, 0x35 }}
+ gIioPolicyHobGuid = { 0xcabb327, 0x11fe, 0x416b, { 0xae, 0x80, 0x2d, 0xe5, 0xdf, 0x60, 0xf7, 0x7d }}
+ gEfiSmmPeiSmramMemoryReserveGuid = { 0x6dadf1d1, 0xd4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d }}
+
+ #
+ # Pch
+ #
+ gSataControllerDriverGuid = { 0xbb929da9, 0x68f7, 0x4035, { 0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 }}
+ gPchInitVariableGuid = { 0xe6c2f70a, 0xb604, 0x4877, { 0x85, 0xba, 0xde, 0xec, 0x89, 0xe1, 0x17, 0xeb }}
+ gPchS3ImageGuid = { 0x271dd6f2, 0x54cb, 0x45e6, { 0x85, 0x85, 0x8c, 0x92, 0x3c, 0x1a, 0xc7, 0x06 }}
+ gEfiSmbusArpMapGuid = { 0x707be83e, 0x0bf6, 0x40a5, { 0xbe, 0x64, 0x34, 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 }}
+ mPchSataRsteProtocolGuid = { 0x3ea94650, 0xfc5b, 0x11e1, { 0xa2, 0x1f, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 }}
+ mPchSataRstProtocolGuid = { 0xfc5f2e00, 0xfc68, 0x11e1, { 0xa2, 0x1f, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 }}
+ gPchInitPeiVariableGuid = { 0xa31b27a4, 0xcae6, 0x48ff, { 0x8c, 0x5a, 0x29, 0x42, 0x21, 0xe6, 0xf3, 0x89 }}
+ gChipsetInitInfoHobGuid = { 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }}
+ gPchOemSmmGuid = { 0xc0cfaf36, 0x4296, 0x40ba, { 0xa9, 0xf1, 0x77, 0x10, 0x9b, 0x91, 0xce, 0x19 }}
+ gPchPowerCycleResetGuid = { 0x8d8ee25b, 0x66dd, 0x4ed8, { 0x8a, 0xbd, 0x14, 0x16, 0xe8, 0x8e, 0x1d, 0x24 }}
+ gPchGlobalResetGuid = { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }}
+ gPchGlobalResetWithEcGuid = { 0xd22e6b72, 0x53cd, 0x4158, { 0x83, 0x3f, 0x6f, 0xd8, 0x7e, 0xbe, 0xa9, 0x93 }}
+#S3 add
+ gPchS3CodeInLockBoxGuid = { 0x1f18c5b3, 0x29ed, 0x4d9e, { 0xa5, 0x04, 0x6d, 0x97, 0x8e, 0x7e, 0xd5, 0x69 }}
+ gPchS3ContextInLockBoxGuid = { 0xe5769ea9, 0xe706, 0x454b, { 0x95, 0x7f, 0xaf, 0xc6, 0xdb, 0x4b, 0x8a, 0x0d }}
+#S3 add
+ gMeBiosExtensionSetupGuid = { 0x1bad711c, 0xd451, 0x4241, { 0xb1, 0xf3, 0x85, 0x37, 0x81, 0x2e, 0x0c, 0x70 }}
+ gAmtForcePushPetPolicyGuid = { 0xacc8e1e4, 0x9f9f, 0x4e40, { 0xa5, 0x7e, 0xf9, 0x9e, 0x52, 0xf3, 0x4c, 0xa5 }}
+ gEfiAcpiVariableGuid = { 0xc020489e, 0x6db2, 0x4ef2, { 0x9a, 0xa5, 0xca, 0x06, 0xfc, 0x11, 0xd3, 0x6a }}
+ gSiPolicyHobGuid = { 0xb3903068, 0x7482, 0x4424, { 0xba, 0x4b, 0x40, 0x5f, 0x8f, 0xd7, 0x65, 0x4e }}
+ gPchPolicyHobGuid = { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0xd9, 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }}
+ gPchDeviceTableHobGuid = { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0x66, 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }}
+ gPchChipsetInitHobGuid = { 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }}
+ gWdtHobGuid = { 0x65675786, 0xacca, 0x4b11, { 0x8a, 0xb7, 0xf8, 0x43, 0xaa, 0x2a, 0x8b, 0xea }}
+ # PCH_SERVER_BIOS_FLAG add
+ gPchPsfErrorHobGuid = { 0x9ee875f4, 0xa463, 0x4b29, { 0x88, 0x79, 0x11, 0x2a, 0x4d, 0x05, 0x47, 0x7f }} #PCH_SERVER_BIOS_FLAG
+
+ #
+ # PreMem Performance
+ #
+ gPerfPchPrePolicyGuid = { 0x3112356F, 0xCC77, 0x4E82, { 0x86, 0xD5, 0x3E, 0x25, 0xEE, 0x81, 0x92, 0xA4 }}
+ gPerfSiValidateGuid = { 0x681F96E6, 0xF9CF, 0x464D, { 0x97, 0x9A, 0xB1, 0x11, 0x33, 0xDE, 0x37, 0xA9 }}
+ gPerfPchValidateGuid = { 0xD0FF37D6, 0xA569, 0x4058, { 0xB3, 0xDA, 0x29, 0x0B, 0x38, 0xC5, 0x32, 0x25 }}
+ gPerfAmtValidateGuid = { 0x9E949422, 0x4A7A, 0x4E41, { 0xB0, 0xAB, 0x3C, 0x0D, 0x88, 0x0A, 0x00, 0xFF }}
+ gPerfCpuValidateGuid = { 0xB760CFCC, 0xDEEF, 0x4C7E, { 0x99, 0x5B, 0xED, 0xFE, 0xF2, 0x23, 0xB2, 0x09 }}
+ gPerfMeValidateGuid = { 0x8CF7A498, 0x588D, 0x4D39, { 0xBD, 0xAC, 0x51, 0x0C, 0x31, 0xAF, 0x45, 0xD0 }}
+ gPerfSaValidateGuid = { 0xA73B382B, 0x62D4, 0x4A19, { 0xBB, 0xF9, 0x09, 0x3E, 0xC5, 0xA5, 0x93, 0x11 }}
+ gPerfHeciPreMemGuid = { 0xD815D922, 0x4994, 0x40B3, { 0x97, 0xCC, 0x07, 0xF3, 0x7D, 0x42, 0xE7, 0x97 }}
+ gPerfPchPreMemGuid = { 0xBB73E2B1, 0xB9FD, 0x4A80, { 0xB8, 0x1A, 0x52, 0x39, 0xE9, 0x4D, 0x06, 0x2E }}
+ gPerfCpuPreMemGuid = { 0xAC5FCBC6, 0x084D, 0x445D, { 0xB3, 0xF3, 0xCA, 0x16, 0xDE, 0xE9, 0xBB, 0x47 }}
+ gPerfMePreMemGuid = { 0x6051338E, 0x0FFA, 0x40F7, { 0xAF, 0xEF, 0xAB, 0x86, 0x7A, 0x38, 0xCC, 0xF3 }}
+ gPerfAmtPreMemGuid = { 0xDB732D50, 0x9BB8, 0x489A, { 0xA1, 0xD1, 0xDD, 0xD2, 0x16, 0x1D, 0x72, 0xB8 }}
+ gPerfSaPreMemGuid = { 0x76F18BDA, 0x2195, 0x4FB6, { 0x9A, 0x94, 0x0E, 0x0B, 0xAC, 0xDE, 0xEC, 0xAB }}
+ gPerfEvlGuid = { 0x8221518B, 0xAC19, 0x4E32, { 0xAB, 0x5F, 0x00, 0x47, 0x0A, 0x50, 0x69, 0x40 }}
+ gPerfMemGuid = { 0x2B57B316, 0x5CF7, 0x4847, { 0xB0, 0x76, 0x6B, 0x5D, 0x23, 0xC3, 0xAA, 0x3E }}
+ gPlatformGpioConfigGuid = { 0xd66acbe3, 0x3293, 0x4ba1, { 0xb0, 0x0b, 0xb3, 0x8f, 0x64, 0x8d, 0x8d, 0x5e }}
+
+[Protocols]
+ ## Include/Protocol/SiliconRegAccess.h
+ gUsraProtocolGuid = { 0xfd480a76, 0xb134, 0x4ef7, { 0xad, 0xfe, 0xb0, 0xe0, 0x54, 0x63, 0x98, 0x07 }}
+
+ #
+ # Uncore
+ #
+ gEfiIioUdsProtocolGuid = { 0xa7ced760, 0xc71c, 0x4e1a, { 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, 0xcb }}
+ gEfiIioSystemProtocolGuid = { 0xddc3080a, 0x2740, 0x4ec2, { 0x9a, 0xa5, 0xa0, 0xad, 0xef, 0xd6, 0xff, 0x9c }}
+ gEfiCpuCsrAccessGuid = { 0x0067835f, 0x9a50, 0x433a, { 0x8c, 0xbb, 0x85, 0x20, 0x78, 0x19, 0x78, 0x14 }}
+ gEfiQuiesceProtocolGuid = { 0x20d6e759, 0x4c4a, 0x40c0, { 0x95, 0x33, 0x2b, 0xf0, 0x06, 0x68, 0x50, 0xfd }}
+ gEfiGlobalNvsAreaProtocolGuid = { 0x074e1e48, 0x8132, 0x47a1, { 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }}
+ gEfiHpIoxAccessGuid = { 0x62652b53, 0x79d9, 0x4cf2, { 0xb5, 0xaa, 0xad, 0x99, 0x81, 0x0a, 0x7f, 0x17 }}
+ gEfiPciCallbackProtocolGuid = { 0x1ca0e202, 0xfe9e, 0x4776, { 0x9f, 0xaa, 0x57, 0x0c, 0x19, 0x61, 0x7a, 0x06 }}
+
+ #
+ # Pch
+ #
+ gEfiSpiProtocolGuid = { 0xf8b84ae6, 0x8465, 0x4f95, { 0x9f, 0x0b, 0xea, 0xaa, 0x37, 0xc6, 0x15, 0x5a }}
+ gEfiActiveBiosProtocolGuid = { 0xebbe2d1b, 0x1647, 0x4bda, { 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a }}
+ gEfiSerialGpioProtocolGuid = { 0xf52c3858, 0x5ef8, 0x4d41, { 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 }}
+ gWdtProtocolGuid = { 0xB42B8D12, 0x2ACB, 0x499a, { 0xA9, 0x20, 0xDD, 0x5B, 0xE6, 0xCF, 0x09, 0xB1 }}
+ gPchPlatformPolicyProtocolGuid = { 0x782ee5ae, 0x586b, 0x47c1, { 0xa4, 0x1d, 0xce, 0x7f, 0xa0, 0x9c, 0x25, 0x9a }}
+ gEfiPchS3SupportProtocolGuid = { 0x2224aee3, 0x8d0b, 0x480a, { 0xb2, 0x72, 0x2a, 0xbe, 0x92, 0xcd, 0x4e, 0x78 }}
+ gEfiPchInfoProtocolGuid = { 0x984eb4e9, 0x5a95, 0x41de, { 0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0 }}
+ gEfiSmmSmbusProtocolGuid = { 0x72e40094, 0x2ee1, 0x497a, { 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c }}
+ gEfiSmmSpiProtocolGuid = { 0xbd75fe35, 0xfdce, 0x49d7, { 0xa9, 0xdd, 0xb2, 0x6f, 0x1f, 0xc6, 0xb4, 0x37 }}
+ gEfiSmmIchnDispatchExProtocolGuid = { 0x3920405b, 0xc897, 0x44da, { 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 }}
+ gEfiSmmIoTrapDispatchProtocolGuid = { 0xdb7f536b, 0xede4, 0x4714, { 0xa5, 0xc8, 0xe3, 0x46, 0xeb, 0xaa, 0x20, 0x1d }}
+ gPchResetCallbackProtocolGuid = { 0x3a3300ab, 0xc929, 0x487d, { 0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0 }}
+ gPchResetProtocolGuid = { 0xdb63592c, 0xb8cc, 0x44c8, { 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a }}
+ gEfiGlobalNvsAreaProtocolGuid = { 0x074e1e48, 0x8132, 0x47a1, { 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }}
+ gPchSmmIoTrapControlGuid = { 0x514D2AFD, 0x2096, 0x4283, { 0x9D, 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 }}
+ gEfiPchSetTmcSrcClkProtocolGuid = { 0xfbaa2549, 0x053d, 0x4012, { 0x86, 0x6c, 0x7a, 0x86, 0xcc, 0x21, 0xae, 0x21 }}
+ gPchPlatformPolicyProtocolGuid = { 0x782ee5ae, 0x586b, 0x47c1, { 0xa4, 0x1d, 0xce, 0x7f, 0xa0, 0x9c, 0x25, 0x9a }}
+ gPchInfoProtocolGuid = { 0x984eb4e9, 0x5a95, 0x41de, { 0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0 }}
+ gPchNvsAreaProtocolGuid = { 0x2E058B2B, 0xEDC1, 0x4431, { 0x87, 0xD9, 0xC6, 0xC4, 0xEA, 0x10, 0x2B, 0xE3 }}
+ gPchSerialIoUartDebugInfoProtocolGuid = { 0x2fd2b1bd, 0x0387, 0x4ec6, { 0x94, 0x1f, 0xf1, 0x4b, 0x7f, 0x1c, 0x94, 0xb6 }}
+ gHeciProtocolGuid = { 0xcfb33810, 0x6e87, 0x4284, { 0xb2, 0x03, 0xa6, 0x6a, 0xbe, 0x07, 0xf6, 0xe8 }}
+ gPchSerialGpioProtocolGuid = { 0xf52c3858, 0x5ef8, 0x4d41, { 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 }}
+ gEfiLoadPeImageProtocolGuid = { 0x5CB5C776, 0x60D5, 0x45EE, { 0x88, 0x3C, 0x45, 0x27, 0x08, 0xCD, 0x74, 0x3F }}
+ gEfiSmmVariableProtocolGuid = { 0xed32d533, 0x99e6, 0x4209, { 0x9c, 0xc0, 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7 }}
+ gDxePchPlatformResetPolicyProtocolGuid = { 0x45ada968, 0xa8c5, 0x4f30, { 0xac, 0xd4, 0xf5, 0x13, 0xbc, 0xe5, 0xb0, 0xb3 }}
+ gDxePchPlatformPolicyProtocolGuid = { 0x4b0165a9, 0x61d6, 0x4e23, { 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 }}
+ gEfiLegacyInterruptProtocolGuid = { 0x31ce593d, 0x108a, 0x485d, { 0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe }}
+ gEfiSmmIchnDispatchProtocolGuid = { 0xc50b323e, 0x9075, 0x4f2a, { 0xac, 0x8e, 0xd2, 0x59, 0x6a, 0x10, 0x85, 0xcc }}
+ gEfiLegacy8259ProtocolGuid = { 0x38321dba, 0x4fe0, 0x4e17, { 0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1 }}
+ gPlatformEmmcInfoProtocolGuid = { 0xf103dd83, 0x3b17, 0x4e1e, { 0x9b, 0x80, 0x5d, 0xcc, 0x9c, 0x59, 0x0b, 0x2f }}
+ gPchEmmcTuningProtocolGuid = { 0x10fe7e3b, 0xdbe5, 0x4cfa, { 0x90, 0x25, 0x40, 0x02, 0xcf, 0xdd, 0xbb, 0x89 }}
+ gPchTcoSmiDispatchProtocolGuid = { 0x9E71D609, 0x6D24, 0x47FD, { 0xB5, 0x72, 0x61, 0x40, 0xF8, 0xD9, 0xC2, 0xA4 }}
+ gPchPcieSmiDispatchProtocolGuid = { 0x3E7D2B56, 0x3F47, 0x42AA, { 0x8F, 0x6B, 0x22, 0xF5, 0x19, 0x81, 0x8D, 0xAB }}
+ gPchAcpiSmiDispatchProtocolGuid = { 0xD52BB262, 0xF022, 0x49EC, { 0x86, 0xD2, 0x7A, 0x29, 0x3A, 0x7A, 0x05, 0x4B }}
+ gPchGpioUnlockSmiDispatchProtocolGuid = { 0x83339EF7, 0x9392, 0x4716, { 0x8D, 0x3A, 0xD1, 0xFC, 0x67, 0xCD, 0x55, 0xDB }}
+ gPchSmiDispatchProtocolGuid = { 0x4566C59F, 0x650B, 0x4B63, { 0xB1, 0xEF, 0x4F, 0x36, 0x66, 0x54, 0x4B, 0xEF }}
+ gEfiSmmIchnDispatch2ProtocolGuid = { 0xe0f0cc19, 0x8912, 0x4077, { 0xbf, 0x8a, 0x6a, 0x5c, 0x27, 0x0a, 0x3e, 0x65 }}
+ gEfiSmmIchnDispatch2ExProtocolGuid = { 0x8497455b, 0xb489, 0x4ac7, { 0xbd, 0x51, 0x78, 0xdf, 0x4e, 0x1f, 0x1a, 0xcd }}
+ gPchEspiSmiDispatchProtocolGuid = { 0xca236c1b, 0x625c, 0x4753, { 0xb5, 0x53, 0x19, 0x05, 0xfc, 0xec, 0x2e, 0xa7 }}
+ gPchPcieIoTrapProtocolGuid = { 0xd66a1cf, 0x79ad, 0x494b, { 0x97, 0x8b, 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 }}
+ gPchSataEfiLoadProtocolGuid = { 0xaee24780, 0x4511, 0x4f23, { 0xa0, 0x28, 0xeb, 0x82, 0x04, 0xd4, 0x82, 0x9c }}
+ gPchsSataEfiLoadProtocolGuid = { 0x8580afee, 0x40ad, 0x4f63, { 0xa5, 0x48, 0x3d, 0x7f, 0x4a, 0x09, 0x86, 0x7d }}
+ gPchSmmPeriodicTimerControlGuid = { 0x6906E93B, 0x603B, 0x4A0F, { 0x86, 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB }}
+
+[Ppis]
+ ## Include/Protocol/SiliconRegAccess.h
+ gUsraPpiGuid = { 0x90766a99, 0x9ca5, 0x44de, { 0x94, 0xda, 0xdc, 0xc1, 0xd2, 0xd6, 0xda, 0x1f }}
+
+ #
+ # Uncore
+ #
+ gPeiBaseMemoryTestPpiGuid = { 0xb6ec423c, 0x21d2, 0x490d, { 0x85, 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74 }}
+ gPeiPlatformMemorySizePpiGuid = { 0x9a7ef41e, 0xc140, 0x4bd1, { 0xb8, 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6 }}
+ gPeiMpServicePpiGuid = { 0xee16160a, 0xe8be, 0x47a6, { 0x82, 0x0a, 0xc6, 0x90, 0x0d, 0xb0, 0x25, 0x0a }}
+
+ #
+ # Pch
+ #
+ gPchPmcXramOffsetDataPpiGuid = { 0xc1392859, 0x1f65, 0x446e, { 0xa3, 0xf6, 0x85, 0x36, 0xfc, 0xc7, 0xd1, 0xc4 }}
+ gPchPlatformPolicyPpiGuid = { 0xdfe2b897, 0x0e8e, 0x4926, { 0xbc, 0x69, 0xe5, 0xed, 0xd3, 0xf9, 0x38, 0xe1 }}
+ gPchInitPreMemDonePpiGuid = { 0xb795d447, 0x7524, 0x4819, { 0xa6, 0x2c, 0xff, 0x6f, 0x46, 0x71, 0xf2, 0xff }}
+ gPeiUsbControllerPpiGuid = { 0x3BC1F6DE, 0x693E, 0x4547, { 0xA3, 0x00, 0x21, 0x82, 0x3C, 0xA4, 0x20, 0xB2 }}
+ gPchUsbPolicyPpiGuid = { 0xc02b0573, 0x2b4e, 0x4a31, { 0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c }}
+ gPchInitPpiGuid = { 0x908c7f8b, 0x5c48, 0x47fb, { 0x83, 0x57, 0xf5, 0xfd, 0x4e, 0x23, 0x52, 0x76 }}
+ gWdtPpiGuid = { 0xF38D1338, 0xAF7A, 0x4FB6, { 0x91, 0xDB, 0x1A, 0x9C, 0x21, 0x83, 0x57, 0x0D }}
+ gPeiSpiPpiGuid = { 0xfbf26154, 0x4e55, 0x4bdc, { 0xaf, 0x7b, 0xd9, 0x18, 0xac, 0x44, 0x3f, 0x61 }}
+ gPchDmiTcVcMapPpiGuid = { 0xed097352, 0x9041, 0x445a, { 0x80, 0xb6, 0xb2, 0x9d, 0x50, 0x9e, 0x88, 0x45 }}
+ gPeiSmbusPolicyPpiGuid = { 0x63b6e435, 0x32bc, 0x49c6, { 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c }}
+ gPchResetCallbackPpiGuid = { 0x17865dc0, 0x0b8b, 0x4da8, { 0x8b, 0x42, 0x7c, 0x46, 0xb8, 0x5c, 0xca, 0x4d }}
+ gPchPeiInitDonePpiGuid = { 0x1edcbdf9, 0xffc6, 0x4bd4, { 0x94, 0xf6, 0x19, 0x5d, 0x1d, 0xe1, 0x70, 0x56 }}
+ gPchResetPpiGuid = { 0x433e0f9f, 0x05ae, 0x410a, { 0xa0, 0xc3, 0xbf, 0x29, 0x8e, 0xcb, 0x25, 0xac }}
+ gPchHdaVerbTablePpiGuid = { 0x220307a4, 0x3670, 0x42a5, { 0xaa, 0x01, 0x32, 0x9d, 0xcd, 0x3e, 0x91, 0x6b }}
+ gPchPcieDeviceTablePpiGuid = { 0xaf4a1998, 0x4949, 0x4545, { 0x9c, 0x4c, 0xc1, 0xe7, 0xc0, 0x42, 0xe0, 0x56 }}
+ gPchSmmIoTrapControlGuid = { 0x514D2AFD, 0x2096, 0x4283, { 0x9D, 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 }}
+ gSaPlatformPolicyPpiGuid = { 0x573eaf99, 0xf445, 0x46b5, { 0xa5, 0xd5, 0xbc, 0x4a, 0x93, 0x35, 0x98, 0xf3 }}
+ gPeiSmmControlPpiGuid = { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d, 0xef, 0xa7, 0x43, 0x05, 0xce, 0x74, 0xc5 }}
+ gPchHsioPtssTablePpiGuid = { 0x220307a4, 0x3671, 0x42b5, { 0xaa, 0x02, 0x32, 0x9d, 0xcd, 0x3e, 0x91, 0x6b }}
+ gDirtyWarmResetSignalGuid = { 0x24b9a592, 0x4cfc, 0x4c8f, { 0x86, 0xf4, 0x87, 0x28, 0x2d, 0x7f, 0x9e, 0x9c }}
+ gDirtyWarmResetGuid = { 0xe60fe263, 0xac2b, 0x43d6, { 0xb3, 0xc7, 0x0d, 0x9d, 0xdc, 0x5a, 0x99, 0x1c }}
+
+[PcdsFeatureFlag]
+ ## Indicate whether USRA can support S3
+ gEfiCpRcPkgTokenSpaceGuid.PcdUsraSupportS3|TRUE|BOOLEAN|0x00000012
+
+ ## Use this feature PCD to support Single PCIe segment with static MMCFG Base
+ gEfiCpRcPkgTokenSpaceGuid.PcdSingleSegFixMmcfg|TRUE|BOOLEAN|0x00000014
+
+ ## enable/disable USRA trace.
+ gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceEnable|FALSE|BOOLEAN|0x00000016
+
+ ## enable/disable Quiesce feature.
+ gEfiCpRcPkgTokenSpaceGuid.PcdQuiesceSupport|TRUE|BOOLEAN|0x00000017
+
+ gEfiCpuTokenSpaceGuid.PcdCpuIvyBridgeFamilyFlag|TRUE|BOOLEAN|0x10000031
+ gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|TRUE|BOOLEAN|0x10000001
+
+ ## This PCD specifies whether StatusCode is reported via USB Serial port.
+ gEfiCpuTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE|BOOLEAN|0x1000000F
+
+[PcdsFixedAtBuild]
+ ## Indicates the size of each PCIE segment
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize|0x10000000|UINT64|0x00000010
+ gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg|0x00000008|UINT32|0x00000013
+ ## Indicates the max nested level
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000008|UINT32|0x00000018
+ ## Maximum number of sockets supported for this firmware build.
+ # This PCD should be used sparingly. Dynamic allocation of data and
+ # dynamic control flows are preferred over using this PCD for static
+ # data allocation and control.
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|0x04|UINT32|0x00000019
+
+ gPlatformTokenSpaceGuid.PcdBusStack|0x06|UINT8|0x30000006
+ gPlatformTokenSpaceGuid.PcdUboDev|0x08|UINT8|0x3000000D
+ gPlatformTokenSpaceGuid.PcdUboFunc|0x02|UINT8|0x3000000E
+ gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC|UINT8|0x3000000F
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0x00FFD00000|UINT32|0x2000000D
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x0000300000|UINT32|0x2000000E
+ gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|0xFFFB0000|UINT32|0x30000004
+ gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize|0x00010000|UINT32|0x30000005
+ gCpuUncoreTokenSpaceGuid.PcdWaSlowModeEnable|0|BOOLEAN|0x30000008
+
+ gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress|0x500|UINT16|0x30000003
+ gEfiPchTokenSpaceGuid.PcdSmmActivationData|0x55|UINT8|0x30000005
+ gEfiPchTokenSpaceGuid.PcdSmmActivationPort|0xb2|UINT16|0x30000001
+ gEfiPchTokenSpaceGuid.PcdSmmDataPort|0xb3|UINT16|0x30000002
+ gEfiCommonPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30001033
+
+ ## From MdeModulePkg.dec
+ ## Progress Code for S3 Suspend end.
+ # PROGRESS_CODE_S3_SUSPEND_END = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000001)) = 0x03078001
+ gEfiPchTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30001033
+
+ ## TraceHub Configuration
+ ## PcdTraceHubEnMode: 0 for Disabled, 1 for Internal Debugger, 2 for Host Debugger
+
+ ## TraceHub temporary disabled, until TraceHubInitialize is not working correctly. Sighting 4929727.
+ gEfiPchTokenSpaceGuid.PcdTraceHubEnMode|0x00|UINT8|0x30003001
+
+ ## PcdTraceHubEnFWTrace: 0 for Disabled, 1 for Enabled
+ gEfiPchTokenSpaceGuid.PcdTraceHubEnFwTrace|0x01|UINT8|0x30003002
+ ## PcdTraceHubDest: 0 for Mem, 1 for PTI, 2 for USB3, 3 for BSSB
+ gEfiPchTokenSpaceGuid.PcdTraceHubDest|0x02|UINT8|0x30003003
+ ## PcdTraceHubTempCsrMtbBar: Temporary CSR MTB BAR
+ gEfiPchTokenSpaceGuid.PcdTraceHubTempCsrMtbBar|0xFE100000|UINT32|0x30003004
+
+ gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x10000001
+ gEfiPchTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x10000002
+
+[PcdsFixedAtBuild,PcdsPatchableInModule]
+ ## From MdeModulePkg.dec
+ ## Default OEM ID for ACPI table creation, its length must be 0x6 bytes to follow ACPI specification.
+ gEfiPchTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034
+ ## Default OEM Table ID for ACPI table creation, it is "EDK2 ".
+ gEfiPchTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64|0x30001035
+ ## Default OEM Revision for ACPI table creation.
+ gEfiPchTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0x30001036
+ ## Default Creator ID for ACPI table creation.
+ gEfiPchTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30001037
+ ## Default Creator Revision for ACPI table creation.
+ gEfiPchTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x30001038
+ gEfiPchTokenSpaceGuid.PcdSmbusBaseAddress|0x0780|UINT16|0x00010031
+ gEfiPchTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034
+
+ ##
+ ## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection
+ ## value of the struct
+ ## 0x00 EfiGcdAllocateAnySearchBottomUp
+ ## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp
+ ## 0x03 EfiGcdAllocateAnySearchTopDown
+ ## 0x04 EfiGcdAllocateMaxAddressSearchTopDown
+ ##
+ ## below value should not using in this situation
+ ## 0x05 EfiGcdMaxAllocateType : design for max value of struct
+ ## 0x02 EfiGcdAllocateAddress : design for speccification address allocate
+ ##
+ gEfiPchTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000
+
+[PcdsDynamicEx]
+ ## | MMCFG Table Header | Segment 0 | Segment 1 | Segment 2 | Segment 3 | Segment 4 | Segment 5 | Segment 6 | Segment 7 |
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}|VOID*|0x00000011
+ gEfiCpRcPkgTokenSpaceGuid.PcdRcRevision|0|UINT32|0x00000015
+
+ gPlatformTokenSpaceGuid.PcdFpgaSwSmiInputValue|0|UINT8|0x30000007
+ gEfiCpuTokenSpaceGuid.PcdSbspSelection|0xFF|UINT8|0x6000801B
+ gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue|0x0|UINT8|0x60008009
+ gEfiCpuTokenSpaceGuid.PcdCpuTurboOverride|0x0|UINT32|0x60008022
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorMsrLockCtrl|0x0|UINT8|0x60008018
+ gEfiCpuTokenSpaceGuid.PcdCpuIioLlcWaysBitMask|0x0|UINT64|0x60008019
+ gEfiCpuTokenSpaceGuid.PcdCpuExpandedIioLlcWaysBitMask|0x0|UINT64|0x6000801C
+ gEfiCpuTokenSpaceGuid.PcdCpuRemoteWaysBitMask|0x0|UINT64|0x60008023
+ gEfiCpuTokenSpaceGuid.PcdPchTraceHubEn|0x0|UINT8|0x6000801D
+ gEfiCpuTokenSpaceGuid.PcdCpuQlruCfgBitMask|0x0|UINT64|0x6000801A
+ gEfiCpuTokenSpaceGuid.PcdCpuPmStructAddr|0x0|UINT64|0x60008020
+ gEfiCpuTokenSpaceGuid.PcdCpuRRQCountThreshold|0x0|UINT64|0x60008024
+ gPlatformTokenSpaceGuid.PcdPlatformType|0x00000000|UINT8|0x30000041
+ ## PCD for ServerCommonPkg\Override\IA32FamilyCpuPkg\CpuMpDxe.inf
+ ## This PCD is the AP state on POST. The value is defined as below.
+ # 1: ApInHltLoop, AP is in the Hlt-Loop state.
+ # 2: ApInMwaitLoop, AP is in the Mwait-Loop state.
+ # 3: ApInRunLoop, AP is in the Run-Loop state.
+ gEfiCpuTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x10001004
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+ gEfiPchTokenSpaceGuid.PcdWakeOnRTCS5|FALSE|BOOLEAN|0x30000018
+ gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeHour|0|UINT8|0x30000019
+ gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeMinute|0|UINT8|0x30000020
+ gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeSecond|0|UINT8|0x30000021
+ gEfiPchTokenSpaceGuid.PcdPchSataInitReg78Data|0x88880000|UINT32|0x30000007
+ gEfiPchTokenSpaceGuid.PcdPchSataInitReg88Data|0x88338822|UINT32|0x30000009
+
+ ##
+ ## SerialIo Uart Configuration
+ ##
+ gEfiPchTokenSpaceGuid.PcdSerialIoUartDebugEnable|FALSE|BOOLEAN|0x00100001
+ gEfiPchTokenSpaceGuid.PcdSerialIoUartNumber|2|UINT8|0x00100002
+
+ #
+ # PcdFviSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS,
+ # values 0-0x7F will be treated as disable FVI reporting.
+ # FVI structure uses it as SMBIOS OEM type to provide version information.
+ #
+ gEfiPchTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x00010037
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgCommonLib.dsc b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgCommonLib.dsc
new file mode 100644
index 0000000000..1ba7285f79
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgCommonLib.dsc
@@ -0,0 +1,33 @@
+## @file
+# Build description file for Purley Refresh silicon PEI and DXE libraries.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[LibraryClasses.common]
+
+ #
+ # Uncore
+ #
+ PcieAddrLib|$(PLATFORM_SI_PACKAGE)/Library/PcieAddressLib/PcieAddressLib.inf
+ SiliconAccessLib|$(PLATFORM_SI_PACKAGE)/Library/UsraAccessLib/UsraAccessLib.inf
+ CsrToPcieLib|$(PLATFORM_SI_PACKAGE)/Library/CsrToPcieLibNull/BaseCsrToPcieLibNull.inf
+ PcieAddrLib|$(PLATFORM_SI_PACKAGE)/Library/PcieAddressLib/PcieAddressLib.inf
+ MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/MmPciBaseLib/MmPciBaseLib.inf
+
+ #
+ # Pch
+ #
+ GpioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
+ PchPolicyLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
+ PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf
+ PchGbeLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchGbeLib/PeiDxeSmmPchGbeLib.inf
+ PchInfoLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLib.inf
+ PchP2sbLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchP2sbLib/PeiDxeSmmPchP2sbLib.inf
+ PchPcrLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
+ PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
+ PchResetCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/LibraryPrivate/BasePchResetCommonLib/BasePchResetCommonLib.inf
+ PchPmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc
new file mode 100644
index 0000000000..be40e45d69
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc
@@ -0,0 +1,22 @@
+## @file
+# Build description file for Purley Refresh silicon DXE libraries.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[LibraryClasses.common.DXE_DRIVER]
+ MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.inf
+ ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
+
+[LibraryClasses.common.DXE_SMM_DRIVER]
+ MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.inf
+ CsrToPcieLib|$(PLATFORM_SI_PACKAGE)/Library/CsrToPcieLib/CsrToPcieDxeLib.inf
+ SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
+
+[LibraryClasses.X64.UEFI_APPLICATION]
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc
new file mode 100644
index 0000000000..98c83dc097
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc
@@ -0,0 +1,12 @@
+## @file
+# Build description file for Purley Refresh silicon PEI libraries.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[LibraryClasses.common.PEIM]
+ CsrToPcieLib|$(PLATFORM_SI_PACKAGE)/Library/CsrToPcieLib/CsrToPciePeiLib.inf
+ PcieAddrLib|$(PLATFORM_SI_PACKAGE)/Library/PcieAddressLib/PcieAddressLib.inf
--
2.27.0.windows.1
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