[edk2-devel] [edk2-platforms] [PATCH V1 12/18] PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add ASL files
Nate DeSimone
nathaniel.l.desimone at intel.com
Tue May 11 09:48:20 UTC 2021
Cc: Chasel Chiu <chasel.chiu at intel.com>
Cc: Mike Kinney <michael.d.kinney at intel.com>
Cc: Isaac Oram <isaac.w.oram at intel.com>
Cc: Mohamed Abbas <mohamed.abbas at intel.com>
Cc: Michael Kubacki <michael.kubacki at microsoft.com>
Cc: Zachary Bobroff <zacharyb at ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad at ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
---
.../Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl | 19 +
.../Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi | 227 +++++
.../Acpi/BoardAcpiDxe/Dsdt/DSDT.asl | 77 ++
.../Acpi/BoardAcpiDxe/Dsdt/Gpe.asl | 134 +++
.../Acpi/BoardAcpiDxe/Dsdt/HostBus.asl | 256 ++++++
.../Dsdt/IioPcieHotPlugGpeHandler.asl | 842 ++++++++++++++++++
.../Dsdt/IioPcieRootPortHotPlug.asl | 686 ++++++++++++++
.../Acpi/BoardAcpiDxe/Dsdt/Itss.asl | 32 +
.../Acpi/BoardAcpiDxe/Dsdt/Mother.asi | 202 +++++
.../Acpi/BoardAcpiDxe/Dsdt/Os.asi | 145 +++
.../Acpi/BoardAcpiDxe/Dsdt/Pch.asi | 10 +
.../Acpi/BoardAcpiDxe/Dsdt/PchApic.asi | 17 +
.../Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi | 91 ++
.../Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi | 92 ++
.../Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl | 17 +
.../Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi | 22 +
.../Acpi/BoardAcpiDxe/Dsdt/PchSata.asi | 807 +++++++++++++++++
.../Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi | 329 +++++++
.../Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi | 312 +++++++
.../Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi | 455 ++++++++++
.../Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi | 644 ++++++++++++++
.../Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi | 14 +
.../Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi | 16 +
.../Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi | 355 ++++++++
.../Acpi/BoardAcpiDxe/Dsdt/Platform.asl | 79 ++
.../Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi | 78 ++
.../Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi | 9 +
.../Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi | 9 +
.../Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi | 9 +
.../Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi | 33 +
.../Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi | 175 ++++
.../Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi | 125 +++
.../Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi | 98 ++
.../Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl | 189 ++++
34 files changed, 6605 insertions(+)
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
new file mode 100644
index 0000000000..b76b062a94
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
@@ -0,0 +1,19 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+///////////////////////////////////////////////////////////////////////////////////
+//Values are set like this to have ASL compiler reserve enough space for objects
+///////////////////////////////////////////////////////////////////////////////////
+//
+// Available Sleep states
+//
+Name(SS1,0)
+Name(SS2,0)
+Name(SS3,1)
+Name(SS4,1)
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi
new file mode 100644
index 0000000000..f5317cff86
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi
@@ -0,0 +1,227 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "MaxSocket.h"
+
+ //
+ // External declarations
+ // HECI-1/HECI-2 are in PurleyPlatPkg\Me\Sps\Acpi\SpsNm.asl
+ //
+ External(\_SB.PC00.HEC2.HPTS, MethodObj)
+ External(\_SB.PC00.HEC2.HWAK, MethodObj)
+
+ //
+ // System Sleep States
+ //
+ Name (\_S0,Package (){0,0,0,0})
+ Name (\_S3,Package (){5,0,0,0}) // Name changed to \DS3 if disabled in Setup
+ Name (\_S4,Package (){6,0,0,0}) // Name changed to \DS4 if disabled in Setup
+ Name (\_S5,Package (){7,0,0,0})
+
+ //
+ // Native OS hot plug support, 0->ACPI, 1->OS
+ //
+ Name (\OSHF, 0)
+
+ //
+ // OS flag
+ //
+ #include "Os.asi"
+
+ //
+ // for determing PIC mode
+ //
+ Name (\PICM,Zero)
+ Method (\_PIC, 1, NotSerialized) {
+ Store(Arg0,\PICM)
+ }
+
+ OperationRegion (DBG0, SystemIO, 0x80, 2)
+ Field (DBG0, ByteAcc,NoLock,Preserve) {
+ IO80, 8,
+ IO81, 8
+ }
+
+ //
+ // Access CMOS range
+ //
+ OperationRegion (ACMS, SystemIO, 0x72, 2)
+ Field ( ACMS, ByteAcc, NoLock, Preserve) {
+ INDX, 8,
+ DATA, 8
+ }
+
+ //
+ // SWGPE_CTRL
+ //
+ OperationRegion (GPCT, SystemIO, 0x442, 1)
+ Field ( GPCT, ByteAcc, NoLock, Preserve) {
+ , 1,
+ SGPC , 1,
+ }
+
+ //
+ // GPI_INV
+ //
+ OperationRegion (GPIV, SystemIO, 0x52c, 2)
+ Field ( GPIV, ByteAcc, NoLock, Preserve) {
+ GP0I , 1,
+ }
+
+#include "Acpi/GlobalNvs.asi"
+
+ //
+ // Operation region for GPI status bits
+ //
+ OperationRegion (GSTS, SystemIO, 0x422, 2)
+ Field ( GSTS, ByteAcc, NoLock, Preserve) {
+ GP00 , 1,
+ , 12,
+ GP13 , 1,
+ }
+
+ //
+ // GPE0 HOT_PLUG_EN
+ //
+ OperationRegion (GPE0, SystemIO, 0x428, 8)
+ Field (GPE0, ByteAcc,NoLock,Preserve) {
+ ,1,
+ GPEH,1,
+ ,1,
+ USB1,1,
+ USB2,1,
+ USB5,1,
+ ,3,
+ PCIE,1,
+ ,1,
+ PMEE,1,
+ USB3,1,
+ PMB0,1,
+ USB4,1,
+ ,9,
+ ,1,
+ ,7,
+ USB6,1,
+ ,15,
+ }
+
+ //
+ // GPES Status
+ //
+ OperationRegion (GPES, SystemIO, 0x420, 8)
+ Field (GPES, ByteAcc,NoLock,Preserve) {
+ ,1,
+ GPSH,1,
+ SGPS,1,
+ US1S,1,
+ US2S,1,
+ US5S,1,
+ ,1,
+ SMWS,1,
+ ,1,
+ PEES,1,
+ ,1,
+ PMES,1,
+
+ US3S ,1,
+ PMBS,1,
+ US4S ,1,
+ ,9,
+ ,1,
+ ,7,
+ US6S,1,
+ ,15,
+ }
+
+ //
+ // System sleep down
+ //
+ Method (_PTS, 1, NotSerialized)
+ {
+ Store (0x72, IO80) // Sync with EfiPostCode.h
+
+ //
+ // Clear wake event status.
+ //
+ Store(1,US1S)
+ Store(1,US2S)
+ Store(1,US5S)
+ Store(1,SMWS)
+ Store(1,PMES)
+ Store(1,US3S)
+ Store(1,PMBS)
+ Store(1,US4S)
+ Store(1,US6S)
+
+ //
+ // Enable SCI and wake event sources.
+ //
+ Store(1,GPEH)
+ Store(1,USB1)
+ Store(1,USB2)
+ Store(1,USB5)
+ Store(1,PCIE)
+ Store(1,PMEE)
+ Store(1,USB3)
+ Store(1,PMB0)
+ Store(1,USB4)
+ Store(1,USB6)
+
+ //
+ // If HECI-2 exist call its prepare-to-sleep handler.
+ // The handler checks whether HECI-2 is enabled.
+ //
+ If (CondRefOf(\_SB.PC00.HEC2.HPTS))
+ {
+ \_SB.PC00.HEC2.HPTS()
+ }
+
+ /// WA for S3 on XHCI
+ \_SB.PC00.XHCI.XHCS()
+ }
+
+ //#include "Uncore.asi"
+
+ //
+ // System Wake up
+ //
+ Method (_WAK, 1, Serialized)
+ {
+ Store (0x73, IO80) // Sync with EfiPostCode.h
+
+ //
+ // If HECI-2 exist call its wake-up handler.
+ // The handler checks whether HECI-2 is enabled.
+ //
+ If (CondRefOf(\_SB.PC00.HEC2.HWAK))
+ {
+ \_SB.PC00.HEC2.HWAK()
+ }
+
+ //
+ // If waking from S3
+ //
+ If (LEqual(Arg0, 3)) {
+ }
+
+ Return(Package(){0, 0})
+ }
+
+ Scope(\_SB) {
+
+ // Information on CPU and Memory for hotplug SKUs
+ // #include "CpuMemHp.asi"
+
+ OperationRegion (IOB2, SystemIO, 0xB2, 2) //MKF_SMIPORT
+ Field (IOB2, ByteAcc, NoLock, Preserve) {
+ SMIC, 8, // SW-SMI ctrl port
+ SMIS, 8, // SW-SMI status port
+ }
+
+ } // end _SB scope
+
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl
new file mode 100644
index 0000000000..55b4c11741
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl
@@ -0,0 +1,77 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+// Comment out includes as ifdefs don't work at trim stage
+
+//
+//
+
+Scope(\_SB) {
+ //
+ //---------------------------------------------------------------------------
+ // List of IRQ resource buffers compatible with _PRS return format.
+ //---------------------------------------------------------------------------
+ // Naming legend:
+ // RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.
+ // Note. PRSy name is generated if IRQ Link name starts from "LNK".
+ // HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.
+ //---------------------------------------------------------------------------
+ Name(PRSA, ResourceTemplate(){ // Link name: LNKA
+ IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}
+ })
+ Alias(PRSA,PRSB) // Link name: LNKB
+ Alias(PRSA,PRSC) // Link name: LNKC
+ Alias(PRSA,PRSD) // Link name: LNKD
+ Alias(PRSA,PRSE) // Link name: LNKE
+ Alias(PRSA,PRSF) // Link name: LNKF
+ Alias(PRSA,PRSG) // Link name: LNKG
+ Alias(PRSA,PRSH) // Link name: LNKH
+}
+
+//
+//
+
+ Scope(\_SB.PC00) {
+ //
+ // PCI-specific method's GUID
+ //
+ Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))
+ //
+ // PCI's _DSM - an attempt at modular _DSM implementation
+ // When writing your own _DSM function that needs to include PCI-specific methods, do this:
+ //
+ // Method(_YOUR_DSM,4){
+ // if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
+ // ...continue your _DSM by checking different GUIDs...
+ // else { return(0) }
+ // }
+ //
+ Method(PCID, 4, Serialized) {
+ If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID
+ If(LGreaterEqual(Arg1,3)) { // revision at least 3
+ If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } // function 0: list of supported functions
+ If(LEqual(Arg2,8)) { Return (1) } // function 8: Avoiding Power-On Reset Delay Duplication on Sx Resume
+ If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,Ones}) } // function 9: Specifying Device Readiness Durations
+ }
+ }
+ return (Buffer(1){0})
+ }
+ }//scope
+Scope(\_SB.PC00) {
+ //PciCheck, Arg0=UUID, returns true if support for 'PCI delays optimization ECR' is enabled and the UUID is correct
+ Method(PCIC,1,Serialized) {
+ If(LEqual(ECR1,1)) {
+ If(LEqual(Arg0, PCIG)) {
+ return (1)
+ }
+ }
+ return (0)
+ }
+}
+
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
new file mode 100644
index 0000000000..97a3ba0eb3
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
@@ -0,0 +1,134 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ // General Purpose Events. This Scope handles the Run-time and
+ // Wake-time SCIs. The specific method called will be determined by
+ // the _Lxx value, where xx equals the bit location in the General
+ // Purpose Event register(s).
+
+ //
+ // If the Root Port is enabled, run PCI_EXP_STS handler
+ //
+ If(LNotEqual(\_SB.PC00.RP01.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP01.HPME()
+ Notify(\_SB.PC00.RP01, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP02.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP02.HPME()
+ Notify(\_SB.PC00.RP02, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP03.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP03.HPME()
+ Notify(\_SB.PC00.RP03, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP04.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP04.HPME()
+ Notify(\_SB.PC00.RP04, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP05.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP05.HPME()
+ Notify(\_SB.PC00.RP05, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP06.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP06.HPME()
+ Notify(\_SB.PC00.RP06, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP07.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP07.HPME()
+ Notify(\_SB.PC00.RP07, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP08.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP08.HPME()
+ Notify(\_SB.PC00.RP08, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP09.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP09.HPME()
+ Notify(\_SB.PC00.RP09, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP10.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP10.HPME()
+ Notify(\_SB.PC00.RP10, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP11.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP11.HPME()
+ Notify(\_SB.PC00.RP11, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP12.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP12.HPME()
+ Notify(\_SB.PC00.RP12, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP13.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP13.HPME()
+ Notify(\_SB.PC00.RP13, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP14.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP14.HPME()
+ Notify(\_SB.PC00.RP14, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP15.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP15.HPME()
+ Notify(\_SB.PC00.RP15, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP16.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP16.HPME()
+ Notify(\_SB.PC00.RP16, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP17.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP17.HPME()
+ Notify(\_SB.PC00.RP17, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP18.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP18.HPME()
+ Notify(\_SB.PC00.RP18, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP19.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP19.HPME()
+ Notify(\_SB.PC00.RP19, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP20.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP20.HPME()
+ Notify(\_SB.PC00.RP20, 0x02)
+ }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl
new file mode 100644
index 0000000000..daf80171a1
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl
@@ -0,0 +1,256 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Define various System Agent (SA) PCI Configuration Space
+// registers which will be used to dynamically produce all
+// resources in the Host Bus _CRS.
+//
+OperationRegion (HBUS, PCI_Config, 0x00, 0x100)
+Field (HBUS, DWordAcc, NoLock, Preserve)
+{
+ Offset(0x40), // EPBAR (0:0:0:40)
+ EPEN, 1, // Enable
+ , 11,
+ EPBR, 20, // EPBAR [31:12]
+
+ Offset(0x48), // MCHBAR (0:0:0:48)
+ MHEN, 1, // Enable
+ , 14,
+ MHBR, 17, // MCHBAR [31:15]
+
+ Offset(0x50), // GGC (0:0:0:50)
+ GCLK, 1, // GGCLCK
+
+ Offset(0x54), // DEVEN (0:0:0:54)
+ D0EN, 1, // DEV0 Enable
+ D1F2, 1, // DEV1 FUN2 Enable
+ D1F1, 1, // DEV1 FUN1 Enable
+ D1F0, 1, // DEV1 FUN0 Enable
+
+ Offset(0x60), // PCIEXBAR (0:0:0:60)
+ PXEN, 1, // Enable
+ PXSZ, 2, // PCI Express Size
+ , 23,
+ PXBR, 6, // PCI Express BAR [31:26]
+
+ Offset(0x68), // DMIBAR (0:0:0:68)
+ DIEN, 1, // Enable
+ , 11,
+ DIBR, 20, // DMIBAR [31:12]
+
+ Offset(0x70), // MESEG_BASE (0:0:0:70)
+ , 20,
+ MEBR, 12, // MESEG_BASE [31:20]
+
+ Offset(0x80), // PAM0 Register (0:0:0:80)
+ , 4,
+ PM0H, 2, // PAM 0, High Nibble
+ , 2,
+
+ Offset(0x81), // PAM1 Register (0:0:0:81)
+ PM1L, 2, // PAM1, Low Nibble
+ , 2,
+ PM1H, 2, // PAM1, High Nibble
+ , 2,
+
+ Offset(0x82), // PAM2 Register (0:0:0:82)
+ PM2L, 2, // PAM2, Low Nibble
+ , 2,
+ PM2H, 2, // PAM2, High Nibble
+ , 2,
+
+ Offset(0x83), // PAM3 Register (0:0:0:83)
+ PM3L, 2, // PAM3, Low Nibble
+ , 2,
+ PM3H, 2, // PAM3, High Nibble
+ , 2,
+
+ Offset(0x84), // PAM4 Register (0:0:0:84)
+ PM4L, 2, // PAM4, Low Nibble
+ , 2,
+ PM4H, 2, // PAM4, High Nibble
+ , 2,
+
+ Offset(0x85), // PAM5 Register (0:0:0:85)
+ PM5L, 2, // PAM5, Low Nibble
+ , 2,
+ PM5H, 2, // PAM5, High Nibble
+ , 2,
+
+ Offset(0x86), // PAM6 Register (0:0:0:86)
+ PM6L, 2, // PAM6, Low Nibble
+ , 2,
+ PM6H, 2, // PAM6, High Nibble
+ , 2,
+
+ Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8)
+ , 20,
+ TUUD, 19, // TOUUD [38:20]
+
+ Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC)
+ , 20,
+ TLUD, 12, // TOLUD [31:20]
+
+ Offset(0xC8), // ERRSTS register (0:0:0:C8)
+ , 7,
+ HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR
+}
+//
+// Define a buffer that will store all the bus, memory, and IO information
+// relating to the Host Bus. This buffer will be dynamically altered in
+// the _CRS and passed back to the OS.
+//
+Name(BUF0,ResourceTemplate()
+{
+ //
+ // Bus Number Allocation: Bus 0 to 0xFF
+ //
+ WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00,
+ 0x0000,0x00FF,0x00,0x0100,,,PB00)
+
+ //
+ // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 )
+ //
+ DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+ 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00)
+
+ //
+ // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
+ //
+ Io(Decode16,0x0CF8,0x0CF8,1,0x08)
+
+ //
+ // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF )
+ //
+ DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+ 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01)
+
+ //
+ // Video Buffer Area ( 0xA0000 - 0xBFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800)
+
+ //
+ // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800)
+
+ //
+ // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00)
+
+ //
+ // BIOS Extension Area ( 0xE0000 - 0xE3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000)
+
+ //
+ // BIOS Extension Area ( 0xE4000 - 0xE7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400)
+
+ //
+ // BIOS Extension Area ( 0xE8000 - 0xEBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800)
+
+ //
+ // BIOS Extension Area ( 0xEC000 - 0xEFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00)
+
+ //
+ // BIOS Area ( 0xF0000 - 0xFFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000)
+
+// //
+// // Memory Hole Region ( 0xF00000 - 0xFFFFFF )
+// //
+// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE)
+
+ //
+ // PCI Memory Region ( TOLUD - 0xFEAFFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0x00000000,0xFEAFFFFF,0x00,0xFEB00000,,,PM01)
+
+ //
+ // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) )
+ // (This is dummy range for OS compatibility, will patch it in _CRS)
+ //
+ QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02)
+})
+
+Name(EP_B, 0) // to store EP BAR
+Name(MH_B, 0) // to store MCH BAR
+Name(PC_B, 0) // to store PCIe BAR
+Name(PC_L, 0) // to store PCIe BAR Length
+Name(DM_B, 0) // to store DMI BAR
+
+
+//
+// Get PCIe BAR
+//
+Method(GPCB,0,Serialized)
+{
+ if(LEqual(PC_B,0))
+ {
+ //ShiftLeft(\_SB.PC00.PXBR,26,PC_B)
+ Store(MCFG,PC_B)
+ }
+ Return(PC_B)
+}
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl
new file mode 100644
index 0000000000..9631d8cee3
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl
@@ -0,0 +1,842 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ //
+ // Delay introduced as initial delay after entering ACPI hotplug method
+ //
+ Sleep (200)
+ Store (0x01, IO80)
+ Sleep (10)
+ Store (0,Local1)
+
+ // PC01 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1A.PMEP,1) ) {
+ Store(\_SB.PC01.BR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC01.BR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC01.BR1A, Local0)
+ }
+
+ // PC01 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1B.PMEP,1) ) {
+ Store(\_SB.PC01.BR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC01.BR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC01.BR1B, Local0)
+ }
+
+ // PC01 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1C.PMEP,1) ) {
+ Store(\_SB.PC01.BR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC01.BR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC01.BR1C, Local0)
+ }
+
+ // PC01 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1D.PMEP,1) ) {
+ Store(\_SB.PC01.BR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC01.BR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC01.BR1D, Local0)
+ }
+
+ // PC02 Port 2A PCI-Ex Hot Plug
+ If( LEqual(\_SB.PC02.BR2A.PMEP,1) ) {
+ Store(\_SB.PC02.BR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC02.BR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC02.BR2A, Local0)
+ }
+
+ // PC02 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC02.BR2B.PMEP,1) ) {
+ Store(\_SB.PC02.BR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC02.BR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC02.BR2B, Local0)
+ }
+
+ // PC02 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC02.BR2C.PMEP,1) ) {
+ Store(\_SB.PC02.BR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC02.BR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC02.BR2C, Local0)
+ }
+
+ // PC02 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC02.BR2D.PMEP,1) ) {
+ Store(\_SB.PC02.BR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC02.BR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC02.BR2D, Local0)
+ }
+
+ // PC03 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3A.PMEP,1) ) {
+ Store(\_SB.PC03.BR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC03.BR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC03.BR3A, Local0)
+ }
+
+ // PC03 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3B.PMEP,10) ) {
+ Store(\_SB.PC03.BR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC03.BR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC03.BR3B, Local0)
+ }
+
+ // PC03 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3C.PMEP,1) ) {
+ Store(\_SB.PC03.BR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC03.BR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC03.BR3C, Local0)
+ }
+
+ // PC03 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3D.PMEP,1) ) {
+ Store(\_SB.PC03.BR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC03.BR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC03.BR3D, Local0)
+ }
+
+ // PC06 Port 0 PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC06.QRP0.PMEP,1) ) {
+ Store(\_SB.PC06.QRP0.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC06.QRP0.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC06.QRP0, Local0)
+ }
+
+ // PC07 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1A.PMEP,1) ) {
+ Store(\_SB.PC07.QR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC07.QR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC07.QR1A, Local0)
+ }
+
+ // PC07 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1B.PMEP,1) ) {
+ Store(\_SB.PC07.QR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC07.QR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC07.QR1B, Local0)
+ }
+
+ // PC07 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1C.PMEP,1) ) {
+ Store(\_SB.PC07.QR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC07.QR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC07.QR1C, Local0)
+ }
+
+ // PC07 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1D.PMEP,1) ) {
+ Store(\_SB.PC07.QR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC07.QR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC07.QR1D, Local0)
+ }
+
+ // PC08 Port 2A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2A.PMEP,1) ) {
+ Store(\_SB.PC08.QR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC08.QR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC08.QR2A, Local0)
+ }
+
+ // PC08 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2B.PMEP,1) ) {
+ Store(\_SB.PC08.QR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC08.QR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC08.QR2B, Local0)
+ }
+
+ // PC08 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2C.PMEP,1) ) {
+ Store(\_SB.PC08.QR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC08.QR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC08.QR2C, Local0)
+ }
+
+ // PC08 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2D.PMEP,1) ) {
+ Store(\_SB.PC08.QR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC08.QR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC08.QR2D, Local0)
+ }
+
+ // PC09 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3A.PMEP,1) ) {
+ Store(\_SB.PC09.QR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC09.QR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC09.QR3A, Local0)
+ }
+
+ // PC09 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3B.PMEP,1) ) {
+ Store(\_SB.PC09.QR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC09.QR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC09.QR3B, Local0)
+ }
+
+ // PC09 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3C.PMEP,1) ) {
+ Store(\_SB.PC09.QR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC09.QR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC09.QR3C, Local0)
+ }
+
+ // PC09 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3D.PMEP,1) ) {
+ Store(\_SB.PC09.QR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC09.QR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC09.QR3D, Local0)
+ }
+
+ // PC12 Port 0 PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC12.RRP0.PMEP,1) ) {
+ Store(\_SB.PC12.RRP0.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC12.RRP0.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC12.RRP0, Local0)
+ }
+
+ // PC13 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1A.PMEP,1) ) {
+ Store(\_SB.PC13.RR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC13.RR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC13.RR1A, Local0)
+ }
+
+ // PC13 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1B.PMEP,1) ) {
+ Store(\_SB.PC13.RR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC13.RR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC13.RR1B, Local0)
+ }
+
+ // PC13 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1C.PMEP,1) ) {
+ Store(\_SB.PC13.RR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC13.RR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC13.RR1C, Local0)
+ }
+
+ // PC13 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1D.PMEP,1) ) {
+ Store(\_SB.PC13.RR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC13.RR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC13.RR1D, Local0)
+ }
+
+ // PC14 Port 2A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2A.PMEP,1) ) {
+ Store(\_SB.PC14.RR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC14.RR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC14.RR2A, Local0)
+ }
+
+ // PC14 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2B.PMEP,1) ) {
+ Store(\_SB.PC14.RR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC14.RR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC14.RR2B, Local0)
+ }
+
+ // PC14 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2C.PMEP,1) ) {
+ Store(\_SB.PC14.RR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC14.RR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC14.RR2C, Local0)
+ }
+
+ // PC15 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2D.PMEP,1) ) {
+ Store(\_SB.PC14.RR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC14.RR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC14.RR2D, Local0)
+ }
+
+ // PC15 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3A.PMEP,1) ) {
+ Store(\_SB.PC15.RR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC15.RR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC15.RR3A, Local0)
+ }
+
+ // PC15 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3B.PMEP,1) ) {
+ Store(\_SB.PC15.RR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC15.RR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC15.RR3B, Local0)
+ }
+
+ // PC15 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3C.PMEP,1) ) {
+ Store(\_SB.PC15.RR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC15.RR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC15.RR3C, Local0)
+ }
+
+ // PC15 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3D.PMEP,1) ) {
+ Store(\_SB.PC15.RR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC15.RR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC15.RR3D, Local0)
+ }
+
+ // PC18 Port 0 PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC18.SRP0.PMEP,1) ) {
+ Store(\_SB.PC18.SRP0.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC18.SRP0.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC18.SRP0, Local0)
+ }
+
+ // PC19 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1A.PMEP,1) ) {
+ Store(\_SB.PC19.SR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC19.SR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC19.SR1A, Local0)
+ }
+
+ // PC19 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1B.PMEP,1) ) {
+ Store(\_SB.PC19.SR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC19.SR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC19.SR1B, Local0)
+ }
+
+ // PC19 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1C.PMEP,1) ) {
+ Store(\_SB.PC19.SR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC19.SR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC19.SR1C, Local0)
+ }
+
+ // PC19 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1D.PMEP,1) ) {
+ Store(\_SB.PC19.SR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC19.SR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC19.SR1D, Local0)
+ }
+
+ // PC20 Port 2A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2A.PMEP,1) ) {
+ Store(\_SB.PC20.SR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC20.SR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC20.SR2A, Local0)
+ }
+
+ // PC20 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2B.PMEP,1) ) {
+ Store(\_SB.PC20.SR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC20.SR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC20.SR2B, Local0)
+ }
+
+ // PC20 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2C.PMEP,1) ) {
+ Store(\_SB.PC20.SR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC20.SR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC20.SR2C, Local0)
+ }
+
+ // PC20 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2D.PMEP,1) ) {
+ Store(\_SB.PC20.SR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC20.SR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC20.SR2D, Local0)
+ }
+
+ // PC21 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3A.PMEP,1) ) {
+ Store(\_SB.PC21.SR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC21.SR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC21.SR3A, Local0)
+ }
+
+ // PC21 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3B.PMEP,1) ) {
+ Store(\_SB.PC21.SR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC21.SR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC21.SR3B, Local0)
+ }
+
+ // PC21 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3C.PMEP,1) ) {
+ Store(\_SB.PC21.SR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC21.SR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC21.SR3C, Local0)
+ }
+
+ // PC21 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3D.PMEP,1) ) {
+ Store(\_SB.PC21.SR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC21.SR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC21.SR3D, Local0)
+ }
+
+ //If a hotplug event was serviced check if this was generated by PM_PME
+ If (Lnot (LEqual(Local0, 0))) {
+ //Clear the status bit 16 of PMEStatus
+ //Clear the PME Pending bit 17 of PMEStatus
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC01.BR1A.PMES)
+ Store(1, \_SB.PC01.BR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC01.BR1B.PMES)
+ Store(1, \_SB.PC01.BR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC01.BR1C.PMES)
+ Store(1, \_SB.PC01.BR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC01.BR1D.PMES)
+ Store(1, \_SB.PC01.BR1D.PMEP)
+ }
+
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC02.BR2A.PMES)
+ Store(1, \_SB.PC02.BR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC02.BR2B.PMES)
+ Store(1, \_SB.PC02.BR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC02.BR2C.PMES)
+ Store(1, \_SB.PC02.BR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC02.BR2D.PMES)
+ Store(1, \_SB.PC02.BR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC03.BR3A.PMES)
+ Store(1, \_SB.PC03.BR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC03.BR3B.PMES)
+ Store(1, \_SB.PC03.BR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC03.BR3C.PMES)
+ Store(1, \_SB.PC03.BR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC03.BR3D.PMES)
+ Store(1, \_SB.PC03.BR3D.PMEP)
+ }
+
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC06.QRP0.PMES)
+ Store(1, \_SB.PC06.QRP0.PMEP)
+ }
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC07.QR1A.PMES)
+ Store(1, \_SB.PC07.QR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC07.QR1B.PMES)
+ Store(1, \_SB.PC07.QR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC07.QR1C.PMES)
+ Store(1, \_SB.PC07.QR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC07.QR1D.PMES)
+ Store(1, \_SB.PC07.QR1D.PMEP)
+ }
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC08.QR2A.PMES)
+ Store(1, \_SB.PC08.QR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC08.QR2B.PMES)
+ Store(1, \_SB.PC08.QR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC08.QR2C.PMES)
+ Store(1, \_SB.PC08.QR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC08.QR2D.PMES)
+ Store(1, \_SB.PC08.QR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC09.QR3A.PMES)
+ Store(1, \_SB.PC09.QR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC09.QR3B.PMES)
+ Store(1, \_SB.PC09.QR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC09.QR3C.PMES)
+ Store(1, \_SB.PC09.QR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC09.QR3D.PMES)
+ Store(1, \_SB.PC09.QR3D.PMEP)
+ }
+
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC12.RRP0.PMES)
+ Store(1, \_SB.PC12.RRP0.PMEP)
+ }
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC13.RR1A.PMES)
+ Store(1, \_SB.PC13.RR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC13.RR1B.PMES)
+ Store(1, \_SB.PC13.RR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC13.RR1C.PMES)
+ Store(1, \_SB.PC13.RR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC13.RR1D.PMES)
+ Store(1, \_SB.PC13.RR1D.PMEP)
+ }
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC14.RR2A.PMES)
+ Store(1, \_SB.PC14.RR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC14.RR2B.PMES)
+ Store(1, \_SB.PC14.RR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC14.RR2C.PMES)
+ Store(1, \_SB.PC14.RR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC14.RR2D.PMES)
+ Store(1, \_SB.PC14.RR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC15.RR3A.PMES)
+ Store(1, \_SB.PC15.RR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC15.RR3B.PMES)
+ Store(1, \_SB.PC15.RR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC15.RR3C.PMES)
+ Store(1, \_SB.PC15.RR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC15.RR3D.PMES)
+ Store(1, \_SB.PC15.RR3D.PMEP)
+ }
+
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC18.SRP0.PMES)
+ Store(1, \_SB.PC18.SRP0.PMEP)
+ }
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC19.SR1A.PMES)
+ Store(1, \_SB.PC19.SR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC19.SR1B.PMES)
+ Store(1, \_SB.PC19.SR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC19.SR1C.PMES)
+ Store(1, \_SB.PC19.SR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC19.SR1D.PMES)
+ Store(1, \_SB.PC19.SR1D.PMEP)
+ }
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC20.SR2A.PMES)
+ Store(1, \_SB.PC20.SR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC20.SR2B.PMES)
+ Store(1, \_SB.PC20.SR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC20.SR2C.PMES)
+ Store(1, \_SB.PC20.SR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC20.SR2D.PMES)
+ Store(1, \_SB.PC20.SR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC21.SR3A.PMES)
+ Store(1, \_SB.PC21.SR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC21.SR3B.PMES)
+ Store(1, \_SB.PC21.SR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC21.SR3C.PMES)
+ Store(1, \_SB.PC21.SR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC21.SR3D.PMES)
+ Store(1, \_SB.PC21.SR3D.PMEP)
+ }
+
+ Store(0x01,PEES) //Clear bit 9 of Status
+ Store(0x00,PMEE) //Clear bit 9 of GPE0_EN
+ }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl
new file mode 100644
index 0000000000..2dd9357359
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl
@@ -0,0 +1,686 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+//;************************************************************************;
+//; IMPORTANT NOTE:
+//; Code in this file should be generic/common for any IIO PCIe root port.
+//; DO NOT use hard-coded Bus/Dev/Function # in this file.
+//;
+//;************************************************************************;
+
+
+
+ Name(DBFL, 0) // Debug flag 0/1 = disable/enable debug checkpoints in this file
+
+
+
+ //;************************************************************************;
+ //; This DVPS() method detects if the root port is present and hot-plug capable.
+ //; Input : None
+ //; Output: Non-zero - Root port is present and hot-plug capable
+ //; Zero - otherwise
+ //;************************************************************************;
+ Method(DVPS,0) {
+ // Check if VID/DID = 3C0x_8086 to see if the root port exists
+ If (LNotEqual(VID, 0x8086)) { Return(Zero) }
+ //If( LNotEqual(And(DID, 0xFFF0), 0x3C00)) { Return(Zero) }
+ If( LNotEqual(And(DID, 0xFFF0), 0x2F00)) { Return(Zero) } //HSX
+ // Check the root port to see if slot is implemented and Hot-Plug Capable
+ If(LNot(And(SLIP, HPCP))) { Return(Zero) }
+ Return (One)
+ }
+
+
+ //;************************************************************************;
+ //; This HPEN() method programs "Enable ACPI mode for Hot-plug" bit based on input Arg0
+ //; See IIO PCIe rootport MISCCTRLSTS register 188h[3] definition
+ //; Input : 0/1 bit value to set "Enable ACPI mode for Hot-plug" (IIO PCIe rootport register 188h[3])
+ //; Output: None
+ //;************************************************************************;
+ Method (HPEN, 1, Serialized) {
+
+ DB55(0x71, 0) // debug point
+
+ // get Bus/Dev/Func information of this root port
+ Store(^^_BBN, Local0) // Local0 = Bus# of parent Host bus
+ //Store(_BBN, Local0) // implicit reference to PC00._BBN
+ ShiftRight(_ADR, 16, Local1) // Local1 = self Device #
+ And(_ADR, 0x0000ffff, Local2) // Local2 = self Function #
+
+ // Calculate MMCFG config address of MISCCTRLSTS register at B:D:F:offset 188h
+ //Name (MISR, 0xC0000188)
+ Name (MISR, 0) // create a pointer to MMCFG region space
+ Add(MMBS, 0x188, MISR) // MISR = MMCFG_BASE_ADDR + Offset of MISCCTRLSTS CSR
+ Add(ShiftLeft(Local0, 20), MISR, MISR) // Build bus/dev/func number fields of MISR
+ Add(ShiftLeft(Local1, 15), MISR, MISR)
+ Add(ShiftLeft(Local2, 12), MISR, MISR)
+
+ DB55(0x77, MISR) // debug point
+
+
+ // Create OpRegion for MISCCTRLSTS register at B:D:F:offset 188h
+ OperationRegion (OP37, SystemMemory, MISR, 0x04)
+ Field (OP37, DWordAcc, NoLock, Preserve) {
+ , 3,
+ HGPE, 1, // "Enable ACPI mode for Hot-plug" (register 188h[3])
+ }
+
+ // Program "Enable ACPI mode for Hot-plug" bit to input Arg0
+ Store(Arg0, HGPE)
+ }
+
+ //;************************************************************************;
+ //; This DB55() method is a debug method
+ //; Input : Arg0 Postcode to be sent to IO Port 80h
+ //; Arg1 DWord data to be copied to debug memory location
+ //; in BIOS Data Area (DBA) 40:42
+ //; Output: None
+ //;************************************************************************;
+ Method (DB55, 2, NotSerialized) {
+
+ If (DBFL) { // if debug is enabled
+ Store(Arg0, IO80) // send postcode to port 80h
+ Store(Arg1, MDWD) // store Arg1 to debug memory location
+ Sleep(4000) // stall for 4 seconds
+ }
+ }
+
+ OperationRegion (OP38, SystemMemory, 0x442, 0x04)
+ Field (OP38, AnyAcc, NoLock, Preserve) {
+ MDWD, 32, // dword at BIOS Data Area (BDA) 40:42 (floppy task-file), used as debug memory location
+ }
+
+
+ Method (_INI, 0, NotSerialized) {
+
+ If (LEqual(Zero,DVPS)) {
+ Return // Do nothing if this root port is not "Present and Hot-plugable"
+ }
+ HPEN(1) // No. Enable ACPI Hot-plug events
+ }
+
+
+/* Greencity code
+ OperationRegion (MCTL, SystemMemory, 0xA0048188, 0x04)
+ Field (MCTL, ByteAcc, NoLock, Preserve) {
+ , 3,
+ HGPE, 1,
+ , 7,
+ , 8,
+ , 8
+ }
+
+ Method (_INI, 0, NotSerialized) {
+ Store (0x01, HGPE) //enable GPE message generation for ACPI hotplug support
+ }
+*/
+
+//MCWU Changed ^HP02 to HP02 to avoid re-definition when this file is included under multiple BRxx devices
+ //Name(^HP02, Package(4){0x08, 0x40, 1, 0} )
+ Name(HP02, Package(4){0x08, 0x40, 1, 0} )
+ Method(_HPP, 0) { return(HP02) }
+
+ //
+ // begin hotplug code
+ //
+ Name(SHPC, 0x40) // Slot Hot-plug Capable
+
+ Name(SPDS, 0x040) // Slot Presence Detect State
+
+ Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on
+ Name(CCOM, 0x010) // Command Complete
+ Name(SPDC, 0x08) // Slot Presence Detect Changes
+ Name(MRLC, 0x04) // Slot MRL Changed
+ Name(SPFD, 0x02) // Slot Power Fault Detected
+ Name(SABP, 0x01) // Slot Attention Button Pressed
+
+ Name(SPOF, 0x10) // Slot Power Off
+ Name(SPON, 0x0F) // Slot Power On Mask
+
+ Name(ALMK, 0x1C) // Slot Atten. LED Mask
+ Name(ALON, 0x01) // Slot Atten. LED On
+ Name(ALBL, 0x02) // Slot Atten LED Blink
+ Name(ALOF, 0x03) // Slot Atten LED Off
+
+ Name(PLMK, 0x13) // Slot Pwr. LED Mask
+ Name(PLON, 0x04) // Slot Pwr. LED On
+ Name(PLBL, 0x08) // Slot Pwr. LED Blink
+ Name(PLOF, 0x0C) // Slot Pwr. LED Off
+
+ //;*************************************
+ //; Bit 3 = Presence Detect Event
+ //; Bit 2 = MRL Sensor Event
+ //; Bit 1 = PWR Fault Event
+ //; Bit 0 = Attention Button Event
+ //;*************************************
+ Name(HPEV, 0xF) // Possible interrupt events (all)
+
+ //;************************************************************************;
+ //;
+ //; PCIe Slot Capabilities Register A4-A7h
+ //; Bit - 31-7 - Not used
+ //; Bit - 6 - Hot-Plug Capable
+ //; Bit - 5 - Hot-Plug Surprise
+ //; Bit - 4 - Power Indicator Present.
+ //; Bit - 3 - Attention Indicator Present.
+ //; Bit - 2 - MRL Sensor Present.
+ //; Bit - 1 - Power Controller Present.
+ //; Bit - 0 - Attention Button Present.
+ //;
+ //; PCIe Slot control Register A8-A9h
+ //;
+ //; Bit - 10 - PWR Control Disable
+ //; Bit - 9:8 - Attn Indicator
+ //; Bit - 7:6 - PWR Indicator
+ //; Bit - 5 - Hot-Plug Interrupt Event Enable
+ //; Bit - 4 - Command Complete Interrupt enable
+ //; Bit - 3 - Presence Detect Changed Interrupt enable
+ //; Bit - 2 - MRL Sensor Changed Interrupt enable
+ //; Bit - 1 - PwrFault Detect Interrupt enable
+ //; Bit - 0 - Attention Button Pressed Interrupt Enable
+ //;
+ //; PCIe Slot Status Registers AA-ADh
+ //;
+ //; Bit - 6 - Presence Detect State.
+ //; Bit - 5 - MRL Sensor State.
+ //; Bit - 4 - Command Completed.
+ //;
+ //; RWC Status Bits
+ //;
+ //; Bit - 3 - Presence Detect Changed.
+ //; Bit - 2 - MRL Sensor Changed.
+ //; Bit - 1 - Power Fault Detected.
+ //; Bit - 0 - Attention Button Pressed.
+ //;************************************************************************;
+
+ OperationRegion(PPA4, PCI_Config, 0x00, 0x0ff)
+ Field(PPA4,ByteAcc,NoLock,Preserve) {
+
+ Offset(0x00), // VenderID/DeviceID register
+ VID, 16, // VID = 0x8086
+ DID, 16, // Device IDs for IIO PCI Express root ports are as follows:
+ // 0x3C00: DMI mode 0x3C01: the DMI port running in PCIe mode
+ // 0x3C02: Port 1a
+ // 0x3C03: Port 1b
+ // 0x3C04: Port 2a
+ // 0x3C05: Port 2b
+ // 0x3C06: Port 2c
+ // 0x3C07: Port 2d
+ // 0x3C08: Port 3a in PCIe mode
+ // 0x3C09: Port 3b
+ // 0x3C0A: Port 3c
+ // 0x3C0B: Port 3d
+ // (0x3C0F: IIO NTB Secondary Endpoint)
+
+ Offset(0x92), // PXPCAP - PCIe CAP Register
+ , 8,
+ SLIP, 1, // bit8 Slot Implemented
+
+ offset(0xA4), // SLTCAP - Slot Capabilities Register
+ ATBP,1, // bit0 Attention Button Present
+ PWCP,1, // bit1 Power Controller Present
+ MRSP,1, // bit2 MRL Sensor Present
+ ATIP,1, // bit3 Attention Indicator Present
+ PWIP,1, // bit4 Power Indicator Present
+ HPSR,1, // bit5 Hot-Plug Surprise
+ HPCP,1, // bit6 Hot-Plug Capable
+
+ offset(0xA8), // SLTCON - PCIE Slot Control Register
+ ABIE,1, // bit0 Attention Button Pressed Interrupt Enable
+ PFIE,1, // bit1 Power Fault Detected Interrupt Enable
+ MSIE,1, // bit2 MRL Sensor Changed Interrupt Enable
+ PDIE,1, // bit3 Presence Detect Changed Interrupt Enable.
+ CCIE,1, // bit4 Command Complete Interrupt Enable.
+ HPIE,1, // bit5 Hot-plug Interrupt Enable.
+ SCTL,5, // bit[10:6] Attn/Power indicator and Power controller.
+
+ offset(0xAA), // SLTSTS - PCIE Slot Status Register
+ SSTS,7, // The status bits in Slot Status Reg
+ ,1,
+}
+
+ OperationRegion(PPA8, PCI_Config, 0x00, 0x0ff)
+ Field(PPA8,ByteAcc,NoLock,Preserve) {
+ Offset(0xA8), // SLTCON - PCIE Slot Control Register
+ ,6,
+ ATID,2, // bit[7:6] Attention Indicator Control.
+ PWID,2, // bit[9:8] Power Indicator Control.
+ PWCC,1, // bit[10] Power Controller Control.
+ ,5,
+ Offset(0xAA), // SLTSTS - PCIE Slot status Register (WRC)
+ ABPS,1, // bit0 Attention Button Pressed Status (RWC)
+ PFDS,1, // bit1 Power Fault Detect Status (RWC)
+ MSCS,1, // bit2 MRL Sensor Changed Status
+ PDCS,1, // bit3 Presence Detect Changed Status
+ CMCS,1, // bit4 Command Complete Status
+ MSSC,1, // bit5 MRL Sensor State
+ PRDS,1, // bit6 Presence Detect State
+ ,1,
+ }
+
+ //;************************************************************************;
+ //; This OSHP (Operating System Hot Plug) method is provided for each HPC
+ //; which is controlled by ACPI. This method disables ACPI access to the
+ //; HPC and restores the normal System Interrupt and Wakeup Signal
+ //; connection.
+ //;************************************************************************;
+ Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express HP code.
+ Store(0, SSTS) // Clear any status
+// Store(0x0, HGPE) // Disable GPE generation
+ HPEN(0) // Disable GPE generation
+ }
+
+ //;************************************************************************;
+ //; Hot Plug Controller Command Method
+ //;
+ //; Input: Arg0 - Command to issue
+ //;
+ //;************************************************************************;
+ Method(HPCC,1) {
+ Store(SCTL, Local0) // get current command state
+ Store(0, Local1) // reset the timeout value
+ If(LNotEqual(Arg0, Local0)) { // see if state is different
+ Store(Arg0, SCTL) // Update the Slot Control
+ While(LAnd (LNot(CMCS), LNotEqual(100, Local1))) { // spin while CMD complete bit is not set,
+ // check for timeout to avoid dead loop
+ Store(0x2C, IO80)
+ Sleep(2) // allow processor time slice
+ Add(Local1, 2, Local1)
+ }
+ Store(0x1, CMCS) // Clear the command complete status
+ }
+ }
+
+ //;************************************************************************;
+ //; Attention Indicator Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = ON
+ //; 2 = Blink
+ //; 3 = OFF
+ //;************************************************************************;
+ Method(ATCM,1) {
+ Store(SCTL, Local0) // Get Slot Control
+ And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
+ If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?"
+ Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON"
+ }
+ If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?"
+ Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK"
+ }
+ If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?"
+ Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; Power Indicator Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = ON
+ //; 2 = Blink
+ //; 3 = OFF
+ //;************************************************************************;
+ Method(PWCM,1){
+ Store(SCTL, Local0) // Get Slot Control
+ And(Local0, PLMK, Local0) // Mask the Power Indicator Bits
+ If(LEqual(Arg0, 0x1)){ // Power indicator "ON?"
+ Or(Local0, PLON, Local0) // Set the Power Indicator to "ON"
+ }
+ If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?"
+ Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK"
+ }
+ If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?"
+ Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; Power Slot Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = Slot Power ON
+ //; 2 = Slot Power Off
+ //;************************************************************************;
+ Method(PWSL,1){
+ Store(SCTL, Local0) // Get Slot Control
+ If(Arg0){ // Power Slot "ON" Arg0 = 1
+ And(Local0, SPON, Local0) // Turns the Power "ON"
+ } Else { // Power Slot "OFF"
+ Or(Local0, SPOF, Local0) // Turns the Power "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; _OST Methods to indicate that the device Eject/insert request is
+ //; pending, OS could not complete it
+ //;
+ //; Input: Arg0 - Value used in Notify to OS
+ //; 0x00 - card insert
+ //; 0x03 - card eject
+ //; Arg1 - status of Notify
+ //; 0 - success
+ //; 0x80 - Ejection not supported by OSPM
+ //; 0x81 - Device in use
+ //; 0x82 - Device Busy
+ //; 0x84 - Ejection in progress-pending
+ //;************************************************************************;
+ Method(_OST,3,Serialized) {
+ Switch(And(Arg0,0xFF)) { // Mask to retain low byte
+ Case(0x03) { // Ejection Request
+ Switch(ToInteger(Arg1)) {
+ Case(Package() {0x80, 0x81, 0x82, 0x83}) {
+ //
+ // Ejection Failure for some reason
+ //
+ If (Lnot(PWCC)) { // if slot is powered
+ PWCM(0x1) // Set PowerIndicator to ON
+ Store(0x1,ABIE) // Set AttnBtn Interrupt ON
+ }
+ }
+ }
+ }
+ }
+ } // End _OST
+
+ //;************************************************************************;
+ //; Eject Control Methods to indicate that the device is hot-ejectable and
+ //; should "eject" the device.
+ //;
+ //; Input: Arg0 - Not use.
+ //;
+ //;************************************************************************;
+ Method(EJ02, 1){
+ Store(0xFF, IO80)
+ Store(SCTL, Local0) // Get IOH Port 9/SLot3 Control state
+ if( LNot( LEqual( ATID, 1))) { // Check if Attention LED is not solid "ON"
+ And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
+ Or(Local0, ALBL, Local0) // Set the Attention Indicator to blink
+ }
+ HPCC(Local0) // issue command
+
+ Store(SCTL, Local0) // Get IOH Port 9/SLot3 Control state
+ Or(Local0, SPOF, Local0) // Set the Power Controller Control to Power Off
+ HPCC(Local0)
+
+ Store(SCTL, Local0) // Get PEXH Port 9/SLot3 Control state
+ Or(Local0, PLOF, Local0) // Set the Power Indicator to Off.
+ HPCC(Local0)
+ } // End of EJ02
+
+ //;************************************************************************;
+ //; PM_PME Wake Handler for Slot 3 only
+ //;
+ //; Input: Arg0 - Slot Number
+ //;
+ //;************************************************************************;
+ Method(PMEH,1){ // Handler for PCI-E PM_PME Wake Event/Interrupt (GPI xxh)
+ If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
+ If(ABPS) {
+ Store (Arg0, IO80) // Send slot number to Port 80
+ Store(0x1, ABPS) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ }
+ }
+ Return (0xff) // Indicate that this controller did not interrupt
+ } // End of Method PMEH
+
+ //;************************************************************************;
+ //; Hot-Plug Handler for an IIO PCIe root port slot
+ //;
+ //; Input: Arg0 - Slot Numnber (not used)
+ //; Output:
+ //; 0xFF - No hotplug event detected
+ //; 0x03 - Eject Request detected
+ //; 0x00 - Device Presence Changed
+ //;
+ //;************************************************************************;
+ Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/Interupt Called from \_SB.GPE._L01()
+
+ If (LEqual(Zero,DVPS)) {
+ Return (0xff) // Do nothing if root port is not "Present and Hot-plugable"
+ }
+
+ Store(0x22, IO80)
+ Sleep(100)
+ Store(0,CCIE) // Disable command interrupt
+ If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
+ Store(0x3A, IO80)
+ Sleep(10)
+ Store(PP3H(0x0), Local0) // Call the Slot 3 Hot plug Interrupt Handler
+ Return(Local0) // Return PP2H information
+ }
+ Else{
+ Return (0xff) // Indicate that this controller did not interrupt
+ }
+ Store(0x2F, IO80)
+ Sleep(10)
+ } // End of Method HPEH
+
+ //;************************************************************************;
+ //; Interrut Event Handler
+ //;
+ //; Input: Arg0 - Slot Numnber
+ //;
+ //;************************************************************************;
+ Method(PP3H,1){ // Slot 3 Hot plug Interrupt Handler
+ //
+ // Check for the Atention Button Press, Slot Empty/Presence, Power Controller Control.
+ //
+ Sleep(200) // HW Workaround for AttentionButton Status to stabilise
+ If(ABPS) { // Check if Attention Button Pressed for Device 4
+ If(LNot(PRDS)) { // See if nothing installed (no card in slot)
+ PWSL(0x0) // make sure Power is Off
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ //
+ // Check for MRL here and set attn indicator accordingly
+ //
+ If(LEqual(MSSC,MRLS)) { // Standby power is on - MRL closed
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ } else { // Standby power is off - MRL open
+ ATCM(0x3) // set attention indicator "OFF"
+ }
+ Store(0x0, ABIE) // set Attention Button Interrupt to disable
+ Store(0x1, ABPS) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ Return(0xff) // Attn Button pressed without card in slot. Do nothing
+ }
+ //
+ // Card is present in slot so....
+ //
+ Store(0x0, ABIE) // set Attention Button Interrupt to disable
+ // Attn Btn Interrupt has to be enabled only after an insert oprn
+ Store(0x1, ABPS) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ //
+ // Check for MRL here - only if SPWR is OFF blink AttnInd and retun 0xff
+ //
+ If(LNot(LEqual(MSSC,MRLS))) { // Standby power is off
+ PWSL(0x0) // make sure Power is Off
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ Return(0xff) // Attn Button pressed with card in slot, but MRL open. Do nothing
+ }
+ //Card Present, if StandbyPwr is ON proceed as below with Eject Sequence
+ If(PWCC) { // Slot not Powered
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ Return(0xff) // Attn Button pressed with card in slot, MRL closed, Slot not powered. Do nothing
+ } else { // See if Slot is already Powered
+ PWCM(0x2) // Set power Indicator to BLINK
+ Sleep(600) // Wait 100ms
+ Store(600, Local0) // set 5 second accumulator to 0
+ Store(0x1, ABPS) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ While(LNot(ABPS)) { // check for someone pressing Attention
+ Sleep(200) // Wait 200ms
+ Add(Local0, 200, Local0)
+ If(LEqual(5000, Local0)) { // heck if 5sec has passed without pressing attnetion btn
+ Store(0x1, ABPS) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ Return (0x3) // continue with Eject request
+ }
+ }
+ PWCM(0x1) // Set power Indicator baCK "ON"
+ Store(0x1, ABPS) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Store(0x1, ABIE) // set Attention Button Interrupt to enable
+ Return (0xff) // do nothing and abort
+ }
+ } // End if for the Attention Button Hot Plug Interrupt.
+
+ If(PFDS) { // Check if Power Fault Detected
+ Store(0x1, PFDS) // Clear the Power Fault Status
+ PWSL(0x0) // set Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ Return(0x03) // Eject request.
+ } // End if for the Power Fault Interrupt.
+
+ If(MSCS) { // Check interrupt caused by the MRL Sensor
+ Store(0x1, MSCS) // Clear the MRL Status
+ If(LEqual(MSSC,MRLS)) { // Standby power is on - MRL closed
+ If(PRDS) { // Card is Present
+ // Slot Power is Off, so power up the slot
+ ATCM(0x3) // Set Attention Indicator to off
+ PWCM(0x2) // Set Power Indicator to Blink
+ Sleep(600) // Wait 100ms
+ Store(600, Local0) // set 5 second accumulator to 0
+ Store(0x1, ABPS) // Clear the interrupt status
+ While(LNot(ABPS)) { // check for someone pressing Attention
+ Sleep(200) // Wait 200ms
+ Add(Local0, 200, Local0)
+ If(LEqual(5000, Local0)) { // Check if 5 sec elapsed
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ ATCM(0x3) // set attention indicator "OFF"
+ PWSL(0x1) // Power the Slot
+ Sleep(500) // Wait for .5 Sec for the Power to Stabilize.
+ // Check for the Power Fault Detection
+ If(LNot(PFDS)) { // No Power Fault
+ PWCM(0x1) // Set Power Indicator to "ON"
+ // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slot Clock (GPIO16)
+ // Notify the OS to load the Driver for the card
+ Store(0x00, Local1)
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ } Else { // Power Fault present
+ PWSL(0x0) // set Slot Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Slot Clock (GPIO16)
+ Store(0x03, Local1) // Eject request.
+ } // End if for the Slot Power Fault
+ Store(0x1, ABPS) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Return(Local1)
+ }
+ }
+ //
+ // someone pressed Attention Button
+ //
+ Store(0x1, ABPS) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(02) // Set Attention Indicator to "BLINK"
+ Return(0xff) // leave it off
+ // End of Insert sequence
+ }
+ //MRL is closed, Card is not present
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(02) // Set Attention Indicator to "BLINK"
+ Return(0xff) // leave it off
+ } else { // MRL is open i.e Stdby power is turned off
+ If(PRDS) {
+ //card present MRL switched off
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ If(Lnot(PWCC)) { // If slot is powered
+ // This event is not supported and someone has opened the MRL and dumped the power
+ // on the slot with possible pending transactions. This could hose the OS.
+ // Try to Notify the OS to unload the drivers.
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ Return(0x03) // Eject request.
+ } else { // Slot not powered, MRL is opened, card still in slot - Eject not fully complete
+ Return(0xFF)
+ }
+ }
+ //no card present and Stdby power switched off, turn AI off
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ Return(0xff) // leave it off
+ } // End of MRL switch open/close state
+ } // End of MRL Sensor State Change
+
+ If(PDCS) { // Check if Presence Detect Changed Status
+ Store(0x1, PDCS) // Clear the Presence Detect Changed Status
+ If(LNot(PRDS)) { // Slot is Empty
+ PWSL(0x0) // Set Slot Power "OFF"
+ PWCM(0x3) // set power indicator to "OFF"
+ If(LEqual(MSSC,MRLS)) { // If Standby power is on
+ ATCM(0x2) // Set Attention Indicator to "Blink"
+ } else {
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ }
+ Return(0xFF) // Do nothing
+ } Else { // Slot Card is inserted
+ // Irrespective of MRL state blink indicator
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(0x2) // Set Attention Indicator to "Blink"
+ Return(0xFF) // Do nothing
+ }
+ } // End if for the Presence Detect Changed Hot Plug Interrupt.
+ Return(0xff) // should not get here, but do device check if it does.
+ } // End of method PP5H
+ //
+ // End of hotplug code
+ //
+
+ Device(H000) {
+ Name(_ADR, 0x00000000)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H001) {
+ Name(_ADR, 0x00000001)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H002) {
+ Name(_ADR, 0x00000002)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H003) {
+ Name(_ADR, 0x00000003)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H004) {
+ Name(_ADR, 0x00000004)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H005) {
+ Name(_ADR, 0x00000005)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H006) {
+ Name(_ADR, 0x00000006)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H007) {
+ Name(_ADR, 0x00000007)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl
new file mode 100644
index 0000000000..af3f6581db
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl
@@ -0,0 +1,32 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+// ITSS
+// Define the needed ITSS registers used by ASL on Interrupt
+// mapping.
+
+scope(\_SB){
+ OperationRegion(ITSS, SystemMemory, 0xfdc43100, 0x208)
+ Field(ITSS, ByteAcc, NoLock, Preserve)
+ {
+ PARC, 8,
+ PBRC, 8,
+ PCRC, 8,
+ PDRC, 8,
+ PERC, 8,
+ PFRC, 8,
+ PGRC, 8,
+ PHRC, 8,
+ Offset(0x200), // Offset 3300h ITSSPRC - ITSS Power Reduction Control
+ , 1,
+ , 1,
+ SCGE, 1, // ITSSPRC[2]: 8254 Static Clock Gating Enable (8254CGE)
+
+ }
+}
+
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi
new file mode 100644
index 0000000000..863518b3a5
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi
@@ -0,0 +1,202 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Device (DMAC) {
+ Name (_HID, EISAID("PNP0200"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16, 0x0, 0x0, 0, 0x10)
+ IO(Decode16, 0x81, 0x81, 0, 0x3)
+ IO(Decode16, 0x87, 0x87, 0, 0x1)
+ IO(Decode16, 0x89, 0x89, 0, 0x3)
+ IO(Decode16, 0x8f, 0x8f, 0, 0x1)
+ IO(Decode16, 0xc0, 0xc0, 0, 0x20)
+ DMA(Compatibility,NotBusMaster,Transfer8) {4}
+ })
+}
+
+Device (RTC) {
+ Name (_HID,EISAID("PNP0B00"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0x70,0x70,0x01,0x02)
+ IO(Decode16,0x74,0x74,0x01,0x04)
+ IRQNoFlags(){8}
+ })
+}
+
+Device (PIC) {
+ Name (_HID,EISAID("PNP0000"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes all aliases
+ IO(Decode16,0xA0,0xA0,0x01,0x1E)
+ IO(Decode16,0x4D0,0x4D0,0x01,0x02)
+ })
+}
+
+Device (FPU) {
+ Name (_HID,EISAID("PNP0C04"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0xF0,0xF0,0x01,0x1)
+ IRQNoFlags(){13}
+ })
+}
+
+Device(TMR)
+{
+ Name(_HID,EISAID("PNP0100"))
+
+ Name(_CRS,ResourceTemplate() {
+ IO(Decode16,0x40,0x40,0x01,0x04)
+ IO(Decode16,0x50,0x50,0x01,0x04) // alias
+ IRQNoFlags(){0}
+ })
+}
+
+Device (SPKR) {
+ Name (_HID,EISAID("PNP0800"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0x61,0x61,0x01,0x01)
+ })
+}
+
+//
+// all "PNP0C02" devices- pieces that don't fit anywhere else
+//
+Device(XTRA) {
+ Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices
+ Name(_CRS,
+ ResourceTemplate() {
+ IO(Decode16,0x500,0x500,0x01,0x40) // GPIO space, ICH5
+ IO(Decode16,0x400,0x400,0x01,0x80) // PM IO, ICH5
+ IO(Decode16,0x92,0x92,0x01,0x01) // INIT & Fast A20 port, ICH5
+ //
+ // Resource conflict with COM Port
+ //
+ //IO(Decode16,0x680,0x680,0x01,0x80) // Runtime registers, National SIO
+ IO(Decode16,0x10,0x10,0x01,0x10)
+ IO(Decode16,0x72,0x72,0x01,0x02)
+ IO(Decode16,0x80,0x80,0x01,0x01)
+ IO(Decode16,0x84,0x84,0x01,0x03)
+ IO(Decode16,0x88,0x88,0x01,0x01)
+ IO(Decode16,0x8c,0x8c,0x01,0x03)
+ IO(Decode16,0x90,0x90,0x01,0x10)
+ //
+ // SMBus decode range
+ //
+ IO(Decode16,0x540,0x540,0x01,0x40)
+ //
+ // Pilot Mail Box decode range
+ //
+ IO(Decode16,0x600,0x600,0x01,0x20)
+ //
+ // BMC KCS decode range
+ //
+ IO(Decode16,0xCA0,0xCA0,0x01,0x6)
+ //
+ // Performance Status and control ports decode range
+ //
+ IO(Decode16,0x880,0x880,0x01,0x4)
+
+ //IO Descriptor added for range 800-81f for S501302
+ IO(Decode16,0x800,0x800,0x01,0x20)
+ //IO Descriptor added for range 2F8-2FF for S501706
+ //IO(Decode16,0x2F8,0x2F8,0x01,0x08)
+ //IO(Decode16,0x60,0x60,0x01,0x01)
+ //IO(Decode16,0x64,0x64,0x01,0x01)
+
+ //PCH_ACPI_FLAG: RCBA is not supported in SPT
+ //
+ // RCBA memory range
+ //
+ //Memory32Fixed (ReadOnly, 0xFED1C000, 0x6FFFF) // ICH9 bios spec section 5.10 - reserved memory address space.
+ Memory32Fixed (ReadOnly, 0xFED1C000, 0x24000) // ICH9 bios spec section 5.10 - reserved memory address space.
+ // Leave FED40000-FED45000 for TPM
+ Memory32Fixed (ReadOnly, 0xFED45000, 0x47000) // ICH9 bios spec section 5.10 - reserved memory address space.
+
+ //
+ // FLASH range
+ //
+ Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000) //16MB as per IIO spec
+
+ //
+ // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
+ //
+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000)
+
+ //
+ // HECI range, 32 bytes from HECI1_BASE_ADDRESS (0xFE90_0000 to 0xFE90_001F)
+ //
+ //Memory32Fixed (ReadWrite, 0xFE900000, 0x20)
+ Memory32Fixed (ReadWrite, 0xFED12000, 0x10)
+
+ //
+ // HECI range, 32 bytes from HECI2_BASE_ADDRESS (0xFEA0_0000 to 0xFEA0_001F)
+ //
+ //Memory32Fixed (ReadWrite, 0xFEA00000, 0x20)
+ Memory32Fixed (ReadWrite, 0xFED12010, 0x10)
+
+ //
+ // IIO RCBA memory range
+ //
+ Memory32Fixed (ReadOnly, 0xFED1B000, 0x1000)
+ }
+ )
+}
+
+//
+// High Performance Event Timer (HPET)
+//
+Device (HPET) {
+ Name (_HID, EisaId ("PNP0103"))
+
+ Method (_STA, 0, NotSerialized) {
+ If (\HPTE) {
+ Return (0x0F)
+ } Else {
+ Return (0x00)
+ }
+ }
+
+ Name (CRS0, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
+ })
+
+ Name (CRS1, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED01000, 0x00000400)
+ })
+
+ Name (CRS2, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED02000, 0x00000400)
+ })
+
+ Name (CRS3, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED03000, 0x00000400)
+ })
+
+ //
+ // Owning control method can't be re-entrant, so _CRS must be Serialized
+ //
+ Method (_CRS, 0, Serialized) {
+ Switch (ToInteger(\HPTB)) {
+ Case (0xFED00000) {
+ Return (CRS0)
+ }
+
+ Case (0xFED01000) {
+ Return (CRS1)
+ }
+
+ Case (0xFED02000) {
+ Return (CRS2)
+ }
+
+ Case (0xFED03000) {
+ Return (CRS3)
+ }
+ }
+ Return (CRS0)
+ }
+}
\ No newline at end of file
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi
new file mode 100644
index 0000000000..532e5ba448
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi
@@ -0,0 +1,145 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Scope (\_SB) {
+
+ Name (XCNT, 0)
+ Name (OSYS, 0) // Global variable for type of OS.
+
+ //
+ // Device specific method
+ //
+ Method (_DSM, 4, Serialized) {
+ If (LEqual(Arg0,ToUUID("663E35AF-CC10-41A4-88EA-5470AF055295"))){
+
+ // L1 DIR POINTER
+ Switch (ToInteger(Arg2)) {
+ //
+ //Function 0: Return supported functions, based on revision
+ //
+ Case(0)
+ {
+ Switch (ToInteger(Arg1)) {
+ Case(0) {
+ If (Lequal(EMCA,1))
+ {
+ Return ( Buffer() {0x3} )
+ }
+ Else
+ {
+ Return (Buffer() {0})
+ }
+ }
+ }
+
+ }
+ //
+ // Function 1:
+ //
+ Case(1) {Return (LDIR) }
+ Default { }
+ }
+ }
+
+ Return (Buffer() {0})
+ }
+
+ Method (_INI) {
+
+ If (CondRefOf (_OSI)) {
+
+ If (\_OSI ("Windows 2001.1 SP1")) {
+ Store (5, OSYS) // Windows Server 2003 SP1
+ }
+
+ If (\_OSI ("Windows 2001.1")) {
+ Store (6, OSYS) // Windows Server 2003
+ }
+
+ If (\_OSI ("Windows 2001 SP2")) {
+ Store (7, OSYS) // Windows XP SP2
+ }
+
+ If (\_OSI ("Windows 2001")) {
+ Store (8, OSYS) // Windows XP
+ }
+
+ If (\_OSI ("Windows 2006.1")) {
+ Store (9, OSYS) // Windows Server 2008
+ }
+
+ If (\_OSI ("Windows 2006 SP1")) {
+ Store (10, OSYS) // Windows Vista SP1
+ }
+
+ If (\_OSI ("Windows 2006")) {
+ Store (11, OSYS) // Windows Vista
+ }
+
+ If (\_OSI ("Windows 2009")) {
+ Store (12, OSYS) // Windows Server 2008 R2 & Windows 7
+ }
+
+ If (\_OSI ("Windows 2012")) {
+ Store (13, OSYS) // Windows Server 2012 & Windows 8
+ }
+
+ If (\_OSI ("Windows 2013")) {
+ Store (14, OSYS) // Windows Server 2012 R2 & Windows 8.1
+ }
+
+ If (\_OSI ("Windows 2015")) {
+ Store (15, OSYS) // Windows 10 & Windows Server Technical Preview
+ }
+
+ If (\_OSI ("Windows 2016")) {
+ Store (16, OSYS) // Windows 10, version 1607
+ }
+
+ If (\_OSI ("Windows 2017")) {
+ Store (17, OSYS) // Windows 10, version 1703
+ }
+
+ //
+ // Check Linux also
+ //
+ If (\_OSI ("Linux")) {
+ Store (1, OSYS)
+ }
+
+ If (\_OSI ("FreeBSD")) {
+ Store (2, OSYS)
+ }
+
+ If (\_OSI ("HP-UX")) {
+ Store (3, OSYS)
+ }
+
+ If (\_OSI ("OpenVMS")) {
+ Store (4, OSYS)
+ }
+
+ //
+ // Running WinSvr2012, Win8, or later?
+ //
+ If (LGreaterEqual (\_SB.OSYS, 13)) {
+ //
+ // It is Svr2012 or Win8
+ // Call xHCI device to switch USB ports over
+ // unless it has been done already
+ //
+ If (LEqual (XCNT, 0)) {
+ Store (0x84, IO80)
+ Increment (XCNT)
+ }
+ } Else {
+ Store (\_SB.OSYS, IO80)
+ }
+ }
+ } // End Method (_INI)
+
+} // End Scope (_SB)
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi
new file mode 100644
index 0000000000..6b9ae9b3e7
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi
@@ -0,0 +1,10 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// I/O controller miscellaneous
+//
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi
new file mode 100644
index 0000000000..57bc9f2ba1
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi
@@ -0,0 +1,17 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Device(APIC) {
+ Name (_HID,EISAID("PNP0003")) // APIC resources
+ Name (_CRS, ResourceTemplate() {
+ //
+ // APIC range(0xFEC0_0000 to 0xFECF_FFFF)
+ //
+ Memory32Fixed (ReadOnly, 0xFEC00000, 0x100000) // IO APIC
+ }
+ )
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi
new file mode 100644
index 0000000000..c25af50ed8
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi
@@ -0,0 +1,91 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Name (OPAC, 0)
+
+OperationRegion(PWKE,PCI_Config,0x54,0x18)
+Field(PWKE,DWordAcc,NoLock,Preserve)
+{
+ , 8,
+ PMEE, 1, // PWR_CNTL_STS.PME_En
+ , 6,
+ PMES, 1, // PWR_CNTL_STS.PME_Sts
+ Offset (0x0E),
+ , 1,
+ PWUC, 10 // Port Wake Up Capability Mask
+}
+
+//
+// Indicate access to OperationRegions is enabled/disabled
+//
+Method (_REG, 2)
+{
+ // If OperationRegion ID = PCI_Config
+ //
+ If (LEqual (Arg0, 2))
+ {
+ // If access is enabled
+ //
+ If (LEqual(Arg1, 1))
+ {
+ // Set local flag
+ //
+ Store (One, OPAC)
+ }
+ Else
+ {
+ // Clear local flag
+ //
+ Store (One, OPAC)
+ }
+ }
+}
+
+//
+// Enable/disable ports on this controller to wake the system
+//
+Method (_PSW,1)
+{
+ If (Arg0)
+ {
+ Store (Ones,PWUC)
+ }
+ Else
+ {
+ Store (0,PWUC)
+ }
+}
+
+//
+// Initialization for this controller
+//
+Method (_INI, 0)
+{
+ // If access to OperationRegion is enabled
+ //
+ If (LEqual (OPAC, One))
+ {
+ Store (1, PMES) // clear PME status
+ Store (0, PMEE) // clear PME enable
+ }
+}
+
+// The CRB leaves the USB ports on in S3/S4 to allow
+// the ability to Wake from USB. Therefore, define
+// the below control methods to state D2 entry during
+// the given S-State.
+
+Method(_S3D,0)
+{
+ Return(2)
+}
+
+Method(_S4D,0)
+{
+ Return(2)
+}
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi
new file mode 100644
index 0000000000..8caae9bbac
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi
@@ -0,0 +1,92 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Name (OPAC, 0)
+
+OperationRegion(PWKE,PCI_Config,0x54,0x18)
+Field(PWKE,DWordAcc,NoLock,Preserve)
+{
+ , 8,
+ PMEE, 1, // PWR_CNTL_STS.PME_En
+ , 6,
+ PMES, 1, // PWR_CNTL_STS.PME_Sts
+ Offset (0x0E),
+ , 1,
+ PWUC, 10 // Port Wake Up Capability Mask
+}
+
+//
+// Indicate access to OperationRegions is enabled/disabled
+//
+Method (_REG, 2)
+{
+ // If OperationRegion ID = PCI_Config
+ //
+ If (LEqual (Arg0, 2))
+ {
+ // If access is enabled
+ //
+ If (LEqual(Arg1, 1))
+ {
+ // Set local flag
+ //
+ Store (One, OPAC)
+ }
+ Else
+ {
+ // Clear local flag
+ //
+ Store (One, OPAC)
+ }
+ }
+}
+
+//
+// Enable/disable ports on this controller to wake the system
+//
+Method (_PSW,1)
+{
+ If (Arg0)
+ {
+ Store (Ones,PWUC)
+ }
+ Else
+ {
+ Store (0,PWUC)
+ }
+}
+
+//
+// Initialization for this controller
+//
+Method (_INI, 0)
+{
+ // If access to OperationRegion is enabled
+ //
+ If (LEqual (OPAC, One))
+ {
+ Store (1, PMES) // clear PME status
+ Store (0, PMEE) // clear PME enable
+ }
+}
+
+// The CRB leaves the USB ports on in S3/S4 to allow
+// the ability to Wake from USB. Therefore, define
+// the below control methods to state D2 entry during
+// the given S-State.
+
+Method(_S3D,0)
+{
+ Return(2)
+}
+
+Method(_S4D,0)
+{
+ Return(2)
+}
+
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl
new file mode 100644
index 0000000000..8ae7c7b8be
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl
@@ -0,0 +1,17 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+///
+/// Gbe Ethernet ASL methods and structures
+///
+
+ //
+ // GPE bit 13 indicates wake from this device, can wakeup from S4 state
+ //
+ Method(_PRW, 0) {
+ Return(Package() {13, 4})
+ }
\ No newline at end of file
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi
new file mode 100644
index 0000000000..d62d5044b4
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi
@@ -0,0 +1,22 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Define bits in LPC bridge config space
+// (\_SB.PCI0.LPC0)
+//
+OperationRegion (LPCB, PCI_Config, 0x00, 0x100)
+Field (LPCB, DWordAcc, NoLock, Preserve)
+{
+ Offset (0xAC),
+ , 16,
+ XSMB, 1 // set when OS routes USB ports to xHCI in SmartAuto mode so next POST will know
+}
+
+#include "IrqLink.asl" // PCI routing control methods
+#include "Mother.asi" // Static motherboard device resource declaration
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi
new file mode 100644
index 0000000000..a74c9b9aae
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi
@@ -0,0 +1,807 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ OperationRegion (IDER,PCI_Config,0x40,0x20)
+ Field (IDER, AnyAcc, NoLock, Preserve)
+ {
+ PFT0 , 1 , // Drive 0 Fast Timing Bank (TIME0)
+ PIE0 , 1 , // Drive 0 IORDY Sample Point Enable (IE0)
+ PPE0 , 1 , // Drive 0 Prefetch/Posting Enable (PPE0)
+ PDE0 , 1 , // Drive 0 DMA Timing Enable (DTE0)
+ PFT1 , 1 , // Drive 1 Fast Timing Bank (TIME1)
+ PIE1 , 1 , // Drive 1 IORDY Sample Point Enable (IE1)
+ PPE1 , 1 , // Drive 1 Prefetch/Posting Enable (PPE1)
+ PDE1 , 1 , // Drive 1 DMA Timing Enable (DTE1)
+ PRT0 , 2 , // Drive 0 Recovery Time (RCT)
+ , 2 , // Reserved
+ PIP0 , 2 , // Drive 0 IORDY Sample Point (ISP)
+ PSIT , 1 , // Drive 1 Timing Register Enable (SITRE)
+ PIDE , 1 , // IDE Decode Enable (IDE)
+ offset (0x2) ,
+ SFT0 , 1 , // Drive 0 Fast Timing Bank (TIME0)
+ SIE0 , 1 , // Drive 0 IORDY Sample Point Enable (IE0)
+ SPE0 , 1 , // Drive 0 Prefetch/Posting Enable (PPE0)
+ SDE0 , 1 , // Drive 0 DMA Timing Enable (DTE0)
+ SFT1 , 1 , // Drive 1 Fast Timing Bank (TIME1)
+ SIE1 , 1 , // Drive 1 IORDY Sample Point Enable (IE1)
+ SPE1 , 1 , // Drive 1 Prefetch/Posting Enable (PPE1)
+ SDE1 , 1 , // Drive 1 DMA Timing Enable (DTE1)
+ SRT0 , 2 , // Drive 0 Recovery Time (RCT)
+ , 2 , // Reserved
+ SIP0 , 2 , // Drive 0 IORDY Sample Point (ISP)
+ SSIT , 1 , // Drive 1 Timing Register Enable (SITRE)
+ SIDE , 1 , // IDE Decode Enable (IDE)
+
+ PRT1 , 2 , // Drive 1 Recovery Time (RCT)
+ PIP1 , 2 , // Drive 1 IORDY Sample Point (ISP)
+ SRT1 , 2 , // Drive 1 Recovery Time (RCT)
+ SIP1 , 2 , // Drive 1 IORDY Sample Point (ISP)
+
+ offset (0x08) ,
+
+ UDM0 , 1 , // Primary Drive 0 Synchronous DMA Mode Enable
+ UDM1 , 1 , // Primary Drive 1 Synchronous DMA Mode Enable
+ UDM2 , 1 , // Secondary Drive 0 Synchronous DMA Mode Enable
+ UDM3 , 1 , // Secondary Drive 1 Synchronous DMA Mode Enable
+
+ offset (0x0A) ,
+
+ PCT0 , 2 , // Primary Drive 0 Cycle Time (PCT0)
+ , 2 , // Reserved
+ PCT1 , 2 , // Primary Drive 1 Cycle Time (PCT1)
+ , 2 , // Reserved
+ SCT0 , 2 , // Secondary Drive 0 Cycle Time (SCT0)
+ , 2 , // Reserved
+ SCT1 , 2 , // Secondary Drive 1 Cycle Time (SCT1)
+
+ offset (0x14) ,
+ PCB0 , 1 , // Primary Drive 0 Base Clock (PCB0)
+ PCB1 , 1 , // Primary Drive 0 Base Clock (PCB0)
+ SCB0 , 1 , // Secondary Drive 1 Base Clock (SCB0)
+ SCB1 , 1 , // Secondary Drive 1 Base Clock (SCB1)
+ PCCR , 2 , // Primary Channel Cable Reporting
+ SCCR , 2 , // Secondary Channel Cable Reporting
+ , 4 , // Reserved
+ PUM0 , 1 , // Primary Drive 0 UDMA 5 Supported
+ PUM1 , 1 , // Primary Drive 1 UDMA 5 Supported
+ SUM0 , 1 , // Secondary Drive 0 UDMA 5 Supported
+ SUM1 , 1 , // Secondary Drive 1 UDMA 5 Supported
+ PSIG , 2 , // PRIM_SIG_MODE
+ SSIG , 2 , // SEC_SIG_MODE
+ }
+
+ //
+ // Get PIO Timing
+ // Arg0 Fast PIO Timing
+ // Arg1 DMA Fast Timing
+ // Arg2 RCT Timing
+ // Arg3 ISP Timing
+ //
+
+ Method(GPIO,4)
+ {
+
+ If (LEqual (Or (Arg0, Arg1) , 0) ) {
+ //
+ // No PIO Timing and DMA Timing support
+ //
+ Return (0xFFFFFFFF)
+
+ } Else {
+ If (And ( LEqual (Arg0, 0) , LEqual (Arg1, 1) ) ) {
+ //
+ // Compatible PIO timing support
+ //
+ Return (900)
+ }
+ }
+
+ //
+ // Using ISP and RCT timing , PCI Clock = 33 Mhz , 30ns per clock
+ //
+ Return (Multiply(30,Subtract(9,Add(Arg2,Arg3))))
+ }
+ //
+ // Get DMA Timing
+ // Arg0 UDMA Supported
+ // Arg1 Ata100
+ // Arg2 Ata66/33
+ // Arg3 Cable report / SATA No mater this input
+ // Arg4 Cycle Timing
+ //
+ Method(GDMA,5)
+ {
+ //
+ // Ultra DMA 66 & 100 need 80 pin conductor
+ //
+ If (LEqual (Arg0, 1)) {
+ //
+ // Ultra DMA Support
+ //
+ If (LEqual (Arg1, 1)) {
+ //
+ // ATA100 80 pin conducter support , Ultra DMA 5 Support
+ //
+ If (LEqual (Arg4, 2)) {
+ Return (15)
+ }
+ Return (20)
+
+ }
+ If (LEqual (Arg2, 1)) {
+ //
+ // ATA66 80 pin conducter support , Base Clock 66Mhz , 15ns per clock
+ //
+ Return (Multiply(15,Subtract(4,Arg4)))
+ }
+ //
+ // Else Ultra DMA33Mhz Supported only,Base Clock 33Mhz , 30ns per clock
+ //
+ Return (Multiply(30,Subtract(4,Arg4)))
+ }
+ // Doesnt support DMA mode
+
+ Return (0xFFFFFFFE)
+ }
+ //
+ // Set Flag
+ // Arg0 IORDY for drive 0
+ // Arg1 Ultra DMA for drive 0
+ // Arg2 IORDY for drive 1
+ // Arg3 Ultra DMA for drive 1
+ // Arg4 indicates chipset can set timing independently for each drive
+ //
+ Method(SFLG, 5)
+ {
+ //
+ // The Chipset always support separate timing setting and always support IORDY
+ //
+ Store (0, Local0)
+ Or (Arg1 ,Local0,Local0)
+ Or (ShiftLeft (Arg0,1) ,Local0, Local0)
+ Or (ShiftLeft (Arg2,3) ,Local0, Local0)
+ Or (ShiftLeft (Arg3,2) ,Local0, Local0)
+ Or (ShiftLeft (Arg4,4) ,Local0, Local0)
+ Return (Local0)
+ }
+ //
+ // Set PIO Timing
+ // Arg0 Timing
+ // Arg1 ATA Device PIO Mode Supported Flag
+ // Arg2 ATA Device PIO Mode Supported Timing
+ //
+ // PIO/Mode Timing
+ // PIO0/Compatible 900 ns
+ // PIO2/SW2 240 ns
+ // PIO3/MW1 180 ns
+ // PIO4/MW2 120 ns
+ //
+
+ Method(SPIO , 3)
+ {
+ Name(PBUF, Buffer(5) { 0x00,0x00,0x00,0x00,0x00})
+ CreateByteField(PBUF, 0, RCT)
+ CreateByteField(PBUF, 1, ISP)
+ CreateByteField(PBUF, 2, FAST)
+ CreateByteField(PBUF, 3, DMAE)
+ CreateByteField(PBUF, 4, PIOT)
+ If (LOr (LEqual (Arg0, 0x0), LEqual (Arg0, 0x0FFFFFFFF)) ) {
+
+ Return (PBUF)
+ }
+ If (LGreater (Arg0, 240)) {
+ //
+ // Compatible timing
+ //
+ Store (1, DMAE) // PIO Mode 0
+ Store (0, PIOT) // Set to PIO Mode 0
+
+ } Else {
+ //
+ // Fast Timing Enable
+ //
+ Store (1, FAST)
+
+ If (And (Arg1, 0x002)) {
+ //
+ // ATA Device Supported PIO Mode Report
+ //
+ If (And (LEqual (Arg0, 120), And( Arg2 , 0x002) ) ) {
+ //
+ // Device support PIO Mode 4
+ //
+ Store (3, RCT) // RCT = 1 CLK
+ Store (2, ISP) // ISP = 3 CLK
+ Store (4, PIOT) // Set to PIO Mode 4
+ } Else {
+ If (And (LLessEqual (Arg0, 180), And( Arg2 , 0x001) ) ) {
+ //
+ // Device support PIO Mode 3
+ //
+ Store (1, RCT) // RCT = 3 CLK
+ Store (2, ISP) // ISP = 3 CLK
+ Store (3, PIOT) // Set to PIO Mode 3
+ } Else {
+ //
+ // PIO Mode 2
+ //
+ Store (0, RCT) // RCT = 4 CLK
+ Store (1, ISP) // ISP = 4 CLK
+ Store (2, PIOT) // Set to PIO Mode 2
+ }
+ }
+ }
+ }
+ Return (PBUF)
+ }
+ //
+ // Set DMA Timing
+ // Arg0 Timing
+ // Arg1 ATA Device PIO Mode Supported Flag
+ // Arg2 ATA Device PIO Mode Supported Timing
+ //
+ // UDMA/Mode Timing
+ // UDMA5 20 ns
+ // UDMA4 30 ns
+ // UDMA3 45 ns
+ // UDMA2 60 ns
+ // UDMA1 90 ns
+ // UDMA0 120 ns
+ //
+
+ Method(SDMA , 3)
+ {
+ Name(PBUF, Buffer(5) { 0x00,0x00,0x00,0x00})
+ CreateByteField(PBUF, 0, PCT)
+ CreateByteField(PBUF, 1, PCB)
+ CreateByteField(PBUF, 2, UDMT) // ATA 100 Support
+ CreateByteField(PBUF, 3, UDME) // Ultra DMA Enable
+ CreateByteField(PBUF, 4, DMAT)
+ If (LOr (LEqual (Arg0, 0x0), LEqual (Arg0, 0x0FFFFFFFF)) ) {
+
+ Return (PBUF)
+ }
+ If (LLessEqual (Arg0, 120)) {
+ //
+ // Ultra DMA Supported
+ //
+ If (And (Arg1, 0x004)) {
+ //
+ // ATA Device Supported UDMA Mode Report
+ //
+ Store (1, UDME)
+ If (And (LEqual (Arg0, 15), And( Arg2 , 0x0040) ) ) {
+ //
+ // Ultra DMA 6
+ //
+ Store (1, UDMT)
+ Store (1, PCB)
+ Store (2, PCT)
+ Store (6, DMAT) // Set to UDMA Mode 6
+ } Else {
+ If (And (LEqual (Arg0, 20), And( Arg2 , 0x0020) ) ) {
+ //
+ // Ultra DMA 5
+ //
+ Store (1, UDMT)
+ Store (1, PCB)
+ Store (1, PCT)
+ Store (5, DMAT) // Set to UDMA Mode 5
+ } Else {
+
+ If (And (LLessEqual (Arg0, 30), And( Arg2 , 0x00010) ) ) {
+ //
+ // Ultra DMA 4
+ //
+ Store (1, PCB)
+ Store (2, PCT)
+ Store (4, DMAT) // Set to UDMA Mode 4
+
+ } Else {
+
+ If (And (LLessEqual (Arg0, 45), And( Arg2 , 0x0008) ) ) {
+ //
+ // Ultra DMA 3
+ //
+ Store (1, PCB)
+ Store (1, PCT)
+ Store (3, DMAT) // Set to UDMA Mode 3
+
+ } Else {
+
+ If (And (LLessEqual (Arg0, 60), And( Arg2 , 0x0004) ) ) {
+ //
+ // Ultra DMA 2
+ //
+ Store (2, PCT)
+ Store (2, DMAT) // Set to UDMA Mode 2
+ } Else {
+
+ If (And (LLessEqual (Arg0, 90), And( Arg2 , 0x0002) ) ) {
+ //
+ // Ultra DMA 1
+ //
+ Store (1, PCT)
+ Store (1, DMAT) // Set to UDMA Mode 1
+ } Else {
+
+ If (And (LLessEqual (Arg0, 120), And( Arg2 , 0x0001) ) ) {
+ //
+ // Ultra DMA 0
+ //
+ Store (0, DMAT) // Set to UDMA Mode 0
+ }
+ }}}}}}
+ }
+ }
+ Return (PBUF)
+ }
+
+
+ //
+ // Primary ide channel
+ //
+ Device(PRID)
+ {
+ Name(_ADR,0)
+ Name(TDM0, 0) // Drive 0 Ultra DMA Type
+ Name(TPI0, 0) // Drive 0 PIO Type
+ Name(TDM1, 0) // Drive 1 Ultra DMA Type
+ Name(TPI1, 0) // Drive 1 PIO Type
+
+ Method(_GTM)
+ {
+ Name(PBUF, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00 })
+
+ CreateDwordField(PBUF, 0, PIO0)
+ CreateDwordField(PBUF, 4, DMA0)
+ CreateDwordField(PBUF, 8, PIO1)
+ CreateDwordField(PBUF, 12, DMA1)
+ CreateDwordField(PBUF, 16, FLAG)
+
+ Store ( GPIO (PFT0, PDE0, PRT0, PIP0 ), PIO0)
+ //
+ // Setting the Drive1 PIO Timing, check if we use the same timging for
+ // both Drive0 and Drive1, and if the Drive0 is attached, else use
+ // separate timing
+ //
+
+ If ( And (PSIT, 1) ) {
+ Store ( GPIO (PFT1, PDE1, PRT1, PIP1 ), PIO1)
+ } Else {
+ Store ( GPIO (PFT1, PDE1, PRT0, PIP0 ), PIO1)
+ }
+
+ If (LEqual (PIO0, 0xFFFFFFFF)) {
+ Store(PIO0, DMA0)
+ } Else {
+ Store ( GDMA(UDM0, PUM0, PCB0,And (PCCR ,0x1), PCT0) , DMA0)
+ If ( LGreater ( DMA0, PIO0)) {
+ Store(PIO0, DMA0)
+ }
+ }
+ If (LEqual (PIO1, 0xFFFFFFFF)) {
+ Store(PIO1, DMA1)
+ } Else {
+ Store ( GDMA(UDM1, PUM1, PCB1,And (PCCR ,0x2), PCT1) , DMA1)
+ If ( LGreater ( DMA1, PIO1)) {
+ Store(PIO1, DMA1)
+ }
+ }
+ Store (SFLG (PIE0, UDM0, PIE1, UDM1, 1), FLAG)
+
+ Return (PBUF)
+ }
+
+ Method(_STM,3)
+ {
+ CreateDwordField(Arg0, 0, PIO0)
+ CreateDwordField(Arg0, 4, DMA0)
+ CreateDwordField(Arg0, 8, PIO1)
+ CreateDwordField(Arg0, 12, DMA1)
+ CreateDwordField(Arg0, 16, FLAG)
+
+ //
+ // Device 0 Raw data
+ //
+ CreateWordField(Arg1, 106, RPS0) // word 53
+ CreateWordField(Arg1, 128, IOM0) // word 64
+ CreateWordField(Arg1, 176, DMM0) // Word 88
+
+ //
+ // Device 1 Raw data
+ //
+ CreateWordField(Arg2, 106, RPS1) // word 53
+ CreateWordField(Arg2, 128, IOM1) // word 64
+ CreateWordField(Arg2, 176, DMM1) // Word 88
+
+ Name(IOTM, Buffer(5) { 0x00,0x00,0x00,0x00})
+
+ CreateByteField(IOTM, 0, RCT)
+ CreateByteField(IOTM, 1, ISP)
+ CreateByteField(IOTM, 2, FAST)
+ CreateByteField(IOTM, 3, DMAE)
+ CreateByteField(IOTM, 4, TPIO) // PIO Type
+
+ Name(DMAT, Buffer(5) { 0x00,0x00,0x00,0x00})
+
+ CreateByteField(DMAT, 0, PCT)
+ CreateByteField(DMAT, 1, PCB)
+ CreateByteField(DMAT, 2, UDMT) // ATA 100 Support
+ CreateByteField(DMAT, 3, UDME) // Ultra DMA Enable
+ CreateByteField(DMAT, 4, TDMA) // UDMA Type
+
+ If (And (FLAG , 0x10)) {
+ Store (1, PSIT)
+ }
+
+ Store (SPIO (PIO0,RPS0,IOM0), IOTM)
+
+ If (Or (DMAE, FAST)) {
+ Store (RCT, PRT0)
+ Store (ISP, PIP0)
+ Store (FAST, PFT0)
+ Store (DMAE, PDE0)
+ Store (TPIO, TPI0)
+ }
+ Store (SPIO (PIO1,RPS1,IOM1), IOTM)
+
+ If (Or (DMAE, FAST)) {
+ Store (FAST, PFT1)
+ Store (DMAE, PDE1)
+ Store (TPIO, TPI1)
+ If (And (PSIT,1)) {
+ //
+ // Need set Drive 1 PIO Timing seperate
+ //
+ Store (RCT, PRT1)
+ Store (ISP, PIP1)
+ } Else {
+ Store (RCT, PRT0)
+ Store (ISP, PIP0)
+ }
+ }
+ If (And (FLAG , 0x01)) {
+ Store (SDMA (DMA0,RPS0,DMM0), DMAT)
+ Store (PCT , PCT0)
+ Store (PCB , PCB0)
+ Store (UDME, UDM0)
+ Store (UDMT, PUM0)
+ Store (TDMA, TDM0)
+ } Else {
+ Store (0, UDM0)
+ }
+
+ If (And (FLAG , 0x04)) {
+ Store (SDMA (DMA1,RPS1,DMM1), DMAT)
+ Store (PCT , PCT1)
+ Store (PCB , PCB1)
+ Store (UDME, UDM1)
+ Store (UDMT, PUM1)
+ Store (TDMA, TDM1)
+ } Else {
+ Store (0, UDM1)
+ }
+ //
+ // Check IORDY Support
+ //
+ If (And (FLAG , 0x2)) {
+ Store (1 , PIE0)
+ }
+ If (And (FLAG , 0x8)) {
+ Store (1 , PIE1)
+ }
+
+ }
+ Device(MAST)
+ {
+ Name(_ADR,0)
+ Method(_GTF)
+ {
+ //
+ // Set ATA Device to corresponding Mode
+ //
+ Name(ATA0, Buffer(14)
+ { 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF })
+
+ CreateByteField(ATA0,1,PIO0) // PIO0 = PIO Mode, Drive 0
+ CreateByteField(ATA0,8,DMA0) // DMA0 = DMA Mode, Drive 0
+
+
+ Store (TPI0, PIO0) // Type we Already get
+
+ Or (PIO0, 0x08 ,PIO0)
+
+ If ( And (UDM0, 1)) {
+ Store (TDM0, DMA0) // Ultra DMA
+ Or (DMA0, 0x40, DMA0)
+ } Else {
+ Store (TPI0, DMA0) // Use PIO Timing
+ If ( LNotEqual (DMA0, 0)) {
+ Subtract(DMA0, 2, DMA0)
+ }
+ Or (DMA0, 0x20, DMA0)
+ }
+ Return (ATA0)
+ }
+ }
+ Device(SLAV)
+ {
+ Name(_ADR,1)
+ Method(_GTF)
+ {
+ //
+ // Set ATA Device to corresponding Mode
+ //
+ Name(ATA1, Buffer(14)
+ { 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF })
+
+ CreateByteField(ATA1,1,PIO1) // PIO0 = PIO Mode, Drive 0
+ CreateByteField(ATA1,8,DMA1) // DMA0 = DMA Mode, Drive 0
+
+ Store (TPI1, PIO1) // Type we Already get
+
+ Or (PIO1, 0x08 ,PIO1)
+
+ If ( And (UDM1, 1)) {
+ Store (TDM1, DMA1) // Ultra DMA
+ Or (DMA1, 0x40, DMA1)
+ } Else {
+ Store (TPI1, DMA1) // Use PIO Timing
+ If ( LNotEqual (DMA1, 0)) {
+ Subtract(DMA1, 2, DMA1)
+ }
+ Or (DMA1, 0x20, DMA1)
+ }
+ Return(ATA1)
+ }
+ }
+ }
+ //
+ // Secondary SATA channel
+ //
+ Device(SECD)
+ {
+ Name(_ADR,1)
+ Name(TDM0, 0)
+ Name(TPI0, 0)
+ Name(TDM1, 0)
+ Name(TPI1, 0)
+
+ Name(DMT1, Buffer(5) { 0x00,0x00,0x00,0x00})
+ Name(DMT2, Buffer(5) { 0x00,0x00,0x00,0x00})
+ Name(POT1, Buffer(5) { 0x00,0x00,0x00,0x00})
+ Name(POT2, Buffer(5) { 0x00,0x00,0x00,0x00})
+
+ Name(STMI, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00 })
+
+ Method(_GTM)
+ {
+ Name(PBUF, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00 })
+
+ CreateDwordField(PBUF, 0, PIO0)
+ CreateDwordField(PBUF, 4, DMA0)
+ CreateDwordField(PBUF, 8, PIO1)
+ CreateDwordField(PBUF, 12, DMA1)
+ CreateDwordField(PBUF, 16, FLAG)
+
+ Store ( GPIO (SFT0, SDE0, SRT0, SIP0 ), PIO0)
+ //
+ // Setting the Drive1 PIO Timing, check if we use the same timging for
+ // both Drive0 and Drive1, and if the Drive0 is attached, else use
+ // separate timing
+ //
+ If ( And (SSIT, 1) ) {
+ Store ( GPIO (SFT1, SDE1, SRT1, SIP1 ), PIO1)
+ } Else {
+ Store ( GPIO (SFT1, SDE1, SRT0, SIP0 ), PIO1)
+ }
+
+ If (LEqual (PIO0, 0xFFFFFFFF)) {
+ Store(PIO0, DMA0)
+ } Else {
+ Store ( GDMA(UDM2, SUM0, SCB0,And (SCCR ,0x1), SCT0) , DMA0)
+ If ( LGreater ( DMA0, PIO0)) {
+ Store(PIO0, DMA0)
+ }
+ }
+
+ If (LEqual (PIO1, 0xFFFFFFFF)) {
+ Store(PIO1, DMA1)
+ } Else {
+ Store ( GDMA(UDM3, SUM1, SCB1,And (SCCR ,0x2), SCT1) , DMA1)
+ If ( LGreater ( DMA1, PIO1)) {
+ Store(PIO1, DMA1)
+ }
+ }
+
+ Store (SFLG (SIE0, UDM2, SIE1, UDM3, 1), FLAG)
+
+ Return (PBUF)
+ }
+ Method(_STM,3)
+ {
+ CreateDwordField(Arg0, 0, PIO0)
+ CreateDwordField(Arg0, 4, DMA0)
+ CreateDwordField(Arg0, 8, PIO1)
+ CreateDwordField(Arg0, 12, DMA1)
+ CreateDwordField(Arg0, 16, FLAG)
+
+ Store (Arg0, STMI)
+ //
+ // Device 0 Raw data
+ //
+ CreateWordField(Arg1, 106, RPS0) // word 53
+ CreateWordField(Arg1, 128, IOM0) // word 64
+ CreateWordField(Arg1, 176, DMM0) // Word 88
+
+ //
+ // Device 1 Raw data
+ //
+ CreateWordField(Arg2, 106, RPS1) // word 53
+ CreateWordField(Arg2, 128, IOM1) // word 64
+ CreateWordField(Arg2, 176, DMM1) // Word 88
+
+ Name(IOTM, Buffer(5) { 0x00,0x00,0x00,0x00})
+
+ CreateByteField(IOTM, 0, RCT)
+ CreateByteField(IOTM, 1, ISP)
+ CreateByteField(IOTM, 2, FAST)
+ CreateByteField(IOTM, 3, DMAE)
+ CreateByteField(IOTM, 4, TPIO) // PIO Type
+
+ Name(DMAT, Buffer(5) { 0x00,0x00,0x00,0x00})
+
+ CreateByteField(DMAT, 0, PCT)
+ CreateByteField(DMAT, 1, PCB)
+ CreateByteField(DMAT, 2, UDMT) // ATA 100 Support
+ CreateByteField(DMAT, 3, UDME) // Ultra DMA Enable
+ CreateByteField(DMAT, 4, TDMA) // UDMA Type
+
+ If (And (FLAG , 0x10)) {
+ Store (1, SSIT)
+ }
+
+ //
+ // Get Timing and Flag Setting
+ //
+ Store (SPIO (PIO0,RPS0,IOM0), IOTM)
+ //
+ // If no drive0 connect, do nothing to program Drive0 timing
+ //
+ If (Or (DMAE, FAST)) {
+ Store (RCT, SRT0)
+ Store (ISP, SIP0)
+ Store (FAST, SFT0)
+ Store (DMAE, SDE0)
+ Store (TPIO, TPI0)
+ }
+
+ Store (SPIO (PIO1,RPS1,IOM1), IOTM)
+
+ Store (IOTM,POT2)
+
+ If (Or (DMAE, FAST)) {
+ Store (FAST, SFT1)
+ Store (DMAE, SDE1)
+ Store (TPIO, TPI1)
+ If (And (SSIT,1)) {
+ //
+ // Need set Drive 1 PIO Timing separately
+ //
+ Store (RCT, SRT1)
+ Store (ISP, SIP1)
+ } Else {
+ Store (RCT, SRT0)
+ Store (ISP, SIP0)
+ }
+ }
+
+ If (And (FLAG , 0x01)) {
+ Store (SDMA (DMA0,RPS0,DMM0), DMAT)
+ Store (PCT , SCT0)
+ Store (PCB , SCB0)
+ Store (UDME , UDM2)
+ Store (UDMT , SUM0)
+ Store (TDMA, TDM0)
+ } Else {
+ Store (0, UDM2)
+ }
+ If (And (FLAG , 0x04)) {
+ Store (SDMA (DMA1,RPS1,DMM1), DMAT)
+ Store (PCT , SCT1)
+ Store (PCB , SCB1)
+ Store (UDME , UDM3)
+ Store (UDMT , SUM1)
+ Store (TDMA , TDM1)
+ } Else {
+ Store (0, UDM3)
+ }
+ //
+ // Check IORDY Support
+ //
+ If (And (FLAG , 0x2)) {
+ Store (1 , SIE0)
+ }
+ If (And (FLAG , 0x8)) {
+ Store (1 , SIE1)
+ }
+
+ }
+ Device(MAST)
+ {
+ Name(_ADR,0)
+ Method(_GTF)
+ {
+ //
+ // Set ATA Device to corresponding Mode
+ //
+ Name(ATA0, Buffer(14)
+ { 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF })
+
+ CreateByteField(ATA0,1,PIO0) // PIO0 = PIO Mode, Drive 0
+ CreateByteField(ATA0,8,DMA0) // DMA0 = DMA Mode, Drive 0
+
+ Store (TPI0, PIO0) // Type we Already get
+
+ Or (PIO0, 0x08 ,PIO0)
+
+ If ( And (UDM2, 1)) {
+ Store (TDM0, DMA0) // Ultra DMA
+ Or (DMA0, 0x40, DMA0)
+ } Else {
+ Store (TPI0, DMA0) // Use PIO Timing
+ If ( LNotEqual (DMA0, 0)) {
+ Subtract(DMA0, 2, DMA0)
+ }
+ Or (DMA0, 0x20, DMA0)
+ }
+ Return (ATA0)
+ }
+ }
+ Device(SLAV)
+ {
+ Name(_ADR,1)
+ Method(_GTF)
+ {
+ //
+ // Set ATA Device to corresponding Mode
+ //
+ Name(ATA1, Buffer(14)
+ { 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF })
+
+ CreateByteField(ATA1,1,PIO1) // PIO0 = PIO Mode, Drive 0
+ CreateByteField(ATA1,8,DMA1) // DMA0 = DMA Mode, Drive 0
+
+ Store (TPI1, PIO1) // Type we Already get
+
+ Or (PIO1, 0x08 ,PIO1)
+
+ If ( And (UDM3, 1)) {
+ Store (TDM1, DMA1) // Ultra DMA
+ Or (DMA1, 0x40, DMA1)
+ } Else {
+ Store (TPI1, DMA1) // Use PIO Timing
+ If ( LNotEqual (DMA1, 0)) {
+ Subtract(DMA1, 2, DMA1)
+ }
+ Or (DMA1, 0x20, DMA1)
+ }
+ Return(ATA1)
+ }
+ }
+ }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi
new file mode 100644
index 0000000000..d2563e0487
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi
@@ -0,0 +1,329 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Name (OPAC, Zero)
+Name (XRST, Zero)
+Name (XUSB, Zero)
+
+OperationRegion (XPRT, PCI_Config, 0x74, 0x6C)
+Field (XPRT, DWordAcc, NoLock, Preserve)
+{
+ , 8,
+ PMEE, 1, // PWR_CNTL_STS.PME_En
+ , 6,
+ PMES, 1, // PWR_CNTL_STS.PME_Sts
+ Offset (0x5C),
+ PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register.
+ PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register.
+ PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register.
+ PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register
+}
+
+Method (_PSW,1)
+{
+ If (Arg0)
+ {
+ Store (Ones,PMEE)
+ }
+ Else
+ {
+ Store (0,PMEE)
+ }
+}
+
+
+//
+// Indicate access to OperationRegions is enabled/disabled
+//
+Method (_REG, 2) {
+ //
+ // If OperationRegion ID = PCI_Config
+ //
+ If (LEqual (Arg0, 2)) {
+ //
+ // If access is enabled
+ //
+ If (LEqual(Arg1, 1)) {
+ //
+ // Set local flag
+ //
+ Store (One, OPAC)
+
+ } Else {
+ //
+ // Clear local flag
+ //
+ Store (One, OPAC)
+ }
+ }
+}
+
+//
+// Initialization for this controller
+//
+Method (_INI, 0) {
+ //
+ // If access to OperationRegion is enabled
+ //
+ If (LEqual (OPAC, One)) {
+ Store (1, PMES) // clear PME status
+ Store (0, PMEE) // clear PME enable
+ }
+}
+
+//
+// _OSC for xHCI
+// This method enables XHCI controller if available.
+//
+// Arguments:
+// Arg0 (Integer): Revision ID - should be set to 1
+//
+// Arg1 (Integer): Count of DWords in Arg3
+//
+// Arg2 (Buffer) : Capabilities Buffer
+// DWORD #0 (Status/Error):
+// Bit 0 - Query Support Flag
+// Bit 1 - Always clear(0)
+// Bit 2 - Always clear(0)
+// Bit 3 - Always clear(0)
+//
+// All others - reserved
+//
+// DWORD #1 (Supported):
+// Bit 0 - 1: Switch to xHCI
+//
+// All others - reserved
+//
+// DWORD #2 (Controlled):
+// Bit 0 - 1: Clear Smart Auto state (disable xHCI)
+//
+// All others - reserved
+//
+// Returns:
+// Capabilities Buffer:
+// DWORD #0 (Status):
+// Bit 0 - Reserved (not used)
+//
+// Bit 1 - _OSC failure. Platform Firmware was unable to process the request or query.
+// Capabilities bits may have been masked.
+//
+// Bit 2 - Unrecognized UUID. This bit is set to indicate that the platform firmware
+// does not recognize the UUID passed in _OSC Arg0.
+// Capabilities bits are preserved.
+//
+// Bit 3 - Unrecognized Revision. This bit is set to indicate that the platform firmware
+// does not recognize the Revision ID passed in via Arg1.
+// Capabilities bits beyond those comprehended by the firmware will be masked.
+//
+// Bit 4 - Capabilities Masked. This bit is set to indicate
+// that capabilities bits set by driver software
+// have been cleared by platform firmware.
+//
+// Bit 5 - 0: EHCI controller exposed to OS
+// 1: xHCI controller exposed to OS
+//
+// All others - reserved (return 0)
+//
+// DWORD #1 (Supported):
+// Bit 0 - 0: EHCI supported
+// 1: xHCI supported
+//
+// All others - reserved
+//
+// DWORD #2 (Controlled):
+//
+// All bits - reserved
+//
+
+Method (POSC, 3) {
+
+ Store (0x81, IO80)
+
+ //
+ // Create DWord fields from the Capabilities Buffer
+ //
+ CreateDWordField (Arg2, 0, CDW1) // CDW1 = DWORD that starts at offset 0 of Arg2
+ CreateDWordField (Arg2, 4, CDW2) // CDW2 = DWORD that starts at offset 4 of Arg2
+ CreateDWordField (Arg2, 8, CDW3) // CDW3 = DWORD that starts at offset 8 of Arg2
+
+ //
+ // Are we running a version of Windows that runs the Intel xHCI driver?
+ // i.e. Windows Server 2008 through Windows Server 2008 R2 & Windows 7
+ //
+ If (LAnd (LGreaterEqual (\_SB.OSYS, 9), LLessEqual (\_SB.OSYS, 12))) {
+ //
+ // Running Windows
+ // Check revision is >= 2
+ //
+ If (LLess (Arg0, 2)) {
+ //
+ // Set unknown revision bit
+ //
+ Or (CDW1, 8, CDW1)
+ Store (0x82, IO80)
+ }
+ } Else {
+ //
+ // If the Intel xHCI driver not calling,
+ // then it must be SVOS
+ If (LNotEqual (Arg0, 1)) {
+ //
+ // Set unknown revision bit
+ //
+ Or (CDW1, 8, CDW1)
+ Store (0x82, IO80)
+ }
+ }
+
+ //
+ // Set failure if xHCI is disabled by BIOS
+ //
+ If (LEqual (XHMD, 0)) {
+ Or (CDW1, 2, CDW1)
+ Store (0x83, IO80)
+ }
+
+ //
+ // If no error bits set
+ //
+ If (LEqual (And (CDW1, 0xE), 0)) {
+ //
+ // If not just querying support
+ //
+ If (LNot (And (CDW1, 1))) {
+ //
+ // If uninstaller calling
+ // to switch back to EHCI
+ //
+ If (And (CDW3, 1)) {
+ //
+ // Switch to EHCI
+ //
+ ESEL()
+ Store (0x85, IO80)
+
+ //
+ // And clear ACPINVS variable
+ // that is a copy of USB3.0 setup option
+ // so that we will not re-enable xHCI until
+ // the next reboot
+ //
+ Store (0, XHMD)
+ }
+
+ //
+ // Uninstaller not calling,
+ // OS wants to enable xHCI?
+ //
+ If (And (CDW2, 1)) {
+ //
+ // Switch to xHCI
+ //
+ XSEL(0)
+ Store (0x84, IO80)
+ } Else {
+ //
+ // Switch to EHCI
+ //
+ ESEL()
+ Store (0x85, IO80)
+ }
+ }
+ }
+
+ Return(Arg2)
+}
+
+//
+// Put all ports in XHCI mode
+//
+Method (XSEL, 1, Serialized) {
+ //
+ // If xHCI in auto or smart auto mode
+ // or Arg0 == 1
+ //
+ If ( LOr (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3)), Arg0) ) {
+ //
+ // If xHCI in smart auto mode
+ //
+ If (LEqual (XHMD, 3)) {
+ //
+ // Set B0:D31:F0 ACh[16] to indicate OS has routed ports to xHCI controller
+ //
+ Store (1, \_SB.PC00.LPC0.XSMB)
+ }
+
+ //
+ // Set flags so on Sx resume, we'll know OS has previously
+ // routed ports to xHCI
+ //
+ Store (1, XUSB)
+ Store (1, XRST) // Backup XUSB, cause it might lost in iRST G3 or DeepSx
+
+ //
+ // Enable selected SS ports, route corresponding HS ports to xHCI
+ //
+ Store (0, Local0)
+ And (PR3, 0xFFFFFFC0, Local0)
+ Or (Local0, PR3M, PR3)
+ Store (0, Local0)
+ And (PR2, 0xFFFF8000, Local0)
+ Or (Local0, PR2M, PR2)
+ }
+}
+
+//
+// Put all ports in EHCI mode
+//
+Method (ESEL, 0, Serialized) {
+ //
+ // xHCI in auto or smart auto mode
+ //
+ If (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3))) {
+ //
+ // Disable all SS ports, route all HS ports to EHCI
+ //
+ And (PR3, 0xFFFFFFC0, PR3)
+ And (PR2, 0xFFFF8000, PR2)
+
+ //
+ // Mark as not routed.
+ //
+ Store (0, XUSB)
+ Store (0, XRST)
+ }
+}
+
+Method (XWAK, 0, Serialized) {
+ //
+ // If ports were routed to xHCI before sleep
+ //
+ If (LOr (LEqual (XUSB, 1), LEqual (XRST, 1))) {
+ //
+ // Restore back to xHCI, ignore XHMD
+ //
+ XSEL(1)
+
+ //
+ // And tell OS to re-enumerate xHCI
+ //
+ Notify (\_SB.PC00.XHCI, 0x00)
+ }
+}
+
+//
+// Report what D state the controller is in
+// when the system changes to S3 and S4
+//
+Method(_S3D, 0, NotSerialized) {
+ Return(2)
+}
+
+Method(_S4D, 0, NotSerialized) {
+ Return(2)
+}
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi
new file mode 100644
index 0000000000..6fb2cb589d
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi
@@ -0,0 +1,312 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+// Return the proximity domain/node # that this bus is on
+// With this info OSPM will know what memory and I/O resources
+// are under the same IOH
+//
+Name(_PXM, 0)
+
+#define RESOURCE_CHUNK1_OFF 0
+#define RESOURCE_CHUNK2_OFF 16 //(RESOURCE_CHUNK1_OFF + 16)
+#define RESOURCE_CHUNK3_OFF 24 //(RESOURCE_CHUNK2_OFF + 8)
+#define RESOURCE_CHUNK4_OFF 40 //(RESOURCE_CHUNK3_OFF + 16)
+#define RESOURCE_CHUNK5_OFF 56 //(RESOURCE_CHUNK4_OFF + 16)
+#define RESOURCE_CHUNK6_OFF 82 //(RESOURCE_CHUNK5_OFF + 26)
+#define RESOURCE_CHUNK7_OFF 108 //(RESOURCE_CHUNK6_OFF + 26)
+
+#define PciResourceStart Local0
+#define PciResourceLen Local1
+
+Name(PBRS, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x0000, // Max
+ 0x0000, // Translation
+ 0x0000,,, // Range Length = Max-Min+1
+ PB00
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ IO( //Consumed resource (CF8-CFF)
+ Decode16,
+ 0x0cf8,
+ 0xcf8,
+ 1,
+ 8
+ )
+
+ //RESOURCE_CHUNK3_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x0cf7, // Max
+ 0x0000, // Translation
+ 0x0cf8 // Range Length
+ )
+
+ //RESOURCE_CHUNK4_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x00, // Granularity
+ 0x0000, // Min
+ 0x0000, // Max
+ 0x00, // Translation
+ 0x0000,,, // Range Length
+ PI01
+ )
+
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x000a0000, // Min
+ 0x000bffff, // Max
+ 0x00000000, // Translation
+ 0x00020000 // Range Length
+ )
+
+ //RESOURCE_CHUNK6_OFF
+ DWORDMEMORY( // descriptor for Shadow RAM
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Min (calculated dynamically)
+ 0x00000000, // Max (calculated dynamically)
+ 0x00000000, // Translation
+ 0x00000000,,, // Range Length (calculated dynamically)
+ SDRM
+ )
+
+ //RESOURCE_TPM
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0xFED40000, // Min (calculated dynamically)
+ 0xFEDFFFFF, // Max = 4GB - 1MB (fwh + fwh alias...)
+ 0x00000000, // Translation
+ 0x000C0000 // Range Length (calculated dynamically)
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00, // Granularity
+ 0x00000000, // Min (calculated dynamically)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias...)
+ 0x00, // Translation
+ 0x00000000,,, // Range Length (calculated dynamically)
+ PM01
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00, // Granularity
+ 0x00000000000, // Min (calculated dynamically)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias...)
+ 0x00, // Translation
+ 0x00000000000,,, // Range Length (calculated dynamically)
+ PM02
+ )
+}) // end of PBRS Buffer
+
+
+Method(_CRS, 0x0, NotSerialized)
+{
+ //calculate Shadow RAM
+ EROM()
+
+ // Fix up Bus Number Resources
+ CreateWordField(PBRS, ^PB00._MIN, PBMN)
+ Store(BBI0, PBMN)
+ CreateWordField(PBRS, ^PB00._MAX, PBMX) // (MAX bus decoded - 1, assuming Uncore Bus is MAX decoded BUS Number)
+ Store(BBL0, PBMX)
+ CreateWordField(PBRS, ^PB00._LEN, PBLN)
+ Subtract(PBMX, PBMN, PBLN)
+ Add(1, PBLN, PBLN)
+
+ // Fix up 16-bit IO resources
+ CreateWordField(PBRS, ^PI01._MIN, PIMN)
+ Store(IOBA, PIMN)
+ CreateWordField(PBRS, ^PI01._MAX, PIMX)
+ Store(IOLA, PIMX)
+ CreateWordField(PBRS, ^PI01._LEN, PILN)
+ Subtract(PIMX, PIMN, PILN)
+ Add(1, PILN, PILN)
+
+ // Fix up 32-bit Memory resources
+ CreateDWordField(PBRS, ^PM01._MIN, PMMN)
+ Store(MMB0, PMMN)
+ CreateDWordField(PBRS, ^PM01._MAX, PMMX)
+ Store(MML0, PMMX)
+ CreateDWordField(PBRS, ^PM01._LEN, PMLN)
+ Subtract(PMMX, PMMN, PMLN)
+ Add(1, PMLN, PMLN)
+
+ // Fix up 64-bit Memory resources
+// If(LAnd(MMH0, LGreater(OSFL, 8))) {
+ CreateQWordField(PBRS, ^PM02._MIN, P2MN)
+ Store(HMB0, P2MN)
+ CreateQWordField(PBRS, ^PM02._MAX, P2MX)
+ Store(HML0, P2MX)
+ CreateQWordField(PBRS, ^PM02._LEN, P2LN)
+ Subtract(P2MX, P2MN, P2LN)
+ Add(1, P2LN, P2LN)
+// }
+
+ Return(PBRS)
+}
+
+Method(_STA,0) {
+ If (NPB0) {
+ Return(0x0F)
+ }
+ Return(0x00)
+}
+
+OperationRegion(TMEM, PCI_Config, 0x52, 0x3)
+Field(TMEM, ByteAcc, NoLock, Preserve) {
+ DIM0, 4,
+ DIM1, 4,
+ , 8,
+ DIM2, 4
+}
+
+Name(MTBL, Package(0x10) {
+ 0x0,
+ 0x20,
+ 0x20,
+ 0x30,
+ 0x40,
+ 0x40,
+ 0x60,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0xc0,
+ 0x100,
+ 0x100,
+ 0x100,
+ 0x200
+})
+
+
+OperationRegion(PAMX, PCI_Config, 0x90, 0x7)
+Field(PAMX, ByteAcc, NoLock, Preserve) {
+ , 4,
+ BSEG, 4,
+ PAMS, 48
+}
+
+Name(ERNG, Package(0xd) {
+ 0xc0000,
+ 0xc4000,
+ 0xc8000,
+ 0xcc000,
+ 0xd0000,
+ 0xd4000,
+ 0xd8000,
+ 0xdc000,
+ 0xe0000,
+ 0xe4000,
+ 0xe8000,
+ 0xec000,
+ 0xf0000
+})
+
+Name(PAMB, Buffer(0x7) {
+})
+
+Method(EROM, 0x0, NotSerialized) {
+ CreateDWordField(PBRS, 0x5c, RMIN)
+ CreateDWordField(PBRS, 0x60, RMAX)
+ CreateDWordField(PBRS, 0x68, RLEN)
+ CreateByteField(PAMB, 0x6, BREG)
+ Store(PAMS, PAMB)
+ Store(BSEG, BREG)
+ Store(0x0, RMIN)
+ Store(0x0, RMAX)
+ Store(0x0, RLEN)
+ Store(0x0, Local0)
+ While(LLess(Local0, 0xd)) {
+ ShiftRight(Local0, 0x1, Local1)
+ Store(DerefOf(Index(PAMB, Local1, )), Local2)
+ If(And(Local0, 0x1, )) {
+ ShiftRight(Local2, 0x4, Local2)
+ }
+ And(Local2, 0x3, Local2)
+ If(RMIN) {
+ If(Local2) {
+ Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
+ If(LEqual(RMAX, 0xf3fff)) {
+ Store(0xfffff, RMAX)
+ }
+ Subtract(RMAX, RMIN, RLEN)
+ Increment(RLEN)
+ } Else {
+ Store(0xc, Local0)
+ }
+ } Else {
+ If(Local2) {
+ Store(DerefOf(Index(ERNG, Local0, )), RMIN)
+ Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
+ If(LEqual(RMAX, 0xf3fff)) {
+ Store(0xfffff, RMAX)
+ }
+ Subtract(RMAX, RMIN, RLEN)
+ Increment(RLEN)
+ } Else {
+ }
+ }
+ Increment(Local0)
+ }
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi
new file mode 100644
index 0000000000..fe7c2b8753
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi
@@ -0,0 +1,455 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+OperationRegion (PRR0, PCI_Config, 0x00, 0x100)
+Field (PRR0, AnyAcc, NoLock, Preserve) {
+ Offset(0x60),
+ PIRA, 8,
+ PIRB, 8,
+ PIRC, 8,
+ PIRD, 8,
+ Offset(0x68),
+ PIRE, 8,
+ PIRF, 8,
+ PIRG, 8,
+ PIRH, 8
+}
+
+Device (LNKA) { // PCI IRQ link A
+ Name (_HID,EISAID("PNP0C0F"))
+ //Name(_UID, 1)
+ Method (_STA,0,NotSerialized) {
+ If(And(PIRA, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRA, 0x80, PIRA)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And(PIRA, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And (PIRA,0x0F),IRQW) // Save in buffer
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)){
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRA)
+ } // End of _SRS Method
+}
+
+Device(LNKB) { // PCI IRQ link B
+ Name (_HID,EISAID("PNP0C0F"))
+ //Name(_UID, 2)
+ Method (_STA,0,NotSerialized) {
+ If (And (PIRB, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRB, 0x80,PIRB)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name(BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRB, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And (PIRB,0x0F),IRQW) // Save in buffer
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name (_PRS,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual(IRQW,Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store (Local0, PIRB)
+ } // End of _SRS Method
+}
+
+Device(LNKC) { // PCI IRQ link C
+ Name(_HID, EISAID("PNP0C0F"))
+ //Name(_UID, 3)
+
+ Method (_STA,0,NotSerialized) {
+ If (And (PIRC, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS, 0, NotSerialized) {
+ Or (PIRC, 0x80, PIRC)
+ }
+
+ Method (_CRS, 0, Serialized) {
+ Name (BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRC, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And (PIRC,0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRC)
+ } // End of _SRS Method
+}
+
+Device (LNKD) { // PCI IRQ link D
+ Name (_HID,EISAID ("PNP0C0F"))
+
+ //Name(_UID, 4)
+
+ Method (_STA, 0, NotSerialized) {
+ If (And (PIRD, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS, 0, NotSerialized) {
+ Or(PIRD, 0x80,PIRD)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name (BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRD, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0, And (PIRD,0x0F), IRQW)
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW, Local0)// Set IRQ
+ If (LNotEqual (IRQW, Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store(Local0, PIRD)
+ } // End of _SRS Method
+}
+
+Device(LNKE) { // PCI IRQ link E
+ Name(_HID,EISAID("PNP0C0F"))
+
+ //Name(_UID, 5)
+
+ Method (_STA,0,NotSerialized) {
+ If (And (PIRE, 0x80)) {
+ Return(0x9)
+ } Else {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRE, 0x80, PIRE)
+ }
+
+ Method (_CRS, 0, Serialized) {
+ Name (BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRE, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One, Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0, And (PIRE,0x0F), IRQW)
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name(_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW, Local0) // Set IRQ
+ If (LNotEqual (IRQW, Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store (Local0, PIRE)
+ } // End of _SRS Method
+}
+
+Device(LNKF) { // PCI IRQ link F
+ Name (_HID,EISAID("PNP0C0F"))
+
+ //Name(_UID, 6)
+
+ Method (_STA,0,Serialized) {
+ If (And (PIRF, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRB, 0x80, PIRF)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name(BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRF, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One, Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0, And (PIRF, 0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name(_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store (Local0, PIRF)
+ } // End of _SRS Method
+}
+
+Device(LNKG) { // PCI IRQ link G
+ Name(_HID,EISAID("PNP0C0F"))
+ //Name(_UID, 7)
+ Method(_STA,0,NotSerialized) {
+ If (And (PIRG, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS, 0, NotSerialized) {
+ Or(PIRG, 0x80,PIRG)
+ }
+
+ Method (_CRS,0,Serialized){
+ Name(BUF0,ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And(PIRG, 0x80)) {
+ Store(Zero, Local0)
+ } Else {
+ Store(One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And(PIRG,0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRG)
+ } // End of _SRS Method
+}
+
+Device(LNKH) { // PCI IRQ link H
+ Name (_HID,EISAID("PNP0C0F"))
+
+ //Name(_UID, 8)
+
+ Method (_STA,0,Serialized) {
+ If (And(PIRH, 0x80)) {
+ Return(0x9)
+ } Else {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or(PIRH, 0x80,PIRH)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name(BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRH, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And(PIRH,0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name(_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW,Local0)// Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRH)
+ }
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi
new file mode 100644
index 0000000000..ced2b3ecd1
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi
@@ -0,0 +1,644 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ //
+ // BIOS parameter
+ // The address will be fixed dynamically during boot.
+ // Will be updated by ACPI platform driver as "FIX8"
+ //
+ OperationRegion (MCTL, SystemMemory, 0x38584946, 0x04)
+ Field (MCTL, ByteAcc, NoLock, Preserve) {
+ , 3,
+ HGPE, 1,
+ , 7,
+ , 8,
+ , 8
+ }
+
+//
+// No longer needed, See PPA4
+//
+// OperationRegion (PSTS, PCI_Config, 0xB0, 0x04)
+// Field (PSTS, ByteAcc, NoLock, Preserve) {
+// , 16,
+// PMES, 1, // PME Status bit 16
+// PMEP, 1, //PME Pending bit 17
+// , 14
+// }
+
+
+ Method (_INI, 0, NotSerialized) {
+ Store (0x01, HGPE) //enable GPE message generation for ACPI hotplug support
+ }
+
+ Name(_HPP, Package(){0x08, 0x40, 1, 0})
+
+ //
+ // begin hotplug code
+ //
+ Name(SHPC, 0x40) // Slot Hot-plug Capable
+
+ Name(SPDS, 0x040) // Slot Presence Detect State
+
+ Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on
+ Name(CCOM, 0x010) // Command Complete
+ Name(SPDC, 0x08) // Slot Presence Detect Changes
+ Name(MRLC, 0x04) // Slot MRL Changed
+ Name(SPFD, 0x02) // Slot Power Fault Detected
+ Name(SABP, 0x01) // Slot Attention Button Pressed
+
+ Name(SPOF, 0x10) // Slot Power Off
+ Name(SPON, 0x0F) // Slot Power On Mask
+
+ Name(ALMK, 0x1C) // Slot Atten. LED Mask
+ Name(ALON, 0x01) // Slot Atten. LED On
+ Name(ALBL, 0x02) // Slot Atten LED Blink
+ Name(ALOF, 0x03) // Slot Atten LED Off
+
+ Name(PLMK, 0x13) // Slot Pwr. LED Mask
+ Name(PLON, 0x04) // Slot Pwr. LED On
+ Name(PLBL, 0x08) // Slot Pwr. LED Blink
+ Name(PLOF, 0x0C) // Slot Pwr. LED Off
+
+ //;*************************************
+ //; Bit 3 = Presence Detect Event
+ //; Bit 2 = MRL Sensor Event
+ //; Bit 1 = PWR Fault Event
+ //; Bit 0 = Attention Button Event
+ //;*************************************
+ Name(HPEV, 0xF) // Possible interrupt events (all)
+
+ //;************************************************************************;
+ //;
+ //; PCIe Link Control Register A0-A1h
+ //;
+ //; Bit - 4 - Link disable.
+ //;
+ //;************************************************************************;
+//
+// No longer needed, see PPA4
+//
+// OperationRegion(PPA0, PCI_Config, 0xA0, 0x02)
+// Field(PPA0,ByteAcc,NoLock,Preserve) {
+// ,4,
+// LDIS,1, // Link Disable bit4.
+// ,11,
+// }
+
+ //;************************************************************************;
+ //;
+ //; PCIe Slot Capabilities Register A4-A7h
+ //; Bit - 31-5 - Not used
+ //; Bit - 4 - Power Indicator Present.
+ //; Bit - 3 - Attention Indicator Present.
+ //; Bit - 2 - MRL Sensor Present.
+ //; Bit - 1 - Power Controller Present.
+ //; Bit - 0 - Attention Button Present.
+ //;
+ //; PCIe Slot control Register A8-A9h
+ //;
+ //; Bit - 10 - PWR Control Disable
+ //; Bit - 9:8 - Attn Indicator
+ //; Bit - 7:6 - PWR Indicator
+ //; Bit - 5 - Hot-Plug Interrupt Event Enable
+ //; Bit - 4 - Command Complete Interrupt enable
+ //; Bit - 3 - Presence Detect Changed Interrupt enable
+ //; Bit - 2 - MRL Sensor Changed Interrupt enable
+ //; Bit - 1 - PwrFault Detect Interrupt enable
+ //; Bit - 0 - Attention Button Pressed Interrupt Enable
+ //;
+ //; PCIe Slot Status Registers AA-ADh
+ //;
+ //; Bit - 6 - Presence Detect State.
+ //; Bit - 5 - MRL Sensor State.
+ //; Bit - 4 - Command Completed.
+ //;
+ //; RWC Status Bits
+ //;
+ //; Bit - 3 - Presence Detect Changed.
+ //; Bit - 2 - MRL Sensor Changed.
+ //; Bit - 1 - Power Fault Detected.
+ //; Bit - 0 - Attention Button Pressed.
+ //;************************************************************************;
+ OperationRegion(PPA4, PCI_Config, 0x00, 0x100)
+ Field(PPA4,ByteAcc,NoLock,Preserve) {
+ Offset (0xA0), // from PPA0 OpRegion
+ ,4,
+ LDIS,1, // Link Disable bit4.
+ ,11,
+ Offset(0xA4), // A4-A7h PCI Slot Capabilities Register
+ ATBP,1, // Attention Button Present
+ ,1, // Skip Power Controller Present
+ MRSP,1, // MRL Sensor Present
+ ATIP,1, // Attention Indicator Present
+ PWIP,1, // Power Indicator Present
+ ,14,
+ PSNM,13, // Physical Slot Number
+ Offset(0xA8), // PCIE Slot Control Register
+ ABIE,1, // Attention Button Pressed Interrupt Enable
+ PFIE,1, // Power Fault Detected Interrupt Enable
+ MSIE,1, // MRL Sensor Changed Interrupt Enable
+ PDIE,1, // Presence Detect Changed Interrupt Enable.
+ CCIE,1, // Command Complete Interrupt Enable.
+ HPIE,1, // Hot-plug Interrupt Enable.
+ SCTL,5, // Attn/Power indicator and Power controller.
+ ,5, // reserved
+ Offset(0xAA), // PCIE Slot Status Register
+ SSTS,7, // The status bits in Slot Status Reg
+ ,1,
+ Offset (0xB0), // from PSTS OpRegion
+ , 16,
+ PMES, 1, // PME Status bit 16
+ PMEP, 1, // PME Pending bit 17
+ , 14
+ }
+
+ //
+ // These Methods replace the bit field definitions in PPA8
+ // that were bit fields within SCTL
+ //
+ Method (ATID, 0) {
+ Return (And (SCTL, 0x03))
+ }
+
+ Method (PWID, 0) {
+ Return (ShiftRight (And (SCTL, 0x0C), 2))
+ }
+
+ Method (PWCC, 0) {
+ Return (ShiftRight (And (SCTL, 0x10), 4))
+ }
+
+ //
+ // These methods replace the bit fields definitions in PPA8
+ // that were bit fields within SSTS
+ //
+ Method (ABPS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x01, SSTS)
+ }
+ Return (And (SSTS, 0x01))
+ }
+
+ Method (PFDS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x02, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x02), 1))
+ }
+
+ Method (MSCS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x04, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x04), 2))
+ }
+
+ Method (PDCS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x08, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x08), 3))
+ }
+
+ Method (CMCS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x10, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x10), 4))
+ }
+
+ Method (MSSC, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x20, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x20), 5))
+ }
+
+ Method (PRDS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x40, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x40), 6))
+ }
+
+
+// OperationRegion(PPA8, PCI_Config, 0x00, 0x0ff)
+// Field(PPA8,ByteAcc,NoLock,Preserve) {
+// Offset(0xA8), // PCIE Slot Control Register
+// ,6,
+// ATID,2, // Attention Indicator Control.
+// PWID,2, // Power Indicator Control.
+// PWCC,1, // Power Controller Control.
+// ,5,
+// Offset(0xAA), // RWC status
+// ABPS,1, // Attention Button Pressed Status (RWC)
+// PFDS,1, // Power Fault Detect Status (RWC)
+// MSCS,1, // MRL Sensor Changed Status
+// PDCS,1, // Presence Detect Changed Status
+// CMCS,1, // Command Complete Status
+// MSSC,1, // MRL Sensor State
+// PRDS,1, // Presence Detect State
+// ,1,
+// }
+
+ //;************************************************************************;
+ //; This OSHP (Operating System Hot Plug) method is provided for each HPC
+ //; which is controlled by ACPI. This method disables ACPI access to the
+ //; HPC and restores the normal System Interrupt and Wakeup Signal
+ //; connection.
+ //;************************************************************************;
+ Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express HP code.
+ Store(0, SSTS) // Clear any status
+ Store(0x0, HGPE) // Disable GPE generation
+ }
+
+ //;************************************************************************;
+ //; Hot Plug Controller Command Method
+ //;
+ //; Input: Arg0 - Command to issue
+ //;
+ //;************************************************************************;
+ Method(HPCC,1) {
+ Store(SCTL, Local0) // get current command state
+ Store(0, Local1) // reset the timeout value
+ If(LNotEqual(Arg0, Local0)) { // see if state is different
+ Store(Arg0, SCTL) // Update the Slot Control
+ While(LAnd (LNot(CMCS(0)), LNotEqual(100, Local1))) { // spin while CMD complete bit is not set,
+ // check for timeout to avoid dead loop
+ Store(0xFB, IO80)
+ Sleep(2) // allow processor time slice
+ Add(Local1, 2, Local1)
+ }
+ CMCS(1) // Clear the command complete status
+ }
+ }
+
+ //;************************************************************************;
+ //; Attention Indicator Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = ON
+ //; 2 = Blink
+ //; 3 = OFF
+ //;************************************************************************;
+ Method(ATCM,1) {
+ Store(SCTL, Local0) // Get Slot Control
+ And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
+ If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?"
+ Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON"
+ }
+ If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?"
+ Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK"
+ }
+ If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?"
+ Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; Power Indicator Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = ON
+ //; 2 = Blink
+ //; 3 = OFF
+ //;************************************************************************;
+ Method(PWCM,1){
+ Store(SCTL, Local0) // Get Slot Control
+ And(Local0, PLMK, Local0) // Mask the Power Indicator Bits
+ If(LEqual(Arg0, 0x1)){ // Power indicator "ON?"
+ Or(Local0, PLON, Local0) // Set the Power Indicator to "ON"
+ }
+ If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?"
+ Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK"
+ }
+ If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?"
+ Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; Power Slot Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = Slot Power ON
+ //; 2 = Slot Power Off
+ //;************************************************************************;
+ Method(PWSL,1){
+ Store(SCTL, Local0) // Get Slot Control
+ If(Arg0){ // Power Slot "ON" Arg0 = 1
+ And(Local0, SPON, Local0) // Turns the Power "ON"
+ } Else { // Power Slot "OFF"
+ Or(Local0, SPOF, Local0) // Turns the Power "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; _OST Methods to indicate that the device Eject/insert request is
+ //; pending, OS could not complete it
+ //;
+ //; Input: Arg0 - Value used in Notify to OS
+ //; 0x00 - card insert
+ //; 0x03 - card eject
+ //; Arg1 - status of Notify
+ //; 0 - success
+ //; 0x80 - Ejection not supported by OSPM
+ //; 0x81 - Device in use
+ //; 0x82 - Device Busy
+ //; 0x84 - Ejection in progress-pending
+ //;************************************************************************;
+ Method(_OST,3,Serialized) {
+ Switch(And(Arg0,0xFF)) { // Mask to retain low byte
+ Case(0x03) { // Ejection Request
+ Switch(ToInteger(Arg1)) {
+ Case(Package() {0x80, 0x81, 0x82, 0x83}) {
+ //
+ // Ejection Failure for some reason
+ //
+ If (Lnot(PWCC())) { // if slot is powered
+ PWCM(0x1) // Set PowerIndicator to ON
+ Store(0x1,ABIE) // Set AttnBtn Interrupt ON
+ }
+ }
+ }
+ }
+ }
+ } // End _OST
+
+ //;************************************************************************;
+ //; Eject Control Methods to indicate that the device is hot-ejectable and
+ //; should "eject" the device.
+ //;
+ //;
+ //;************************************************************************;
+ Method(EJ0L){
+ Store(0xFF, IO80)
+ Store(SCTL, Local0) // Get IIO Port Control state
+ if( LNot( LEqual( ATID(), 1))) { // Check if Attention LED is not solid "ON"
+ And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
+ Or(Local0, ALBL, Local0) // Set the Attention Indicator to blink
+ }
+ HPCC(Local0) // issue command
+
+ Store(SCTL, Local0) // Get IIO Port Control state
+ Or(Local0, SPOF, Local0) // Set the Power Controller Control to Power Off
+ HPCC(Local0)
+
+ Store(SCTL, Local0) // Get IIO Port Control state
+ Or(Local0, PLOF, Local0) // Set the Power Indicator to Off.
+ HPCC(Local0)
+
+ Store(SCTL, Local0) // Get IIO Port Control state
+ Or(Local0, ALOF, Local0) // Set the Attntion LED to Off.
+ HPCC(Local0)
+
+ } // End of EJ0L
+
+ //;************************************************************************;
+ //; PM_PME Wake Handler for All Slots
+ //;
+ //; Input: Arg0 - Slot Numnber
+ //;
+ //;************************************************************************;
+ Method(PMEH,1){ // Handler for PCI-E PM_PME Wake Event/Interupt (GPI xxh)
+ If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
+ If(ABPS(0)) {
+ Store (Arg0, IO80) // Send slot number to Port 80
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ }
+ }
+ Return (0xff) // Indicate that this controller did not interrupt
+ } // End of Method PMEH
+
+ //;************************************************************************;
+ //; Hot-Plug Handler for All Slots.
+ //;
+ //; Input: Arg0 - Slot Number
+ //;
+ //;************************************************************************;
+ Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/Interupt (GPI xxh)
+ Store(0xFE, IO80)
+ Sleep(100)
+ Store(0,CCIE) // Disable command interrupt
+ If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
+ Store(0xFD, IO80)
+ Sleep(10)
+ Store (Arg0, IO80) // Send slot number to Port 80
+ Sleep(10)
+ Store(PPXH(), Local0) // Call Hot plug Interrupt Handler
+ Return(Local0) // Return PPXH information
+ }
+ Else{
+ Return (0xff) // Indicate that this controller did not interrupt
+ }
+ Store(0xFC, IO80)
+ Sleep(10)
+ } // End of Method HPEH
+
+ //;************************************************************************;
+ //; Interrut Event Handler
+ //;
+ //;
+ //;************************************************************************;
+ Method(PPXH){ // Hot plug Interrupt Handler
+ //
+ // Check for the Atention Button Press, Slot Empty/Presence, Power Controller Control.
+ //
+ Sleep(200) // HW Workaround for AttentionButton Status to stabilise
+ If(ABPS(0)) { // Check if Attention Button Pressed
+ If(LNot(PRDS(0))) { // See if nothing installed (no card in slot)
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ PWSL(0x0) // make sure Power is Off
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ //
+ // Check for MRL here and set attn indicator accordingly
+ //
+ If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ } else { // Standby power is off - MRL open
+ ATCM(0x3) // set attention indicator "OFF"
+ }
+ Store(0x0, ABIE) // set Attention Button Interrupt to disable
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ Return(0xff) // Attn Button pressed without card in slot. Do nothing
+ }
+ //
+ // Card is present in slot so....
+ //
+ Store(0x0, ABIE) // set Attention Button Interrupt to disable
+ // Attn Btn Interrupt has to be enabled only after an insert oprn
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ //
+ // Check for MRL here - only if SPWR is OFF blink AttnInd and retun 0xff
+ //
+ //If(LNot(LEqual(MSSC()),MRLS))) { // Standby power is off
+ // PWSL(0x0) // make sure Power is Off
+ // PWCM(0x3) // Set Power Indicator to "OFF"
+ // ATCM(0x2) // Set Attention Indicator to "BLINK"
+ // Return(0xff) // Attn Button pressed with card in slot, but MRL open. Do nothing
+ //}
+ //Card Present, if StandbyPwr is ON proceed as below with Eject Sequence
+ If(PWCC()) { // Slot not Powered
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ Return(0xff) // Attn Button pressed with card in slot, MRL closed, Slot not powered. Do nothing
+ } Else { // See if Slot is already Powered
+ PWCM(0x2) // Set power Indicator to BLINK
+ Sleep(600) // Wait 100ms
+ Store(600, Local0) // set 5 second accumulator to 0
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ While(LNot(ABPS(0))) { // check for someone pressing Attention
+ Sleep(200) // Wait 200ms
+ Add(Local0, 200, Local0)
+ If(LEqual(5000, Local0)) { // heck if 5sec has passed without pressing attnetion btn
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ Return (0x3) // continue with Eject request
+ }
+ }
+ PWCM(0x1) // Set power Indicator baCK "ON"
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Store(0x1, ABIE) // set Attention Button Interrupt to enable
+ Return (0xff) // do nothing and abort
+ }
+ } // End if for the Attention Button Hot Plug Interrupt.
+
+ If(PFDS(0)) { // Check if Power Fault Detected
+ PFDS(1) // Clear the Power Fault Status
+ PWSL(0x0) // set Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0x03) // Eject request.
+ } // End if for the Power Fault Interrupt.
+
+ If(MSCS(0)) { // Check interrupt caused by the MRL Sensor
+ MSCS(1) // Clear the MRL Status
+ If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed
+ If(PRDS(0)) { // Card is Present
+
+ ATCM(0x3) // Set Attention Indicator to off
+ PWCM(0x2) // Set Power Indicator to Blink
+ Sleep(600) // Wait 100ms
+ Store(600, Local0) // set 5 second accumulator to 0
+ ABPS(1) // Clear the interrupt status
+ While(LNot(ABPS(0))) { // check for someone pressing Attention
+ Sleep(200) // Wait 200ms
+ Add(Local0, 200, Local0)
+ If(LEqual(5000, Local0)) { // Check if 5 sec elapsed
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ ATCM(0x3) // set attention indicator "OFF"
+ Store(0x0, LDIS) // Enable the Link associated with PCI-E port
+ PWSL(0x1) // Power the Slot
+ Sleep(500) // Wait for .5 Sec for the Power to Stabilize.
+ // Check for the Power Fault Detection
+ If(LNot(PFDS(0))) { // No Power Fault
+ PWCM(0x1) // Set Power Indicator to "ON"
+ // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slot Clock (GPIO16)
+ // Notify the OS to load the Driver for the card
+ Store(0x00, Local1)
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ } Else { // Power Fault present
+ PWSL(0x0) // set Slot Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Slot Clock (GPIO16)
+ Store(0x03, Local1) // Eject request.
+ } // End if for the Slot Power Fault
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Return(Local1)
+ }
+ }
+ //
+ // someone pressed Attention Button
+ //
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(02) // Set Attention Indicator to "BLINK"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0xff) // leave it off
+ // End of Insert sequence
+ }
+ //MRL is closed, Card is not present
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(02) // Set Attention Indicator to "BLINK"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0xff) // leave it off
+ } Else { // MRL is open i.e Stdby power is turned off
+ If(PRDS(0)) { //card present MRL switched off
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ If(Lnot(PWCC())) { // If slot is powered
+ // This event is not supported and someone has opened the MRL and dumped the power
+ // on the slot with possible pending transactions. This could hose the OS.
+ // Try to Notify the OS to unload the drivers.
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0x03) // Eject request.
+ } Else { // Slot not powered, MRL is opened, card still in slot - Eject not fully complete
+ Return(0xFF)
+ }
+ }
+ //no card present and Stdby power switched off, turn AI off
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ Return(0xff) // leave it off
+ } // End of MRL switch open/close state
+ } // End of MRL Sensor State Change
+
+ If(PDCS(0)) { // Check if Presence Detect Changed Status
+ PDCS(1) // Clear the Presence Detect Changed Status
+ If(LNot(PRDS(0))) { // Slot is Empty
+ PWSL(0x0) // Set Slot Power "OFF"
+ PWCM(0x3) // set power indicator to "OFF"
+ If(LEqual(MSSC(0),MRLS)) { // If Standby power is on
+ ATCM(0x2) // Set Attention Indicator to "Blink"
+ } else {
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ }
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0xFF) // Do nothing
+ } Else { // Slot Card is inserted
+ // Irrespective of MRL state, do the following
+ Store(0x0, LDIS) // Enable the Link associated with PCI-E port
+ PWSL(0x1) // Set Slot Power ON
+ Sleep(500) // Wait for .5 Sec for the Power to Stabilize.
+ If(LNot(PFDS(0))) { // No Power Fault
+ PWCM(0x1) // Set Power Indicator to "ON"
+ Store(0x00, Local1)
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ } Else { // Power Fault present
+ PWSL(0x0) // set Slot Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Store(0x03, Local1) // Eject request.
+ } // End if for the Slot Power Fault
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Return(Local1)
+ }
+ } // End if for the Presence Detect Changed Hot Plug Interrupt.
+ Return(0xff) // should not get here, but do device check if it does.
+ } // End of method PP5H
+ //
+ // End of hotplug code
+ //
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi
new file mode 100644
index 0000000000..34feaa8137
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi
@@ -0,0 +1,14 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ Method(SNUM, 0, Serialized) {
+ Store(PSNM, Local0)
+ Return(Local0)
+ }
+
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi
new file mode 100644
index 0000000000..c990898e87
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi
@@ -0,0 +1,16 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ Method(SNUM, 0, Serialized) {
+ Store(PSNM, Local0)
+ Return(Local0)
+ }
+
+ Method(_SUN, 0) {
+ Return(SNUM)
+ } // Slot User Number
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi
new file mode 100644
index 0000000000..51c919f5e5
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi
@@ -0,0 +1,355 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "MaxSocket.h"
+
+ Scope(\) {
+
+ //
+ // \SG00, SG01,... SG07 are defined to contain Segment # for Segment/socket 0, 1, ....
+ //
+ // Create _SEG for each segment/socket
+ //
+
+ //
+ // Debug method for use under BITS
+ // Example: Set SG01 to 5 SSEG(1,5)
+ //
+ Method(SSEG, 2) {
+ If (LEqual(Arg0, 0) ) { Store (Arg1, SG00) }
+ If (LEqual(Arg0, 1) ) { Store (Arg1, SG01) }
+ If (LEqual(Arg0, 2) ) { Store (Arg1, SG02) }
+ If (LEqual(Arg0, 3) ) { Store (Arg1, SG03) }
+ }
+
+
+// ------------------------------------------------------
+// Socket 0 PC00 - PC05 share the same segment number SG00
+// ------------------------------------------------------
+
+ Scope(\_SB.PC00) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+ Scope(\_SB.PC01) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+ Scope(\_SB.PC02) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+ Scope(\_SB.PC03) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+ Scope(\_SB.PC04) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+ Scope(\_SB.PC05) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+// ------------------------------------------------------
+// Socket 1 PC06 - PC11 share the same segment number SG01
+// ------------------------------------------------------
+
+ Scope(\_SB.PC06) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+ Scope(\_SB.PC07) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+ Scope(\_SB.PC08) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+ Scope(\_SB.PC09) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+ Scope(\_SB.PC10) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+ Scope(\_SB.PC11) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+// ------------------------------------------------------
+// Socket 2 PC12 - PC17 share the same segment number SG02
+// ------------------------------------------------------
+
+ Scope(\_SB.PC12) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+ Scope(\_SB.PC13) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+ Scope(\_SB.PC14) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+ Scope(\_SB.PC15) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+ Scope(\_SB.PC16) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+ Scope(\_SB.PC17) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+
+// ------------------------------------------------------
+// Socket 3 PC18 - PC23 share the same segment number SG03
+// ------------------------------------------------------
+
+ Scope(\_SB.PC18) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+ Scope(\_SB.PC19) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+ Scope(\_SB.PC20) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+ Scope(\_SB.PC21) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+ Scope(\_SB.PC22) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+ Scope(\_SB.PC23) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+#if MAX_SOCKET > 4
+
+// ------------------------------------------------------
+// Socket 4 PC24 - PC29 share the same segment number SG03
+// ------------------------------------------------------
+
+ Scope(\_SB.PC24) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+ Scope(\_SB.PC25) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+ Scope(\_SB.PC26) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+ Scope(\_SB.PC27) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+ Scope(\_SB.PC28) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+ Scope(\_SB.PC29) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+// ------------------------------------------------------
+// Socket 5 PC30 - PC35 share the same segment number SG03
+// ------------------------------------------------------
+
+ Scope(\_SB.PC30) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+ Scope(\_SB.PC31) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+ Scope(\_SB.PC32) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+ Scope(\_SB.PC33) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+ Scope(\_SB.PC34) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+ Scope(\_SB.PC35) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+// ------------------------------------------------------
+// Socket 6 PC36 - PC41 share the same segment number SG03
+// ------------------------------------------------------
+
+ Scope(\_SB.PC36) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+ Scope(\_SB.PC37) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+ Scope(\_SB.PC38) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+ Scope(\_SB.PC39) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+ Scope(\_SB.PC40) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+ Scope(\_SB.PC41) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+// ------------------------------------------------------
+// Socket 7 PC42 - PC47 share the same segment number SG03
+// ------------------------------------------------------
+
+ Scope(\_SB.PC42) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+
+ Scope(\_SB.PC43) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+
+ Scope(\_SB.PC44) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+
+ Scope(\_SB.PC45) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+
+ Scope(\_SB.PC46) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+
+ Scope(\_SB.PC47) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+#endif
+
+} // End Scope(\)
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
new file mode 100644
index 0000000000..40cc31b86a
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
@@ -0,0 +1,79 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+// Interrupt specific registers
+include("Itss.asl")
+//
+// Original file line: 163
+//
+
+Method(ADBG,1,Serialized)
+{
+ Return(0)
+}
+
+//
+// Original file line: 1460
+//
+Scope (\)
+{
+ //
+ // Global Name, returns current Interrupt controller mode;
+ // updated from _PIC control method
+ //
+
+ //
+ // Procedure: GPRW
+ //
+ // Description: Generic Wake up Control Method ("Big brother")
+ // to detect the Max Sleep State available in ASL Name scope
+ // and Return the Package compatible with _PRW format.
+ // Input: Arg0 = bit offset within GPE register space device event will be triggered to.
+ // Arg1 = Max Sleep state, device can resume the System from.
+ // If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System.
+ // Output: _PRW package
+ //
+ Name(PRWP, Package(){Zero, Zero}) // _PRW Package
+
+ Method(GPRW, 2)
+ {
+ Store(Arg0, Index(PRWP, 0)) // copy GPE#
+ //
+ // SS1-SS4 - enabled in BIOS Setup Sleep states
+ //
+ Store(ShiftLeft(SS1,1),Local0) // S1 ?
+ Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ?
+ Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ?
+ Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ?
+ //
+ // Local0 has a bit mask of enabled Sx(1 based)
+ // bit mask of enabled in BIOS Setup Sleep states(1 based)
+ //
+ If(And(ShiftLeft(1, Arg1), Local0))
+ {
+ //
+ // Requested wake up value (Arg1) is present in Sx list of available Sleep states
+ //
+ Store(Arg1, Index(PRWP, 1)) // copy Sx#
+ }
+ Else
+ {
+ //
+ // Not available -> match Wake up value to the higher Sx state
+ //
+ ShiftRight(Local0, 1, Local0)
+ // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x
+ // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx
+ // } Else { // ??? Win2k / XP
+ FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx
+ // }
+ }
+
+ Return(PRWP)
+ }
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi
new file mode 100644
index 0000000000..1f3087a7b3
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi
@@ -0,0 +1,78 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+// General Purpose Event
+#include "MaxSocket.h"
+
+Scope (\_GPE) {
+
+ //
+ // ME HECI2 SCI handler
+ // Note: This SCI from HECI2 is routed to ICH9 over the DMI and it
+ // sets the DMISCI status bit in TCO block. From there it is routed
+ // to bit6 GPE0 status register.
+ //
+ OperationRegion (TCOS, SystemIO, 0x464, 2) // ICH_ACPI_BASE_ADDRESS + TCO_BASE + R_TCO1_STS
+ Field (TCOS, ByteAcc, NoLock, WriteAsZeros) {
+ Offset (0x1),
+ , 1,
+ DSCI, 1,
+ }
+
+ Method(NTFI, 2){
+ If(And(Arg0, 0x01)){
+ Notify(\_SB.PC06, Arg1)
+ Notify(\_SB.PC07, Arg1)
+ Notify(\_SB.PC08, Arg1)
+ Notify(\_SB.PC09, Arg1)
+ Notify(\_SB.PC10, Arg1)
+ Notify(\_SB.PC11, Arg1)
+ }
+ If(And(Arg0, 0x02)){
+ Notify(\_SB.PC12, Arg1)
+ Notify(\_SB.PC13, Arg1)
+ Notify(\_SB.PC14, Arg1)
+ Notify(\_SB.PC15, Arg1)
+ Notify(\_SB.PC16, Arg1)
+ Notify(\_SB.PC17, Arg1)
+ }
+ If(And(Arg0, 0x04)){
+ Notify(\_SB.PC18, Arg1)
+ Notify(\_SB.PC19, Arg1)
+ Notify(\_SB.PC20, Arg1)
+ Notify(\_SB.PC21, Arg1)
+ Notify(\_SB.PC22, Arg1)
+ Notify(\_SB.PC23, Arg1)
+ }
+ } //End Method NTFI
+
+ // Tell OS to run thru the new status of this device (Software SCI generated from SMM for all Hot plug events)
+ Method (_L62, 0x0, NotSerialized) {
+ if(LEqual(SCI0, 3)) { // Device ejection (Invoked with _EJ0 method called)
+ Store (0, SCI0)
+ } else { // Device check (OS can still reject online request based on resources and capability)
+ NTFI (IIOP, 0)
+ Store (0, MEBC)
+ Store (0, CPHP)
+ Store (0, IIOP)
+ }
+ Store (0, SGPC)
+ Store (1, SGPS)
+
+ }
+
+ // PME supported for Slots, use GPE 9 for PME
+ // Hot plug on all slots for now, change later.
+ // Slot numbers on silk screen might be different than the port number, currently use port numbers.
+ //
+ // IIO PCI_E Slot Hotplug GPE Event
+ //
+ Method (_L61, 0, NotSerialized) {
+ #include "IioPcieHotPlugGpeHandler.asl"
+ }// end of _L01 GPE Method
+
+}// end of _GPE scope.
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi
new file mode 100644
index 0000000000..2cbe3aa5cc
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi
@@ -0,0 +1,9 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ // Eject device if SCK1 is removed.
+ Name(_EJD,"\\_SB.SCK1") // Dependent on SCK1
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi
new file mode 100644
index 0000000000..4a89bb99d6
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi
@@ -0,0 +1,9 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ // Eject device if SCK2 is removed.
+ Name(_EJD,"\\_SB.SCK2") // Dependent on SCK2
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi
new file mode 100644
index 0000000000..8cbaeffeb5
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi
@@ -0,0 +1,9 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ // Eject device if SCK3 is removed.
+ Name(_EJD,"\\_SB.SCK3") // Dependent on SCK3
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi
new file mode 100644
index 0000000000..a5a447d037
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi
@@ -0,0 +1,33 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ Name (PRU0, Package() {
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }
+ })
+
+ Name (ARU0, Package() {
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 }
+ })
+
+
+ Device (UNC0) {
+ Name (_UID, "UNCORE0")
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PRU0)
+ }
+ Return (ARU0)
+ }
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi
new file mode 100644
index 0000000000..a86aaa7b3f
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi
@@ -0,0 +1,175 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ Name (PRU1, Package() {
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (ARU1, Package() {
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+
+ Package() { 0x0011FFFF, 0, 0, 16 },
+ Package() { 0x0011FFFF, 1, 0, 17 },
+ Package() { 0x0011FFFF, 2, 0, 18 },
+ Package() { 0x0011FFFF, 3, 0, 19 },
+
+ Package() { 0x0014FFFF, 0, 0, 16 },
+ Package() { 0x0014FFFF, 1, 0, 17 },
+ Package() { 0x0014FFFF, 2, 0, 18 },
+ Package() { 0x0014FFFF, 3, 0, 19 },
+
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ Package() { 0x001DFFFF, 3, 0, 19 },
+
+ Package() { 0x001EFFFF, 0, 0, 16 },
+ Package() { 0x001EFFFF, 1, 0, 17 },
+ Package() { 0x001EFFFF, 2, 0, 18 },
+ Package() { 0x001EFFFF, 3, 0, 19 },
+
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ Package() { 0x001FFFFF, 1, 0, 17 },
+ Package() { 0x001FFFFF, 2, 0, 18 },
+ Package() { 0x001FFFFF, 3, 0, 19 },
+ })
+
+ //
+ // Devices 8 - 31 on PStack
+ //
+ Device (UNC1) {
+ Name (_UID, "UNCORE1")
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PRU1)
+ }
+ Return (ARU1)
+ }
+ }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi
new file mode 100644
index 0000000000..dc7453c294
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi
@@ -0,0 +1,125 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ Name (PRU2, Package() {
+ //
+ // PCIe2 PortA/NTB
+ //
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ })
+
+ Name (ARU2, Package() {
+ //
+ // PCIe2 PortA/NTB
+ //
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+
+
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+
+ })
+
+ //
+ // Devices 8 - 31 on each stack
+ //
+ Device (UNC2) {
+ Name (_UID, "UNCORE2")
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PRU2)
+ }
+ Return (ARU2)
+ }
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi
new file mode 100644
index 0000000000..f59e04539b
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi
@@ -0,0 +1,98 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ Name (PRU3, Package() {
+
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+
+ Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ })
+
+ Name (ARU3, Package() {
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+
+ Package() { 0x0012FFFF, 0, 0, 16 },
+ Package() { 0x0012FFFF, 1, 0, 17 },
+ Package() { 0x0012FFFF, 2, 0, 18 },
+ Package() { 0x0012FFFF, 3, 0, 19 },
+
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ })
+
+ //
+ // Devices 8 - 31 on each stack
+ //
+ Device (UNC3) {
+ Name (_UID, "UNCORE3")
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PRU3)
+ }
+ Return (ARU3)
+ }
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl
new file mode 100644
index 0000000000..254806cbc8
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl
@@ -0,0 +1,189 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+DefinitionBlock ("WFPPlatform.asl","DSDT",2,"INTEL","PLATWFP ",3)
+{
+
+ #include "CommonPlatform.asi"
+ #include "PlatformPciTree_WFP.asi"
+ #include "AMLUPD.asl"
+ #include "DSDT.ASL"
+ #include "Pch.asl" //This is in another package (PchPkg)
+ #include "Platform.asl"
+ #include "PlatformGpe.asi"
+ #include "PcieSeg.asi"
+
+ Scope (\_SB.PC00.XHCI.RHUB) {
+
+
+
+ //
+ // Method for creating generic _PLD buffers
+ // _PLD contains lots of data, but for purpose of internal validation we care only about
+ // ports' visibility and pairing (this requires group position)
+ // so these are the only 2 configurable parameters (User Visible, Group Position)
+ //
+ Method(GPLD, 2, Serialized) {
+ Name(PCKG, Package() { Buffer(0x10) {} } )
+ CreateField(DerefOf(Index(PCKG,0)), 0, 7, REV)
+ Store(1,REV)
+ CreateField(DerefOf(Index(PCKG,0)), 64, 1, VISI)
+ Store(Arg0, VISI)
+ CreateField(DerefOf(Index(PCKG,0)), 87, 8, GPOS)
+ Store(Arg1, GPOS)
+
+
+ return (PCKG)
+ }
+
+ //
+ // Method for creating generic _UPC buffers
+ // Similar to _PLD, for internal testing we only care about 1 parameter (port connectable)
+ //
+ Method(GUPC, 1, Serialized) {
+ Name(PCKG, Package(4) { 0, 0xFF, 0, 0 } )
+ Store(Arg0,Index(PCKG,0))
+
+
+ return (PCKG)
+ }
+
+
+
+ } //end scope RHUB
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS01) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,1)) } //Rear Panel A [CONN27] - Upper - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS02) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,2)) } //Rear Panel A [CONN27] - Center - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS03) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,3)) } //Rear Panel A [CONN27] - Bottom - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS04) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,4)) } //Internal A1 [CONN9] - Right - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS05) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,5)) } //Front Panel [CONN20] - Right - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS06) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,6)) } //Front Panel [CONN20] - Left - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS07) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,7)) } //Internal Type A3 [CONN4] - ? - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS08) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,8)) } //Internal Type A3 [CONN4] - ? - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS09) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,9)) } //Jacksonville [CONN22] - Bottom - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS10) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,10)) } //Usb daughter card [CONN14] - ? - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS11) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(0,11)) } //Jacksonville [CONN22] - Center - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS12) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(0,12)) } //Usb daughter card [CONN14] - ? - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS13) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,13)) } //Internal A1 [CONN4] - Left - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS14) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,14)) } //Usb daughter card [CONN14] - ? - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.USR1) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) }
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.USR2) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) }
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS01) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,1)) } //Rear Panel A [CONN27] - Upper - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS02) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,2)) } //Rear Panel A [CONN27] - Center - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS03) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,3)) } //Rear Panel A [CONN27] - Bottom - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS04) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,4)) } //Internal A1 [CONN9] - Right - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS05) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,5)) } //Front Panel [CONN20] - Right - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS06) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,6)) } //Front Panel [CONN20] - Left - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS07) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) } //N/A
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS08) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) } //N/A
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS09) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) } //N/A
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS10) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) } //N/A
+ }
+
+} // end of DSDT
--
2.27.0.windows.1
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