[edk2-devel] [edk2-platforms] [PATCH V1 14/18] PurleyOpenBoardPkg: Add MtOlympus build files
Nate DeSimone
nathaniel.l.desimone at intel.com
Tue May 11 09:48:22 UTC 2021
Cc: Chasel Chiu <chasel.chiu at intel.com>
Cc: Mike Kinney <michael.d.kinney at intel.com>
Cc: Isaac Oram <isaac.w.oram at intel.com>
Cc: Mohamed Abbas <mohamed.abbas at intel.com>
Cc: Michael Kubacki <michael.kubacki at microsoft.com>
Cc: Zachary Bobroff <zacharyb at ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad at ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
---
.../BoardMtOlympus/GitEdk2MinMtOlympus.bat | 74 +++
.../BoardMtOlympus/OpenBoardPkg.dsc | 221 +++++++
.../BoardMtOlympus/OpenBoardPkg.fdf | 589 ++++++++++++++++++
.../BoardMtOlympus/PlatformPkgBuildOption.dsc | 81 +++
.../BoardMtOlympus/PlatformPkgConfig.dsc | 58 ++
.../BoardMtOlympus/PlatformPkgPcd.dsc | 389 ++++++++++++
.../PurleyOpenBoardPkg/BoardMtOlympus/bld.bat | 138 ++++
.../BoardMtOlympus/build_board.py | 177 ++++++
.../BoardMtOlympus/build_config.cfg | 32 +
.../BoardMtOlympus/logo.txt | 11 +
.../BoardMtOlympus/postbuild.bat | 95 +++
.../BoardMtOlympus/prebuild.bat | 197 ++++++
Platform/Intel/build.cfg | 1 +
13 files changed, 2063 insertions(+)
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgBuildOption.dsc
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgConfig.dsc
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_board.py
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat
new file mode 100644
index 0000000000..85ce5beaf8
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat
@@ -0,0 +1,74 @@
+ at REM @file
+ at REM
+ at REM Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+ at REM SPDX-License-Identifier: BSD-2-Clause-Patent
+ at REM
+
+ at echo off
+
+pushd ..\..\..\..\..\
+
+ at REM Set WORKSPACE environment.
+set WORKSPACE=%cd%
+echo.
+echo Set WORKSPACE as: %WORKSPACE%
+echo.
+
+ at REM Check whether Git has been installed and been added to system path.
+git --help >nul 2>nul
+if %ERRORLEVEL% NEQ 0 (
+ echo.
+ echo The 'git' command is not recognized.
+ echo Please make sure that Git is installed and has been added to system path.
+ echo.
+ goto :EOF
+)
+
+ at REM Create the Conf directory under WORKSPACE
+if not exist %WORKSPACE%\Conf (
+ mkdir Conf
+)
+
+ at REM Set other environments.
+ at REM Basic Rule:
+ at REM Platform override Silicon override Core
+ at REM Source override Binary
+
+set PACKAGES_PATH=%WORKSPACE%\edk2-platforms\Platform\Intel;%WORKSPACE%\edk2-platforms\Silicon\Intel;%WORKSPACE%\edk2-platforms\Features\Intel;%WORKSPACE%\edk2-platforms\Features\Intel\Debugging;%WORKSPACE%\edk2-platforms\Features\Intel\Network;%WORKSPACE%\edk2-platforms\Features\Intel\OutOfBandManagement;%WORKSPACE%\edk2-platforms\Features\Intel\PowerManagement;%WORKSPACE%\edk2-platforms\Features\Intel\SystemInformation;%WORKSPACE%\edk2-platforms\Features\Intel\UserInterface;%WORKSPACE%\edk2-non-osi\Silicon\Intel;%WORKSPACE%\edk2;%WORKSPACE%
+
+set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32
+
+ at if not defined PYTHON_HOME (
+ @if exist C:\Python27 (
+ set PYTHON_HOME=C:\Python27
+ )
+)
+
+set EDK_SETUP_OPTION=
+ at rem if python is installed, disable the binary base tools.
+if defined PYTHON_HOME (
+ set EDK_TOOLS_BIN=
+ set EDK_SETUP_OPTION=Rebuild
+)
+pushd %WORKSPACE%\edk2
+call edksetup.bat %EDK_SETUP_OPTION%
+popd
+
+set openssl_path=%WORKSPACE%
+
+popd
+
+goto :EOF
+
+:Help
+echo.
+echo Usage:
+echo GitEdk2.bat [-w Workspace_Directory] (optional) [-b Branch_Name] (optional)
+echo.
+echo -w A absolute/relative path to be the workspace.
+echo Default value is the current directory.
+echo.
+echo -b The branch name of the repository. Currently, only master, udk2015,
+echo trunk (same as master) and bp13 (same as udk2015) are supported.
+echo Default value is master.
+echo.
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc
new file mode 100644
index 0000000000..98e02f35e7
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc
@@ -0,0 +1,221 @@
+## @file
+# The main build description file for the MtOlympus board.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ DEFINE PLATFORM_PACKAGE = MinPlatformPkg
+ DEFINE PLATFORM_SI_PACKAGE = PurleyRefreshSiliconPkg
+ DEFINE PLATFORM_SI_BIN_PACKAGE = PurleySiliconBinPkg
+ DEFINE PLATFORM_BOARD_PACKAGE = PurleyOpenBoardPkg
+ DEFINE BOARD = BoardMtOlympus
+ DEFINE PROJECT = $(PLATFORM_BOARD_PACKAGE)/$(BOARD)
+ DEFINE PEI_ARCH = IA32
+ DEFINE DXE_ARCH = X64
+
+ PLATFORM_NAME = PurleyOpenBoardPkg
+ PLATFORM_GUID = D7EAF54D-C9B9-4075-89F0-71943DBCFA61
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(PROJECT)
+ SUPPORTED_ARCHITECTURES = IA32|X64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = $(PROJECT)/OpenBoardPkg.fdf
+
+ FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
+
+ #
+ # Platform On/Off features are defined here
+ #
+ !include $(PROJECT)/PlatformPkgConfig.dsc
+
+ #
+ # Include PCD configuration for this board.
+ #
+ !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
+
+ !include PlatformPkgPcd.dsc
+ !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
+
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+# Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
+
+[DefaultStores]
+ 0|STANDARD # UEFI Standard default 0|STANDARD is reserved.
+ 1|MANUFACTURING # UEFI Manufacturing default 1|MANUFACTURING is reserved.
+
+################################################################################
+#
+# Includes section - other DSC file contents included for this board build.
+#
+################################################################################
+
+#######################################
+# Library Includes
+#######################################
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc
+
+#######################################
+# Component Includes
+#######################################
+
+[Components.$(PEI_ARCH)]
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc
+
+[Components.$(DXE_ARCH)]
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc
+
+#######################################
+# Build Option Includes
+#######################################
+!include $(PROJECT)/PlatformPkgBuildOption.dsc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+!if gPlatformTokenSpaceGuid.PcdFastBoot == FALSE
+ PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
+!else
+ PlatformBootManagerLib|$(PLATFORM_BOARD_PACKAGE)/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
+!endif
+
+ ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+
+ CompressLib|$(PLATFORM_PACKAGE)/Library/CompressLib/CompressLib.inf
+
+ PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
+ AslUpdateLib|$(PLATFORM_PACKAGE)/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
+
+ #
+ # Board
+ #
+ SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf
+ PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+ BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
+
+[LibraryClasses.IA32]
+!if $(TARGET) == DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
+!endif
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
+ ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+
+[LibraryClasses.X64]
+ BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
+!if $(TARGET) == DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf
+!endif
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLib.inf
+ BoardBootManagerLib|BoardModulePkg/Library/BoardBootManagerLib/BoardBootManagerLib.inf
+
+[LibraryClasses.X64.DXE_SMM_DRIVER]
+!if $(TARGET) == DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
+!endif
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointLib.inf
+
+[Components.IA32]
+
+ $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempMemorySilicon.inf
+ $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.inf
+ $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.inf
+
+ $(PLATFORM_BOARD_PACKAGE)/Policy/SystemBoard/SystemBoardPei.inf
+
+ $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ <LibraryClasses>
+ BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+ }
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
+ <LibraryClasses>
+ BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
+ }
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
+
+[Components.X64]
+
+ $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(TARGET)/FvLateSilicon.inf
+ $(PLATFORM_SI_BIN_PACKAGE)/Microcode/Microcode.inf
+
+ $(PLATFORM_BOARD_PACKAGE)/Policy/IioUdsDataDxe/IioUdsDataDxe.inf
+ $(PLATFORM_BOARD_PACKAGE)/Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf
+ $(PLATFORM_BOARD_PACKAGE)/Pci/PciPlatform/PciPlatform.inf
+ $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf {
+ <BuildOptions>
+ MSFT:*_*_*_ASLCC_FLAGS = /D PURLEY_FLAG /D PCH_SPT
+ GCC:*_*_*_ASLCC_FLAGS = -D PURLEY_FLAG -D PCH_SPT
+ }
+
+# This is for prebuild only. No need to include in final FDF.
+ $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/Dsdt.inf {
+ <BuildOptions>
+ MSFT:*_*_*_ASLCC_FLAGS = /D PURLEY_FLAG /D PCH_SPT
+ GCC:*_*_*_ASLCC_FLAGS = -D PURLEY_FLAG -D PCH_SPT
+ }
+
+ $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+ $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
+ $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {
+ <LibraryClasses>
+ BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
+ }
+
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+
+ $(PLATFORM_BOARD_PACKAGE)/Policy/S3NvramSave/S3NvramSave.inf
+
+ #
+ # Shell
+ #
+ ShellPkg/Application/Shell/Shell.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ <LibraryClasses>
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ }
+
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
new file mode 100644
index 0000000000..7a3ffff7ff
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
@@ -0,0 +1,589 @@
+## @file
+# FDF file for the MtOlympus board.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+
+# Note: FlashNv PCD naming conventions are as follows:
+# Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for
+# Others should be examined with an effort to work toward this guideline.
+# PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
+# PcdFlash*Size is a hex count of the length of the FD or FV
+# All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
+#
+# Also all values will have a PCD assigned so that they can be used in the system, and
+# the FlashMap edit tool can be used to change the values here, without effecting the code.
+# This requires all code to only use the PCD tokens to recover the values.
+
+[FD.Platform]
+BaseAddress = 0xFF000000 | gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress
+Size = 0x01000000 | gEfiPchTokenSpaceGuid.PcdFlashAreaSize
+ErasePolarity = 1
+BlockSize = 0x10000
+NumBlocks = 0x100
+
+0x00000000|0x00500000
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+FV = FvAdvanced
+
+0x00500000|0x00100000
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+FV = FvSecurity
+
+0x00600000|0x00100000
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+FV = FvOsBoot
+
+0x00700000|0x00200000
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize
+FV = FvLateSiliconCompressed
+
+0x00900000|0x00400000
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+FV = FvUefiBoot
+
+0x00D00000|0x0007C000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x100000
+ 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
+ #Signature "_FVH" #Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+ #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x1A, 0x09, 0x00, 0x00, 0x00, 0x02,
+ #Blockmap[0]: 16 Blocks * 0x10000 Bytes / Block
+ 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ #Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
+ # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } }
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+ !else
+ # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ !endif
+ #Size: 0x7c000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x7BFFB8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xBF, 0x07, 0x00,
+ #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x00D7C000|0x00002000
+#NV_EVENT_LOG
+
+0x00D7E000|0x00002000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x00D80000|0x00080000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
+
+
+0x00E00000|0x00010000
+gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
+FV = MICROCODE_FV
+
+0x00E10000|0x00010000
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+FV = FvPostMemory
+
+0x00E20000|0x00030000
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+FILE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.Fv
+
+0x00E50000|0x00060000
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+FV = FvPreMemory
+
+0x00EB0000|0x00130000
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+FILE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.Fv
+
+0x00FE0000|0x00020000
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+FILE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempMemorySilicon.Fv
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
+
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60
+
+SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60
+SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvLateSiliconCompressed]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = BA793112-EA2E-47C4-9AFE-A8FCFE603D6D
+
+FILE FV_IMAGE = A626BB34-2455-4FCA-8DFB-FEE96DB0DC5F {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(TARGET)/FvLateSilicon.Fv
+ }
+ }
+
+[FV.MICROCODE_FV]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = FALSE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/Microcode.inf
+
+[FV.FvPreMemory]
+FvAlignment = 16
+FvForceRebase = TRUE
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
+
+ ##
+ # PEI Apriori file example, more PEIM module added later.
+ ##
+INF MdeModulePkg/Core/Pei/PeiMain.inf
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
+
+INF $(PLATFORM_BOARD_PACKAGE)/Policy/SystemBoard/SystemBoardPei.inf
+
+INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+
+[FV.FvPostMemory]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = C54E3E8D-9FF5-4D52-AF03-58018EB55F63
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
+
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
+
+[FV.FvUefiBootUncompact]
+BlockSize = 0x10000
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
+
+ ##
+ # DXE Phase modules
+ ##
+
+ ##
+ # DXE Apriori file example, more DXE module added later.
+ ##
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
+
+INF PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf
+
+INF $(PLATFORM_BOARD_PACKAGE)/Policy/IioUdsDataDxe/IioUdsDataDxe.inf
+INF $(PLATFORM_BOARD_PACKAGE)/Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf
+INF $(PLATFORM_BOARD_PACKAGE)/Pci/PciPlatform/PciPlatform.inf
+
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+
+INF ShellPkg/Application/Shell/Shell.inf
+
+INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+
+[FV.FvUefiBoot]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 27A72E80-3118-4c0c-8673-AA5B4EFA9613
+
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvUefiBootUncompact
+ }
+ }
+
+[FV.FvOsBootUncompact]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 5AB52883-85DF-445B-99F7-E0C1D517A905
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
+
+INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
+INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
+
+INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
+
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+
+[FV.FvOsBoot]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 5e2363c4-3e9e-4203-b873-bb40df46c8e6
+
+FILE FV_IMAGE = AC09A11F-BD9F-4C87-B656-F4868EEA89B8 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvOsBootUncompact
+ }
+ }
+
+[FV.FvSecurityPreMem]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = A91F91A0-0CCD-4E1C-9FD8-4DAE39F348FA
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
+
+[FV.FvSecurityPostMem]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 04B00029-2391-44C1-97BA-3FA8A42E9D3A
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
+!endif
+
+[FV.FvSecurityLate]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = CCBC50ED-0902-413E-BC2C-409C906F4A80
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
+!endif
+
+[FV.FvSecurity]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 8CBBA80C-FE21-4749-B015-6EDFC34B6BE7
+
+FILE FV_IMAGE = A63B2BBF-7A02-4862-BF22-A1BA5258DD68 {
+ SECTION FV_IMAGE = FvSecurityPreMem
+ }
+
+FILE FV_IMAGE = 47B40638-0087-4938-97CF-B56983A1A07B {
+ SECTION FV_IMAGE = FvSecurityPostMem
+ }
+
+FILE FV_IMAGE = 605CBDF4-61DB-4B77-BAED-65232B8EC6D6 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecurityLate
+ }
+ }
+
+[FV.FvAdvancedPreMem]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = EBC45843-B180-44D3-A485-0031A75DB16D
+
+!include AdvancedFeaturePkg/Include/PreMemory.fdf
+
+[FV.FvAdvancedUncompact]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 05411CAD-6C35-4675-B6CA-8748032144B4
+
+!include AdvancedFeaturePkg/Include/PostMemory.fdf
+
+[FV.FvAdvanced]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 59584CB6-0740-4EE6-A335-A46B370A101A
+
+FILE FV_IMAGE = 0112F63C-E0EA-4CA7-BFAA-9574DB03B230 {
+ SECTION FV_IMAGE = FvAdvancedPreMem
+ }
+
+FILE FV_IMAGE = 07FC4960-5322-4DDC-A6A4-A17DE492DFE3 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvAdvancedUncompact
+ }
+ }
+
+[FV.FvDummy]
+FvAlignment = 16
+FvForceRebase = FALSE
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+# Add dummy FV here to build the PCD in FV into PCD database.
+INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempMemorySilicon.inf
+INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.inf
+INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.inf
+INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(TARGET)/FvLateSilicon.inf
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgBuildOption.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgBuildOption.dsc
new file mode 100644
index 0000000000..eb282963e9
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgBuildOption.dsc
@@ -0,0 +1,81 @@
+## @file
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[BuildOptions.Common.EDKII]
+# Append build options for EDK and EDKII drivers (= is Append, == is Replace)
+
+ DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG
+ DEFINE EDKII_CPU_BUILD_OPTIONS = -D PURLEY_FLAG
+ DEFINE TRAD_BUILD_OPTION = -D TRAD_FLAG=1
+ DEFINE SUS_WELL_RESTORE_BUILD_OPTION = -D SUS_WELL_RESTORE=1
+ DEFINE PCH_BUILD_OPTION = -D PCH_SERVER_BIOS_FLAG=1
+ DEFINE SERVER_BUILD_OPTION = -D SERVER_BIOS_FLAG=1
+ DEFINE PCH_PKG_OPTIONS = -D PCH_SPT
+ DEFINE MAX_SOCKET_OPTIONS = -D MAX_SOCKET=2
+
+ DEFINE EDKII_ALL_PPO_OPTIONS = $(EDKII_CPU_BUILD_OPTIONS)
+ DEFINE PCH_BIOS_BUILD_OPTIONS = $(TRAD_BUILD_OPTION) $(ULT_BUILD_OPTION) $(PCH_BUILD_OPTION) $(SUS_WELL_RESTORE_BUILD_OPTION) $(SERVER_BUILD_OPTION)
+ DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(CRB_EDKII_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(EDKII_ALL_PPO_OPTIONS) $(SPARING_SCRATCHPAD_OPTION) $(TRACE_HUB_DEBUG_BUILD_OPTIONS) $(TRACE_HUB_INIT_BUILD_OPTIONS) $(MAX_SOCKET_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT -D SKX_HOST -D CLX_HOST
+
+!if $(TARGET) == "DEBUG"
+ DEFINE DEBUG_BUILD_FLAG = -D SERIAL_DBG_MSG=1
+!else
+ DEFINE DEBUG_BUILD_FLAG = -D MDEPKG_NDEBUG -D SILENT_MODE
+!endif
+
+ DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(DEBUG_BUILD_FLAG)
+#
+# PC_BUILD_END
+#
+
+
+ DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+ *_*_*_CC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+#
+# Enable source level debugging for RELEASE build
+#
+!if $(TARGET) == "RELEASE"
+ DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS = /Zi
+ DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS = /Zi /Gm
+ DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS = /DEBUG
+
+ MSFT:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
+ MSFT:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
+ MSFT:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
+!endif
+
+
+#
+# Override the existing iasl path in tools_def.template
+#
+# MSFT:*_*_*_ASL_PATH == c:/Iasl/iasl.exe
+
+#
+# Override the VFR compile flags to speed the build time
+#
+
+*_*_*_VFR_FLAGS == -n
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support page level protection
+[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+ GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support MemoryAttribute table
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+ GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgConfig.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgConfig.dsc
new file mode 100644
index 0000000000..2bd714c01e
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgConfig.dsc
@@ -0,0 +1,58 @@
+## @file
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+#
+# TRUE is ENABLE. FALSE is DISABLE.
+#
+
+[PcdsFixedAtBuild]
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
+
+[PcdsFeatureFlag]
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
+!endif
+
+ !if $(TARGET) == DEBUG
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+ !else
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
+ !endif
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|TRUE
+
+ gPlatformTokenSpaceGuid.PcdFastBoot|FALSE
+!if gPlatformTokenSpaceGuid.PcdFastBoot == TRUE
+ gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable|FALSE
+ gPlatformTokenSpaceGuid.PcdUpdateConsoleInBds|FALSE
+!endif
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc
new file mode 100644
index 0000000000..6f6fb20d46
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc
@@ -0,0 +1,389 @@
+## @file
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all PCD Entries defined by this board.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ ######################################
+ # Key Boot Stage and FSP configuration
+ ######################################
+ #
+ # Please select the Boot Stage here.
+ # Stage 1 - enable debug (system deadloop after debug init)
+ # Stage 2 - mem init (system deadloop after mem init)
+ # Stage 3 - boot to shell only
+ # Stage 4 - boot to OS
+ # Stage 5 - boot to OS with security boot enabled
+ # Stage 6 - boot with advanced features enabled
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
+
+[PcdsFeatureFlag.common]
+ gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|FALSE
+ # Server doesn't support capsle update on Reset.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE
+ gEfiCpuTokenSpaceGuid.PcdCpuHotPlugSupport|TRUE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
+
+#S3 add
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+#S3 add
+
+ gEfiCpuTokenSpaceGuid.PcdCpuConroeFamilyFlag|FALSE
+ gEfiCpuTokenSpaceGuid.PcdCpuCedarMillFamilyFlag|FALSE
+ gEfiCpuTokenSpaceGuid.PcdCpuPrescottFamilyFlag|FALSE
+ gEfiCpuTokenSpaceGuid.PcdCpuNehalemFamilyFlag|FALSE
+ gEfiCpuTokenSpaceGuid.PcdCpuIvyBridgeFamilyFlag|FALSE
+ gEfiCpuTokenSpaceGuid.PcdCpuSandyBridgeFamilyFlag|FALSE
+ gEfiCpuTokenSpaceGuid.PcdCpuHaswellFamilyFlag|TRUE
+ gEfiCpuTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE
+
+ gEfiCpuTokenSpaceGuid.PcdCpuGateA20MDisableFlag|FALSE
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmDebug|TRUE
+ gEfiCpuTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE
+ gEfiCpuTokenSpaceGuid.PcdCpuSocketIdReassignmentFlag|TRUE
+
+ ## This PCD specified whether ACPI SDT protocol is installed.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
+!endif
+
+!if $(TARGET) == DEBUG
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
+!endif
+
+[PcdsFeatureFlag.X64]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE
+
+[PcdsFeatureFlag]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE
+
+[PcdsDynamicExDefault]
+!include $(PROJECT)/StructureConfig.dsc
+
+[PcdsFixedAtBuild.X64]
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x01, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x01, 0x01, 0x01, 0x06, 0x00, 0x00, 0x01, 0x7F, 0xFF, 0x04, 0x00}
+
+[PcdsFixedAtBuild.IA32]
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0x00FFA00000
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x0000600000
+
+[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE
+!if $(TARGET) == "RELEASE"
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+!if $(TARGET) == RELEASE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+!endif
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+#S3 modified
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
+#S3 modified
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x1700000
+
+ gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gEfiCpuTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
+ gEfiCpuTokenSpaceGuid.PcdPlatformType|2
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxFsbFrequency|1066
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmStackSize|0x10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000
+
+ ## Specifies delay value in microseconds after sending out an INIT IPI.
+ # @Prompt Configure delay value after send an INIT IPI
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10
+
+ ## Specifies max supported number of Logical Processors.
+ # @Prompt Configure max supported number of Logical Processorss
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+!endif
+
+ gPlatformTokenSpaceGuid.PcdBusStack|0x06
+ gPlatformTokenSpaceGuid.PcdUboDev|0x08
+ gPlatformTokenSpaceGuid.PcdUboFunc|0x02
+ gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC
+
+ gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
+
+ ## Defines the ACPI register set base address.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Timer IO Port Address
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500
+
+ ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # @Prompt ACPI Hardware PCI Bus Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x20091013
+
+ ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Device Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F
+
+ ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Function Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02
+
+ ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044
+
+ ## Defines the bit mask that must be set to enable the APIC hardware register BAR.
+ # @Prompt ACPI Hardware PCI Bar Enable BitMask
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80
+
+ ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Bar Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040
+
+ ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.
+ # @Prompt Offset to 32-bit Timer register in ACPI BAR
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008
+
+ ## Defines the bit mask to retrieve ACPI IO Port Base Address
+ # @Prompt ACPI IO Port Base Address Mask
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFC
+
+ # Indicates the max nested level
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000010
+
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET)
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET)
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x70
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x80
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x1470
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0xA0
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x80
+
+ #
+ # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
+ #
+ # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
+ # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
+ # that lie entirely within the expected fixed memory regions.
+ # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
+ # BIT3-31: Reserved
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
+
+[PcdsFixedAtBuild.X64]
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099
+ # Change PcdBootManagerMenuFile to UiApp
+##
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5
+
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1
+
+ gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24
+
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0
+
+[PcdsPatchableInModule.common]
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
+!endif
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase |0x1000
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0x90000000
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit |0xFBFFFFFF
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase |0x380000000000
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit |0x3803FFFFFFFF
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
+
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE
+ gEfiCpuTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x01400000
+
+[PcdsDynamicExDefault.common.DEFAULT]
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfiguration|0x002CF6CF
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfigurationEx1|0
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000
+ gEfiCpuTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0
+
+ gEfiPchTokenSpaceGuid.PcdWakeOnRTCS5|FALSE
+ gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeHour|0
+ gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeMinute|0
+ gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeSecond|0
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0x5
+
+[PcdsDynamicExHii.common.DEFAULT]
+!if gPlatformTokenSpaceGuid.PcdFastBoot == FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|3 # Variable: L"Timeout"
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0 # Variable: L"Timeout"
+!endif
+ gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+
+
+[PcdsDynamicExDefault]
+
+ gOemSkuTokenSpaceGuid.PcdForceTo1SConfigMode|FALSE
+
+## *** PURLEY_PPO *** - Added in 8th segment in PcdPcieMmcfgTablePtr to fix size assert in PcieAddressLib.c
+## | MMCFG Table Header | Segment 0 | Segment 1 | Segment 2 | Segment 3 | Segment 4 | Segment 5 | Segment 6 | Segment 7 | Segment 8
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
+
+ gEfiCpuTokenSpaceGuid.PcdCpuEnergyPolicy|0
+ gEfiCpuTokenSpaceGuid.PcdCpuAcpiLvl2Addr|0
+ gEfiCpuTokenSpaceGuid.PcdCpuPackageCStateLimit|0
+ gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue|0
+ gEfiCpuTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0
+ gEfiCpuTokenSpaceGuid.PcdCpuHwCoordination|TRUE
+ gEfiCpuTokenSpaceGuid.PcdCpuDcuMode|0
+ gEfiCpuTokenSpaceGuid.PcdCpuTurboOverride|0x0
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorMsrLockCtrl|0
+ gEfiCpuTokenSpaceGuid.PcdCpuIioLlcWaysBitMask|0x0
+ gEfiCpuTokenSpaceGuid.PcdCpuExpandedIioLlcWaysBitMask|0x0
+ gEfiCpuTokenSpaceGuid.PcdCpuRemoteWaysBitMask|0x0
+ gEfiCpuTokenSpaceGuid.PcdPchTraceHubEn|0x0
+ gEfiCpuTokenSpaceGuid.PcdCpuQlruCfgBitMask|0x0
+ gEfiCpuTokenSpaceGuid.PcdSbspSelection|0xFF
+# gEfiCpuTokenSpaceGuid.PcdCpuSocketId|{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x3,0x0,0x0,0x0}
+ gEfiCpuTokenSpaceGuid.PcdCpuPmStructAddr|0x0
+ gEfiCpuTokenSpaceGuid.PcdCpuRRQCountThreshold|0x0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, 0x54, 0x45, 0x4C, 0x20}
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2046573030363253
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0
+
+[PcdsDynamicExDefault.X64]
+
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat
new file mode 100644
index 0000000000..99c082b5f9
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat
@@ -0,0 +1,138 @@
+ at REM @file
+ at REM
+ at REM Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+ at REM SPDX-License-Identifier: BSD-2-Clause-Patent
+ at REM
+
+ at echo off
+
+REM Run setlocal to take a snapshot of the environment variables. endlocal is called to restore the environment.
+setlocal
+set SCRIPT_ERROR=0
+
+REM ---- Do NOT use :: for comments Inside of code blocks() ----
+
+::**********************************************************************
+:: Initial Setup
+::**********************************************************************
+
+:parseCmdLine
+if "%1"=="" goto :argumentCheck
+
+if /I "%1"=="debug" set TARGET=DEBUG
+if /I "%1"=="release" set TARGET=RELEASE
+
+if /I "%1"=="clean" (
+ set BUILD_TYPE=cleantree
+ call :cleantree
+ goto :EOF
+)
+
+shift
+GOTO :parseCmdLine
+
+:argumentCheck:
+
+if /I "%TARGET%" == "" (
+ echo Info: debug/release argument is empty, use DEBUG as default
+ set TARGET=DEBUG
+)
+
+REM Art to notify which board you're working on
+echo.
+type logo.txt
+echo.
+
+::
+:: Build configuration
+::
+set BUILD_REPORT_FLAGS=
+set BUILD_CMD_LINE=
+set BUILD_LOG=%WORKSPACE%\Build\build.log
+set BUILD_REPORT=%WORKSPACE%\Build\BuildReport.txt
+
+del %BUILD_LOG% *.efi *.log 2>NUL
+
+echo --------------------------------------------------------------------------------------------
+echo.
+echo Purley Build Start
+echo.
+echo --------------------------------------------------------------------------------------------
+
+
+:doPreBuild
+echo.
+echo --------------------------------------------------------------------
+echo.
+echo Prebuild Start
+echo.
+echo --------------------------------------------------------------------
+call prebuild.bat
+if %SCRIPT_ERROR% NEQ 0 EXIT /b %ERRORLEVEL%
+
+echo --------------------------------------------------------------------
+echo.
+echo Prebuild End
+echo.
+echo --------------------------------------------------------------------
+if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL%
+timeout 1
+
+:buildBios
+set BUILD_CMD_LINE=%BUILD_CMD_LINE% -D MAX_SOCKET=%MAX_SOCKET% -y %BUILD_REPORT%
+echo --------------------------------------------------------------------
+echo.
+echo Build Start
+echo.
+echo --------------------------------------------------------------------
+echo.
+echo build %BUILD_CMD_LINE% --log=%BUILD_LOG% %BUILD_REPORT_FLAGS%
+call build %BUILD_CMD_LINE% --log=%BUILD_LOG% %BUILD_REPORT_FLAGS%
+echo --------------------------------------------------------------------
+echo.
+echo Build End
+echo.
+echo --------------------------------------------------------------------
+if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL%
+timeout 1
+
+:postBuild
+
+echo --------------------------------------------------------------------
+echo.
+echo PostBuild Start
+echo.
+echo --------------------------------------------------------------------
+echo.
+call postbuild.bat
+if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL%
+timeout 1
+echo --------------------------------------------------------------------
+echo.
+echo PostBuild End
+echo.
+echo --------------------------------------------------------------------
+
+echo %date% %time%
+echo.
+
+echo --------------------------------------------------------------------------------------------
+echo.
+echo Purley Build End
+echo.
+echo --------------------------------------------------------------------------------------------
+
+:done
+endlocal & EXIT /b %SCRIPT_ERROR%
+
+::--------------------------------------------------------
+::-- Function section starts below here
+::--------------------------------------------------------
+:cleantree
+choice /t 3 /d y /m "Confirm: clean tree of intermediate files created in tree during build"
+if %ERRORLEVEL% EQU 2 goto :EOF
+goto :EOF
+
+
+:ErrorHandler:
+echo Error handler
\ No newline at end of file
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_board.py b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_board.py
new file mode 100644
index 0000000000..2ba615d3e4
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_board.py
@@ -0,0 +1,177 @@
+# @ build_board.py
+# This adds additional functions to the build_bios.py
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+"""
+This module serves as an additional build steps for the Mt Olympus board
+"""
+
+import os
+import sys
+
+
+def pre_build_ex(config, functions):
+ """Additional Pre BIOS build function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: nothing
+ """
+ print("Info: re-generating PlatformOffset header files")
+
+ execute_script = functions.get("execute_script")
+
+ command = ["build", "-D", "MAX_SOCKET=" + config.get("MAX_SOCKET", "1"),
+ "-m",
+ os.path.join(config["PLATFORM_BOARD_PACKAGE"],
+ "Acpi", "BoardAcpiDxe", "Dsdt.inf"),
+ "-y",
+ config.get("PRE_BUILD_REPORT",
+ os.path.join(config["WORKSPACE"],
+ "preBuildReport.txt")),
+ "--log=" + config.get("PRE_BUILD_LOG",
+ os.path.join(config["WORKSPACE"],
+ "prebuild.log"))]
+
+ _, _, _, code = execute_script(command, config)
+ if code != 0:
+ print(" ".join(command))
+ print("Error re-generating PlatformOffset header files")
+ sys.exit(1)
+
+ config["AML_FILTER"] = "\"PSYS\" .MCTL\" .FIX[0-9,A-Z]\""
+ print("AML_FILTER= ", config.get("AML_FILTER"))
+
+ # build the command with arguments
+ command = ["python",
+ os.path.join(config["MIN_PACKAGE_TOOLS"],
+ "AmlGenOffset",
+ "AmlGenOffset.py"),
+ "-d", "--aml_filter", config["AML_FILTER"],
+ "-o", os.path.join(config["WORKSPACE_PLATFORM"],
+ config["PLATFORM_BOARD_PACKAGE"],
+ "Acpi", "BoardAcpiDxe",
+ "AmlOffsetTable.c"),
+ os.path.join(config["BUILD_X64"],
+ "PurleyOpenBoardPkg",
+ "Acpi",
+ "BoardAcpiDxe",
+ "DSDT",
+ "OUTPUT",
+ "Dsdt", "WFPPlatform.offset.h")]
+
+ # execute the command
+ _, _, _, code = execute_script(command, config)
+ if code != 0:
+ print(" ".join(command))
+ print("Error re-generating PlatformOffset header files")
+ sys.exit(1)
+
+ print("GenOffset done")
+ return config
+
+
+def build_ex(config, functions):
+ """Additional BIOS build function
+
+ :param config: The environment variables to be used in
+ the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("build_ex")
+ return None
+
+
+def post_build_ex(config, functions):
+ """Additional Post BIOS build function
+
+ :param config: The environment variables to be used in the post
+ build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("post_build_ex")
+
+ execute_script = functions.get("execute_script")
+
+ if not execute_script:
+ print("post_build_ex Error")
+ sys.exit(1)
+
+ common_patch_command = [os.path.join(config["PYTHON_HOME"], "python"),
+ os.path.join(config["MIN_PACKAGE_TOOLS"],
+ "PatchFv", "PatchBinFv.py"),
+ config["TARGET"],
+ os.path.join(config["WORKSPACE_SILICON_BIN"],
+ "PurleySiliconBinPkg", "FV"),
+ os.path.join(config["WORKSPACE"],
+ "BuildReport.log")]
+
+ fvs_to_patch = ["FvTempMemorySilicon",
+ "FvPreMemorySilicon",
+ "FvPostMemorySilicon",
+ "FvLateSilicon"]
+ for fv in fvs_to_patch:
+ patch_command = common_patch_command + [fv]
+ _, _, _, code = execute_script(patch_command, config)
+ if code != 0:
+ print(" ".join(patch_command))
+ print("Patch Error!")
+ sys.exit(1)
+
+ common_rebase_command = [os.path.join(config["PYTHON_HOME"], "python"),
+ os.path.join(config["MIN_PACKAGE_TOOLS"],
+ "PatchFv", "RebaseBinFv.py"),
+ config["TARGET"],
+ os.path.join(config["WORKSPACE_SILICON_BIN"],
+ "PurleySiliconBinPkg", "FV"),
+ os.path.join(config["WORKSPACE"],
+ "BuildReport.log")]
+
+ rebase_command = common_rebase_command +\
+ ["FvPreMemorySilicon",
+ "gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase"]
+
+ _, _, _, code = execute_script(rebase_command, config)
+ if code != 0:
+ print(" ".join(rebase_command))
+ print("Patch Error!")
+ sys.exit(1)
+
+ rebase_command = common_rebase_command +\
+ ["FvPostMemorySilicon",
+ "gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase"]
+
+ _, _, _, code = execute_script(rebase_command, config)
+ if code != 0:
+ print(" ".join(rebase_command))
+ print("Patch Error!")
+ sys.exit(1)
+
+ return None
+
+
+def clean_ex(config, functions):
+ """Additional clean function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("clean_ex")
+ return None
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg
new file mode 100644
index 0000000000..165c7db0e3
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg
@@ -0,0 +1,32 @@
+# @ build_config.cfg
+# This is the main/default build configuration file
+#
+# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[CONFIG]
+WORKSPACE_PLATFORM_BIN =
+EDK_SETUP_OPTION =
+openssl_path =
+PLATFORM_BOARD_PACKAGE = PurleyOpenBoardPkg
+PROJECT = PurleyOpenBoardPkg/BoardMtOlympus
+BOARD = BoardMtOlympus
+FLASH_MAP_FDF = PurleyOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf
+PROJECT_DSC = PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc
+BOARD_PKG_PCD_DSC = PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc
+ADDITIONAL_SCRIPTS = PurleyOpenBoardPkg/BoardMtOlympus/build_board.py
+PRE_BUILD_LOG = prebuild.log
+PRE_BUILD_REPORT = prebuildReport.log
+PrepRELEASE = DEBUG
+SILENT_MODE = FALSE
+EXT_CONFIG_CLEAR =
+CapsuleBuild = FALSE
+EXT_BUILD_FLAGS =
+CAPSULE_BUILD = 0
+TARGET = DEBUG
+TARGET_SHORT = D
+PERFORMANCE_BUILD = FALSE
+FSP_WRAPPER_BUILD = FALSE
+MAX_SOCKET = 2
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt
new file mode 100644
index 0000000000..979ddb6691
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt
@@ -0,0 +1,11 @@
+
+ _____ ______ _________ ________ ___ ___ ___ _____ ______ ________ ___ ___ ________
+|\ _ \ _ \ |\___ ___\ |\ __ \ |\ \ |\ \ / /||\ _ \ _ \ |\ __ \ |\ \|\ \ |\ ____\
+\ \ \\\__\ \ \ \|___ \ \_| \ \ \|\ \ \ \ \ \ \ \/ / /\ \ \\\__\ \ \ \ \ \|\ \ \ \ \\\ \ \ \ \___|_
+ \ \ \\|__| \ \ \ \ \ \ \ \\\ \ \ \ \ \ \ / / \ \ \\|__| \ \ \ \ ____\ \ \ \\\ \ \ \_____ \
+ \ \ \ \ \ \ \ \ \ \ \ \\\ \ \ \ \____ \/ / / \ \ \ \ \ \ \ \ \___| \ \ \\\ \ \|____|\ \
+ \ \__\ \ \__\ \ \__\ \ \_______\ \ \_______\ __/ / / \ \__\ \ \__\ \ \__\ \ \_______\ ____\_\ \
+ \|__| \|__| \|__| \|_______| \|_______||\___/ / \|__| \|__| \|__| \|_______| |\_________\
+ \|___|/ \|_________|
+
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat
new file mode 100644
index 0000000000..6393e4caec
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat
@@ -0,0 +1,95 @@
+ at REM @file
+ at REM
+ at REM Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+ at REM SPDX-License-Identifier: BSD-2-Clause-Patent
+ at REM
+
+ at set SCRIPT_ERROR=0
+
+set /a postbuildstep=0
+
+ at echo.
+ at echo BoardPostBuild.%postbuildstep% python PatchBinFv.py
+ at set /a postbuildstep=%postbuildstep%+1
+echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvTempMemorySilicon
+call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvTempMemorySilicon
+if %ERRORLEVEL% NEQ 0 (
+ set SCRIPT_ERROR=1
+ echo PatchBinFv Error. Exit
+ goto :EOF
+)
+echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon
+call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon
+if %ERRORLEVEL% NEQ 0 (
+ set SCRIPT_ERROR=1
+ echo PatchBinFv Error. Exit
+ goto :EOF
+)
+echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon
+call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon
+if %ERRORLEVEL% NEQ 0 (
+ set SCRIPT_ERROR=1
+ echo PatchBinFv Error. Exit
+ goto :EOF
+)
+echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvLateSilicon
+call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvLateSilicon
+if %ERRORLEVEL% NEQ 0 (
+ set SCRIPT_ERROR=1
+ echo PatchBinFv Error. Exit
+ goto :EOF
+)
+
+ at echo.
+ at echo BoardPostBuild.%postbuildstep% python RebaseBinFv.py
+ at set /a postbuildstep=%postbuildstep%+1
+echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+if %ERRORLEVEL% NEQ 0 (
+ set SCRIPT_ERROR=1
+ echo RebaseBinFv Error. Exit
+ goto :EOF
+)
+
+echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
+call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
+if %ERRORLEVEL% NEQ 0 (
+ set SCRIPT_ERROR=1
+ echo RebaseBinFv Error. Exit
+ goto :EOF
+)
+
+ at echo.
+ at echo BoardPostBuild.%postbuildstep% re-generate FDS
+ at set /a postbuildstep=%postbuildstep%+1
+echo build fds
+ at REM call build fds
+if %ERRORLEVEL% NEQ 0 (
+ set SCRIPT_ERROR=1
+ echo gen FDS Error. Exit
+ goto :EOF
+)
+
+ at echo.
+ at echo BoardPostBuild.%postbuildstep% python PatchBfv.py
+ at set /a postbuildstep=%postbuildstep%+1
+echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBfv.py %WORKSPACE%\Build\%BOARD_PKG%\%BOARD_NAME%\%TARGET%_%TOOL_CHAIN_TAG%\FV\PLATFORM.fd %WORKSPACE%\Build\BuildReport.txt gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
+call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBfv.py %WORKSPACE%\Build\%BOARD_PKG%\%BOARD_NAME%\%TARGET%_%TOOL_CHAIN_TAG%\FV\PLATFORM.fd %WORKSPACE%\Build\BuildReport.txt gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
+if %ERRORLEVEL% NEQ 0 (
+ set SCRIPT_ERROR=1
+ echo PatchBfv Error. Exit
+ goto :EOF
+)
+
+:_done
+
+ at echo.
+ at cd %WORKSPACE%
+ at if "%SCRIPT_ERROR%" == "0" (
+ @echo PostBuild SUCCEEDED.
+) else (
+ @echo PostBuild FAILED.
+ Pause 0
+)
+
+EXIT /B %SCRIPT_ERROR%
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat
new file mode 100644
index 0000000000..22eeac1e80
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat
@@ -0,0 +1,197 @@
+ at REM @file
+ at REM
+ at REM Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+ at REM SPDX-License-Identifier: BSD-2-Clause-Patent
+ at REM
+
+ at set SCRIPT_ERROR=0
+
+set /a prebuildstep=0
+
+call :check_BuildTools
+if %SCRIPT_ERROR% NEQ 0 GOTO :done
+
+call :setBuildEnv
+if %SCRIPT_ERROR% NEQ 0 GOTO :done
+
+call :createTargetTxt
+if %SCRIPT_ERROR% NEQ 0 GOTO :done
+
+call :genPlatformOffsetHeaderFile
+if %SCRIPT_ERROR% NEQ 0 GOTO :done
+
+:prebuildFinish
+echo.
+echo ACTIVE_PLATFORM = %WORKSPACE%\edk2-platforms\Platform\Intel\%BOARD_PKG%\%BOARD_NAME%\OpenBoardPkg.dsc
+echo EDK_TOOLS_PATH = %EDK_TOOLS_PATH%
+echo TARGET = %TARGET%
+echo TARGET_ARCH = IA32 X64
+echo TOOL_CHAIN_TAG = %TOOL_CHAIN_TAG%
+echo WORKSPACE = %WORKSPACE%
+echo PACKAGES_PATH = %PACKAGES_PATH%
+echo MAX_CONCURRENT_THREAD_NUMBER = %BUILD_MAX_CON_THREAD_NUM%
+echo.
+echo Build Path = %OUTPUT_DIR%
+echo.
+
+REM Remove environment variable because it's no longer needed.
+set BUILD_MAX_CON_THREAD_NUM=
+
+:done
+REM Use done label to exit batch file and run any final steps; GOTO :EOF immediately exits.
+EXIT /B %SCRIPT_ERROR%
+
+::--------------------------------------------------------
+::-- Function section starts below here
+::--------------------------------------------------------
+
+:cleanup_check_VSTools
+set COMPILER_VERSION_STRING=
+del cloutput.txt > nul
+REM cleanup_check_VSTools is called below. When a label is called, 'GOTO :EOF' is used to return to caller.
+GOTO :EOF
+
+:check_BuildTools
+echo PreBuild.%prebuildstep% check_BuildTools
+echo ..VSTools
+set /a prebuildstep=%prebuildstep%+1
+set TOOL_CHAIN_TAG=
+ at if not defined TOOL_CHAIN_TAG (
+ echo.
+ echo Prebuild: TOOL_CHAIN_TAG is not set before
+ echo.
+
+ @if defined VS140COMNTOOLS (
+ echo.
+ echo Set the VS2015 environment.
+ echo.
+ set CL_SEL=VS2015
+ if /I "%VS140COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio 14.0\Common7\Tools\" (
+ set TOOL_CHAIN_TAG=VS2015
+ ) else (
+ set TOOL_CHAIN_TAG=VS2015x86
+ )
+ if /I "%PROCESSOR_ARCHITECTURE%" == "AMD64" (
+ set CL_CMDLINE="%VS140COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe"
+ ) else (
+ set CL_CMDLINE="%VS140COMNTOOLS:~0,-14%VC\bin\cl.exe"
+ )
+ ) else if defined VS120COMNTOOLS (
+ echo.
+ echo Set the VS2013 environment.
+ echo.
+ set CL_SEL=VS2013
+ if /I "%VS120COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio 12.0\Common7\Tools\" (
+ set TOOL_CHAIN_TAG=VS2013
+ ) else (
+ set TOOL_CHAIN_TAG=VS2013x86
+ )
+ if /I "%PROCESSOR_ARCHITECTURE%" == "AMD64" (
+ set CL_CMDLINE="%VS120COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe"
+ ) else (
+ set CL_CMDLINE="%VS120COMNTOOLS:~0,-14%VC\bin\cl.exe"
+ )
+ ) else (
+ echo.
+ echo !!! ERROR !!! VS2015 or VS2013 not installed correctly. !!!
+ echo.
+ goto :ErrorExit
+ )
+)
+
+echo ..iASL
+set CHECK_PATH_IASL=%IASL_PREFIX%
+if not exist %CHECK_PATH_IASL%\iasl.exe (
+ echo.
+ echo !!! ERROR !!! Could not find iASL compiler at %CHECK_PATH_IASL%\iasl.exe. !!!
+ echo.
+ set SCRIPT_ERROR=1
+)
+set CHECK_PATH_IASL=
+
+echo ..NASM
+set CHECK_PATH_NASM=c:\NASM
+if not exist %CHECK_PATH_NASM%\nasm.exe (
+ echo.
+ echo !!! ERROR !!! Could not find NASM compiler at %CHECK_PATH_NASM%\nasm.exe. !!!
+ echo.
+ set SCRIPT_ERROR=1
+)
+set CHECK_PATH_NASM=
+
+echo ..Python
+set CHECK_PATH_PYTHON=c:\Python27
+if not exist %CHECK_PATH_PYTHON%\python.exe (
+ echo.
+ echo !!! ERROR !!! Could not find Python at %CHECK_PATH_PYTHON%\python.exe. !!!
+ echo.
+ set SCRIPT_ERROR=1
+)
+set CHECK_PATH_PYTHON=
+set PYTHON_HOME=C:\Python27
+
+GOTO :EOF
+
+:setBuildEnv
+echo PreBuild.%prebuildstep% SetBuildEnv
+set /a prebuildstep=%prebuildstep%+1
+
+ at set BOARD_PKG=PurleyOpenBoardPkg
+ at set BOARD_NAME=BoardMtOlympus
+ at set MAX_SOCKET=2
+
+echo.
+echo BOARD_NAME=%BOARD_NAME%
+echo BOARD_PKG=%BOARD_PKG%
+echo MAX_SOCKET=%MAX_SOCKET%
+echo TARGET=%TARGET%
+
+ at set OUTPUT_DIR=%WORKSPACE%\Build\%BOARD_PKG%\%BOARD_NAME%\%TARGET%_%TOOL_CHAIN_TAG%
+
+if not exist %OUTPUT_DIR% mkdir %OUTPUT_DIR%
+GOTO :EOF
+
+:createTargetTxt
+echo PreBuild.%prebuildstep% CreateTargetTxt
+set /a prebuildstep=%prebuildstep%+1
+set /a BUILD_MAX_CON_THREAD_NUM = %NUMBER_OF_PROCESSORS%-1
+ at REM set /a BUILD_MAX_CON_THREAD_NUM = 1
+findstr /V "ACTIVE_PLATFORM TARGET TARGET_ARCH TOOL_CHAIN_TAG BUILD_RULE_CONF MAX_CONCURRENT_THREAD_NUMBER" %WORKSPACE%\Conf\target.txt > %OUTPUT_DIR%\target.txt 2>NUL
+echo ACTIVE_PLATFORM = %WORKSPACE%/edk2-platforms/Platform/Intel/%BOARD_PKG%/%BOARD_NAME%/OpenBoardPkg.dsc >> %OUTPUT_DIR%\target.txt
+echo TARGET = %TARGET% >> %OUTPUT_DIR%\target.txt
+echo TARGET_ARCH = IA32 X64 >> %OUTPUT_DIR%\target.txt
+echo TOOL_CHAIN_TAG = %TOOL_CHAIN_TAG% >> %OUTPUT_DIR%\target.txt
+echo BUILD_RULE_CONF = Conf/build_rule.txt >> %OUTPUT_DIR%\target.txt
+echo MAX_CONCURRENT_THREAD_NUMBER = %BUILD_MAX_CON_THREAD_NUM% >> %OUTPUT_DIR%\target.txt
+if exist %WORKSPACE%\Conf\target.txt (
+ del /f %WORKSPACE%\Conf\target.txt
+)
+move /Y %OUTPUT_DIR%\target.txt %WORKSPACE%\Conf\ > nul
+if not exist %OUTPUT_DIR%\X64 mkdir %OUTPUT_DIR%\X64
+GOTO :EOF
+
+
+:genPlatformOffsetHeaderFile
+echo.
+echo PreBuild.%prebuildstep% GenPlatformOffsetHeaderFile
+set /a prebuildstep=%prebuildstep%+1
+
+echo Info: re-generating PlatformOffset header files
+
+set PRE_BUILD_CMD_LINE=%BUILD_CMD_LINE% -D MAX_SOCKET=%MAX_SOCKET%
+set PRE_BUILD_LOG=%WORKSPACE%\Build\prebuild.log
+set PRE_BUILD_REPORT=%WORKSPACE%\Build\preBuildReport.txt
+
+echo build %PRE_BUILD_CMD_LINE% -m %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% --log=%PRE_BUILD_LOG%
+call build %PRE_BUILD_CMD_LINE% -m %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% --log=%PRE_BUILD_LOG%
+if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL%
+
+ at REM PSYS == FIX0
+ at REM MCTL == FIX8
+set AML_FILTER="\"PSYS\" .MCTL\" .FIX[0-9,A-Z]\""
+echo AML_FILTER=%AML_FILTER%
+call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\AmlGenOffset\AmlGenOffset.py -d --aml_filter %AML_FILTER% -o %WORKSPACE%\edk2-platforms\Platform\Intel\%BOARD_PKG%\Acpi\BoardAcpiDxe\AmlOffsetTable.c %OUTPUT_DIR%\X64\PurleyOpenBoardPkg\Acpi\BoardAcpiDxe\DSDT\OUTPUT\Dsdt\WFPPlatform.offset.h
+echo.
+echo GenOffset done
+
+GOTO :EOF
\ No newline at end of file
diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg
index 97c5c9a290..ede542f9f5 100644
--- a/Platform/Intel/build.cfg
+++ b/Platform/Intel/build.cfg
@@ -54,6 +54,7 @@ BIOS_INFO_GUID =
[PLATFORMS]
# board_name = path_to_board_build_config.cfg
+BoardMtOlympus = PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg
BoardX58Ich10 = SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
GalagoPro3 = KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg
KabylakeRvp3 = KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg
--
2.27.0.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#74983): https://edk2.groups.io/g/devel/message/74983
Mute This Topic: https://groups.io/mt/82742444/1813853
Group Owner: devel+owner at edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [edk2-devel-archive at redhat.com]
-=-=-=-=-=-=-=-=-=-=-=-
More information about the edk2-devel-archive
mailing list