[edk2-devel] [edk2-platforms][PATCH V1 2/6] Platform/Sgi: ACPI PPTT table for RD-N2-Cfg1 platform
Sami Mujawar
sami.mujawar at arm.com
Mon May 24 14:13:28 UTC 2021
Hi Pranav,
This patch looks good to me.
Reviewed-by: Sami Mujawar <sami.mujawar at arm.com>
Regards,
Sami Mujawar
On 19/05/2021 09:22 AM, Pranav Madhu wrote:
> The RD-N2-Cfg1 platform includes eight single-thread CPUS. Each of the
> CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
> cache. The platform also includes a system level cache of 8MB. Add PPTT
> table for RD-N2-Cfg1 platform with this information.
>
> Signed-off-by: Pranav Madhu <pranav.madhu at arm.com>
> ---
> Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 1 +
> Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 166 ++++++++++++++++++++
> 2 files changed, 167 insertions(+)
>
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
> index 8c8ce462c9d3..59e9dfceec76 100644
> --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
> @@ -22,6 +22,7 @@
> Mcfg.aslc
> RdN2Cfg1/Dsdt.asl
> RdN2Cfg1/Madt.aslc
> + RdN2Cfg1/Pptt.aslc
> Spcr.aslc
> Ssdt.asl
> SsdtRos.asl
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
> new file mode 100644
> index 000000000000..5890544c0b92
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
> @@ -0,0 +1,166 @@
> +/** @file
> +* Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform
> +*
> +* This file describes the topological structure of the processor block on the
> +* RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-N2-Cfg1
> +* platform includes eight single-thread CPUS. Each of the CPUs include 64KB
> +* L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also
> +* includes system level cache of 8MB.
> +*
> +* Copyright (c) 2021, ARM Limited. All rights reserved.
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +* @par Specification Reference:
> +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
> +**/
> +
> +#include <IndustryStandard/Acpi.h>
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +
> +#include "SgiAcpiHeader.h"
> +#include "SgiPlatform.h"
> +
> +/** Define helper macro for populating processor core information.
> +
> + @param [in] PackageId Package instance number.
> + @param [in] ClusterId Cluster instance number.
> + @param [in] CpuId CPU instance number.
> +**/
> +#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
> + { \
> + /* Parameters for CPU Core */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
> + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
> + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId]), /* Parent */ \
> + ((PackageId << 4) | ClusterId), /* ACPI Id */ \
> + 2 /* Num of private resource */ \
> + ), \
> + \
> + /* Offsets of the private resources */ \
> + { \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].DCache), \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].ICache) \
> + }, \
> + \
> + /* L1 data cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
> + /* Next level of cache */ \
> + SIZE_64KB, /* Size */ \
> + 256, /* Num of sets */ \
> + 4, /* Associativity */ \
> + PPTT_DATA_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + /* L1 instruction cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
> + /* Next level of cache */ \
> + SIZE_64KB, /* Size */ \
> + 256, /* Num of sets */ \
> + 4, /* Associativity */ \
> + PPTT_INST_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + /* L2 cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + 0, /* Next level of cache */ \
> + SIZE_1MB, /* Size */ \
> + 2048, /* Num of sets */ \
> + 8, /* Associativity */ \
> + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + }
> +
> +/** Define helper macro for populating processor container information.
> +
> + @param [in] PackageId Package instance number.
> + @param [in] ClusterId Cluster instance number.
> +**/
> +#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
> + { \
> + /* Parameters for Cluster */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
> + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
> + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package), /* Parent */ \
> + ((PackageId << 4) | ClusterId), /* ACPI Id */ \
> + 0 /* Num of private resource */ \
> + ), \
> + \
> + /* Initialize child core */ \
> + { \
> + PPTT_CORE_INIT (PackageId, ClusterId, 0) \
> + } \
> + }
> +
> +#pragma pack(1)
> +/*
> + * Processor Properties Topology Table
> + */
> +typedef struct {
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
> + RD_PPTT_SLC_PACKAGE Package;
> +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
> +#pragma pack ()
> +
> +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
> + {
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> + )
> + },
> +
> + {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
> + OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc),
> + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
> +
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
> + Package.Slc),
> +
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
> + 0, /* Next level of cache */
> + SIZE_8MB, /* Size */
> + 8192, /* Num of sets */
> + 16, /* Associativity */
> + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
> + 64 /* Line size */
> + ),
> +
> + {
> + PPTT_CLUSTER_INIT (0, 0),
> + PPTT_CLUSTER_INIT (0, 1),
> + PPTT_CLUSTER_INIT (0, 2),
> + PPTT_CLUSTER_INIT (0, 3),
> + PPTT_CLUSTER_INIT (0, 4),
> + PPTT_CLUSTER_INIT (0, 5),
> + PPTT_CLUSTER_INIT (0, 6),
> + PPTT_CLUSTER_INIT (0, 7),
> + }
> + }
> +};
> +
> +/*
> + * Reference the table being generated to prevent the optimizer from removing
> + * the data structure from the executable
> + */
> +VOID* CONST ReferenceAcpiTable = &Pptt;
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75517): https://edk2.groups.io/g/devel/message/75517
Mute This Topic: https://groups.io/mt/82931742/1813853
Group Owner: devel+owner at edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [edk2-devel-archive at redhat.com]
-=-=-=-=-=-=-=-=-=-=-=-
More information about the edk2-devel-archive
mailing list