[edk2-devel] [edk2-platforms][PATCH V2 1/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform
Pranav Madhu
pranav.madhu at arm.com
Tue May 25 10:57:56 UTC 2021
From: Aditya Angadi <aditya.angadi at arm.com>
Arm's RD-N2-Cfg1 platform is a variant of the RD-N2 platform. Compared
to RD-N2 platform, RD-N2-Cfg1 has a reduced core count of eight Neoverse
N2 CPUs and a smaller interconnect mesh. As part of the initial platform
support for RD-N2-Cfg1 platform, add the corresponding ACPI tables,
platform and flash description files.
Signed-off-by: Pranav Madhu <pranav.madhu at arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar at arm.com>
---
Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc | 57 ++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 65 ++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 110 ++++++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 101 ++++++++++++++++++
Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc | 12 +++
5 files changed, 345 insertions(+)
diff --git a/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
new file mode 100644
index 000000000000..c26f652cb9e9
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
@@ -0,0 +1,57 @@
+## @file
+# Platform Description file for RD-N2-Cfg1 platform.
+#
+# Copyright (c) 2017 - 2020, Arm Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = RdN2Cfg1
+ PLATFORM_GUID = aca676d8-3acb-43d0-9e05-95e1ce6bf5d3
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = NOOPT|DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
+ BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc
+ BUILD_NUMBER = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+
+# include common/basic libraries from MdePkg.
+!include MdePkg/MdeLibs.dsc.inc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ # GIC Base Addresses
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x30100000
+ gArmSgiTokenSpaceGuid.PcdGicSize|0x200000
+
+ # ARM Cores and Clusters
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|1
+ gArmPlatformTokenSpaceGuid.PcdClusterCount|8
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+
+[Components.common]
+ Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
new file mode 100644
index 000000000000..f96353087b68
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
@@ -0,0 +1,65 @@
+## @file
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2021, Arm Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = RdN2Cfg1AcpiTables
+ FILE_GUID = c712719a-0aaf-438c-9cdd-35ab4d60207d # gArmSgiAcpiTablesGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dbg2.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Iort.aslc
+ Mcfg.aslc
+ RdN2Cfg1/Dsdt.asl
+ RdN2Cfg1/Madt.aslc
+ Spcr.aslc
+ Ssdt.asl
+ SsdtRos.asl
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdClusterCount
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+
+ gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
+ gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuBase
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+ gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+ gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
+ gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
new file mode 100644
index 000000000000..d68523bc43ed
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
@@ -0,0 +1,110 @@
+/** @file
+* Differentiated System Description Table (DSDT) for RD-N2-Cfg1 platform
+*
+* This file describes the peripheral devices, system hardware features and the
+* information about supported power events.
+*
+* Copyright (c) 2021, Arm Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.11.1, Differentiated System Description
+ Table (DSDT)
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+ Scope (_SB) {
+ Device (CL00) { // Cluster 0
+ Name (_HID, "ACPI0010")
+ Name (_UID, 0)
+
+ Device (CP00) { // Neoverse N2 core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL01) { // Cluster 1
+ Name (_HID, "ACPI0010")
+ Name (_UID, 1)
+
+ Device (CP01) { // Neoverse N2 core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL02) { // Cluster 2
+ Name (_HID, "ACPI0010")
+ Name (_UID, 2)
+
+ Device (CP02) { // Neoverse N2 core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL03) { // Cluster 3
+ Name (_HID, "ACPI0010")
+ Name (_UID, 3)
+
+ Device (CP03) { // Neoverse N2 core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL04) { // Cluster 4
+ Name (_HID, "ACPI0010")
+ Name (_UID, 4)
+
+ Device (CP04) { // Neoverse N2 core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL05) { // Cluster 5
+ Name (_HID, "ACPI0010")
+ Name (_UID, 5)
+
+ Device (CP05) { // Neoverse N2 core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL06) { // Cluster 6
+ Name (_HID, "ACPI0010")
+ Name (_UID, 6)
+
+ Device (CP06) { // Neoverse N2 core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL07) { // Cluster 7
+ Name (_HID, "ACPI0010")
+ Name (_UID, 7)
+
+ Device (CP07) { // Neoverse N2 core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
+ }
+ } // Scope(_SB)
+}
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
new file mode 100644
index 000000000000..c6bb29a25c61
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
@@ -0,0 +1,101 @@
+/** @file
+* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
+*
+* This file lists all the processors available on the platform that the OSPM
+* can enumerate and boot. It also lists all the interrupt controllers available
+* in the system.
+*
+* Copyright (c) 2021, Arm Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
+ FixedPcdGet32 (PcdCoreCount))
+
+// Multiple APIC Description Table
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[3];
+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ // MADT specific fields
+ 0, // LocalApicAddress
+ 0 // Flags
+ },
+ {
+ // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // PmuIrq, GicBase, GicVBase,
+ // GicHBase, GsivId, GicRBase,
+ // Efficiency)
+ // Note: The GIC Structure of the primary CPU must be the first entry
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
+ 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
+ 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
+ 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7
+ 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0),
+ },
+ // GIC Distributor Entry
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ 0, 3),
+ // GIC Redistributor
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ SIZE_16MB),
+ // GIC ITS
+ {
+ EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
+ },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc
new file mode 100644
index 000000000000..ef0c02afb4f4
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc
@@ -0,0 +1,12 @@
+## @file
+# Flash Description include file for RD-N2-Cfg1 platform.
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+# Per-platform additional content of the DXE phase firmware volume
+
+ # ACPI support
+ INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
--
2.17.1
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