[edk2-devel] [PATCH 21/43] OvmfPkg/PlatformPei: remove Xen support
Laszlo Ersek
lersek at redhat.com
Wed May 26 20:14:24 UTC 2021
The "OvmfPkg/PlatformPei/PlatformPei.inf" module is used by the following
platform DSCs:
OvmfPkg/AmdSev/AmdSevX64.dsc
OvmfPkg/OvmfPkgIa32.dsc
OvmfPkg/OvmfPkgIa32X64.dsc
OvmfPkg/OvmfPkgX64.dsc
Remove Xen support from "OvmfPkg/PlatformPei", including any dependencies
that now become unused. The basic idea is to substitute FALSE for "mXen".
Remove "OvmfPkg/PlatformPei" from the "OvmfPkg: Xen-related modules"
section of "Maintainers.txt".
This patch is best reviewed with "git show -b -W".
Cc: Andrew Fish <afish at apple.com>
Cc: Ard Biesheuvel <ardb+tianocore at kernel.org>
Cc: Jordan Justen <jordan.l.justen at intel.com>
Cc: Leif Lindholm <leif at nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney at intel.com>
Cc: Philippe Mathieu-Daudé <philmd at redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek at redhat.com>
---
OvmfPkg/PlatformPei/PlatformPei.inf | 4 -
Maintainers.txt | 3 -
OvmfPkg/PlatformPei/Platform.h | 17 --
OvmfPkg/PlatformPei/Xen.h | 39 ----
OvmfPkg/PlatformPei/MemDetect.c | 10 +-
OvmfPkg/PlatformPei/Platform.c | 162 +++++++-------
OvmfPkg/PlatformPei/Xen.c | 222 --------------------
7 files changed, 77 insertions(+), 380 deletions(-)
diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf
index 6ef77ba7bb21..89d1f7636870 100644
--- a/OvmfPkg/PlatformPei/PlatformPei.inf
+++ b/OvmfPkg/PlatformPei/PlatformPei.inf
@@ -30,26 +30,23 @@ [Sources]
FeatureControl.c
Fv.c
MemDetect.c
MemTypeInfo.c
Platform.c
Platform.h
- Xen.c
- Xen.h
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
SecurityPkg/SecurityPkg.dec
UefiCpuPkg/UefiCpuPkg.dec
OvmfPkg/OvmfPkg.dec
[Guids]
gEfiMemoryTypeInformationGuid
- gEfiXenInfoGuid
[LibraryClasses]
BaseLib
CacheMaintenanceLib
DebugLib
HobLib
@@ -93,13 +90,12 @@ [Pcd]
gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes
gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
- gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable
gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable
gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase
diff --git a/Maintainers.txt b/Maintainers.txt
index 82008a0046c6..be40a1d6f2b6 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -498,15 +498,12 @@ F: OvmfPkg/Library/XenConsoleSerialPortLib/
F: OvmfPkg/Library/XenHypercallLib/
F: OvmfPkg/Library/XenIoMmioLib/
F: OvmfPkg/Library/XenPlatformLib/
F: OvmfPkg/Library/XenRealTimeClockLib/
F: OvmfPkg/OvmfXen.*
F: OvmfPkg/OvmfXenElfHeaderGenerator.c
-F: OvmfPkg/PlatformPei/MemDetect.c
-F: OvmfPkg/PlatformPei/Platform.*
-F: OvmfPkg/PlatformPei/Xen.*
F: OvmfPkg/SmbiosPlatformDxe/*Xen.c
F: OvmfPkg/XenAcpiPlatformDxe/
F: OvmfPkg/XenBusDxe/
F: OvmfPkg/XenIoPciDxe/
F: OvmfPkg/XenIoPvhDxe/
F: OvmfPkg/XenPlatformPei/
diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h
index 0484ec9e6b4c..8b1d270c2b0b 100644
--- a/OvmfPkg/PlatformPei/Platform.h
+++ b/OvmfPkg/PlatformPei/Platform.h
@@ -94,34 +94,17 @@ InstallFeatureControlCallback (
VOID
InstallClearCacheCallback (
VOID
);
-EFI_STATUS
-InitializeXen (
- VOID
- );
-
-BOOLEAN
-XenDetect (
- VOID
- );
-
VOID
AmdSevInitialize (
VOID
);
-extern BOOLEAN mXen;
-
-VOID
-XenPublishRamRegions (
- VOID
- );
-
extern EFI_BOOT_MODE mBootMode;
extern BOOLEAN mS3Supported;
extern UINT8 mPhysMemAddressWidth;
diff --git a/OvmfPkg/PlatformPei/Xen.h b/OvmfPkg/PlatformPei/Xen.h
deleted file mode 100644
index 2605481280c0..000000000000
--- a/OvmfPkg/PlatformPei/Xen.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/** @file
- Ovmf info structure passed by Xen
-
-Copyright (c) 2013, Citrix Systems UK Ltd.<BR>
-
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __XEN_H__
-#define __XEN_H__
-
-#include <PiPei.h>
-
-// Physical address of OVMF info
-#define OVMF_INFO_PHYSICAL_ADDRESS 0x00001000
-
-// This structure must match the definition on Xen side
-#pragma pack(1)
-typedef struct {
- CHAR8 Signature[14]; // XenHVMOVMF\0
- UINT8 Length; // Length of this structure
- UINT8 Checksum; // Set such that the sum over bytes 0..length == 0
- //
- // Physical address of an array of TablesCount elements.
- //
- // Each element contains the physical address of a BIOS table.
- //
- EFI_PHYSICAL_ADDRESS Tables;
- UINT32 TablesCount;
- //
- // Physical address of the E820 table, contains E820EntriesCount entries.
- //
- EFI_PHYSICAL_ADDRESS E820;
- UINT32 E820EntriesCount;
-} EFI_XEN_OVMF_INFO;
-#pragma pack()
-
-#endif /* __XEN_H__ */
diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index c08aa2e45a53..2deec128f464 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -132,16 +132,12 @@ QemuUc32BaseInitialization (
VOID
)
{
UINT32 LowerMemorySize;
UINT32 Uc32Size;
- if (mXen) {
- return;
- }
-
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
// On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
// starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
// setting PcdPciExpressBaseAddress such that describing the
// [PcdPciExpressBaseAddress, 4GB) range require a very small number of
@@ -816,17 +812,13 @@ QemuInitializeRam (
**/
VOID
InitializeRamRegions (
VOID
)
{
- if (!mXen) {
- QemuInitializeRam ();
- } else {
- XenPublishRamRegions ();
- }
+ QemuInitializeRam ();
if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {
//
// This is the memory range that will be used for PEI on S3 resume
//
BuildMemoryAllocationHob (
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 96468701e3b8..d3a20122a2ea 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -143,103 +143,100 @@ MemMapInitialization (
VOID
)
{
UINT64 PciIoBase;
UINT64 PciIoSize;
RETURN_STATUS PcdStatus;
+ UINT32 TopOfLowRam;
+ UINT64 PciExBarBase;
+ UINT32 PciBase;
+ UINT32 PciSize;
PciIoBase = 0xC000;
PciIoSize = 0x4000;
//
// Video memory + Legacy BIOS region
//
AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
- if (!mXen) {
- UINT32 TopOfLowRam;
- UINT64 PciExBarBase;
- UINT32 PciBase;
- UINT32 PciSize;
-
- TopOfLowRam = GetSystemMemorySizeBelow4gb ();
- PciExBarBase = 0;
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
- //
- // The MMCONFIG area is expected to fall between the top of low RAM and
- // the base of the 32-bit PCI host aperture.
- //
- PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
- ASSERT (TopOfLowRam <= PciExBarBase);
- ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
- PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
- } else {
- ASSERT (TopOfLowRam <= mQemuUc32Base);
- PciBase = mQemuUc32Base;
- }
-
+ TopOfLowRam = GetSystemMemorySizeBelow4gb ();
+ PciExBarBase = 0;
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
- // address purpose size
- // ------------ -------- -------------------------
- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
- // 0xFC000000 gap 44 MB
- // 0xFEC00000 IO-APIC 4 KB
- // 0xFEC01000 gap 1020 KB
- // 0xFED00000 HPET 1 KB
- // 0xFED00400 gap 111 KB
- // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
- // 0xFED20000 gap 896 KB
- // 0xFEE00000 LAPIC 1 MB
+ // The MMCONFIG area is expected to fall between the top of low RAM and
+ // the base of the 32-bit PCI host aperture.
//
- PciSize = 0xFC000000 - PciBase;
- AddIoMemoryBaseSizeHob (PciBase, PciSize);
- PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
- ASSERT_RETURN_ERROR (PcdStatus);
- PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
- ASSERT_RETURN_ERROR (PcdStatus);
+ PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
+ ASSERT (TopOfLowRam <= PciExBarBase);
+ ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
+ PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
+ } else {
+ ASSERT (TopOfLowRam <= mQemuUc32Base);
+ PciBase = mQemuUc32Base;
+ }
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
- AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
- AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
- //
- // Note: there should be an
- //
- // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
- //
- // call below, just like the one above for RCBA. However, Linux insists
- // that the MMCONFIG area be marked in the E820 or UEFI memory map as
- // "reserved memory" -- Linux does not content itself with a simple gap
- // in the memory map wherever the MCFG ACPI table points to.
- //
- // This appears to be a safety measure. The PCI Firmware Specification
- // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
- // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
- // [...]". (Emphasis added here.)
- //
- // Normally we add memory resource descriptor HOBs in
- // QemuInitializeRam(), and pre-allocate from those with memory
- // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
- // is most definitely not RAM; so, as an exception, cover it with
- // uncacheable reserved memory right here.
- //
- AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
- BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
- EfiReservedMemoryType);
- }
- AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
+ //
+ // address purpose size
+ // ------------ -------- -------------------------
+ // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
+ // 0xFC000000 gap 44 MB
+ // 0xFEC00000 IO-APIC 4 KB
+ // 0xFEC01000 gap 1020 KB
+ // 0xFED00000 HPET 1 KB
+ // 0xFED00400 gap 111 KB
+ // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
+ // 0xFED20000 gap 896 KB
+ // 0xFEE00000 LAPIC 1 MB
+ //
+ PciSize = 0xFC000000 - PciBase;
+ AddIoMemoryBaseSizeHob (PciBase, PciSize);
+ PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
+ ASSERT_RETURN_ERROR (PcdStatus);
+ PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
+ ASSERT_RETURN_ERROR (PcdStatus);
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
+ AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+ AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
+ //
+ // Note: there should be an
+ //
+ // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
//
- // On Q35, the IO Port space is available for PCI resource allocations from
- // 0x6000 up.
+ // call below, just like the one above for RCBA. However, Linux insists
+ // that the MMCONFIG area be marked in the E820 or UEFI memory map as
+ // "reserved memory" -- Linux does not content itself with a simple gap
+ // in the memory map wherever the MCFG ACPI table points to.
//
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
- PciIoBase = 0x6000;
- PciIoSize = 0xA000;
- ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
- }
+ // This appears to be a safety measure. The PCI Firmware Specification
+ // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
+ // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
+ // [...]". (Emphasis added here.)
+ //
+ // Normally we add memory resource descriptor HOBs in
+ // QemuInitializeRam(), and pre-allocate from those with memory
+ // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
+ // is most definitely not RAM; so, as an exception, cover it with
+ // uncacheable reserved memory right here.
+ //
+ AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
+ BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
+ EfiReservedMemoryType);
+ }
+ AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
+
+ //
+ // On Q35, the IO Port space is available for PCI resource allocations from
+ // 0x6000 up.
+ //
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+ PciIoBase = 0x6000;
+ PciIoSize = 0xA000;
+ ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
}
//
// Add PCI IO Port space available for PCI resource allocations.
//
BuildResourceDescriptorHob (
@@ -368,15 +365,15 @@ MiscInitialization (
return;
}
PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
ASSERT_RETURN_ERROR (PcdStatus);
//
- // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
- // has been configured (e.g., by Xen) and skip the setup here.
- // This matches the logic in AcpiTimerLibConstructor ().
+ // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has
+ // been configured and skip the setup here. This matches the logic in
+ // AcpiTimerLibConstructor ().
//
if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
//
// The PEI phase should be exited with fully accessibe ACPI PM IO space:
// 1. set PMBA
//
@@ -700,14 +697,12 @@ InitializePlatform (
EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
DebugDumpCmos ();
- XenDetect ();
-
if (QemuFwCfgS3Enabled ()) {
DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));
mS3Supported = TRUE;
Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
ASSERT_EFI_ERROR (Status);
}
@@ -732,17 +727,12 @@ InitializePlatform (
PublishPeiMemory ();
QemuUc32BaseInitialization ();
InitializeRamRegions ();
- if (mXen) {
- DEBUG ((DEBUG_INFO, "Xen was detected\n"));
- InitializeXen ();
- }
-
if (mBootMode != BOOT_ON_S3_RESUME) {
if (!FeaturePcdGet (PcdSmmSmramRequire)) {
ReserveEmuVariableNvStore ();
}
PeiFvInitialization ();
MemTypeInfoInitialization ();
diff --git a/OvmfPkg/PlatformPei/Xen.c b/OvmfPkg/PlatformPei/Xen.c
deleted file mode 100644
index 104922c67e7e..000000000000
--- a/OvmfPkg/PlatformPei/Xen.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/**@file
- Xen Platform PEI support
-
- Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2011, Andrei Warkentin <andreiw at motorola.com>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-//
-// The package level header files this module uses
-//
-#include <PiPei.h>
-
-//
-// The Library classes this module consumes
-//
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PcdLib.h>
-#include <Guid/XenInfo.h>
-#include <IndustryStandard/E820.h>
-#include <Library/ResourcePublicationLib.h>
-#include <Library/MtrrLib.h>
-
-#include "Platform.h"
-#include "Xen.h"
-
-BOOLEAN mXen = FALSE;
-
-STATIC UINT32 mXenLeaf = 0;
-
-EFI_XEN_INFO mXenInfo;
-
-/**
- Returns E820 map provided by Xen
-
- @param Entries Pointer to E820 map
- @param Count Number of entries
-
- @return EFI_STATUS
-**/
-EFI_STATUS
-XenGetE820Map (
- EFI_E820_ENTRY64 **Entries,
- UINT32 *Count
- )
-{
- EFI_XEN_OVMF_INFO *Info =
- (EFI_XEN_OVMF_INFO *)(UINTN) OVMF_INFO_PHYSICAL_ADDRESS;
-
- if (AsciiStrCmp ((CHAR8 *) Info->Signature, "XenHVMOVMF")) {
- return EFI_NOT_FOUND;
- }
-
- ASSERT (Info->E820 < MAX_ADDRESS);
- *Entries = (EFI_E820_ENTRY64 *)(UINTN) Info->E820;
- *Count = Info->E820EntriesCount;
-
- return EFI_SUCCESS;
-}
-
-/**
- Connects to the Hypervisor.
-
- @param XenLeaf CPUID index used to connect.
-
- @return EFI_STATUS
-
-**/
-EFI_STATUS
-XenConnect (
- UINT32 XenLeaf
- )
-{
- UINT32 Index;
- UINT32 TransferReg;
- UINT32 TransferPages;
- UINT32 XenVersion;
-
- AsmCpuid (XenLeaf + 2, &TransferPages, &TransferReg, NULL, NULL);
- mXenInfo.HyperPages = AllocatePages (TransferPages);
- if (!mXenInfo.HyperPages) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- for (Index = 0; Index < TransferPages; Index++) {
- AsmWriteMsr64 (TransferReg,
- (UINTN) mXenInfo.HyperPages +
- (Index << EFI_PAGE_SHIFT) + Index);
- }
-
- AsmCpuid (XenLeaf + 1, &XenVersion, NULL, NULL, NULL);
- DEBUG ((DEBUG_ERROR, "Detected Xen version %d.%d\n",
- XenVersion >> 16, XenVersion & 0xFFFF));
- mXenInfo.VersionMajor = (UINT16)(XenVersion >> 16);
- mXenInfo.VersionMinor = (UINT16)(XenVersion & 0xFFFF);
-
- BuildGuidDataHob (
- &gEfiXenInfoGuid,
- &mXenInfo,
- sizeof(mXenInfo)
- );
-
- return EFI_SUCCESS;
-}
-
-/**
- Figures out if we are running inside Xen HVM.
-
- @retval TRUE Xen was detected
- @retval FALSE Xen was not detected
-
-**/
-BOOLEAN
-XenDetect (
- VOID
- )
-{
- UINT8 Signature[13];
-
- if (mXenLeaf != 0) {
- return TRUE;
- }
-
- Signature[12] = '\0';
- for (mXenLeaf = 0x40000000; mXenLeaf < 0x40010000; mXenLeaf += 0x100) {
- AsmCpuid (mXenLeaf,
- NULL,
- (UINT32 *) &Signature[0],
- (UINT32 *) &Signature[4],
- (UINT32 *) &Signature[8]);
-
- if (!AsciiStrCmp ((CHAR8 *) Signature, "XenVMMXenVMM")) {
- mXen = TRUE;
- return TRUE;
- }
- }
-
- mXenLeaf = 0;
- return FALSE;
-}
-
-
-VOID
-XenPublishRamRegions (
- VOID
- )
-{
- EFI_E820_ENTRY64 *E820Map;
- UINT32 E820EntriesCount;
- EFI_STATUS Status;
-
- if (!mXen) {
- return;
- }
-
- DEBUG ((DEBUG_INFO, "Using memory map provided by Xen\n"));
-
- //
- // Parse RAM in E820 map
- //
- E820EntriesCount = 0;
- Status = XenGetE820Map (&E820Map, &E820EntriesCount);
-
- ASSERT_EFI_ERROR (Status);
-
- if (E820EntriesCount > 0) {
- EFI_E820_ENTRY64 *Entry;
- UINT32 Loop;
-
- for (Loop = 0; Loop < E820EntriesCount; Loop++) {
- Entry = E820Map + Loop;
-
- //
- // Only care about RAM
- //
- if (Entry->Type != EfiAcpiAddressRangeMemory) {
- continue;
- }
-
- AddMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length);
-
- MtrrSetMemoryAttribute (Entry->BaseAddr, Entry->Length, CacheWriteBack);
- }
- }
-}
-
-
-/**
- Perform Xen PEI initialization.
-
- @return EFI_SUCCESS Xen initialized successfully
- @return EFI_NOT_FOUND Not running under Xen
-
-**/
-EFI_STATUS
-InitializeXen (
- VOID
- )
-{
- RETURN_STATUS PcdStatus;
-
- if (mXenLeaf == 0) {
- return EFI_NOT_FOUND;
- }
-
- XenConnect (mXenLeaf);
-
- //
- // Reserve away HVMLOADER reserved memory [0xFC000000,0xFD000000).
- // This needs to match HVMLOADER RESERVED_MEMBASE/RESERVED_MEMSIZE.
- //
- AddReservedMemoryBaseSizeHob (0xFC000000, 0x1000000, FALSE);
-
- PcdStatus = PcdSetBoolS (PcdPciDisableBusEnumeration, TRUE);
- ASSERT_RETURN_ERROR (PcdStatus);
-
- return EFI_SUCCESS;
-}
--
2.19.1.3.g30247aa5d201
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