rpms/valgrind/devel valgrind-3.1.1-amd64-speedup.patch, NONE, 1.1 valgrind-3.1.1-cfa-val-expr.patch, NONE, 1.1 valgrind-3.1.1-glibc24.patch, NONE, 1.1 valgrind-3.1.1-valgrind_h.patch, NONE, 1.1 .cvsignore, 1.8, 1.9 sources, 1.8, 1.9 valgrind.spec, 1.28, 1.29 valgrind-3.1.0-amd64-highbase.patch, 1.1, NONE valgrind-3.1.0-amd64-speedup.patch, 1.1, NONE valgrind-3.1.0-cfa-val-expr.patch, 1.2, NONE valgrind-3.1.0-glibc24.patch, 1.1, NONE valgrind-3.1.0-valgrind_h.patch, 1.1, NONE
fedora-cvs-commits at redhat.com
fedora-cvs-commits at redhat.com
Mon Apr 3 16:55:09 UTC 2006
Author: jakub
Update of /cvs/dist/rpms/valgrind/devel
In directory cvs.devel.redhat.com:/tmp/cvs-serv26828
Modified Files:
.cvsignore sources valgrind.spec
Added Files:
valgrind-3.1.1-amd64-speedup.patch
valgrind-3.1.1-cfa-val-expr.patch valgrind-3.1.1-glibc24.patch
valgrind-3.1.1-valgrind_h.patch
Removed Files:
valgrind-3.1.0-amd64-highbase.patch
valgrind-3.1.0-amd64-speedup.patch
valgrind-3.1.0-cfa-val-expr.patch valgrind-3.1.0-glibc24.patch
valgrind-3.1.0-valgrind_h.patch
Log Message:
3.1.1-1
valgrind-3.1.1-amd64-speedup.patch:
toIR.c | 384 ++++++++++++++++++++++++++++++++---------------------------------
1 files changed, 193 insertions(+), 191 deletions(-)
--- NEW FILE valgrind-3.1.1-amd64-speedup.patch ---
Replaces 188 insn[0] == 0x0F tests with just one, allows for insn[0] != 0x0F
to quickly skip all the 188 if clauses. I haven't analyzed if the compiler
could possibly figure this out itself, certainly it would be hard.
--- valgrind-3.1.1/VEX/priv/toIR.c.jj 2006-03-14 14:16:38.000000000 -0500
+++ valgrind-3.1.1/VEX/priv/toIR.c 2006-04-03 12:44:42.000000000 -0400
@@ -8139,13 +8139,14 @@ DisResult disInstr_AMD64_WRK (
insn = (UChar*)&guest_code[delta];
+ if (insn[0] == 0x0F) {
//.. /* Treat fxsave specially. It should be doable even on an SSE0
//.. (Pentium-II class) CPU. Hence be prepared to handle it on
//.. any subarchitecture variant.
//.. */
//..
//.. /* 0F AE /0 = FXSAVE m512 -- write x87 and SSE state to memory */
-//.. if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xAE
+//.. if (sz == 4 /* && insn[0] == 0x0F */ && insn[1] == 0xAE
//.. && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 0) {
//.. modrm = getUChar(delta+2);
//.. vassert(sz == 4);
@@ -8225,42 +8226,42 @@ DisResult disInstr_AMD64_WRK (
/* 0F 58 = ADDPS -- add 32Fx4 from R/M to R */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x58) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x58) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "addps", Iop_Add32Fx4 );
goto decode_success;
}
/* F3 0F 58 = ADDSS -- add 32F0x4 from R/M to R */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x58) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x58) {
delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "addss", Iop_Add32F0x4 );
goto decode_success;
}
/* 0F 55 = ANDNPS -- G = (not G) and E */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x55) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x55) {
delta = dis_SSE_E_to_G_all_invG( pfx, delta+2, "andnps", Iop_AndV128 );
goto decode_success;
}
/* 0F 54 = ANDPS -- G = G and E */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x54) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x54) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "andps", Iop_AndV128 );
goto decode_success;
}
/* 0F C2 = CMPPS -- 32Fx4 comparison from R/M to R */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xC2) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xC2) {
delta = dis_SSEcmp_E_to_G( pfx, delta+2, "cmpps", True, 4 );
goto decode_success;
}
/* F3 0F C2 = CMPSS -- 32F0x4 comparison from R/M to R */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xC2) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xC2) {
delta = dis_SSEcmp_E_to_G( pfx, delta+2, "cmpss", False, 4 );
goto decode_success;
}
@@ -8268,7 +8269,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 2F = COMISS -- 32F0x4 comparison G,E, and set ZCP */
/* 0F 2E = UCOMISS -- 32F0x4 comparison G,E, and set ZCP */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && (insn[1] == 0x2F || insn[1] == 0x2E)) {
+ /* && insn[0] == 0x0F */ && (insn[1] == 0x2F || insn[1] == 0x2E)) {
IRTemp argL = newTemp(Ity_F32);
IRTemp argR = newTemp(Ity_F32);
modrm = getUChar(delta+2);
@@ -8308,7 +8309,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 2A = CVTPI2PS -- convert 2 x I32 in mem/mmx to 2 x F32 in low
half xmm */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x2A) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x2A) {
IRTemp arg64 = newTemp(Ity_I64);
IRTemp rmode = newTemp(Ity_I32);
@@ -8350,7 +8351,7 @@ DisResult disInstr_AMD64_WRK (
-- sz==4: convert I32 in mem/ireg to F32 in low quarter xmm
-- sz==8: convert I64 in mem/ireg to F32 in low quarter xmm */
if (haveF3no66noF2(pfx) && (sz == 4 || sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x2A) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x2A) {
IRTemp rmode = newTemp(Ity_I32);
assign( rmode, get_sse_roundingmode() );
@@ -8405,7 +8406,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 2C = CVTTPS2PI -- convert 2 x F32 in mem/low half xmm to 2 x
I32 in mmx, rounding towards zero */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && (insn[1] == 0x2D || insn[1] == 0x2C)) {
+ /* && insn[0] == 0x0F */ && (insn[1] == 0x2D || insn[1] == 0x2C)) {
IRTemp dst64 = newTemp(Ity_I64);
IRTemp rmode = newTemp(Ity_I32);
IRTemp f32lo = newTemp(Ity_F32);
@@ -8469,7 +8470,7 @@ DisResult disInstr_AMD64_WRK (
truncating towards zero
*/
if (haveF3no66noF2(pfx)
- && insn[0] == 0x0F
+ /* && insn[0] == 0x0F */
&& (insn[1] == 0x2D || insn[1] == 0x2C)) {
IRTemp rmode = newTemp(Ity_I32);
IRTemp f32lo = newTemp(Ity_F32);
@@ -8515,20 +8516,20 @@ DisResult disInstr_AMD64_WRK (
/* 0F 5E = DIVPS -- div 32Fx4 from R/M to R */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5E) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5E) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "divps", Iop_Div32Fx4 );
goto decode_success;
}
/* F3 0F 5E = DIVSS -- div 32F0x4 from R/M to R */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5E) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5E) {
delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "divss", Iop_Div32F0x4 );
goto decode_success;
}
/* 0F AE /2 = LDMXCSR m32 -- load %mxcsr */
- if (insn[0] == 0x0F && insn[1] == 0xAE
+ if (/* insn[0] == 0x0F && */ insn[1] == 0xAE
&& haveNo66noF2noF3(pfx)
&& !epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) == 2) {
@@ -8578,28 +8579,28 @@ DisResult disInstr_AMD64_WRK (
/* 0F 5F = MAXPS -- max 32Fx4 from R/M to R */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5F) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5F) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "maxps", Iop_Max32Fx4 );
goto decode_success;
}
/* F3 0F 5F = MAXSS -- max 32F0x4 from R/M to R */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5F) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5F) {
delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "maxss", Iop_Max32F0x4 );
goto decode_success;
}
/* 0F 5D = MINPS -- min 32Fx4 from R/M to R */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5D) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5D) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "minps", Iop_Min32Fx4 );
goto decode_success;
}
/* F3 0F 5D = MINSS -- min 32F0x4 from R/M to R */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5D) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5D) {
delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "minss", Iop_Min32F0x4 );
goto decode_success;
}
@@ -8607,7 +8608,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 28 = MOVAPS -- move from E (mem or xmm) to G (xmm). */
/* 0F 10 = MOVUPS -- move from E (mem or xmm) to G (xmm). */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && (insn[1] == 0x28 || insn[1] == 0x10)) {
+ /* && insn[0] == 0x0F */ && (insn[1] == 0x28 || insn[1] == 0x10)) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
putXMMReg( gregOfRexRM(pfx,modrm),
@@ -8629,7 +8630,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 29 = MOVAPS -- move from G (xmm) to E (mem or xmm). */
/* 0F 11 = MOVUPS -- move from G (xmm) to E (mem or xmm). */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && (insn[1] == 0x29 || insn[1] == 0x11)) {
+ /* && insn[0] == 0x0F */ && (insn[1] == 0x29 || insn[1] == 0x11)) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
/* fall through; awaiting test case */
@@ -8646,7 +8647,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 16 = MOVHPS -- move from mem to high half of XMM. */
/* 0F 16 = MOVLHPS -- move from lo half to hi half of XMM. */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x16) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x16) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
delta += 2+1;
@@ -8667,7 +8668,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 17 = MOVHPS -- move from high half of XMM to mem. */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x17) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x17) {
if (!epartIsReg(insn[2])) {
delta += 2;
addr = disAMode ( &alen, pfx, delta, dis_buf, 0 );
@@ -8685,7 +8686,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 12 = MOVLPS -- move from mem to low half of XMM. */
/* OF 12 = MOVHLPS -- from from hi half to lo half of XMM. */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x12) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x12) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
delta += 2+1;
@@ -8707,7 +8708,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 13 = MOVLPS -- move from low half of XMM to mem. */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x13) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x13) {
if (!epartIsReg(insn[2])) {
delta += 2;
addr = disAMode ( &alen, pfx, delta, dis_buf, 0 );
@@ -8725,7 +8726,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 50 = MOVMSKPS - move 4 sign bits from 4 x F32 in xmm(E)
to 4 lowest bits of ireg(G) */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x50) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x50) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
Int src;
@@ -8765,7 +8766,7 @@ DisResult disInstr_AMD64_WRK (
if ( ( (haveNo66noF2noF3(pfx) && sz == 4)
|| (have66noF2noF3(pfx) && sz == 2)
)
- && insn[0] == 0x0F && insn[1] == 0x2B) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x2B) {
modrm = getUChar(delta+2);
if (!epartIsReg(modrm)) {
addr = disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
@@ -8786,7 +8787,7 @@ DisResult disInstr_AMD64_WRK (
So we just leave them alone.
*/
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xE7) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE7) {
modrm = getUChar(delta+2);
if (!epartIsReg(modrm)) {
/* do_MMX_preamble(); Intel docs don't specify this */
@@ -8803,7 +8804,7 @@ DisResult disInstr_AMD64_WRK (
/* F3 0F 10 = MOVSS -- move 32 bits from E (mem or lo 1/4 xmm) to G
(lo 1/4 xmm). If E is mem, upper 3/4 of G is zeroed out. */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x10) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x10) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
putXMMRegLane32( gregOfRexRM(pfx,modrm), 0,
@@ -8826,7 +8827,7 @@ DisResult disInstr_AMD64_WRK (
/* F3 0F 11 = MOVSS -- move 32 bits from G (lo 1/4 xmm) to E (mem
or lo 1/4 xmm). */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x11) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x11) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
/* fall through, we don't yet have a test case */
@@ -8843,21 +8844,21 @@ DisResult disInstr_AMD64_WRK (
/* 0F 59 = MULPS -- mul 32Fx4 from R/M to R */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x59) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x59) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "mulps", Iop_Mul32Fx4 );
goto decode_success;
}
/* F3 0F 59 = MULSS -- mul 32F0x4 from R/M to R */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x59) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x59) {
delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "mulss", Iop_Mul32F0x4 );
goto decode_success;
}
/* 0F 56 = ORPS -- G = G and E */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x56) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x56) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "orps", Iop_OrV128 );
goto decode_success;
}
@@ -8865,7 +8866,7 @@ DisResult disInstr_AMD64_WRK (
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F E0 = PAVGB -- 8x8 unsigned Packed Average, with rounding */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xE0) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE0) {
do_MMX_preamble();
delta = dis_MMXop_regmem_to_reg (
pfx, delta+2, insn[1], "pavgb", False );
@@ -8875,7 +8876,7 @@ DisResult disInstr_AMD64_WRK (
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F E3 = PAVGW -- 16x4 unsigned Packed Average, with rounding */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xE3) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE3) {
do_MMX_preamble();
delta = dis_MMXop_regmem_to_reg (
pfx, delta+2, insn[1], "pavgw", False );
@@ -8886,7 +8887,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F C5 = PEXTRW -- extract 16-bit field from mmx(E) and put
zero-extend of it in ireg(G). */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xC5) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xC5) {
modrm = insn[2];
if (epartIsReg(modrm)) {
IRTemp sV = newTemp(Ity_I64);
@@ -8918,7 +8919,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
put it into the specified lane of mmx(G). */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xC4) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xC4) {
/* Use t0 .. t3 to hold the 4 original 16-bit lanes of the
mmx reg. t4 is the new lane value. t5 is the original
mmx value. t6 is the new mmx value. */
@@ -8963,7 +8964,7 @@ DisResult disInstr_AMD64_WRK (
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F EE = PMAXSW -- 16x4 signed max */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xEE) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xEE) {
do_MMX_preamble();
delta = dis_MMXop_regmem_to_reg (
pfx, delta+2, insn[1], "pmaxsw", False );
@@ -8973,7 +8974,7 @@ DisResult disInstr_AMD64_WRK (
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F DE = PMAXUB -- 8x8 unsigned max */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xDE) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xDE) {
do_MMX_preamble();
delta = dis_MMXop_regmem_to_reg (
pfx, delta+2, insn[1], "pmaxub", False );
@@ -8983,7 +8984,7 @@ DisResult disInstr_AMD64_WRK (
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F EA = PMINSW -- 16x4 signed min */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xEA) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xEA) {
do_MMX_preamble();
delta = dis_MMXop_regmem_to_reg (
pfx, delta+2, insn[1], "pminsw", False );
@@ -8993,7 +8994,7 @@ DisResult disInstr_AMD64_WRK (
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F DA = PMINUB -- 8x8 unsigned min */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xDA) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xDA) {
do_MMX_preamble();
delta = dis_MMXop_regmem_to_reg (
pfx, delta+2, insn[1], "pminub", False );
@@ -9005,7 +9006,7 @@ DisResult disInstr_AMD64_WRK (
mmx(G), turn them into a byte, and put zero-extend of it in
ireg(G). */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xD7) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD7) {
modrm = insn[2];
if (epartIsReg(modrm)) {
do_MMX_preamble();
@@ -9029,7 +9030,7 @@ DisResult disInstr_AMD64_WRK (
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F E4 = PMULUH -- 16x4 hi-half of unsigned widening multiply */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xE4) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE4) {
do_MMX_preamble();
delta = dis_MMXop_regmem_to_reg (
pfx, delta+2, insn[1], "pmuluh", False );
@@ -9040,7 +9041,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 18 /1 = PREFETCH0 -- with various different hints */
/* 0F 18 /2 = PREFETCH1 */
/* 0F 18 /3 = PREFETCH2 */
- if (insn[0] == 0x0F && insn[1] == 0x18
+ if (/* insn[0] == 0x0F && */ insn[1] == 0x18
&& haveNo66noF2noF3(pfx)
&& !epartIsReg(insn[2])
&& gregLO3ofRM(insn[2]) >= 0 && gregLO3ofRM(insn[2]) <= 3) {
@@ -9067,7 +9068,7 @@ DisResult disInstr_AMD64_WRK (
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F F6 = PSADBW -- sum of 8Ux8 absolute differences */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xF6) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xF6) {
do_MMX_preamble();
delta = dis_MMXop_regmem_to_reg (
pfx, delta+2, insn[1], "psadbw", False );
@@ -9077,7 +9078,7 @@ DisResult disInstr_AMD64_WRK (
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F 70 = PSHUFW -- rearrange 4x16 from E(mmx or mem) to G(mmx) */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x70) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x70) {
Int order;
IRTemp sV, dV, s3, s2, s1, s0;
s3 = s2 = s1 = s0 = IRTemp_INVALID;
@@ -9116,7 +9117,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 53 = RCPPS -- approx reciprocal 32Fx4 from R/M to R */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x53) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x53) {
delta = dis_SSE_E_to_G_unary_all( pfx, delta+2,
"rcpps", Iop_Recip32Fx4 );
goto decode_success;
@@ -9124,7 +9125,7 @@ DisResult disInstr_AMD64_WRK (
/* F3 0F 53 = RCPSS -- approx reciprocal 32F0x4 from R/M to R */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x53) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x53) {
delta = dis_SSE_E_to_G_unary_lo32( pfx, delta+2,
"rcpss", Iop_Recip32F0x4 );
goto decode_success;
@@ -9132,7 +9133,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 52 = RSQRTPS -- approx reciprocal sqrt 32Fx4 from R/M to R */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x52) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x52) {
delta = dis_SSE_E_to_G_unary_all( pfx, delta+2,
"rsqrtps", Iop_RSqrt32Fx4 );
goto decode_success;
@@ -9140,7 +9141,7 @@ DisResult disInstr_AMD64_WRK (
/* F3 0F 52 = RSQRTSS -- approx reciprocal sqrt 32F0x4 from R/M to R */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x52) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x52) {
delta = dis_SSE_E_to_G_unary_lo32( pfx, delta+2,
"rsqrtss", Iop_RSqrt32F0x4 );
goto decode_success;
@@ -9148,7 +9149,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F AE /7 = SFENCE -- flush pending operations to memory */
if (haveNo66noF2noF3(pfx)
- && insn[0] == 0x0F && insn[1] == 0xAE
+ /* && insn[0] == 0x0F */ && insn[1] == 0xAE
&& epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) == 7
&& sz == 4) {
delta += 3;
@@ -9161,7 +9162,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F C6 /r ib = SHUFPS -- shuffle packed F32s */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xC6) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xC6) {
Int select;
IRTemp sV, dV;
IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
@@ -9209,7 +9210,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 51 = SQRTPS -- approx sqrt 32Fx4 from R/M to R */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x51) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x51) {
delta = dis_SSE_E_to_G_unary_all( pfx, delta+2,
"sqrtps", Iop_Sqrt32Fx4 );
goto decode_success;
@@ -9217,14 +9218,14 @@ DisResult disInstr_AMD64_WRK (
/* F3 0F 51 = SQRTSS -- approx sqrt 32F0x4 from R/M to R */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x51) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x51) {
delta = dis_SSE_E_to_G_unary_lo32( pfx, delta+2,
"sqrtss", Iop_Sqrt32F0x4 );
goto decode_success;
}
/* 0F AE /3 = STMXCSR m32 -- store %mxcsr */
- if (insn[0] == 0x0F && insn[1] == 0xAE
+ if (/* insn[0] == 0x0F && */ insn[1] == 0xAE
&& haveNo66noF2noF3(pfx)
&& !epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) == 3) {
@@ -9252,14 +9253,14 @@ DisResult disInstr_AMD64_WRK (
/* 0F 5C = SUBPS -- sub 32Fx4 from R/M to R */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5C) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5C) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "subps", Iop_Sub32Fx4 );
goto decode_success;
}
/* F3 0F 5C = SUBSS -- sub 32F0x4 from R/M to R */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5C) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5C) {
delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "subss", Iop_Sub32F0x4 );
goto decode_success;
}
@@ -9268,7 +9269,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 14 = UNPCKLPS -- unpack and interleave low part F32s */
/* These just appear to be special cases of SHUFPS */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && (insn[1] == 0x15 || insn[1] == 0x14)) {
+ /* && insn[0] == 0x0F */ && (insn[1] == 0x15 || insn[1] == 0x14)) {
IRTemp sV, dV;
IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
Bool hi = toBool(insn[1] == 0x15);
@@ -9307,7 +9308,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 57 = XORPS -- G = G and E */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x57) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x57) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "xorps", Iop_XorV128 );
goto decode_success;
}
@@ -9322,13 +9323,13 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 58 = ADDPD -- add 32Fx4 from R/M to R */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x58) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x58) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "addpd", Iop_Add64Fx2 );
goto decode_success;
}
/* F2 0F 58 = ADDSD -- add 64F0x2 from R/M to R */
- if (haveF2no66noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x58) {
+ if (haveF2no66noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x58) {
vassert(sz == 4);
delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "addsd", Iop_Add64F0x2 );
goto decode_success;
@@ -9336,28 +9337,28 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 55 = ANDNPD -- G = (not G) and E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x55) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x55) {
delta = dis_SSE_E_to_G_all_invG( pfx, delta+2, "andnpd", Iop_AndV128 );
goto decode_success;
}
/* 66 0F 54 = ANDPD -- G = G and E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x54) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x54) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "andpd", Iop_AndV128 );
goto decode_success;
}
/* 66 0F C2 = CMPPD -- 64Fx2 comparison from R/M to R */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xC2) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xC2) {
delta = dis_SSEcmp_E_to_G( pfx, delta+2, "cmppd", True, 8 );
goto decode_success;
}
/* F2 0F C2 = CMPSD -- 64F0x2 comparison from R/M to R */
if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xC2) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xC2) {
delta = dis_SSEcmp_E_to_G( pfx, delta+2, "cmpsd", False, 8 );
goto decode_success;
}
@@ -9365,7 +9366,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 2F = COMISD -- 64F0x2 comparison G,E, and set ZCP */
/* 66 0F 2E = UCOMISD -- 64F0x2 comparison G,E, and set ZCP */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && (insn[1] == 0x2F || insn[1] == 0x2E)) {
+ /* && insn[0] == 0x0F */ && (insn[1] == 0x2F || insn[1] == 0x2E)) {
IRTemp argL = newTemp(Ity_F64);
IRTemp argR = newTemp(Ity_F64);
modrm = getUChar(delta+2);
@@ -9402,7 +9403,7 @@ DisResult disInstr_AMD64_WRK (
/* F3 0F E6 = CVTDQ2PD -- convert 2 x I32 in mem/lo half xmm to 2 x
F64 in xmm(G) */
- if (haveF3no66noF2(pfx) && insn[0] == 0x0F && insn[1] == 0xE6) {
+ if (haveF3no66noF2(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0xE6) {
IRTemp arg64 = newTemp(Ity_I64);
if (sz != 4) goto decode_failure;
@@ -9436,7 +9437,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 5B = CVTDQ2PS -- convert 4 x I32 in mem/xmm to 4 x F32 in
xmm(G) */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5B) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5B) {
IRTemp argV = newTemp(Ity_V128);
IRTemp rmode = newTemp(Ity_I32);
@@ -9479,7 +9480,7 @@ DisResult disInstr_AMD64_WRK (
if ( ( (haveF2no66noF3(pfx) && sz == 4)
|| (have66noF2noF3(pfx) && sz == 2)
)
- && insn[0] == 0x0F && insn[1] == 0xE6) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE6) {
IRTemp argV = newTemp(Ity_V128);
IRTemp rmode = newTemp(Ity_I32);
Bool r2zero = toBool(sz == 2);
@@ -9532,7 +9533,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 2C = CVTTPD2PI -- convert 2 x F64 in mem/xmm to 2 x
I32 in mmx, rounding towards zero */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && (insn[1] == 0x2D || insn[1] == 0x2C)) {
+ /* && insn[0] == 0x0F */ && (insn[1] == 0x2D || insn[1] == 0x2C)) {
IRTemp dst64 = newTemp(Ity_I64);
IRTemp rmode = newTemp(Ity_I32);
IRTemp f64lo = newTemp(Ity_F64);
@@ -9586,7 +9587,7 @@ DisResult disInstr_AMD64_WRK (
been nicer to merge them together, but the insn[] offsets differ
by one. */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x5A) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5A) {
IRTemp argV = newTemp(Ity_V128);
IRTemp rmode = newTemp(Ity_I32);
@@ -9629,7 +9630,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 2A = CVTPI2PD -- convert 2 x I32 in mem/mmx to 2 x F64 in
xmm(G) */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x2A) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x2A) {
IRTemp arg64 = newTemp(Ity_I64);
modrm = getUChar(delta+2);
@@ -9667,7 +9668,7 @@ DisResult disInstr_AMD64_WRK (
if ( ( (have66noF2noF3(pfx) && sz == 2)
|| (haveF3no66noF2(pfx) && sz == 4)
)
- && insn[0] == 0x0F && insn[1] == 0x5B) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5B) {
IRTemp argV = newTemp(Ity_V128);
IRTemp rmode = newTemp(Ity_I32);
Bool r2zero = toBool(sz == 4);
@@ -9715,7 +9716,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F 5A = CVTPS2PD -- convert 2 x F32 in low half mem/xmm to 2 x
F64 in xmm(G). */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5A) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5A) {
IRTemp f32lo = newTemp(Ity_F32);
IRTemp f32hi = newTemp(Ity_F32);
@@ -9757,7 +9758,7 @@ DisResult disInstr_AMD64_WRK (
truncating towards zero
*/
if (haveF2no66noF3(pfx)
- && insn[0] == 0x0F
+ /* && insn[0] == 0x0F */
&& (insn[1] == 0x2D || insn[1] == 0x2C)) {
IRTemp rmode = newTemp(Ity_I32);
IRTemp f64lo = newTemp(Ity_F64);
@@ -9800,7 +9801,7 @@ DisResult disInstr_AMD64_WRK (
/* F2 0F 5A = CVTSD2SS -- convert F64 in mem/low half xmm to F32 in
low 1/4 xmm(G), according to prevailing SSE rounding mode */
if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5A) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5A) {
IRTemp rmode = newTemp(Ity_I32);
IRTemp f64lo = newTemp(Ity_F64);
vassert(sz == 4);
@@ -9833,7 +9834,7 @@ DisResult disInstr_AMD64_WRK (
when sz==8 -- convert I64 in mem/ireg to F64 in low half xmm
*/
if (haveF2no66noF3(pfx) && (sz == 4 || sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x2A) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x2A) {
modrm = getUChar(delta+2);
if (sz == 4) {
@@ -9885,7 +9886,7 @@ DisResult disInstr_AMD64_WRK (
/* F3 0F 5A = CVTSS2SD -- convert F32 in mem/low 1/4 xmm to F64 in
low half xmm(G) */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5A) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5A) {
IRTemp f32lo = newTemp(Ity_F32);
modrm = getUChar(delta+2);
@@ -9910,13 +9911,13 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 5E = DIVPD -- div 64Fx2 from R/M to R */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x5E) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5E) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "divpd", Iop_Div64Fx2 );
goto decode_success;
}
/* F2 0F 5E = DIVSD -- div 64F0x2 from R/M to R */
- if (haveF2no66noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x5E) {
+ if (haveF2no66noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x5E) {
vassert(sz == 4);
delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "divsd", Iop_Div64F0x2 );
goto decode_success;
@@ -9925,7 +9926,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F AE /5 = LFENCE -- flush pending operations to memory */
/* 0F AE /6 = MFENCE -- flush pending operations to memory */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xAE
+ /* && insn[0] == 0x0F */ && insn[1] == 0xAE
&& epartIsReg(insn[2])
&& (gregLO3ofRM(insn[2]) == 5 || gregLO3ofRM(insn[2]) == 6)) {
delta += 3;
@@ -9938,28 +9939,28 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 5F = MAXPD -- max 64Fx2 from R/M to R */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x5F) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5F) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "maxpd", Iop_Max64Fx2 );
goto decode_success;
}
/* F2 0F 5F = MAXSD -- max 64F0x2 from R/M to R */
if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5F) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5F) {
delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "maxsd", Iop_Max64F0x2 );
goto decode_success;
}
/* 66 0F 5D = MINPD -- min 64Fx2 from R/M to R */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x5D) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5D) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "minpd", Iop_Min64Fx2 );
goto decode_success;
}
/* F2 0F 5D = MINSD -- min 64F0x2 from R/M to R */
if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5D) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5D) {
delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "minsd", Iop_Min64F0x2 );
goto decode_success;
}
@@ -9968,7 +9969,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 10 = MOVUPD -- move from E (mem or xmm) to G (xmm). */
/* 66 0F 6F = MOVDQA -- move from E (mem or xmm) to G (xmm). */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F
+ /* && insn[0] == 0x0F */
&& (insn[1] == 0x28 || insn[1] == 0x10 || insn[1] == 0x6F)) {
HChar* wot = insn[1]==0x28 ? "apd" :
insn[1]==0x10 ? "upd" : "dqa";
@@ -9992,7 +9993,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 29 = MOVAPD -- move from G (xmm) to E (mem or xmm). */
/* 66 0F 11 = MOVUPD -- move from G (xmm) to E (mem or xmm). */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F
+ if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */
&& (insn[1] == 0x29 || insn[1] == 0x11)) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
@@ -10009,7 +10010,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 6E = MOVD from ireg32/m32 to xmm lo 1/4, zeroing high 3/4 of xmm. */
/* or from ireg64/m64 to xmm lo 1/2, zeroing high 1/2 of xmm. */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x6E) {
+ if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x6E) {
vassert(sz == 2 || sz == 8);
if (sz == 2) sz = 4;
modrm = getUChar(delta+2);
@@ -10047,7 +10048,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 7E = MOVD from xmm low 1/4 to ireg32 or m32. */
/* or from xmm low 1/2 to ireg64 or m64. */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x7E) {
+ if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x7E) {
if (sz == 2) sz = 4;
vassert(sz == 4 || sz == 8);
modrm = getUChar(delta+2);
@@ -10079,7 +10080,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 7F = MOVDQA -- move from G (xmm) to E (mem or xmm). */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x7F) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x7F) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
delta += 2+1;
@@ -10098,7 +10099,7 @@ DisResult disInstr_AMD64_WRK (
/* F3 0F 6F = MOVDQU -- move from E (mem or xmm) to G (xmm). */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x6F) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x6F) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
putXMMReg( gregOfRexRM(pfx,modrm),
@@ -10119,7 +10120,7 @@ DisResult disInstr_AMD64_WRK (
/* F3 0F 7F = MOVDQU -- move from G (xmm) to E (mem or xmm). */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x7F) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x7F) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
goto decode_failure; /* awaiting test case */
@@ -10139,7 +10140,7 @@ DisResult disInstr_AMD64_WRK (
/* F2 0F D6 = MOVDQ2Q -- move from E (lo half xmm, not mem) to G (mmx). */
if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xD6) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD6) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
do_MMX_preamble();
@@ -10158,7 +10159,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 16 = MOVHPD -- move from mem to high half of XMM. */
/* These seems identical to MOVHPS. This instruction encoding is
completely crazy. */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x16) {
+ if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x16) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
/* fall through; apparently reg-reg is not possible */
@@ -10175,7 +10176,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 17 = MOVHPD -- move from high half of XMM to mem. */
/* Again, this seems identical to MOVHPS. */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x17) {
+ if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x17) {
if (!epartIsReg(insn[2])) {
delta += 2;
addr = disAMode ( &alen, pfx, delta, dis_buf, 0 );
@@ -10192,7 +10193,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 12 = MOVLPD -- move from mem to low half of XMM. */
/* Identical to MOVLPS ? */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x12) {
+ if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x12) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
/* fall through; apparently reg-reg is not possible */
@@ -10210,7 +10211,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 13 = MOVLPD -- move from low half of XMM to mem. */
/* Identical to MOVLPS ? */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x13) {
+ if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x13) {
modrm = getUChar(delta+2);
if (!epartIsReg(modrm)) {
addr = disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
@@ -10228,7 +10229,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 50 = MOVMSKPD - move 2 sign bits from 2 x F64 in xmm(E) to
2 lowest bits of ireg(G) */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x50) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x50) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
Int src;
@@ -10255,7 +10256,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F E7 = MOVNTDQ -- for us, just a plain SSE store. */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE7) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE7) {
modrm = getUChar(delta+2);
if (!epartIsReg(modrm)) {
addr = disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
@@ -10271,7 +10272,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F C3 = MOVNTI -- for us, just a plain ireg store. */
if (haveNo66noF2noF3(pfx) &&
- insn[0] == 0x0F && insn[1] == 0xC3) {
+ /* insn[0] == 0x0F && */ insn[1] == 0xC3) {
vassert(sz == 4 || sz == 8);
modrm = getUChar(delta+2);
if (!epartIsReg(modrm)) {
@@ -10287,7 +10288,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F D6 = MOVQ -- move 64 bits from G (lo half xmm) to E (mem
or lo half xmm). */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0xD6) {
+ if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0xD6) {
vassert(sz == 2);
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
@@ -10306,7 +10307,7 @@ DisResult disInstr_AMD64_WRK (
/* F3 0F D6 = MOVQ2DQ -- move from E (mmx) to G (lo half xmm, zero
hi half). */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xD6) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD6) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
do_MMX_preamble();
@@ -10328,10 +10329,10 @@ DisResult disInstr_AMD64_WRK (
G (lo half xmm). If E is mem, upper half of G is zeroed out.
If E is reg, upper half of G is unchanged. */
if ( (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x10)
+ /* && insn[0] == 0x0F */ && insn[1] == 0x10)
||
(haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x7E)
+ /* && insn[0] == 0x0F */ && insn[1] == 0x7E)
) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
@@ -10359,7 +10360,7 @@ DisResult disInstr_AMD64_WRK (
/* F2 0F 11 = MOVSD -- move 64 bits from G (lo half xmm) to E (mem
or lo half xmm). */
if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x11) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x11) {
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
/* fall through, we don't yet have a test case */
@@ -10376,28 +10377,28 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 59 = MULPD -- mul 64Fx2 from R/M to R */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x59) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x59) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "mulpd", Iop_Mul64Fx2 );
goto decode_success;
}
/* F2 0F 59 = MULSD -- mul 64F0x2 from R/M to R */
if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x59) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x59) {
delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "mulsd", Iop_Mul64F0x2 );
goto decode_success;
}
/* 66 0F 56 = ORPD -- G = G and E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x56) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x56) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "orpd", Iop_OrV128 );
goto decode_success;
}
/* 66 0F C6 /r ib = SHUFPD -- shuffle packed F64s */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xC6) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xC6) {
Int select;
IRTemp sV = newTemp(Ity_V128);
IRTemp dV = newTemp(Ity_V128);
@@ -10447,14 +10448,14 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 51 = SQRTPD -- approx sqrt 64Fx2 from R/M to R */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x51) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x51) {
delta = dis_SSE_E_to_G_unary_all( pfx, delta+2,
"sqrtpd", Iop_Sqrt64Fx2 );
goto decode_success;
}
/* F2 0F 51 = SQRTSD -- approx sqrt 64F0x2 from R/M to R */
- if (haveF2no66noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x51) {
+ if (haveF2no66noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x51) {
vassert(sz == 4);
delta = dis_SSE_E_to_G_unary_lo64( pfx, delta+2,
"sqrtsd", Iop_Sqrt64F0x2 );
@@ -10463,13 +10464,13 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 5C = SUBPD -- sub 64Fx2 from R/M to R */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x5C) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x5C) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "subpd", Iop_Sub64Fx2 );
goto decode_success;
}
/* F2 0F 5C = SUBSD -- sub 64F0x2 from R/M to R */
- if (haveF2no66noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x5C) {
+ if (haveF2no66noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x5C) {
vassert(sz == 4);
delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "subsd", Iop_Sub64F0x2 );
goto decode_success;
@@ -10480,7 +10481,7 @@ DisResult disInstr_AMD64_WRK (
/* These just appear to be special cases of SHUFPS */
if (have66noF2noF3(pfx)
&& sz == 2 /* could be 8 if rex also present */
- && insn[0] == 0x0F && (insn[1] == 0x15 || insn[1] == 0x14)) {
+ /* && insn[0] == 0x0F */ && (insn[1] == 0x15 || insn[1] == 0x14)) {
IRTemp s1 = newTemp(Ity_I64);
IRTemp s0 = newTemp(Ity_I64);
IRTemp d1 = newTemp(Ity_I64);
@@ -10525,14 +10526,14 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 57 = XORPD -- G = G xor E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x57) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x57) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "xorpd", Iop_XorV128 );
goto decode_success;
}
/* 66 0F 6B = PACKSSDW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x6B) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x6B) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"packssdw", Iop_QNarrow32Sx4, True );
goto decode_success;
@@ -10540,7 +10541,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 63 = PACKSSWB */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x63) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x63) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"packsswb", Iop_QNarrow16Sx8, True );
goto decode_success;
@@ -10548,7 +10549,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 67 = PACKUSWB */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x67) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x67) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"packuswb", Iop_QNarrow16Ux8, True );
goto decode_success;
@@ -10556,7 +10557,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F FC = PADDB */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xFC) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xFC) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"paddb", Iop_Add8x16, False );
goto decode_success;
@@ -10564,7 +10565,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F FE = PADDD */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xFE) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xFE) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"paddd", Iop_Add32x4, False );
goto decode_success;
@@ -10573,7 +10574,7 @@ DisResult disInstr_AMD64_WRK (
/* ***--- this is an MMX class insn introduced in SSE2 ---*** */
/* 0F D4 = PADDQ -- add 64x1 */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xD4) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD4) {
do_MMX_preamble();
delta = dis_MMXop_regmem_to_reg (
pfx, delta+2, insn[1], "paddq", False );
@@ -10582,7 +10583,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F D4 = PADDQ */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD4) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD4) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"paddq", Iop_Add64x2, False );
goto decode_success;
@@ -10590,7 +10591,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F FD = PADDW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xFD) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xFD) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"paddw", Iop_Add16x8, False );
goto decode_success;
@@ -10598,7 +10599,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F EC = PADDSB */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEC) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xEC) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"paddsb", Iop_QAdd8Sx16, False );
goto decode_success;
@@ -10606,7 +10607,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F ED = PADDSW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xED) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xED) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"paddsw", Iop_QAdd16Sx8, False );
goto decode_success;
@@ -10614,7 +10615,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F DC = PADDUSB */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDC) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xDC) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"paddusb", Iop_QAdd8Ux16, False );
goto decode_success;
@@ -10622,7 +10623,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F DD = PADDUSW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDD) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xDD) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"paddusw", Iop_QAdd16Ux8, False );
goto decode_success;
@@ -10630,21 +10631,21 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F DB = PAND */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDB) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xDB) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "pand", Iop_AndV128 );
goto decode_success;
}
/* 66 0F DF = PANDN */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDF) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xDF) {
delta = dis_SSE_E_to_G_all_invG( pfx, delta+2, "pandn", Iop_AndV128 );
goto decode_success;
}
/* 66 0F E0 = PAVGB */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE0) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE0) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pavgb", Iop_Avg8Ux16, False );
goto decode_success;
@@ -10652,7 +10653,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F E3 = PAVGW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE3) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE3) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pavgw", Iop_Avg16Ux8, False );
goto decode_success;
@@ -10660,7 +10661,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 74 = PCMPEQB */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x74) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x74) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pcmpeqb", Iop_CmpEQ8x16, False );
goto decode_success;
@@ -10668,7 +10669,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 76 = PCMPEQD */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x76) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x76) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pcmpeqd", Iop_CmpEQ32x4, False );
goto decode_success;
@@ -10676,7 +10677,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 75 = PCMPEQW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x75) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x75) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pcmpeqw", Iop_CmpEQ16x8, False );
goto decode_success;
@@ -10684,7 +10685,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 64 = PCMPGTB */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x64) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x64) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pcmpgtb", Iop_CmpGT8Sx16, False );
goto decode_success;
@@ -10692,7 +10693,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 66 = PCMPGTD */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x66) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x66) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pcmpgtd", Iop_CmpGT32Sx4, False );
goto decode_success;
@@ -10700,7 +10701,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 65 = PCMPGTW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x65) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x65) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pcmpgtw", Iop_CmpGT16Sx8, False );
goto decode_success;
@@ -10709,7 +10710,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F C5 = PEXTRW -- extract 16-bit field from xmm(E) and put
zero-extend of it in ireg(G). */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xC5) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xC5) {
modrm = insn[2];
if (epartIsReg(modrm)) {
t5 = newTemp(Ity_V128);
@@ -10742,7 +10743,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
put it into the specified lane of xmm(G). */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xC4) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xC4) {
Int lane;
t4 = newTemp(Ity_I16);
modrm = insn[2];
@@ -10771,7 +10772,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F EE = PMAXSW -- 16x8 signed max */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEE) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xEE) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pmaxsw", Iop_Max16Sx8, False );
goto decode_success;
@@ -10779,7 +10780,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F DE = PMAXUB -- 8x16 unsigned max */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDE) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xDE) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pmaxub", Iop_Max8Ux16, False );
goto decode_success;
@@ -10787,7 +10788,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F EA = PMINSW -- 16x8 signed min */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEA) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xEA) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pminsw", Iop_Min16Sx8, False );
goto decode_success;
@@ -10795,7 +10796,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F DA = PMINUB -- 8x16 unsigned min */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDA) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xDA) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pminub", Iop_Min8Ux16, False );
goto decode_success;
@@ -10807,7 +10808,7 @@ DisResult disInstr_AMD64_WRK (
therefore and call a helper. */
/* UInt x86g_calculate_sse_pmovmskb ( ULong w64hi, ULong w64lo ); */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD7) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD7) {
modrm = insn[2];
if (epartIsReg(modrm)) {
t0 = newTemp(Ity_I64);
@@ -10831,7 +10832,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F E4 = PMULHUW -- 16x8 hi-half of unsigned widening multiply */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE4) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE4) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pmulhuw", Iop_MulHi16Ux8, False );
goto decode_success;
@@ -10839,7 +10840,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F E5 = PMULHW -- 16x8 hi-half of signed widening multiply */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE5) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE5) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pmulhw", Iop_MulHi16Sx8, False );
goto decode_success;
@@ -10847,7 +10848,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F D5 = PMULHL -- 16x8 multiply */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD5) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD5) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"pmullw", Iop_Mul16x8, False );
goto decode_success;
@@ -10857,7 +10858,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F F4 = PMULUDQ -- unsigned widening multiply of 32-lanes 0 x
0 to form 64-bit result */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xF4) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xF4) {
IRTemp sV = newTemp(Ity_I64);
IRTemp dV = newTemp(Ity_I64);
t1 = newTemp(Ity_I32);
@@ -10893,7 +10894,7 @@ DisResult disInstr_AMD64_WRK (
/* This is a really poor translation -- could be improved if
performance critical */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF4) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xF4) {
IRTemp sV, dV;
IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
sV = newTemp(Ity_V128);
@@ -10929,14 +10930,14 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F EB = POR */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEB) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xEB) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "por", Iop_OrV128 );
goto decode_success;
}
/* 66 0F 70 = PSHUFD -- rearrange 4x32 from E(xmm or mem) to G(xmm) */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x70) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x70) {
Int order;
IRTemp sV, dV, s3, s2, s1, s0;
s3 = s2 = s1 = s0 = IRTemp_INVALID;
@@ -10976,7 +10977,7 @@ DisResult disInstr_AMD64_WRK (
/* F3 0F 70 = PSHUFHW -- rearrange upper half 4x16 from E(xmm or
mem) to G(xmm), and copy lower half */
if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x70) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x70) {
Int order;
IRTemp sVhi, dVhi, sV, dV, s3, s2, s1, s0;
s3 = s2 = s1 = s0 = IRTemp_INVALID;
@@ -11022,7 +11023,7 @@ DisResult disInstr_AMD64_WRK (
/* F2 0F 70 = PSHUFLW -- rearrange lower half 4x16 from E(xmm or
mem) to G(xmm), and copy upper half */
if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x70) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x70) {
Int order;
IRTemp sVlo, dVlo, sV, dV, s3, s2, s1, s0;
s3 = s2 = s1 = s0 = IRTemp_INVALID;
@@ -11067,7 +11068,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 72 /6 ib = PSLLD by immediate */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x72
+ /* && insn[0] == 0x0F */ && insn[1] == 0x72
&& epartIsReg(insn[2])
&& gregLO3ofRM(insn[2]) == 6) {
delta = dis_SSE_shiftE_imm( pfx, delta+2, "pslld", Iop_ShlN32x4 );
@@ -11076,7 +11077,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F F2 = PSLLD by E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF2) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xF2) {
delta = dis_SSE_shiftG_byE( pfx, delta+2, "pslld", Iop_ShlN32x4 );
goto decode_success;
}
@@ -11084,7 +11085,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 73 /7 ib = PSLLDQ by immediate */
/* note, if mem case ever filled in, 1 byte after amode */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x73
+ /* && insn[0] == 0x0F */ && insn[1] == 0x73
&& epartIsReg(insn[2])
&& gregLO3ofRM(insn[2]) == 7) {
IRTemp sV, dV, hi64, lo64, hi64r, lo64r;
@@ -11145,7 +11146,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 73 /6 ib = PSLLQ by immediate */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x73
+ /* && insn[0] == 0x0F */ && insn[1] == 0x73
&& epartIsReg(insn[2])
&& gregLO3ofRM(insn[2]) == 6) {
delta = dis_SSE_shiftE_imm( pfx, delta+2, "psllq", Iop_ShlN64x2 );
@@ -11154,14 +11155,14 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F F3 = PSLLQ by E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF3) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xF3) {
delta = dis_SSE_shiftG_byE( pfx, delta+2, "psllq", Iop_ShlN64x2 );
goto decode_success;
}
/* 66 0F 71 /6 ib = PSLLW by immediate */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x71
+ /* && insn[0] == 0x0F */ && insn[1] == 0x71
&& epartIsReg(insn[2])
&& gregLO3ofRM(insn[2]) == 6) {
delta = dis_SSE_shiftE_imm( pfx, delta+2, "psllw", Iop_ShlN16x8 );
@@ -11170,14 +11171,14 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F F1 = PSLLW by E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF1) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xF1) {
delta = dis_SSE_shiftG_byE( pfx, delta+2, "psllw", Iop_ShlN16x8 );
goto decode_success;
}
/* 66 0F 72 /4 ib = PSRAD by immediate */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x72
+ /* && insn[0] == 0x0F */ && insn[1] == 0x72
&& epartIsReg(insn[2])
&& gregLO3ofRM(insn[2]) == 4) {
delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrad", Iop_SarN32x4 );
@@ -11186,14 +11187,14 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F E2 = PSRAD by E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE2) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE2) {
delta = dis_SSE_shiftG_byE( pfx, delta+2, "psrad", Iop_SarN32x4 );
goto decode_success;
}
/* 66 0F 71 /4 ib = PSRAW by immediate */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x71
+ /* && insn[0] == 0x0F */ && insn[1] == 0x71
&& epartIsReg(insn[2])
&& gregLO3ofRM(insn[2]) == 4) {
delta = dis_SSE_shiftE_imm( pfx, delta+2, "psraw", Iop_SarN16x8 );
@@ -11202,14 +11203,14 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F E1 = PSRAW by E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE1) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE1) {
delta = dis_SSE_shiftG_byE( pfx, delta+2, "psraw", Iop_SarN16x8 );
goto decode_success;
}
/* 66 0F 72 /2 ib = PSRLD by immediate */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x72
+ /* && insn[0] == 0x0F */ && insn[1] == 0x72
&& epartIsReg(insn[2])
&& gregLO3ofRM(insn[2]) == 2) {
delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrld", Iop_ShrN32x4 );
@@ -11218,7 +11219,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F D2 = PSRLD by E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD2) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD2) {
delta = dis_SSE_shiftG_byE( pfx, delta+2, "psrld", Iop_ShrN32x4 );
goto decode_success;
}
@@ -11226,7 +11227,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 73 /3 ib = PSRLDQ by immediate */
/* note, if mem case ever filled in, 1 byte after amode */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x73
+ /* && insn[0] == 0x0F */ && insn[1] == 0x73
&& epartIsReg(insn[2])
&& gregLO3ofRM(insn[2]) == 3) {
IRTemp sV, dV, hi64, lo64, hi64r, lo64r;
@@ -11288,7 +11289,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 73 /2 ib = PSRLQ by immediate */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x73
+ /* && insn[0] == 0x0F */ && insn[1] == 0x73
&& epartIsReg(insn[2])
&& gregLO3ofRM(insn[2]) == 2) {
delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrlq", Iop_ShrN64x2 );
@@ -11297,14 +11298,14 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F D3 = PSRLQ by E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD3) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD3) {
delta = dis_SSE_shiftG_byE( pfx, delta+2, "psrlq", Iop_ShrN64x2 );
goto decode_success;
}
/* 66 0F 71 /2 ib = PSRLW by immediate */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x71
+ /* && insn[0] == 0x0F */ && insn[1] == 0x71
&& epartIsReg(insn[2])
&& gregLO3ofRM(insn[2]) == 2) {
delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrlw", Iop_ShrN16x8 );
@@ -11313,14 +11314,14 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F D1 = PSRLW by E */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD1) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD1) {
delta = dis_SSE_shiftG_byE( pfx, delta+2, "psrlw", Iop_ShrN16x8 );
goto decode_success;
}
/* 66 0F F8 = PSUBB */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF8) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xF8) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"psubb", Iop_Sub8x16, False );
goto decode_success;
@@ -11328,7 +11329,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F FA = PSUBD */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xFA) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xFA) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"psubd", Iop_Sub32x4, False );
goto decode_success;
@@ -11337,7 +11338,7 @@ DisResult disInstr_AMD64_WRK (
/* ***--- this is an MMX class insn introduced in SSE2 ---*** */
/* 0F FB = PSUBQ -- sub 64x1 */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xFB) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xFB) {
do_MMX_preamble();
delta = dis_MMXop_regmem_to_reg (
pfx, delta+2, insn[1], "psubq", False );
@@ -11346,7 +11347,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F FB = PSUBQ */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xFB) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xFB) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"psubq", Iop_Sub64x2, False );
goto decode_success;
@@ -11354,7 +11355,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F F9 = PSUBW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF9) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xF9) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"psubw", Iop_Sub16x8, False );
goto decode_success;
@@ -11362,7 +11363,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F E8 = PSUBSB */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE8) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE8) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"psubsb", Iop_QSub8Sx16, False );
goto decode_success;
@@ -11370,7 +11371,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F E9 = PSUBSW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE9) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xE9) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"psubsw", Iop_QSub16Sx8, False );
goto decode_success;
@@ -11378,7 +11379,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F D8 = PSUBSB */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD8) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD8) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"psubusb", Iop_QSub8Ux16, False );
goto decode_success;
@@ -11386,7 +11387,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F D9 = PSUBSW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD9) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xD9) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"psubusw", Iop_QSub16Ux8, False );
goto decode_success;
@@ -11394,7 +11395,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 68 = PUNPCKHBW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x68) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x68) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"punpckhbw",
Iop_InterleaveHI8x16, True );
@@ -11403,7 +11404,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 6A = PUNPCKHDQ */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x6A) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x6A) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"punpckhdq",
Iop_InterleaveHI32x4, True );
@@ -11412,7 +11413,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 6D = PUNPCKHQDQ */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x6D) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x6D) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"punpckhqdq",
Iop_InterleaveHI64x2, True );
@@ -11421,7 +11422,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 69 = PUNPCKHWD */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x69) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x69) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"punpckhwd",
Iop_InterleaveHI16x8, True );
@@ -11430,7 +11431,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 60 = PUNPCKLBW */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x60) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x60) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"punpcklbw",
Iop_InterleaveLO8x16, True );
@@ -11439,7 +11440,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 62 = PUNPCKLDQ */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x62) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x62) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"punpckldq",
Iop_InterleaveLO32x4, True );
@@ -11448,7 +11449,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 6C = PUNPCKLQDQ */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x6C) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x6C) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"punpcklqdq",
Iop_InterleaveLO64x2, True );
@@ -11457,7 +11458,7 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F 61 = PUNPCKLWD */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x61) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0x61) {
delta = dis_SSEint_E_to_G( pfx, delta+2,
"punpcklwd",
Iop_InterleaveLO16x8, True );
@@ -11466,13 +11467,13 @@ DisResult disInstr_AMD64_WRK (
/* 66 0F EF = PXOR */
if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEF) {
+ /* && insn[0] == 0x0F */ && insn[1] == 0xEF) {
delta = dis_SSE_E_to_G_all( pfx, delta+2, "pxor", Iop_XorV128 );
goto decode_success;
}
//.. //-- /* FXSAVE/FXRSTOR m32 -- load/store the FPU/MMX/SSE state. */
-//.. //-- if (insn[0] == 0x0F && insn[1] == 0xAE
+//.. //-- if (/* insn[0] == 0x0F && */ insn[1] == 0xAE
//.. //-- && (!epartIsReg(insn[2]))
//.. //-- && (gregOfRM(insn[2]) == 1 || gregOfRM(insn[2]) == 0) ) {
//.. //-- Bool store = gregOfRM(insn[2]) == 0;
@@ -11490,7 +11491,7 @@ DisResult disInstr_AMD64_WRK (
/* 0F AE /7 = CLFLUSH -- flush cache line */
if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xAE
+ /* && insn[0] == 0x0F */ && insn[1] == 0xAE
&& !epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) == 7) {
/* This is something of a hack. We need to know the size of the
@@ -11519,6 +11520,7 @@ DisResult disInstr_AMD64_WRK (
DIP("clflush %s\n", dis_buf);
goto decode_success;
}
+ }
/* ---------------------------------------------------- */
valgrind-3.1.1-cfa-val-expr.patch:
dwarf.c | 190 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--
1 files changed, 186 insertions(+), 4 deletions(-)
--- NEW FILE valgrind-3.1.1-cfa-val-expr.patch ---
--- valgrind-3.1.1/coregrind/m_debuginfo/dwarf.c.jj 2005-11-25 07:36:18.000000000 -0500
+++ valgrind-3.1.1/coregrind/m_debuginfo/dwarf.c 2006-03-13 04:11:35.000000000 -0500
@@ -1303,8 +1303,8 @@ void ML_(read_debuginfo_dwarf1) (
8 is the return address (EIP) */
/* Note that we don't support DWARF3 expressions (DW_CFA_expression,
- DW_CFA_def_cfa_expression). The code just reads over them and
- ignores them.
+ DW_CFA_def_cfa_expression, DW_CFA_val_expression). The code just
+ reads over them and ignores them.
*/
/* --------------- Decls --------------- */
@@ -1357,10 +1357,15 @@ enum dwarf_cfa_secondary_ops
DW_CFA_def_cfa_expression = 0x0f, /* DWARF3 only */
DW_CFA_expression = 0x10, /* DWARF3 only */
DW_CFA_offset_extended_sf = 0x11, /* DWARF3 only */
+ DW_CFA_def_cfa_sf = 0x12, /* DWARF3 only */
DW_CFA_def_cfa_offset_sf = 0x13, /* DWARF3 only */
+ DW_CFA_val_offset = 0x14, /* DWARF3 only */
+ DW_CFA_val_offset_sf = 0x15, /* DWARF3 only */
+ DW_CFA_val_expression = 0x16, /* DWARF3 only */
DW_CFA_lo_user = 0x1c,
DW_CFA_GNU_window_save = 0x2d, /* GNU extension */
DW_CFA_GNU_args_size = 0x2e, /* GNU extension */
+ DW_CFA_GNU_negative_offset_extended = 0x2f, /* GNU extension */
DW_CFA_hi_user = 0x3f
};
@@ -1393,7 +1398,8 @@ enum dwarf_cfa_secondary_ops
*/
typedef
struct {
- enum { RR_Undef, RR_Same, RR_CFAoff, RR_Reg, RR_Arch, RR_Expr } tag;
+ enum { RR_Undef, RR_Same, RR_CFAoff, RR_Reg, RR_Arch, RR_Expr,
+ RR_CFAValoff, RR_ValExpr } tag;
/* Note, .coff and .reg are never both in use. Therefore could
merge them into one. */
@@ -1412,9 +1418,11 @@ static void ppRegRule ( RegRule* reg )
case RR_Undef: VG_(printf)("u "); break;
case RR_Same: VG_(printf)("s "); break;
case RR_CFAoff: VG_(printf)("c%d ", reg->coff); break;
+ case RR_CFAValoff: VG_(printf)("v%d ", reg->coff); break;
case RR_Reg: VG_(printf)("r%d ", reg->reg); break;
case RR_Arch: VG_(printf)("a "); break;
case RR_Expr: VG_(printf)("e "); break;
+ case RR_ValExpr: VG_(printf)("ve "); break;
default: VG_(core_panic)("ppRegRule");
}
}
@@ -1557,6 +1565,7 @@ static Bool summarise_context( /*OUT*/Cf
case RR_Undef: _how = CFIR_UNKNOWN; _off = 0; break; \
case RR_Same: _how = CFIR_SAME; _off = 0; break; \
case RR_CFAoff: _how = CFIR_MEMCFAREL; _off = _ctxreg.coff; break; \
+ case RR_CFAValoff: _how = CFIR_CFAREL; _off = _ctxreg.coff; break; \
default: { why = 2; goto failed; } /* otherwise give up */ \
}
@@ -1883,6 +1892,17 @@ static Int run_CF_instruction ( /*MOD*/U
ctx->cfa_offset = off;
break;
+ case DW_CFA_def_cfa_sf:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ off = read_leb128( &instr[i], &nleb, 1 );
+ i += nleb;
+ if (reg < 0 || reg >= N_CFI_REGS)
+ return 0; /* fail */
+ ctx->cfa_reg = reg;
+ ctx->cfa_offset = off;
+ break;
+
case DW_CFA_register:
reg = read_leb128( &instr[i], &nleb, 0);
i += nleb;
@@ -1896,6 +1916,17 @@ static Int run_CF_instruction ( /*MOD*/U
ctx->reg[reg].reg = reg2;
break;
+ case DW_CFA_offset_extended:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ off = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ if (reg < 0 || reg >= N_CFI_REGS)
+ return 0; /* fail */
+ ctx->reg[reg].tag = RR_CFAoff;
+ ctx->reg[reg].coff = off * ctx->data_a_f;
+ break;
+
case DW_CFA_offset_extended_sf:
reg = read_leb128( &instr[i], &nleb, 0 );
i += nleb;
@@ -1907,6 +1938,49 @@ static Int run_CF_instruction ( /*MOD*/U
ctx->reg[reg].coff = off * ctx->data_a_f;
break;
+ case DW_CFA_GNU_negative_offset_extended:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ off = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ if (reg < 0 || reg >= N_CFI_REGS)
+ return 0; /* fail */
+ ctx->reg[reg].tag = RR_CFAoff;
+ ctx->reg[reg].coff = -off * ctx->data_a_f;
+ break;
+
+ case DW_CFA_restore_extended:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ if (reg < 0 || reg >= N_CFI_REGS)
+ return 0; /* fail */
+ if (restore_ctx == NULL)
+ return 0; /* fail */
+ ctx->reg[reg] = restore_ctx->reg[reg];
+ break;
+
+ case DW_CFA_val_offset:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ off = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ if (reg < 0 || reg >= N_CFI_REGS)
+ return 0; /* fail */
+ ctx->reg[reg].tag = RR_CFAValoff;
+ ctx->reg[reg].coff = off * ctx->data_a_f;
+ break;
+
+ case DW_CFA_val_offset_sf:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ off = read_leb128( &instr[i], &nleb, 1 );
+ i += nleb;
+ if (reg < 0 || reg >= N_CFI_REGS)
+ return 0; /* fail */
+ ctx->reg[reg].tag = RR_CFAValoff;
+ ctx->reg[reg].coff = off * ctx->data_a_f;
+ break;
+
case DW_CFA_def_cfa_register:
reg = read_leb128( &instr[i], &nleb, 0);
i += nleb;
@@ -1950,6 +2024,22 @@ static Int run_CF_instruction ( /*MOD*/U
ctx->reg[reg].tag = RR_Expr;
break;
+ case DW_CFA_val_expression:
+ /* Too difficult to really handle; just skip over it and say
+ that we don't know what do to with the register. */
+ if (VG_(clo_trace_cfi))
+ VG_(printf)("DWARF2 CFI reader: "
+ "ignoring DW_CFA_val_expression\n");
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ len = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ i += len;
+ if (reg < 0 || reg >= N_CFI_REGS)
+ return 0; /* fail */
+ ctx->reg[reg].tag = RR_ValExpr;
+ break;
+
case DW_CFA_def_cfa_expression:
if (VG_(clo_trace_cfi))
VG_(printf)("DWARF2 CFI reader: "
@@ -2006,7 +2096,7 @@ static Int show_CF_instruction ( UChar*
}
if (hi2 == DW_CFA_restore) {
- VG_(printf)("DW_CFA_restore(%d)\n", (Int)lo6);
+ VG_(printf)("DW_CFA_restore(r%d)\n", (Int)lo6);
return i;
}
@@ -2046,6 +2136,14 @@ static Int show_CF_instruction ( UChar*
VG_(printf)("DW_CFA_def_cfa(r%d, off %d)\n", reg, off);
break;
+ case DW_CFA_def_cfa_sf:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ off = read_leb128( &instr[i], &nleb, 1 );
+ i += nleb;
+ VG_(printf)("DW_CFA_def_cfa_sf(r%d, off %d)\n", reg, off);
+ break;
+
case DW_CFA_register:
reg = read_leb128( &instr[i], &nleb, 0);
i += nleb;
@@ -2066,6 +2164,38 @@ static Int show_CF_instruction ( UChar*
VG_(printf)("DW_CFA_def_cfa_offset(%d)\n", off);
break;
+ case DW_CFA_def_cfa_offset_sf:
+ off = read_leb128( &instr[i], &nleb, 1);
+ i += nleb;
+ VG_(printf)("DW_CFA_def_cfa_offset_sf(%d)\n", off);
+ break;
+
+ case DW_CFA_restore_extended:
+ reg = read_leb128( &instr[i], &nleb, 0);
+ i += nleb;
+ VG_(printf)("DW_CFA_restore_extended(r%d)\n", reg);
+ break;
+
+ case DW_CFA_undefined:
+ reg = read_leb128( &instr[i], &nleb, 0);
+ i += nleb;
+ VG_(printf)("DW_CFA_undefined(r%d)\n", reg);
+ break;
+
+ case DW_CFA_same_value:
+ reg = read_leb128( &instr[i], &nleb, 0);
+ i += nleb;
+ VG_(printf)("DW_CFA_same_value(r%d)\n", reg);
+ break;
+
+ case DW_CFA_remember_state:
+ VG_(printf)("DW_CFA_remember_state\n");
+ break;
+
+ case DW_CFA_restore_state:
+ VG_(printf)("DW_CFA_restore_state\n");
+ break;
+
case DW_CFA_GNU_args_size:
off = read_leb128( &instr[i], &nleb, 0 );
i += nleb;
@@ -2088,6 +2218,55 @@ static Int show_CF_instruction ( UChar*
VG_(printf)("DW_CFA_expression(r%d, length %d)\n", reg, len);
break;
+ case DW_CFA_val_expression:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ len = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ i += len;
+ VG_(printf)("DW_CFA_val_expression(r%d, length %d)\n", reg, len);
+ break;
+
+ case DW_CFA_offset_extended:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ off = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ VG_(printf)("DW_CFA_offset_extended(r%d, off %d x data_af)\n", reg, off);
+ break;
+
+ case DW_CFA_offset_extended_sf:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ off = read_leb128( &instr[i], &nleb, 1 );
+ i += nleb;
+ VG_(printf)("DW_CFA_offset_extended_sf(r%d, off %d x data_af)\n", reg, off);
+ break;
+
+ case DW_CFA_GNU_negative_offset_extended:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ off = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ VG_(printf)("DW_CFA_GNU_negative_offset_extended(r%d, off %d x data_af)\n", reg, -off);
+ break;
+
+ case DW_CFA_val_offset:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ off = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ VG_(printf)("DW_CFA_val_offset(r%d, off %d x data_af)\n", reg, off);
+ break;
+
+ case DW_CFA_val_offset_sf:
+ reg = read_leb128( &instr[i], &nleb, 0 );
+ i += nleb;
+ off = read_leb128( &instr[i], &nleb, 1 );
+ i += nleb;
+ VG_(printf)("DW_CFA_val_offset_sf(r%d, off %d x data_af)\n", reg, off);
+ break;
+
case DW_CFA_GNU_window_save:
VG_(printf)("DW_CFA_GNU_window_save\n");
break;
@@ -2378,6 +2557,9 @@ void ML_(read_callframe_info_dwarf2)
data++;
cie_augmentation++;
break;
+ case 'S':
+ cie_augmentation++;
+ break;
default:
if (the_CIEs[this_CIE].instrs == NULL) {
how = "unhandled cie.augmentation";
valgrind-3.1.1-glibc24.patch:
glibc-2.4.supp | 9 +++++++++
1 files changed, 9 insertions(+)
--- NEW FILE valgrind-3.1.1-glibc24.patch ---
--- valgrind-3.1.1/glibc-2.4.supp.jj 2006-03-15 12:52:00.000000000 -0500
+++ valgrind-3.1.1/glibc-2.4.supp 2006-04-03 12:51:31.000000000 -0400
@@ -61,6 +61,15 @@
obj:/lib*/libc-2.3.90.so
}
+{
+ Fedora-Core-5-hack3a
+ Memcheck:Cond
+ obj:/lib*/ld-2.4*so
+ obj:/lib*/ld-2.4*so
+ obj:/lib*/ld-2.4*so
+ obj:/lib*/libc-2.4*so
+}
+
##----------------------------------------------------------------------##
{
glibc-2.3.x-on-SUSE-10.1-(PPC)-1
valgrind-3.1.1-valgrind_h.patch:
valgrind.h | 16 ++++++++--------
1 files changed, 8 insertions(+), 8 deletions(-)
--- NEW FILE valgrind-3.1.1-valgrind_h.patch ---
--- valgrind-3.1.1/include/valgrind.h.jj 2005-03-11 01:28:13.000000000 -0500
+++ valgrind-3.1.1/include/valgrind.h 2005-03-29 16:42:31.000000000 -0500
@@ -215,10 +215,11 @@ typedef
#else /* NVALGRIND */
-int VALGRIND_PRINTF(const char *format, ...)
- __attribute__((format(__printf__, 1, 2)));
-__attribute__((weak))
-int
+/* Modern GCC will optimize the static routine out if unused,
+ and unused attribute will shut down warnings about it. */
+static int VALGRIND_PRINTF(const char *format, ...)
+ __attribute__((format(__printf__, 1, 2), __unused__));
+static int
VALGRIND_PRINTF(const char *format, ...)
{
unsigned long _qzz_res;
@@ -230,10 +231,9 @@ VALGRIND_PRINTF(const char *format, ...)
return (int)_qzz_res;
}
-int VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
- __attribute__((format(__printf__, 1, 2)));
-__attribute__((weak))
-int
+static int VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
+ __attribute__((format(__printf__, 1, 2), __unused__));
+static int
VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
{
unsigned long _qzz_res;
Index: .cvsignore
===================================================================
RCS file: /cvs/dist/rpms/valgrind/devel/.cvsignore,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -r1.8 -r1.9
--- .cvsignore 10 Jan 2006 10:36:37 -0000 1.8
+++ .cvsignore 3 Apr 2006 16:55:06 -0000 1.9
@@ -1 +1 @@
-valgrind-3.1.0.tar.bz2
+valgrind-3.1.1.tar.bz2
Index: sources
===================================================================
RCS file: /cvs/dist/rpms/valgrind/devel/sources,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -r1.8 -r1.9
--- sources 10 Jan 2006 10:36:37 -0000 1.8
+++ sources 3 Apr 2006 16:55:06 -0000 1.9
@@ -1 +1 @@
-d92156e9172dc6097e56c69ea9c88013 valgrind-3.1.0.tar.bz2
+3bbfafedb59c19bf75977381ce2eb6d7 valgrind-3.1.1.tar.bz2
Index: valgrind.spec
===================================================================
RCS file: /cvs/dist/rpms/valgrind/devel/valgrind.spec,v
retrieving revision 1.28
retrieving revision 1.29
diff -u -r1.28 -r1.29
--- valgrind.spec 13 Mar 2006 09:22:55 -0000 1.28
+++ valgrind.spec 3 Apr 2006 16:55:06 -0000 1.29
@@ -1,14 +1,13 @@
Summary: Tool for finding memory management bugs in programs
Name: valgrind
-Version: 3.1.0
-Release: 2
+Version: 3.1.1
+Release: 1
Epoch: 1
Source0: http://www.valgrind.org/downloads/valgrind-%{version}.tar.bz2
-Patch1: valgrind-3.1.0-valgrind_h.patch
-Patch2: valgrind-3.1.0-amd64-highbase.patch
-Patch3: valgrind-3.1.0-amd64-speedup.patch
-Patch4: valgrind-3.1.0-cfa-val-expr.patch
-Patch5: valgrind-3.1.0-glibc24.patch
+Patch1: valgrind-3.1.1-valgrind_h.patch
+Patch2: valgrind-3.1.1-amd64-speedup.patch
+Patch3: valgrind-3.1.1-cfa-val-expr.patch
+Patch4: valgrind-3.1.1-glibc24.patch
License: GPL
URL: http://www.valgrind.org/
Group: Development/Debuggers
@@ -32,12 +31,9 @@
%prep
%setup -q
%patch1 -p1
-%ifarch x86_64
-#%patch2 -p1
-%endif
+%patch2 -p1
%patch3 -p1
%patch4 -p1
-%patch5 -p1
%build
%ifarch x86_64
@@ -115,6 +111,10 @@
%{_mandir}/man1/valgrind*
%changelog
+* Mon Apr 3 2006 Jakub Jelinek <jakub at redhat.com> 3.1.1-1
+- upgrade to 3.1.1
+ - many bugfixes
+
* Mon Mar 13 2006 Jakub Jelinek <jakub at redhat.com> 3.1.0-2
- add support for DW_CFA_val_offset{,_sf}, DW_CFA_def_cfa_sf
and skip over DW_CFA_val_expression quietly
--- valgrind-3.1.0-amd64-highbase.patch DELETED ---
--- valgrind-3.1.0-amd64-speedup.patch DELETED ---
--- valgrind-3.1.0-cfa-val-expr.patch DELETED ---
--- valgrind-3.1.0-glibc24.patch DELETED ---
--- valgrind-3.1.0-valgrind_h.patch DELETED ---
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