rpms/oprofile/devel oprofile-power6.patch, NONE, 1.1 oprofile.spec, 1.43, 1.44
fedora-cvs-commits at redhat.com
fedora-cvs-commits at redhat.com
Mon Jul 10 14:39:22 UTC 2006
Author: wcohen
Update of /cvs/dist/rpms/oprofile/devel
In directory cvs.devel.redhat.com:/tmp/cvs-serv8894
Modified Files:
oprofile.spec
Added Files:
oprofile-power6.patch
Log Message:
- Add power6 support. (#196505)
oprofile-power6.patch:
events/Makefile.am | 1
events/ppc64/power6/event_mappings | 949 ++++++++++++++++++++++++++++++++++++
events/ppc64/power6/events | 960 +++++++++++++++++++++++++++++++++++++
events/ppc64/power6/unit_masks | 4
libop/op_cpu_type.c | 1
libop/op_cpu_type.h | 1
libop/op_events.c | 2
utils/opcontrol | 2
utils/ophelp.c | 1
9 files changed, 1920 insertions(+), 1 deletion(-)
--- NEW FILE oprofile-power6.patch ---
diff -paurN oprof-cvs-05.05.2006/events/Makefile.am oprof-cvs-power6-ver-2/events/Makefile.am
--- oprof-cvs-05.05.2006/events/Makefile.am 2006-02-22 08:36:36.000000000 -0600
+++ oprof-cvs-power6-ver-2/events/Makefile.am 2006-06-22 10:12:09.000000000 -0500
@@ -17,6 +17,7 @@ event_files = \
ppc64/power4/events ppc64/power4/event_mappings ppc64/power4/unit_masks \
ppc64/power5/events ppc64/power5/event_mappings ppc64/power5/unit_masks \
ppc64/power5+/events ppc64/power5+/event_mappings ppc64/power5+/unit_masks \
+ ppc64/power6/events ppc64/power6/event_mappings ppc64/power6/unit_masks \
ppc64/970/events ppc64/970/event_mappings ppc64/970/unit_masks \
rtc/events rtc/unit_masks \
x86-64/hammer/events x86-64/hammer/unit_masks \
diff -paurN oprof-cvs-05.05.2006/events/ppc64/power6/event_mappings oprof-cvs-power6-ver-2/events/ppc64/power6/event_mappings
--- oprof-cvs-05.05.2006/events/ppc64/power6/event_mappings 1969-12-31 18:00:00.000000000 -0600
+++ oprof-cvs-power6-ver-2/events/ppc64/power6/event_mappings 2006-06-22 11:52:25.000000000 -0500
@@ -0,0 +1,949 @@
+#Mapping of event groups to MMCR values
+
+#Group Default
+event:0X001 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+
+#Group 0 with random sampling
+event:0X002 mmcr0:0X00000000 mmcr1:0X000000001E1E021A mmcra:0X00000001
+
+#Group 1 pm_utilization, CPI and utilization data
+event:0X0010 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+event:0X0011 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+event:0X0012 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+event:0X0013 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+
+#Group 2 pm_dcache, D cache
+event:0X0020 mmcr0:0X00000000 mmcr1:0X000000000C0E0C06 mmcra:0X00000000
+event:0X0021 mmcr0:0X00000000 mmcr1:0X000000000C0E0C06 mmcra:0X00000000
+event:0X0022 mmcr0:0X00000000 mmcr1:0X000000000C0E0C06 mmcra:0X00000000
+event:0X0023 mmcr0:0X00000000 mmcr1:0X000000000C0E0C06 mmcra:0X00000000
+
+#Group 3 pm_branch, Branch operations
+event:0X0030 mmcr0:0X00000000 mmcr1:0X04000000A2A8808A mmcra:0X00000000
+event:0X0031 mmcr0:0X00000000 mmcr1:0X04000000A2A8808A mmcra:0X00000000
+event:0X0032 mmcr0:0X00000000 mmcr1:0X04000000A2A8808A mmcra:0X00000000
+event:0X0033 mmcr0:0X00000000 mmcr1:0X04000000A2A8808A mmcra:0X00000000
+
+#Group 4 pm_branch2, Branch operations
+event:0X0040 mmcr0:0X00000000 mmcr1:0X04000000A4A68E8C mmcra:0X00000000
+event:0X0041 mmcr0:0X00000000 mmcr1:0X04000000A4A68E8C mmcra:0X00000000
+event:0X0042 mmcr0:0X00000000 mmcr1:0X04000000A4A68E8C mmcra:0X00000000
+event:0X0043 mmcr0:0X00000000 mmcr1:0X04000000A4A68E8C mmcra:0X00000000
+
+#Group 5 pm_branch3, Branch operations
+event:0X0050 mmcr0:0X00000000 mmcr1:0X04000000A0A28486 mmcra:0X00000000
+event:0X0051 mmcr0:0X00000000 mmcr1:0X04000000A0A28486 mmcra:0X00000000
+event:0X0052 mmcr0:0X00000000 mmcr1:0X04000000A0A28486 mmcra:0X00000000
+event:0X0053 mmcr0:0X00000000 mmcr1:0X04000000A0A28486 mmcra:0X00000000
+
+#Group 6 pm_branch4, Branch operations
+event:0X0060 mmcr0:0X00000000 mmcr1:0X04000000A8AA8C8E mmcra:0X00000000
+event:0X0061 mmcr0:0X00000000 mmcr1:0X04000000A8AA8C8E mmcra:0X00000000
+event:0X0062 mmcr0:0X00000000 mmcr1:0X04000000A8AA8C8E mmcra:0X00000000
+event:0X0063 mmcr0:0X00000000 mmcr1:0X04000000A8AA8C8E mmcra:0X00000000
+
+#Group 7 pm_branch5, Branch operations
+event:0X0070 mmcr0:0X00000000 mmcr1:0X04040000A052C652 mmcra:0X00000000
+event:0X0071 mmcr0:0X00000000 mmcr1:0X04040000A052C652 mmcra:0X00000000
+event:0X0072 mmcr0:0X00000000 mmcr1:0X04040000A052C652 mmcra:0X00000000
+event:0X0073 mmcr0:0X00000000 mmcr1:0X04040000A052C652 mmcra:0X00000000
+
+#Group 8 pm_dsource, Data source
+event:0X0080 mmcr0:0X00000000 mmcr1:0X0000000058585656 mmcra:0X00000000
+event:0X0081 mmcr0:0X00000000 mmcr1:0X0000000058585656 mmcra:0X00000000
+event:0X0082 mmcr0:0X00000000 mmcr1:0X0000000058585656 mmcra:0X00000000
+event:0X0083 mmcr0:0X00000000 mmcr1:0X0000000058585656 mmcra:0X00000000
+
+#Group 9 pm_dsource2, Data sources
+event:0X0090 mmcr0:0X00000000 mmcr1:0X000000005A5A5856 mmcra:0X00000000
+event:0X0091 mmcr0:0X00000000 mmcr1:0X000000005A5A5856 mmcra:0X00000000
+event:0X0092 mmcr0:0X00000000 mmcr1:0X000000005A5A5856 mmcra:0X00000000
+event:0X0093 mmcr0:0X00000000 mmcr1:0X000000005A5A5856 mmcra:0X00000000
+
+#Group 10 pm_dsource3, Data sources
+event:0X00A0 mmcr0:0X00000000 mmcr1:0X000000005A5A5A5A mmcra:0X00000000
+event:0X00A1 mmcr0:0X00000000 mmcr1:0X000000005A5A5A5A mmcra:0X00000000
+event:0X00A2 mmcr0:0X00000000 mmcr1:0X000000005A5A5A5A mmcra:0X00000000
+event:0X00A3 mmcr0:0X00000000 mmcr1:0X000000005A5A5A5A mmcra:0X00000000
+
+#Group 11 pm_dsource4, Data sources
+event:0X00B0 mmcr0:0X00000000 mmcr1:0X000000005C5C5C5C mmcra:0X00000000
+event:0X00B1 mmcr0:0X00000000 mmcr1:0X000000005C5C5C5C mmcra:0X00000000
+event:0X00B2 mmcr0:0X00000000 mmcr1:0X000000005C5C5C5C mmcra:0X00000000
+event:0X00B3 mmcr0:0X00000000 mmcr1:0X000000005C5C5C5C mmcra:0X00000000
+
+#Group 12 pm_dsource4, Data sources
+event:0X00C0 mmcr0:0X00000000 mmcr1:0X000000005E5E5E5E mmcra:0X00000000
+event:0X00C1 mmcr0:0X00000000 mmcr1:0X000000005E5E5E5E mmcra:0X00000000
+event:0X00C2 mmcr0:0X00000000 mmcr1:0X000000005E5E5E5E mmcra:0X00000000
+event:0X00C3 mmcr0:0X00000000 mmcr1:0X000000005E5E5E5E mmcra:0X00000000
+
+#Group 13 pm_dlatencies, Data latencies
+event:0X00D0 mmcr0:0X00000000 mmcr1:0X000000000C281E24 mmcra:0X00000000
+event:0X00D1 mmcr0:0X00000000 mmcr1:0X000000000C281E24 mmcra:0X00000000
+event:0X00D2 mmcr0:0X00000000 mmcr1:0X000000000C281E24 mmcra:0X00000000
+event:0X00D3 mmcr0:0X00000000 mmcr1:0X000000000C281E24 mmcra:0X00000000
+
+#Group 14 pm_dlatencies2, Data latencies
+event:0X00E0 mmcr0:0X00000000 mmcr1:0X00000000022C1E2A mmcra:0X00000000
+event:0X00E1 mmcr0:0X00000000 mmcr1:0X00000000022C1E2A mmcra:0X00000000
+event:0X00E2 mmcr0:0X00000000 mmcr1:0X00000000022C1E2A mmcra:0X00000000
+event:0X00E3 mmcr0:0X00000000 mmcr1:0X00000000022C1E2A mmcra:0X00000000
+
+#Group 15 pm_dlatencies3, Data latencies
+event:0X00F0 mmcr0:0X00000000 mmcr1:0X00000000022E5E2C mmcra:0X00000000
+event:0X00F1 mmcr0:0X00000000 mmcr1:0X00000000022E5E2C mmcra:0X00000000
+event:0X00F2 mmcr0:0X00000000 mmcr1:0X00000000022E5E2C mmcra:0X00000000
+event:0X00F3 mmcr0:0X00000000 mmcr1:0X00000000022E5E2C mmcra:0X00000000
+
+#Group 16 pm_dlatencies4, Data latencies
+event:0X0100 mmcr0:0X00000000 mmcr1:0X000000005A2A5C26 mmcra:0X00000000
+event:0X0101 mmcr0:0X00000000 mmcr1:0X000000005A2A5C26 mmcra:0X00000000
+event:0X0102 mmcr0:0X00000000 mmcr1:0X000000005A2A5C26 mmcra:0X00000000
+event:0X0103 mmcr0:0X00000000 mmcr1:0X000000005A2A5C26 mmcra:0X00000000
+
+#Group 17 pm_dlatencies5, Data latencies
+event:0X0110 mmcr0:0X00000000 mmcr1:0X000000005C225828 mmcra:0X00000000
+event:0X0111 mmcr0:0X00000000 mmcr1:0X000000005C225828 mmcra:0X00000000
+event:0X0112 mmcr0:0X00000000 mmcr1:0X000000005C225828 mmcra:0X00000000
+event:0X0113 mmcr0:0X00000000 mmcr1:0X000000005C225828 mmcra:0X00000000
+
+#Group 18 pm_dlatencies6, Data latencies
+event:0X0120 mmcr0:0X00000000 mmcr1:0X000000005E245A2E mmcra:0X00000000
+event:0X0121 mmcr0:0X00000000 mmcr1:0X000000005E245A2E mmcra:0X00000000
+event:0X0122 mmcr0:0X00000000 mmcr1:0X000000005E245A2E mmcra:0X00000000
+event:0X0123 mmcr0:0X00000000 mmcr1:0X000000005E245A2E mmcra:0X00000000
+
+#Group 19 pm_dlatencies7, Data latencies
+event:0X0130 mmcr0:0X00000000 mmcr1:0X000000005820120E mmcra:0X00000000
+event:0X0131 mmcr0:0X00000000 mmcr1:0X000000005820120E mmcra:0X00000000
+event:0X0132 mmcr0:0X00000000 mmcr1:0X000000005820120E mmcra:0X00000000
+event:0X0133 mmcr0:0X00000000 mmcr1:0X000000005820120E mmcra:0X00000000
+
+#Group 20 pm_dlatencies8, Data latencies
+event:0X0140 mmcr0:0X00000000 mmcr1:0X0000000010581E20 mmcra:0X00000000
+event:0X0141 mmcr0:0X00000000 mmcr1:0X0000000010581E20 mmcra:0X00000000
+event:0X0142 mmcr0:0X00000000 mmcr1:0X0000000010581E20 mmcra:0X00000000
+event:0X0143 mmcr0:0X00000000 mmcr1:0X0000000010581E20 mmcra:0X00000000
+
+#Group 21 pm_dlatencies9, Data latencies
+event:0X0150 mmcr0:0X00000000 mmcr1:0X00000000122C125E mmcra:0X00000000
+event:0X0151 mmcr0:0X00000000 mmcr1:0X00000000122C125E mmcra:0X00000000
+event:0X0152 mmcr0:0X00000000 mmcr1:0X00000000122C125E mmcra:0X00000000
+event:0X0153 mmcr0:0X00000000 mmcr1:0X00000000122C125E mmcra:0X00000000
+
+#Group 22 pm_dlatencies10, Data latencies
+event:0X0160 mmcr0:0X00000000 mmcr1:0X000000005A261E26 mmcra:0X00000000
+event:0X0161 mmcr0:0X00000000 mmcr1:0X000000005A261E26 mmcra:0X00000000
+event:0X0162 mmcr0:0X00000000 mmcr1:0X000000005A261E26 mmcra:0X00000000
+event:0X0163 mmcr0:0X00000000 mmcr1:0X000000005A261E26 mmcra:0X00000000
+
+#Group 23 pm_isource, Instruction sources
+event:0X0170 mmcr0:0X00000000 mmcr1:0X0040000040404654 mmcra:0X00000000
+event:0X0171 mmcr0:0X00000000 mmcr1:0X0040000040404654 mmcra:0X00000000
+event:0X0172 mmcr0:0X00000000 mmcr1:0X0040000040404654 mmcra:0X00000000
+event:0X0173 mmcr0:0X00000000 mmcr1:0X0040000040404654 mmcra:0X00000000
+
+#Group 24 pm_isource2, Instruction sources
+event:0X0180 mmcr0:0X00000000 mmcr1:0X0040000046464046 mmcra:0X00000000
+event:0X0181 mmcr0:0X00000000 mmcr1:0X0040000046464046 mmcra:0X00000000
+event:0X0182 mmcr0:0X00000000 mmcr1:0X0040000046464046 mmcra:0X00000000
+event:0X0183 mmcr0:0X00000000 mmcr1:0X0040000046464046 mmcra:0X00000000
+
+#Group 25 pm_isource3, Instruction sources
+event:0X0190 mmcr0:0X00000000 mmcr1:0X0040000044444444 mmcra:0X00000000
+event:0X0191 mmcr0:0X00000000 mmcr1:0X0040000044444444 mmcra:0X00000000
+event:0X0192 mmcr0:0X00000000 mmcr1:0X0040000044444444 mmcra:0X00000000
+event:0X0193 mmcr0:0X00000000 mmcr1:0X0040000044444444 mmcra:0X00000000
+
+#Group 26 pm_isource4, Instruction sources
+event:0X01A0 mmcr0:0X00000000 mmcr1:0X0040000042424242 mmcra:0X00000000
+event:0X01A1 mmcr0:0X00000000 mmcr1:0X0040000042424242 mmcra:0X00000000
+event:0X01A2 mmcr0:0X00000000 mmcr1:0X0040000042424242 mmcra:0X00000000
+event:0X01A3 mmcr0:0X00000000 mmcr1:0X0040000042424242 mmcra:0X00000000
+
+#Group 27 pm_isource5, Instruction sources
+event:0X01B0 mmcr0:0X00000000 mmcr1:0X0040000040405454 mmcra:0X00000000
+event:0X01B1 mmcr0:0X00000000 mmcr1:0X0040000040405454 mmcra:0X00000000
+event:0X01B2 mmcr0:0X00000000 mmcr1:0X0040000040405454 mmcra:0X00000000
+event:0X01B3 mmcr0:0X00000000 mmcr1:0X0040000040405454 mmcra:0X00000000
+
+#Group 28 pm_pteg, PTEG sources
+event:0X01C0 mmcr0:0X00000000 mmcr1:0X0001000048484E4E mmcra:0X00000000
+event:0X01C1 mmcr0:0X00000000 mmcr1:0X0001000048484E4E mmcra:0X00000000
+event:0X01C2 mmcr0:0X00000000 mmcr1:0X0001000048484E4E mmcra:0X00000000
+event:0X01C3 mmcr0:0X00000000 mmcr1:0X0001000048484E4E mmcra:0X00000000
+
+#Group 29 pm_pteg2, PTEG sources
+event:0X01D0 mmcr0:0X00000000 mmcr1:0X000100002848484C mmcra:0X00000000
+event:0X01D1 mmcr0:0X00000000 mmcr1:0X000100002848484C mmcra:0X00000000
+event:0X01D2 mmcr0:0X00000000 mmcr1:0X000100002848484C mmcra:0X00000000
+event:0X01D3 mmcr0:0X00000000 mmcr1:0X000100002848484C mmcra:0X00000000
+
+#Group 30 pm_pteg3, PTEG sources
+event:0X01E0 mmcr0:0X00000000 mmcr1:0X000100004E4E284A mmcra:0X00000000
[...1601 lines suppressed...]
+event:0X0882 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP136 : (Group 136 pm_mrk_dsource5) Instructions completed
+event:0X0883 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_GRP136 : (Group 136 pm_mrk_dsource5) Marked data loaded from local memory
+
+#Group 137 pm_mrk_dsource6, Marked data sources
+event:0X0890 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_MOD_GRP137 : (Group 137 pm_mrk_dsource6) Marked data loaded from remote L2 or L3 modified
+event:0X0891 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_SHR_GRP137 : (Group 137 pm_mrk_dsource6) Marked data loaded from remote L2 or L3 shared
+event:0X0892 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_GRP137 : (Group 137 pm_mrk_dsource6) Marked data loaded from remote memory
+event:0X0893 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP137 : (Group 137 pm_mrk_dsource6) Instructions completed
+
+#Group 138 pm_mrk_rejects, Marked rejects
+event:0X08A0 counters:0 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_ULD_GRP138 : (Group 138 pm_mrk_rejects) Marked unaligned load reject
+event:0X08A1 counters:1 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_UST_GRP138 : (Group 138 pm_mrk_rejects) Marked unaligned store reject
+event:0X08A2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP138 : (Group 138 pm_mrk_rejects) Instructions completed
+event:0X08A3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_LHS_GRP138 : (Group 138 pm_mrk_rejects) Marked load hit store reject
+
+#Group 139 pm_mrk_rejects2, Marked rejects LSU0
+event:0X08B0 counters:0 um:zero minimum:1000 name:PM_MRK_LSU0_REJECT_LHS_GRP139 : (Group 139 pm_mrk_rejects2) LSU0 marked load hit store reject
+event:0X08B1 counters:1 um:zero minimum:1000 name:PM_MRK_LSU0_REJECT_ULD_GRP139 : (Group 139 pm_mrk_rejects2) LSU0 marked unaligned load reject
+event:0X08B2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_REJECT_UST_GRP139 : (Group 139 pm_mrk_rejects2) LSU0 marked unaligned store reject
+event:0X08B3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP139 : (Group 139 pm_mrk_rejects2) Instructions completed
+
+#Group 140 pm_mrk_rejects3, Marked rejects LSU1
+event:0X08C0 counters:0 um:zero minimum:1000 name:PM_MRK_LSU1_REJECT_LHS_GRP140 : (Group 140 pm_mrk_rejects3) LSU1 marked load hit store reject
+event:0X08C1 counters:1 um:zero minimum:1000 name:PM_MRK_LSU1_REJECT_ULD_GRP140 : (Group 140 pm_mrk_rejects3) LSU1 marked unaligned load reject
+event:0X08C2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU1_REJECT_UST_GRP140 : (Group 140 pm_mrk_rejects3) LSU1 marked unaligned store reject
+event:0X08C3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP140 : (Group 140 pm_mrk_rejects3) Instructions completed
+
+#Group 141 pm_mrk_inst, Marked instruction events
+event:0X08D0 counters:0 um:zero minimum:1000 name:PM_MRK_INST_ISSUED_GRP141 : (Group 141 pm_mrk_inst) Marked instruction issued
+event:0X08D1 counters:1 um:zero minimum:1000 name:PM_MRK_INST_DISP_GRP141 : (Group 141 pm_mrk_inst) Marked instruction dispatched
+event:0X08D2 counters:2 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP141 : (Group 141 pm_mrk_inst) Marked instruction finished
+event:0X08D3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP141 : (Group 141 pm_mrk_inst) Instructions completed
+
+#Group 142 pm_mrk_fpu_fin, Marked Floating Point instructions finished
+event:0X08E0 counters:0 um:zero minimum:1000 name:PM_MRK_FPU0_FIN_GRP142 : (Group 142 pm_mrk_fpu_fin) Marked instruction FPU0 processing finished
+event:0X08E1 counters:1 um:zero minimum:1000 name:PM_MRK_FPU1_FIN_GRP142 : (Group 142 pm_mrk_fpu_fin) Marked instruction FPU1 processing finished
+event:0X08E2 counters:2 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP142 : (Group 142 pm_mrk_fpu_fin) Marked instruction FPU processing finished
+event:0X08E3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP142 : (Group 142 pm_mrk_fpu_fin) Instructions completed
+
+#Group 143 pm_mrk_misc, Marked misc events
+event:0X08F0 counters:0 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_ULD_GRP143 : (Group 143 pm_mrk_misc) Marked unaligned load reject
+event:0X08F1 counters:1 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP143 : (Group 143 pm_mrk_misc) Marked instruction FXU processing finished
+event:0X08F2 counters:2 um:zero minimum:1000 name:PM_MRK_DFU_FIN_GRP143 : (Group 143 pm_mrk_misc) DFU marked instruction finish
+event:0X08F3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP143 : (Group 143 pm_mrk_misc) Instructions completed
+
+#Group 144 pm_mrk_misc2, Marked misc events
+event:0X0900 counters:0 um:zero minimum:1000 name:PM_MRK_STCX_FAIL_GRP144 : (Group 144 pm_mrk_misc2) Marked STCX failed
+event:0X0901 counters:1 um:zero minimum:1000 name:PM_MRK_IFU_FIN_GRP144 : (Group 144 pm_mrk_misc2) Marked instruction IFU processing finished
+event:0X0902 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP144 : (Group 144 pm_mrk_misc2) Instructions completed
+event:0X0903 counters:3 um:zero minimum:1000 name:PM_MRK_INST_TIMEO_GRP144 : (Group 144 pm_mrk_misc2) Marked Instruction finish timeout
+
+#Group 145 pm_mrk_misc3, Marked misc events
+event:0X0910 counters:0 um:zero minimum:1000 name:PM_MRK_VMX_ST_ISSUED_GRP145 : (Group 145 pm_mrk_misc3) Marked VMX store issued
+event:0X0911 counters:1 um:zero minimum:1000 name:PM_MRK_LSU0_REJECT_L2MISS_GRP145 : (Group 145 pm_mrk_misc3) LSU0 marked L2 miss reject
+event:0X0912 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP145 : (Group 145 pm_mrk_misc3) Instructions completed
+event:0X0913 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_DERAT_MISS_GRP145 : (Group 145 pm_mrk_misc3) Marked DERAT miss
+
+#Group 146 pm_mrk_misc4, Marked misc events
+event:0X0920 counters:0 um:zero minimum:10000 name:PM_CYC_GRP146 : (Group 146 pm_mrk_misc4) Processor cycles
+event:0X0921 counters:1 um:zero minimum:10000 name:PM_CYC_GRP146 : (Group 146 pm_mrk_misc4) Processor cycles
+event:0X0922 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP146 : (Group 146 pm_mrk_misc4) Instructions completed
+event:0X0923 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP146 : (Group 146 pm_mrk_misc4) Marked instruction LSU processing finished
+
+#Group 147 pm_mrk_st, Marked stores events
+event:0X0930 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP147 : (Group 147 pm_mrk_st) Marked store instruction completed
+event:0X0931 counters:1 um:zero minimum:1000 name:PM_MRK_ST_GPS_GRP147 : (Group 147 pm_mrk_st) Marked store sent to GPS
+event:0X0932 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP147 : (Group 147 pm_mrk_st) Marked store completed with intervention
+event:0X0933 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP147 : (Group 147 pm_mrk_st) Instructions completed
+
+#Group 148 pm_mrk_pteg, Marked PTEG
+event:0X0940 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L2_GRP148 : (Group 148 pm_mrk_pteg) Marked PTEG loaded from L2.5 modified
+event:0X0941 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DMEM_GRP148 : (Group 148 pm_mrk_pteg) Marked PTEG loaded from distant memory
+event:0X0942 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DL2L3_SHR_GRP148 : (Group 148 pm_mrk_pteg) Marked PTEG loaded from distant L2 or L3 shared
+event:0X0943 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP148 : (Group 148 pm_mrk_pteg) Instructions completed
+
+#Group 149 pm_mrk_pteg2, Marked PTEG
+event:0X0950 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP149 : (Group 149 pm_mrk_pteg2) Instructions completed
+event:0X0951 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L21_GRP149 : (Group 149 pm_mrk_pteg2) Marked PTEG loaded from private L2 other core
+event:0X0952 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L25_SHR_GRP149 : (Group 149 pm_mrk_pteg2) Marked PTEG loaded from L2.5 shared
+event:0X0953 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DL2L3_MOD_GRP149 : (Group 149 pm_mrk_pteg2) Marked PTEG loaded from distant L2 or L3 modified
+
+#Group 150 pm_mrk_pteg3, Marked PTEG
+event:0X0960 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L35_MOD_GRP150 : (Group 150 pm_mrk_pteg3) Marked PTEG loaded from L3.5 modified
+event:0X0961 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L35_SHR_GRP150 : (Group 150 pm_mrk_pteg3) Marked PTEG loaded from L3.5 shared
+event:0X0962 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP150 : (Group 150 pm_mrk_pteg3) Instructions completed
+event:0X0963 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L25_MOD_GRP150 : (Group 150 pm_mrk_pteg3) Marked PTEG loaded from L2.5 modified
+
+#Group 151 pm_mrk_pteg4, Marked PTEG
+event:0X0970 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_MEM_DP_GRP151 : (Group 151 pm_mrk_pteg4) Marked PTEG loaded from double pump memory
+event:0X0971 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP151 : (Group 151 pm_mrk_pteg4) Instructions completed
+event:0X0972 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L3_GRP151 : (Group 151 pm_mrk_pteg4) Marked PTEG loaded from L3
+event:0X0973 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L2MISS_GRP151 : (Group 151 pm_mrk_pteg4) Marked PTEG loaded from L2 miss
+
+#Group 152 pm_mrk_pteg5, Marked PTEG
+event:0X0980 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_RL2L3_MOD_GRP152 : (Group 152 pm_mrk_pteg5) Marked PTEG loaded from remote L2 or L3 modified
+event:0X0981 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP152 : (Group 152 pm_mrk_pteg5) Instructions completed
+event:0X0982 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L3MISS_GRP152 : (Group 152 pm_mrk_pteg5) Marked PTEG loaded from L3 miss
+event:0X0983 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_LMEM_GRP152 : (Group 152 pm_mrk_pteg5) Marked PTEG loaded from local memory
+
+#Group 153 pm_mrk_pteg6, Marked PTEG
+event:0X0990 counters:0 um:zero minimum:10000 name:PM_CYC_GRP153 : (Group 153 pm_mrk_pteg6) Processor cycles
+event:0X0991 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_RL2L3_SHR_GRP153 : (Group 153 pm_mrk_pteg6) Marked PTEG loaded from remote L2 or L3 shared
+event:0X0992 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_RMEM_GRP153 : (Group 153 pm_mrk_pteg6) Marked PTEG loaded from remote memory
+event:0X0993 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP153 : (Group 153 pm_mrk_pteg6) Instructions completed
+
+#Group 154 pm_mrk_vmx, Marked VMX
+event:0X09A0 counters:0 um:zero minimum:1000 name:PM_MRK_VMX_COMPLEX_ISSUED_GRP154 : (Group 154 pm_mrk_vmx) Marked VMX instruction issued to complex
+event:0X09A1 counters:1 um:zero minimum:1000 name:PM_MRK_VMX_FLOAT_ISSUED_GRP154 : (Group 154 pm_mrk_vmx) Marked VMX instruction issued to float
+event:0X09A2 counters:2 um:zero minimum:1000 name:PM_MRK_VMX_PERMUTE_ISSUED_GRP154 : (Group 154 pm_mrk_vmx) Marked VMX instruction issued to permute
+event:0X09A3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP154 : (Group 154 pm_mrk_vmx) Instructions completed
+
+#Group 155 pm_mrk_vmx2, Marked VMX
+event:0X09B0 counters:0 um:zero minimum:1000 name:PM_MRK_VMX0_LD_WRBACK_GRP155 : (Group 155 pm_mrk_vmx2) Marked VMX0 load writeback valid
+event:0X09B1 counters:1 um:zero minimum:1000 name:PM_MRK_VMX1_LD_WRBACK_GRP155 : (Group 155 pm_mrk_vmx2) Marked VMX1 load writeback valid
+event:0X09B2 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_REF_GRP155 : (Group 155 pm_mrk_vmx2) Marked Data TLB reference
+event:0X09B3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP155 : (Group 155 pm_mrk_vmx2) Instructions completed
+
+#Group 156 pm_mrk_vmx3, Marked VMX
+event:0X09C0 counters:0 um:zero minimum:1000 name:PM_MRK_VMX_SIMPLE_ISSUED_GRP156 : (Group 156 pm_mrk_vmx3) Marked VMX instruction issued to simple
+event:0X09C1 counters:1 um:zero minimum:1000 name:PM_VMX_SIMPLE_ISSUED_GRP156 : (Group 156 pm_mrk_vmx3) VMX instruction issued to simple
+event:0X09C2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP156 : (Group 156 pm_mrk_vmx3) Processor cycles
+event:0X09C3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP156 : (Group 156 pm_mrk_vmx3) Instructions completed
+
+#Group 157 pm_mrk_fp , Marked FP events
+event:0X09D0 counters:0 um:zero minimum:1000 name:PM_MRK_FPU0_FIN_GRP157 : (Group 157 pm_mrk_fp ) Marked instruction FPU0 processing finished
+event:0X09D1 counters:1 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP157 : (Group 157 pm_mrk_fp ) Marked instruction FPU processing finished
+event:0X09D2 counters:2 um:zero minimum:1000 name:PM_MRK_FPU1_FIN_GRP157 : (Group 157 pm_mrk_fp ) Marked instruction FPU1 processing finished
+event:0X09D3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP157 : (Group 157 pm_mrk_fp ) Instructions completed
diff -paurN oprof-cvs-05.05.2006/events/ppc64/power6/unit_masks oprof-cvs-power6-ver-2/events/ppc64/power6/unit_masks
--- oprof-cvs-05.05.2006/events/ppc64/power6/unit_masks 1969-12-31 18:00:00.000000000 -0600
+++ oprof-cvs-power6-ver-2/events/ppc64/power6/unit_masks 2006-06-22 10:12:09.000000000 -0500
@@ -0,0 +1,4 @@
+# ppc64 POWER6 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff -paurN oprof-cvs-05.05.2006/libop/op_cpu_type.c oprof-cvs-power6-ver-2/libop/op_cpu_type.c
--- oprof-cvs-05.05.2006/libop/op_cpu_type.c 2006-02-22 08:36:40.000000000 -0600
+++ oprof-cvs-power6-ver-2/libop/op_cpu_type.c 2006-06-22 10:12:09.000000000 -0500
@@ -46,6 +46,7 @@ static struct cpu_descr const cpu_descrs
{ "ppc64 POWER4", "ppc64/power4", CPU_PPC64_POWER4, 8 },
{ "ppc64 POWER5", "ppc64/power5", CPU_PPC64_POWER5, 6 },
{ "ppc64 POWER5+", "ppc64/power5+", CPU_PPC64_POWER5p, 6 },
+ { "ppc64 POWER6", "ppc64/power6", CPU_PPC64_POWER6, 4 },
{ "ppc64 970", "ppc64/970", CPU_PPC64_970, 8 },
{ "MIPS 24K", "mips/24K", CPU_MIPS_24K, 2},
{ "MIPS R10000", "mips/r10000", CPU_MIPS_R10000, 2 },
diff -paurN oprof-cvs-05.05.2006/libop/op_cpu_type.h oprof-cvs-power6-ver-2/libop/op_cpu_type.h
--- oprof-cvs-05.05.2006/libop/op_cpu_type.h 2006-02-22 08:36:40.000000000 -0600
+++ oprof-cvs-power6-ver-2/libop/op_cpu_type.h 2006-06-22 10:12:09.000000000 -0500
@@ -42,6 +42,7 @@ typedef enum {
CPU_PPC64_POWER4, /**< ppc64 POWER4 family */
CPU_PPC64_POWER5, /**< ppc64 POWER5 family */
CPU_PPC64_POWER5p, /**< ppc64 Power5+ family */
+ CPU_PPC64_POWER6, /**< ppc64 POWER6 family */
CPU_PPC64_970, /**< ppc64 970 family */
CPU_MIPS_24K, /**< MIPS 24K */
CPU_MIPS_R10000, /**< MIPS R10000 */
diff -paurN oprof-cvs-05.05.2006/libop/op_events.c oprof-cvs-power6-ver-2/libop/op_events.c
--- oprof-cvs-05.05.2006/libop/op_events.c 2006-02-22 08:36:40.000000000 -0600
+++ oprof-cvs-power6-ver-2/libop/op_events.c 2006-06-22 10:12:09.000000000 -0500
@@ -643,6 +643,7 @@ char const * find_mapping_for_event(u32
case CPU_PPC64_970:
case CPU_PPC64_POWER4:
case CPU_PPC64_POWER5:
+ case CPU_PPC64_POWER6:
case CPU_PPC64_POWER5p:
if (!fp) {
fprintf(stderr, "oprofile: could not open event mapping file %s\n", filename);
@@ -783,6 +784,7 @@ void op_default_event(op_cpu cpu_type, s
case CPU_PPC64_970:
case CPU_PPC64_POWER4:
case CPU_PPC64_POWER5:
+ case CPU_PPC64_POWER6:
case CPU_PPC64_POWER5p:
descr->name = "CYCLES";
break;
diff -paurN oprof-cvs-05.05.2006/utils/opcontrol oprof-cvs-power6-ver-2/utils/opcontrol
--- oprof-cvs-05.05.2006/utils/opcontrol 2006-03-29 15:54:07.000000000 -0600
+++ oprof-cvs-power6-ver-2/utils/opcontrol 2006-06-22 10:12:09.000000000 -0500
@@ -1007,7 +1007,7 @@ set_ctr_param()
check_event_mapping_data()
{
- if [ "$CPUTYPE" = "ppc64/power4" -o "$CPUTYPE" = "ppc64/power5" -o "$CPUTYPE" = "ppc64/power5+" -o "$CPUTYPE" = "ppc64/970" ]; then
+ if [ "$CPUTYPE" = "ppc64/power4" -o "$CPUTYPE" = "ppc64/power5" -o "$CPUTYPE" = "ppc64/power5+" -o "$CPUTYPE" = "ppc64/970" -o "$CPUTYPE" = "ppc64/power6" ]; then
MMCR0=`echo $EVENT_STR | awk '{print $2}'`
MMCR1=`echo $EVENT_STR | awk '{print $3}'`
MMCRA=`echo $EVENT_STR | awk '{print $4}'`
diff -paurN oprof-cvs-05.05.2006/utils/ophelp.c oprof-cvs-power6-ver-2/utils/ophelp.c
--- oprof-cvs-05.05.2006/utils/ophelp.c 2006-02-22 08:36:41.000000000 -0600
+++ oprof-cvs-power6-ver-2/utils/ophelp.c 2006-06-22 10:12:09.000000000 -0500
@@ -411,6 +411,7 @@ int main(int argc, char const * argv[])
case CPU_PPC64_POWER4:
case CPU_PPC64_POWER5:
+ case CPU_PPC64_POWER6:
case CPU_PPC64_POWER5p:
case CPU_PPC64_970:
printf("Obtain PowerPC64 processor documentation at:\n"
Index: oprofile.spec
===================================================================
RCS file: /cvs/dist/rpms/oprofile/devel/oprofile.spec,v
retrieving revision 1.43
retrieving revision 1.44
diff -u -r1.43 -r1.44
--- oprofile.spec 7 Jul 2006 20:03:51 -0000 1.43
+++ oprofile.spec 10 Jul 2006 14:39:19 -0000 1.44
@@ -1,6 +1,6 @@
-%define DATE 200511111
+%define DATE 20060710
%define oprofile_version 0.9.1
-%define oprofile_release 12
+%define oprofile_release 13
Summary: System wide profiler
Name: oprofile
Version: 0.9.1
@@ -22,6 +22,7 @@
Patch83: oprofile-0.9.1-xen.patch
Patch84: oprofile-power5p.patch
Patch86: oprofile-ppc64evts.patch
+Patch87: oprofile-power6.patch
URL: http://oprofile.sf.net
ExclusiveArch: %{ix86} ia64 x86_64 ppc ppc64 s390 s390x alpha alphaev6 sparc sparc64
@@ -72,6 +73,7 @@
%patch83 -p1 -b .xen
%patch84 -p1 -b .power5p
%patch86 -p1 -b .ppc64evts
+%patch87 -p1 -b .power6
./autogen.sh
@@ -208,6 +210,9 @@
/usr/share/oprofile/ppc64/power5+/event_mappings
/usr/share/oprofile/ppc64/power5+/events
/usr/share/oprofile/ppc64/power5+/unit_masks
+/usr/share/oprofile/ppc64/power6/event_mappings
+/usr/share/oprofile/ppc64/power6/events
+/usr/share/oprofile/ppc64/power6/unit_masks
/usr/share/oprofile/ppc64/970/event_mappings
/usr/share/oprofile/ppc64/970/events
/usr/share/oprofile/ppc64/970/unit_masks
@@ -253,6 +258,9 @@
%{_bindir}/oprof_start
%changelog
+* Mon Jul 10 2006 Will Cohen <wcohen at redhat.com>
+- Add power6 support. (#196505)
+
* Fri Jul 7 2006 Will Cohen <wcohen at redhat.com>
- Support for power5+. (#197728)
- Fix PPC64 events and groups. (#197895)
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